drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34 #include <drm/drm_atomic_helper.h>
  35
  36 /**
  37  * DOC: RC6
  38  *
  39  * RC6 is a special power stage which allows the GPU to enter an very
  40  * low-voltage mode when idle, using down to 0V while at this stage.  This
  41  * stage is entered automatically when the GPU is idle when RC6 support is
  42  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  43  *
  44  * There are different RC6 modes available in Intel GPU, which differentiate
  45  * among each other with the latency required to enter and leave RC6 and
  46  * voltage consumed by the GPU in different states.
  47  *
  48  * The combination of the following flags define which states GPU is allowed
  49  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  50  * RC6pp is deepest RC6. Their support by hardware varies according to the
  51  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  52  * which brings the most power savings; deeper states save more power, but
  53  * require higher latency to switch to and wake up.
  54  */
  55 #define INTEL_RC6_ENABLE                        (1<<0)
  56 #define INTEL_RC6p_ENABLE                       (1<<1)
  57 #define INTEL_RC6pp_ENABLE                      (1<<2)
  58
  59 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
  60 {
  61         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
  62         I915_WRITE(CHICKEN_PAR1_1,
  63                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  64
  65         I915_WRITE(GEN8_CONFIG0,
  66                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  67
  68         /* WaEnableChickenDCPR:skl,bxt,kbl */
  69         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  70                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  71
  72         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
  73         /* WaFbcWakeMemOn:skl,bxt,kbl */
  74         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  75                    DISP_FBC_WM_DIS |
  76                    DISP_FBC_MEMORY_WAKE);
  77
  78         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
  79         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  80                    ILK_DPFC_DISABLE_DUMMY0);
  81 }
  82
  83 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
  84 {
  85         gen9_init_clock_gating(dev_priv);
  86
  87         /* WaDisableSDEUnitClockGating:bxt */
  88         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  89                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  90
  91         /*
  92          * FIXME:
  93          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  94          */
  95         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  96                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  97
  98         /*
  99          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 100          * to stay fully on.
 101          */
 102         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
 103                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 104                            PWM1_GATING_DIS | PWM2_GATING_DIS);
 105 }
 106
 107 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
 108 {
 109         u32 tmp;
 110
 111         tmp = I915_READ(CLKCFG);
 112
 113         switch (tmp & CLKCFG_FSB_MASK) {
 114         case CLKCFG_FSB_533:
 115                 dev_priv->fsb_freq = 533; /* 133*4 */
 116                 break;
 117         case CLKCFG_FSB_800:
 118                 dev_priv->fsb_freq = 800; /* 200*4 */
 119                 break;
 120         case CLKCFG_FSB_667:
 121                 dev_priv->fsb_freq =  667; /* 167*4 */
 122                 break;
 123         case CLKCFG_FSB_400:
 124                 dev_priv->fsb_freq = 400; /* 100*4 */
 125                 break;
 126         }
 127
 128         switch (tmp & CLKCFG_MEM_MASK) {
 129         case CLKCFG_MEM_533:
 130                 dev_priv->mem_freq = 533;
 131                 break;
 132         case CLKCFG_MEM_667:
 133                 dev_priv->mem_freq = 667;
 134                 break;
 135         case CLKCFG_MEM_800:
 136                 dev_priv->mem_freq = 800;
 137                 break;
 138         }
 139
 140         /* detect pineview DDR3 setting */
 141         tmp = I915_READ(CSHRDDR3CTL);
 142         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 143 }
 144
 145 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
 146 {
 147         u16 ddrpll, csipll;
 148
 149         ddrpll = I915_READ16(DDRMPLL1);
 150         csipll = I915_READ16(CSIPLL0);
 151
 152         switch (ddrpll & 0xff) {
 153         case 0xc:
 154                 dev_priv->mem_freq = 800;
 155                 break;
 156         case 0x10:
 157                 dev_priv->mem_freq = 1066;
 158                 break;
 159         case 0x14:
 160                 dev_priv->mem_freq = 1333;
 161                 break;
 162         case 0x18:
 163                 dev_priv->mem_freq = 1600;
 164                 break;
 165         default:
 166                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 167                                  ddrpll & 0xff);
 168                 dev_priv->mem_freq = 0;
 169                 break;
 170         }
 171
 172         dev_priv->ips.r_t = dev_priv->mem_freq;
 173
 174         switch (csipll & 0x3ff) {
 175         case 0x00c:
 176                 dev_priv->fsb_freq = 3200;
 177                 break;
 178         case 0x00e:
 179                 dev_priv->fsb_freq = 3733;
 180                 break;
 181         case 0x010:
 182                 dev_priv->fsb_freq = 4266;
 183                 break;
 184         case 0x012:
 185                 dev_priv->fsb_freq = 4800;
 186                 break;
 187         case 0x014:
 188                 dev_priv->fsb_freq = 5333;
 189                 break;
 190         case 0x016:
 191                 dev_priv->fsb_freq = 5866;
 192                 break;
 193         case 0x018:
 194                 dev_priv->fsb_freq = 6400;
 195                 break;
 196         default:
 197                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 198                                  csipll & 0x3ff);
 199                 dev_priv->fsb_freq = 0;
 200                 break;
 201         }
 202
 203         if (dev_priv->fsb_freq == 3200) {
 204                 dev_priv->ips.c_m = 0;
 205         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 206                 dev_priv->ips.c_m = 1;
 207         } else {
 208                 dev_priv->ips.c_m = 2;
 209         }
 210 }
 211
 212 static const struct cxsr_latency cxsr_latency_table[] = {
 213         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 214         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 215         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 216         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 217         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 218
 219         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 220         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 221         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 222         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 223         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 224
 225         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 226         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 227         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 228         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 229         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 230
 231         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 232         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 233         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 234         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 235         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 236
 237         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 238         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 239         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 240         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 241         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 242
 243         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 244         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 245         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 246         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 247         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 248 };
 249
 250 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 251                                                          bool is_ddr3,
 252                                                          int fsb,
 253                                                          int mem)
 254 {
 255         const struct cxsr_latency *latency;
 256         int i;
 257
 258         if (fsb == 0 || mem == 0)
 259                 return NULL;
 260
 261         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 262                 latency = &cxsr_latency_table[i];
 263                 if (is_desktop == latency->is_desktop &&
 264                     is_ddr3 == latency->is_ddr3 &&
 265                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 266                         return latency;
 267         }
 268
 269         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 270
 271         return NULL;
 272 }
 273
 274 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 275 {
 276         u32 val;
 277
 278         mutex_lock(&dev_priv->rps.hw_lock);
 279
 280         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 281         if (enable)
 282                 val &= ~FORCE_DDR_HIGH_FREQ;
 283         else
 284                 val |= FORCE_DDR_HIGH_FREQ;
 285         val &= ~FORCE_DDR_LOW_FREQ;
 286         val |= FORCE_DDR_FREQ_REQ_ACK;
 287         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 288
 289         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 290                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 291                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 292
 293         mutex_unlock(&dev_priv->rps.hw_lock);
 294 }
 295
 296 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 297 {
 298         u32 val;
 299
 300         mutex_lock(&dev_priv->rps.hw_lock);
 301
 302         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 303         if (enable)
 304                 val |= DSP_MAXFIFO_PM5_ENABLE;
 305         else
 306                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 307         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 308
 309         mutex_unlock(&dev_priv->rps.hw_lock);
 310 }
 311
 312 #define FW_WM(value, plane) \
 313         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 314
 315 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 316 {
 317         u32 val;
 318
 319         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 320                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 321                 POSTING_READ(FW_BLC_SELF_VLV);
 322                 dev_priv->wm.vlv.cxsr = enable;
 323         } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
 324                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 325                 POSTING_READ(FW_BLC_SELF);
 326         } else if (IS_PINEVIEW(dev_priv)) {
 327                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 328                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 329                 I915_WRITE(DSPFW3, val);
 330                 POSTING_READ(DSPFW3);
 331         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 332                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 333                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 334                 I915_WRITE(FW_BLC_SELF, val);
 335                 POSTING_READ(FW_BLC_SELF);
 336         } else if (IS_I915GM(dev_priv)) {
 337                 /*
 338                  * FIXME can't find a bit like this for 915G, and
 339                  * and yet it does have the related watermark in
 340                  * FW_BLC_SELF. What's going on?
 341                  */
 342                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 343                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 344                 I915_WRITE(INSTPM, val);
 345                 POSTING_READ(INSTPM);
 346         } else {
 347                 return;
 348         }
 349
 350         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 351                       enable ? "enabled" : "disabled");
 352 }
 353
 354
 355 /*
 356  * Latency for FIFO fetches is dependent on several factors:
 357  *   - memory configuration (speed, channels)
 358  *   - chipset
 359  *   - current MCH state
 360  * It can be fairly high in some situations, so here we assume a fairly
 361  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 362  * set this value too high, the FIFO will fetch frequently to stay full)
 363  * and power consumption (set it too low to save power and we might see
 364  * FIFO underruns and display "flicker").
 365  *
 366  * A value of 5us seems to be a good balance; safe for very low end
 367  * platforms but not overly aggressive on lower latency configs.
 368  */
 369 static const int pessimal_latency_ns = 5000;
 370
 371 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 372         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 373
 374 static int vlv_get_fifo_size(struct drm_i915_private *dev_priv,
 375                               enum pipe pipe, int plane)
 376 {
 377         int sprite0_start, sprite1_start, size;
 378
 379         switch (pipe) {
 380                 uint32_t dsparb, dsparb2, dsparb3;
 381         case PIPE_A:
 382                 dsparb = I915_READ(DSPARB);
 383                 dsparb2 = I915_READ(DSPARB2);
 384                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 385                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 386                 break;
 387         case PIPE_B:
 388                 dsparb = I915_READ(DSPARB);
 389                 dsparb2 = I915_READ(DSPARB2);
 390                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 391                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 392                 break;
 393         case PIPE_C:
 394                 dsparb2 = I915_READ(DSPARB2);
 395                 dsparb3 = I915_READ(DSPARB3);
 396                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 397                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 398                 break;
 399         default:
 400                 return 0;
 401         }
 402
 403         switch (plane) {
 404         case 0:
 405                 size = sprite0_start;
 406                 break;
 407         case 1:
 408                 size = sprite1_start - sprite0_start;
 409                 break;
 410         case 2:
 411                 size = 512 - 1 - sprite1_start;
 412                 break;
 413         default:
 414                 return 0;
 415         }
 416
 417         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 418                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 419                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 420                       size);
 421
 422         return size;
 423 }
 424
 425 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 426 {
 427         uint32_t dsparb = I915_READ(DSPARB);
 428         int size;
 429
 430         size = dsparb & 0x7f;
 431         if (plane)
 432                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 433
 434         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 435                       plane ? "B" : "A", size);
 436
 437         return size;
 438 }
 439
 440 static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 441 {
 442         uint32_t dsparb = I915_READ(DSPARB);
 443         int size;
 444
 445         size = dsparb & 0x1ff;
 446         if (plane)
 447                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 448         size >>= 1; /* Convert to cachelines */
 449
 450         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 451                       plane ? "B" : "A", size);
 452
 453         return size;
 454 }
 455
 456 static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 457 {
 458         uint32_t dsparb = I915_READ(DSPARB);
 459         int size;
 460
 461         size = dsparb & 0x7f;
 462         size >>= 2; /* Convert to cachelines */
 463
 464         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 465                       plane ? "B" : "A",
 466                       size);
 467
 468         return size;
 469 }
 470
 471 /* Pineview has different values for various configs */
 472 static const struct intel_watermark_params pineview_display_wm = {
 473         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 474         .max_wm = PINEVIEW_MAX_WM,
 475         .default_wm = PINEVIEW_DFT_WM,
 476         .guard_size = PINEVIEW_GUARD_WM,
 477         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 478 };
 479 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 480         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 481         .max_wm = PINEVIEW_MAX_WM,
 482         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 483         .guard_size = PINEVIEW_GUARD_WM,
 484         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 485 };
 486 static const struct intel_watermark_params pineview_cursor_wm = {
 487         .fifo_size = PINEVIEW_CURSOR_FIFO,
 488         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 489         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 490         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 491         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 492 };
 493 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 494         .fifo_size = PINEVIEW_CURSOR_FIFO,
 495         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 496         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 497         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 498         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 499 };
 500 static const struct intel_watermark_params g4x_wm_info = {
 501         .fifo_size = G4X_FIFO_SIZE,
 502         .max_wm = G4X_MAX_WM,
 503         .default_wm = G4X_MAX_WM,
 504         .guard_size = 2,
 505         .cacheline_size = G4X_FIFO_LINE_SIZE,
 506 };
 507 static const struct intel_watermark_params g4x_cursor_wm_info = {
 508         .fifo_size = I965_CURSOR_FIFO,
 509         .max_wm = I965_CURSOR_MAX_WM,
 510         .default_wm = I965_CURSOR_DFT_WM,
 511         .guard_size = 2,
 512         .cacheline_size = G4X_FIFO_LINE_SIZE,
 513 };
 514 static const struct intel_watermark_params i965_cursor_wm_info = {
 515         .fifo_size = I965_CURSOR_FIFO,
 516         .max_wm = I965_CURSOR_MAX_WM,
 517         .default_wm = I965_CURSOR_DFT_WM,
 518         .guard_size = 2,
 519         .cacheline_size = I915_FIFO_LINE_SIZE,
 520 };
 521 static const struct intel_watermark_params i945_wm_info = {
 522         .fifo_size = I945_FIFO_SIZE,
 523         .max_wm = I915_MAX_WM,
 524         .default_wm = 1,
 525         .guard_size = 2,
 526         .cacheline_size = I915_FIFO_LINE_SIZE,
 527 };
 528 static const struct intel_watermark_params i915_wm_info = {
 529         .fifo_size = I915_FIFO_SIZE,
 530         .max_wm = I915_MAX_WM,
 531         .default_wm = 1,
 532         .guard_size = 2,
 533         .cacheline_size = I915_FIFO_LINE_SIZE,
 534 };
 535 static const struct intel_watermark_params i830_a_wm_info = {
 536         .fifo_size = I855GM_FIFO_SIZE,
 537         .max_wm = I915_MAX_WM,
 538         .default_wm = 1,
 539         .guard_size = 2,
 540         .cacheline_size = I830_FIFO_LINE_SIZE,
 541 };
 542 static const struct intel_watermark_params i830_bc_wm_info = {
 543         .fifo_size = I855GM_FIFO_SIZE,
 544         .max_wm = I915_MAX_WM/2,
 545         .default_wm = 1,
 546         .guard_size = 2,
 547         .cacheline_size = I830_FIFO_LINE_SIZE,
 548 };
 549 static const struct intel_watermark_params i845_wm_info = {
 550         .fifo_size = I830_FIFO_SIZE,
 551         .max_wm = I915_MAX_WM,
 552         .default_wm = 1,
 553         .guard_size = 2,
 554         .cacheline_size = I830_FIFO_LINE_SIZE,
 555 };
 556
 557 /**
 558  * intel_calculate_wm - calculate watermark level
 559  * @clock_in_khz: pixel clock
 560  * @wm: chip FIFO params
 561  * @cpp: bytes per pixel
 562  * @latency_ns: memory latency for the platform
 563  *
 564  * Calculate the watermark level (the level at which the display plane will
 565  * start fetching from memory again).  Each chip has a different display
 566  * FIFO size and allocation, so the caller needs to figure that out and pass
 567  * in the correct intel_watermark_params structure.
 568  *
 569  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 570  * on the pixel size.  When it reaches the watermark level, it'll start
 571  * fetching FIFO line sized based chunks from memory until the FIFO fills
 572  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 573  * will occur, and a display engine hang could result.
 574  */
 575 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 576                                         const struct intel_watermark_params *wm,
 577                                         int fifo_size, int cpp,
 578                                         unsigned long latency_ns)
 579 {
 580         long entries_required, wm_size;
 581
 582         /*
 583          * Note: we need to make sure we don't overflow for various clock &
 584          * latency values.
 585          * clocks go from a few thousand to several hundred thousand.
 586          * latency is usually a few thousand
 587          */
 588         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 589                 1000;
 590         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 591
 592         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 593
 594         wm_size = fifo_size - (entries_required + wm->guard_size);
 595
 596         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 597
 598         /* Don't promote wm_size to unsigned... */
 599         if (wm_size > (long)wm->max_wm)
 600                 wm_size = wm->max_wm;
 601         if (wm_size <= 0)
 602                 wm_size = wm->default_wm;
 603
 604         /*
 605          * Bspec seems to indicate that the value shouldn't be lower than
 606          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 607          * Lets go for 8 which is the burst size since certain platforms
 608          * already use a hardcoded 8 (which is what the spec says should be
 609          * done).
 610          */
 611         if (wm_size <= 8)
 612                 wm_size = 8;
 613
 614         return wm_size;
 615 }
 616
 617 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 618 {
 619         struct intel_crtc *crtc, *enabled = NULL;
 620
 621         for_each_intel_crtc(&dev_priv->drm, crtc) {
 622                 if (intel_crtc_active(crtc)) {
 623                         if (enabled)
 624                                 return NULL;
 625                         enabled = crtc;
 626                 }
 627         }
 628
 629         return enabled;
 630 }
 631
 632 static void pineview_update_wm(struct intel_crtc *unused_crtc)
 633 {
 634         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 635         struct intel_crtc *crtc;
 636         const struct cxsr_latency *latency;
 637         u32 reg;
 638         unsigned long wm;
 639
 640         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 641                                          dev_priv->is_ddr3,
 642                                          dev_priv->fsb_freq,
 643                                          dev_priv->mem_freq);
 644         if (!latency) {
 645                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 646                 intel_set_memory_cxsr(dev_priv, false);
 647                 return;
 648         }
 649
 650         crtc = single_enabled_crtc(dev_priv);
 651         if (crtc) {
 652                 const struct drm_display_mode *adjusted_mode =
 653                         &crtc->config->base.adjusted_mode;
 654                 const struct drm_framebuffer *fb =
 655                         crtc->base.primary->state->fb;
 656                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 657                 int clock = adjusted_mode->crtc_clock;
 658
 659                 /* Display SR */
 660                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 661                                         pineview_display_wm.fifo_size,
 662                                         cpp, latency->display_sr);
 663                 reg = I915_READ(DSPFW1);
 664                 reg &= ~DSPFW_SR_MASK;
 665                 reg |= FW_WM(wm, SR);
 666                 I915_WRITE(DSPFW1, reg);
 667                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 668
 669                 /* cursor SR */
 670                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 671                                         pineview_display_wm.fifo_size,
 672                                         cpp, latency->cursor_sr);
 673                 reg = I915_READ(DSPFW3);
 674                 reg &= ~DSPFW_CURSOR_SR_MASK;
 675                 reg |= FW_WM(wm, CURSOR_SR);
 676                 I915_WRITE(DSPFW3, reg);
 677
 678                 /* Display HPLL off SR */
 679                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 680                                         pineview_display_hplloff_wm.fifo_size,
 681                                         cpp, latency->display_hpll_disable);
 682                 reg = I915_READ(DSPFW3);
 683                 reg &= ~DSPFW_HPLL_SR_MASK;
 684                 reg |= FW_WM(wm, HPLL_SR);
 685                 I915_WRITE(DSPFW3, reg);
 686
 687                 /* cursor HPLL off SR */
 688                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 689                                         pineview_display_hplloff_wm.fifo_size,
 690                                         cpp, latency->cursor_hpll_disable);
 691                 reg = I915_READ(DSPFW3);
 692                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 693                 reg |= FW_WM(wm, HPLL_CURSOR);
 694                 I915_WRITE(DSPFW3, reg);
 695                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 696
 697                 intel_set_memory_cxsr(dev_priv, true);
 698         } else {
 699                 intel_set_memory_cxsr(dev_priv, false);
 700         }
 701 }
 702
 703 static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
 704                             int plane,
 705                             const struct intel_watermark_params *display,
 706                             int display_latency_ns,
 707                             const struct intel_watermark_params *cursor,
 708                             int cursor_latency_ns,
 709                             int *plane_wm,
 710                             int *cursor_wm)
 711 {
 712         struct intel_crtc *crtc;
 713         const struct drm_display_mode *adjusted_mode;
 714         const struct drm_framebuffer *fb;
 715         int htotal, hdisplay, clock, cpp;
 716         int line_time_us, line_count;
 717         int entries, tlb_miss;
 718
 719         crtc = intel_get_crtc_for_plane(dev_priv, plane);
 720         if (!intel_crtc_active(crtc)) {
 721                 *cursor_wm = cursor->guard_size;
 722                 *plane_wm = display->guard_size;
 723                 return false;
 724         }
 725
 726         adjusted_mode = &crtc->config->base.adjusted_mode;
 727         fb = crtc->base.primary->state->fb;
 728         clock = adjusted_mode->crtc_clock;
 729         htotal = adjusted_mode->crtc_htotal;
 730         hdisplay = crtc->config->pipe_src_w;
 731         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 732
 733         /* Use the small buffer method to calculate plane watermark */
 734         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 735         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 736         if (tlb_miss > 0)
 737                 entries += tlb_miss;
 738         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 739         *plane_wm = entries + display->guard_size;
 740         if (*plane_wm > (int)display->max_wm)
 741                 *plane_wm = display->max_wm;
 742
 743         /* Use the large buffer method to calculate cursor watermark */
 744         line_time_us = max(htotal * 1000 / clock, 1);
 745         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 746         entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
 747         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 748         if (tlb_miss > 0)
 749                 entries += tlb_miss;
 750         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 751         *cursor_wm = entries + cursor->guard_size;
 752         if (*cursor_wm > (int)cursor->max_wm)
 753                 *cursor_wm = (int)cursor->max_wm;
 754
 755         return true;
 756 }
 757
 758 /*
 759  * Check the wm result.
 760  *
 761  * If any calculated watermark values is larger than the maximum value that
 762  * can be programmed into the associated watermark register, that watermark
 763  * must be disabled.
 764  */
 765 static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
 766                            int display_wm, int cursor_wm,
 767                            const struct intel_watermark_params *display,
 768                            const struct intel_watermark_params *cursor)
 769 {
 770         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 771                       display_wm, cursor_wm);
 772
 773         if (display_wm > display->max_wm) {
 774                 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
 775                               display_wm, display->max_wm);
 776                 return false;
 777         }
 778
 779         if (cursor_wm > cursor->max_wm) {
 780                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
 781                               cursor_wm, cursor->max_wm);
 782                 return false;
 783         }
 784
 785         if (!(display_wm || cursor_wm)) {
 786                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 787                 return false;
 788         }
 789
 790         return true;
 791 }
 792
 793 static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
 794                              int plane,
 795                              int latency_ns,
 796                              const struct intel_watermark_params *display,
 797                              const struct intel_watermark_params *cursor,
 798                              int *display_wm, int *cursor_wm)
 799 {
 800         struct intel_crtc *crtc;
 801         const struct drm_display_mode *adjusted_mode;
 802         const struct drm_framebuffer *fb;
 803         int hdisplay, htotal, cpp, clock;
 804         unsigned long line_time_us;
 805         int line_count, line_size;
 806         int small, large;
 807         int entries;
 808
 809         if (!latency_ns) {
 810                 *display_wm = *cursor_wm = 0;
 811                 return false;
 812         }
 813
 814         crtc = intel_get_crtc_for_plane(dev_priv, plane);
 815         adjusted_mode = &crtc->config->base.adjusted_mode;
 816         fb = crtc->base.primary->state->fb;
 817         clock = adjusted_mode->crtc_clock;
 818         htotal = adjusted_mode->crtc_htotal;
 819         hdisplay = crtc->config->pipe_src_w;
 820         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 821
 822         line_time_us = max(htotal * 1000 / clock, 1);
 823         line_count = (latency_ns / line_time_us + 1000) / 1000;
 824         line_size = hdisplay * cpp;
 825
 826         /* Use the minimum of the small and large buffer method for primary */
 827         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 828         large = line_count * line_size;
 829
 830         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 831         *display_wm = entries + display->guard_size;
 832
 833         /* calculate the self-refresh watermark for display cursor */
 834         entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
 835         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 836         *cursor_wm = entries + cursor->guard_size;
 837
 838         return g4x_check_srwm(dev_priv,
 839                               *display_wm, *cursor_wm,
 840                               display, cursor);
 841 }
 842
 843 #define FW_WM_VLV(value, plane) \
 844         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 845
 846 static void vlv_write_wm_values(struct intel_crtc *crtc,
 847                                 const struct vlv_wm_values *wm)
 848 {
 849         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 850         enum pipe pipe = crtc->pipe;
 851
 852         I915_WRITE(VLV_DDL(pipe),
 853                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 854                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 855                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 856                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 857
 858         I915_WRITE(DSPFW1,
 859                    FW_WM(wm->sr.plane, SR) |
 860                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 861                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 862                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 863         I915_WRITE(DSPFW2,
 864                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 865                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 866                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 867         I915_WRITE(DSPFW3,
 868                    FW_WM(wm->sr.cursor, CURSOR_SR));
 869
 870         if (IS_CHERRYVIEW(dev_priv)) {
 871                 I915_WRITE(DSPFW7_CHV,
 872                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 873                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 874                 I915_WRITE(DSPFW8_CHV,
 875                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 876                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 877                 I915_WRITE(DSPFW9_CHV,
 878                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 879                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 880                 I915_WRITE(DSPHOWM,
 881                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 882                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 883                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 884                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 885                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 886                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 887                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 888                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 889                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 890                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 891         } else {
 892                 I915_WRITE(DSPFW7,
 893                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 894                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 895                 I915_WRITE(DSPHOWM,
 896                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 897                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 898                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 899                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 900                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 901                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 902                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 903         }
 904
 905         /* zero (unused) WM1 watermarks */
 906         I915_WRITE(DSPFW4, 0);
 907         I915_WRITE(DSPFW5, 0);
 908         I915_WRITE(DSPFW6, 0);
 909         I915_WRITE(DSPHOWM1, 0);
 910
 911         POSTING_READ(DSPFW1);
 912 }
 913
 914 #undef FW_WM_VLV
 915
 916 enum vlv_wm_level {
 917         VLV_WM_LEVEL_PM2,
 918         VLV_WM_LEVEL_PM5,
 919         VLV_WM_LEVEL_DDR_DVFS,
 920 };
 921
 922 /* latency must be in 0.1us units. */
 923 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 924                                    unsigned int pipe_htotal,
 925                                    unsigned int horiz_pixels,
 926                                    unsigned int cpp,
 927                                    unsigned int latency)
 928 {
 929         unsigned int ret;
 930
 931         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 932         ret = (ret + 1) * horiz_pixels * cpp;
 933         ret = DIV_ROUND_UP(ret, 64);
 934
 935         return ret;
 936 }
 937
 938 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
 939 {
 940         /* all latencies in usec */
 941         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 942
 943         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 944
 945         if (IS_CHERRYVIEW(dev_priv)) {
 946                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 947                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 948
 949                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 950         }
 951 }
 952
 953 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 954                                      struct intel_crtc *crtc,
 955                                      const struct intel_plane_state *state,
 956                                      int level)
 957 {
 958         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 959         int clock, htotal, cpp, width, wm;
 960
 961         if (dev_priv->wm.pri_latency[level] == 0)
 962                 return USHRT_MAX;
 963
 964         if (!state->base.visible)
 965                 return 0;
 966
 967         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 968         clock = crtc->config->base.adjusted_mode.crtc_clock;
 969         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 970         width = crtc->config->pipe_src_w;
 971         if (WARN_ON(htotal == 0))
 972                 htotal = 1;
 973
 974         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 975                 /*
 976                  * FIXME the formula gives values that are
 977                  * too big for the cursor FIFO, and hence we
 978                  * would never be able to use cursors. For
 979                  * now just hardcode the watermark.
 980                  */
 981                 wm = 63;
 982         } else {
 983                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 984                                     dev_priv->wm.pri_latency[level] * 10);
 985         }
 986
 987         return min_t(int, wm, USHRT_MAX);
 988 }
 989
 990 static void vlv_compute_fifo(struct intel_crtc *crtc)
 991 {
 992         struct drm_device *dev = crtc->base.dev;
 993         struct vlv_wm_state *wm_state = &crtc->wm_state;
 994         struct intel_plane *plane;
 995         unsigned int total_rate = 0;
 996         const int fifo_size = 512 - 1;
 997         int fifo_extra, fifo_left = fifo_size;
 998
 999         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1000                 struct intel_plane_state *state =
1001                         to_intel_plane_state(plane->base.state);
1002
1003                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1004                         continue;
1005
1006                 if (state->base.visible) {
1007                         wm_state->num_active_planes++;
1008                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1009                 }
1010         }
1011
1012         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1013                 struct intel_plane_state *state =
1014                         to_intel_plane_state(plane->base.state);
1015                 unsigned int rate;
1016
1017                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1018                         plane->wm.fifo_size = 63;
1019                         continue;
1020                 }
1021
1022                 if (!state->base.visible) {
1023                         plane->wm.fifo_size = 0;
1024                         continue;
1025                 }
1026
1027                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1028                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1029                 fifo_left -= plane->wm.fifo_size;
1030         }
1031
1032         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1033
1034         /* spread the remainder evenly */
1035         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1036                 int plane_extra;
1037
1038                 if (fifo_left == 0)
1039                         break;
1040
1041                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1042                         continue;
1043
1044                 /* give it all to the first plane if none are active */
1045                 if (plane->wm.fifo_size == 0 &&
1046                     wm_state->num_active_planes)
1047                         continue;
1048
1049                 plane_extra = min(fifo_extra, fifo_left);
1050                 plane->wm.fifo_size += plane_extra;
1051                 fifo_left -= plane_extra;
1052         }
1053
1054         WARN_ON(fifo_left != 0);
1055 }
1056
1057 static void vlv_invert_wms(struct intel_crtc *crtc)
1058 {
1059         struct vlv_wm_state *wm_state = &crtc->wm_state;
1060         int level;
1061
1062         for (level = 0; level < wm_state->num_levels; level++) {
1063                 struct drm_device *dev = crtc->base.dev;
1064                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1065                 struct intel_plane *plane;
1066
1067                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1068                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1069
1070                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1071                         switch (plane->base.type) {
1072                                 int sprite;
1073                         case DRM_PLANE_TYPE_CURSOR:
1074                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1075                                         wm_state->wm[level].cursor;
1076                                 break;
1077                         case DRM_PLANE_TYPE_PRIMARY:
1078                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1079                                         wm_state->wm[level].primary;
1080                                 break;
1081                         case DRM_PLANE_TYPE_OVERLAY:
1082                                 sprite = plane->plane;
1083                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1084                                         wm_state->wm[level].sprite[sprite];
1085                                 break;
1086                         }
1087                 }
1088         }
1089 }
1090
1091 static void vlv_compute_wm(struct intel_crtc *crtc)
1092 {
1093         struct drm_device *dev = crtc->base.dev;
1094         struct vlv_wm_state *wm_state = &crtc->wm_state;
1095         struct intel_plane *plane;
1096         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1097         int level;
1098
1099         memset(wm_state, 0, sizeof(*wm_state));
1100
1101         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1102         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1103
1104         wm_state->num_active_planes = 0;
1105
1106         vlv_compute_fifo(crtc);
1107
1108         if (wm_state->num_active_planes != 1)
1109                 wm_state->cxsr = false;
1110
1111         if (wm_state->cxsr) {
1112                 for (level = 0; level < wm_state->num_levels; level++) {
1113                         wm_state->sr[level].plane = sr_fifo_size;
1114                         wm_state->sr[level].cursor = 63;
1115                 }
1116         }
1117
1118         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1119                 struct intel_plane_state *state =
1120                         to_intel_plane_state(plane->base.state);
1121
1122                 if (!state->base.visible)
1123                         continue;
1124
1125                 /* normal watermarks */
1126                 for (level = 0; level < wm_state->num_levels; level++) {
1127                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1128                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1129
1130                         /* hack */
1131                         if (WARN_ON(level == 0 && wm > max_wm))
1132                                 wm = max_wm;
1133
1134                         if (wm > plane->wm.fifo_size)
1135                                 break;
1136
1137                         switch (plane->base.type) {
1138                                 int sprite;
1139                         case DRM_PLANE_TYPE_CURSOR:
1140                                 wm_state->wm[level].cursor = wm;
1141                                 break;
1142                         case DRM_PLANE_TYPE_PRIMARY:
1143                                 wm_state->wm[level].primary = wm;
1144                                 break;
1145                         case DRM_PLANE_TYPE_OVERLAY:
1146                                 sprite = plane->plane;
1147                                 wm_state->wm[level].sprite[sprite] = wm;
1148                                 break;
1149                         }
1150                 }
1151
1152                 wm_state->num_levels = level;
1153
1154                 if (!wm_state->cxsr)
1155                         continue;
1156
1157                 /* maxfifo watermarks */
1158                 switch (plane->base.type) {
1159                         int sprite, level;
1160                 case DRM_PLANE_TYPE_CURSOR:
1161                         for (level = 0; level < wm_state->num_levels; level++)
1162                                 wm_state->sr[level].cursor =
1163                                         wm_state->wm[level].cursor;
1164                         break;
1165                 case DRM_PLANE_TYPE_PRIMARY:
1166                         for (level = 0; level < wm_state->num_levels; level++)
1167                                 wm_state->sr[level].plane =
1168                                         min(wm_state->sr[level].plane,
1169                                             wm_state->wm[level].primary);
1170                         break;
1171                 case DRM_PLANE_TYPE_OVERLAY:
1172                         sprite = plane->plane;
1173                         for (level = 0; level < wm_state->num_levels; level++)
1174                                 wm_state->sr[level].plane =
1175                                         min(wm_state->sr[level].plane,
1176                                             wm_state->wm[level].sprite[sprite]);
1177                         break;
1178                 }
1179         }
1180
1181         /* clear any (partially) filled invalid levels */
1182         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1183                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1184                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1185         }
1186
1187         vlv_invert_wms(crtc);
1188 }
1189
1190 #define VLV_FIFO(plane, value) \
1191         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1192
1193 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1194 {
1195         struct drm_device *dev = crtc->base.dev;
1196         struct drm_i915_private *dev_priv = to_i915(dev);
1197         struct intel_plane *plane;
1198         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1199
1200         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1201                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1202                         WARN_ON(plane->wm.fifo_size != 63);
1203                         continue;
1204                 }
1205
1206                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1207                         sprite0_start = plane->wm.fifo_size;
1208                 else if (plane->plane == 0)
1209                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1210                 else
1211                         fifo_size = sprite1_start + plane->wm.fifo_size;
1212         }
1213
1214         WARN_ON(fifo_size != 512 - 1);
1215
1216         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1217                       pipe_name(crtc->pipe), sprite0_start,
1218                       sprite1_start, fifo_size);
1219
1220         switch (crtc->pipe) {
1221                 uint32_t dsparb, dsparb2, dsparb3;
1222         case PIPE_A:
1223                 dsparb = I915_READ(DSPARB);
1224                 dsparb2 = I915_READ(DSPARB2);
1225
1226                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1227                             VLV_FIFO(SPRITEB, 0xff));
1228                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1229                            VLV_FIFO(SPRITEB, sprite1_start));
1230
1231                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1232                              VLV_FIFO(SPRITEB_HI, 0x1));
1233                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1234                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1235
1236                 I915_WRITE(DSPARB, dsparb);
1237                 I915_WRITE(DSPARB2, dsparb2);
1238                 break;
1239         case PIPE_B:
1240                 dsparb = I915_READ(DSPARB);
1241                 dsparb2 = I915_READ(DSPARB2);
1242
1243                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1244                             VLV_FIFO(SPRITED, 0xff));
1245                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1246                            VLV_FIFO(SPRITED, sprite1_start));
1247
1248                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1249                              VLV_FIFO(SPRITED_HI, 0xff));
1250                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1251                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1252
1253                 I915_WRITE(DSPARB, dsparb);
1254                 I915_WRITE(DSPARB2, dsparb2);
1255                 break;
1256         case PIPE_C:
1257                 dsparb3 = I915_READ(DSPARB3);
1258                 dsparb2 = I915_READ(DSPARB2);
1259
1260                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1261                              VLV_FIFO(SPRITEF, 0xff));
1262                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1263                             VLV_FIFO(SPRITEF, sprite1_start));
1264
1265                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1266                              VLV_FIFO(SPRITEF_HI, 0xff));
1267                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1268                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1269
1270                 I915_WRITE(DSPARB3, dsparb3);
1271                 I915_WRITE(DSPARB2, dsparb2);
1272                 break;
1273         default:
1274                 break;
1275         }
1276 }
1277
1278 #undef VLV_FIFO
1279
1280 static void vlv_merge_wm(struct drm_device *dev,
1281                          struct vlv_wm_values *wm)
1282 {
1283         struct intel_crtc *crtc;
1284         int num_active_crtcs = 0;
1285
1286         wm->level = to_i915(dev)->wm.max_level;
1287         wm->cxsr = true;
1288
1289         for_each_intel_crtc(dev, crtc) {
1290                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1291
1292                 if (!crtc->active)
1293                         continue;
1294
1295                 if (!wm_state->cxsr)
1296                         wm->cxsr = false;
1297
1298                 num_active_crtcs++;
1299                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1300         }
1301
1302         if (num_active_crtcs != 1)
1303                 wm->cxsr = false;
1304
1305         if (num_active_crtcs > 1)
1306                 wm->level = VLV_WM_LEVEL_PM2;
1307
1308         for_each_intel_crtc(dev, crtc) {
1309                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1310                 enum pipe pipe = crtc->pipe;
1311
1312                 if (!crtc->active)
1313                         continue;
1314
1315                 wm->pipe[pipe] = wm_state->wm[wm->level];
1316                 if (wm->cxsr)
1317                         wm->sr = wm_state->sr[wm->level];
1318
1319                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1320                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1321                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1322                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1323         }
1324 }
1325
1326 static void vlv_update_wm(struct intel_crtc *crtc)
1327 {
1328         struct drm_device *dev = crtc->base.dev;
1329         struct drm_i915_private *dev_priv = to_i915(dev);
1330         enum pipe pipe = crtc->pipe;
1331         struct vlv_wm_values wm = {};
1332
1333         vlv_compute_wm(crtc);
1334         vlv_merge_wm(dev, &wm);
1335
1336         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1337                 /* FIXME should be part of crtc atomic commit */
1338                 vlv_pipe_set_fifo_size(crtc);
1339                 return;
1340         }
1341
1342         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1343             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1344                 chv_set_memory_dvfs(dev_priv, false);
1345
1346         if (wm.level < VLV_WM_LEVEL_PM5 &&
1347             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1348                 chv_set_memory_pm5(dev_priv, false);
1349
1350         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1351                 intel_set_memory_cxsr(dev_priv, false);
1352
1353         /* FIXME should be part of crtc atomic commit */
1354         vlv_pipe_set_fifo_size(crtc);
1355
1356         vlv_write_wm_values(crtc, &wm);
1357
1358         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1359                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1360                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1361                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1362                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1363
1364         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1365                 intel_set_memory_cxsr(dev_priv, true);
1366
1367         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1368             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1369                 chv_set_memory_pm5(dev_priv, true);
1370
1371         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1372             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1373                 chv_set_memory_dvfs(dev_priv, true);
1374
1375         dev_priv->wm.vlv = wm;
1376 }
1377
1378 #define single_plane_enabled(mask) is_power_of_2(mask)
1379
1380 static void g4x_update_wm(struct intel_crtc *crtc)
1381 {
1382         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1383         static const int sr_latency_ns = 12000;
1384         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1385         int plane_sr, cursor_sr;
1386         unsigned int enabled = 0;
1387         bool cxsr_enabled;
1388
1389         if (g4x_compute_wm0(dev_priv, PIPE_A,
1390                             &g4x_wm_info, pessimal_latency_ns,
1391                             &g4x_cursor_wm_info, pessimal_latency_ns,
1392                             &planea_wm, &cursora_wm))
1393                 enabled |= 1 << PIPE_A;
1394
1395         if (g4x_compute_wm0(dev_priv, PIPE_B,
1396                             &g4x_wm_info, pessimal_latency_ns,
1397                             &g4x_cursor_wm_info, pessimal_latency_ns,
1398                             &planeb_wm, &cursorb_wm))
1399                 enabled |= 1 << PIPE_B;
1400
1401         if (single_plane_enabled(enabled) &&
1402             g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
1403                              sr_latency_ns,
1404                              &g4x_wm_info,
1405                              &g4x_cursor_wm_info,
1406                              &plane_sr, &cursor_sr)) {
1407                 cxsr_enabled = true;
1408         } else {
1409                 cxsr_enabled = false;
1410                 intel_set_memory_cxsr(dev_priv, false);
1411                 plane_sr = cursor_sr = 0;
1412         }
1413
1414         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1415                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1416                       planea_wm, cursora_wm,
1417                       planeb_wm, cursorb_wm,
1418                       plane_sr, cursor_sr);
1419
1420         I915_WRITE(DSPFW1,
1421                    FW_WM(plane_sr, SR) |
1422                    FW_WM(cursorb_wm, CURSORB) |
1423                    FW_WM(planeb_wm, PLANEB) |
1424                    FW_WM(planea_wm, PLANEA));
1425         I915_WRITE(DSPFW2,
1426                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1427                    FW_WM(cursora_wm, CURSORA));
1428         /* HPLL off in SR has some issues on G4x... disable it */
1429         I915_WRITE(DSPFW3,
1430                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1431                    FW_WM(cursor_sr, CURSOR_SR));
1432
1433         if (cxsr_enabled)
1434                 intel_set_memory_cxsr(dev_priv, true);
1435 }
1436
1437 static void i965_update_wm(struct intel_crtc *unused_crtc)
1438 {
1439         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1440         struct intel_crtc *crtc;
1441         int srwm = 1;
1442         int cursor_sr = 16;
1443         bool cxsr_enabled;
1444
1445         /* Calc sr entries for one plane configs */
1446         crtc = single_enabled_crtc(dev_priv);
1447         if (crtc) {
1448                 /* self-refresh has much higher latency */
1449                 static const int sr_latency_ns = 12000;
1450                 const struct drm_display_mode *adjusted_mode =
1451                         &crtc->config->base.adjusted_mode;
1452                 const struct drm_framebuffer *fb =
1453                         crtc->base.primary->state->fb;
1454                 int clock = adjusted_mode->crtc_clock;
1455                 int htotal = adjusted_mode->crtc_htotal;
1456                 int hdisplay = crtc->config->pipe_src_w;
1457                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1458                 unsigned long line_time_us;
1459                 int entries;
1460
1461                 line_time_us = max(htotal * 1000 / clock, 1);
1462
1463                 /* Use ns/us then divide to preserve precision */
1464                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1465                         cpp * hdisplay;
1466                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1467                 srwm = I965_FIFO_SIZE - entries;
1468                 if (srwm < 0)
1469                         srwm = 1;
1470                 srwm &= 0x1ff;
1471                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1472                               entries, srwm);
1473
1474                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1475                         cpp * crtc->base.cursor->state->crtc_w;
1476                 entries = DIV_ROUND_UP(entries,
1477                                           i965_cursor_wm_info.cacheline_size);
1478                 cursor_sr = i965_cursor_wm_info.fifo_size -
1479                         (entries + i965_cursor_wm_info.guard_size);
1480
1481                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1482                         cursor_sr = i965_cursor_wm_info.max_wm;
1483
1484                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1485                               "cursor %d\n", srwm, cursor_sr);
1486
1487                 cxsr_enabled = true;
1488         } else {
1489                 cxsr_enabled = false;
1490                 /* Turn off self refresh if both pipes are enabled */
1491                 intel_set_memory_cxsr(dev_priv, false);
1492         }
1493
1494         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1495                       srwm);
1496
1497         /* 965 has limitations... */
1498         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1499                    FW_WM(8, CURSORB) |
1500                    FW_WM(8, PLANEB) |
1501                    FW_WM(8, PLANEA));
1502         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1503                    FW_WM(8, PLANEC_OLD));
1504         /* update cursor SR watermark */
1505         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1506
1507         if (cxsr_enabled)
1508                 intel_set_memory_cxsr(dev_priv, true);
1509 }
1510
1511 #undef FW_WM
1512
1513 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
1514 {
1515         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1516         const struct intel_watermark_params *wm_info;
1517         uint32_t fwater_lo;
1518         uint32_t fwater_hi;
1519         int cwm, srwm = 1;
1520         int fifo_size;
1521         int planea_wm, planeb_wm;
1522         struct intel_crtc *crtc, *enabled = NULL;
1523
1524         if (IS_I945GM(dev_priv))
1525                 wm_info = &i945_wm_info;
1526         else if (!IS_GEN2(dev_priv))
1527                 wm_info = &i915_wm_info;
1528         else
1529                 wm_info = &i830_a_wm_info;
1530
1531         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
1532         crtc = intel_get_crtc_for_plane(dev_priv, 0);
1533         if (intel_crtc_active(crtc)) {
1534                 const struct drm_display_mode *adjusted_mode =
1535                         &crtc->config->base.adjusted_mode;
1536                 const struct drm_framebuffer *fb =
1537                         crtc->base.primary->state->fb;
1538                 int cpp;
1539
1540                 if (IS_GEN2(dev_priv))
1541                         cpp = 4;
1542                 else
1543                         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1544
1545                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1546                                                wm_info, fifo_size, cpp,
1547                                                pessimal_latency_ns);
1548                 enabled = crtc;
1549         } else {
1550                 planea_wm = fifo_size - wm_info->guard_size;
1551                 if (planea_wm > (long)wm_info->max_wm)
1552                         planea_wm = wm_info->max_wm;
1553         }
1554
1555         if (IS_GEN2(dev_priv))
1556                 wm_info = &i830_bc_wm_info;
1557
1558         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
1559         crtc = intel_get_crtc_for_plane(dev_priv, 1);
1560         if (intel_crtc_active(crtc)) {
1561                 const struct drm_display_mode *adjusted_mode =
1562                         &crtc->config->base.adjusted_mode;
1563                 const struct drm_framebuffer *fb =
1564                         crtc->base.primary->state->fb;
1565                 int cpp;
1566
1567                 if (IS_GEN2(dev_priv))
1568                         cpp = 4;
1569                 else
1570                         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1571
1572                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1573                                                wm_info, fifo_size, cpp,
1574                                                pessimal_latency_ns);
1575                 if (enabled == NULL)
1576                         enabled = crtc;
1577                 else
1578                         enabled = NULL;
1579         } else {
1580                 planeb_wm = fifo_size - wm_info->guard_size;
1581                 if (planeb_wm > (long)wm_info->max_wm)
1582                         planeb_wm = wm_info->max_wm;
1583         }
1584
1585         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1586
1587         if (IS_I915GM(dev_priv) && enabled) {
1588                 struct drm_i915_gem_object *obj;
1589
1590                 obj = intel_fb_obj(enabled->base.primary->state->fb);
1591
1592                 /* self-refresh seems busted with untiled */
1593                 if (!i915_gem_object_is_tiled(obj))
1594                         enabled = NULL;
1595         }
1596
1597         /*
1598          * Overlay gets an aggressive default since video jitter is bad.
1599          */
1600         cwm = 2;
1601
1602         /* Play safe and disable self-refresh before adjusting watermarks. */
1603         intel_set_memory_cxsr(dev_priv, false);
1604
1605         /* Calc sr entries for one plane configs */
1606         if (HAS_FW_BLC(dev_priv) && enabled) {
1607                 /* self-refresh has much higher latency */
1608                 static const int sr_latency_ns = 6000;
1609                 const struct drm_display_mode *adjusted_mode =
1610                         &enabled->config->base.adjusted_mode;
1611                 const struct drm_framebuffer *fb =
1612                         enabled->base.primary->state->fb;
1613                 int clock = adjusted_mode->crtc_clock;
1614                 int htotal = adjusted_mode->crtc_htotal;
1615                 int hdisplay = enabled->config->pipe_src_w;
1616                 int cpp;
1617                 unsigned long line_time_us;
1618                 int entries;
1619
1620                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
1621                         cpp = 4;
1622                 else
1623                         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1624
1625                 line_time_us = max(htotal * 1000 / clock, 1);
1626
1627                 /* Use ns/us then divide to preserve precision */
1628                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1629                         cpp * hdisplay;
1630                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1631                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1632                 srwm = wm_info->fifo_size - entries;
1633                 if (srwm < 0)
1634                         srwm = 1;
1635
1636                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1637                         I915_WRITE(FW_BLC_SELF,
1638                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1639                 else
1640                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1641         }
1642
1643         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1644                       planea_wm, planeb_wm, cwm, srwm);
1645
1646         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1647         fwater_hi = (cwm & 0x1f);
1648
1649         /* Set request length to 8 cachelines per fetch */
1650         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1651         fwater_hi = fwater_hi | (1 << 8);
1652
1653         I915_WRITE(FW_BLC, fwater_lo);
1654         I915_WRITE(FW_BLC2, fwater_hi);
1655
1656         if (enabled)
1657                 intel_set_memory_cxsr(dev_priv, true);
1658 }
1659
1660 static void i845_update_wm(struct intel_crtc *unused_crtc)
1661 {
1662         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1663         struct intel_crtc *crtc;
1664         const struct drm_display_mode *adjusted_mode;
1665         uint32_t fwater_lo;
1666         int planea_wm;
1667
1668         crtc = single_enabled_crtc(dev_priv);
1669         if (crtc == NULL)
1670                 return;
1671
1672         adjusted_mode = &crtc->config->base.adjusted_mode;
1673         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1674                                        &i845_wm_info,
1675                                        dev_priv->display.get_fifo_size(dev_priv, 0),
1676                                        4, pessimal_latency_ns);
1677         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1678         fwater_lo |= (3<<8) | planea_wm;
1679
1680         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1681
1682         I915_WRITE(FW_BLC, fwater_lo);
1683 }
1684
1685 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1686 {
1687         uint32_t pixel_rate;
1688
1689         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1690
1691         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1692          * adjust the pixel_rate here. */
1693
1694         if (pipe_config->pch_pfit.enabled) {
1695                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1696                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1697
1698                 pipe_w = pipe_config->pipe_src_w;
1699                 pipe_h = pipe_config->pipe_src_h;
1700
1701                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1702                 pfit_h = pfit_size & 0xFFFF;
1703                 if (pipe_w < pfit_w)
1704                         pipe_w = pfit_w;
1705                 if (pipe_h < pfit_h)
1706                         pipe_h = pfit_h;
1707
1708                 if (WARN_ON(!pfit_w || !pfit_h))
1709                         return pixel_rate;
1710
1711                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1712                                      pfit_w * pfit_h);
1713         }
1714
1715         return pixel_rate;
1716 }
1717
1718 /* latency must be in 0.1us units. */
1719 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1720 {
1721         uint64_t ret;
1722
1723         if (WARN(latency == 0, "Latency value missing\n"))
1724                 return UINT_MAX;
1725
1726         ret = (uint64_t) pixel_rate * cpp * latency;
1727         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1728
1729         return ret;
1730 }
1731
1732 /* latency must be in 0.1us units. */
1733 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1734                                uint32_t horiz_pixels, uint8_t cpp,
1735                                uint32_t latency)
1736 {
1737         uint32_t ret;
1738
1739         if (WARN(latency == 0, "Latency value missing\n"))
1740                 return UINT_MAX;
1741         if (WARN_ON(!pipe_htotal))
1742                 return UINT_MAX;
1743
1744         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1745         ret = (ret + 1) * horiz_pixels * cpp;
1746         ret = DIV_ROUND_UP(ret, 64) + 2;
1747         return ret;
1748 }
1749
1750 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1751                            uint8_t cpp)
1752 {
1753         /*
1754          * Neither of these should be possible since this function shouldn't be
1755          * called if the CRTC is off or the plane is invisible.  But let's be
1756          * extra paranoid to avoid a potential divide-by-zero if we screw up
1757          * elsewhere in the driver.
1758          */
1759         if (WARN_ON(!cpp))
1760                 return 0;
1761         if (WARN_ON(!horiz_pixels))
1762                 return 0;
1763
1764         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1765 }
1766
1767 struct ilk_wm_maximums {
1768         uint16_t pri;
1769         uint16_t spr;
1770         uint16_t cur;
1771         uint16_t fbc;
1772 };
1773
1774 /*
1775  * For both WM_PIPE and WM_LP.
1776  * mem_value must be in 0.1us units.
1777  */
1778 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1779                                    const struct intel_plane_state *pstate,
1780                                    uint32_t mem_value,
1781                                    bool is_lp)
1782 {
1783         int cpp = pstate->base.fb ?
1784                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1785         uint32_t method1, method2;
1786
1787         if (!cstate->base.active || !pstate->base.visible)
1788                 return 0;
1789
1790         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1791
1792         if (!is_lp)
1793                 return method1;
1794
1795         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1796                                  cstate->base.adjusted_mode.crtc_htotal,
1797                                  drm_rect_width(&pstate->base.dst),
1798                                  cpp, mem_value);
1799
1800         return min(method1, method2);
1801 }
1802
1803 /*
1804  * For both WM_PIPE and WM_LP.
1805  * mem_value must be in 0.1us units.
1806  */
1807 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1808                                    const struct intel_plane_state *pstate,
1809                                    uint32_t mem_value)
1810 {
1811         int cpp = pstate->base.fb ?
1812                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1813         uint32_t method1, method2;
1814
1815         if (!cstate->base.active || !pstate->base.visible)
1816                 return 0;
1817
1818         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1819         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1820                                  cstate->base.adjusted_mode.crtc_htotal,
1821                                  drm_rect_width(&pstate->base.dst),
1822                                  cpp, mem_value);
1823         return min(method1, method2);
1824 }
1825
1826 /*
1827  * For both WM_PIPE and WM_LP.
1828  * mem_value must be in 0.1us units.
1829  */
1830 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1831                                    const struct intel_plane_state *pstate,
1832                                    uint32_t mem_value)
1833 {
1834         /*
1835          * We treat the cursor plane as always-on for the purposes of watermark
1836          * calculation.  Until we have two-stage watermark programming merged,
1837          * this is necessary to avoid flickering.
1838          */
1839         int cpp = 4;
1840         int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1841
1842         if (!cstate->base.active)
1843                 return 0;
1844
1845         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1846                               cstate->base.adjusted_mode.crtc_htotal,
1847                               width, cpp, mem_value);
1848 }
1849
1850 /* Only for WM_LP. */
1851 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1852                                    const struct intel_plane_state *pstate,
1853                                    uint32_t pri_val)
1854 {
1855         int cpp = pstate->base.fb ?
1856                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1857
1858         if (!cstate->base.active || !pstate->base.visible)
1859                 return 0;
1860
1861         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1862 }
1863
1864 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1865 {
1866         if (INTEL_INFO(dev)->gen >= 8)
1867                 return 3072;
1868         else if (INTEL_INFO(dev)->gen >= 7)
1869                 return 768;
1870         else
1871                 return 512;
1872 }
1873
1874 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1875                                          int level, bool is_sprite)
1876 {
1877         if (INTEL_INFO(dev)->gen >= 8)
1878                 /* BDW primary/sprite plane watermarks */
1879                 return level == 0 ? 255 : 2047;
1880         else if (INTEL_INFO(dev)->gen >= 7)
1881                 /* IVB/HSW primary/sprite plane watermarks */
1882                 return level == 0 ? 127 : 1023;
1883         else if (!is_sprite)
1884                 /* ILK/SNB primary plane watermarks */
1885                 return level == 0 ? 127 : 511;
1886         else
1887                 /* ILK/SNB sprite plane watermarks */
1888                 return level == 0 ? 63 : 255;
1889 }
1890
1891 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1892                                           int level)
1893 {
1894         if (INTEL_INFO(dev)->gen >= 7)
1895                 return level == 0 ? 63 : 255;
1896         else
1897                 return level == 0 ? 31 : 63;
1898 }
1899
1900 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1901 {
1902         if (INTEL_INFO(dev)->gen >= 8)
1903                 return 31;
1904         else
1905                 return 15;
1906 }
1907
1908 /* Calculate the maximum primary/sprite plane watermark */
1909 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1910                                      int level,
1911                                      const struct intel_wm_config *config,
1912                                      enum intel_ddb_partitioning ddb_partitioning,
1913                                      bool is_sprite)
1914 {
1915         unsigned int fifo_size = ilk_display_fifo_size(dev);
1916
1917         /* if sprites aren't enabled, sprites get nothing */
1918         if (is_sprite && !config->sprites_enabled)
1919                 return 0;
1920
1921         /* HSW allows LP1+ watermarks even with multiple pipes */
1922         if (level == 0 || config->num_pipes_active > 1) {
1923                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1924
1925                 /*
1926                  * For some reason the non self refresh
1927                  * FIFO size is only half of the self
1928                  * refresh FIFO size on ILK/SNB.
1929                  */
1930                 if (INTEL_INFO(dev)->gen <= 6)
1931                         fifo_size /= 2;
1932         }
1933
1934         if (config->sprites_enabled) {
1935                 /* level 0 is always calculated with 1:1 split */
1936                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1937                         if (is_sprite)
1938                                 fifo_size *= 5;
1939                         fifo_size /= 6;
1940                 } else {
1941                         fifo_size /= 2;
1942                 }
1943         }
1944
1945         /* clamp to max that the registers can hold */
1946         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1947 }
1948
1949 /* Calculate the maximum cursor plane watermark */
1950 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1951                                       int level,
1952                                       const struct intel_wm_config *config)
1953 {
1954         /* HSW LP1+ watermarks w/ multiple pipes */
1955         if (level > 0 && config->num_pipes_active > 1)
1956                 return 64;
1957
1958         /* otherwise just report max that registers can hold */
1959         return ilk_cursor_wm_reg_max(dev, level);
1960 }
1961
1962 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1963                                     int level,
1964                                     const struct intel_wm_config *config,
1965                                     enum intel_ddb_partitioning ddb_partitioning,
1966                                     struct ilk_wm_maximums *max)
1967 {
1968         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1969         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1970         max->cur = ilk_cursor_wm_max(dev, level, config);
1971         max->fbc = ilk_fbc_wm_reg_max(dev);
1972 }
1973
1974 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1975                                         int level,
1976                                         struct ilk_wm_maximums *max)
1977 {
1978         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1979         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1980         max->cur = ilk_cursor_wm_reg_max(dev, level);
1981         max->fbc = ilk_fbc_wm_reg_max(dev);
1982 }
1983
1984 static bool ilk_validate_wm_level(int level,
1985                                   const struct ilk_wm_maximums *max,
1986                                   struct intel_wm_level *result)
1987 {
1988         bool ret;
1989
1990         /* already determined to be invalid? */
1991         if (!result->enable)
1992                 return false;
1993
1994         result->enable = result->pri_val <= max->pri &&
1995                          result->spr_val <= max->spr &&
1996                          result->cur_val <= max->cur;
1997
1998         ret = result->enable;
1999
2000         /*
2001          * HACK until we can pre-compute everything,
2002          * and thus fail gracefully if LP0 watermarks
2003          * are exceeded...
2004          */
2005         if (level == 0 && !result->enable) {
2006                 if (result->pri_val > max->pri)
2007                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2008                                       level, result->pri_val, max->pri);
2009                 if (result->spr_val > max->spr)
2010                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2011                                       level, result->spr_val, max->spr);
2012                 if (result->cur_val > max->cur)
2013                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2014                                       level, result->cur_val, max->cur);
2015
2016                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2017                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2018                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2019                 result->enable = true;
2020         }
2021
2022         return ret;
2023 }
2024
2025 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2026                                  const struct intel_crtc *intel_crtc,
2027                                  int level,
2028                                  struct intel_crtc_state *cstate,
2029                                  struct intel_plane_state *pristate,
2030                                  struct intel_plane_state *sprstate,
2031                                  struct intel_plane_state *curstate,
2032                                  struct intel_wm_level *result)
2033 {
2034         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2035         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2036         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2037
2038         /* WM1+ latency values stored in 0.5us units */
2039         if (level > 0) {
2040                 pri_latency *= 5;
2041                 spr_latency *= 5;
2042                 cur_latency *= 5;
2043         }
2044
2045         if (pristate) {
2046                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2047                                                      pri_latency, level);
2048                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2049         }
2050
2051         if (sprstate)
2052                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2053
2054         if (curstate)
2055                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2056
2057         result->enable = true;
2058 }
2059
2060 static uint32_t
2061 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2062 {
2063         const struct intel_atomic_state *intel_state =
2064                 to_intel_atomic_state(cstate->base.state);
2065         const struct drm_display_mode *adjusted_mode =
2066                 &cstate->base.adjusted_mode;
2067         u32 linetime, ips_linetime;
2068
2069         if (!cstate->base.active)
2070                 return 0;
2071         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2072                 return 0;
2073         if (WARN_ON(intel_state->cdclk == 0))
2074                 return 0;
2075
2076         /* The WM are computed with base on how long it takes to fill a single
2077          * row at the given clock rate, multiplied by 8.
2078          * */
2079         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2080                                      adjusted_mode->crtc_clock);
2081         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2082                                          intel_state->cdclk);
2083
2084         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2085                PIPE_WM_LINETIME_TIME(linetime);
2086 }
2087
2088 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2089                                   uint16_t wm[8])
2090 {
2091         if (IS_GEN9(dev_priv)) {
2092                 uint32_t val;
2093                 int ret, i;
2094                 int level, max_level = ilk_wm_max_level(dev_priv);
2095
2096                 /* read the first set of memory latencies[0:3] */
2097                 val = 0; /* data0 to be programmed to 0 for first set */
2098                 mutex_lock(&dev_priv->rps.hw_lock);
2099                 ret = sandybridge_pcode_read(dev_priv,
2100                                              GEN9_PCODE_READ_MEM_LATENCY,
2101                                              &val);
2102                 mutex_unlock(&dev_priv->rps.hw_lock);
2103
2104                 if (ret) {
2105                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2106                         return;
2107                 }
2108
2109                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2110                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2111                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2112                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2113                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2114                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2115                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2116
2117                 /* read the second set of memory latencies[4:7] */
2118                 val = 1; /* data0 to be programmed to 1 for second set */
2119                 mutex_lock(&dev_priv->rps.hw_lock);
2120                 ret = sandybridge_pcode_read(dev_priv,
2121                                              GEN9_PCODE_READ_MEM_LATENCY,
2122                                              &val);
2123                 mutex_unlock(&dev_priv->rps.hw_lock);
2124                 if (ret) {
2125                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2126                         return;
2127                 }
2128
2129                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2130                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2131                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2132                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2133                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2134                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2135                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2136
2137                 /*
2138                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2139                  * need to be disabled. We make sure to sanitize the values out
2140                  * of the punit to satisfy this requirement.
2141                  */
2142                 for (level = 1; level <= max_level; level++) {
2143                         if (wm[level] == 0) {
2144                                 for (i = level + 1; i <= max_level; i++)
2145                                         wm[i] = 0;
2146                                 break;
2147                         }
2148                 }
2149
2150                 /*
2151                  * WaWmMemoryReadLatency:skl
2152                  *
2153                  * punit doesn't take into account the read latency so we need
2154                  * to add 2us to the various latency levels we retrieve from the
2155                  * punit when level 0 response data us 0us.
2156                  */
2157                 if (wm[0] == 0) {
2158                         wm[0] += 2;
2159                         for (level = 1; level <= max_level; level++) {
2160                                 if (wm[level] == 0)
2161                                         break;
2162                                 wm[level] += 2;
2163                         }
2164                 }
2165
2166         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2167                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2168
2169                 wm[0] = (sskpd >> 56) & 0xFF;
2170                 if (wm[0] == 0)
2171                         wm[0] = sskpd & 0xF;
2172                 wm[1] = (sskpd >> 4) & 0xFF;
2173                 wm[2] = (sskpd >> 12) & 0xFF;
2174                 wm[3] = (sskpd >> 20) & 0x1FF;
2175                 wm[4] = (sskpd >> 32) & 0x1FF;
2176         } else if (INTEL_GEN(dev_priv) >= 6) {
2177                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2178
2179                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2180                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2181                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2182                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2183         } else if (INTEL_GEN(dev_priv) >= 5) {
2184                 uint32_t mltr = I915_READ(MLTR_ILK);
2185
2186                 /* ILK primary LP0 latency is 700 ns */
2187                 wm[0] = 7;
2188                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2189                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2190         }
2191 }
2192
2193 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2194                                        uint16_t wm[5])
2195 {
2196         /* ILK sprite LP0 latency is 1300 ns */
2197         if (IS_GEN5(dev_priv))
2198                 wm[0] = 13;
2199 }
2200
2201 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2202                                        uint16_t wm[5])
2203 {
2204         /* ILK cursor LP0 latency is 1300 ns */
2205         if (IS_GEN5(dev_priv))
2206                 wm[0] = 13;
2207
2208         /* WaDoubleCursorLP3Latency:ivb */
2209         if (IS_IVYBRIDGE(dev_priv))
2210                 wm[3] *= 2;
2211 }
2212
2213 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2214 {
2215         /* how many WM levels are we expecting */
2216         if (INTEL_GEN(dev_priv) >= 9)
2217                 return 7;
2218         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2219                 return 4;
2220         else if (INTEL_GEN(dev_priv) >= 6)
2221                 return 3;
2222         else
2223                 return 2;
2224 }
2225
2226 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2227                                    const char *name,
2228                                    const uint16_t wm[8])
2229 {
2230         int level, max_level = ilk_wm_max_level(dev_priv);
2231
2232         for (level = 0; level <= max_level; level++) {
2233                 unsigned int latency = wm[level];
2234
2235                 if (latency == 0) {
2236                         DRM_ERROR("%s WM%d latency not provided\n",
2237                                   name, level);
2238                         continue;
2239                 }
2240
2241                 /*
2242                  * - latencies are in us on gen9.
2243                  * - before then, WM1+ latency values are in 0.5us units
2244                  */
2245                 if (IS_GEN9(dev_priv))
2246                         latency *= 10;
2247                 else if (level > 0)
2248                         latency *= 5;
2249
2250                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2251                               name, level, wm[level],
2252                               latency / 10, latency % 10);
2253         }
2254 }
2255
2256 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2257                                     uint16_t wm[5], uint16_t min)
2258 {
2259         int level, max_level = ilk_wm_max_level(dev_priv);
2260
2261         if (wm[0] >= min)
2262                 return false;
2263
2264         wm[0] = max(wm[0], min);
2265         for (level = 1; level <= max_level; level++)
2266                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2267
2268         return true;
2269 }
2270
2271 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2272 {
2273         bool changed;
2274
2275         /*
2276          * The BIOS provided WM memory latency values are often
2277          * inadequate for high resolution displays. Adjust them.
2278          */
2279         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2280                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2281                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2282
2283         if (!changed)
2284                 return;
2285
2286         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2287         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2288         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2289         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2290 }
2291
2292 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
2293 {
2294         intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
2295
2296         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2297                sizeof(dev_priv->wm.pri_latency));
2298         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2299                sizeof(dev_priv->wm.pri_latency));
2300
2301         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2302         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2303
2304         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2305         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2306         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2307
2308         if (IS_GEN6(dev_priv))
2309                 snb_wm_latency_quirk(dev_priv);
2310 }
2311
2312 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
2313 {
2314         intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
2315         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2316 }
2317
2318 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2319                                  struct intel_pipe_wm *pipe_wm)
2320 {
2321         /* LP0 watermark maximums depend on this pipe alone */
2322         const struct intel_wm_config config = {
2323                 .num_pipes_active = 1,
2324                 .sprites_enabled = pipe_wm->sprites_enabled,
2325                 .sprites_scaled = pipe_wm->sprites_scaled,
2326         };
2327         struct ilk_wm_maximums max;
2328
2329         /* LP0 watermarks always use 1/2 DDB partitioning */
2330         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2331
2332         /* At least LP0 must be valid */
2333         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2334                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2335                 return false;
2336         }
2337
2338         return true;
2339 }
2340
2341 /* Compute new watermarks for the pipe */
2342 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2343 {
2344         struct drm_atomic_state *state = cstate->base.state;
2345         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2346         struct intel_pipe_wm *pipe_wm;
2347         struct drm_device *dev = state->dev;
2348         const struct drm_i915_private *dev_priv = to_i915(dev);
2349         struct intel_plane *intel_plane;
2350         struct intel_plane_state *pristate = NULL;
2351         struct intel_plane_state *sprstate = NULL;
2352         struct intel_plane_state *curstate = NULL;
2353         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
2354         struct ilk_wm_maximums max;
2355
2356         pipe_wm = &cstate->wm.ilk.optimal;
2357
2358         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2359                 struct intel_plane_state *ps;
2360
2361                 ps = intel_atomic_get_existing_plane_state(state,
2362                                                            intel_plane);
2363                 if (!ps)
2364                         continue;
2365
2366                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2367                         pristate = ps;
2368                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2369                         sprstate = ps;
2370                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2371                         curstate = ps;
2372         }
2373
2374         pipe_wm->pipe_enabled = cstate->base.active;
2375         if (sprstate) {
2376                 pipe_wm->sprites_enabled = sprstate->base.visible;
2377                 pipe_wm->sprites_scaled = sprstate->base.visible &&
2378                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2379                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2380         }
2381
2382         usable_level = max_level;
2383
2384         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2385         if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2386                 usable_level = 1;
2387
2388         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2389         if (pipe_wm->sprites_scaled)
2390                 usable_level = 0;
2391
2392         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2393                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2394
2395         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2396         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2397
2398         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2399                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2400
2401         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2402                 return -EINVAL;
2403
2404         ilk_compute_wm_reg_maximums(dev, 1, &max);
2405
2406         for (level = 1; level <= max_level; level++) {
2407                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2408
2409                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2410                                      pristate, sprstate, curstate, wm);
2411
2412                 /*
2413                  * Disable any watermark level that exceeds the
2414                  * register maximums since such watermarks are
2415                  * always invalid.
2416                  */
2417                 if (level > usable_level)
2418                         continue;
2419
2420                 if (ilk_validate_wm_level(level, &max, wm))
2421                         pipe_wm->wm[level] = *wm;
2422                 else
2423                         usable_level = level;
2424         }
2425
2426         return 0;
2427 }
2428
2429 /*
2430  * Build a set of 'intermediate' watermark values that satisfy both the old
2431  * state and the new state.  These can be programmed to the hardware
2432  * immediately.
2433  */
2434 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2435                                        struct intel_crtc *intel_crtc,
2436                                        struct intel_crtc_state *newstate)
2437 {
2438         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2439         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2440         int level, max_level = ilk_wm_max_level(to_i915(dev));
2441
2442         /*
2443          * Start with the final, target watermarks, then combine with the
2444          * currently active watermarks to get values that are safe both before
2445          * and after the vblank.
2446          */
2447         *a = newstate->wm.ilk.optimal;
2448         a->pipe_enabled |= b->pipe_enabled;
2449         a->sprites_enabled |= b->sprites_enabled;
2450         a->sprites_scaled |= b->sprites_scaled;
2451
2452         for (level = 0; level <= max_level; level++) {
2453                 struct intel_wm_level *a_wm = &a->wm[level];
2454                 const struct intel_wm_level *b_wm = &b->wm[level];
2455
2456                 a_wm->enable &= b_wm->enable;
2457                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2458                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2459                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2460                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2461         }
2462
2463         /*
2464          * We need to make sure that these merged watermark values are
2465          * actually a valid configuration themselves.  If they're not,
2466          * there's no safe way to transition from the old state to
2467          * the new state, so we need to fail the atomic transaction.
2468          */
2469         if (!ilk_validate_pipe_wm(dev, a))
2470                 return -EINVAL;
2471
2472         /*
2473          * If our intermediate WM are identical to the final WM, then we can
2474          * omit the post-vblank programming; only update if it's different.
2475          */
2476         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2477                 newstate->wm.need_postvbl_update = false;
2478
2479         return 0;
2480 }
2481
2482 /*
2483  * Merge the watermarks from all active pipes for a specific level.
2484  */
2485 static void ilk_merge_wm_level(struct drm_device *dev,
2486                                int level,
2487                                struct intel_wm_level *ret_wm)
2488 {
2489         const struct intel_crtc *intel_crtc;
2490
2491         ret_wm->enable = true;
2492
2493         for_each_intel_crtc(dev, intel_crtc) {
2494                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2495                 const struct intel_wm_level *wm = &active->wm[level];
2496
2497                 if (!active->pipe_enabled)
2498                         continue;
2499
2500                 /*
2501                  * The watermark values may have been used in the past,
2502                  * so we must maintain them in the registers for some
2503                  * time even if the level is now disabled.
2504                  */
2505                 if (!wm->enable)
2506                         ret_wm->enable = false;
2507
2508                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2509                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2510                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2511                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2512         }
2513 }
2514
2515 /*
2516  * Merge all low power watermarks for all active pipes.
2517  */
2518 static void ilk_wm_merge(struct drm_device *dev,
2519                          const struct intel_wm_config *config,
2520                          const struct ilk_wm_maximums *max,
2521                          struct intel_pipe_wm *merged)
2522 {
2523         struct drm_i915_private *dev_priv = to_i915(dev);
2524         int level, max_level = ilk_wm_max_level(dev_priv);
2525         int last_enabled_level = max_level;
2526
2527         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2528         if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
2529             config->num_pipes_active > 1)
2530                 last_enabled_level = 0;
2531
2532         /* ILK: FBC WM must be disabled always */
2533         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2534
2535         /* merge each WM1+ level */
2536         for (level = 1; level <= max_level; level++) {
2537                 struct intel_wm_level *wm = &merged->wm[level];
2538
2539                 ilk_merge_wm_level(dev, level, wm);
2540
2541                 if (level > last_enabled_level)
2542                         wm->enable = false;
2543                 else if (!ilk_validate_wm_level(level, max, wm))
2544                         /* make sure all following levels get disabled */
2545                         last_enabled_level = level - 1;
2546
2547                 /*
2548                  * The spec says it is preferred to disable
2549                  * FBC WMs instead of disabling a WM level.
2550                  */
2551                 if (wm->fbc_val > max->fbc) {
2552                         if (wm->enable)
2553                                 merged->fbc_wm_enabled = false;
2554                         wm->fbc_val = 0;
2555                 }
2556         }
2557
2558         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2559         /*
2560          * FIXME this is racy. FBC might get enabled later.
2561          * What we should check here is whether FBC can be
2562          * enabled sometime later.
2563          */
2564         if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
2565             intel_fbc_is_active(dev_priv)) {
2566                 for (level = 2; level <= max_level; level++) {
2567                         struct intel_wm_level *wm = &merged->wm[level];
2568
2569                         wm->enable = false;
2570                 }
2571         }
2572 }
2573
2574 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2575 {
2576         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2577         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2578 }
2579
2580 /* The value we need to program into the WM_LPx latency field */
2581 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2582 {
2583         struct drm_i915_private *dev_priv = to_i915(dev);
2584
2585         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2586                 return 2 * level;
2587         else
2588                 return dev_priv->wm.pri_latency[level];
2589 }
2590
2591 static void ilk_compute_wm_results(struct drm_device *dev,
2592                                    const struct intel_pipe_wm *merged,
2593                                    enum intel_ddb_partitioning partitioning,
2594                                    struct ilk_wm_values *results)
2595 {
2596         struct intel_crtc *intel_crtc;
2597         int level, wm_lp;
2598
2599         results->enable_fbc_wm = merged->fbc_wm_enabled;
2600         results->partitioning = partitioning;
2601
2602         /* LP1+ register values */
2603         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2604                 const struct intel_wm_level *r;
2605
2606                 level = ilk_wm_lp_to_level(wm_lp, merged);
2607
2608                 r = &merged->wm[level];
2609
2610                 /*
2611                  * Maintain the watermark values even if the level is
2612                  * disabled. Doing otherwise could cause underruns.
2613                  */
2614                 results->wm_lp[wm_lp - 1] =
2615                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2616                         (r->pri_val << WM1_LP_SR_SHIFT) |
2617                         r->cur_val;
2618
2619                 if (r->enable)
2620                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2621
2622                 if (INTEL_INFO(dev)->gen >= 8)
2623                         results->wm_lp[wm_lp - 1] |=
2624                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2625                 else
2626                         results->wm_lp[wm_lp - 1] |=
2627                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2628
2629                 /*
2630                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2631                  * level is disabled. Doing otherwise could cause underruns.
2632                  */
2633                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2634                         WARN_ON(wm_lp != 1);
2635                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2636                 } else
2637                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2638         }
2639
2640         /* LP0 register values */
2641         for_each_intel_crtc(dev, intel_crtc) {
2642                 enum pipe pipe = intel_crtc->pipe;
2643                 const struct intel_wm_level *r =
2644                         &intel_crtc->wm.active.ilk.wm[0];
2645
2646                 if (WARN_ON(!r->enable))
2647                         continue;
2648
2649                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2650
2651                 results->wm_pipe[pipe] =
2652                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2653                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2654                         r->cur_val;
2655         }
2656 }
2657
2658 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2659  * case both are at the same level. Prefer r1 in case they're the same. */
2660 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2661                                                   struct intel_pipe_wm *r1,
2662                                                   struct intel_pipe_wm *r2)
2663 {
2664         int level, max_level = ilk_wm_max_level(to_i915(dev));
2665         int level1 = 0, level2 = 0;
2666
2667         for (level = 1; level <= max_level; level++) {
2668                 if (r1->wm[level].enable)
2669                         level1 = level;
2670                 if (r2->wm[level].enable)
2671                         level2 = level;
2672         }
2673
2674         if (level1 == level2) {
2675                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2676                         return r2;
2677                 else
2678                         return r1;
2679         } else if (level1 > level2) {
2680                 return r1;
2681         } else {
2682                 return r2;
2683         }
2684 }
2685
2686 /* dirty bits used to track which watermarks need changes */
2687 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2688 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2689 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2690 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2691 #define WM_DIRTY_FBC (1 << 24)
2692 #define WM_DIRTY_DDB (1 << 25)
2693
2694 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2695                                          const struct ilk_wm_values *old,
2696                                          const struct ilk_wm_values *new)
2697 {
2698         unsigned int dirty = 0;
2699         enum pipe pipe;
2700         int wm_lp;
2701
2702         for_each_pipe(dev_priv, pipe) {
2703                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2704                         dirty |= WM_DIRTY_LINETIME(pipe);
2705                         /* Must disable LP1+ watermarks too */
2706                         dirty |= WM_DIRTY_LP_ALL;
2707                 }
2708
2709                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2710                         dirty |= WM_DIRTY_PIPE(pipe);
2711                         /* Must disable LP1+ watermarks too */
2712                         dirty |= WM_DIRTY_LP_ALL;
2713                 }
2714         }
2715
2716         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2717                 dirty |= WM_DIRTY_FBC;
2718                 /* Must disable LP1+ watermarks too */
2719                 dirty |= WM_DIRTY_LP_ALL;
2720         }
2721
2722         if (old->partitioning != new->partitioning) {
2723                 dirty |= WM_DIRTY_DDB;
2724                 /* Must disable LP1+ watermarks too */
2725                 dirty |= WM_DIRTY_LP_ALL;
2726         }
2727
2728         /* LP1+ watermarks already deemed dirty, no need to continue */
2729         if (dirty & WM_DIRTY_LP_ALL)
2730                 return dirty;
2731
2732         /* Find the lowest numbered LP1+ watermark in need of an update... */
2733         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2734                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2735                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2736                         break;
2737         }
2738
2739         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2740         for (; wm_lp <= 3; wm_lp++)
2741                 dirty |= WM_DIRTY_LP(wm_lp);
2742
2743         return dirty;
2744 }
2745
2746 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2747                                unsigned int dirty)
2748 {
2749         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2750         bool changed = false;
2751
2752         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2753                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2754                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2755                 changed = true;
2756         }
2757         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2758                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2759                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2760                 changed = true;
2761         }
2762         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2763                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2764                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2765                 changed = true;
2766         }
2767
2768         /*
2769          * Don't touch WM1S_LP_EN here.
2770          * Doing so could cause underruns.
2771          */
2772
2773         return changed;
2774 }
2775
2776 /*
2777  * The spec says we shouldn't write when we don't need, because every write
2778  * causes WMs to be re-evaluated, expending some power.
2779  */
2780 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2781                                 struct ilk_wm_values *results)
2782 {
2783         struct drm_device *dev = &dev_priv->drm;
2784         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2785         unsigned int dirty;
2786         uint32_t val;
2787
2788         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2789         if (!dirty)
2790                 return;
2791
2792         _ilk_disable_lp_wm(dev_priv, dirty);
2793
2794         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2795                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2796         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2797                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2798         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2799                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2800
2801         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2802                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2803         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2804                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2805         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2806                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2807
2808         if (dirty & WM_DIRTY_DDB) {
2809                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2810                         val = I915_READ(WM_MISC);
2811                         if (results->partitioning == INTEL_DDB_PART_1_2)
2812                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2813                         else
2814                                 val |= WM_MISC_DATA_PARTITION_5_6;
2815                         I915_WRITE(WM_MISC, val);
2816                 } else {
2817                         val = I915_READ(DISP_ARB_CTL2);
2818                         if (results->partitioning == INTEL_DDB_PART_1_2)
2819                                 val &= ~DISP_DATA_PARTITION_5_6;
2820                         else
2821                                 val |= DISP_DATA_PARTITION_5_6;
2822                         I915_WRITE(DISP_ARB_CTL2, val);
2823                 }
2824         }
2825
2826         if (dirty & WM_DIRTY_FBC) {
2827                 val = I915_READ(DISP_ARB_CTL);
2828                 if (results->enable_fbc_wm)
2829                         val &= ~DISP_FBC_WM_DIS;
2830                 else
2831                         val |= DISP_FBC_WM_DIS;
2832                 I915_WRITE(DISP_ARB_CTL, val);
2833         }
2834
2835         if (dirty & WM_DIRTY_LP(1) &&
2836             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2837                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2838
2839         if (INTEL_INFO(dev)->gen >= 7) {
2840                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2841                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2842                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2843                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2844         }
2845
2846         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2847                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2848         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2849                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2850         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2851                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2852
2853         dev_priv->wm.hw = *results;
2854 }
2855
2856 bool ilk_disable_lp_wm(struct drm_device *dev)
2857 {
2858         struct drm_i915_private *dev_priv = to_i915(dev);
2859
2860         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2861 }
2862
2863 #define SKL_SAGV_BLOCK_TIME     30 /* µs */
2864
2865 /*
2866  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2867  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2868  * other universal planes are in indices 1..n.  Note that this may leave unused
2869  * indices between the top "sprite" plane and the cursor.
2870  */
2871 static int
2872 skl_wm_plane_id(const struct intel_plane *plane)
2873 {
2874         switch (plane->base.type) {
2875         case DRM_PLANE_TYPE_PRIMARY:
2876                 return 0;
2877         case DRM_PLANE_TYPE_CURSOR:
2878                 return PLANE_CURSOR;
2879         case DRM_PLANE_TYPE_OVERLAY:
2880                 return plane->plane + 1;
2881         default:
2882                 MISSING_CASE(plane->base.type);
2883                 return plane->plane;
2884         }
2885 }
2886
2887 /*
2888  * FIXME: We still don't have the proper code detect if we need to apply the WA,
2889  * so assume we'll always need it in order to avoid underruns.
2890  */
2891 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2892 {
2893         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2894
2895         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2896             IS_KABYLAKE(dev_priv))
2897                 return true;
2898
2899         return false;
2900 }
2901
2902 static bool
2903 intel_has_sagv(struct drm_i915_private *dev_priv)
2904 {
2905         if (IS_KABYLAKE(dev_priv))
2906                 return true;
2907
2908         if (IS_SKYLAKE(dev_priv) &&
2909             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2910                 return true;
2911
2912         return false;
2913 }
2914
2915 /*
2916  * SAGV dynamically adjusts the system agent voltage and clock frequencies
2917  * depending on power and performance requirements. The display engine access
2918  * to system memory is blocked during the adjustment time. Because of the
2919  * blocking time, having this enabled can cause full system hangs and/or pipe
2920  * underruns if we don't meet all of the following requirements:
2921  *
2922  *  - <= 1 pipe enabled
2923  *  - All planes can enable watermarks for latencies >= SAGV engine block time
2924  *  - We're not using an interlaced display configuration
2925  */
2926 int
2927 intel_enable_sagv(struct drm_i915_private *dev_priv)
2928 {
2929         int ret;
2930
2931         if (!intel_has_sagv(dev_priv))
2932                 return 0;
2933
2934         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
2935                 return 0;
2936
2937         DRM_DEBUG_KMS("Enabling the SAGV\n");
2938         mutex_lock(&dev_priv->rps.hw_lock);
2939
2940         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2941                                       GEN9_SAGV_ENABLE);
2942
2943         /* We don't need to wait for the SAGV when enabling */
2944         mutex_unlock(&dev_priv->rps.hw_lock);
2945
2946         /*
2947          * Some skl systems, pre-release machines in particular,
2948          * don't actually have an SAGV.
2949          */
2950         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2951                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2952                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2953                 return 0;
2954         } else if (ret < 0) {
2955                 DRM_ERROR("Failed to enable the SAGV\n");
2956                 return ret;
2957         }
2958
2959         dev_priv->sagv_status = I915_SAGV_ENABLED;
2960         return 0;
2961 }
2962
2963 static int
2964 intel_do_sagv_disable(struct drm_i915_private *dev_priv)
2965 {
2966         int ret;
2967         uint32_t temp = GEN9_SAGV_DISABLE;
2968
2969         ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2970                                      &temp);
2971         if (ret)
2972                 return ret;
2973         else
2974                 return temp & GEN9_SAGV_IS_DISABLED;
2975 }
2976
2977 int
2978 intel_disable_sagv(struct drm_i915_private *dev_priv)
2979 {
2980         int ret, result;
2981
2982         if (!intel_has_sagv(dev_priv))
2983                 return 0;
2984
2985         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
2986                 return 0;
2987
2988         DRM_DEBUG_KMS("Disabling the SAGV\n");
2989         mutex_lock(&dev_priv->rps.hw_lock);
2990
2991         /* bspec says to keep retrying for at least 1 ms */
2992         ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
2993         mutex_unlock(&dev_priv->rps.hw_lock);
2994
2995         if (ret == -ETIMEDOUT) {
2996                 DRM_ERROR("Request to disable SAGV timed out\n");
2997                 return -ETIMEDOUT;
2998         }
2999
3000         /*
3001          * Some skl systems, pre-release machines in particular,
3002          * don't actually have an SAGV.
3003          */
3004         if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
3005                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3006                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3007                 return 0;
3008         } else if (result < 0) {
3009                 DRM_ERROR("Failed to disable the SAGV\n");
3010                 return result;
3011         }
3012
3013         dev_priv->sagv_status = I915_SAGV_DISABLED;
3014         return 0;
3015 }
3016
3017 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3018 {
3019         struct drm_device *dev = state->dev;
3020         struct drm_i915_private *dev_priv = to_i915(dev);
3021         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3022         struct intel_crtc *crtc;
3023         struct intel_plane *plane;
3024         struct intel_crtc_state *cstate;
3025         struct skl_plane_wm *wm;
3026         enum pipe pipe;
3027         int level, latency;
3028
3029         if (!intel_has_sagv(dev_priv))
3030                 return false;
3031
3032         /*
3033          * SKL workaround: bspec recommends we disable the SAGV when we have
3034          * more then one pipe enabled
3035          *
3036          * If there are no active CRTCs, no additional checks need be performed
3037          */
3038         if (hweight32(intel_state->active_crtcs) == 0)
3039                 return true;
3040         else if (hweight32(intel_state->active_crtcs) > 1)
3041                 return false;
3042
3043         /* Since we're now guaranteed to only have one active CRTC... */
3044         pipe = ffs(intel_state->active_crtcs) - 1;
3045         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3046         cstate = to_intel_crtc_state(crtc->base.state);
3047
3048         if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3049                 return false;
3050
3051         for_each_intel_plane_on_crtc(dev, crtc, plane) {
3052                 wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
3053
3054                 /* Skip this plane if it's not enabled */
3055                 if (!wm->wm[0].plane_en)
3056                         continue;
3057
3058                 /* Find the highest enabled wm level for this plane */
3059                 for (level = ilk_wm_max_level(dev_priv);
3060                      !wm->wm[level].plane_en; --level)
3061                      { }
3062
3063                 latency = dev_priv->wm.skl_latency[level];
3064
3065                 if (skl_needs_memory_bw_wa(intel_state) &&
3066                     plane->base.state->fb->modifier[0] ==
3067                     I915_FORMAT_MOD_X_TILED)
3068                         latency += 15;
3069
3070                 /*
3071                  * If any of the planes on this pipe don't enable wm levels
3072                  * that incur memory latencies higher then 30µs we can't enable
3073                  * the SAGV
3074                  */
3075                 if (latency < SKL_SAGV_BLOCK_TIME)
3076                         return false;
3077         }
3078
3079         return true;
3080 }
3081
3082 static void
3083 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3084                                    const struct intel_crtc_state *cstate,
3085                                    struct skl_ddb_entry *alloc, /* out */
3086                                    int *num_active /* out */)
3087 {
3088         struct drm_atomic_state *state = cstate->base.state;
3089         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3090         struct drm_i915_private *dev_priv = to_i915(dev);
3091         struct drm_crtc *for_crtc = cstate->base.crtc;
3092         unsigned int pipe_size, ddb_size;
3093         int nth_active_pipe;
3094
3095         if (WARN_ON(!state) || !cstate->base.active) {
3096                 alloc->start = 0;
3097                 alloc->end = 0;
3098                 *num_active = hweight32(dev_priv->active_crtcs);
3099                 return;
3100         }
3101
3102         if (intel_state->active_pipe_changes)
3103                 *num_active = hweight32(intel_state->active_crtcs);
3104         else
3105                 *num_active = hweight32(dev_priv->active_crtcs);
3106
3107         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3108         WARN_ON(ddb_size == 0);
3109
3110         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3111
3112         /*
3113          * If the state doesn't change the active CRTC's, then there's
3114          * no need to recalculate; the existing pipe allocation limits
3115          * should remain unchanged.  Note that we're safe from racing
3116          * commits since any racing commit that changes the active CRTC
3117          * list would need to grab _all_ crtc locks, including the one
3118          * we currently hold.
3119          */
3120         if (!intel_state->active_pipe_changes) {
3121                 *alloc = to_intel_crtc(for_crtc)->hw_ddb;
3122                 return;
3123         }
3124
3125         nth_active_pipe = hweight32(intel_state->active_crtcs &
3126                                     (drm_crtc_mask(for_crtc) - 1));
3127         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3128         alloc->start = nth_active_pipe * ddb_size / *num_active;
3129         alloc->end = alloc->start + pipe_size;
3130 }
3131
3132 static unsigned int skl_cursor_allocation(int num_active)
3133 {
3134         if (num_active == 1)
3135                 return 32;
3136
3137         return 8;
3138 }
3139
3140 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3141 {
3142         entry->start = reg & 0x3ff;
3143         entry->end = (reg >> 16) & 0x3ff;
3144         if (entry->end)
3145                 entry->end += 1;
3146 }
3147
3148 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3149                           struct skl_ddb_allocation *ddb /* out */)
3150 {
3151         enum pipe pipe;
3152         int plane;
3153         u32 val;
3154
3155         memset(ddb, 0, sizeof(*ddb));
3156
3157         for_each_pipe(dev_priv, pipe) {
3158                 enum intel_display_power_domain power_domain;
3159
3160                 power_domain = POWER_DOMAIN_PIPE(pipe);
3161                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3162                         continue;
3163
3164                 for_each_universal_plane(dev_priv, pipe, plane) {
3165                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3166                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3167                                                    val);
3168                 }
3169
3170                 val = I915_READ(CUR_BUF_CFG(pipe));
3171                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3172                                            val);
3173
3174                 intel_display_power_put(dev_priv, power_domain);
3175         }
3176 }
3177
3178 /*
3179  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3180  * The bspec defines downscale amount as:
3181  *
3182  * """
3183  * Horizontal down scale amount = maximum[1, Horizontal source size /
3184  *                                           Horizontal destination size]
3185  * Vertical down scale amount = maximum[1, Vertical source size /
3186  *                                         Vertical destination size]
3187  * Total down scale amount = Horizontal down scale amount *
3188  *                           Vertical down scale amount
3189  * """
3190  *
3191  * Return value is provided in 16.16 fixed point form to retain fractional part.
3192  * Caller should take care of dividing & rounding off the value.
3193  */
3194 static uint32_t
3195 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3196 {
3197         uint32_t downscale_h, downscale_w;
3198         uint32_t src_w, src_h, dst_w, dst_h;
3199
3200         if (WARN_ON(!pstate->base.visible))
3201                 return DRM_PLANE_HELPER_NO_SCALING;
3202
3203         /* n.b., src is 16.16 fixed point, dst is whole integer */
3204         src_w = drm_rect_width(&pstate->base.src);
3205         src_h = drm_rect_height(&pstate->base.src);
3206         dst_w = drm_rect_width(&pstate->base.dst);
3207         dst_h = drm_rect_height(&pstate->base.dst);
3208         if (drm_rotation_90_or_270(pstate->base.rotation))
3209                 swap(dst_w, dst_h);
3210
3211         downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3212         downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3213
3214         /* Provide result in 16.16 fixed point */
3215         return (uint64_t)downscale_w * downscale_h >> 16;
3216 }
3217
3218 static unsigned int
3219 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3220                              const struct drm_plane_state *pstate,
3221                              int y)
3222 {
3223         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3224         struct drm_framebuffer *fb = pstate->fb;
3225         uint32_t down_scale_amount, data_rate;
3226         uint32_t width = 0, height = 0;
3227         unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3228
3229         if (!intel_pstate->base.visible)
3230                 return 0;
3231         if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3232                 return 0;
3233         if (y && format != DRM_FORMAT_NV12)
3234                 return 0;
3235
3236         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3237         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3238
3239         if (drm_rotation_90_or_270(pstate->rotation))
3240                 swap(width, height);
3241
3242         /* for planar format */
3243         if (format == DRM_FORMAT_NV12) {
3244                 if (y)  /* y-plane data rate */
3245                         data_rate = width * height *
3246                                 drm_format_plane_cpp(format, 0);
3247                 else    /* uv-plane data rate */
3248                         data_rate = (width / 2) * (height / 2) *
3249                                 drm_format_plane_cpp(format, 1);
3250         } else {
3251                 /* for packed formats */
3252                 data_rate = width * height * drm_format_plane_cpp(format, 0);
3253         }
3254
3255         down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3256
3257         return (uint64_t)data_rate * down_scale_amount >> 16;
3258 }
3259
3260 /*
3261  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3262  * a 8192x4096@32bpp framebuffer:
3263  *   3 * 4096 * 8192  * 4 < 2^32
3264  */
3265 static unsigned int
3266 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3267                                  unsigned *plane_data_rate,
3268                                  unsigned *plane_y_data_rate)
3269 {
3270         struct drm_crtc_state *cstate = &intel_cstate->base;
3271         struct drm_atomic_state *state = cstate->state;
3272         struct drm_plane *plane;
3273         const struct intel_plane *intel_plane;
3274         const struct drm_plane_state *pstate;
3275         unsigned int rate, total_data_rate = 0;
3276         int id;
3277
3278         if (WARN_ON(!state))
3279                 return 0;
3280
3281         /* Calculate and cache data rate for each plane */
3282         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
3283                 id = skl_wm_plane_id(to_intel_plane(plane));
3284                 intel_plane = to_intel_plane(plane);
3285
3286                 /* packed/uv */
3287                 rate = skl_plane_relative_data_rate(intel_cstate,
3288                                                     pstate, 0);
3289                 plane_data_rate[id] = rate;
3290
3291                 total_data_rate += rate;
3292
3293                 /* y-plane */
3294                 rate = skl_plane_relative_data_rate(intel_cstate,
3295                                                     pstate, 1);
3296                 plane_y_data_rate[id] = rate;
3297
3298                 total_data_rate += rate;
3299         }
3300
3301         return total_data_rate;
3302 }
3303
3304 static uint16_t
3305 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3306                   const int y)
3307 {
3308         struct drm_framebuffer *fb = pstate->fb;
3309         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3310         uint32_t src_w, src_h;
3311         uint32_t min_scanlines = 8;
3312         uint8_t plane_bpp;
3313
3314         if (WARN_ON(!fb))
3315                 return 0;
3316
3317         /* For packed formats, no y-plane, return 0 */
3318         if (y && fb->pixel_format != DRM_FORMAT_NV12)
3319                 return 0;
3320
3321         /* For Non Y-tile return 8-blocks */
3322         if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3323             fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3324                 return 8;
3325
3326         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3327         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3328
3329         if (drm_rotation_90_or_270(pstate->rotation))
3330                 swap(src_w, src_h);
3331
3332         /* Halve UV plane width and height for NV12 */
3333         if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3334                 src_w /= 2;
3335                 src_h /= 2;
3336         }
3337
3338         if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3339                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3340         else
3341                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3342
3343         if (drm_rotation_90_or_270(pstate->rotation)) {
3344                 switch (plane_bpp) {
3345                 case 1:
3346                         min_scanlines = 32;
3347                         break;
3348                 case 2:
3349                         min_scanlines = 16;
3350                         break;
3351                 case 4:
3352                         min_scanlines = 8;
3353                         break;
3354                 case 8:
3355                         min_scanlines = 4;
3356                         break;
3357                 default:
3358                         WARN(1, "Unsupported pixel depth %u for rotation",
3359                              plane_bpp);
3360                         min_scanlines = 32;
3361                 }
3362         }
3363
3364         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3365 }
3366
3367 static void
3368 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3369                  uint16_t *minimum, uint16_t *y_minimum)
3370 {
3371         const struct drm_plane_state *pstate;
3372         struct drm_plane *plane;
3373
3374         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3375                 struct intel_plane *intel_plane = to_intel_plane(plane);
3376                 int id = skl_wm_plane_id(intel_plane);
3377
3378                 if (id == PLANE_CURSOR)
3379                         continue;
3380
3381                 if (!pstate->visible)
3382                         continue;
3383
3384                 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3385                 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3386         }
3387
3388         minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3389 }
3390
3391 static int
3392 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3393                       struct skl_ddb_allocation *ddb /* out */)
3394 {
3395         struct drm_atomic_state *state = cstate->base.state;
3396         struct drm_crtc *crtc = cstate->base.crtc;
3397         struct drm_device *dev = crtc->dev;
3398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399         enum pipe pipe = intel_crtc->pipe;
3400         struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
3401         uint16_t alloc_size, start;
3402         uint16_t minimum[I915_MAX_PLANES] = {};
3403         uint16_t y_minimum[I915_MAX_PLANES] = {};
3404         unsigned int total_data_rate;
3405         int num_active;
3406         int id, i;
3407         unsigned plane_data_rate[I915_MAX_PLANES] = {};
3408         unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
3409
3410         /* Clear the partitioning for disabled planes. */
3411         memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3412         memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3413
3414         if (WARN_ON(!state))
3415                 return 0;
3416
3417         if (!cstate->base.active) {
3418                 alloc->start = alloc->end = 0;
3419                 return 0;
3420         }
3421
3422         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3423         alloc_size = skl_ddb_entry_size(alloc);
3424         if (alloc_size == 0) {
3425                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3426                 return 0;
3427         }
3428
3429         skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
3430
3431         /*
3432          * 1. Allocate the mininum required blocks for each active plane
3433          * and allocate the cursor, it doesn't require extra allocation
3434          * proportional to the data rate.
3435          */
3436
3437         for (i = 0; i < I915_MAX_PLANES; i++) {
3438                 alloc_size -= minimum[i];
3439                 alloc_size -= y_minimum[i];
3440         }
3441
3442         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3443         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3444
3445         /*
3446          * 2. Distribute the remaining space in proportion to the amount of
3447          * data each plane needs to fetch from memory.
3448          *
3449          * FIXME: we may not allocate every single block here.
3450          */
3451         total_data_rate = skl_get_total_relative_data_rate(cstate,
3452                                                            plane_data_rate,
3453                                                            plane_y_data_rate);
3454         if (total_data_rate == 0)
3455                 return 0;
3456
3457         start = alloc->start;
3458         for (id = 0; id < I915_MAX_PLANES; id++) {
3459                 unsigned int data_rate, y_data_rate;
3460                 uint16_t plane_blocks, y_plane_blocks = 0;
3461
3462                 if (id == PLANE_CURSOR)
3463                         continue;
3464
3465                 data_rate = plane_data_rate[id];
3466
3467                 /*
3468                  * allocation for (packed formats) or (uv-plane part of planar format):
3469                  * promote the expression to 64 bits to avoid overflowing, the
3470                  * result is < available as data_rate / total_data_rate < 1
3471                  */
3472                 plane_blocks = minimum[id];
3473                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3474                                         total_data_rate);
3475
3476                 /* Leave disabled planes at (0,0) */
3477                 if (data_rate) {
3478                         ddb->plane[pipe][id].start = start;
3479                         ddb->plane[pipe][id].end = start + plane_blocks;
3480                 }
3481
3482                 start += plane_blocks;
3483
3484                 /*
3485                  * allocation for y_plane part of planar format:
3486                  */
3487                 y_data_rate = plane_y_data_rate[id];
3488
3489                 y_plane_blocks = y_minimum[id];
3490                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3491                                         total_data_rate);
3492
3493                 if (y_data_rate) {
3494                         ddb->y_plane[pipe][id].start = start;
3495                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3496                 }
3497
3498                 start += y_plane_blocks;
3499         }
3500
3501         return 0;
3502 }
3503
3504 /*
3505  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3506  * for the read latency) and cpp should always be <= 8, so that
3507  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3508  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3509 */
3510 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3511 {
3512         uint32_t wm_intermediate_val, ret;
3513
3514         if (latency == 0)
3515                 return UINT_MAX;
3516
3517         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3518         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3519
3520         return ret;
3521 }
3522
3523 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3524                                uint32_t latency, uint32_t plane_blocks_per_line)
3525 {
3526         uint32_t ret;
3527         uint32_t wm_intermediate_val;
3528
3529         if (latency == 0)
3530                 return UINT_MAX;
3531
3532         wm_intermediate_val = latency * pixel_rate;
3533         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3534                                 plane_blocks_per_line;
3535
3536         return ret;
3537 }
3538
3539 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3540                                               struct intel_plane_state *pstate)
3541 {
3542         uint64_t adjusted_pixel_rate;
3543         uint64_t downscale_amount;
3544         uint64_t pixel_rate;
3545
3546         /* Shouldn't reach here on disabled planes... */
3547         if (WARN_ON(!pstate->base.visible))
3548                 return 0;
3549
3550         /*
3551          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3552          * with additional adjustments for plane-specific scaling.
3553          */
3554         adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
3555         downscale_amount = skl_plane_downscale_amount(pstate);
3556
3557         pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3558         WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3559
3560         return pixel_rate;
3561 }
3562
3563 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3564                                 struct intel_crtc_state *cstate,
3565                                 struct intel_plane_state *intel_pstate,
3566                                 uint16_t ddb_allocation,
3567                                 int level,
3568                                 uint16_t *out_blocks, /* out */
3569                                 uint8_t *out_lines, /* out */
3570                                 bool *enabled /* out */)
3571 {
3572         struct drm_plane_state *pstate = &intel_pstate->base;
3573         struct drm_framebuffer *fb = pstate->fb;
3574         uint32_t latency = dev_priv->wm.skl_latency[level];
3575         uint32_t method1, method2;
3576         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3577         uint32_t res_blocks, res_lines;
3578         uint32_t selected_result;
3579         uint8_t cpp;
3580         uint32_t width = 0, height = 0;
3581         uint32_t plane_pixel_rate;
3582         uint32_t y_tile_minimum, y_min_scanlines;
3583         struct intel_atomic_state *state =
3584                 to_intel_atomic_state(cstate->base.state);
3585         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
3586
3587         if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3588                 *enabled = false;
3589                 return 0;
3590         }
3591
3592         if (apply_memory_bw_wa && fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3593                 latency += 15;
3594
3595         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3596         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3597
3598         if (drm_rotation_90_or_270(pstate->rotation))
3599                 swap(width, height);
3600
3601         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3602         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3603
3604         if (drm_rotation_90_or_270(pstate->rotation)) {
3605                 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3606                         drm_format_plane_cpp(fb->pixel_format, 1) :
3607                         drm_format_plane_cpp(fb->pixel_format, 0);
3608
3609                 switch (cpp) {
3610                 case 1:
3611                         y_min_scanlines = 16;
3612                         break;
3613                 case 2:
3614                         y_min_scanlines = 8;
3615                         break;
3616                 case 4:
3617                         y_min_scanlines = 4;
3618                         break;
3619                 default:
3620                         MISSING_CASE(cpp);
3621                         return -EINVAL;
3622                 }
3623         } else {
3624                 y_min_scanlines = 4;
3625         }
3626
3627         plane_bytes_per_line = width * cpp;
3628         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3629             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3630                 plane_blocks_per_line =
3631                       DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3632                 plane_blocks_per_line /= y_min_scanlines;
3633         } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3634                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3635                                         + 1;
3636         } else {
3637                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3638         }
3639
3640         method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3641         method2 = skl_wm_method2(plane_pixel_rate,
3642                                  cstate->base.adjusted_mode.crtc_htotal,
3643                                  latency,
3644                                  plane_blocks_per_line);
3645
3646         y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3647         if (apply_memory_bw_wa)
3648                 y_tile_minimum *= 2;
3649
3650         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3651             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3652                 selected_result = max(method2, y_tile_minimum);
3653         } else {
3654                 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3655                     (plane_bytes_per_line / 512 < 1))
3656                         selected_result = method2;
3657                 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
3658                         selected_result = min(method1, method2);
3659                 else
3660                         selected_result = method1;
3661         }
3662
3663         res_blocks = selected_result + 1;
3664         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3665
3666         if (level >= 1 && level <= 7) {
3667                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3668                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3669                         res_blocks += y_tile_minimum;
3670                         res_lines += y_min_scanlines;
3671                 } else {
3672                         res_blocks++;
3673                 }
3674         }
3675
3676         if (res_blocks >= ddb_allocation || res_lines > 31) {
3677                 *enabled = false;
3678
3679                 /*
3680                  * If there are no valid level 0 watermarks, then we can't
3681                  * support this display configuration.
3682                  */
3683                 if (level) {
3684                         return 0;
3685                 } else {
3686                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3687                         DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3688                                       to_intel_crtc(cstate->base.crtc)->pipe,
3689                                       skl_wm_plane_id(to_intel_plane(pstate->plane)),
3690                                       res_blocks, ddb_allocation, res_lines);
3691
3692                         return -EINVAL;
3693                 }
3694         }
3695
3696         *out_blocks = res_blocks;
3697         *out_lines = res_lines;
3698         *enabled = true;
3699
3700         return 0;
3701 }
3702
3703 static int
3704 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3705                      struct skl_ddb_allocation *ddb,
3706                      struct intel_crtc_state *cstate,
3707                      struct intel_plane *intel_plane,
3708                      int level,
3709                      struct skl_wm_level *result)
3710 {
3711         struct drm_atomic_state *state = cstate->base.state;
3712         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3713         struct drm_plane *plane = &intel_plane->base;
3714         struct intel_plane_state *intel_pstate = NULL;
3715         uint16_t ddb_blocks;
3716         enum pipe pipe = intel_crtc->pipe;
3717         int ret;
3718         int i = skl_wm_plane_id(intel_plane);
3719
3720         if (state)
3721                 intel_pstate =
3722                         intel_atomic_get_existing_plane_state(state,
3723                                                               intel_plane);
3724
3725         /*
3726          * Note: If we start supporting multiple pending atomic commits against
3727          * the same planes/CRTC's in the future, plane->state will no longer be
3728          * the correct pre-state to use for the calculations here and we'll
3729          * need to change where we get the 'unchanged' plane data from.
3730          *
3731          * For now this is fine because we only allow one queued commit against
3732          * a CRTC.  Even if the plane isn't modified by this transaction and we
3733          * don't have a plane lock, we still have the CRTC's lock, so we know
3734          * that no other transactions are racing with us to update it.
3735          */
3736         if (!intel_pstate)
3737                 intel_pstate = to_intel_plane_state(plane->state);
3738
3739         WARN_ON(!intel_pstate->base.fb);
3740
3741         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3742
3743         ret = skl_compute_plane_wm(dev_priv,
3744                                    cstate,
3745                                    intel_pstate,
3746                                    ddb_blocks,
3747                                    level,
3748                                    &result->plane_res_b,
3749                                    &result->plane_res_l,
3750                                    &result->plane_en);
3751         if (ret)
3752                 return ret;
3753
3754         return 0;
3755 }
3756
3757 static uint32_t
3758 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3759 {
3760         uint32_t pixel_rate;
3761
3762         if (!cstate->base.active)
3763                 return 0;
3764
3765         pixel_rate = ilk_pipe_pixel_rate(cstate);
3766
3767         if (WARN_ON(pixel_rate == 0))
3768                 return 0;
3769
3770         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3771                             pixel_rate);
3772 }
3773
3774 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3775                                       struct skl_wm_level *trans_wm /* out */)
3776 {
3777         if (!cstate->base.active)
3778                 return;
3779
3780         /* Until we know more, just disable transition WMs */
3781         trans_wm->plane_en = false;
3782 }
3783
3784 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3785                              struct skl_ddb_allocation *ddb,
3786                              struct skl_pipe_wm *pipe_wm)
3787 {
3788         struct drm_device *dev = cstate->base.crtc->dev;
3789         const struct drm_i915_private *dev_priv = to_i915(dev);
3790         struct intel_plane *intel_plane;
3791         struct skl_plane_wm *wm;
3792         int level, max_level = ilk_wm_max_level(dev_priv);
3793         int ret;
3794
3795         /*
3796          * We'll only calculate watermarks for planes that are actually
3797          * enabled, so make sure all other planes are set as disabled.
3798          */
3799         memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3800
3801         for_each_intel_plane_mask(&dev_priv->drm,
3802                                   intel_plane,
3803                                   cstate->base.plane_mask) {
3804                 wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
3805
3806                 for (level = 0; level <= max_level; level++) {
3807                         ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3808                                                    intel_plane, level,
3809                                                    &wm->wm[level]);
3810                         if (ret)
3811                                 return ret;
3812                 }
3813                 skl_compute_transition_wm(cstate, &wm->trans_wm);
3814         }
3815         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3816
3817         return 0;
3818 }
3819
3820 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3821                                 i915_reg_t reg,
3822                                 const struct skl_ddb_entry *entry)
3823 {
3824         if (entry->end)
3825                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3826         else
3827                 I915_WRITE(reg, 0);
3828 }
3829
3830 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3831                                i915_reg_t reg,
3832                                const struct skl_wm_level *level)
3833 {
3834         uint32_t val = 0;
3835
3836         if (level->plane_en) {
3837                 val |= PLANE_WM_EN;
3838                 val |= level->plane_res_b;
3839                 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3840         }
3841
3842         I915_WRITE(reg, val);
3843 }
3844
3845 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3846                         const struct skl_plane_wm *wm,
3847                         const struct skl_ddb_allocation *ddb,
3848                         int plane)
3849 {
3850         struct drm_crtc *crtc = &intel_crtc->base;
3851         struct drm_device *dev = crtc->dev;
3852         struct drm_i915_private *dev_priv = to_i915(dev);
3853         int level, max_level = ilk_wm_max_level(dev_priv);
3854         enum pipe pipe = intel_crtc->pipe;
3855
3856         for (level = 0; level <= max_level; level++) {
3857                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane, level),
3858                                    &wm->wm[level]);
3859         }
3860         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
3861                            &wm->trans_wm);
3862
3863         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3864                             &ddb->plane[pipe][plane]);
3865         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3866                             &ddb->y_plane[pipe][plane]);
3867 }
3868
3869 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3870                          const struct skl_plane_wm *wm,
3871                          const struct skl_ddb_allocation *ddb)
3872 {
3873         struct drm_crtc *crtc = &intel_crtc->base;
3874         struct drm_device *dev = crtc->dev;
3875         struct drm_i915_private *dev_priv = to_i915(dev);
3876         int level, max_level = ilk_wm_max_level(dev_priv);
3877         enum pipe pipe = intel_crtc->pipe;
3878
3879         for (level = 0; level <= max_level; level++) {
3880                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3881                                    &wm->wm[level]);
3882         }
3883         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
3884
3885         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3886                             &ddb->plane[pipe][PLANE_CURSOR]);
3887 }
3888
3889 bool skl_wm_level_equals(const struct skl_wm_level *l1,
3890                          const struct skl_wm_level *l2)
3891 {
3892         if (l1->plane_en != l2->plane_en)
3893                 return false;
3894
3895         /* If both planes aren't enabled, the rest shouldn't matter */
3896         if (!l1->plane_en)
3897                 return true;
3898
3899         return (l1->plane_res_l == l2->plane_res_l &&
3900                 l1->plane_res_b == l2->plane_res_b);
3901 }
3902
3903 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3904                                            const struct skl_ddb_entry *b)
3905 {
3906         return a->start < b->end && b->start < a->end;
3907 }
3908
3909 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
3910                                  struct intel_crtc *intel_crtc)
3911 {
3912         struct drm_crtc *other_crtc;
3913         struct drm_crtc_state *other_cstate;
3914         struct intel_crtc *other_intel_crtc;
3915         const struct skl_ddb_entry *ddb =
3916                 &to_intel_crtc_state(intel_crtc->base.state)->wm.skl.ddb;
3917         int i;
3918
3919         for_each_crtc_in_state(state, other_crtc, other_cstate, i) {
3920                 other_intel_crtc = to_intel_crtc(other_crtc);
3921
3922                 if (other_intel_crtc == intel_crtc)
3923                         continue;
3924
3925                 if (skl_ddb_entries_overlap(ddb, &other_intel_crtc->hw_ddb))
3926                         return true;
3927         }
3928
3929         return false;
3930 }
3931
3932 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3933                               const struct skl_pipe_wm *old_pipe_wm,
3934                               struct skl_pipe_wm *pipe_wm, /* out */
3935                               struct skl_ddb_allocation *ddb, /* out */
3936                               bool *changed /* out */)
3937 {
3938         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3939         int ret;
3940
3941         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3942         if (ret)
3943                 return ret;
3944
3945         if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
3946                 *changed = false;
3947         else
3948                 *changed = true;
3949
3950         return 0;
3951 }
3952
3953 static uint32_t
3954 pipes_modified(struct drm_atomic_state *state)
3955 {
3956         struct drm_crtc *crtc;
3957         struct drm_crtc_state *cstate;
3958         uint32_t i, ret = 0;
3959
3960         for_each_crtc_in_state(state, crtc, cstate, i)
3961                 ret |= drm_crtc_mask(crtc);
3962
3963         return ret;
3964 }
3965
3966 static int
3967 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3968 {
3969         struct drm_atomic_state *state = cstate->base.state;
3970         struct drm_device *dev = state->dev;
3971         struct drm_crtc *crtc = cstate->base.crtc;
3972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3973         struct drm_i915_private *dev_priv = to_i915(dev);
3974         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3975         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3976         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3977         struct drm_plane_state *plane_state;
3978         struct drm_plane *plane;
3979         enum pipe pipe = intel_crtc->pipe;
3980         int id;
3981
3982         WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3983
3984         drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
3985                 id = skl_wm_plane_id(to_intel_plane(plane));
3986
3987                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3988                                         &new_ddb->plane[pipe][id]) &&
3989                     skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3990                                         &new_ddb->y_plane[pipe][id]))
3991                         continue;
3992
3993                 plane_state = drm_atomic_get_plane_state(state, plane);
3994                 if (IS_ERR(plane_state))
3995                         return PTR_ERR(plane_state);
3996         }
3997
3998         return 0;
3999 }
4000
4001 static int
4002 skl_compute_ddb(struct drm_atomic_state *state)
4003 {
4004         struct drm_device *dev = state->dev;
4005         struct drm_i915_private *dev_priv = to_i915(dev);
4006         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4007         struct intel_crtc *intel_crtc;
4008         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4009         uint32_t realloc_pipes = pipes_modified(state);
4010         int ret;
4011
4012         /*
4013          * If this is our first atomic update following hardware readout,
4014          * we can't trust the DDB that the BIOS programmed for us.  Let's
4015          * pretend that all pipes switched active status so that we'll
4016          * ensure a full DDB recompute.
4017          */
4018         if (dev_priv->wm.distrust_bios_wm) {
4019                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4020                                        state->acquire_ctx);
4021                 if (ret)
4022                         return ret;
4023
4024                 intel_state->active_pipe_changes = ~0;
4025
4026                 /*
4027                  * We usually only initialize intel_state->active_crtcs if we
4028                  * we're doing a modeset; make sure this field is always
4029                  * initialized during the sanitization process that happens
4030                  * on the first commit too.
4031                  */
4032                 if (!intel_state->modeset)
4033                         intel_state->active_crtcs = dev_priv->active_crtcs;
4034         }
4035
4036         /*
4037          * If the modeset changes which CRTC's are active, we need to
4038          * recompute the DDB allocation for *all* active pipes, even
4039          * those that weren't otherwise being modified in any way by this
4040          * atomic commit.  Due to the shrinking of the per-pipe allocations
4041          * when new active CRTC's are added, it's possible for a pipe that
4042          * we were already using and aren't changing at all here to suddenly
4043          * become invalid if its DDB needs exceeds its new allocation.
4044          *
4045          * Note that if we wind up doing a full DDB recompute, we can't let
4046          * any other display updates race with this transaction, so we need
4047          * to grab the lock on *all* CRTC's.
4048          */
4049         if (intel_state->active_pipe_changes) {
4050                 realloc_pipes = ~0;
4051                 intel_state->wm_results.dirty_pipes = ~0;
4052         }
4053
4054         /*
4055          * We're not recomputing for the pipes not included in the commit, so
4056          * make sure we start with the current state.
4057          */
4058         memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4059
4060         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4061                 struct intel_crtc_state *cstate;
4062
4063                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4064                 if (IS_ERR(cstate))
4065                         return PTR_ERR(cstate);
4066
4067                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4068                 if (ret)
4069                         return ret;
4070
4071                 ret = skl_ddb_add_affected_planes(cstate);
4072                 if (ret)
4073                         return ret;
4074         }
4075
4076         return 0;
4077 }
4078
4079 static void
4080 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4081                      struct skl_wm_values *src,
4082                      enum pipe pipe)
4083 {
4084         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4085                sizeof(dst->ddb.y_plane[pipe]));
4086         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4087                sizeof(dst->ddb.plane[pipe]));
4088 }
4089
4090 static void
4091 skl_print_wm_changes(const struct drm_atomic_state *state)
4092 {
4093         const struct drm_device *dev = state->dev;
4094         const struct drm_i915_private *dev_priv = to_i915(dev);
4095         const struct intel_atomic_state *intel_state =
4096                 to_intel_atomic_state(state);
4097         const struct drm_crtc *crtc;
4098         const struct drm_crtc_state *cstate;
4099         const struct intel_plane *intel_plane;
4100         const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4101         const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4102         int id;
4103         int i;
4104
4105         for_each_crtc_in_state(state, crtc, cstate, i) {
4106                 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4107                 enum pipe pipe = intel_crtc->pipe;
4108
4109                 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4110                         const struct skl_ddb_entry *old, *new;
4111
4112                         id = skl_wm_plane_id(intel_plane);
4113                         old = &old_ddb->plane[pipe][id];
4114                         new = &new_ddb->plane[pipe][id];
4115
4116                         if (skl_ddb_entry_equal(old, new))
4117                                 continue;
4118
4119                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4120                                          intel_plane->base.base.id,
4121                                          intel_plane->base.name,
4122                                          old->start, old->end,
4123                                          new->start, new->end);
4124                 }
4125         }
4126 }
4127
4128 static int
4129 skl_compute_wm(struct drm_atomic_state *state)
4130 {
4131         struct drm_crtc *crtc;
4132         struct drm_crtc_state *cstate;
4133         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4134         struct skl_wm_values *results = &intel_state->wm_results;
4135         struct skl_pipe_wm *pipe_wm;
4136         bool changed = false;
4137         int ret, i;
4138
4139         /*
4140          * If this transaction isn't actually touching any CRTC's, don't
4141          * bother with watermark calculation.  Note that if we pass this
4142          * test, we're guaranteed to hold at least one CRTC state mutex,
4143          * which means we can safely use values like dev_priv->active_crtcs
4144          * since any racing commits that want to update them would need to
4145          * hold _all_ CRTC state mutexes.
4146          */
4147         for_each_crtc_in_state(state, crtc, cstate, i)
4148                 changed = true;
4149         if (!changed)
4150                 return 0;
4151
4152         /* Clear all dirty flags */
4153         results->dirty_pipes = 0;
4154
4155         ret = skl_compute_ddb(state);
4156         if (ret)
4157                 return ret;
4158
4159         /*
4160          * Calculate WM's for all pipes that are part of this transaction.
4161          * Note that the DDB allocation above may have added more CRTC's that
4162          * weren't otherwise being modified (and set bits in dirty_pipes) if
4163          * pipe allocations had to change.
4164          *
4165          * FIXME:  Now that we're doing this in the atomic check phase, we
4166          * should allow skl_update_pipe_wm() to return failure in cases where
4167          * no suitable watermark values can be found.
4168          */
4169         for_each_crtc_in_state(state, crtc, cstate, i) {
4170                 struct intel_crtc_state *intel_cstate =
4171                         to_intel_crtc_state(cstate);
4172                 const struct skl_pipe_wm *old_pipe_wm =
4173                         &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
4174
4175                 pipe_wm = &intel_cstate->wm.skl.optimal;
4176                 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4177                                          &results->ddb, &changed);
4178                 if (ret)
4179                         return ret;
4180
4181                 if (changed)
4182                         results->dirty_pipes |= drm_crtc_mask(crtc);
4183
4184                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4185                         /* This pipe's WM's did not change */
4186                         continue;
4187
4188                 intel_cstate->update_wm_pre = true;
4189         }
4190
4191         skl_print_wm_changes(state);
4192
4193         return 0;
4194 }
4195
4196 static void skl_update_wm(struct intel_crtc *intel_crtc)
4197 {
4198         struct drm_device *dev = intel_crtc->base.dev;
4199         struct drm_i915_private *dev_priv = to_i915(dev);
4200         struct skl_wm_values *results = &dev_priv->wm.skl_results;
4201         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4202         struct intel_crtc_state *cstate = to_intel_crtc_state(intel_crtc->base.state);
4203         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4204         enum pipe pipe = intel_crtc->pipe;
4205
4206         if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
4207                 return;
4208
4209         mutex_lock(&dev_priv->wm.wm_mutex);
4210
4211         /*
4212          * If this pipe isn't active already, we're going to be enabling it
4213          * very soon. Since it's safe to update a pipe's ddb allocation while
4214          * the pipe's shut off, just do so here. Already active pipes will have
4215          * their watermarks updated once we update their planes.
4216          */
4217         if (intel_crtc->base.state->active_changed) {
4218                 int plane;
4219
4220                 for_each_universal_plane(dev_priv, pipe, plane)
4221                         skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane],
4222                                            &results->ddb, plane);
4223
4224                 skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[PLANE_CURSOR],
4225                                     &results->ddb);
4226         }
4227
4228         skl_copy_wm_for_pipe(hw_vals, results, pipe);
4229
4230         intel_crtc->hw_ddb = cstate->wm.skl.ddb;
4231
4232         mutex_unlock(&dev_priv->wm.wm_mutex);
4233 }
4234
4235 static void ilk_compute_wm_config(struct drm_device *dev,
4236                                   struct intel_wm_config *config)
4237 {
4238         struct intel_crtc *crtc;
4239
4240         /* Compute the currently _active_ config */
4241         for_each_intel_crtc(dev, crtc) {
4242                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4243
4244                 if (!wm->pipe_enabled)
4245                         continue;
4246
4247                 config->sprites_enabled |= wm->sprites_enabled;
4248                 config->sprites_scaled |= wm->sprites_scaled;
4249                 config->num_pipes_active++;
4250         }
4251 }
4252
4253 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4254 {
4255         struct drm_device *dev = &dev_priv->drm;
4256         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4257         struct ilk_wm_maximums max;
4258         struct intel_wm_config config = {};
4259         struct ilk_wm_values results = {};
4260         enum intel_ddb_partitioning partitioning;
4261
4262         ilk_compute_wm_config(dev, &config);
4263
4264         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4265         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4266
4267         /* 5/6 split only in single pipe config on IVB+ */
4268         if (INTEL_INFO(dev)->gen >= 7 &&
4269             config.num_pipes_active == 1 && config.sprites_enabled) {
4270                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4271                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4272
4273                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4274         } else {
4275                 best_lp_wm = &lp_wm_1_2;
4276         }
4277
4278         partitioning = (best_lp_wm == &lp_wm_1_2) ?
4279                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4280
4281         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4282
4283         ilk_write_wm_values(dev_priv, &results);
4284 }
4285
4286 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
4287 {
4288         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4289         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4290
4291         mutex_lock(&dev_priv->wm.wm_mutex);
4292         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4293         ilk_program_watermarks(dev_priv);
4294         mutex_unlock(&dev_priv->wm.wm_mutex);
4295 }
4296
4297 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4298 {
4299         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4300         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4301
4302         mutex_lock(&dev_priv->wm.wm_mutex);
4303         if (cstate->wm.need_postvbl_update) {
4304                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4305                 ilk_program_watermarks(dev_priv);
4306         }
4307         mutex_unlock(&dev_priv->wm.wm_mutex);
4308 }
4309
4310 static inline void skl_wm_level_from_reg_val(uint32_t val,
4311                                              struct skl_wm_level *level)
4312 {
4313         level->plane_en = val & PLANE_WM_EN;
4314         level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4315         level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4316                 PLANE_WM_LINES_MASK;
4317 }
4318
4319 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4320                               struct skl_pipe_wm *out)
4321 {
4322         struct drm_device *dev = crtc->dev;
4323         struct drm_i915_private *dev_priv = to_i915(dev);
4324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4325         struct intel_plane *intel_plane;
4326         struct skl_plane_wm *wm;
4327         enum pipe pipe = intel_crtc->pipe;
4328         int level, id, max_level;
4329         uint32_t val;
4330
4331         max_level = ilk_wm_max_level(dev_priv);
4332
4333         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4334                 id = skl_wm_plane_id(intel_plane);
4335                 wm = &out->planes[id];
4336
4337                 for (level = 0; level <= max_level; level++) {
4338                         if (id != PLANE_CURSOR)
4339                                 val = I915_READ(PLANE_WM(pipe, id, level));
4340                         else
4341                                 val = I915_READ(CUR_WM(pipe, level));
4342
4343                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
4344                 }
4345
4346                 if (id != PLANE_CURSOR)
4347                         val = I915_READ(PLANE_WM_TRANS(pipe, id));
4348                 else
4349                         val = I915_READ(CUR_WM_TRANS(pipe));
4350
4351                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
4352         }
4353
4354         if (!intel_crtc->active)
4355                 return;
4356
4357         out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
4358 }
4359
4360 void skl_wm_get_hw_state(struct drm_device *dev)
4361 {
4362         struct drm_i915_private *dev_priv = to_i915(dev);
4363         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4364         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4365         struct drm_crtc *crtc;
4366         struct intel_crtc *intel_crtc;
4367         struct intel_crtc_state *cstate;
4368
4369         skl_ddb_get_hw_state(dev_priv, ddb);
4370         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4371                 intel_crtc = to_intel_crtc(crtc);
4372                 cstate = to_intel_crtc_state(crtc->state);
4373
4374                 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4375
4376                 if (intel_crtc->active)
4377                         hw->dirty_pipes |= drm_crtc_mask(crtc);
4378         }
4379
4380         if (dev_priv->active_crtcs) {
4381                 /* Fully recompute DDB on first atomic commit */
4382                 dev_priv->wm.distrust_bios_wm = true;
4383         } else {
4384                 /* Easy/common case; just sanitize DDB now if everything off */
4385                 memset(ddb, 0, sizeof(*ddb));
4386         }
4387 }
4388
4389 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4390 {
4391         struct drm_device *dev = crtc->dev;
4392         struct drm_i915_private *dev_priv = to_i915(dev);
4393         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4395         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4396         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4397         enum pipe pipe = intel_crtc->pipe;
4398         static const i915_reg_t wm0_pipe_reg[] = {
4399                 [PIPE_A] = WM0_PIPEA_ILK,
4400                 [PIPE_B] = WM0_PIPEB_ILK,
4401                 [PIPE_C] = WM0_PIPEC_IVB,
4402         };
4403
4404         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4405         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4406                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4407
4408         memset(active, 0, sizeof(*active));
4409
4410         active->pipe_enabled = intel_crtc->active;
4411
4412         if (active->pipe_enabled) {
4413                 u32 tmp = hw->wm_pipe[pipe];
4414
4415                 /*
4416                  * For active pipes LP0 watermark is marked as
4417                  * enabled, and LP1+ watermaks as disabled since
4418                  * we can't really reverse compute them in case
4419                  * multiple pipes are active.
4420                  */
4421                 active->wm[0].enable = true;
4422                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4423                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4424                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4425                 active->linetime = hw->wm_linetime[pipe];
4426         } else {
4427                 int level, max_level = ilk_wm_max_level(dev_priv);
4428
4429                 /*
4430                  * For inactive pipes, all watermark levels
4431                  * should be marked as enabled but zeroed,
4432                  * which is what we'd compute them to.
4433                  */
4434                 for (level = 0; level <= max_level; level++)
4435                         active->wm[level].enable = true;
4436         }
4437
4438         intel_crtc->wm.active.ilk = *active;
4439 }
4440
4441 #define _FW_WM(value, plane) \
4442         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4443 #define _FW_WM_VLV(value, plane) \
4444         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4445
4446 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4447                                struct vlv_wm_values *wm)
4448 {
4449         enum pipe pipe;
4450         uint32_t tmp;
4451
4452         for_each_pipe(dev_priv, pipe) {
4453                 tmp = I915_READ(VLV_DDL(pipe));
4454
4455                 wm->ddl[pipe].primary =
4456                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4457                 wm->ddl[pipe].cursor =
4458                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4459                 wm->ddl[pipe].sprite[0] =
4460                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4461                 wm->ddl[pipe].sprite[1] =
4462                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4463         }
4464
4465         tmp = I915_READ(DSPFW1);
4466         wm->sr.plane = _FW_WM(tmp, SR);
4467         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4468         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4469         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4470
4471         tmp = I915_READ(DSPFW2);
4472         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4473         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4474         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4475
4476         tmp = I915_READ(DSPFW3);
4477         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4478
4479         if (IS_CHERRYVIEW(dev_priv)) {
4480                 tmp = I915_READ(DSPFW7_CHV);
4481                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4482                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4483
4484                 tmp = I915_READ(DSPFW8_CHV);
4485                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4486                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4487
4488                 tmp = I915_READ(DSPFW9_CHV);
4489                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4490                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4491
4492                 tmp = I915_READ(DSPHOWM);
4493                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4494                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4495                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4496                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4497                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4498                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4499                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4500                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4501                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4502                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4503         } else {
4504                 tmp = I915_READ(DSPFW7);
4505                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4506                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4507
4508                 tmp = I915_READ(DSPHOWM);
4509                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4510                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4511                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4512                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4513                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4514                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4515                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4516         }
4517 }
4518
4519 #undef _FW_WM
4520 #undef _FW_WM_VLV
4521
4522 void vlv_wm_get_hw_state(struct drm_device *dev)
4523 {
4524         struct drm_i915_private *dev_priv = to_i915(dev);
4525         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4526         struct intel_plane *plane;
4527         enum pipe pipe;
4528         u32 val;
4529
4530         vlv_read_wm_values(dev_priv, wm);
4531
4532         for_each_intel_plane(dev, plane) {
4533                 switch (plane->base.type) {
4534                         int sprite;
4535                 case DRM_PLANE_TYPE_CURSOR:
4536                         plane->wm.fifo_size = 63;
4537                         break;
4538                 case DRM_PLANE_TYPE_PRIMARY:
4539                         plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, 0);
4540                         break;
4541                 case DRM_PLANE_TYPE_OVERLAY:
4542                         sprite = plane->plane;
4543                         plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, sprite + 1);
4544                         break;
4545                 }
4546         }
4547
4548         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4549         wm->level = VLV_WM_LEVEL_PM2;
4550
4551         if (IS_CHERRYVIEW(dev_priv)) {
4552                 mutex_lock(&dev_priv->rps.hw_lock);
4553
4554                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4555                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4556                         wm->level = VLV_WM_LEVEL_PM5;
4557
4558                 /*
4559                  * If DDR DVFS is disabled in the BIOS, Punit
4560                  * will never ack the request. So if that happens
4561                  * assume we don't have to enable/disable DDR DVFS
4562                  * dynamically. To test that just set the REQ_ACK
4563                  * bit to poke the Punit, but don't change the
4564                  * HIGH/LOW bits so that we don't actually change
4565                  * the current state.
4566                  */
4567                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4568                 val |= FORCE_DDR_FREQ_REQ_ACK;
4569                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4570
4571                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4572                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4573                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4574                                       "assuming DDR DVFS is disabled\n");
4575                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4576                 } else {
4577                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4578                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4579                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4580                 }
4581
4582                 mutex_unlock(&dev_priv->rps.hw_lock);
4583         }
4584
4585         for_each_pipe(dev_priv, pipe)
4586                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4587                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4588                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4589
4590         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4591                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4592 }
4593
4594 void ilk_wm_get_hw_state(struct drm_device *dev)
4595 {
4596         struct drm_i915_private *dev_priv = to_i915(dev);
4597         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4598         struct drm_crtc *crtc;
4599
4600         for_each_crtc(dev, crtc)
4601                 ilk_pipe_wm_get_hw_state(crtc);
4602
4603         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4604         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4605         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4606
4607         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4608         if (INTEL_INFO(dev)->gen >= 7) {
4609                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4610                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4611         }
4612
4613         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4614                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4615                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4616         else if (IS_IVYBRIDGE(dev_priv))
4617                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4618                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4619
4620         hw->enable_fbc_wm =
4621                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4622 }
4623
4624 /**
4625  * intel_update_watermarks - update FIFO watermark values based on current modes
4626  *
4627  * Calculate watermark values for the various WM regs based on current mode
4628  * and plane configuration.
4629  *
4630  * There are several cases to deal with here:
4631  *   - normal (i.e. non-self-refresh)
4632  *   - self-refresh (SR) mode
4633  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4634  *   - lines are small relative to FIFO size (buffer can hold more than 2
4635  *     lines), so need to account for TLB latency
4636  *
4637  *   The normal calculation is:
4638  *     watermark = dotclock * bytes per pixel * latency
4639  *   where latency is platform & configuration dependent (we assume pessimal
4640  *   values here).
4641  *
4642  *   The SR calculation is:
4643  *     watermark = (trunc(latency/line time)+1) * surface width *
4644  *       bytes per pixel
4645  *   where
4646  *     line time = htotal / dotclock
4647  *     surface width = hdisplay for normal plane and 64 for cursor
4648  *   and latency is assumed to be high, as above.
4649  *
4650  * The final value programmed to the register should always be rounded up,
4651  * and include an extra 2 entries to account for clock crossings.
4652  *
4653  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4654  * to set the non-SR watermarks to 8.
4655  */
4656 void intel_update_watermarks(struct intel_crtc *crtc)
4657 {
4658         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4659
4660         if (dev_priv->display.update_wm)
4661                 dev_priv->display.update_wm(crtc);
4662 }
4663
4664 /*
4665  * Lock protecting IPS related data structures
4666  */
4667 DEFINE_SPINLOCK(mchdev_lock);
4668
4669 /* Global for IPS driver to get at the current i915 device. Protected by
4670  * mchdev_lock. */
4671 static struct drm_i915_private *i915_mch_dev;
4672
4673 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4674 {
4675         u16 rgvswctl;
4676
4677         assert_spin_locked(&mchdev_lock);
4678
4679         rgvswctl = I915_READ16(MEMSWCTL);
4680         if (rgvswctl & MEMCTL_CMD_STS) {
4681                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4682                 return false; /* still busy with another command */
4683         }
4684
4685         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4686                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4687         I915_WRITE16(MEMSWCTL, rgvswctl);
4688         POSTING_READ16(MEMSWCTL);
4689
4690         rgvswctl |= MEMCTL_CMD_STS;
4691         I915_WRITE16(MEMSWCTL, rgvswctl);
4692
4693         return true;
4694 }
4695
4696 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4697 {
4698         u32 rgvmodectl;
4699         u8 fmax, fmin, fstart, vstart;
4700
4701         spin_lock_irq(&mchdev_lock);
4702
4703         rgvmodectl = I915_READ(MEMMODECTL);
4704
4705         /* Enable temp reporting */
4706         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4707         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4708
4709         /* 100ms RC evaluation intervals */
4710         I915_WRITE(RCUPEI, 100000);
4711         I915_WRITE(RCDNEI, 100000);
4712
4713         /* Set max/min thresholds to 90ms and 80ms respectively */
4714         I915_WRITE(RCBMAXAVG, 90000);
4715         I915_WRITE(RCBMINAVG, 80000);
4716
4717         I915_WRITE(MEMIHYST, 1);
4718
4719         /* Set up min, max, and cur for interrupt handling */
4720         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4721         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4722         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4723                 MEMMODE_FSTART_SHIFT;
4724
4725         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4726                 PXVFREQ_PX_SHIFT;
4727
4728         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4729         dev_priv->ips.fstart = fstart;
4730
4731         dev_priv->ips.max_delay = fstart;
4732         dev_priv->ips.min_delay = fmin;
4733         dev_priv->ips.cur_delay = fstart;
4734
4735         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4736                          fmax, fmin, fstart);
4737
4738         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4739
4740         /*
4741          * Interrupts will be enabled in ironlake_irq_postinstall
4742          */
4743
4744         I915_WRITE(VIDSTART, vstart);
4745         POSTING_READ(VIDSTART);
4746
4747         rgvmodectl |= MEMMODE_SWMODE_EN;
4748         I915_WRITE(MEMMODECTL, rgvmodectl);
4749
4750         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4751                 DRM_ERROR("stuck trying to change perf mode\n");
4752         mdelay(1);
4753
4754         ironlake_set_drps(dev_priv, fstart);
4755
4756         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4757                 I915_READ(DDREC) + I915_READ(CSIEC);
4758         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4759         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4760         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4761
4762         spin_unlock_irq(&mchdev_lock);
4763 }
4764
4765 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4766 {
4767         u16 rgvswctl;
4768
4769         spin_lock_irq(&mchdev_lock);
4770
4771         rgvswctl = I915_READ16(MEMSWCTL);
4772
4773         /* Ack interrupts, disable EFC interrupt */
4774         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4775         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4776         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4777         I915_WRITE(DEIIR, DE_PCU_EVENT);
4778         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4779
4780         /* Go back to the starting frequency */
4781         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4782         mdelay(1);
4783         rgvswctl |= MEMCTL_CMD_STS;
4784         I915_WRITE(MEMSWCTL, rgvswctl);
4785         mdelay(1);
4786
4787         spin_unlock_irq(&mchdev_lock);
4788 }
4789
4790 /* There's a funny hw issue where the hw returns all 0 when reading from
4791  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4792  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4793  * all limits and the gpu stuck at whatever frequency it is at atm).
4794  */
4795 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4796 {
4797         u32 limits;
4798
4799         /* Only set the down limit when we've reached the lowest level to avoid
4800          * getting more interrupts, otherwise leave this clear. This prevents a
4801          * race in the hw when coming out of rc6: There's a tiny window where
4802          * the hw runs at the minimal clock before selecting the desired
4803          * frequency, if the down threshold expires in that window we will not
4804          * receive a down interrupt. */
4805         if (IS_GEN9(dev_priv)) {
4806                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4807                 if (val <= dev_priv->rps.min_freq_softlimit)
4808                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4809         } else {
4810                 limits = dev_priv->rps.max_freq_softlimit << 24;
4811                 if (val <= dev_priv->rps.min_freq_softlimit)
4812                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4813         }
4814
4815         return limits;
4816 }
4817
4818 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4819 {
4820         int new_power;
4821         u32 threshold_up = 0, threshold_down = 0; /* in % */
4822         u32 ei_up = 0, ei_down = 0;
4823
4824         new_power = dev_priv->rps.power;
4825         switch (dev_priv->rps.power) {
4826         case LOW_POWER:
4827                 if (val > dev_priv->rps.efficient_freq + 1 &&
4828                     val > dev_priv->rps.cur_freq)
4829                         new_power = BETWEEN;
4830                 break;
4831
4832         case BETWEEN:
4833                 if (val <= dev_priv->rps.efficient_freq &&
4834                     val < dev_priv->rps.cur_freq)
4835                         new_power = LOW_POWER;
4836                 else if (val >= dev_priv->rps.rp0_freq &&
4837                          val > dev_priv->rps.cur_freq)
4838                         new_power = HIGH_POWER;
4839                 break;
4840
4841         case HIGH_POWER:
4842                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4843                     val < dev_priv->rps.cur_freq)
4844                         new_power = BETWEEN;
4845                 break;
4846         }
4847         /* Max/min bins are special */
4848         if (val <= dev_priv->rps.min_freq_softlimit)
4849                 new_power = LOW_POWER;
4850         if (val >= dev_priv->rps.max_freq_softlimit)
4851                 new_power = HIGH_POWER;
4852         if (new_power == dev_priv->rps.power)
4853                 return;
4854
4855         /* Note the units here are not exactly 1us, but 1280ns. */
4856         switch (new_power) {
4857         case LOW_POWER:
4858                 /* Upclock if more than 95% busy over 16ms */
4859                 ei_up = 16000;
4860                 threshold_up = 95;
4861
4862                 /* Downclock if less than 85% busy over 32ms */
4863                 ei_down = 32000;
4864                 threshold_down = 85;
4865                 break;
4866
4867         case BETWEEN:
4868                 /* Upclock if more than 90% busy over 13ms */
4869                 ei_up = 13000;
4870                 threshold_up = 90;
4871
4872                 /* Downclock if less than 75% busy over 32ms */
4873                 ei_down = 32000;
4874                 threshold_down = 75;
4875                 break;
4876
4877         case HIGH_POWER:
4878                 /* Upclock if more than 85% busy over 10ms */
4879                 ei_up = 10000;
4880                 threshold_up = 85;
4881
4882                 /* Downclock if less than 60% busy over 32ms */
4883                 ei_down = 32000;
4884                 threshold_down = 60;
4885                 break;
4886         }
4887
4888         I915_WRITE(GEN6_RP_UP_EI,
4889                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
4890         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4891                    GT_INTERVAL_FROM_US(dev_priv,
4892                                        ei_up * threshold_up / 100));
4893
4894         I915_WRITE(GEN6_RP_DOWN_EI,
4895                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
4896         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4897                    GT_INTERVAL_FROM_US(dev_priv,
4898                                        ei_down * threshold_down / 100));
4899
4900         I915_WRITE(GEN6_RP_CONTROL,
4901                    GEN6_RP_MEDIA_TURBO |
4902                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4903                    GEN6_RP_MEDIA_IS_GFX |
4904                    GEN6_RP_ENABLE |
4905                    GEN6_RP_UP_BUSY_AVG |
4906                    GEN6_RP_DOWN_IDLE_AVG);
4907
4908         dev_priv->rps.power = new_power;
4909         dev_priv->rps.up_threshold = threshold_up;
4910         dev_priv->rps.down_threshold = threshold_down;
4911         dev_priv->rps.last_adj = 0;
4912 }
4913
4914 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4915 {
4916         u32 mask = 0;
4917
4918         if (val > dev_priv->rps.min_freq_softlimit)
4919                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4920         if (val < dev_priv->rps.max_freq_softlimit)
4921                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4922
4923         mask &= dev_priv->pm_rps_events;
4924
4925         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4926 }
4927
4928 /* gen6_set_rps is called to update the frequency request, but should also be
4929  * called when the range (min_delay and max_delay) is modified so that we can
4930  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4931 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4932 {
4933         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4934         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4935                 return;
4936
4937         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4938         WARN_ON(val > dev_priv->rps.max_freq);
4939         WARN_ON(val < dev_priv->rps.min_freq);
4940
4941         /* min/max delay may still have been modified so be sure to
4942          * write the limits value.
4943          */
4944         if (val != dev_priv->rps.cur_freq) {
4945                 gen6_set_rps_thresholds(dev_priv, val);
4946
4947                 if (IS_GEN9(dev_priv))
4948                         I915_WRITE(GEN6_RPNSWREQ,
4949                                    GEN9_FREQUENCY(val));
4950                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4951                         I915_WRITE(GEN6_RPNSWREQ,
4952                                    HSW_FREQUENCY(val));
4953                 else
4954                         I915_WRITE(GEN6_RPNSWREQ,
4955                                    GEN6_FREQUENCY(val) |
4956                                    GEN6_OFFSET(0) |
4957                                    GEN6_AGGRESSIVE_TURBO);
4958         }
4959
4960         /* Make sure we continue to get interrupts
4961          * until we hit the minimum or maximum frequencies.
4962          */
4963         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4964         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4965
4966         POSTING_READ(GEN6_RPNSWREQ);
4967
4968         dev_priv->rps.cur_freq = val;
4969         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4970 }
4971
4972 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4973 {
4974         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4975         WARN_ON(val > dev_priv->rps.max_freq);
4976         WARN_ON(val < dev_priv->rps.min_freq);
4977
4978         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4979                       "Odd GPU freq value\n"))
4980                 val &= ~1;
4981
4982         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4983
4984         if (val != dev_priv->rps.cur_freq) {
4985                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4986                 if (!IS_CHERRYVIEW(dev_priv))
4987                         gen6_set_rps_thresholds(dev_priv, val);
4988         }
4989
4990         dev_priv->rps.cur_freq = val;
4991         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4992 }
4993
4994 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4995  *
4996  * * If Gfx is Idle, then
4997  * 1. Forcewake Media well.
4998  * 2. Request idle freq.
4999  * 3. Release Forcewake of Media well.
5000 */
5001 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5002 {
5003         u32 val = dev_priv->rps.idle_freq;
5004
5005         if (dev_priv->rps.cur_freq <= val)
5006                 return;
5007
5008         /* Wake up the media well, as that takes a lot less
5009          * power than the Render well. */
5010         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5011         valleyview_set_rps(dev_priv, val);
5012         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5013 }
5014
5015 void gen6_rps_busy(struct drm_i915_private *dev_priv)
5016 {
5017         mutex_lock(&dev_priv->rps.hw_lock);
5018         if (dev_priv->rps.enabled) {
5019                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5020                         gen6_rps_reset_ei(dev_priv);
5021                 I915_WRITE(GEN6_PMINTRMSK,
5022                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5023
5024                 gen6_enable_rps_interrupts(dev_priv);
5025
5026                 /* Ensure we start at the user's desired frequency */
5027                 intel_set_rps(dev_priv,
5028                               clamp(dev_priv->rps.cur_freq,
5029                                     dev_priv->rps.min_freq_softlimit,
5030                                     dev_priv->rps.max_freq_softlimit));
5031         }
5032         mutex_unlock(&dev_priv->rps.hw_lock);
5033 }
5034
5035 void gen6_rps_idle(struct drm_i915_private *dev_priv)
5036 {
5037         /* Flush our bottom-half so that it does not race with us
5038          * setting the idle frequency and so that it is bounded by
5039          * our rpm wakeref. And then disable the interrupts to stop any
5040          * futher RPS reclocking whilst we are asleep.
5041          */
5042         gen6_disable_rps_interrupts(dev_priv);
5043
5044         mutex_lock(&dev_priv->rps.hw_lock);
5045         if (dev_priv->rps.enabled) {
5046                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5047                         vlv_set_rps_idle(dev_priv);
5048                 else
5049                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5050                 dev_priv->rps.last_adj = 0;
5051                 I915_WRITE(GEN6_PMINTRMSK,
5052                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5053         }
5054         mutex_unlock(&dev_priv->rps.hw_lock);
5055
5056         spin_lock(&dev_priv->rps.client_lock);
5057         while (!list_empty(&dev_priv->rps.clients))
5058                 list_del_init(dev_priv->rps.clients.next);
5059         spin_unlock(&dev_priv->rps.client_lock);
5060 }
5061
5062 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5063                     struct intel_rps_client *rps,
5064                     unsigned long submitted)
5065 {
5066         /* This is intentionally racy! We peek at the state here, then
5067          * validate inside the RPS worker.
5068          */
5069         if (!(dev_priv->gt.awake &&
5070               dev_priv->rps.enabled &&
5071               dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5072                 return;
5073
5074         /* Force a RPS boost (and don't count it against the client) if
5075          * the GPU is severely congested.
5076          */
5077         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5078                 rps = NULL;
5079
5080         spin_lock(&dev_priv->rps.client_lock);
5081         if (rps == NULL || list_empty(&rps->link)) {
5082                 spin_lock_irq(&dev_priv->irq_lock);
5083                 if (dev_priv->rps.interrupts_enabled) {
5084                         dev_priv->rps.client_boost = true;
5085                         schedule_work(&dev_priv->rps.work);
5086                 }
5087                 spin_unlock_irq(&dev_priv->irq_lock);
5088
5089                 if (rps != NULL) {
5090                         list_add(&rps->link, &dev_priv->rps.clients);
5091                         rps->boosts++;
5092                 } else
5093                         dev_priv->rps.boosts++;
5094         }
5095         spin_unlock(&dev_priv->rps.client_lock);
5096 }
5097
5098 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5099 {
5100         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5101                 valleyview_set_rps(dev_priv, val);
5102         else
5103                 gen6_set_rps(dev_priv, val);
5104 }
5105
5106 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5107 {
5108         I915_WRITE(GEN6_RC_CONTROL, 0);
5109         I915_WRITE(GEN9_PG_ENABLE, 0);
5110 }
5111
5112 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5113 {
5114         I915_WRITE(GEN6_RP_CONTROL, 0);
5115 }
5116
5117 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5118 {
5119         I915_WRITE(GEN6_RC_CONTROL, 0);
5120         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5121         I915_WRITE(GEN6_RP_CONTROL, 0);
5122 }
5123
5124 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5125 {
5126         I915_WRITE(GEN6_RC_CONTROL, 0);
5127 }
5128
5129 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5130 {
5131         /* we're doing forcewake before Disabling RC6,
5132          * This what the BIOS expects when going into suspend */
5133         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5134
5135         I915_WRITE(GEN6_RC_CONTROL, 0);
5136
5137         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5138 }
5139
5140 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5141 {
5142         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5143                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5144                         mode = GEN6_RC_CTL_RC6_ENABLE;
5145                 else
5146                         mode = 0;
5147         }
5148         if (HAS_RC6p(dev_priv))
5149                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5150                                  "RC6 %s RC6p %s RC6pp %s\n",
5151                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5152                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5153                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5154
5155         else
5156                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5157                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5158 }
5159
5160 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5161 {
5162         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5163         bool enable_rc6 = true;
5164         unsigned long rc6_ctx_base;
5165         u32 rc_ctl;
5166         int rc_sw_target;
5167
5168         rc_ctl = I915_READ(GEN6_RC_CONTROL);
5169         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5170                        RC_SW_TARGET_STATE_SHIFT;
5171         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5172                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5173                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5174                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5175                          rc_sw_target);
5176
5177         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5178                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5179                 enable_rc6 = false;
5180         }
5181
5182         /*
5183          * The exact context size is not known for BXT, so assume a page size
5184          * for this check.
5185          */
5186         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5187         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5188               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5189                                         ggtt->stolen_reserved_size))) {
5190                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5191                 enable_rc6 = false;
5192         }
5193
5194         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5195               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5196               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5197               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5198                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5199                 enable_rc6 = false;
5200         }
5201
5202         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5203             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5204             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5205                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5206                 enable_rc6 = false;
5207         }
5208
5209         if (!I915_READ(GEN6_GFXPAUSE)) {
5210                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5211                 enable_rc6 = false;
5212         }
5213
5214         if (!I915_READ(GEN8_MISC_CTRL0)) {
5215                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5216                 enable_rc6 = false;
5217         }
5218
5219         return enable_rc6;
5220 }
5221
5222 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5223 {
5224         /* No RC6 before Ironlake and code is gone for ilk. */
5225         if (INTEL_INFO(dev_priv)->gen < 6)
5226                 return 0;
5227
5228         if (!enable_rc6)
5229                 return 0;
5230
5231         if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5232                 DRM_INFO("RC6 disabled by BIOS\n");
5233                 return 0;
5234         }
5235
5236         /* Respect the kernel parameter if it is set */
5237         if (enable_rc6 >= 0) {
5238                 int mask;
5239
5240                 if (HAS_RC6p(dev_priv))
5241                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5242                                INTEL_RC6pp_ENABLE;
5243                 else
5244                         mask = INTEL_RC6_ENABLE;
5245
5246                 if ((enable_rc6 & mask) != enable_rc6)
5247                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5248                                          "(requested %d, valid %d)\n",
5249                                          enable_rc6 & mask, enable_rc6, mask);
5250
5251                 return enable_rc6 & mask;
5252         }
5253
5254         if (IS_IVYBRIDGE(dev_priv))
5255                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5256
5257         return INTEL_RC6_ENABLE;
5258 }
5259
5260 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5261 {
5262         /* All of these values are in units of 50MHz */
5263
5264         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5265         if (IS_BROXTON(dev_priv)) {
5266                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5267                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5268                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5269                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
5270         } else {
5271                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5272                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
5273                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5274                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5275         }
5276         /* hw_max = RP0 until we check for overclocking */
5277         dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5278
5279         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5280         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5281             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5282                 u32 ddcc_status = 0;
5283
5284                 if (sandybridge_pcode_read(dev_priv,
5285                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5286                                            &ddcc_status) == 0)
5287                         dev_priv->rps.efficient_freq =
5288                                 clamp_t(u8,
5289                                         ((ddcc_status >> 8) & 0xff),
5290                                         dev_priv->rps.min_freq,
5291                                         dev_priv->rps.max_freq);
5292         }
5293
5294         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5295                 /* Store the frequency values in 16.66 MHZ units, which is
5296                  * the natural hardware unit for SKL
5297                  */
5298                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5299                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5300                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5301                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5302                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5303         }
5304 }
5305
5306 static void reset_rps(struct drm_i915_private *dev_priv,
5307                       void (*set)(struct drm_i915_private *, u8))
5308 {
5309         u8 freq = dev_priv->rps.cur_freq;
5310
5311         /* force a reset */
5312         dev_priv->rps.power = -1;
5313         dev_priv->rps.cur_freq = -1;
5314
5315         set(dev_priv, freq);
5316 }
5317
5318 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5319 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5320 {
5321         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5322
5323         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5324         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5325                 /*
5326                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
5327                  * clear out the Control register just to avoid inconsitency
5328                  * with debugfs interface, which will show  Turbo as enabled
5329                  * only and that is not expected by the User after adding the
5330                  * WaGsvDisableTurbo. Apart from this there is no problem even
5331                  * if the Turbo is left enabled in the Control register, as the
5332                  * Up/Down interrupts would remain masked.
5333                  */
5334                 gen9_disable_rps(dev_priv);
5335                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5336                 return;
5337         }
5338
5339         /* Program defaults and thresholds for RPS*/
5340         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5341                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5342
5343         /* 1 second timeout*/
5344         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5345                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5346
5347         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5348
5349         /* Leaning on the below call to gen6_set_rps to program/setup the
5350          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5351          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5352         reset_rps(dev_priv, gen6_set_rps);
5353
5354         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5355 }
5356
5357 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5358 {
5359         struct intel_engine_cs *engine;
5360         enum intel_engine_id id;
5361         uint32_t rc6_mask = 0;
5362
5363         /* 1a: Software RC state - RC0 */
5364         I915_WRITE(GEN6_RC_STATE, 0);
5365
5366         /* 1b: Get forcewake during program sequence. Although the driver
5367          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5368         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5369
5370         /* 2a: Disable RC states. */
5371         I915_WRITE(GEN6_RC_CONTROL, 0);
5372
5373         /* 2b: Program RC6 thresholds.*/
5374
5375         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5376         if (IS_SKYLAKE(dev_priv))
5377                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5378         else
5379                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5380         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5381         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5382         for_each_engine(engine, dev_priv, id)
5383                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5384
5385         if (HAS_GUC(dev_priv))
5386                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5387
5388         I915_WRITE(GEN6_RC_SLEEP, 0);
5389
5390         /* 2c: Program Coarse Power Gating Policies. */
5391         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5392         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5393
5394         /* 3a: Enable RC6 */
5395         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5396                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5397         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5398         /* WaRsUseTimeoutMode:bxt */
5399         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5400                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5401                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5402                            GEN7_RC_CTL_TO_MODE |
5403                            rc6_mask);
5404         } else {
5405                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5406                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5407                            GEN6_RC_CTL_EI_MODE(1) |
5408                            rc6_mask);
5409         }
5410
5411         /*
5412          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5413          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5414          */
5415         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5416                 I915_WRITE(GEN9_PG_ENABLE, 0);
5417         else
5418                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5419                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5420
5421         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5422 }
5423
5424 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5425 {
5426         struct intel_engine_cs *engine;
5427         enum intel_engine_id id;
5428         uint32_t rc6_mask = 0;
5429
5430         /* 1a: Software RC state - RC0 */
5431         I915_WRITE(GEN6_RC_STATE, 0);
5432
5433         /* 1c & 1d: Get forcewake during program sequence. Although the driver
5434          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5435         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5436
5437         /* 2a: Disable RC states. */
5438         I915_WRITE(GEN6_RC_CONTROL, 0);
5439
5440         /* 2b: Program RC6 thresholds.*/
5441         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5442         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5443         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5444         for_each_engine(engine, dev_priv, id)
5445                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5446         I915_WRITE(GEN6_RC_SLEEP, 0);
5447         if (IS_BROADWELL(dev_priv))
5448                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5449         else
5450                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5451
5452         /* 3: Enable RC6 */
5453         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5454                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5455         intel_print_rc6_info(dev_priv, rc6_mask);
5456         if (IS_BROADWELL(dev_priv))
5457                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5458                                 GEN7_RC_CTL_TO_MODE |
5459                                 rc6_mask);
5460         else
5461                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5462                                 GEN6_RC_CTL_EI_MODE(1) |
5463                                 rc6_mask);
5464
5465         /* 4 Program defaults and thresholds for RPS*/
5466         I915_WRITE(GEN6_RPNSWREQ,
5467                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5468         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5469                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5470         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5471         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5472
5473         /* Docs recommend 900MHz, and 300 MHz respectively */
5474         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5475                    dev_priv->rps.max_freq_softlimit << 24 |
5476                    dev_priv->rps.min_freq_softlimit << 16);
5477
5478         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5479         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5480         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5481         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5482
5483         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5484
5485         /* 5: Enable RPS */
5486         I915_WRITE(GEN6_RP_CONTROL,
5487                    GEN6_RP_MEDIA_TURBO |
5488                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5489                    GEN6_RP_MEDIA_IS_GFX |
5490                    GEN6_RP_ENABLE |
5491                    GEN6_RP_UP_BUSY_AVG |
5492                    GEN6_RP_DOWN_IDLE_AVG);
5493
5494         /* 6: Ring frequency + overclocking (our driver does this later */
5495
5496         reset_rps(dev_priv, gen6_set_rps);
5497
5498         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5499 }
5500
5501 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5502 {
5503         struct intel_engine_cs *engine;
5504         enum intel_engine_id id;
5505         u32 rc6vids, rc6_mask = 0;
5506         u32 gtfifodbg;
5507         int rc6_mode;
5508         int ret;
5509
5510         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5511
5512         /* Here begins a magic sequence of register writes to enable
5513          * auto-downclocking.
5514          *
5515          * Perhaps there might be some value in exposing these to
5516          * userspace...
5517          */
5518         I915_WRITE(GEN6_RC_STATE, 0);
5519
5520         /* Clear the DBG now so we don't confuse earlier errors */
5521         gtfifodbg = I915_READ(GTFIFODBG);
5522         if (gtfifodbg) {
5523                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5524                 I915_WRITE(GTFIFODBG, gtfifodbg);
5525         }
5526
5527         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5528
5529         /* disable the counters and set deterministic thresholds */
5530         I915_WRITE(GEN6_RC_CONTROL, 0);
5531
5532         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5533         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5534         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5535         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5536         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5537
5538         for_each_engine(engine, dev_priv, id)
5539                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5540
5541         I915_WRITE(GEN6_RC_SLEEP, 0);
5542         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5543         if (IS_IVYBRIDGE(dev_priv))
5544                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5545         else
5546                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5547         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5548         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5549
5550         /* Check if we are enabling RC6 */
5551         rc6_mode = intel_enable_rc6();
5552         if (rc6_mode & INTEL_RC6_ENABLE)
5553                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5554
5555         /* We don't use those on Haswell */
5556         if (!IS_HASWELL(dev_priv)) {
5557                 if (rc6_mode & INTEL_RC6p_ENABLE)
5558                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5559
5560                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5561                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5562         }
5563
5564         intel_print_rc6_info(dev_priv, rc6_mask);
5565
5566         I915_WRITE(GEN6_RC_CONTROL,
5567                    rc6_mask |
5568                    GEN6_RC_CTL_EI_MODE(1) |
5569                    GEN6_RC_CTL_HW_ENABLE);
5570
5571         /* Power down if completely idle for over 50ms */
5572         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5573         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5574
5575         reset_rps(dev_priv, gen6_set_rps);
5576
5577         rc6vids = 0;
5578         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5579         if (IS_GEN6(dev_priv) && ret) {
5580                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5581         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5582                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5583                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5584                 rc6vids &= 0xffff00;
5585                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5586                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5587                 if (ret)
5588                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5589         }
5590
5591         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5592 }
5593
5594 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5595 {
5596         int min_freq = 15;
5597         unsigned int gpu_freq;
5598         unsigned int max_ia_freq, min_ring_freq;
5599         unsigned int max_gpu_freq, min_gpu_freq;
5600         int scaling_factor = 180;
5601         struct cpufreq_policy *policy;
5602
5603         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5604
5605         policy = cpufreq_cpu_get(0);
5606         if (policy) {
5607                 max_ia_freq = policy->cpuinfo.max_freq;
5608                 cpufreq_cpu_put(policy);
5609         } else {
5610                 /*
5611                  * Default to measured freq if none found, PCU will ensure we
5612                  * don't go over
5613                  */
5614                 max_ia_freq = tsc_khz;
5615         }
5616
5617         /* Convert from kHz to MHz */
5618         max_ia_freq /= 1000;
5619
5620         min_ring_freq = I915_READ(DCLK) & 0xf;
5621         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5622         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5623
5624         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5625                 /* Convert GT frequency to 50 HZ units */
5626                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5627                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5628         } else {
5629                 min_gpu_freq = dev_priv->rps.min_freq;
5630                 max_gpu_freq = dev_priv->rps.max_freq;
5631         }
5632
5633         /*
5634          * For each potential GPU frequency, load a ring frequency we'd like
5635          * to use for memory access.  We do this by specifying the IA frequency
5636          * the PCU should use as a reference to determine the ring frequency.
5637          */
5638         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5639                 int diff = max_gpu_freq - gpu_freq;
5640                 unsigned int ia_freq = 0, ring_freq = 0;
5641
5642                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5643                         /*
5644                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5645                          * No floor required for ring frequency on SKL.
5646                          */
5647                         ring_freq = gpu_freq;
5648                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5649                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5650                         ring_freq = max(min_ring_freq, gpu_freq);
5651                 } else if (IS_HASWELL(dev_priv)) {
5652                         ring_freq = mult_frac(gpu_freq, 5, 4);
5653                         ring_freq = max(min_ring_freq, ring_freq);
5654                         /* leave ia_freq as the default, chosen by cpufreq */
5655                 } else {
5656                         /* On older processors, there is no separate ring
5657                          * clock domain, so in order to boost the bandwidth
5658                          * of the ring, we need to upclock the CPU (ia_freq).
5659                          *
5660                          * For GPU frequencies less than 750MHz,
5661                          * just use the lowest ring freq.
5662                          */
5663                         if (gpu_freq < min_freq)
5664                                 ia_freq = 800;
5665                         else
5666                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5667                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5668                 }
5669
5670                 sandybridge_pcode_write(dev_priv,
5671                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5672                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5673                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5674                                         gpu_freq);
5675         }
5676 }
5677
5678 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5679 {
5680         u32 val, rp0;
5681
5682         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5683
5684         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5685         case 8:
5686                 /* (2 * 4) config */
5687                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5688                 break;
5689         case 12:
5690                 /* (2 * 6) config */
5691                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5692                 break;
5693         case 16:
5694                 /* (2 * 8) config */
5695         default:
5696                 /* Setting (2 * 8) Min RP0 for any other combination */
5697                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5698                 break;
5699         }
5700
5701         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5702
5703         return rp0;
5704 }
5705
5706 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5707 {
5708         u32 val, rpe;
5709
5710         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5711         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5712
5713         return rpe;
5714 }
5715
5716 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5717 {
5718         u32 val, rp1;
5719
5720         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5721         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5722
5723         return rp1;
5724 }
5725
5726 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5727 {
5728         u32 val, rp1;
5729
5730         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5731
5732         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5733
5734         return rp1;
5735 }
5736
5737 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5738 {
5739         u32 val, rp0;
5740
5741         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5742
5743         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5744         /* Clamp to max */
5745         rp0 = min_t(u32, rp0, 0xea);
5746
5747         return rp0;
5748 }
5749
5750 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5751 {
5752         u32 val, rpe;
5753
5754         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5755         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5756         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5757         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5758
5759         return rpe;
5760 }
5761
5762 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5763 {
5764         u32 val;
5765
5766         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5767         /*
5768          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5769          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5770          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5771          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5772          * to make sure it matches what Punit accepts.
5773          */
5774         return max_t(u32, val, 0xc0);
5775 }
5776
5777 /* Check that the pctx buffer wasn't move under us. */
5778 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5779 {
5780         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5781
5782         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5783                              dev_priv->vlv_pctx->stolen->start);
5784 }
5785
5786
5787 /* Check that the pcbr address is not empty. */
5788 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5789 {
5790         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5791
5792         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5793 }
5794
5795 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5796 {
5797         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5798         unsigned long pctx_paddr, paddr;
5799         u32 pcbr;
5800         int pctx_size = 32*1024;
5801
5802         pcbr = I915_READ(VLV_PCBR);
5803         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5804                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5805                 paddr = (dev_priv->mm.stolen_base +
5806                          (ggtt->stolen_size - pctx_size));
5807
5808                 pctx_paddr = (paddr & (~4095));
5809                 I915_WRITE(VLV_PCBR, pctx_paddr);
5810         }
5811
5812         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5813 }
5814
5815 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5816 {
5817         struct drm_i915_gem_object *pctx;
5818         unsigned long pctx_paddr;
5819         u32 pcbr;
5820         int pctx_size = 24*1024;
5821
5822         pcbr = I915_READ(VLV_PCBR);
5823         if (pcbr) {
5824                 /* BIOS set it up already, grab the pre-alloc'd space */
5825                 int pcbr_offset;
5826
5827                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5828                 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
5829                                                                       pcbr_offset,
5830                                                                       I915_GTT_OFFSET_NONE,
5831                                                                       pctx_size);
5832                 goto out;
5833         }
5834
5835         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5836
5837         /*
5838          * From the Gunit register HAS:
5839          * The Gfx driver is expected to program this register and ensure
5840          * proper allocation within Gfx stolen memory.  For example, this
5841          * register should be programmed such than the PCBR range does not
5842          * overlap with other ranges, such as the frame buffer, protected
5843          * memory, or any other relevant ranges.
5844          */
5845         pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
5846         if (!pctx) {
5847                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5848                 goto out;
5849         }
5850
5851         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5852         I915_WRITE(VLV_PCBR, pctx_paddr);
5853
5854 out:
5855         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5856         dev_priv->vlv_pctx = pctx;
5857 }
5858
5859 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5860 {
5861         if (WARN_ON(!dev_priv->vlv_pctx))
5862                 return;
5863
5864         i915_gem_object_put(dev_priv->vlv_pctx);
5865         dev_priv->vlv_pctx = NULL;
5866 }
5867
5868 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5869 {
5870         dev_priv->rps.gpll_ref_freq =
5871                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5872                                   CCK_GPLL_CLOCK_CONTROL,
5873                                   dev_priv->czclk_freq);
5874
5875         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5876                          dev_priv->rps.gpll_ref_freq);
5877 }
5878
5879 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5880 {
5881         u32 val;
5882
5883         valleyview_setup_pctx(dev_priv);
5884
5885         vlv_init_gpll_ref_freq(dev_priv);
5886
5887         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5888         switch ((val >> 6) & 3) {
5889         case 0:
5890         case 1:
5891                 dev_priv->mem_freq = 800;
5892                 break;
5893         case 2:
5894                 dev_priv->mem_freq = 1066;
5895                 break;
5896         case 3:
5897                 dev_priv->mem_freq = 1333;
5898                 break;
5899         }
5900         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5901
5902         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5903         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5904         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5905                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5906                          dev_priv->rps.max_freq);
5907
5908         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5909         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5910                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5911                          dev_priv->rps.efficient_freq);
5912
5913         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5914         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5915                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5916                          dev_priv->rps.rp1_freq);
5917
5918         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5919         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5920                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5921                          dev_priv->rps.min_freq);
5922 }
5923
5924 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5925 {
5926         u32 val;
5927
5928         cherryview_setup_pctx(dev_priv);
5929
5930         vlv_init_gpll_ref_freq(dev_priv);
5931
5932         mutex_lock(&dev_priv->sb_lock);
5933         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5934         mutex_unlock(&dev_priv->sb_lock);
5935
5936         switch ((val >> 2) & 0x7) {
5937         case 3:
5938                 dev_priv->mem_freq = 2000;
5939                 break;
5940         default:
5941                 dev_priv->mem_freq = 1600;
5942                 break;
5943         }
5944         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5945
5946         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5947         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5948         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5949                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5950                          dev_priv->rps.max_freq);
5951
5952         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5953         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5954                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5955                          dev_priv->rps.efficient_freq);
5956
5957         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5958         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5959                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5960                          dev_priv->rps.rp1_freq);
5961
5962         /* PUnit validated range is only [RPe, RP0] */
5963         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5964         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5965                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5966                          dev_priv->rps.min_freq);
5967
5968         WARN_ONCE((dev_priv->rps.max_freq |
5969                    dev_priv->rps.efficient_freq |
5970                    dev_priv->rps.rp1_freq |
5971                    dev_priv->rps.min_freq) & 1,
5972                   "Odd GPU freq values\n");
5973 }
5974
5975 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5976 {
5977         valleyview_cleanup_pctx(dev_priv);
5978 }
5979
5980 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5981 {
5982         struct intel_engine_cs *engine;
5983         enum intel_engine_id id;
5984         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5985
5986         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5987
5988         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5989                                              GT_FIFO_FREE_ENTRIES_CHV);
5990         if (gtfifodbg) {
5991                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5992                                  gtfifodbg);
5993                 I915_WRITE(GTFIFODBG, gtfifodbg);
5994         }
5995
5996         cherryview_check_pctx(dev_priv);
5997
5998         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5999          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6000         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6001
6002         /*  Disable RC states. */
6003         I915_WRITE(GEN6_RC_CONTROL, 0);
6004
6005         /* 2a: Program RC6 thresholds.*/
6006         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6007         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6008         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6009
6010         for_each_engine(engine, dev_priv, id)
6011                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6012         I915_WRITE(GEN6_RC_SLEEP, 0);
6013
6014         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6015         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6016
6017         /* allows RC6 residency counter to work */
6018         I915_WRITE(VLV_COUNTER_CONTROL,
6019                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6020                                       VLV_MEDIA_RC6_COUNT_EN |
6021                                       VLV_RENDER_RC6_COUNT_EN));
6022
6023         /* For now we assume BIOS is allocating and populating the PCBR  */
6024         pcbr = I915_READ(VLV_PCBR);
6025
6026         /* 3: Enable RC6 */
6027         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6028             (pcbr >> VLV_PCBR_ADDR_SHIFT))
6029                 rc6_mode = GEN7_RC_CTL_TO_MODE;
6030
6031         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6032
6033         /* 4 Program defaults and thresholds for RPS*/
6034         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6035         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6036         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6037         I915_WRITE(GEN6_RP_UP_EI, 66000);
6038         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6039
6040         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6041
6042         /* 5: Enable RPS */
6043         I915_WRITE(GEN6_RP_CONTROL,
6044                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6045                    GEN6_RP_MEDIA_IS_GFX |
6046                    GEN6_RP_ENABLE |
6047                    GEN6_RP_UP_BUSY_AVG |
6048                    GEN6_RP_DOWN_IDLE_AVG);
6049
6050         /* Setting Fixed Bias */
6051         val = VLV_OVERRIDE_EN |
6052                   VLV_SOC_TDP_EN |
6053                   CHV_BIAS_CPU_50_SOC_50;
6054         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6055
6056         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6057
6058         /* RPS code assumes GPLL is used */
6059         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6060
6061         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6062         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6063
6064         reset_rps(dev_priv, valleyview_set_rps);
6065
6066         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6067 }
6068
6069 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6070 {
6071         struct intel_engine_cs *engine;
6072         enum intel_engine_id id;
6073         u32 gtfifodbg, val, rc6_mode = 0;
6074
6075         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6076
6077         valleyview_check_pctx(dev_priv);
6078
6079         gtfifodbg = I915_READ(GTFIFODBG);
6080         if (gtfifodbg) {
6081                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6082                                  gtfifodbg);
6083                 I915_WRITE(GTFIFODBG, gtfifodbg);
6084         }
6085
6086         /* If VLV, Forcewake all wells, else re-direct to regular path */
6087         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6088
6089         /*  Disable RC states. */
6090         I915_WRITE(GEN6_RC_CONTROL, 0);
6091
6092         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6093         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6094         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6095         I915_WRITE(GEN6_RP_UP_EI, 66000);
6096         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6097
6098         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6099
6100         I915_WRITE(GEN6_RP_CONTROL,
6101                    GEN6_RP_MEDIA_TURBO |
6102                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6103                    GEN6_RP_MEDIA_IS_GFX |
6104                    GEN6_RP_ENABLE |
6105                    GEN6_RP_UP_BUSY_AVG |
6106                    GEN6_RP_DOWN_IDLE_CONT);
6107
6108         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6109         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6110         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6111
6112         for_each_engine(engine, dev_priv, id)
6113                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6114
6115         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6116
6117         /* allows RC6 residency counter to work */
6118         I915_WRITE(VLV_COUNTER_CONTROL,
6119                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6120                                       VLV_RENDER_RC0_COUNT_EN |
6121                                       VLV_MEDIA_RC6_COUNT_EN |
6122                                       VLV_RENDER_RC6_COUNT_EN));
6123
6124         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6125                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6126
6127         intel_print_rc6_info(dev_priv, rc6_mode);
6128
6129         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6130
6131         /* Setting Fixed Bias */
6132         val = VLV_OVERRIDE_EN |
6133                   VLV_SOC_TDP_EN |
6134                   VLV_BIAS_CPU_125_SOC_875;
6135         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6136
6137         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6138
6139         /* RPS code assumes GPLL is used */
6140         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6141
6142         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6143         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6144
6145         reset_rps(dev_priv, valleyview_set_rps);
6146
6147         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6148 }
6149
6150 static unsigned long intel_pxfreq(u32 vidfreq)
6151 {
6152         unsigned long freq;
6153         int div = (vidfreq & 0x3f0000) >> 16;
6154         int post = (vidfreq & 0x3000) >> 12;
6155         int pre = (vidfreq & 0x7);
6156
6157         if (!pre)
6158                 return 0;
6159
6160         freq = ((div * 133333) / ((1<<post) * pre));
6161
6162         return freq;
6163 }
6164
6165 static const struct cparams {
6166         u16 i;
6167         u16 t;
6168         u16 m;
6169         u16 c;
6170 } cparams[] = {
6171         { 1, 1333, 301, 28664 },
6172         { 1, 1066, 294, 24460 },
6173         { 1, 800, 294, 25192 },
6174         { 0, 1333, 276, 27605 },
6175         { 0, 1066, 276, 27605 },
6176         { 0, 800, 231, 23784 },
6177 };
6178
6179 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6180 {
6181         u64 total_count, diff, ret;
6182         u32 count1, count2, count3, m = 0, c = 0;
6183         unsigned long now = jiffies_to_msecs(jiffies), diff1;
6184         int i;
6185
6186         assert_spin_locked(&mchdev_lock);
6187
6188         diff1 = now - dev_priv->ips.last_time1;
6189
6190         /* Prevent division-by-zero if we are asking too fast.
6191          * Also, we don't get interesting results if we are polling
6192          * faster than once in 10ms, so just return the saved value
6193          * in such cases.
6194          */
6195         if (diff1 <= 10)
6196                 return dev_priv->ips.chipset_power;
6197
6198         count1 = I915_READ(DMIEC);
6199         count2 = I915_READ(DDREC);
6200         count3 = I915_READ(CSIEC);
6201
6202         total_count = count1 + count2 + count3;
6203
6204         /* FIXME: handle per-counter overflow */
6205         if (total_count < dev_priv->ips.last_count1) {
6206                 diff = ~0UL - dev_priv->ips.last_count1;
6207                 diff += total_count;
6208         } else {
6209                 diff = total_count - dev_priv->ips.last_count1;
6210         }
6211
6212         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6213                 if (cparams[i].i == dev_priv->ips.c_m &&
6214                     cparams[i].t == dev_priv->ips.r_t) {
6215                         m = cparams[i].m;
6216                         c = cparams[i].c;
6217                         break;
6218                 }
6219         }
6220
6221         diff = div_u64(diff, diff1);
6222         ret = ((m * diff) + c);
6223         ret = div_u64(ret, 10);
6224
6225         dev_priv->ips.last_count1 = total_count;
6226         dev_priv->ips.last_time1 = now;
6227
6228         dev_priv->ips.chipset_power = ret;
6229
6230         return ret;
6231 }
6232
6233 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6234 {
6235         unsigned long val;
6236
6237         if (INTEL_INFO(dev_priv)->gen != 5)
6238                 return 0;
6239
6240         spin_lock_irq(&mchdev_lock);
6241
6242         val = __i915_chipset_val(dev_priv);
6243
6244         spin_unlock_irq(&mchdev_lock);
6245
6246         return val;
6247 }
6248
6249 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6250 {
6251         unsigned long m, x, b;
6252         u32 tsfs;
6253
6254         tsfs = I915_READ(TSFS);
6255
6256         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6257         x = I915_READ8(TR1);
6258
6259         b = tsfs & TSFS_INTR_MASK;
6260
6261         return ((m * x) / 127) - b;
6262 }
6263
6264 static int _pxvid_to_vd(u8 pxvid)
6265 {
6266         if (pxvid == 0)
6267                 return 0;
6268
6269         if (pxvid >= 8 && pxvid < 31)
6270                 pxvid = 31;
6271
6272         return (pxvid + 2) * 125;
6273 }
6274
6275 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6276 {
6277         const int vd = _pxvid_to_vd(pxvid);
6278         const int vm = vd - 1125;
6279
6280         if (INTEL_INFO(dev_priv)->is_mobile)
6281                 return vm > 0 ? vm : 0;
6282
6283         return vd;
6284 }
6285
6286 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6287 {
6288         u64 now, diff, diffms;
6289         u32 count;
6290
6291         assert_spin_locked(&mchdev_lock);
6292
6293         now = ktime_get_raw_ns();
6294         diffms = now - dev_priv->ips.last_time2;
6295         do_div(diffms, NSEC_PER_MSEC);
6296
6297         /* Don't divide by 0 */
6298         if (!diffms)
6299                 return;
6300
6301         count = I915_READ(GFXEC);
6302
6303         if (count < dev_priv->ips.last_count2) {
6304                 diff = ~0UL - dev_priv->ips.last_count2;
6305                 diff += count;
6306         } else {
6307                 diff = count - dev_priv->ips.last_count2;
6308         }
6309
6310         dev_priv->ips.last_count2 = count;
6311         dev_priv->ips.last_time2 = now;
6312
6313         /* More magic constants... */
6314         diff = diff * 1181;
6315         diff = div_u64(diff, diffms * 10);
6316         dev_priv->ips.gfx_power = diff;
6317 }
6318
6319 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6320 {
6321         if (INTEL_INFO(dev_priv)->gen != 5)
6322                 return;
6323
6324         spin_lock_irq(&mchdev_lock);
6325
6326         __i915_update_gfx_val(dev_priv);
6327
6328         spin_unlock_irq(&mchdev_lock);
6329 }
6330
6331 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6332 {
6333         unsigned long t, corr, state1, corr2, state2;
6334         u32 pxvid, ext_v;
6335
6336         assert_spin_locked(&mchdev_lock);
6337
6338         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6339         pxvid = (pxvid >> 24) & 0x7f;
6340         ext_v = pvid_to_extvid(dev_priv, pxvid);
6341
6342         state1 = ext_v;
6343
6344         t = i915_mch_val(dev_priv);
6345
6346         /* Revel in the empirically derived constants */
6347
6348         /* Correction factor in 1/100000 units */
6349         if (t > 80)
6350                 corr = ((t * 2349) + 135940);
6351         else if (t >= 50)
6352                 corr = ((t * 964) + 29317);
6353         else /* < 50 */
6354                 corr = ((t * 301) + 1004);
6355
6356         corr = corr * ((150142 * state1) / 10000 - 78642);
6357         corr /= 100000;
6358         corr2 = (corr * dev_priv->ips.corr);
6359
6360         state2 = (corr2 * state1) / 10000;
6361         state2 /= 100; /* convert to mW */
6362
6363         __i915_update_gfx_val(dev_priv);
6364
6365         return dev_priv->ips.gfx_power + state2;
6366 }
6367
6368 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6369 {
6370         unsigned long val;
6371
6372         if (INTEL_INFO(dev_priv)->gen != 5)
6373                 return 0;
6374
6375         spin_lock_irq(&mchdev_lock);
6376
6377         val = __i915_gfx_val(dev_priv);
6378
6379         spin_unlock_irq(&mchdev_lock);
6380
6381         return val;
6382 }
6383
6384 /**
6385  * i915_read_mch_val - return value for IPS use
6386  *
6387  * Calculate and return a value for the IPS driver to use when deciding whether
6388  * we have thermal and power headroom to increase CPU or GPU power budget.
6389  */
6390 unsigned long i915_read_mch_val(void)
6391 {
6392         struct drm_i915_private *dev_priv;
6393         unsigned long chipset_val, graphics_val, ret = 0;
6394
6395         spin_lock_irq(&mchdev_lock);
6396         if (!i915_mch_dev)
6397                 goto out_unlock;
6398         dev_priv = i915_mch_dev;
6399
6400         chipset_val = __i915_chipset_val(dev_priv);
6401         graphics_val = __i915_gfx_val(dev_priv);
6402
6403         ret = chipset_val + graphics_val;
6404
6405 out_unlock:
6406         spin_unlock_irq(&mchdev_lock);
6407
6408         return ret;
6409 }
6410 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6411
6412 /**
6413  * i915_gpu_raise - raise GPU frequency limit
6414  *
6415  * Raise the limit; IPS indicates we have thermal headroom.
6416  */
6417 bool i915_gpu_raise(void)
6418 {
6419         struct drm_i915_private *dev_priv;
6420         bool ret = true;
6421
6422         spin_lock_irq(&mchdev_lock);
6423         if (!i915_mch_dev) {
6424                 ret = false;
6425                 goto out_unlock;
6426         }
6427         dev_priv = i915_mch_dev;
6428
6429         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6430                 dev_priv->ips.max_delay--;
6431
6432 out_unlock:
6433         spin_unlock_irq(&mchdev_lock);
6434
6435         return ret;
6436 }
6437 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6438
6439 /**
6440  * i915_gpu_lower - lower GPU frequency limit
6441  *
6442  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6443  * frequency maximum.
6444  */
6445 bool i915_gpu_lower(void)
6446 {
6447         struct drm_i915_private *dev_priv;
6448         bool ret = true;
6449
6450         spin_lock_irq(&mchdev_lock);
6451         if (!i915_mch_dev) {
6452                 ret = false;
6453                 goto out_unlock;
6454         }
6455         dev_priv = i915_mch_dev;
6456
6457         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6458                 dev_priv->ips.max_delay++;
6459
6460 out_unlock:
6461         spin_unlock_irq(&mchdev_lock);
6462
6463         return ret;
6464 }
6465 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6466
6467 /**
6468  * i915_gpu_busy - indicate GPU business to IPS
6469  *
6470  * Tell the IPS driver whether or not the GPU is busy.
6471  */
6472 bool i915_gpu_busy(void)
6473 {
6474         bool ret = false;
6475
6476         spin_lock_irq(&mchdev_lock);
6477         if (i915_mch_dev)
6478                 ret = i915_mch_dev->gt.awake;
6479         spin_unlock_irq(&mchdev_lock);
6480
6481         return ret;
6482 }
6483 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6484
6485 /**
6486  * i915_gpu_turbo_disable - disable graphics turbo
6487  *
6488  * Disable graphics turbo by resetting the max frequency and setting the
6489  * current frequency to the default.
6490  */
6491 bool i915_gpu_turbo_disable(void)
6492 {
6493         struct drm_i915_private *dev_priv;
6494         bool ret = true;
6495
6496         spin_lock_irq(&mchdev_lock);
6497         if (!i915_mch_dev) {
6498                 ret = false;
6499                 goto out_unlock;
6500         }
6501         dev_priv = i915_mch_dev;
6502
6503         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6504
6505         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6506                 ret = false;
6507
6508 out_unlock:
6509         spin_unlock_irq(&mchdev_lock);
6510
6511         return ret;
6512 }
6513 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6514
6515 /**
6516  * Tells the intel_ips driver that the i915 driver is now loaded, if
6517  * IPS got loaded first.
6518  *
6519  * This awkward dance is so that neither module has to depend on the
6520  * other in order for IPS to do the appropriate communication of
6521  * GPU turbo limits to i915.
6522  */
6523 static void
6524 ips_ping_for_i915_load(void)
6525 {
6526         void (*link)(void);
6527
6528         link = symbol_get(ips_link_to_i915_driver);
6529         if (link) {
6530                 link();
6531                 symbol_put(ips_link_to_i915_driver);
6532         }
6533 }
6534
6535 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6536 {
6537         /* We only register the i915 ips part with intel-ips once everything is
6538          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6539         spin_lock_irq(&mchdev_lock);
6540         i915_mch_dev = dev_priv;
6541         spin_unlock_irq(&mchdev_lock);
6542
6543         ips_ping_for_i915_load();
6544 }
6545
6546 void intel_gpu_ips_teardown(void)
6547 {
6548         spin_lock_irq(&mchdev_lock);
6549         i915_mch_dev = NULL;
6550         spin_unlock_irq(&mchdev_lock);
6551 }
6552
6553 static void intel_init_emon(struct drm_i915_private *dev_priv)
6554 {
6555         u32 lcfuse;
6556         u8 pxw[16];
6557         int i;
6558
6559         /* Disable to program */
6560         I915_WRITE(ECR, 0);
6561         POSTING_READ(ECR);
6562
6563         /* Program energy weights for various events */
6564         I915_WRITE(SDEW, 0x15040d00);
6565         I915_WRITE(CSIEW0, 0x007f0000);
6566         I915_WRITE(CSIEW1, 0x1e220004);
6567         I915_WRITE(CSIEW2, 0x04000004);
6568
6569         for (i = 0; i < 5; i++)
6570                 I915_WRITE(PEW(i), 0);
6571         for (i = 0; i < 3; i++)
6572                 I915_WRITE(DEW(i), 0);
6573
6574         /* Program P-state weights to account for frequency power adjustment */
6575         for (i = 0; i < 16; i++) {
6576                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6577                 unsigned long freq = intel_pxfreq(pxvidfreq);
6578                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6579                         PXVFREQ_PX_SHIFT;
6580                 unsigned long val;
6581
6582                 val = vid * vid;
6583                 val *= (freq / 1000);
6584                 val *= 255;
6585                 val /= (127*127*900);
6586                 if (val > 0xff)
6587                         DRM_ERROR("bad pxval: %ld\n", val);
6588                 pxw[i] = val;
6589         }
6590         /* Render standby states get 0 weight */
6591         pxw[14] = 0;
6592         pxw[15] = 0;
6593
6594         for (i = 0; i < 4; i++) {
6595                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6596                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6597                 I915_WRITE(PXW(i), val);
6598         }
6599
6600         /* Adjust magic regs to magic values (more experimental results) */
6601         I915_WRITE(OGW0, 0);
6602         I915_WRITE(OGW1, 0);
6603         I915_WRITE(EG0, 0x00007f00);
6604         I915_WRITE(EG1, 0x0000000e);
6605         I915_WRITE(EG2, 0x000e0000);
6606         I915_WRITE(EG3, 0x68000300);
6607         I915_WRITE(EG4, 0x42000000);
6608         I915_WRITE(EG5, 0x00140031);
6609         I915_WRITE(EG6, 0);
6610         I915_WRITE(EG7, 0);
6611
6612         for (i = 0; i < 8; i++)
6613                 I915_WRITE(PXWL(i), 0);
6614
6615         /* Enable PMON + select events */
6616         I915_WRITE(ECR, 0x80000019);
6617
6618         lcfuse = I915_READ(LCFUSE02);
6619
6620         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6621 }
6622
6623 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6624 {
6625         /*
6626          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6627          * requirement.
6628          */
6629         if (!i915.enable_rc6) {
6630                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6631                 intel_runtime_pm_get(dev_priv);
6632         }
6633
6634         mutex_lock(&dev_priv->drm.struct_mutex);
6635         mutex_lock(&dev_priv->rps.hw_lock);
6636
6637         /* Initialize RPS limits (for userspace) */
6638         if (IS_CHERRYVIEW(dev_priv))
6639                 cherryview_init_gt_powersave(dev_priv);
6640         else if (IS_VALLEYVIEW(dev_priv))
6641                 valleyview_init_gt_powersave(dev_priv);
6642         else if (INTEL_GEN(dev_priv) >= 6)
6643                 gen6_init_rps_frequencies(dev_priv);
6644
6645         /* Derive initial user preferences/limits from the hardware limits */
6646         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6647         dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6648
6649         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6650         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6651
6652         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6653                 dev_priv->rps.min_freq_softlimit =
6654                         max_t(int,
6655                               dev_priv->rps.efficient_freq,
6656                               intel_freq_opcode(dev_priv, 450));
6657
6658         /* After setting max-softlimit, find the overclock max freq */
6659         if (IS_GEN6(dev_priv) ||
6660             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6661                 u32 params = 0;
6662
6663                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6664                 if (params & BIT(31)) { /* OC supported */
6665                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6666                                          (dev_priv->rps.max_freq & 0xff) * 50,
6667                                          (params & 0xff) * 50);
6668                         dev_priv->rps.max_freq = params & 0xff;
6669                 }
6670         }
6671
6672         /* Finally allow us to boost to max by default */
6673         dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6674
6675         mutex_unlock(&dev_priv->rps.hw_lock);
6676         mutex_unlock(&dev_priv->drm.struct_mutex);
6677
6678         intel_autoenable_gt_powersave(dev_priv);
6679 }
6680
6681 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6682 {
6683         if (IS_VALLEYVIEW(dev_priv))
6684                 valleyview_cleanup_gt_powersave(dev_priv);
6685
6686         if (!i915.enable_rc6)
6687                 intel_runtime_pm_put(dev_priv);
6688 }
6689
6690 /**
6691  * intel_suspend_gt_powersave - suspend PM work and helper threads
6692  * @dev_priv: i915 device
6693  *
6694  * We don't want to disable RC6 or other features here, we just want
6695  * to make sure any work we've queued has finished and won't bother
6696  * us while we're suspended.
6697  */
6698 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6699 {
6700         if (INTEL_GEN(dev_priv) < 6)
6701                 return;
6702
6703         if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6704                 intel_runtime_pm_put(dev_priv);
6705
6706         /* gen6_rps_idle() will be called later to disable interrupts */
6707 }
6708
6709 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6710 {
6711         dev_priv->rps.enabled = true; /* force disabling */
6712         intel_disable_gt_powersave(dev_priv);
6713
6714         gen6_reset_rps_interrupts(dev_priv);
6715 }
6716
6717 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6718 {
6719         if (!READ_ONCE(dev_priv->rps.enabled))
6720                 return;
6721
6722         mutex_lock(&dev_priv->rps.hw_lock);
6723
6724         if (INTEL_GEN(dev_priv) >= 9) {
6725                 gen9_disable_rc6(dev_priv);
6726                 gen9_disable_rps(dev_priv);
6727         } else if (IS_CHERRYVIEW(dev_priv)) {
6728                 cherryview_disable_rps(dev_priv);
6729         } else if (IS_VALLEYVIEW(dev_priv)) {
6730                 valleyview_disable_rps(dev_priv);
6731         } else if (INTEL_GEN(dev_priv) >= 6) {
6732                 gen6_disable_rps(dev_priv);
6733         }  else if (IS_IRONLAKE_M(dev_priv)) {
6734                 ironlake_disable_drps(dev_priv);
6735         }
6736
6737         dev_priv->rps.enabled = false;
6738         mutex_unlock(&dev_priv->rps.hw_lock);
6739 }
6740
6741 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6742 {
6743         /* We shouldn't be disabling as we submit, so this should be less
6744          * racy than it appears!
6745          */
6746         if (READ_ONCE(dev_priv->rps.enabled))
6747                 return;
6748
6749         /* Powersaving is controlled by the host when inside a VM */
6750         if (intel_vgpu_active(dev_priv))
6751                 return;
6752
6753         mutex_lock(&dev_priv->rps.hw_lock);
6754
6755         if (IS_CHERRYVIEW(dev_priv)) {
6756                 cherryview_enable_rps(dev_priv);
6757         } else if (IS_VALLEYVIEW(dev_priv)) {
6758                 valleyview_enable_rps(dev_priv);
6759         } else if (INTEL_GEN(dev_priv) >= 9) {
6760                 gen9_enable_rc6(dev_priv);
6761                 gen9_enable_rps(dev_priv);
6762                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6763                         gen6_update_ring_freq(dev_priv);
6764         } else if (IS_BROADWELL(dev_priv)) {
6765                 gen8_enable_rps(dev_priv);
6766                 gen6_update_ring_freq(dev_priv);
6767         } else if (INTEL_GEN(dev_priv) >= 6) {
6768                 gen6_enable_rps(dev_priv);
6769                 gen6_update_ring_freq(dev_priv);
6770         } else if (IS_IRONLAKE_M(dev_priv)) {
6771                 ironlake_enable_drps(dev_priv);
6772                 intel_init_emon(dev_priv);
6773         }
6774
6775         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6776         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6777
6778         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6779         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6780
6781         dev_priv->rps.enabled = true;
6782         mutex_unlock(&dev_priv->rps.hw_lock);
6783 }
6784
6785 static void __intel_autoenable_gt_powersave(struct work_struct *work)
6786 {
6787         struct drm_i915_private *dev_priv =
6788                 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6789         struct intel_engine_cs *rcs;
6790         struct drm_i915_gem_request *req;
6791
6792         if (READ_ONCE(dev_priv->rps.enabled))
6793                 goto out;
6794
6795         rcs = dev_priv->engine[RCS];
6796         if (rcs->last_context)
6797                 goto out;
6798
6799         if (!rcs->init_context)
6800                 goto out;
6801
6802         mutex_lock(&dev_priv->drm.struct_mutex);
6803
6804         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6805         if (IS_ERR(req))
6806                 goto unlock;
6807
6808         if (!i915.enable_execlists && i915_switch_context(req) == 0)
6809                 rcs->init_context(req);
6810
6811         /* Mark the device busy, calling intel_enable_gt_powersave() */
6812         i915_add_request_no_flush(req);
6813
6814 unlock:
6815         mutex_unlock(&dev_priv->drm.struct_mutex);
6816 out:
6817         intel_runtime_pm_put(dev_priv);
6818 }
6819
6820 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6821 {
6822         if (READ_ONCE(dev_priv->rps.enabled))
6823                 return;
6824
6825         if (IS_IRONLAKE_M(dev_priv)) {
6826                 ironlake_enable_drps(dev_priv);
6827                 intel_init_emon(dev_priv);
6828         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6829                 /*
6830                  * PCU communication is slow and this doesn't need to be
6831                  * done at any specific time, so do this out of our fast path
6832                  * to make resume and init faster.
6833                  *
6834                  * We depend on the HW RC6 power context save/restore
6835                  * mechanism when entering D3 through runtime PM suspend. So
6836                  * disable RPM until RPS/RC6 is properly setup. We can only
6837                  * get here via the driver load/system resume/runtime resume
6838                  * paths, so the _noresume version is enough (and in case of
6839                  * runtime resume it's necessary).
6840                  */
6841                 if (queue_delayed_work(dev_priv->wq,
6842                                        &dev_priv->rps.autoenable_work,
6843                                        round_jiffies_up_relative(HZ)))
6844                         intel_runtime_pm_get_noresume(dev_priv);
6845         }
6846 }
6847
6848 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
6849 {
6850         /*
6851          * On Ibex Peak and Cougar Point, we need to disable clock
6852          * gating for the panel power sequencer or it will fail to
6853          * start up when no ports are active.
6854          */
6855         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6856 }
6857
6858 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
6859 {
6860         enum pipe pipe;
6861
6862         for_each_pipe(dev_priv, pipe) {
6863                 I915_WRITE(DSPCNTR(pipe),
6864                            I915_READ(DSPCNTR(pipe)) |
6865                            DISPPLANE_TRICKLE_FEED_DISABLE);
6866
6867                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6868                 POSTING_READ(DSPSURF(pipe));
6869         }
6870 }
6871
6872 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
6873 {
6874         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6875         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6876         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6877
6878         /*
6879          * Don't touch WM1S_LP_EN here.
6880          * Doing so could cause underruns.
6881          */
6882 }
6883
6884 static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
6885 {
6886         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6887
6888         /*
6889          * Required for FBC
6890          * WaFbcDisableDpfcClockGating:ilk
6891          */
6892         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6893                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6894                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6895
6896         I915_WRITE(PCH_3DCGDIS0,
6897                    MARIUNIT_CLOCK_GATE_DISABLE |
6898                    SVSMUNIT_CLOCK_GATE_DISABLE);
6899         I915_WRITE(PCH_3DCGDIS1,
6900                    VFMUNIT_CLOCK_GATE_DISABLE);
6901
6902         /*
6903          * According to the spec the following bits should be set in
6904          * order to enable memory self-refresh
6905          * The bit 22/21 of 0x42004
6906          * The bit 5 of 0x42020
6907          * The bit 15 of 0x45000
6908          */
6909         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6910                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6911                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6912         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6913         I915_WRITE(DISP_ARB_CTL,
6914                    (I915_READ(DISP_ARB_CTL) |
6915                     DISP_FBC_WM_DIS));
6916
6917         ilk_init_lp_watermarks(dev_priv);
6918
6919         /*
6920          * Based on the document from hardware guys the following bits
6921          * should be set unconditionally in order to enable FBC.
6922          * The bit 22 of 0x42000
6923          * The bit 22 of 0x42004
6924          * The bit 7,8,9 of 0x42020.
6925          */
6926         if (IS_IRONLAKE_M(dev_priv)) {
6927                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6928                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6929                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6930                            ILK_FBCQ_DIS);
6931                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6932                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6933                            ILK_DPARB_GATE);
6934         }
6935
6936         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6937
6938         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6939                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6940                    ILK_ELPIN_409_SELECT);
6941         I915_WRITE(_3D_CHICKEN2,
6942                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6943                    _3D_CHICKEN2_WM_READ_PIPELINED);
6944
6945         /* WaDisableRenderCachePipelinedFlush:ilk */
6946         I915_WRITE(CACHE_MODE_0,
6947                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6948
6949         /* WaDisable_RenderCache_OperationalFlush:ilk */
6950         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6951
6952         g4x_disable_trickle_feed(dev_priv);
6953
6954         ibx_init_clock_gating(dev_priv);
6955 }
6956
6957 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
6958 {
6959         int pipe;
6960         uint32_t val;
6961
6962         /*
6963          * On Ibex Peak and Cougar Point, we need to disable clock
6964          * gating for the panel power sequencer or it will fail to
6965          * start up when no ports are active.
6966          */
6967         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6968                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6969                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6970         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6971                    DPLS_EDP_PPS_FIX_DIS);
6972         /* The below fixes the weird display corruption, a few pixels shifted
6973          * downward, on (only) LVDS of some HP laptops with IVY.
6974          */
6975         for_each_pipe(dev_priv, pipe) {
6976                 val = I915_READ(TRANS_CHICKEN2(pipe));
6977                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6978                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6979                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6980                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6981                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6982                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6983                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6984                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6985         }
6986         /* WADP0ClockGatingDisable */
6987         for_each_pipe(dev_priv, pipe) {
6988                 I915_WRITE(TRANS_CHICKEN1(pipe),
6989                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6990         }
6991 }
6992
6993 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
6994 {
6995         uint32_t tmp;
6996
6997         tmp = I915_READ(MCH_SSKPD);
6998         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6999                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7000                               tmp);
7001 }
7002
7003 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
7004 {
7005         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7006
7007         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7008
7009         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7010                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7011                    ILK_ELPIN_409_SELECT);
7012
7013         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7014         I915_WRITE(_3D_CHICKEN,
7015                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7016
7017         /* WaDisable_RenderCache_OperationalFlush:snb */
7018         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7019
7020         /*
7021          * BSpec recoomends 8x4 when MSAA is used,
7022          * however in practice 16x4 seems fastest.
7023          *
7024          * Note that PS/WM thread counts depend on the WIZ hashing
7025          * disable bit, which we don't touch here, but it's good
7026          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7027          */
7028         I915_WRITE(GEN6_GT_MODE,
7029                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7030
7031         ilk_init_lp_watermarks(dev_priv);
7032
7033         I915_WRITE(CACHE_MODE_0,
7034                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7035
7036         I915_WRITE(GEN6_UCGCTL1,
7037                    I915_READ(GEN6_UCGCTL1) |
7038                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7039                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7040
7041         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7042          * gating disable must be set.  Failure to set it results in
7043          * flickering pixels due to Z write ordering failures after
7044          * some amount of runtime in the Mesa "fire" demo, and Unigine
7045          * Sanctuary and Tropics, and apparently anything else with
7046          * alpha test or pixel discard.
7047          *
7048          * According to the spec, bit 11 (RCCUNIT) must also be set,
7049          * but we didn't debug actual testcases to find it out.
7050          *
7051          * WaDisableRCCUnitClockGating:snb
7052          * WaDisableRCPBUnitClockGating:snb
7053          */
7054         I915_WRITE(GEN6_UCGCTL2,
7055                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7056                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7057
7058         /* WaStripsFansDisableFastClipPerformanceFix:snb */
7059         I915_WRITE(_3D_CHICKEN3,
7060                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7061
7062         /*
7063          * Bspec says:
7064          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7065          * 3DSTATE_SF number of SF output attributes is more than 16."
7066          */
7067         I915_WRITE(_3D_CHICKEN3,
7068                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7069
7070         /*
7071          * According to the spec the following bits should be
7072          * set in order to enable memory self-refresh and fbc:
7073          * The bit21 and bit22 of 0x42000
7074          * The bit21 and bit22 of 0x42004
7075          * The bit5 and bit7 of 0x42020
7076          * The bit14 of 0x70180
7077          * The bit14 of 0x71180
7078          *
7079          * WaFbcAsynchFlipDisableFbcQueue:snb
7080          */
7081         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7082                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7083                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7084         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7085                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7086                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7087         I915_WRITE(ILK_DSPCLK_GATE_D,
7088                    I915_READ(ILK_DSPCLK_GATE_D) |
7089                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7090                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7091
7092         g4x_disable_trickle_feed(dev_priv);
7093
7094         cpt_init_clock_gating(dev_priv);
7095
7096         gen6_check_mch_setup(dev_priv);
7097 }
7098
7099 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7100 {
7101         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7102
7103         /*
7104          * WaVSThreadDispatchOverride:ivb,vlv
7105          *
7106          * This actually overrides the dispatch
7107          * mode for all thread types.
7108          */
7109         reg &= ~GEN7_FF_SCHED_MASK;
7110         reg |= GEN7_FF_TS_SCHED_HW;
7111         reg |= GEN7_FF_VS_SCHED_HW;
7112         reg |= GEN7_FF_DS_SCHED_HW;
7113
7114         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7115 }
7116
7117 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
7118 {
7119         /*
7120          * TODO: this bit should only be enabled when really needed, then
7121          * disabled when not needed anymore in order to save power.
7122          */
7123         if (HAS_PCH_LPT_LP(dev_priv))
7124                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7125                            I915_READ(SOUTH_DSPCLK_GATE_D) |
7126                            PCH_LP_PARTITION_LEVEL_DISABLE);
7127
7128         /* WADPOClockGatingDisable:hsw */
7129         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7130                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7131                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7132 }
7133
7134 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7135 {
7136         if (HAS_PCH_LPT_LP(dev_priv)) {
7137                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7138
7139                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7140                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7141         }
7142 }
7143
7144 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7145                                    int general_prio_credits,
7146                                    int high_prio_credits)
7147 {
7148         u32 misccpctl;
7149
7150         /* WaTempDisableDOPClkGating:bdw */
7151         misccpctl = I915_READ(GEN7_MISCCPCTL);
7152         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7153
7154         I915_WRITE(GEN8_L3SQCREG1,
7155                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7156                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
7157
7158         /*
7159          * Wait at least 100 clocks before re-enabling clock gating.
7160          * See the definition of L3SQCREG1 in BSpec.
7161          */
7162         POSTING_READ(GEN8_L3SQCREG1);
7163         udelay(1);
7164         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7165 }
7166
7167 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
7168 {
7169         gen9_init_clock_gating(dev_priv);
7170
7171         /* WaDisableSDEUnitClockGating:kbl */
7172         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7173                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7174                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7175
7176         /* WaDisableGamClockGating:kbl */
7177         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7178                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7179                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7180
7181         /* WaFbcNukeOnHostModify:kbl */
7182         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7183                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7184 }
7185
7186 static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
7187 {
7188         gen9_init_clock_gating(dev_priv);
7189
7190         /* WAC6entrylatency:skl */
7191         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7192                    FBC_LLC_FULLY_OPEN);
7193
7194         /* WaFbcNukeOnHostModify:skl */
7195         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7196                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7197 }
7198
7199 static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
7200 {
7201         enum pipe pipe;
7202
7203         ilk_init_lp_watermarks(dev_priv);
7204
7205         /* WaSwitchSolVfFArbitrationPriority:bdw */
7206         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7207
7208         /* WaPsrDPAMaskVBlankInSRD:bdw */
7209         I915_WRITE(CHICKEN_PAR1_1,
7210                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7211
7212         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7213         for_each_pipe(dev_priv, pipe) {
7214                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7215                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
7216                            BDW_DPRS_MASK_VBLANK_SRD);
7217         }
7218
7219         /* WaVSRefCountFullforceMissDisable:bdw */
7220         /* WaDSRefCountFullforceMissDisable:bdw */
7221         I915_WRITE(GEN7_FF_THREAD_MODE,
7222                    I915_READ(GEN7_FF_THREAD_MODE) &
7223                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7224
7225         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7226                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7227
7228         /* WaDisableSDEUnitClockGating:bdw */
7229         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7230                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7231
7232         /* WaProgramL3SqcReg1Default:bdw */
7233         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7234
7235         /*
7236          * WaGttCachingOffByDefault:bdw
7237          * GTT cache may not work with big pages, so if those
7238          * are ever enabled GTT cache may need to be disabled.
7239          */
7240         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7241
7242         /* WaKVMNotificationOnConfigChange:bdw */
7243         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7244                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7245
7246         lpt_init_clock_gating(dev_priv);
7247 }
7248
7249 static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
7250 {
7251         ilk_init_lp_watermarks(dev_priv);
7252
7253         /* L3 caching of data atomics doesn't work -- disable it. */
7254         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7255         I915_WRITE(HSW_ROW_CHICKEN3,
7256                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7257
7258         /* This is required by WaCatErrorRejectionIssue:hsw */
7259         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7260                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7261                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7262
7263         /* WaVSRefCountFullforceMissDisable:hsw */
7264         I915_WRITE(GEN7_FF_THREAD_MODE,
7265                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7266
7267         /* WaDisable_RenderCache_OperationalFlush:hsw */
7268         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7269
7270         /* enable HiZ Raw Stall Optimization */
7271         I915_WRITE(CACHE_MODE_0_GEN7,
7272                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7273
7274         /* WaDisable4x2SubspanOptimization:hsw */
7275         I915_WRITE(CACHE_MODE_1,
7276                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7277
7278         /*
7279          * BSpec recommends 8x4 when MSAA is used,
7280          * however in practice 16x4 seems fastest.
7281          *
7282          * Note that PS/WM thread counts depend on the WIZ hashing
7283          * disable bit, which we don't touch here, but it's good
7284          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7285          */
7286         I915_WRITE(GEN7_GT_MODE,
7287                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7288
7289         /* WaSampleCChickenBitEnable:hsw */
7290         I915_WRITE(HALF_SLICE_CHICKEN3,
7291                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7292
7293         /* WaSwitchSolVfFArbitrationPriority:hsw */
7294         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7295
7296         /* WaRsPkgCStateDisplayPMReq:hsw */
7297         I915_WRITE(CHICKEN_PAR1_1,
7298                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7299
7300         lpt_init_clock_gating(dev_priv);
7301 }
7302
7303 static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
7304 {
7305         uint32_t snpcr;
7306
7307         ilk_init_lp_watermarks(dev_priv);
7308
7309         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7310
7311         /* WaDisableEarlyCull:ivb */
7312         I915_WRITE(_3D_CHICKEN3,
7313                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7314
7315         /* WaDisableBackToBackFlipFix:ivb */
7316         I915_WRITE(IVB_CHICKEN3,
7317                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7318                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7319
7320         /* WaDisablePSDDualDispatchEnable:ivb */
7321         if (IS_IVB_GT1(dev_priv))
7322                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7323                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7324
7325         /* WaDisable_RenderCache_OperationalFlush:ivb */
7326         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7327
7328         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7329         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7330                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7331
7332         /* WaApplyL3ControlAndL3ChickenMode:ivb */
7333         I915_WRITE(GEN7_L3CNTLREG1,
7334                         GEN7_WA_FOR_GEN7_L3_CONTROL);
7335         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7336                    GEN7_WA_L3_CHICKEN_MODE);
7337         if (IS_IVB_GT1(dev_priv))
7338                 I915_WRITE(GEN7_ROW_CHICKEN2,
7339                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7340         else {
7341                 /* must write both registers */
7342                 I915_WRITE(GEN7_ROW_CHICKEN2,
7343                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7344                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7345                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7346         }
7347
7348         /* WaForceL3Serialization:ivb */
7349         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7350                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7351
7352         /*
7353          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7354          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7355          */
7356         I915_WRITE(GEN6_UCGCTL2,
7357                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7358
7359         /* This is required by WaCatErrorRejectionIssue:ivb */
7360         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7361                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7362                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7363
7364         g4x_disable_trickle_feed(dev_priv);
7365
7366         gen7_setup_fixed_func_scheduler(dev_priv);
7367
7368         if (0) { /* causes HiZ corruption on ivb:gt1 */
7369                 /* enable HiZ Raw Stall Optimization */
7370                 I915_WRITE(CACHE_MODE_0_GEN7,
7371                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7372         }
7373
7374         /* WaDisable4x2SubspanOptimization:ivb */
7375         I915_WRITE(CACHE_MODE_1,
7376                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7377
7378         /*
7379          * BSpec recommends 8x4 when MSAA is used,
7380          * however in practice 16x4 seems fastest.
7381          *
7382          * Note that PS/WM thread counts depend on the WIZ hashing
7383          * disable bit, which we don't touch here, but it's good
7384          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7385          */
7386         I915_WRITE(GEN7_GT_MODE,
7387                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7388
7389         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7390         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7391         snpcr |= GEN6_MBC_SNPCR_MED;
7392         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7393
7394         if (!HAS_PCH_NOP(dev_priv))
7395                 cpt_init_clock_gating(dev_priv);
7396
7397         gen6_check_mch_setup(dev_priv);
7398 }
7399
7400 static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
7401 {
7402         /* WaDisableEarlyCull:vlv */
7403         I915_WRITE(_3D_CHICKEN3,
7404                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7405
7406         /* WaDisableBackToBackFlipFix:vlv */
7407         I915_WRITE(IVB_CHICKEN3,
7408                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7409                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7410
7411         /* WaPsdDispatchEnable:vlv */
7412         /* WaDisablePSDDualDispatchEnable:vlv */
7413         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7414                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7415                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7416
7417         /* WaDisable_RenderCache_OperationalFlush:vlv */
7418         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7419
7420         /* WaForceL3Serialization:vlv */
7421         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7422                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7423
7424         /* WaDisableDopClockGating:vlv */
7425         I915_WRITE(GEN7_ROW_CHICKEN2,
7426                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7427
7428         /* This is required by WaCatErrorRejectionIssue:vlv */
7429         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7430                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7431                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7432
7433         gen7_setup_fixed_func_scheduler(dev_priv);
7434
7435         /*
7436          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7437          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7438          */
7439         I915_WRITE(GEN6_UCGCTL2,
7440                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7441
7442         /* WaDisableL3Bank2xClockGate:vlv
7443          * Disabling L3 clock gating- MMIO 940c[25] = 1
7444          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7445         I915_WRITE(GEN7_UCGCTL4,
7446                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7447
7448         /*
7449          * BSpec says this must be set, even though
7450          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7451          */
7452         I915_WRITE(CACHE_MODE_1,
7453                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7454
7455         /*
7456          * BSpec recommends 8x4 when MSAA is used,
7457          * however in practice 16x4 seems fastest.
7458          *
7459          * Note that PS/WM thread counts depend on the WIZ hashing
7460          * disable bit, which we don't touch here, but it's good
7461          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7462          */
7463         I915_WRITE(GEN7_GT_MODE,
7464                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7465
7466         /*
7467          * WaIncreaseL3CreditsForVLVB0:vlv
7468          * This is the hardware default actually.
7469          */
7470         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7471
7472         /*
7473          * WaDisableVLVClockGating_VBIIssue:vlv
7474          * Disable clock gating on th GCFG unit to prevent a delay
7475          * in the reporting of vblank events.
7476          */
7477         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7478 }
7479
7480 static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
7481 {
7482         /* WaVSRefCountFullforceMissDisable:chv */
7483         /* WaDSRefCountFullforceMissDisable:chv */
7484         I915_WRITE(GEN7_FF_THREAD_MODE,
7485                    I915_READ(GEN7_FF_THREAD_MODE) &
7486                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7487
7488         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7489         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7490                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7491
7492         /* WaDisableCSUnitClockGating:chv */
7493         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7494                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7495
7496         /* WaDisableSDEUnitClockGating:chv */
7497         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7498                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7499
7500         /*
7501          * WaProgramL3SqcReg1Default:chv
7502          * See gfxspecs/Related Documents/Performance Guide/
7503          * LSQC Setting Recommendations.
7504          */
7505         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7506
7507         /*
7508          * GTT cache may not work with big pages, so if those
7509          * are ever enabled GTT cache may need to be disabled.
7510          */
7511         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7512 }
7513
7514 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
7515 {
7516         uint32_t dspclk_gate;
7517
7518         I915_WRITE(RENCLK_GATE_D1, 0);
7519         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7520                    GS_UNIT_CLOCK_GATE_DISABLE |
7521                    CL_UNIT_CLOCK_GATE_DISABLE);
7522         I915_WRITE(RAMCLK_GATE_D, 0);
7523         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7524                 OVRUNIT_CLOCK_GATE_DISABLE |
7525                 OVCUNIT_CLOCK_GATE_DISABLE;
7526         if (IS_GM45(dev_priv))
7527                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7528         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7529
7530         /* WaDisableRenderCachePipelinedFlush */
7531         I915_WRITE(CACHE_MODE_0,
7532                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7533
7534         /* WaDisable_RenderCache_OperationalFlush:g4x */
7535         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7536
7537         g4x_disable_trickle_feed(dev_priv);
7538 }
7539
7540 static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
7541 {
7542         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7543         I915_WRITE(RENCLK_GATE_D2, 0);
7544         I915_WRITE(DSPCLK_GATE_D, 0);
7545         I915_WRITE(RAMCLK_GATE_D, 0);
7546         I915_WRITE16(DEUC, 0);
7547         I915_WRITE(MI_ARB_STATE,
7548                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7549
7550         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7551         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7552 }
7553
7554 static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
7555 {
7556         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7557                    I965_RCC_CLOCK_GATE_DISABLE |
7558                    I965_RCPB_CLOCK_GATE_DISABLE |
7559                    I965_ISC_CLOCK_GATE_DISABLE |
7560                    I965_FBC_CLOCK_GATE_DISABLE);
7561         I915_WRITE(RENCLK_GATE_D2, 0);
7562         I915_WRITE(MI_ARB_STATE,
7563                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7564
7565         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7566         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7567 }
7568
7569 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
7570 {
7571         u32 dstate = I915_READ(D_STATE);
7572
7573         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7574                 DSTATE_DOT_CLOCK_GATING;
7575         I915_WRITE(D_STATE, dstate);
7576
7577         if (IS_PINEVIEW(dev_priv))
7578                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7579
7580         /* IIR "flip pending" means done if this bit is set */
7581         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7582
7583         /* interrupts should cause a wake up from C3 */
7584         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7585
7586         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7587         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7588
7589         I915_WRITE(MI_ARB_STATE,
7590                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7591 }
7592
7593 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
7594 {
7595         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7596
7597         /* interrupts should cause a wake up from C3 */
7598         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7599                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7600
7601         I915_WRITE(MEM_MODE,
7602                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7603 }
7604
7605 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
7606 {
7607         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7608
7609         I915_WRITE(MEM_MODE,
7610                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7611                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7612 }
7613
7614 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
7615 {
7616         dev_priv->display.init_clock_gating(dev_priv);
7617 }
7618
7619 void intel_suspend_hw(struct drm_i915_private *dev_priv)
7620 {
7621         if (HAS_PCH_LPT(dev_priv))
7622                 lpt_suspend_hw(dev_priv);
7623 }
7624
7625 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
7626 {
7627         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7628 }
7629
7630 /**
7631  * intel_init_clock_gating_hooks - setup the clock gating hooks
7632  * @dev_priv: device private
7633  *
7634  * Setup the hooks that configure which clocks of a given platform can be
7635  * gated and also apply various GT and display specific workarounds for these
7636  * platforms. Note that some GT specific workarounds are applied separately
7637  * when GPU contexts or batchbuffers start their execution.
7638  */
7639 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7640 {
7641         if (IS_SKYLAKE(dev_priv))
7642                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7643         else if (IS_KABYLAKE(dev_priv))
7644                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7645         else if (IS_BROXTON(dev_priv))
7646                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7647         else if (IS_BROADWELL(dev_priv))
7648                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7649         else if (IS_CHERRYVIEW(dev_priv))
7650                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7651         else if (IS_HASWELL(dev_priv))
7652                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7653         else if (IS_IVYBRIDGE(dev_priv))
7654                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7655         else if (IS_VALLEYVIEW(dev_priv))
7656                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7657         else if (IS_GEN6(dev_priv))
7658                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7659         else if (IS_GEN5(dev_priv))
7660                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7661         else if (IS_G4X(dev_priv))
7662                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7663         else if (IS_CRESTLINE(dev_priv))
7664                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7665         else if (IS_BROADWATER(dev_priv))
7666                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7667         else if (IS_GEN3(dev_priv))
7668                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7669         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7670                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7671         else if (IS_GEN2(dev_priv))
7672                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7673         else {
7674                 MISSING_CASE(INTEL_DEVID(dev_priv));
7675                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7676         }
7677 }
7678
7679 /* Set up chip specific power management-related functions */
7680 void intel_init_pm(struct drm_i915_private *dev_priv)
7681 {
7682         intel_fbc_init(dev_priv);
7683
7684         /* For cxsr */
7685         if (IS_PINEVIEW(dev_priv))
7686                 i915_pineview_get_mem_freq(dev_priv);
7687         else if (IS_GEN5(dev_priv))
7688                 i915_ironlake_get_mem_freq(dev_priv);
7689
7690         /* For FIFO watermark updates */
7691         if (INTEL_GEN(dev_priv) >= 9) {
7692                 skl_setup_wm_latency(dev_priv);
7693                 dev_priv->display.update_wm = skl_update_wm;
7694                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7695         } else if (HAS_PCH_SPLIT(dev_priv)) {
7696                 ilk_setup_wm_latency(dev_priv);
7697
7698                 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
7699                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7700                     (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
7701                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7702                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7703                         dev_priv->display.compute_intermediate_wm =
7704                                 ilk_compute_intermediate_wm;
7705                         dev_priv->display.initial_watermarks =
7706                                 ilk_initial_watermarks;
7707                         dev_priv->display.optimize_watermarks =
7708                                 ilk_optimize_watermarks;
7709                 } else {
7710                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7711                                       "Disable CxSR\n");
7712                 }
7713         } else if (IS_CHERRYVIEW(dev_priv)) {
7714                 vlv_setup_wm_latency(dev_priv);
7715                 dev_priv->display.update_wm = vlv_update_wm;
7716         } else if (IS_VALLEYVIEW(dev_priv)) {
7717                 vlv_setup_wm_latency(dev_priv);
7718                 dev_priv->display.update_wm = vlv_update_wm;
7719         } else if (IS_PINEVIEW(dev_priv)) {
7720                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
7721                                             dev_priv->is_ddr3,
7722                                             dev_priv->fsb_freq,
7723                                             dev_priv->mem_freq)) {
7724                         DRM_INFO("failed to find known CxSR latency "
7725                                  "(found ddr%s fsb freq %d, mem freq %d), "
7726                                  "disabling CxSR\n",
7727                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7728                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7729                         /* Disable CxSR and never update its watermark again */
7730                         intel_set_memory_cxsr(dev_priv, false);
7731                         dev_priv->display.update_wm = NULL;
7732                 } else
7733                         dev_priv->display.update_wm = pineview_update_wm;
7734         } else if (IS_G4X(dev_priv)) {
7735                 dev_priv->display.update_wm = g4x_update_wm;
7736         } else if (IS_GEN4(dev_priv)) {
7737                 dev_priv->display.update_wm = i965_update_wm;
7738         } else if (IS_GEN3(dev_priv)) {
7739                 dev_priv->display.update_wm = i9xx_update_wm;
7740                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7741         } else if (IS_GEN2(dev_priv)) {
7742                 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
7743                         dev_priv->display.update_wm = i845_update_wm;
7744                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7745                 } else {
7746                         dev_priv->display.update_wm = i9xx_update_wm;
7747                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7748                 }
7749         } else {
7750                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7751         }
7752 }
7753
7754 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7755 {
7756         uint32_t flags =
7757                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7758
7759         switch (flags) {
7760         case GEN6_PCODE_SUCCESS:
7761                 return 0;
7762         case GEN6_PCODE_UNIMPLEMENTED_CMD:
7763         case GEN6_PCODE_ILLEGAL_CMD:
7764                 return -ENXIO;
7765         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7766         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7767                 return -EOVERFLOW;
7768         case GEN6_PCODE_TIMEOUT:
7769                 return -ETIMEDOUT;
7770         default:
7771                 MISSING_CASE(flags)
7772                 return 0;
7773         }
7774 }
7775
7776 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7777 {
7778         uint32_t flags =
7779                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7780
7781         switch (flags) {
7782         case GEN6_PCODE_SUCCESS:
7783                 return 0;
7784         case GEN6_PCODE_ILLEGAL_CMD:
7785                 return -ENXIO;
7786         case GEN7_PCODE_TIMEOUT:
7787                 return -ETIMEDOUT;
7788         case GEN7_PCODE_ILLEGAL_DATA:
7789                 return -EINVAL;
7790         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7791                 return -EOVERFLOW;
7792         default:
7793                 MISSING_CASE(flags);
7794                 return 0;
7795         }
7796 }
7797
7798 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7799 {
7800         int status;
7801
7802         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7803
7804         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7805          * use te fw I915_READ variants to reduce the amount of work
7806          * required when reading/writing.
7807          */
7808
7809         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7810                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7811                 return -EAGAIN;
7812         }
7813
7814         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7815         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7816         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7817
7818         if (intel_wait_for_register_fw(dev_priv,
7819                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7820                                        500)) {
7821                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7822                 return -ETIMEDOUT;
7823         }
7824
7825         *val = I915_READ_FW(GEN6_PCODE_DATA);
7826         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7827
7828         if (INTEL_GEN(dev_priv) > 6)
7829                 status = gen7_check_mailbox_status(dev_priv);
7830         else
7831                 status = gen6_check_mailbox_status(dev_priv);
7832
7833         if (status) {
7834                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7835                                  status);
7836                 return status;
7837         }
7838
7839         return 0;
7840 }
7841
7842 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7843                             u32 mbox, u32 val)
7844 {
7845         int status;
7846
7847         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7848
7849         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7850          * use te fw I915_READ variants to reduce the amount of work
7851          * required when reading/writing.
7852          */
7853
7854         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7855                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7856                 return -EAGAIN;
7857         }
7858
7859         I915_WRITE_FW(GEN6_PCODE_DATA, val);
7860         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7861
7862         if (intel_wait_for_register_fw(dev_priv,
7863                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7864                                        500)) {
7865                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7866                 return -ETIMEDOUT;
7867         }
7868
7869         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7870
7871         if (INTEL_GEN(dev_priv) > 6)
7872                 status = gen7_check_mailbox_status(dev_priv);
7873         else
7874                 status = gen6_check_mailbox_status(dev_priv);
7875
7876         if (status) {
7877                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7878                                  status);
7879                 return status;
7880         }
7881
7882         return 0;
7883 }
7884
7885 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7886 {
7887         /*
7888          * N = val - 0xb7
7889          * Slow = Fast = GPLL ref * N
7890          */
7891         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7892 }
7893
7894 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7895 {
7896         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7897 }
7898
7899 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7900 {
7901         /*
7902          * N = val / 2
7903          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7904          */
7905         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7906 }
7907
7908 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7909 {
7910         /* CHV needs even values */
7911         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7912 }
7913
7914 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7915 {
7916         if (IS_GEN9(dev_priv))
7917                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7918                                          GEN9_FREQ_SCALER);
7919         else if (IS_CHERRYVIEW(dev_priv))
7920                 return chv_gpu_freq(dev_priv, val);
7921         else if (IS_VALLEYVIEW(dev_priv))
7922                 return byt_gpu_freq(dev_priv, val);
7923         else
7924                 return val * GT_FREQUENCY_MULTIPLIER;
7925 }
7926
7927 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7928 {
7929         if (IS_GEN9(dev_priv))
7930                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7931                                          GT_FREQUENCY_MULTIPLIER);
7932         else if (IS_CHERRYVIEW(dev_priv))
7933                 return chv_freq_opcode(dev_priv, val);
7934         else if (IS_VALLEYVIEW(dev_priv))
7935                 return byt_freq_opcode(dev_priv, val);
7936         else
7937                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7938 }
7939
7940 struct request_boost {
7941         struct work_struct work;
7942         struct drm_i915_gem_request *req;
7943 };
7944
7945 static void __intel_rps_boost_work(struct work_struct *work)
7946 {
7947         struct request_boost *boost = container_of(work, struct request_boost, work);
7948         struct drm_i915_gem_request *req = boost->req;
7949
7950         if (!i915_gem_request_completed(req))
7951                 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7952
7953         i915_gem_request_put(req);
7954         kfree(boost);
7955 }
7956
7957 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
7958 {
7959         struct request_boost *boost;
7960
7961         if (req == NULL || INTEL_GEN(req->i915) < 6)
7962                 return;
7963
7964         if (i915_gem_request_completed(req))
7965                 return;
7966
7967         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7968         if (boost == NULL)
7969                 return;
7970
7971         boost->req = i915_gem_request_get(req);
7972
7973         INIT_WORK(&boost->work, __intel_rps_boost_work);
7974         queue_work(req->i915->wq, &boost->work);
7975 }
7976
7977 void intel_pm_setup(struct drm_device *dev)
7978 {
7979         struct drm_i915_private *dev_priv = to_i915(dev);
7980
7981         mutex_init(&dev_priv->rps.hw_lock);
7982         spin_lock_init(&dev_priv->rps.client_lock);
7983
7984         INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
7985                           __intel_autoenable_gt_powersave);
7986         INIT_LIST_HEAD(&dev_priv->rps.clients);
7987
7988         dev_priv->pm.suspended = false;
7989         atomic_set(&dev_priv->pm.wakeref_count, 0);
7990 }