drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34 #include <drm/drm_atomic_helper.h>
  35
  36 /**
  37  * DOC: RC6
  38  *
  39  * RC6 is a special power stage which allows the GPU to enter an very
  40  * low-voltage mode when idle, using down to 0V while at this stage.  This
  41  * stage is entered automatically when the GPU is idle when RC6 support is
  42  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  43  *
  44  * There are different RC6 modes available in Intel GPU, which differentiate
  45  * among each other with the latency required to enter and leave RC6 and
  46  * voltage consumed by the GPU in different states.
  47  *
  48  * The combination of the following flags define which states GPU is allowed
  49  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  50  * RC6pp is deepest RC6. Their support by hardware varies according to the
  51  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  52  * which brings the most power savings; deeper states save more power, but
  53  * require higher latency to switch to and wake up.
  54  */
  55 #define INTEL_RC6_ENABLE                        (1<<0)
  56 #define INTEL_RC6p_ENABLE                       (1<<1)
  57 #define INTEL_RC6pp_ENABLE                      (1<<2)
  58
  59 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
  60 {
  61         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
  62         I915_WRITE(CHICKEN_PAR1_1,
  63                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  64
  65         I915_WRITE(GEN8_CONFIG0,
  66                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  67
  68         /* WaEnableChickenDCPR:skl,bxt,kbl */
  69         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  70                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  71
  72         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
  73         /* WaFbcWakeMemOn:skl,bxt,kbl */
  74         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  75                    DISP_FBC_WM_DIS |
  76                    DISP_FBC_MEMORY_WAKE);
  77
  78         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
  79         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  80                    ILK_DPFC_DISABLE_DUMMY0);
  81 }
  82
  83 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
  84 {
  85         gen9_init_clock_gating(dev_priv);
  86
  87         /* WaDisableSDEUnitClockGating:bxt */
  88         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  89                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  90
  91         /*
  92          * FIXME:
  93          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  94          */
  95         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  96                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  97
  98         /*
  99          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 100          * to stay fully on.
 101          */
 102         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
 103                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 104                            PWM1_GATING_DIS | PWM2_GATING_DIS);
 105 }
 106
 107 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
 108 {
 109         u32 tmp;
 110
 111         tmp = I915_READ(CLKCFG);
 112
 113         switch (tmp & CLKCFG_FSB_MASK) {
 114         case CLKCFG_FSB_533:
 115                 dev_priv->fsb_freq = 533; /* 133*4 */
 116                 break;
 117         case CLKCFG_FSB_800:
 118                 dev_priv->fsb_freq = 800; /* 200*4 */
 119                 break;
 120         case CLKCFG_FSB_667:
 121                 dev_priv->fsb_freq =  667; /* 167*4 */
 122                 break;
 123         case CLKCFG_FSB_400:
 124                 dev_priv->fsb_freq = 400; /* 100*4 */
 125                 break;
 126         }
 127
 128         switch (tmp & CLKCFG_MEM_MASK) {
 129         case CLKCFG_MEM_533:
 130                 dev_priv->mem_freq = 533;
 131                 break;
 132         case CLKCFG_MEM_667:
 133                 dev_priv->mem_freq = 667;
 134                 break;
 135         case CLKCFG_MEM_800:
 136                 dev_priv->mem_freq = 800;
 137                 break;
 138         }
 139
 140         /* detect pineview DDR3 setting */
 141         tmp = I915_READ(CSHRDDR3CTL);
 142         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 143 }
 144
 145 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
 146 {
 147         u16 ddrpll, csipll;
 148
 149         ddrpll = I915_READ16(DDRMPLL1);
 150         csipll = I915_READ16(CSIPLL0);
 151
 152         switch (ddrpll & 0xff) {
 153         case 0xc:
 154                 dev_priv->mem_freq = 800;
 155                 break;
 156         case 0x10:
 157                 dev_priv->mem_freq = 1066;
 158                 break;
 159         case 0x14:
 160                 dev_priv->mem_freq = 1333;
 161                 break;
 162         case 0x18:
 163                 dev_priv->mem_freq = 1600;
 164                 break;
 165         default:
 166                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 167                                  ddrpll & 0xff);
 168                 dev_priv->mem_freq = 0;
 169                 break;
 170         }
 171
 172         dev_priv->ips.r_t = dev_priv->mem_freq;
 173
 174         switch (csipll & 0x3ff) {
 175         case 0x00c:
 176                 dev_priv->fsb_freq = 3200;
 177                 break;
 178         case 0x00e:
 179                 dev_priv->fsb_freq = 3733;
 180                 break;
 181         case 0x010:
 182                 dev_priv->fsb_freq = 4266;
 183                 break;
 184         case 0x012:
 185                 dev_priv->fsb_freq = 4800;
 186                 break;
 187         case 0x014:
 188                 dev_priv->fsb_freq = 5333;
 189                 break;
 190         case 0x016:
 191                 dev_priv->fsb_freq = 5866;
 192                 break;
 193         case 0x018:
 194                 dev_priv->fsb_freq = 6400;
 195                 break;
 196         default:
 197                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 198                                  csipll & 0x3ff);
 199                 dev_priv->fsb_freq = 0;
 200                 break;
 201         }
 202
 203         if (dev_priv->fsb_freq == 3200) {
 204                 dev_priv->ips.c_m = 0;
 205         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 206                 dev_priv->ips.c_m = 1;
 207         } else {
 208                 dev_priv->ips.c_m = 2;
 209         }
 210 }
 211
 212 static const struct cxsr_latency cxsr_latency_table[] = {
 213         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 214         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 215         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 216         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 217         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 218
 219         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 220         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 221         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 222         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 223         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 224
 225         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 226         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 227         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 228         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 229         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 230
 231         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 232         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 233         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 234         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 235         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 236
 237         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 238         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 239         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 240         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 241         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 242
 243         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 244         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 245         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 246         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 247         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 248 };
 249
 250 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 251                                                          bool is_ddr3,
 252                                                          int fsb,
 253                                                          int mem)
 254 {
 255         const struct cxsr_latency *latency;
 256         int i;
 257
 258         if (fsb == 0 || mem == 0)
 259                 return NULL;
 260
 261         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 262                 latency = &cxsr_latency_table[i];
 263                 if (is_desktop == latency->is_desktop &&
 264                     is_ddr3 == latency->is_ddr3 &&
 265                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 266                         return latency;
 267         }
 268
 269         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 270
 271         return NULL;
 272 }
 273
 274 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 275 {
 276         u32 val;
 277
 278         mutex_lock(&dev_priv->rps.hw_lock);
 279
 280         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 281         if (enable)
 282                 val &= ~FORCE_DDR_HIGH_FREQ;
 283         else
 284                 val |= FORCE_DDR_HIGH_FREQ;
 285         val &= ~FORCE_DDR_LOW_FREQ;
 286         val |= FORCE_DDR_FREQ_REQ_ACK;
 287         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 288
 289         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 290                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 291                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 292
 293         mutex_unlock(&dev_priv->rps.hw_lock);
 294 }
 295
 296 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 297 {
 298         u32 val;
 299
 300         mutex_lock(&dev_priv->rps.hw_lock);
 301
 302         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 303         if (enable)
 304                 val |= DSP_MAXFIFO_PM5_ENABLE;
 305         else
 306                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 307         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 308
 309         mutex_unlock(&dev_priv->rps.hw_lock);
 310 }
 311
 312 #define FW_WM(value, plane) \
 313         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 314
 315 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 316 {
 317         u32 val;
 318
 319         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 320                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 321                 POSTING_READ(FW_BLC_SELF_VLV);
 322                 dev_priv->wm.vlv.cxsr = enable;
 323         } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
 324                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 325                 POSTING_READ(FW_BLC_SELF);
 326         } else if (IS_PINEVIEW(dev_priv)) {
 327                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 328                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 329                 I915_WRITE(DSPFW3, val);
 330                 POSTING_READ(DSPFW3);
 331         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 332                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 333                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 334                 I915_WRITE(FW_BLC_SELF, val);
 335                 POSTING_READ(FW_BLC_SELF);
 336         } else if (IS_I915GM(dev_priv)) {
 337                 /*
 338                  * FIXME can't find a bit like this for 915G, and
 339                  * and yet it does have the related watermark in
 340                  * FW_BLC_SELF. What's going on?
 341                  */
 342                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 343                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 344                 I915_WRITE(INSTPM, val);
 345                 POSTING_READ(INSTPM);
 346         } else {
 347                 return;
 348         }
 349
 350         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 351                       enable ? "enabled" : "disabled");
 352 }
 353
 354
 355 /*
 356  * Latency for FIFO fetches is dependent on several factors:
 357  *   - memory configuration (speed, channels)
 358  *   - chipset
 359  *   - current MCH state
 360  * It can be fairly high in some situations, so here we assume a fairly
 361  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 362  * set this value too high, the FIFO will fetch frequently to stay full)
 363  * and power consumption (set it too low to save power and we might see
 364  * FIFO underruns and display "flicker").
 365  *
 366  * A value of 5us seems to be a good balance; safe for very low end
 367  * platforms but not overly aggressive on lower latency configs.
 368  */
 369 static const int pessimal_latency_ns = 5000;
 370
 371 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 372         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 373
 374 static int vlv_get_fifo_size(struct drm_i915_private *dev_priv,
 375                               enum pipe pipe, int plane)
 376 {
 377         int sprite0_start, sprite1_start, size;
 378
 379         switch (pipe) {
 380                 uint32_t dsparb, dsparb2, dsparb3;
 381         case PIPE_A:
 382                 dsparb = I915_READ(DSPARB);
 383                 dsparb2 = I915_READ(DSPARB2);
 384                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 385                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 386                 break;
 387         case PIPE_B:
 388                 dsparb = I915_READ(DSPARB);
 389                 dsparb2 = I915_READ(DSPARB2);
 390                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 391                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 392                 break;
 393         case PIPE_C:
 394                 dsparb2 = I915_READ(DSPARB2);
 395                 dsparb3 = I915_READ(DSPARB3);
 396                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 397                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 398                 break;
 399         default:
 400                 return 0;
 401         }
 402
 403         switch (plane) {
 404         case 0:
 405                 size = sprite0_start;
 406                 break;
 407         case 1:
 408                 size = sprite1_start - sprite0_start;
 409                 break;
 410         case 2:
 411                 size = 512 - 1 - sprite1_start;
 412                 break;
 413         default:
 414                 return 0;
 415         }
 416
 417         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 418                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 419                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 420                       size);
 421
 422         return size;
 423 }
 424
 425 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 426 {
 427         uint32_t dsparb = I915_READ(DSPARB);
 428         int size;
 429
 430         size = dsparb & 0x7f;
 431         if (plane)
 432                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 433
 434         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 435                       plane ? "B" : "A", size);
 436
 437         return size;
 438 }
 439
 440 static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 441 {
 442         uint32_t dsparb = I915_READ(DSPARB);
 443         int size;
 444
 445         size = dsparb & 0x1ff;
 446         if (plane)
 447                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 448         size >>= 1; /* Convert to cachelines */
 449
 450         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 451                       plane ? "B" : "A", size);
 452
 453         return size;
 454 }
 455
 456 static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 457 {
 458         uint32_t dsparb = I915_READ(DSPARB);
 459         int size;
 460
 461         size = dsparb & 0x7f;
 462         size >>= 2; /* Convert to cachelines */
 463
 464         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 465                       plane ? "B" : "A",
 466                       size);
 467
 468         return size;
 469 }
 470
 471 /* Pineview has different values for various configs */
 472 static const struct intel_watermark_params pineview_display_wm = {
 473         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 474         .max_wm = PINEVIEW_MAX_WM,
 475         .default_wm = PINEVIEW_DFT_WM,
 476         .guard_size = PINEVIEW_GUARD_WM,
 477         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 478 };
 479 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 480         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 481         .max_wm = PINEVIEW_MAX_WM,
 482         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 483         .guard_size = PINEVIEW_GUARD_WM,
 484         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 485 };
 486 static const struct intel_watermark_params pineview_cursor_wm = {
 487         .fifo_size = PINEVIEW_CURSOR_FIFO,
 488         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 489         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 490         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 491         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 492 };
 493 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 494         .fifo_size = PINEVIEW_CURSOR_FIFO,
 495         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 496         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 497         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 498         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 499 };
 500 static const struct intel_watermark_params g4x_wm_info = {
 501         .fifo_size = G4X_FIFO_SIZE,
 502         .max_wm = G4X_MAX_WM,
 503         .default_wm = G4X_MAX_WM,
 504         .guard_size = 2,
 505         .cacheline_size = G4X_FIFO_LINE_SIZE,
 506 };
 507 static const struct intel_watermark_params g4x_cursor_wm_info = {
 508         .fifo_size = I965_CURSOR_FIFO,
 509         .max_wm = I965_CURSOR_MAX_WM,
 510         .default_wm = I965_CURSOR_DFT_WM,
 511         .guard_size = 2,
 512         .cacheline_size = G4X_FIFO_LINE_SIZE,
 513 };
 514 static const struct intel_watermark_params i965_cursor_wm_info = {
 515         .fifo_size = I965_CURSOR_FIFO,
 516         .max_wm = I965_CURSOR_MAX_WM,
 517         .default_wm = I965_CURSOR_DFT_WM,
 518         .guard_size = 2,
 519         .cacheline_size = I915_FIFO_LINE_SIZE,
 520 };
 521 static const struct intel_watermark_params i945_wm_info = {
 522         .fifo_size = I945_FIFO_SIZE,
 523         .max_wm = I915_MAX_WM,
 524         .default_wm = 1,
 525         .guard_size = 2,
 526         .cacheline_size = I915_FIFO_LINE_SIZE,
 527 };
 528 static const struct intel_watermark_params i915_wm_info = {
 529         .fifo_size = I915_FIFO_SIZE,
 530         .max_wm = I915_MAX_WM,
 531         .default_wm = 1,
 532         .guard_size = 2,
 533         .cacheline_size = I915_FIFO_LINE_SIZE,
 534 };
 535 static const struct intel_watermark_params i830_a_wm_info = {
 536         .fifo_size = I855GM_FIFO_SIZE,
 537         .max_wm = I915_MAX_WM,
 538         .default_wm = 1,
 539         .guard_size = 2,
 540         .cacheline_size = I830_FIFO_LINE_SIZE,
 541 };
 542 static const struct intel_watermark_params i830_bc_wm_info = {
 543         .fifo_size = I855GM_FIFO_SIZE,
 544         .max_wm = I915_MAX_WM/2,
 545         .default_wm = 1,
 546         .guard_size = 2,
 547         .cacheline_size = I830_FIFO_LINE_SIZE,
 548 };
 549 static const struct intel_watermark_params i845_wm_info = {
 550         .fifo_size = I830_FIFO_SIZE,
 551         .max_wm = I915_MAX_WM,
 552         .default_wm = 1,
 553         .guard_size = 2,
 554         .cacheline_size = I830_FIFO_LINE_SIZE,
 555 };
 556
 557 /**
 558  * intel_calculate_wm - calculate watermark level
 559  * @clock_in_khz: pixel clock
 560  * @wm: chip FIFO params
 561  * @cpp: bytes per pixel
 562  * @latency_ns: memory latency for the platform
 563  *
 564  * Calculate the watermark level (the level at which the display plane will
 565  * start fetching from memory again).  Each chip has a different display
 566  * FIFO size and allocation, so the caller needs to figure that out and pass
 567  * in the correct intel_watermark_params structure.
 568  *
 569  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 570  * on the pixel size.  When it reaches the watermark level, it'll start
 571  * fetching FIFO line sized based chunks from memory until the FIFO fills
 572  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 573  * will occur, and a display engine hang could result.
 574  */
 575 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 576                                         const struct intel_watermark_params *wm,
 577                                         int fifo_size, int cpp,
 578                                         unsigned long latency_ns)
 579 {
 580         long entries_required, wm_size;
 581
 582         /*
 583          * Note: we need to make sure we don't overflow for various clock &
 584          * latency values.
 585          * clocks go from a few thousand to several hundred thousand.
 586          * latency is usually a few thousand
 587          */
 588         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 589                 1000;
 590         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 591
 592         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 593
 594         wm_size = fifo_size - (entries_required + wm->guard_size);
 595
 596         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 597
 598         /* Don't promote wm_size to unsigned... */
 599         if (wm_size > (long)wm->max_wm)
 600                 wm_size = wm->max_wm;
 601         if (wm_size <= 0)
 602                 wm_size = wm->default_wm;
 603
 604         /*
 605          * Bspec seems to indicate that the value shouldn't be lower than
 606          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 607          * Lets go for 8 which is the burst size since certain platforms
 608          * already use a hardcoded 8 (which is what the spec says should be
 609          * done).
 610          */
 611         if (wm_size <= 8)
 612                 wm_size = 8;
 613
 614         return wm_size;
 615 }
 616
 617 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 618 {
 619         struct intel_crtc *crtc, *enabled = NULL;
 620
 621         for_each_intel_crtc(&dev_priv->drm, crtc) {
 622                 if (intel_crtc_active(crtc)) {
 623                         if (enabled)
 624                                 return NULL;
 625                         enabled = crtc;
 626                 }
 627         }
 628
 629         return enabled;
 630 }
 631
 632 static void pineview_update_wm(struct intel_crtc *unused_crtc)
 633 {
 634         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 635         struct intel_crtc *crtc;
 636         const struct cxsr_latency *latency;
 637         u32 reg;
 638         unsigned long wm;
 639
 640         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 641                                          dev_priv->is_ddr3,
 642                                          dev_priv->fsb_freq,
 643                                          dev_priv->mem_freq);
 644         if (!latency) {
 645                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 646                 intel_set_memory_cxsr(dev_priv, false);
 647                 return;
 648         }
 649
 650         crtc = single_enabled_crtc(dev_priv);
 651         if (crtc) {
 652                 const struct drm_display_mode *adjusted_mode =
 653                         &crtc->config->base.adjusted_mode;
 654                 const struct drm_framebuffer *fb =
 655                         crtc->base.primary->state->fb;
 656                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 657                 int clock = adjusted_mode->crtc_clock;
 658
 659                 /* Display SR */
 660                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 661                                         pineview_display_wm.fifo_size,
 662                                         cpp, latency->display_sr);
 663                 reg = I915_READ(DSPFW1);
 664                 reg &= ~DSPFW_SR_MASK;
 665                 reg |= FW_WM(wm, SR);
 666                 I915_WRITE(DSPFW1, reg);
 667                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 668
 669                 /* cursor SR */
 670                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 671                                         pineview_display_wm.fifo_size,
 672                                         cpp, latency->cursor_sr);
 673                 reg = I915_READ(DSPFW3);
 674                 reg &= ~DSPFW_CURSOR_SR_MASK;
 675                 reg |= FW_WM(wm, CURSOR_SR);
 676                 I915_WRITE(DSPFW3, reg);
 677
 678                 /* Display HPLL off SR */
 679                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 680                                         pineview_display_hplloff_wm.fifo_size,
 681                                         cpp, latency->display_hpll_disable);
 682                 reg = I915_READ(DSPFW3);
 683                 reg &= ~DSPFW_HPLL_SR_MASK;
 684                 reg |= FW_WM(wm, HPLL_SR);
 685                 I915_WRITE(DSPFW3, reg);
 686
 687                 /* cursor HPLL off SR */
 688                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 689                                         pineview_display_hplloff_wm.fifo_size,
 690                                         cpp, latency->cursor_hpll_disable);
 691                 reg = I915_READ(DSPFW3);
 692                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 693                 reg |= FW_WM(wm, HPLL_CURSOR);
 694                 I915_WRITE(DSPFW3, reg);
 695                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 696
 697                 intel_set_memory_cxsr(dev_priv, true);
 698         } else {
 699                 intel_set_memory_cxsr(dev_priv, false);
 700         }
 701 }
 702
 703 static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
 704                             int plane,
 705                             const struct intel_watermark_params *display,
 706                             int display_latency_ns,
 707                             const struct intel_watermark_params *cursor,
 708                             int cursor_latency_ns,
 709                             int *plane_wm,
 710                             int *cursor_wm)
 711 {
 712         struct intel_crtc *crtc;
 713         const struct drm_display_mode *adjusted_mode;
 714         const struct drm_framebuffer *fb;
 715         int htotal, hdisplay, clock, cpp;
 716         int line_time_us, line_count;
 717         int entries, tlb_miss;
 718
 719         crtc = intel_get_crtc_for_plane(dev_priv, plane);
 720         if (!intel_crtc_active(crtc)) {
 721                 *cursor_wm = cursor->guard_size;
 722                 *plane_wm = display->guard_size;
 723                 return false;
 724         }
 725
 726         adjusted_mode = &crtc->config->base.adjusted_mode;
 727         fb = crtc->base.primary->state->fb;
 728         clock = adjusted_mode->crtc_clock;
 729         htotal = adjusted_mode->crtc_htotal;
 730         hdisplay = crtc->config->pipe_src_w;
 731         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 732
 733         /* Use the small buffer method to calculate plane watermark */
 734         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 735         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 736         if (tlb_miss > 0)
 737                 entries += tlb_miss;
 738         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 739         *plane_wm = entries + display->guard_size;
 740         if (*plane_wm > (int)display->max_wm)
 741                 *plane_wm = display->max_wm;
 742
 743         /* Use the large buffer method to calculate cursor watermark */
 744         line_time_us = max(htotal * 1000 / clock, 1);
 745         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 746         entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
 747         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 748         if (tlb_miss > 0)
 749                 entries += tlb_miss;
 750         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 751         *cursor_wm = entries + cursor->guard_size;
 752         if (*cursor_wm > (int)cursor->max_wm)
 753                 *cursor_wm = (int)cursor->max_wm;
 754
 755         return true;
 756 }
 757
 758 /*
 759  * Check the wm result.
 760  *
 761  * If any calculated watermark values is larger than the maximum value that
 762  * can be programmed into the associated watermark register, that watermark
 763  * must be disabled.
 764  */
 765 static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
 766                            int display_wm, int cursor_wm,
 767                            const struct intel_watermark_params *display,
 768                            const struct intel_watermark_params *cursor)
 769 {
 770         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 771                       display_wm, cursor_wm);
 772
 773         if (display_wm > display->max_wm) {
 774                 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
 775                               display_wm, display->max_wm);
 776                 return false;
 777         }
 778
 779         if (cursor_wm > cursor->max_wm) {
 780                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
 781                               cursor_wm, cursor->max_wm);
 782                 return false;
 783         }
 784
 785         if (!(display_wm || cursor_wm)) {
 786                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 787                 return false;
 788         }
 789
 790         return true;
 791 }
 792
 793 static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
 794                              int plane,
 795                              int latency_ns,
 796                              const struct intel_watermark_params *display,
 797                              const struct intel_watermark_params *cursor,
 798                              int *display_wm, int *cursor_wm)
 799 {
 800         struct intel_crtc *crtc;
 801         const struct drm_display_mode *adjusted_mode;
 802         const struct drm_framebuffer *fb;
 803         int hdisplay, htotal, cpp, clock;
 804         unsigned long line_time_us;
 805         int line_count, line_size;
 806         int small, large;
 807         int entries;
 808
 809         if (!latency_ns) {
 810                 *display_wm = *cursor_wm = 0;
 811                 return false;
 812         }
 813
 814         crtc = intel_get_crtc_for_plane(dev_priv, plane);
 815         adjusted_mode = &crtc->config->base.adjusted_mode;
 816         fb = crtc->base.primary->state->fb;
 817         clock = adjusted_mode->crtc_clock;
 818         htotal = adjusted_mode->crtc_htotal;
 819         hdisplay = crtc->config->pipe_src_w;
 820         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 821
 822         line_time_us = max(htotal * 1000 / clock, 1);
 823         line_count = (latency_ns / line_time_us + 1000) / 1000;
 824         line_size = hdisplay * cpp;
 825
 826         /* Use the minimum of the small and large buffer method for primary */
 827         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 828         large = line_count * line_size;
 829
 830         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 831         *display_wm = entries + display->guard_size;
 832
 833         /* calculate the self-refresh watermark for display cursor */
 834         entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
 835         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 836         *cursor_wm = entries + cursor->guard_size;
 837
 838         return g4x_check_srwm(dev_priv,
 839                               *display_wm, *cursor_wm,
 840                               display, cursor);
 841 }
 842
 843 #define FW_WM_VLV(value, plane) \
 844         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 845
 846 static void vlv_write_wm_values(struct intel_crtc *crtc,
 847                                 const struct vlv_wm_values *wm)
 848 {
 849         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 850         enum pipe pipe = crtc->pipe;
 851
 852         I915_WRITE(VLV_DDL(pipe),
 853                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 854                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 855                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 856                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 857
 858         I915_WRITE(DSPFW1,
 859                    FW_WM(wm->sr.plane, SR) |
 860                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 861                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 862                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 863         I915_WRITE(DSPFW2,
 864                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 865                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 866                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 867         I915_WRITE(DSPFW3,
 868                    FW_WM(wm->sr.cursor, CURSOR_SR));
 869
 870         if (IS_CHERRYVIEW(dev_priv)) {
 871                 I915_WRITE(DSPFW7_CHV,
 872                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 873                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 874                 I915_WRITE(DSPFW8_CHV,
 875                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 876                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 877                 I915_WRITE(DSPFW9_CHV,
 878                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 879                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 880                 I915_WRITE(DSPHOWM,
 881                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 882                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 883                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 884                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 885                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 886                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 887                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 888                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 889                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 890                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 891         } else {
 892                 I915_WRITE(DSPFW7,
 893                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 894                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 895                 I915_WRITE(DSPHOWM,
 896                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 897                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 898                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 899                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 900                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 901                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 902                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 903         }
 904
 905         /* zero (unused) WM1 watermarks */
 906         I915_WRITE(DSPFW4, 0);
 907         I915_WRITE(DSPFW5, 0);
 908         I915_WRITE(DSPFW6, 0);
 909         I915_WRITE(DSPHOWM1, 0);
 910
 911         POSTING_READ(DSPFW1);
 912 }
 913
 914 #undef FW_WM_VLV
 915
 916 enum vlv_wm_level {
 917         VLV_WM_LEVEL_PM2,
 918         VLV_WM_LEVEL_PM5,
 919         VLV_WM_LEVEL_DDR_DVFS,
 920 };
 921
 922 /* latency must be in 0.1us units. */
 923 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 924                                    unsigned int pipe_htotal,
 925                                    unsigned int horiz_pixels,
 926                                    unsigned int cpp,
 927                                    unsigned int latency)
 928 {
 929         unsigned int ret;
 930
 931         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 932         ret = (ret + 1) * horiz_pixels * cpp;
 933         ret = DIV_ROUND_UP(ret, 64);
 934
 935         return ret;
 936 }
 937
 938 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
 939 {
 940         /* all latencies in usec */
 941         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 942
 943         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 944
 945         if (IS_CHERRYVIEW(dev_priv)) {
 946                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 947                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 948
 949                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 950         }
 951 }
 952
 953 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 954                                      struct intel_crtc *crtc,
 955                                      const struct intel_plane_state *state,
 956                                      int level)
 957 {
 958         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 959         int clock, htotal, cpp, width, wm;
 960
 961         if (dev_priv->wm.pri_latency[level] == 0)
 962                 return USHRT_MAX;
 963
 964         if (!state->base.visible)
 965                 return 0;
 966
 967         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 968         clock = crtc->config->base.adjusted_mode.crtc_clock;
 969         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 970         width = crtc->config->pipe_src_w;
 971         if (WARN_ON(htotal == 0))
 972                 htotal = 1;
 973
 974         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 975                 /*
 976                  * FIXME the formula gives values that are
 977                  * too big for the cursor FIFO, and hence we
 978                  * would never be able to use cursors. For
 979                  * now just hardcode the watermark.
 980                  */
 981                 wm = 63;
 982         } else {
 983                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 984                                     dev_priv->wm.pri_latency[level] * 10);
 985         }
 986
 987         return min_t(int, wm, USHRT_MAX);
 988 }
 989
 990 static void vlv_compute_fifo(struct intel_crtc *crtc)
 991 {
 992         struct drm_device *dev = crtc->base.dev;
 993         struct vlv_wm_state *wm_state = &crtc->wm_state;
 994         struct intel_plane *plane;
 995         unsigned int total_rate = 0;
 996         const int fifo_size = 512 - 1;
 997         int fifo_extra, fifo_left = fifo_size;
 998
 999         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1000                 struct intel_plane_state *state =
1001                         to_intel_plane_state(plane->base.state);
1002
1003                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1004                         continue;
1005
1006                 if (state->base.visible) {
1007                         wm_state->num_active_planes++;
1008                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1009                 }
1010         }
1011
1012         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1013                 struct intel_plane_state *state =
1014                         to_intel_plane_state(plane->base.state);
1015                 unsigned int rate;
1016
1017                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1018                         plane->wm.fifo_size = 63;
1019                         continue;
1020                 }
1021
1022                 if (!state->base.visible) {
1023                         plane->wm.fifo_size = 0;
1024                         continue;
1025                 }
1026
1027                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1028                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1029                 fifo_left -= plane->wm.fifo_size;
1030         }
1031
1032         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1033
1034         /* spread the remainder evenly */
1035         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1036                 int plane_extra;
1037
1038                 if (fifo_left == 0)
1039                         break;
1040
1041                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1042                         continue;
1043
1044                 /* give it all to the first plane if none are active */
1045                 if (plane->wm.fifo_size == 0 &&
1046                     wm_state->num_active_planes)
1047                         continue;
1048
1049                 plane_extra = min(fifo_extra, fifo_left);
1050                 plane->wm.fifo_size += plane_extra;
1051                 fifo_left -= plane_extra;
1052         }
1053
1054         WARN_ON(fifo_left != 0);
1055 }
1056
1057 static void vlv_invert_wms(struct intel_crtc *crtc)
1058 {
1059         struct vlv_wm_state *wm_state = &crtc->wm_state;
1060         int level;
1061
1062         for (level = 0; level < wm_state->num_levels; level++) {
1063                 struct drm_device *dev = crtc->base.dev;
1064                 const int sr_fifo_size =
1065                         INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
1066                 struct intel_plane *plane;
1067
1068                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1069                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1070
1071                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1072                         switch (plane->base.type) {
1073                                 int sprite;
1074                         case DRM_PLANE_TYPE_CURSOR:
1075                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1076                                         wm_state->wm[level].cursor;
1077                                 break;
1078                         case DRM_PLANE_TYPE_PRIMARY:
1079                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1080                                         wm_state->wm[level].primary;
1081                                 break;
1082                         case DRM_PLANE_TYPE_OVERLAY:
1083                                 sprite = plane->plane;
1084                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1085                                         wm_state->wm[level].sprite[sprite];
1086                                 break;
1087                         }
1088                 }
1089         }
1090 }
1091
1092 static void vlv_compute_wm(struct intel_crtc *crtc)
1093 {
1094         struct drm_device *dev = crtc->base.dev;
1095         struct drm_i915_private *dev_priv = to_i915(dev);
1096         struct vlv_wm_state *wm_state = &crtc->wm_state;
1097         struct intel_plane *plane;
1098         int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1099         int level;
1100
1101         memset(wm_state, 0, sizeof(*wm_state));
1102
1103         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1104         wm_state->num_levels = dev_priv->wm.max_level + 1;
1105
1106         wm_state->num_active_planes = 0;
1107
1108         vlv_compute_fifo(crtc);
1109
1110         if (wm_state->num_active_planes != 1)
1111                 wm_state->cxsr = false;
1112
1113         if (wm_state->cxsr) {
1114                 for (level = 0; level < wm_state->num_levels; level++) {
1115                         wm_state->sr[level].plane = sr_fifo_size;
1116                         wm_state->sr[level].cursor = 63;
1117                 }
1118         }
1119
1120         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1121                 struct intel_plane_state *state =
1122                         to_intel_plane_state(plane->base.state);
1123
1124                 if (!state->base.visible)
1125                         continue;
1126
1127                 /* normal watermarks */
1128                 for (level = 0; level < wm_state->num_levels; level++) {
1129                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1130                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1131
1132                         /* hack */
1133                         if (WARN_ON(level == 0 && wm > max_wm))
1134                                 wm = max_wm;
1135
1136                         if (wm > plane->wm.fifo_size)
1137                                 break;
1138
1139                         switch (plane->base.type) {
1140                                 int sprite;
1141                         case DRM_PLANE_TYPE_CURSOR:
1142                                 wm_state->wm[level].cursor = wm;
1143                                 break;
1144                         case DRM_PLANE_TYPE_PRIMARY:
1145                                 wm_state->wm[level].primary = wm;
1146                                 break;
1147                         case DRM_PLANE_TYPE_OVERLAY:
1148                                 sprite = plane->plane;
1149                                 wm_state->wm[level].sprite[sprite] = wm;
1150                                 break;
1151                         }
1152                 }
1153
1154                 wm_state->num_levels = level;
1155
1156                 if (!wm_state->cxsr)
1157                         continue;
1158
1159                 /* maxfifo watermarks */
1160                 switch (plane->base.type) {
1161                         int sprite, level;
1162                 case DRM_PLANE_TYPE_CURSOR:
1163                         for (level = 0; level < wm_state->num_levels; level++)
1164                                 wm_state->sr[level].cursor =
1165                                         wm_state->wm[level].cursor;
1166                         break;
1167                 case DRM_PLANE_TYPE_PRIMARY:
1168                         for (level = 0; level < wm_state->num_levels; level++)
1169                                 wm_state->sr[level].plane =
1170                                         min(wm_state->sr[level].plane,
1171                                             wm_state->wm[level].primary);
1172                         break;
1173                 case DRM_PLANE_TYPE_OVERLAY:
1174                         sprite = plane->plane;
1175                         for (level = 0; level < wm_state->num_levels; level++)
1176                                 wm_state->sr[level].plane =
1177                                         min(wm_state->sr[level].plane,
1178                                             wm_state->wm[level].sprite[sprite]);
1179                         break;
1180                 }
1181         }
1182
1183         /* clear any (partially) filled invalid levels */
1184         for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
1185                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1186                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1187         }
1188
1189         vlv_invert_wms(crtc);
1190 }
1191
1192 #define VLV_FIFO(plane, value) \
1193         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1194
1195 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1196 {
1197         struct drm_device *dev = crtc->base.dev;
1198         struct drm_i915_private *dev_priv = to_i915(dev);
1199         struct intel_plane *plane;
1200         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1201
1202         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1203                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1204                         WARN_ON(plane->wm.fifo_size != 63);
1205                         continue;
1206                 }
1207
1208                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1209                         sprite0_start = plane->wm.fifo_size;
1210                 else if (plane->plane == 0)
1211                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1212                 else
1213                         fifo_size = sprite1_start + plane->wm.fifo_size;
1214         }
1215
1216         WARN_ON(fifo_size != 512 - 1);
1217
1218         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1219                       pipe_name(crtc->pipe), sprite0_start,
1220                       sprite1_start, fifo_size);
1221
1222         switch (crtc->pipe) {
1223                 uint32_t dsparb, dsparb2, dsparb3;
1224         case PIPE_A:
1225                 dsparb = I915_READ(DSPARB);
1226                 dsparb2 = I915_READ(DSPARB2);
1227
1228                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1229                             VLV_FIFO(SPRITEB, 0xff));
1230                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1231                            VLV_FIFO(SPRITEB, sprite1_start));
1232
1233                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1234                              VLV_FIFO(SPRITEB_HI, 0x1));
1235                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1236                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1237
1238                 I915_WRITE(DSPARB, dsparb);
1239                 I915_WRITE(DSPARB2, dsparb2);
1240                 break;
1241         case PIPE_B:
1242                 dsparb = I915_READ(DSPARB);
1243                 dsparb2 = I915_READ(DSPARB2);
1244
1245                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1246                             VLV_FIFO(SPRITED, 0xff));
1247                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1248                            VLV_FIFO(SPRITED, sprite1_start));
1249
1250                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1251                              VLV_FIFO(SPRITED_HI, 0xff));
1252                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1253                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1254
1255                 I915_WRITE(DSPARB, dsparb);
1256                 I915_WRITE(DSPARB2, dsparb2);
1257                 break;
1258         case PIPE_C:
1259                 dsparb3 = I915_READ(DSPARB3);
1260                 dsparb2 = I915_READ(DSPARB2);
1261
1262                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1263                              VLV_FIFO(SPRITEF, 0xff));
1264                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1265                             VLV_FIFO(SPRITEF, sprite1_start));
1266
1267                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1268                              VLV_FIFO(SPRITEF_HI, 0xff));
1269                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1270                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1271
1272                 I915_WRITE(DSPARB3, dsparb3);
1273                 I915_WRITE(DSPARB2, dsparb2);
1274                 break;
1275         default:
1276                 break;
1277         }
1278 }
1279
1280 #undef VLV_FIFO
1281
1282 static void vlv_merge_wm(struct drm_device *dev,
1283                          struct vlv_wm_values *wm)
1284 {
1285         struct intel_crtc *crtc;
1286         int num_active_crtcs = 0;
1287
1288         wm->level = to_i915(dev)->wm.max_level;
1289         wm->cxsr = true;
1290
1291         for_each_intel_crtc(dev, crtc) {
1292                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1293
1294                 if (!crtc->active)
1295                         continue;
1296
1297                 if (!wm_state->cxsr)
1298                         wm->cxsr = false;
1299
1300                 num_active_crtcs++;
1301                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1302         }
1303
1304         if (num_active_crtcs != 1)
1305                 wm->cxsr = false;
1306
1307         if (num_active_crtcs > 1)
1308                 wm->level = VLV_WM_LEVEL_PM2;
1309
1310         for_each_intel_crtc(dev, crtc) {
1311                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1312                 enum pipe pipe = crtc->pipe;
1313
1314                 if (!crtc->active)
1315                         continue;
1316
1317                 wm->pipe[pipe] = wm_state->wm[wm->level];
1318                 if (wm->cxsr)
1319                         wm->sr = wm_state->sr[wm->level];
1320
1321                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1322                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1323                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1324                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1325         }
1326 }
1327
1328 static void vlv_update_wm(struct intel_crtc *crtc)
1329 {
1330         struct drm_device *dev = crtc->base.dev;
1331         struct drm_i915_private *dev_priv = to_i915(dev);
1332         enum pipe pipe = crtc->pipe;
1333         struct vlv_wm_values wm = {};
1334
1335         vlv_compute_wm(crtc);
1336         vlv_merge_wm(dev, &wm);
1337
1338         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1339                 /* FIXME should be part of crtc atomic commit */
1340                 vlv_pipe_set_fifo_size(crtc);
1341                 return;
1342         }
1343
1344         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1345             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1346                 chv_set_memory_dvfs(dev_priv, false);
1347
1348         if (wm.level < VLV_WM_LEVEL_PM5 &&
1349             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1350                 chv_set_memory_pm5(dev_priv, false);
1351
1352         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1353                 intel_set_memory_cxsr(dev_priv, false);
1354
1355         /* FIXME should be part of crtc atomic commit */
1356         vlv_pipe_set_fifo_size(crtc);
1357
1358         vlv_write_wm_values(crtc, &wm);
1359
1360         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1361                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1362                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1363                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1364                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1365
1366         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1367                 intel_set_memory_cxsr(dev_priv, true);
1368
1369         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1370             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1371                 chv_set_memory_pm5(dev_priv, true);
1372
1373         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1374             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1375                 chv_set_memory_dvfs(dev_priv, true);
1376
1377         dev_priv->wm.vlv = wm;
1378 }
1379
1380 #define single_plane_enabled(mask) is_power_of_2(mask)
1381
1382 static void g4x_update_wm(struct intel_crtc *crtc)
1383 {
1384         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1385         static const int sr_latency_ns = 12000;
1386         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1387         int plane_sr, cursor_sr;
1388         unsigned int enabled = 0;
1389         bool cxsr_enabled;
1390
1391         if (g4x_compute_wm0(dev_priv, PIPE_A,
1392                             &g4x_wm_info, pessimal_latency_ns,
1393                             &g4x_cursor_wm_info, pessimal_latency_ns,
1394                             &planea_wm, &cursora_wm))
1395                 enabled |= 1 << PIPE_A;
1396
1397         if (g4x_compute_wm0(dev_priv, PIPE_B,
1398                             &g4x_wm_info, pessimal_latency_ns,
1399                             &g4x_cursor_wm_info, pessimal_latency_ns,
1400                             &planeb_wm, &cursorb_wm))
1401                 enabled |= 1 << PIPE_B;
1402
1403         if (single_plane_enabled(enabled) &&
1404             g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
1405                              sr_latency_ns,
1406                              &g4x_wm_info,
1407                              &g4x_cursor_wm_info,
1408                              &plane_sr, &cursor_sr)) {
1409                 cxsr_enabled = true;
1410         } else {
1411                 cxsr_enabled = false;
1412                 intel_set_memory_cxsr(dev_priv, false);
1413                 plane_sr = cursor_sr = 0;
1414         }
1415
1416         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1417                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1418                       planea_wm, cursora_wm,
1419                       planeb_wm, cursorb_wm,
1420                       plane_sr, cursor_sr);
1421
1422         I915_WRITE(DSPFW1,
1423                    FW_WM(plane_sr, SR) |
1424                    FW_WM(cursorb_wm, CURSORB) |
1425                    FW_WM(planeb_wm, PLANEB) |
1426                    FW_WM(planea_wm, PLANEA));
1427         I915_WRITE(DSPFW2,
1428                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1429                    FW_WM(cursora_wm, CURSORA));
1430         /* HPLL off in SR has some issues on G4x... disable it */
1431         I915_WRITE(DSPFW3,
1432                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1433                    FW_WM(cursor_sr, CURSOR_SR));
1434
1435         if (cxsr_enabled)
1436                 intel_set_memory_cxsr(dev_priv, true);
1437 }
1438
1439 static void i965_update_wm(struct intel_crtc *unused_crtc)
1440 {
1441         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1442         struct intel_crtc *crtc;
1443         int srwm = 1;
1444         int cursor_sr = 16;
1445         bool cxsr_enabled;
1446
1447         /* Calc sr entries for one plane configs */
1448         crtc = single_enabled_crtc(dev_priv);
1449         if (crtc) {
1450                 /* self-refresh has much higher latency */
1451                 static const int sr_latency_ns = 12000;
1452                 const struct drm_display_mode *adjusted_mode =
1453                         &crtc->config->base.adjusted_mode;
1454                 const struct drm_framebuffer *fb =
1455                         crtc->base.primary->state->fb;
1456                 int clock = adjusted_mode->crtc_clock;
1457                 int htotal = adjusted_mode->crtc_htotal;
1458                 int hdisplay = crtc->config->pipe_src_w;
1459                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1460                 unsigned long line_time_us;
1461                 int entries;
1462
1463                 line_time_us = max(htotal * 1000 / clock, 1);
1464
1465                 /* Use ns/us then divide to preserve precision */
1466                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1467                         cpp * hdisplay;
1468                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1469                 srwm = I965_FIFO_SIZE - entries;
1470                 if (srwm < 0)
1471                         srwm = 1;
1472                 srwm &= 0x1ff;
1473                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1474                               entries, srwm);
1475
1476                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1477                         cpp * crtc->base.cursor->state->crtc_w;
1478                 entries = DIV_ROUND_UP(entries,
1479                                           i965_cursor_wm_info.cacheline_size);
1480                 cursor_sr = i965_cursor_wm_info.fifo_size -
1481                         (entries + i965_cursor_wm_info.guard_size);
1482
1483                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1484                         cursor_sr = i965_cursor_wm_info.max_wm;
1485
1486                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1487                               "cursor %d\n", srwm, cursor_sr);
1488
1489                 cxsr_enabled = true;
1490         } else {
1491                 cxsr_enabled = false;
1492                 /* Turn off self refresh if both pipes are enabled */
1493                 intel_set_memory_cxsr(dev_priv, false);
1494         }
1495
1496         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1497                       srwm);
1498
1499         /* 965 has limitations... */
1500         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1501                    FW_WM(8, CURSORB) |
1502                    FW_WM(8, PLANEB) |
1503                    FW_WM(8, PLANEA));
1504         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1505                    FW_WM(8, PLANEC_OLD));
1506         /* update cursor SR watermark */
1507         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1508
1509         if (cxsr_enabled)
1510                 intel_set_memory_cxsr(dev_priv, true);
1511 }
1512
1513 #undef FW_WM
1514
1515 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
1516 {
1517         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1518         const struct intel_watermark_params *wm_info;
1519         uint32_t fwater_lo;
1520         uint32_t fwater_hi;
1521         int cwm, srwm = 1;
1522         int fifo_size;
1523         int planea_wm, planeb_wm;
1524         struct intel_crtc *crtc, *enabled = NULL;
1525
1526         if (IS_I945GM(dev_priv))
1527                 wm_info = &i945_wm_info;
1528         else if (!IS_GEN2(dev_priv))
1529                 wm_info = &i915_wm_info;
1530         else
1531                 wm_info = &i830_a_wm_info;
1532
1533         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
1534         crtc = intel_get_crtc_for_plane(dev_priv, 0);
1535         if (intel_crtc_active(crtc)) {
1536                 const struct drm_display_mode *adjusted_mode =
1537                         &crtc->config->base.adjusted_mode;
1538                 const struct drm_framebuffer *fb =
1539                         crtc->base.primary->state->fb;
1540                 int cpp;
1541
1542                 if (IS_GEN2(dev_priv))
1543                         cpp = 4;
1544                 else
1545                         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1546
1547                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1548                                                wm_info, fifo_size, cpp,
1549                                                pessimal_latency_ns);
1550                 enabled = crtc;
1551         } else {
1552                 planea_wm = fifo_size - wm_info->guard_size;
1553                 if (planea_wm > (long)wm_info->max_wm)
1554                         planea_wm = wm_info->max_wm;
1555         }
1556
1557         if (IS_GEN2(dev_priv))
1558                 wm_info = &i830_bc_wm_info;
1559
1560         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
1561         crtc = intel_get_crtc_for_plane(dev_priv, 1);
1562         if (intel_crtc_active(crtc)) {
1563                 const struct drm_display_mode *adjusted_mode =
1564                         &crtc->config->base.adjusted_mode;
1565                 const struct drm_framebuffer *fb =
1566                         crtc->base.primary->state->fb;
1567                 int cpp;
1568
1569                 if (IS_GEN2(dev_priv))
1570                         cpp = 4;
1571                 else
1572                         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1573
1574                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1575                                                wm_info, fifo_size, cpp,
1576                                                pessimal_latency_ns);
1577                 if (enabled == NULL)
1578                         enabled = crtc;
1579                 else
1580                         enabled = NULL;
1581         } else {
1582                 planeb_wm = fifo_size - wm_info->guard_size;
1583                 if (planeb_wm > (long)wm_info->max_wm)
1584                         planeb_wm = wm_info->max_wm;
1585         }
1586
1587         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1588
1589         if (IS_I915GM(dev_priv) && enabled) {
1590                 struct drm_i915_gem_object *obj;
1591
1592                 obj = intel_fb_obj(enabled->base.primary->state->fb);
1593
1594                 /* self-refresh seems busted with untiled */
1595                 if (!i915_gem_object_is_tiled(obj))
1596                         enabled = NULL;
1597         }
1598
1599         /*
1600          * Overlay gets an aggressive default since video jitter is bad.
1601          */
1602         cwm = 2;
1603
1604         /* Play safe and disable self-refresh before adjusting watermarks. */
1605         intel_set_memory_cxsr(dev_priv, false);
1606
1607         /* Calc sr entries for one plane configs */
1608         if (HAS_FW_BLC(dev_priv) && enabled) {
1609                 /* self-refresh has much higher latency */
1610                 static const int sr_latency_ns = 6000;
1611                 const struct drm_display_mode *adjusted_mode =
1612                         &enabled->config->base.adjusted_mode;
1613                 const struct drm_framebuffer *fb =
1614                         enabled->base.primary->state->fb;
1615                 int clock = adjusted_mode->crtc_clock;
1616                 int htotal = adjusted_mode->crtc_htotal;
1617                 int hdisplay = enabled->config->pipe_src_w;
1618                 int cpp;
1619                 unsigned long line_time_us;
1620                 int entries;
1621
1622                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
1623                         cpp = 4;
1624                 else
1625                         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1626
1627                 line_time_us = max(htotal * 1000 / clock, 1);
1628
1629                 /* Use ns/us then divide to preserve precision */
1630                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1631                         cpp * hdisplay;
1632                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1633                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1634                 srwm = wm_info->fifo_size - entries;
1635                 if (srwm < 0)
1636                         srwm = 1;
1637
1638                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1639                         I915_WRITE(FW_BLC_SELF,
1640                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1641                 else
1642                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1643         }
1644
1645         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1646                       planea_wm, planeb_wm, cwm, srwm);
1647
1648         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1649         fwater_hi = (cwm & 0x1f);
1650
1651         /* Set request length to 8 cachelines per fetch */
1652         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1653         fwater_hi = fwater_hi | (1 << 8);
1654
1655         I915_WRITE(FW_BLC, fwater_lo);
1656         I915_WRITE(FW_BLC2, fwater_hi);
1657
1658         if (enabled)
1659                 intel_set_memory_cxsr(dev_priv, true);
1660 }
1661
1662 static void i845_update_wm(struct intel_crtc *unused_crtc)
1663 {
1664         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1665         struct intel_crtc *crtc;
1666         const struct drm_display_mode *adjusted_mode;
1667         uint32_t fwater_lo;
1668         int planea_wm;
1669
1670         crtc = single_enabled_crtc(dev_priv);
1671         if (crtc == NULL)
1672                 return;
1673
1674         adjusted_mode = &crtc->config->base.adjusted_mode;
1675         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1676                                        &i845_wm_info,
1677                                        dev_priv->display.get_fifo_size(dev_priv, 0),
1678                                        4, pessimal_latency_ns);
1679         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1680         fwater_lo |= (3<<8) | planea_wm;
1681
1682         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1683
1684         I915_WRITE(FW_BLC, fwater_lo);
1685 }
1686
1687 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1688 {
1689         uint32_t pixel_rate;
1690
1691         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1692
1693         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1694          * adjust the pixel_rate here. */
1695
1696         if (pipe_config->pch_pfit.enabled) {
1697                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1698                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1699
1700                 pipe_w = pipe_config->pipe_src_w;
1701                 pipe_h = pipe_config->pipe_src_h;
1702
1703                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1704                 pfit_h = pfit_size & 0xFFFF;
1705                 if (pipe_w < pfit_w)
1706                         pipe_w = pfit_w;
1707                 if (pipe_h < pfit_h)
1708                         pipe_h = pfit_h;
1709
1710                 if (WARN_ON(!pfit_w || !pfit_h))
1711                         return pixel_rate;
1712
1713                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1714                                      pfit_w * pfit_h);
1715         }
1716
1717         return pixel_rate;
1718 }
1719
1720 /* latency must be in 0.1us units. */
1721 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1722 {
1723         uint64_t ret;
1724
1725         if (WARN(latency == 0, "Latency value missing\n"))
1726                 return UINT_MAX;
1727
1728         ret = (uint64_t) pixel_rate * cpp * latency;
1729         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1730
1731         return ret;
1732 }
1733
1734 /* latency must be in 0.1us units. */
1735 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1736                                uint32_t horiz_pixels, uint8_t cpp,
1737                                uint32_t latency)
1738 {
1739         uint32_t ret;
1740
1741         if (WARN(latency == 0, "Latency value missing\n"))
1742                 return UINT_MAX;
1743         if (WARN_ON(!pipe_htotal))
1744                 return UINT_MAX;
1745
1746         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1747         ret = (ret + 1) * horiz_pixels * cpp;
1748         ret = DIV_ROUND_UP(ret, 64) + 2;
1749         return ret;
1750 }
1751
1752 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1753                            uint8_t cpp)
1754 {
1755         /*
1756          * Neither of these should be possible since this function shouldn't be
1757          * called if the CRTC is off or the plane is invisible.  But let's be
1758          * extra paranoid to avoid a potential divide-by-zero if we screw up
1759          * elsewhere in the driver.
1760          */
1761         if (WARN_ON(!cpp))
1762                 return 0;
1763         if (WARN_ON(!horiz_pixels))
1764                 return 0;
1765
1766         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1767 }
1768
1769 struct ilk_wm_maximums {
1770         uint16_t pri;
1771         uint16_t spr;
1772         uint16_t cur;
1773         uint16_t fbc;
1774 };
1775
1776 /*
1777  * For both WM_PIPE and WM_LP.
1778  * mem_value must be in 0.1us units.
1779  */
1780 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1781                                    const struct intel_plane_state *pstate,
1782                                    uint32_t mem_value,
1783                                    bool is_lp)
1784 {
1785         int cpp = pstate->base.fb ?
1786                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1787         uint32_t method1, method2;
1788
1789         if (!cstate->base.active || !pstate->base.visible)
1790                 return 0;
1791
1792         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1793
1794         if (!is_lp)
1795                 return method1;
1796
1797         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1798                                  cstate->base.adjusted_mode.crtc_htotal,
1799                                  drm_rect_width(&pstate->base.dst),
1800                                  cpp, mem_value);
1801
1802         return min(method1, method2);
1803 }
1804
1805 /*
1806  * For both WM_PIPE and WM_LP.
1807  * mem_value must be in 0.1us units.
1808  */
1809 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1810                                    const struct intel_plane_state *pstate,
1811                                    uint32_t mem_value)
1812 {
1813         int cpp = pstate->base.fb ?
1814                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1815         uint32_t method1, method2;
1816
1817         if (!cstate->base.active || !pstate->base.visible)
1818                 return 0;
1819
1820         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1821         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1822                                  cstate->base.adjusted_mode.crtc_htotal,
1823                                  drm_rect_width(&pstate->base.dst),
1824                                  cpp, mem_value);
1825         return min(method1, method2);
1826 }
1827
1828 /*
1829  * For both WM_PIPE and WM_LP.
1830  * mem_value must be in 0.1us units.
1831  */
1832 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1833                                    const struct intel_plane_state *pstate,
1834                                    uint32_t mem_value)
1835 {
1836         /*
1837          * We treat the cursor plane as always-on for the purposes of watermark
1838          * calculation.  Until we have two-stage watermark programming merged,
1839          * this is necessary to avoid flickering.
1840          */
1841         int cpp = 4;
1842         int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1843
1844         if (!cstate->base.active)
1845                 return 0;
1846
1847         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1848                               cstate->base.adjusted_mode.crtc_htotal,
1849                               width, cpp, mem_value);
1850 }
1851
1852 /* Only for WM_LP. */
1853 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1854                                    const struct intel_plane_state *pstate,
1855                                    uint32_t pri_val)
1856 {
1857         int cpp = pstate->base.fb ?
1858                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1859
1860         if (!cstate->base.active || !pstate->base.visible)
1861                 return 0;
1862
1863         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1864 }
1865
1866 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1867 {
1868         if (INTEL_INFO(dev)->gen >= 8)
1869                 return 3072;
1870         else if (INTEL_INFO(dev)->gen >= 7)
1871                 return 768;
1872         else
1873                 return 512;
1874 }
1875
1876 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1877                                          int level, bool is_sprite)
1878 {
1879         if (INTEL_INFO(dev)->gen >= 8)
1880                 /* BDW primary/sprite plane watermarks */
1881                 return level == 0 ? 255 : 2047;
1882         else if (INTEL_INFO(dev)->gen >= 7)
1883                 /* IVB/HSW primary/sprite plane watermarks */
1884                 return level == 0 ? 127 : 1023;
1885         else if (!is_sprite)
1886                 /* ILK/SNB primary plane watermarks */
1887                 return level == 0 ? 127 : 511;
1888         else
1889                 /* ILK/SNB sprite plane watermarks */
1890                 return level == 0 ? 63 : 255;
1891 }
1892
1893 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1894                                           int level)
1895 {
1896         if (INTEL_INFO(dev)->gen >= 7)
1897                 return level == 0 ? 63 : 255;
1898         else
1899                 return level == 0 ? 31 : 63;
1900 }
1901
1902 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1903 {
1904         if (INTEL_INFO(dev)->gen >= 8)
1905                 return 31;
1906         else
1907                 return 15;
1908 }
1909
1910 /* Calculate the maximum primary/sprite plane watermark */
1911 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1912                                      int level,
1913                                      const struct intel_wm_config *config,
1914                                      enum intel_ddb_partitioning ddb_partitioning,
1915                                      bool is_sprite)
1916 {
1917         unsigned int fifo_size = ilk_display_fifo_size(dev);
1918
1919         /* if sprites aren't enabled, sprites get nothing */
1920         if (is_sprite && !config->sprites_enabled)
1921                 return 0;
1922
1923         /* HSW allows LP1+ watermarks even with multiple pipes */
1924         if (level == 0 || config->num_pipes_active > 1) {
1925                 fifo_size /= INTEL_INFO(to_i915(dev))->num_pipes;
1926
1927                 /*
1928                  * For some reason the non self refresh
1929                  * FIFO size is only half of the self
1930                  * refresh FIFO size on ILK/SNB.
1931                  */
1932                 if (INTEL_INFO(dev)->gen <= 6)
1933                         fifo_size /= 2;
1934         }
1935
1936         if (config->sprites_enabled) {
1937                 /* level 0 is always calculated with 1:1 split */
1938                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1939                         if (is_sprite)
1940                                 fifo_size *= 5;
1941                         fifo_size /= 6;
1942                 } else {
1943                         fifo_size /= 2;
1944                 }
1945         }
1946
1947         /* clamp to max that the registers can hold */
1948         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1949 }
1950
1951 /* Calculate the maximum cursor plane watermark */
1952 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1953                                       int level,
1954                                       const struct intel_wm_config *config)
1955 {
1956         /* HSW LP1+ watermarks w/ multiple pipes */
1957         if (level > 0 && config->num_pipes_active > 1)
1958                 return 64;
1959
1960         /* otherwise just report max that registers can hold */
1961         return ilk_cursor_wm_reg_max(dev, level);
1962 }
1963
1964 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1965                                     int level,
1966                                     const struct intel_wm_config *config,
1967                                     enum intel_ddb_partitioning ddb_partitioning,
1968                                     struct ilk_wm_maximums *max)
1969 {
1970         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1971         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1972         max->cur = ilk_cursor_wm_max(dev, level, config);
1973         max->fbc = ilk_fbc_wm_reg_max(dev);
1974 }
1975
1976 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1977                                         int level,
1978                                         struct ilk_wm_maximums *max)
1979 {
1980         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1981         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1982         max->cur = ilk_cursor_wm_reg_max(dev, level);
1983         max->fbc = ilk_fbc_wm_reg_max(dev);
1984 }
1985
1986 static bool ilk_validate_wm_level(int level,
1987                                   const struct ilk_wm_maximums *max,
1988                                   struct intel_wm_level *result)
1989 {
1990         bool ret;
1991
1992         /* already determined to be invalid? */
1993         if (!result->enable)
1994                 return false;
1995
1996         result->enable = result->pri_val <= max->pri &&
1997                          result->spr_val <= max->spr &&
1998                          result->cur_val <= max->cur;
1999
2000         ret = result->enable;
2001
2002         /*
2003          * HACK until we can pre-compute everything,
2004          * and thus fail gracefully if LP0 watermarks
2005          * are exceeded...
2006          */
2007         if (level == 0 && !result->enable) {
2008                 if (result->pri_val > max->pri)
2009                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2010                                       level, result->pri_val, max->pri);
2011                 if (result->spr_val > max->spr)
2012                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2013                                       level, result->spr_val, max->spr);
2014                 if (result->cur_val > max->cur)
2015                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2016                                       level, result->cur_val, max->cur);
2017
2018                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2019                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2020                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2021                 result->enable = true;
2022         }
2023
2024         return ret;
2025 }
2026
2027 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2028                                  const struct intel_crtc *intel_crtc,
2029                                  int level,
2030                                  struct intel_crtc_state *cstate,
2031                                  struct intel_plane_state *pristate,
2032                                  struct intel_plane_state *sprstate,
2033                                  struct intel_plane_state *curstate,
2034                                  struct intel_wm_level *result)
2035 {
2036         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2037         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2038         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2039
2040         /* WM1+ latency values stored in 0.5us units */
2041         if (level > 0) {
2042                 pri_latency *= 5;
2043                 spr_latency *= 5;
2044                 cur_latency *= 5;
2045         }
2046
2047         if (pristate) {
2048                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2049                                                      pri_latency, level);
2050                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2051         }
2052
2053         if (sprstate)
2054                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2055
2056         if (curstate)
2057                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2058
2059         result->enable = true;
2060 }
2061
2062 static uint32_t
2063 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2064 {
2065         const struct intel_atomic_state *intel_state =
2066                 to_intel_atomic_state(cstate->base.state);
2067         const struct drm_display_mode *adjusted_mode =
2068                 &cstate->base.adjusted_mode;
2069         u32 linetime, ips_linetime;
2070
2071         if (!cstate->base.active)
2072                 return 0;
2073         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2074                 return 0;
2075         if (WARN_ON(intel_state->cdclk == 0))
2076                 return 0;
2077
2078         /* The WM are computed with base on how long it takes to fill a single
2079          * row at the given clock rate, multiplied by 8.
2080          * */
2081         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2082                                      adjusted_mode->crtc_clock);
2083         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2084                                          intel_state->cdclk);
2085
2086         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2087                PIPE_WM_LINETIME_TIME(linetime);
2088 }
2089
2090 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2091                                   uint16_t wm[8])
2092 {
2093         if (IS_GEN9(dev_priv)) {
2094                 uint32_t val;
2095                 int ret, i;
2096                 int level, max_level = ilk_wm_max_level(dev_priv);
2097
2098                 /* read the first set of memory latencies[0:3] */
2099                 val = 0; /* data0 to be programmed to 0 for first set */
2100                 mutex_lock(&dev_priv->rps.hw_lock);
2101                 ret = sandybridge_pcode_read(dev_priv,
2102                                              GEN9_PCODE_READ_MEM_LATENCY,
2103                                              &val);
2104                 mutex_unlock(&dev_priv->rps.hw_lock);
2105
2106                 if (ret) {
2107                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2108                         return;
2109                 }
2110
2111                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2112                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2113                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2114                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2115                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2116                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2117                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2118
2119                 /* read the second set of memory latencies[4:7] */
2120                 val = 1; /* data0 to be programmed to 1 for second set */
2121                 mutex_lock(&dev_priv->rps.hw_lock);
2122                 ret = sandybridge_pcode_read(dev_priv,
2123                                              GEN9_PCODE_READ_MEM_LATENCY,
2124                                              &val);
2125                 mutex_unlock(&dev_priv->rps.hw_lock);
2126                 if (ret) {
2127                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2128                         return;
2129                 }
2130
2131                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2132                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2133                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2134                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2135                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2136                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2137                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2138
2139                 /*
2140                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2141                  * need to be disabled. We make sure to sanitize the values out
2142                  * of the punit to satisfy this requirement.
2143                  */
2144                 for (level = 1; level <= max_level; level++) {
2145                         if (wm[level] == 0) {
2146                                 for (i = level + 1; i <= max_level; i++)
2147                                         wm[i] = 0;
2148                                 break;
2149                         }
2150                 }
2151
2152                 /*
2153                  * WaWmMemoryReadLatency:skl
2154                  *
2155                  * punit doesn't take into account the read latency so we need
2156                  * to add 2us to the various latency levels we retrieve from the
2157                  * punit when level 0 response data us 0us.
2158                  */
2159                 if (wm[0] == 0) {
2160                         wm[0] += 2;
2161                         for (level = 1; level <= max_level; level++) {
2162                                 if (wm[level] == 0)
2163                                         break;
2164                                 wm[level] += 2;
2165                         }
2166                 }
2167
2168         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2169                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2170
2171                 wm[0] = (sskpd >> 56) & 0xFF;
2172                 if (wm[0] == 0)
2173                         wm[0] = sskpd & 0xF;
2174                 wm[1] = (sskpd >> 4) & 0xFF;
2175                 wm[2] = (sskpd >> 12) & 0xFF;
2176                 wm[3] = (sskpd >> 20) & 0x1FF;
2177                 wm[4] = (sskpd >> 32) & 0x1FF;
2178         } else if (INTEL_GEN(dev_priv) >= 6) {
2179                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2180
2181                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2182                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2183                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2184                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2185         } else if (INTEL_GEN(dev_priv) >= 5) {
2186                 uint32_t mltr = I915_READ(MLTR_ILK);
2187
2188                 /* ILK primary LP0 latency is 700 ns */
2189                 wm[0] = 7;
2190                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2191                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2192         }
2193 }
2194
2195 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2196                                        uint16_t wm[5])
2197 {
2198         /* ILK sprite LP0 latency is 1300 ns */
2199         if (IS_GEN5(dev_priv))
2200                 wm[0] = 13;
2201 }
2202
2203 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2204                                        uint16_t wm[5])
2205 {
2206         /* ILK cursor LP0 latency is 1300 ns */
2207         if (IS_GEN5(dev_priv))
2208                 wm[0] = 13;
2209
2210         /* WaDoubleCursorLP3Latency:ivb */
2211         if (IS_IVYBRIDGE(dev_priv))
2212                 wm[3] *= 2;
2213 }
2214
2215 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2216 {
2217         /* how many WM levels are we expecting */
2218         if (INTEL_GEN(dev_priv) >= 9)
2219                 return 7;
2220         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2221                 return 4;
2222         else if (INTEL_GEN(dev_priv) >= 6)
2223                 return 3;
2224         else
2225                 return 2;
2226 }
2227
2228 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2229                                    const char *name,
2230                                    const uint16_t wm[8])
2231 {
2232         int level, max_level = ilk_wm_max_level(dev_priv);
2233
2234         for (level = 0; level <= max_level; level++) {
2235                 unsigned int latency = wm[level];
2236
2237                 if (latency == 0) {
2238                         DRM_ERROR("%s WM%d latency not provided\n",
2239                                   name, level);
2240                         continue;
2241                 }
2242
2243                 /*
2244                  * - latencies are in us on gen9.
2245                  * - before then, WM1+ latency values are in 0.5us units
2246                  */
2247                 if (IS_GEN9(dev_priv))
2248                         latency *= 10;
2249                 else if (level > 0)
2250                         latency *= 5;
2251
2252                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2253                               name, level, wm[level],
2254                               latency / 10, latency % 10);
2255         }
2256 }
2257
2258 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2259                                     uint16_t wm[5], uint16_t min)
2260 {
2261         int level, max_level = ilk_wm_max_level(dev_priv);
2262
2263         if (wm[0] >= min)
2264                 return false;
2265
2266         wm[0] = max(wm[0], min);
2267         for (level = 1; level <= max_level; level++)
2268                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2269
2270         return true;
2271 }
2272
2273 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2274 {
2275         bool changed;
2276
2277         /*
2278          * The BIOS provided WM memory latency values are often
2279          * inadequate for high resolution displays. Adjust them.
2280          */
2281         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2282                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2283                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2284
2285         if (!changed)
2286                 return;
2287
2288         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2289         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2290         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2291         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2292 }
2293
2294 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
2295 {
2296         intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
2297
2298         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2299                sizeof(dev_priv->wm.pri_latency));
2300         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2301                sizeof(dev_priv->wm.pri_latency));
2302
2303         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2304         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2305
2306         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2307         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2308         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2309
2310         if (IS_GEN6(dev_priv))
2311                 snb_wm_latency_quirk(dev_priv);
2312 }
2313
2314 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
2315 {
2316         intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
2317         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2318 }
2319
2320 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2321                                  struct intel_pipe_wm *pipe_wm)
2322 {
2323         /* LP0 watermark maximums depend on this pipe alone */
2324         const struct intel_wm_config config = {
2325                 .num_pipes_active = 1,
2326                 .sprites_enabled = pipe_wm->sprites_enabled,
2327                 .sprites_scaled = pipe_wm->sprites_scaled,
2328         };
2329         struct ilk_wm_maximums max;
2330
2331         /* LP0 watermarks always use 1/2 DDB partitioning */
2332         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2333
2334         /* At least LP0 must be valid */
2335         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2336                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2337                 return false;
2338         }
2339
2340         return true;
2341 }
2342
2343 /* Compute new watermarks for the pipe */
2344 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2345 {
2346         struct drm_atomic_state *state = cstate->base.state;
2347         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2348         struct intel_pipe_wm *pipe_wm;
2349         struct drm_device *dev = state->dev;
2350         const struct drm_i915_private *dev_priv = to_i915(dev);
2351         struct intel_plane *intel_plane;
2352         struct intel_plane_state *pristate = NULL;
2353         struct intel_plane_state *sprstate = NULL;
2354         struct intel_plane_state *curstate = NULL;
2355         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
2356         struct ilk_wm_maximums max;
2357
2358         pipe_wm = &cstate->wm.ilk.optimal;
2359
2360         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2361                 struct intel_plane_state *ps;
2362
2363                 ps = intel_atomic_get_existing_plane_state(state,
2364                                                            intel_plane);
2365                 if (!ps)
2366                         continue;
2367
2368                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2369                         pristate = ps;
2370                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2371                         sprstate = ps;
2372                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2373                         curstate = ps;
2374         }
2375
2376         pipe_wm->pipe_enabled = cstate->base.active;
2377         if (sprstate) {
2378                 pipe_wm->sprites_enabled = sprstate->base.visible;
2379                 pipe_wm->sprites_scaled = sprstate->base.visible &&
2380                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2381                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2382         }
2383
2384         usable_level = max_level;
2385
2386         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2387         if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2388                 usable_level = 1;
2389
2390         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2391         if (pipe_wm->sprites_scaled)
2392                 usable_level = 0;
2393
2394         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2395                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2396
2397         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2398         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2399
2400         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2401                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2402
2403         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2404                 return -EINVAL;
2405
2406         ilk_compute_wm_reg_maximums(dev, 1, &max);
2407
2408         for (level = 1; level <= max_level; level++) {
2409                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2410
2411                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2412                                      pristate, sprstate, curstate, wm);
2413
2414                 /*
2415                  * Disable any watermark level that exceeds the
2416                  * register maximums since such watermarks are
2417                  * always invalid.
2418                  */
2419                 if (level > usable_level)
2420                         continue;
2421
2422                 if (ilk_validate_wm_level(level, &max, wm))
2423                         pipe_wm->wm[level] = *wm;
2424                 else
2425                         usable_level = level;
2426         }
2427
2428         return 0;
2429 }
2430
2431 /*
2432  * Build a set of 'intermediate' watermark values that satisfy both the old
2433  * state and the new state.  These can be programmed to the hardware
2434  * immediately.
2435  */
2436 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2437                                        struct intel_crtc *intel_crtc,
2438                                        struct intel_crtc_state *newstate)
2439 {
2440         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2441         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2442         int level, max_level = ilk_wm_max_level(to_i915(dev));
2443
2444         /*
2445          * Start with the final, target watermarks, then combine with the
2446          * currently active watermarks to get values that are safe both before
2447          * and after the vblank.
2448          */
2449         *a = newstate->wm.ilk.optimal;
2450         a->pipe_enabled |= b->pipe_enabled;
2451         a->sprites_enabled |= b->sprites_enabled;
2452         a->sprites_scaled |= b->sprites_scaled;
2453
2454         for (level = 0; level <= max_level; level++) {
2455                 struct intel_wm_level *a_wm = &a->wm[level];
2456                 const struct intel_wm_level *b_wm = &b->wm[level];
2457
2458                 a_wm->enable &= b_wm->enable;
2459                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2460                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2461                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2462                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2463         }
2464
2465         /*
2466          * We need to make sure that these merged watermark values are
2467          * actually a valid configuration themselves.  If they're not,
2468          * there's no safe way to transition from the old state to
2469          * the new state, so we need to fail the atomic transaction.
2470          */
2471         if (!ilk_validate_pipe_wm(dev, a))
2472                 return -EINVAL;
2473
2474         /*
2475          * If our intermediate WM are identical to the final WM, then we can
2476          * omit the post-vblank programming; only update if it's different.
2477          */
2478         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2479                 newstate->wm.need_postvbl_update = false;
2480
2481         return 0;
2482 }
2483
2484 /*
2485  * Merge the watermarks from all active pipes for a specific level.
2486  */
2487 static void ilk_merge_wm_level(struct drm_device *dev,
2488                                int level,
2489                                struct intel_wm_level *ret_wm)
2490 {
2491         const struct intel_crtc *intel_crtc;
2492
2493         ret_wm->enable = true;
2494
2495         for_each_intel_crtc(dev, intel_crtc) {
2496                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2497                 const struct intel_wm_level *wm = &active->wm[level];
2498
2499                 if (!active->pipe_enabled)
2500                         continue;
2501
2502                 /*
2503                  * The watermark values may have been used in the past,
2504                  * so we must maintain them in the registers for some
2505                  * time even if the level is now disabled.
2506                  */
2507                 if (!wm->enable)
2508                         ret_wm->enable = false;
2509
2510                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2511                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2512                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2513                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2514         }
2515 }
2516
2517 /*
2518  * Merge all low power watermarks for all active pipes.
2519  */
2520 static void ilk_wm_merge(struct drm_device *dev,
2521                          const struct intel_wm_config *config,
2522                          const struct ilk_wm_maximums *max,
2523                          struct intel_pipe_wm *merged)
2524 {
2525         struct drm_i915_private *dev_priv = to_i915(dev);
2526         int level, max_level = ilk_wm_max_level(dev_priv);
2527         int last_enabled_level = max_level;
2528
2529         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2530         if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
2531             config->num_pipes_active > 1)
2532                 last_enabled_level = 0;
2533
2534         /* ILK: FBC WM must be disabled always */
2535         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2536
2537         /* merge each WM1+ level */
2538         for (level = 1; level <= max_level; level++) {
2539                 struct intel_wm_level *wm = &merged->wm[level];
2540
2541                 ilk_merge_wm_level(dev, level, wm);
2542
2543                 if (level > last_enabled_level)
2544                         wm->enable = false;
2545                 else if (!ilk_validate_wm_level(level, max, wm))
2546                         /* make sure all following levels get disabled */
2547                         last_enabled_level = level - 1;
2548
2549                 /*
2550                  * The spec says it is preferred to disable
2551                  * FBC WMs instead of disabling a WM level.
2552                  */
2553                 if (wm->fbc_val > max->fbc) {
2554                         if (wm->enable)
2555                                 merged->fbc_wm_enabled = false;
2556                         wm->fbc_val = 0;
2557                 }
2558         }
2559
2560         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2561         /*
2562          * FIXME this is racy. FBC might get enabled later.
2563          * What we should check here is whether FBC can be
2564          * enabled sometime later.
2565          */
2566         if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
2567             intel_fbc_is_active(dev_priv)) {
2568                 for (level = 2; level <= max_level; level++) {
2569                         struct intel_wm_level *wm = &merged->wm[level];
2570
2571                         wm->enable = false;
2572                 }
2573         }
2574 }
2575
2576 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2577 {
2578         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2579         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2580 }
2581
2582 /* The value we need to program into the WM_LPx latency field */
2583 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2584 {
2585         struct drm_i915_private *dev_priv = to_i915(dev);
2586
2587         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2588                 return 2 * level;
2589         else
2590                 return dev_priv->wm.pri_latency[level];
2591 }
2592
2593 static void ilk_compute_wm_results(struct drm_device *dev,
2594                                    const struct intel_pipe_wm *merged,
2595                                    enum intel_ddb_partitioning partitioning,
2596                                    struct ilk_wm_values *results)
2597 {
2598         struct intel_crtc *intel_crtc;
2599         int level, wm_lp;
2600
2601         results->enable_fbc_wm = merged->fbc_wm_enabled;
2602         results->partitioning = partitioning;
2603
2604         /* LP1+ register values */
2605         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2606                 const struct intel_wm_level *r;
2607
2608                 level = ilk_wm_lp_to_level(wm_lp, merged);
2609
2610                 r = &merged->wm[level];
2611
2612                 /*
2613                  * Maintain the watermark values even if the level is
2614                  * disabled. Doing otherwise could cause underruns.
2615                  */
2616                 results->wm_lp[wm_lp - 1] =
2617                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2618                         (r->pri_val << WM1_LP_SR_SHIFT) |
2619                         r->cur_val;
2620
2621                 if (r->enable)
2622                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2623
2624                 if (INTEL_INFO(dev)->gen >= 8)
2625                         results->wm_lp[wm_lp - 1] |=
2626                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2627                 else
2628                         results->wm_lp[wm_lp - 1] |=
2629                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2630
2631                 /*
2632                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2633                  * level is disabled. Doing otherwise could cause underruns.
2634                  */
2635                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2636                         WARN_ON(wm_lp != 1);
2637                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2638                 } else
2639                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2640         }
2641
2642         /* LP0 register values */
2643         for_each_intel_crtc(dev, intel_crtc) {
2644                 enum pipe pipe = intel_crtc->pipe;
2645                 const struct intel_wm_level *r =
2646                         &intel_crtc->wm.active.ilk.wm[0];
2647
2648                 if (WARN_ON(!r->enable))
2649                         continue;
2650
2651                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2652
2653                 results->wm_pipe[pipe] =
2654                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2655                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2656                         r->cur_val;
2657         }
2658 }
2659
2660 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2661  * case both are at the same level. Prefer r1 in case they're the same. */
2662 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2663                                                   struct intel_pipe_wm *r1,
2664                                                   struct intel_pipe_wm *r2)
2665 {
2666         int level, max_level = ilk_wm_max_level(to_i915(dev));
2667         int level1 = 0, level2 = 0;
2668
2669         for (level = 1; level <= max_level; level++) {
2670                 if (r1->wm[level].enable)
2671                         level1 = level;
2672                 if (r2->wm[level].enable)
2673                         level2 = level;
2674         }
2675
2676         if (level1 == level2) {
2677                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2678                         return r2;
2679                 else
2680                         return r1;
2681         } else if (level1 > level2) {
2682                 return r1;
2683         } else {
2684                 return r2;
2685         }
2686 }
2687
2688 /* dirty bits used to track which watermarks need changes */
2689 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2690 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2691 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2692 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2693 #define WM_DIRTY_FBC (1 << 24)
2694 #define WM_DIRTY_DDB (1 << 25)
2695
2696 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2697                                          const struct ilk_wm_values *old,
2698                                          const struct ilk_wm_values *new)
2699 {
2700         unsigned int dirty = 0;
2701         enum pipe pipe;
2702         int wm_lp;
2703
2704         for_each_pipe(dev_priv, pipe) {
2705                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2706                         dirty |= WM_DIRTY_LINETIME(pipe);
2707                         /* Must disable LP1+ watermarks too */
2708                         dirty |= WM_DIRTY_LP_ALL;
2709                 }
2710
2711                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2712                         dirty |= WM_DIRTY_PIPE(pipe);
2713                         /* Must disable LP1+ watermarks too */
2714                         dirty |= WM_DIRTY_LP_ALL;
2715                 }
2716         }
2717
2718         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2719                 dirty |= WM_DIRTY_FBC;
2720                 /* Must disable LP1+ watermarks too */
2721                 dirty |= WM_DIRTY_LP_ALL;
2722         }
2723
2724         if (old->partitioning != new->partitioning) {
2725                 dirty |= WM_DIRTY_DDB;
2726                 /* Must disable LP1+ watermarks too */
2727                 dirty |= WM_DIRTY_LP_ALL;
2728         }
2729
2730         /* LP1+ watermarks already deemed dirty, no need to continue */
2731         if (dirty & WM_DIRTY_LP_ALL)
2732                 return dirty;
2733
2734         /* Find the lowest numbered LP1+ watermark in need of an update... */
2735         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2736                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2737                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2738                         break;
2739         }
2740
2741         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2742         for (; wm_lp <= 3; wm_lp++)
2743                 dirty |= WM_DIRTY_LP(wm_lp);
2744
2745         return dirty;
2746 }
2747
2748 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2749                                unsigned int dirty)
2750 {
2751         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2752         bool changed = false;
2753
2754         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2755                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2756                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2757                 changed = true;
2758         }
2759         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2760                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2761                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2762                 changed = true;
2763         }
2764         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2765                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2766                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2767                 changed = true;
2768         }
2769
2770         /*
2771          * Don't touch WM1S_LP_EN here.
2772          * Doing so could cause underruns.
2773          */
2774
2775         return changed;
2776 }
2777
2778 /*
2779  * The spec says we shouldn't write when we don't need, because every write
2780  * causes WMs to be re-evaluated, expending some power.
2781  */
2782 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2783                                 struct ilk_wm_values *results)
2784 {
2785         struct drm_device *dev = &dev_priv->drm;
2786         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2787         unsigned int dirty;
2788         uint32_t val;
2789
2790         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2791         if (!dirty)
2792                 return;
2793
2794         _ilk_disable_lp_wm(dev_priv, dirty);
2795
2796         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2797                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2798         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2799                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2800         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2801                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2802
2803         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2804                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2805         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2806                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2807         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2808                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2809
2810         if (dirty & WM_DIRTY_DDB) {
2811                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2812                         val = I915_READ(WM_MISC);
2813                         if (results->partitioning == INTEL_DDB_PART_1_2)
2814                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2815                         else
2816                                 val |= WM_MISC_DATA_PARTITION_5_6;
2817                         I915_WRITE(WM_MISC, val);
2818                 } else {
2819                         val = I915_READ(DISP_ARB_CTL2);
2820                         if (results->partitioning == INTEL_DDB_PART_1_2)
2821                                 val &= ~DISP_DATA_PARTITION_5_6;
2822                         else
2823                                 val |= DISP_DATA_PARTITION_5_6;
2824                         I915_WRITE(DISP_ARB_CTL2, val);
2825                 }
2826         }
2827
2828         if (dirty & WM_DIRTY_FBC) {
2829                 val = I915_READ(DISP_ARB_CTL);
2830                 if (results->enable_fbc_wm)
2831                         val &= ~DISP_FBC_WM_DIS;
2832                 else
2833                         val |= DISP_FBC_WM_DIS;
2834                 I915_WRITE(DISP_ARB_CTL, val);
2835         }
2836
2837         if (dirty & WM_DIRTY_LP(1) &&
2838             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2839                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2840
2841         if (INTEL_INFO(dev)->gen >= 7) {
2842                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2843                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2844                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2845                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2846         }
2847
2848         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2849                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2850         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2851                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2852         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2853                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2854
2855         dev_priv->wm.hw = *results;
2856 }
2857
2858 bool ilk_disable_lp_wm(struct drm_device *dev)
2859 {
2860         struct drm_i915_private *dev_priv = to_i915(dev);
2861
2862         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2863 }
2864
2865 #define SKL_SAGV_BLOCK_TIME     30 /* µs */
2866
2867 /*
2868  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2869  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2870  * other universal planes are in indices 1..n.  Note that this may leave unused
2871  * indices between the top "sprite" plane and the cursor.
2872  */
2873 static int
2874 skl_wm_plane_id(const struct intel_plane *plane)
2875 {
2876         switch (plane->base.type) {
2877         case DRM_PLANE_TYPE_PRIMARY:
2878                 return 0;
2879         case DRM_PLANE_TYPE_CURSOR:
2880                 return PLANE_CURSOR;
2881         case DRM_PLANE_TYPE_OVERLAY:
2882                 return plane->plane + 1;
2883         default:
2884                 MISSING_CASE(plane->base.type);
2885                 return plane->plane;
2886         }
2887 }
2888
2889 /*
2890  * FIXME: We still don't have the proper code detect if we need to apply the WA,
2891  * so assume we'll always need it in order to avoid underruns.
2892  */
2893 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2894 {
2895         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2896
2897         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2898             IS_KABYLAKE(dev_priv))
2899                 return true;
2900
2901         return false;
2902 }
2903
2904 static bool
2905 intel_has_sagv(struct drm_i915_private *dev_priv)
2906 {
2907         if (IS_KABYLAKE(dev_priv))
2908                 return true;
2909
2910         if (IS_SKYLAKE(dev_priv) &&
2911             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2912                 return true;
2913
2914         return false;
2915 }
2916
2917 /*
2918  * SAGV dynamically adjusts the system agent voltage and clock frequencies
2919  * depending on power and performance requirements. The display engine access
2920  * to system memory is blocked during the adjustment time. Because of the
2921  * blocking time, having this enabled can cause full system hangs and/or pipe
2922  * underruns if we don't meet all of the following requirements:
2923  *
2924  *  - <= 1 pipe enabled
2925  *  - All planes can enable watermarks for latencies >= SAGV engine block time
2926  *  - We're not using an interlaced display configuration
2927  */
2928 int
2929 intel_enable_sagv(struct drm_i915_private *dev_priv)
2930 {
2931         int ret;
2932
2933         if (!intel_has_sagv(dev_priv))
2934                 return 0;
2935
2936         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
2937                 return 0;
2938
2939         DRM_DEBUG_KMS("Enabling the SAGV\n");
2940         mutex_lock(&dev_priv->rps.hw_lock);
2941
2942         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2943                                       GEN9_SAGV_ENABLE);
2944
2945         /* We don't need to wait for the SAGV when enabling */
2946         mutex_unlock(&dev_priv->rps.hw_lock);
2947
2948         /*
2949          * Some skl systems, pre-release machines in particular,
2950          * don't actually have an SAGV.
2951          */
2952         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2953                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2954                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2955                 return 0;
2956         } else if (ret < 0) {
2957                 DRM_ERROR("Failed to enable the SAGV\n");
2958                 return ret;
2959         }
2960
2961         dev_priv->sagv_status = I915_SAGV_ENABLED;
2962         return 0;
2963 }
2964
2965 static int
2966 intel_do_sagv_disable(struct drm_i915_private *dev_priv)
2967 {
2968         int ret;
2969         uint32_t temp = GEN9_SAGV_DISABLE;
2970
2971         ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2972                                      &temp);
2973         if (ret)
2974                 return ret;
2975         else
2976                 return temp & GEN9_SAGV_IS_DISABLED;
2977 }
2978
2979 int
2980 intel_disable_sagv(struct drm_i915_private *dev_priv)
2981 {
2982         int ret, result;
2983
2984         if (!intel_has_sagv(dev_priv))
2985                 return 0;
2986
2987         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
2988                 return 0;
2989
2990         DRM_DEBUG_KMS("Disabling the SAGV\n");
2991         mutex_lock(&dev_priv->rps.hw_lock);
2992
2993         /* bspec says to keep retrying for at least 1 ms */
2994         ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
2995         mutex_unlock(&dev_priv->rps.hw_lock);
2996
2997         if (ret == -ETIMEDOUT) {
2998                 DRM_ERROR("Request to disable SAGV timed out\n");
2999                 return -ETIMEDOUT;
3000         }
3001
3002         /*
3003          * Some skl systems, pre-release machines in particular,
3004          * don't actually have an SAGV.
3005          */
3006         if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
3007                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3008                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3009                 return 0;
3010         } else if (result < 0) {
3011                 DRM_ERROR("Failed to disable the SAGV\n");
3012                 return result;
3013         }
3014
3015         dev_priv->sagv_status = I915_SAGV_DISABLED;
3016         return 0;
3017 }
3018
3019 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3020 {
3021         struct drm_device *dev = state->dev;
3022         struct drm_i915_private *dev_priv = to_i915(dev);
3023         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3024         struct intel_crtc *crtc;
3025         struct intel_plane *plane;
3026         struct intel_crtc_state *cstate;
3027         struct skl_plane_wm *wm;
3028         enum pipe pipe;
3029         int level, latency;
3030
3031         if (!intel_has_sagv(dev_priv))
3032                 return false;
3033
3034         /*
3035          * SKL workaround: bspec recommends we disable the SAGV when we have
3036          * more then one pipe enabled
3037          *
3038          * If there are no active CRTCs, no additional checks need be performed
3039          */
3040         if (hweight32(intel_state->active_crtcs) == 0)
3041                 return true;
3042         else if (hweight32(intel_state->active_crtcs) > 1)
3043                 return false;
3044
3045         /* Since we're now guaranteed to only have one active CRTC... */
3046         pipe = ffs(intel_state->active_crtcs) - 1;
3047         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3048         cstate = to_intel_crtc_state(crtc->base.state);
3049
3050         if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3051                 return false;
3052
3053         for_each_intel_plane_on_crtc(dev, crtc, plane) {
3054                 wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
3055
3056                 /* Skip this plane if it's not enabled */
3057                 if (!wm->wm[0].plane_en)
3058                         continue;
3059
3060                 /* Find the highest enabled wm level for this plane */
3061                 for (level = ilk_wm_max_level(dev_priv);
3062                      !wm->wm[level].plane_en; --level)
3063                      { }
3064
3065                 latency = dev_priv->wm.skl_latency[level];
3066
3067                 if (skl_needs_memory_bw_wa(intel_state) &&
3068                     plane->base.state->fb->modifier[0] ==
3069                     I915_FORMAT_MOD_X_TILED)
3070                         latency += 15;
3071
3072                 /*
3073                  * If any of the planes on this pipe don't enable wm levels
3074                  * that incur memory latencies higher then 30µs we can't enable
3075                  * the SAGV
3076                  */
3077                 if (latency < SKL_SAGV_BLOCK_TIME)
3078                         return false;
3079         }
3080
3081         return true;
3082 }
3083
3084 static void
3085 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3086                                    const struct intel_crtc_state *cstate,
3087                                    struct skl_ddb_entry *alloc, /* out */
3088                                    int *num_active /* out */)
3089 {
3090         struct drm_atomic_state *state = cstate->base.state;
3091         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3092         struct drm_i915_private *dev_priv = to_i915(dev);
3093         struct drm_crtc *for_crtc = cstate->base.crtc;
3094         unsigned int pipe_size, ddb_size;
3095         int nth_active_pipe;
3096
3097         if (WARN_ON(!state) || !cstate->base.active) {
3098                 alloc->start = 0;
3099                 alloc->end = 0;
3100                 *num_active = hweight32(dev_priv->active_crtcs);
3101                 return;
3102         }
3103
3104         if (intel_state->active_pipe_changes)
3105                 *num_active = hweight32(intel_state->active_crtcs);
3106         else
3107                 *num_active = hweight32(dev_priv->active_crtcs);
3108
3109         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3110         WARN_ON(ddb_size == 0);
3111
3112         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3113
3114         /*
3115          * If the state doesn't change the active CRTC's, then there's
3116          * no need to recalculate; the existing pipe allocation limits
3117          * should remain unchanged.  Note that we're safe from racing
3118          * commits since any racing commit that changes the active CRTC
3119          * list would need to grab _all_ crtc locks, including the one
3120          * we currently hold.
3121          */
3122         if (!intel_state->active_pipe_changes) {
3123                 /*
3124                  * alloc may be cleared by clear_intel_crtc_state,
3125                  * copy from old state to be sure
3126                  */
3127                 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3128                 return;
3129         }
3130
3131         nth_active_pipe = hweight32(intel_state->active_crtcs &
3132                                     (drm_crtc_mask(for_crtc) - 1));
3133         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3134         alloc->start = nth_active_pipe * ddb_size / *num_active;
3135         alloc->end = alloc->start + pipe_size;
3136 }
3137
3138 static unsigned int skl_cursor_allocation(int num_active)
3139 {
3140         if (num_active == 1)
3141                 return 32;
3142
3143         return 8;
3144 }
3145
3146 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3147 {
3148         entry->start = reg & 0x3ff;
3149         entry->end = (reg >> 16) & 0x3ff;
3150         if (entry->end)
3151                 entry->end += 1;
3152 }
3153
3154 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3155                           struct skl_ddb_allocation *ddb /* out */)
3156 {
3157         enum pipe pipe;
3158         int plane;
3159         u32 val;
3160
3161         memset(ddb, 0, sizeof(*ddb));
3162
3163         for_each_pipe(dev_priv, pipe) {
3164                 enum intel_display_power_domain power_domain;
3165
3166                 power_domain = POWER_DOMAIN_PIPE(pipe);
3167                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3168                         continue;
3169
3170                 for_each_universal_plane(dev_priv, pipe, plane) {
3171                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3172                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3173                                                    val);
3174                 }
3175
3176                 val = I915_READ(CUR_BUF_CFG(pipe));
3177                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3178                                            val);
3179
3180                 intel_display_power_put(dev_priv, power_domain);
3181         }
3182 }
3183
3184 /*
3185  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3186  * The bspec defines downscale amount as:
3187  *
3188  * """
3189  * Horizontal down scale amount = maximum[1, Horizontal source size /
3190  *                                           Horizontal destination size]
3191  * Vertical down scale amount = maximum[1, Vertical source size /
3192  *                                         Vertical destination size]
3193  * Total down scale amount = Horizontal down scale amount *
3194  *                           Vertical down scale amount
3195  * """
3196  *
3197  * Return value is provided in 16.16 fixed point form to retain fractional part.
3198  * Caller should take care of dividing & rounding off the value.
3199  */
3200 static uint32_t
3201 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3202 {
3203         uint32_t downscale_h, downscale_w;
3204         uint32_t src_w, src_h, dst_w, dst_h;
3205
3206         if (WARN_ON(!pstate->base.visible))
3207                 return DRM_PLANE_HELPER_NO_SCALING;
3208
3209         /* n.b., src is 16.16 fixed point, dst is whole integer */
3210         src_w = drm_rect_width(&pstate->base.src);
3211         src_h = drm_rect_height(&pstate->base.src);
3212         dst_w = drm_rect_width(&pstate->base.dst);
3213         dst_h = drm_rect_height(&pstate->base.dst);
3214         if (drm_rotation_90_or_270(pstate->base.rotation))
3215                 swap(dst_w, dst_h);
3216
3217         downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3218         downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3219
3220         /* Provide result in 16.16 fixed point */
3221         return (uint64_t)downscale_w * downscale_h >> 16;
3222 }
3223
3224 static unsigned int
3225 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3226                              const struct drm_plane_state *pstate,
3227                              int y)
3228 {
3229         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3230         struct drm_framebuffer *fb = pstate->fb;
3231         uint32_t down_scale_amount, data_rate;
3232         uint32_t width = 0, height = 0;
3233         unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3234
3235         if (!intel_pstate->base.visible)
3236                 return 0;
3237         if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3238                 return 0;
3239         if (y && format != DRM_FORMAT_NV12)
3240                 return 0;
3241
3242         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3243         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3244
3245         if (drm_rotation_90_or_270(pstate->rotation))
3246                 swap(width, height);
3247
3248         /* for planar format */
3249         if (format == DRM_FORMAT_NV12) {
3250                 if (y)  /* y-plane data rate */
3251                         data_rate = width * height *
3252                                 drm_format_plane_cpp(format, 0);
3253                 else    /* uv-plane data rate */
3254                         data_rate = (width / 2) * (height / 2) *
3255                                 drm_format_plane_cpp(format, 1);
3256         } else {
3257                 /* for packed formats */
3258                 data_rate = width * height * drm_format_plane_cpp(format, 0);
3259         }
3260
3261         down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3262
3263         return (uint64_t)data_rate * down_scale_amount >> 16;
3264 }
3265
3266 /*
3267  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3268  * a 8192x4096@32bpp framebuffer:
3269  *   3 * 4096 * 8192  * 4 < 2^32
3270  */
3271 static unsigned int
3272 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3273                                  unsigned *plane_data_rate,
3274                                  unsigned *plane_y_data_rate)
3275 {
3276         struct drm_crtc_state *cstate = &intel_cstate->base;
3277         struct drm_atomic_state *state = cstate->state;
3278         struct drm_plane *plane;
3279         const struct intel_plane *intel_plane;
3280         const struct drm_plane_state *pstate;
3281         unsigned int rate, total_data_rate = 0;
3282         int id;
3283
3284         if (WARN_ON(!state))
3285                 return 0;
3286
3287         /* Calculate and cache data rate for each plane */
3288         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
3289                 id = skl_wm_plane_id(to_intel_plane(plane));
3290                 intel_plane = to_intel_plane(plane);
3291
3292                 /* packed/uv */
3293                 rate = skl_plane_relative_data_rate(intel_cstate,
3294                                                     pstate, 0);
3295                 plane_data_rate[id] = rate;
3296
3297                 total_data_rate += rate;
3298
3299                 /* y-plane */
3300                 rate = skl_plane_relative_data_rate(intel_cstate,
3301                                                     pstate, 1);
3302                 plane_y_data_rate[id] = rate;
3303
3304                 total_data_rate += rate;
3305         }
3306
3307         return total_data_rate;
3308 }
3309
3310 static uint16_t
3311 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3312                   const int y)
3313 {
3314         struct drm_framebuffer *fb = pstate->fb;
3315         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3316         uint32_t src_w, src_h;
3317         uint32_t min_scanlines = 8;
3318         uint8_t plane_bpp;
3319
3320         if (WARN_ON(!fb))
3321                 return 0;
3322
3323         /* For packed formats, no y-plane, return 0 */
3324         if (y && fb->pixel_format != DRM_FORMAT_NV12)
3325                 return 0;
3326
3327         /* For Non Y-tile return 8-blocks */
3328         if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3329             fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3330                 return 8;
3331
3332         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3333         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3334
3335         if (drm_rotation_90_or_270(pstate->rotation))
3336                 swap(src_w, src_h);
3337
3338         /* Halve UV plane width and height for NV12 */
3339         if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3340                 src_w /= 2;
3341                 src_h /= 2;
3342         }
3343
3344         if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3345                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3346         else
3347                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3348
3349         if (drm_rotation_90_or_270(pstate->rotation)) {
3350                 switch (plane_bpp) {
3351                 case 1:
3352                         min_scanlines = 32;
3353                         break;
3354                 case 2:
3355                         min_scanlines = 16;
3356                         break;
3357                 case 4:
3358                         min_scanlines = 8;
3359                         break;
3360                 case 8:
3361                         min_scanlines = 4;
3362                         break;
3363                 default:
3364                         WARN(1, "Unsupported pixel depth %u for rotation",
3365                              plane_bpp);
3366                         min_scanlines = 32;
3367                 }
3368         }
3369
3370         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3371 }
3372
3373 static void
3374 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3375                  uint16_t *minimum, uint16_t *y_minimum)
3376 {
3377         const struct drm_plane_state *pstate;
3378         struct drm_plane *plane;
3379
3380         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3381                 struct intel_plane *intel_plane = to_intel_plane(plane);
3382                 int id = skl_wm_plane_id(intel_plane);
3383
3384                 if (id == PLANE_CURSOR)
3385                         continue;
3386
3387                 if (!pstate->visible)
3388                         continue;
3389
3390                 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3391                 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3392         }
3393
3394         minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3395 }
3396
3397 static int
3398 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3399                       struct skl_ddb_allocation *ddb /* out */)
3400 {
3401         struct drm_atomic_state *state = cstate->base.state;
3402         struct drm_crtc *crtc = cstate->base.crtc;
3403         struct drm_device *dev = crtc->dev;
3404         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3405         enum pipe pipe = intel_crtc->pipe;
3406         struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
3407         uint16_t alloc_size, start;
3408         uint16_t minimum[I915_MAX_PLANES] = {};
3409         uint16_t y_minimum[I915_MAX_PLANES] = {};
3410         unsigned int total_data_rate;
3411         int num_active;
3412         int id, i;
3413         unsigned plane_data_rate[I915_MAX_PLANES] = {};
3414         unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
3415
3416         /* Clear the partitioning for disabled planes. */
3417         memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3418         memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3419
3420         if (WARN_ON(!state))
3421                 return 0;
3422
3423         if (!cstate->base.active) {
3424                 alloc->start = alloc->end = 0;
3425                 return 0;
3426         }
3427
3428         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3429         alloc_size = skl_ddb_entry_size(alloc);
3430         if (alloc_size == 0) {
3431                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3432                 return 0;
3433         }
3434
3435         skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
3436
3437         /*
3438          * 1. Allocate the mininum required blocks for each active plane
3439          * and allocate the cursor, it doesn't require extra allocation
3440          * proportional to the data rate.
3441          */
3442
3443         for (i = 0; i < I915_MAX_PLANES; i++) {
3444                 alloc_size -= minimum[i];
3445                 alloc_size -= y_minimum[i];
3446         }
3447
3448         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3449         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3450
3451         /*
3452          * 2. Distribute the remaining space in proportion to the amount of
3453          * data each plane needs to fetch from memory.
3454          *
3455          * FIXME: we may not allocate every single block here.
3456          */
3457         total_data_rate = skl_get_total_relative_data_rate(cstate,
3458                                                            plane_data_rate,
3459                                                            plane_y_data_rate);
3460         if (total_data_rate == 0)
3461                 return 0;
3462
3463         start = alloc->start;
3464         for (id = 0; id < I915_MAX_PLANES; id++) {
3465                 unsigned int data_rate, y_data_rate;
3466                 uint16_t plane_blocks, y_plane_blocks = 0;
3467
3468                 if (id == PLANE_CURSOR)
3469                         continue;
3470
3471                 data_rate = plane_data_rate[id];
3472
3473                 /*
3474                  * allocation for (packed formats) or (uv-plane part of planar format):
3475                  * promote the expression to 64 bits to avoid overflowing, the
3476                  * result is < available as data_rate / total_data_rate < 1
3477                  */
3478                 plane_blocks = minimum[id];
3479                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3480                                         total_data_rate);
3481
3482                 /* Leave disabled planes at (0,0) */
3483                 if (data_rate) {
3484                         ddb->plane[pipe][id].start = start;
3485                         ddb->plane[pipe][id].end = start + plane_blocks;
3486                 }
3487
3488                 start += plane_blocks;
3489
3490                 /*
3491                  * allocation for y_plane part of planar format:
3492                  */
3493                 y_data_rate = plane_y_data_rate[id];
3494
3495                 y_plane_blocks = y_minimum[id];
3496                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3497                                         total_data_rate);
3498
3499                 if (y_data_rate) {
3500                         ddb->y_plane[pipe][id].start = start;
3501                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3502                 }
3503
3504                 start += y_plane_blocks;
3505         }
3506
3507         return 0;
3508 }
3509
3510 /*
3511  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3512  * for the read latency) and cpp should always be <= 8, so that
3513  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3514  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3515 */
3516 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3517 {
3518         uint32_t wm_intermediate_val, ret;
3519
3520         if (latency == 0)
3521                 return UINT_MAX;
3522
3523         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3524         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3525
3526         return ret;
3527 }
3528
3529 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3530                                uint32_t latency, uint32_t plane_blocks_per_line)
3531 {
3532         uint32_t ret;
3533         uint32_t wm_intermediate_val;
3534
3535         if (latency == 0)
3536                 return UINT_MAX;
3537
3538         wm_intermediate_val = latency * pixel_rate;
3539         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3540                                 plane_blocks_per_line;
3541
3542         return ret;
3543 }
3544
3545 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3546                                               struct intel_plane_state *pstate)
3547 {
3548         uint64_t adjusted_pixel_rate;
3549         uint64_t downscale_amount;
3550         uint64_t pixel_rate;
3551
3552         /* Shouldn't reach here on disabled planes... */
3553         if (WARN_ON(!pstate->base.visible))
3554                 return 0;
3555
3556         /*
3557          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3558          * with additional adjustments for plane-specific scaling.
3559          */
3560         adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
3561         downscale_amount = skl_plane_downscale_amount(pstate);
3562
3563         pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3564         WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3565
3566         return pixel_rate;
3567 }
3568
3569 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3570                                 struct intel_crtc_state *cstate,
3571                                 struct intel_plane_state *intel_pstate,
3572                                 uint16_t ddb_allocation,
3573                                 int level,
3574                                 uint16_t *out_blocks, /* out */
3575                                 uint8_t *out_lines, /* out */
3576                                 bool *enabled /* out */)
3577 {
3578         struct drm_plane_state *pstate = &intel_pstate->base;
3579         struct drm_framebuffer *fb = pstate->fb;
3580         uint32_t latency = dev_priv->wm.skl_latency[level];
3581         uint32_t method1, method2;
3582         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3583         uint32_t res_blocks, res_lines;
3584         uint32_t selected_result;
3585         uint8_t cpp;
3586         uint32_t width = 0, height = 0;
3587         uint32_t plane_pixel_rate;
3588         uint32_t y_tile_minimum, y_min_scanlines;
3589         struct intel_atomic_state *state =
3590                 to_intel_atomic_state(cstate->base.state);
3591         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
3592
3593         if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3594                 *enabled = false;
3595                 return 0;
3596         }
3597
3598         if (apply_memory_bw_wa && fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3599                 latency += 15;
3600
3601         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3602         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3603
3604         if (drm_rotation_90_or_270(pstate->rotation))
3605                 swap(width, height);
3606
3607         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3608         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3609
3610         if (drm_rotation_90_or_270(pstate->rotation)) {
3611                 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3612                         drm_format_plane_cpp(fb->pixel_format, 1) :
3613                         drm_format_plane_cpp(fb->pixel_format, 0);
3614
3615                 switch (cpp) {
3616                 case 1:
3617                         y_min_scanlines = 16;
3618                         break;
3619                 case 2:
3620                         y_min_scanlines = 8;
3621                         break;
3622                 case 4:
3623                         y_min_scanlines = 4;
3624                         break;
3625                 default:
3626                         MISSING_CASE(cpp);
3627                         return -EINVAL;
3628                 }
3629         } else {
3630                 y_min_scanlines = 4;
3631         }
3632
3633         if (apply_memory_bw_wa)
3634                 y_min_scanlines *= 2;
3635
3636         plane_bytes_per_line = width * cpp;
3637         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3638             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3639                 plane_blocks_per_line =
3640                       DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3641                 plane_blocks_per_line /= y_min_scanlines;
3642         } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3643                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3644                                         + 1;
3645         } else {
3646                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3647         }
3648
3649         method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3650         method2 = skl_wm_method2(plane_pixel_rate,
3651                                  cstate->base.adjusted_mode.crtc_htotal,
3652                                  latency,
3653                                  plane_blocks_per_line);
3654
3655         y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3656
3657         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3658             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3659                 selected_result = max(method2, y_tile_minimum);
3660         } else {
3661                 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3662                     (plane_bytes_per_line / 512 < 1))
3663                         selected_result = method2;
3664                 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
3665                         selected_result = min(method1, method2);
3666                 else
3667                         selected_result = method1;
3668         }
3669
3670         res_blocks = selected_result + 1;
3671         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3672
3673         if (level >= 1 && level <= 7) {
3674                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3675                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3676                         res_blocks += y_tile_minimum;
3677                         res_lines += y_min_scanlines;
3678                 } else {
3679                         res_blocks++;
3680                 }
3681         }
3682
3683         if (res_blocks >= ddb_allocation || res_lines > 31) {
3684                 *enabled = false;
3685
3686                 /*
3687                  * If there are no valid level 0 watermarks, then we can't
3688                  * support this display configuration.
3689                  */
3690                 if (level) {
3691                         return 0;
3692                 } else {
3693                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3694                         DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3695                                       to_intel_crtc(cstate->base.crtc)->pipe,
3696                                       skl_wm_plane_id(to_intel_plane(pstate->plane)),
3697                                       res_blocks, ddb_allocation, res_lines);
3698
3699                         return -EINVAL;
3700                 }
3701         }
3702
3703         *out_blocks = res_blocks;
3704         *out_lines = res_lines;
3705         *enabled = true;
3706
3707         return 0;
3708 }
3709
3710 static int
3711 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3712                      struct skl_ddb_allocation *ddb,
3713                      struct intel_crtc_state *cstate,
3714                      struct intel_plane *intel_plane,
3715                      int level,
3716                      struct skl_wm_level *result)
3717 {
3718         struct drm_atomic_state *state = cstate->base.state;
3719         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3720         struct drm_plane *plane = &intel_plane->base;
3721         struct intel_plane_state *intel_pstate = NULL;
3722         uint16_t ddb_blocks;
3723         enum pipe pipe = intel_crtc->pipe;
3724         int ret;
3725         int i = skl_wm_plane_id(intel_plane);
3726
3727         if (state)
3728                 intel_pstate =
3729                         intel_atomic_get_existing_plane_state(state,
3730                                                               intel_plane);
3731
3732         /*
3733          * Note: If we start supporting multiple pending atomic commits against
3734          * the same planes/CRTC's in the future, plane->state will no longer be
3735          * the correct pre-state to use for the calculations here and we'll
3736          * need to change where we get the 'unchanged' plane data from.
3737          *
3738          * For now this is fine because we only allow one queued commit against
3739          * a CRTC.  Even if the plane isn't modified by this transaction and we
3740          * don't have a plane lock, we still have the CRTC's lock, so we know
3741          * that no other transactions are racing with us to update it.
3742          */
3743         if (!intel_pstate)
3744                 intel_pstate = to_intel_plane_state(plane->state);
3745
3746         WARN_ON(!intel_pstate->base.fb);
3747
3748         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3749
3750         ret = skl_compute_plane_wm(dev_priv,
3751                                    cstate,
3752                                    intel_pstate,
3753                                    ddb_blocks,
3754                                    level,
3755                                    &result->plane_res_b,
3756                                    &result->plane_res_l,
3757                                    &result->plane_en);
3758         if (ret)
3759                 return ret;
3760
3761         return 0;
3762 }
3763
3764 static uint32_t
3765 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3766 {
3767         uint32_t pixel_rate;
3768
3769         if (!cstate->base.active)
3770                 return 0;
3771
3772         pixel_rate = ilk_pipe_pixel_rate(cstate);
3773
3774         if (WARN_ON(pixel_rate == 0))
3775                 return 0;
3776
3777         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3778                             pixel_rate);
3779 }
3780
3781 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3782                                       struct skl_wm_level *trans_wm /* out */)
3783 {
3784         if (!cstate->base.active)
3785                 return;
3786
3787         /* Until we know more, just disable transition WMs */
3788         trans_wm->plane_en = false;
3789 }
3790
3791 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3792                              struct skl_ddb_allocation *ddb,
3793                              struct skl_pipe_wm *pipe_wm)
3794 {
3795         struct drm_device *dev = cstate->base.crtc->dev;
3796         const struct drm_i915_private *dev_priv = to_i915(dev);
3797         struct intel_plane *intel_plane;
3798         struct skl_plane_wm *wm;
3799         int level, max_level = ilk_wm_max_level(dev_priv);
3800         int ret;
3801
3802         /*
3803          * We'll only calculate watermarks for planes that are actually
3804          * enabled, so make sure all other planes are set as disabled.
3805          */
3806         memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3807
3808         for_each_intel_plane_mask(&dev_priv->drm,
3809                                   intel_plane,
3810                                   cstate->base.plane_mask) {
3811                 wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
3812
3813                 for (level = 0; level <= max_level; level++) {
3814                         ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3815                                                    intel_plane, level,
3816                                                    &wm->wm[level]);
3817                         if (ret)
3818                                 return ret;
3819                 }
3820                 skl_compute_transition_wm(cstate, &wm->trans_wm);
3821         }
3822         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3823
3824         return 0;
3825 }
3826
3827 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3828                                 i915_reg_t reg,
3829                                 const struct skl_ddb_entry *entry)
3830 {
3831         if (entry->end)
3832                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3833         else
3834                 I915_WRITE(reg, 0);
3835 }
3836
3837 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3838                                i915_reg_t reg,
3839                                const struct skl_wm_level *level)
3840 {
3841         uint32_t val = 0;
3842
3843         if (level->plane_en) {
3844                 val |= PLANE_WM_EN;
3845                 val |= level->plane_res_b;
3846                 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3847         }
3848
3849         I915_WRITE(reg, val);
3850 }
3851
3852 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3853                         const struct skl_plane_wm *wm,
3854                         const struct skl_ddb_allocation *ddb,
3855                         int plane)
3856 {
3857         struct drm_crtc *crtc = &intel_crtc->base;
3858         struct drm_device *dev = crtc->dev;
3859         struct drm_i915_private *dev_priv = to_i915(dev);
3860         int level, max_level = ilk_wm_max_level(dev_priv);
3861         enum pipe pipe = intel_crtc->pipe;
3862
3863         for (level = 0; level <= max_level; level++) {
3864                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane, level),
3865                                    &wm->wm[level]);
3866         }
3867         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
3868                            &wm->trans_wm);
3869
3870         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3871                             &ddb->plane[pipe][plane]);
3872         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3873                             &ddb->y_plane[pipe][plane]);
3874 }
3875
3876 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3877                          const struct skl_plane_wm *wm,
3878                          const struct skl_ddb_allocation *ddb)
3879 {
3880         struct drm_crtc *crtc = &intel_crtc->base;
3881         struct drm_device *dev = crtc->dev;
3882         struct drm_i915_private *dev_priv = to_i915(dev);
3883         int level, max_level = ilk_wm_max_level(dev_priv);
3884         enum pipe pipe = intel_crtc->pipe;
3885
3886         for (level = 0; level <= max_level; level++) {
3887                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3888                                    &wm->wm[level]);
3889         }
3890         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
3891
3892         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3893                             &ddb->plane[pipe][PLANE_CURSOR]);
3894 }
3895
3896 bool skl_wm_level_equals(const struct skl_wm_level *l1,
3897                          const struct skl_wm_level *l2)
3898 {
3899         if (l1->plane_en != l2->plane_en)
3900                 return false;
3901
3902         /* If both planes aren't enabled, the rest shouldn't matter */
3903         if (!l1->plane_en)
3904                 return true;
3905
3906         return (l1->plane_res_l == l2->plane_res_l &&
3907                 l1->plane_res_b == l2->plane_res_b);
3908 }
3909
3910 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3911                                            const struct skl_ddb_entry *b)
3912 {
3913         return a->start < b->end && b->start < a->end;
3914 }
3915
3916 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
3917                                  const struct skl_ddb_entry *ddb,
3918                                  int ignore)
3919 {
3920         int i;
3921
3922         for (i = 0; i < I915_MAX_PIPES; i++)
3923                 if (i != ignore && entries[i] &&
3924                     skl_ddb_entries_overlap(ddb, entries[i]))
3925                         return true;
3926
3927         return false;
3928 }
3929
3930 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3931                               const struct skl_pipe_wm *old_pipe_wm,
3932                               struct skl_pipe_wm *pipe_wm, /* out */
3933                               struct skl_ddb_allocation *ddb, /* out */
3934                               bool *changed /* out */)
3935 {
3936         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3937         int ret;
3938
3939         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3940         if (ret)
3941                 return ret;
3942
3943         if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
3944                 *changed = false;
3945         else
3946                 *changed = true;
3947
3948         return 0;
3949 }
3950
3951 static uint32_t
3952 pipes_modified(struct drm_atomic_state *state)
3953 {
3954         struct drm_crtc *crtc;
3955         struct drm_crtc_state *cstate;
3956         uint32_t i, ret = 0;
3957
3958         for_each_crtc_in_state(state, crtc, cstate, i)
3959                 ret |= drm_crtc_mask(crtc);
3960
3961         return ret;
3962 }
3963
3964 static int
3965 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3966 {
3967         struct drm_atomic_state *state = cstate->base.state;
3968         struct drm_device *dev = state->dev;
3969         struct drm_crtc *crtc = cstate->base.crtc;
3970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3971         struct drm_i915_private *dev_priv = to_i915(dev);
3972         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3973         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3974         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3975         struct drm_plane_state *plane_state;
3976         struct drm_plane *plane;
3977         enum pipe pipe = intel_crtc->pipe;
3978         int id;
3979
3980         WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3981
3982         drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
3983                 id = skl_wm_plane_id(to_intel_plane(plane));
3984
3985                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3986                                         &new_ddb->plane[pipe][id]) &&
3987                     skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3988                                         &new_ddb->y_plane[pipe][id]))
3989                         continue;
3990
3991                 plane_state = drm_atomic_get_plane_state(state, plane);
3992                 if (IS_ERR(plane_state))
3993                         return PTR_ERR(plane_state);
3994         }
3995
3996         return 0;
3997 }
3998
3999 static int
4000 skl_compute_ddb(struct drm_atomic_state *state)
4001 {
4002         struct drm_device *dev = state->dev;
4003         struct drm_i915_private *dev_priv = to_i915(dev);
4004         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4005         struct intel_crtc *intel_crtc;
4006         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4007         uint32_t realloc_pipes = pipes_modified(state);
4008         int ret;
4009
4010         /*
4011          * If this is our first atomic update following hardware readout,
4012          * we can't trust the DDB that the BIOS programmed for us.  Let's
4013          * pretend that all pipes switched active status so that we'll
4014          * ensure a full DDB recompute.
4015          */
4016         if (dev_priv->wm.distrust_bios_wm) {
4017                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4018                                        state->acquire_ctx);
4019                 if (ret)
4020                         return ret;
4021
4022                 intel_state->active_pipe_changes = ~0;
4023
4024                 /*
4025                  * We usually only initialize intel_state->active_crtcs if we
4026                  * we're doing a modeset; make sure this field is always
4027                  * initialized during the sanitization process that happens
4028                  * on the first commit too.
4029                  */
4030                 if (!intel_state->modeset)
4031                         intel_state->active_crtcs = dev_priv->active_crtcs;
4032         }
4033
4034         /*
4035          * If the modeset changes which CRTC's are active, we need to
4036          * recompute the DDB allocation for *all* active pipes, even
4037          * those that weren't otherwise being modified in any way by this
4038          * atomic commit.  Due to the shrinking of the per-pipe allocations
4039          * when new active CRTC's are added, it's possible for a pipe that
4040          * we were already using and aren't changing at all here to suddenly
4041          * become invalid if its DDB needs exceeds its new allocation.
4042          *
4043          * Note that if we wind up doing a full DDB recompute, we can't let
4044          * any other display updates race with this transaction, so we need
4045          * to grab the lock on *all* CRTC's.
4046          */
4047         if (intel_state->active_pipe_changes) {
4048                 realloc_pipes = ~0;
4049                 intel_state->wm_results.dirty_pipes = ~0;
4050         }
4051
4052         /*
4053          * We're not recomputing for the pipes not included in the commit, so
4054          * make sure we start with the current state.
4055          */
4056         memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4057
4058         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4059                 struct intel_crtc_state *cstate;
4060
4061                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4062                 if (IS_ERR(cstate))
4063                         return PTR_ERR(cstate);
4064
4065                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4066                 if (ret)
4067                         return ret;
4068
4069                 ret = skl_ddb_add_affected_planes(cstate);
4070                 if (ret)
4071                         return ret;
4072         }
4073
4074         return 0;
4075 }
4076
4077 static void
4078 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4079                      struct skl_wm_values *src,
4080                      enum pipe pipe)
4081 {
4082         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4083                sizeof(dst->ddb.y_plane[pipe]));
4084         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4085                sizeof(dst->ddb.plane[pipe]));
4086 }
4087
4088 static void
4089 skl_print_wm_changes(const struct drm_atomic_state *state)
4090 {
4091         const struct drm_device *dev = state->dev;
4092         const struct drm_i915_private *dev_priv = to_i915(dev);
4093         const struct intel_atomic_state *intel_state =
4094                 to_intel_atomic_state(state);
4095         const struct drm_crtc *crtc;
4096         const struct drm_crtc_state *cstate;
4097         const struct intel_plane *intel_plane;
4098         const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4099         const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4100         int id;
4101         int i;
4102
4103         for_each_crtc_in_state(state, crtc, cstate, i) {
4104                 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4105                 enum pipe pipe = intel_crtc->pipe;
4106
4107                 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4108                         const struct skl_ddb_entry *old, *new;
4109
4110                         id = skl_wm_plane_id(intel_plane);
4111                         old = &old_ddb->plane[pipe][id];
4112                         new = &new_ddb->plane[pipe][id];
4113
4114                         if (skl_ddb_entry_equal(old, new))
4115                                 continue;
4116
4117                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4118                                          intel_plane->base.base.id,
4119                                          intel_plane->base.name,
4120                                          old->start, old->end,
4121                                          new->start, new->end);
4122                 }
4123         }
4124 }
4125
4126 static int
4127 skl_compute_wm(struct drm_atomic_state *state)
4128 {
4129         struct drm_crtc *crtc;
4130         struct drm_crtc_state *cstate;
4131         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4132         struct skl_wm_values *results = &intel_state->wm_results;
4133         struct skl_pipe_wm *pipe_wm;
4134         bool changed = false;
4135         int ret, i;
4136
4137         /*
4138          * If this transaction isn't actually touching any CRTC's, don't
4139          * bother with watermark calculation.  Note that if we pass this
4140          * test, we're guaranteed to hold at least one CRTC state mutex,
4141          * which means we can safely use values like dev_priv->active_crtcs
4142          * since any racing commits that want to update them would need to
4143          * hold _all_ CRTC state mutexes.
4144          */
4145         for_each_crtc_in_state(state, crtc, cstate, i)
4146                 changed = true;
4147         if (!changed)
4148                 return 0;
4149
4150         /* Clear all dirty flags */
4151         results->dirty_pipes = 0;
4152
4153         ret = skl_compute_ddb(state);
4154         if (ret)
4155                 return ret;
4156
4157         /*
4158          * Calculate WM's for all pipes that are part of this transaction.
4159          * Note that the DDB allocation above may have added more CRTC's that
4160          * weren't otherwise being modified (and set bits in dirty_pipes) if
4161          * pipe allocations had to change.
4162          *
4163          * FIXME:  Now that we're doing this in the atomic check phase, we
4164          * should allow skl_update_pipe_wm() to return failure in cases where
4165          * no suitable watermark values can be found.
4166          */
4167         for_each_crtc_in_state(state, crtc, cstate, i) {
4168                 struct intel_crtc_state *intel_cstate =
4169                         to_intel_crtc_state(cstate);
4170                 const struct skl_pipe_wm *old_pipe_wm =
4171                         &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
4172
4173                 pipe_wm = &intel_cstate->wm.skl.optimal;
4174                 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4175                                          &results->ddb, &changed);
4176                 if (ret)
4177                         return ret;
4178
4179                 if (changed)
4180                         results->dirty_pipes |= drm_crtc_mask(crtc);
4181
4182                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4183                         /* This pipe's WM's did not change */
4184                         continue;
4185
4186                 intel_cstate->update_wm_pre = true;
4187         }
4188
4189         skl_print_wm_changes(state);
4190
4191         return 0;
4192 }
4193
4194 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
4195                                       struct intel_crtc_state *cstate)
4196 {
4197         struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
4198         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4199         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4200         const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
4201         enum pipe pipe = crtc->pipe;
4202         int plane;
4203
4204         if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
4205                 return;
4206
4207         I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
4208
4209         for_each_universal_plane(dev_priv, pipe, plane)
4210                 skl_write_plane_wm(crtc, &pipe_wm->planes[plane], ddb, plane);
4211
4212         skl_write_cursor_wm(crtc, &pipe_wm->planes[PLANE_CURSOR], ddb);
4213 }
4214
4215 static void skl_initial_wm(struct intel_atomic_state *state,
4216                            struct intel_crtc_state *cstate)
4217 {
4218         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4219         struct drm_device *dev = intel_crtc->base.dev;
4220         struct drm_i915_private *dev_priv = to_i915(dev);
4221         struct skl_wm_values *results = &state->wm_results;
4222         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4223         enum pipe pipe = intel_crtc->pipe;
4224
4225         if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
4226                 return;
4227
4228         mutex_lock(&dev_priv->wm.wm_mutex);
4229
4230         if (cstate->base.active_changed)
4231                 skl_atomic_update_crtc_wm(state, cstate);
4232
4233         skl_copy_wm_for_pipe(hw_vals, results, pipe);
4234
4235         mutex_unlock(&dev_priv->wm.wm_mutex);
4236 }
4237
4238 static void ilk_compute_wm_config(struct drm_device *dev,
4239                                   struct intel_wm_config *config)
4240 {
4241         struct intel_crtc *crtc;
4242
4243         /* Compute the currently _active_ config */
4244         for_each_intel_crtc(dev, crtc) {
4245                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4246
4247                 if (!wm->pipe_enabled)
4248                         continue;
4249
4250                 config->sprites_enabled |= wm->sprites_enabled;
4251                 config->sprites_scaled |= wm->sprites_scaled;
4252                 config->num_pipes_active++;
4253         }
4254 }
4255
4256 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4257 {
4258         struct drm_device *dev = &dev_priv->drm;
4259         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4260         struct ilk_wm_maximums max;
4261         struct intel_wm_config config = {};
4262         struct ilk_wm_values results = {};
4263         enum intel_ddb_partitioning partitioning;
4264
4265         ilk_compute_wm_config(dev, &config);
4266
4267         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4268         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4269
4270         /* 5/6 split only in single pipe config on IVB+ */
4271         if (INTEL_INFO(dev)->gen >= 7 &&
4272             config.num_pipes_active == 1 && config.sprites_enabled) {
4273                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4274                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4275
4276                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4277         } else {
4278                 best_lp_wm = &lp_wm_1_2;
4279         }
4280
4281         partitioning = (best_lp_wm == &lp_wm_1_2) ?
4282                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4283
4284         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4285
4286         ilk_write_wm_values(dev_priv, &results);
4287 }
4288
4289 static void ilk_initial_watermarks(struct intel_atomic_state *state,
4290                                    struct intel_crtc_state *cstate)
4291 {
4292         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4293         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4294
4295         mutex_lock(&dev_priv->wm.wm_mutex);
4296         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4297         ilk_program_watermarks(dev_priv);
4298         mutex_unlock(&dev_priv->wm.wm_mutex);
4299 }
4300
4301 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
4302                                     struct intel_crtc_state *cstate)
4303 {
4304         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4305         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4306
4307         mutex_lock(&dev_priv->wm.wm_mutex);
4308         if (cstate->wm.need_postvbl_update) {
4309                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4310                 ilk_program_watermarks(dev_priv);
4311         }
4312         mutex_unlock(&dev_priv->wm.wm_mutex);
4313 }
4314
4315 static inline void skl_wm_level_from_reg_val(uint32_t val,
4316                                              struct skl_wm_level *level)
4317 {
4318         level->plane_en = val & PLANE_WM_EN;
4319         level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4320         level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4321                 PLANE_WM_LINES_MASK;
4322 }
4323
4324 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4325                               struct skl_pipe_wm *out)
4326 {
4327         struct drm_device *dev = crtc->dev;
4328         struct drm_i915_private *dev_priv = to_i915(dev);
4329         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4330         struct intel_plane *intel_plane;
4331         struct skl_plane_wm *wm;
4332         enum pipe pipe = intel_crtc->pipe;
4333         int level, id, max_level;
4334         uint32_t val;
4335
4336         max_level = ilk_wm_max_level(dev_priv);
4337
4338         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4339                 id = skl_wm_plane_id(intel_plane);
4340                 wm = &out->planes[id];
4341
4342                 for (level = 0; level <= max_level; level++) {
4343                         if (id != PLANE_CURSOR)
4344                                 val = I915_READ(PLANE_WM(pipe, id, level));
4345                         else
4346                                 val = I915_READ(CUR_WM(pipe, level));
4347
4348                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
4349                 }
4350
4351                 if (id != PLANE_CURSOR)
4352                         val = I915_READ(PLANE_WM_TRANS(pipe, id));
4353                 else
4354                         val = I915_READ(CUR_WM_TRANS(pipe));
4355
4356                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
4357         }
4358
4359         if (!intel_crtc->active)
4360                 return;
4361
4362         out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
4363 }
4364
4365 void skl_wm_get_hw_state(struct drm_device *dev)
4366 {
4367         struct drm_i915_private *dev_priv = to_i915(dev);
4368         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4369         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4370         struct drm_crtc *crtc;
4371         struct intel_crtc *intel_crtc;
4372         struct intel_crtc_state *cstate;
4373
4374         skl_ddb_get_hw_state(dev_priv, ddb);
4375         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4376                 intel_crtc = to_intel_crtc(crtc);
4377                 cstate = to_intel_crtc_state(crtc->state);
4378
4379                 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4380
4381                 if (intel_crtc->active)
4382                         hw->dirty_pipes |= drm_crtc_mask(crtc);
4383         }
4384
4385         if (dev_priv->active_crtcs) {
4386                 /* Fully recompute DDB on first atomic commit */
4387                 dev_priv->wm.distrust_bios_wm = true;
4388         } else {
4389                 /* Easy/common case; just sanitize DDB now if everything off */
4390                 memset(ddb, 0, sizeof(*ddb));
4391         }
4392 }
4393
4394 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4395 {
4396         struct drm_device *dev = crtc->dev;
4397         struct drm_i915_private *dev_priv = to_i915(dev);
4398         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4400         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4401         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4402         enum pipe pipe = intel_crtc->pipe;
4403         static const i915_reg_t wm0_pipe_reg[] = {
4404                 [PIPE_A] = WM0_PIPEA_ILK,
4405                 [PIPE_B] = WM0_PIPEB_ILK,
4406                 [PIPE_C] = WM0_PIPEC_IVB,
4407         };
4408
4409         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4410         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4411                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4412
4413         memset(active, 0, sizeof(*active));
4414
4415         active->pipe_enabled = intel_crtc->active;
4416
4417         if (active->pipe_enabled) {
4418                 u32 tmp = hw->wm_pipe[pipe];
4419
4420                 /*
4421                  * For active pipes LP0 watermark is marked as
4422                  * enabled, and LP1+ watermaks as disabled since
4423                  * we can't really reverse compute them in case
4424                  * multiple pipes are active.
4425                  */
4426                 active->wm[0].enable = true;
4427                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4428                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4429                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4430                 active->linetime = hw->wm_linetime[pipe];
4431         } else {
4432                 int level, max_level = ilk_wm_max_level(dev_priv);
4433
4434                 /*
4435                  * For inactive pipes, all watermark levels
4436                  * should be marked as enabled but zeroed,
4437                  * which is what we'd compute them to.
4438                  */
4439                 for (level = 0; level <= max_level; level++)
4440                         active->wm[level].enable = true;
4441         }
4442
4443         intel_crtc->wm.active.ilk = *active;
4444 }
4445
4446 #define _FW_WM(value, plane) \
4447         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4448 #define _FW_WM_VLV(value, plane) \
4449         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4450
4451 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4452                                struct vlv_wm_values *wm)
4453 {
4454         enum pipe pipe;
4455         uint32_t tmp;
4456
4457         for_each_pipe(dev_priv, pipe) {
4458                 tmp = I915_READ(VLV_DDL(pipe));
4459
4460                 wm->ddl[pipe].primary =
4461                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4462                 wm->ddl[pipe].cursor =
4463                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4464                 wm->ddl[pipe].sprite[0] =
4465                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4466                 wm->ddl[pipe].sprite[1] =
4467                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4468         }
4469
4470         tmp = I915_READ(DSPFW1);
4471         wm->sr.plane = _FW_WM(tmp, SR);
4472         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4473         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4474         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4475
4476         tmp = I915_READ(DSPFW2);
4477         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4478         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4479         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4480
4481         tmp = I915_READ(DSPFW3);
4482         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4483
4484         if (IS_CHERRYVIEW(dev_priv)) {
4485                 tmp = I915_READ(DSPFW7_CHV);
4486                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4487                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4488
4489                 tmp = I915_READ(DSPFW8_CHV);
4490                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4491                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4492
4493                 tmp = I915_READ(DSPFW9_CHV);
4494                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4495                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4496
4497                 tmp = I915_READ(DSPHOWM);
4498                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4499                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4500                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4501                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4502                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4503                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4504                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4505                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4506                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4507                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4508         } else {
4509                 tmp = I915_READ(DSPFW7);
4510                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4511                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4512
4513                 tmp = I915_READ(DSPHOWM);
4514                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4515                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4516                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4517                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4518                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4519                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4520                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4521         }
4522 }
4523
4524 #undef _FW_WM
4525 #undef _FW_WM_VLV
4526
4527 void vlv_wm_get_hw_state(struct drm_device *dev)
4528 {
4529         struct drm_i915_private *dev_priv = to_i915(dev);
4530         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4531         struct intel_plane *plane;
4532         enum pipe pipe;
4533         u32 val;
4534
4535         vlv_read_wm_values(dev_priv, wm);
4536
4537         for_each_intel_plane(dev, plane) {
4538                 switch (plane->base.type) {
4539                         int sprite;
4540                 case DRM_PLANE_TYPE_CURSOR:
4541                         plane->wm.fifo_size = 63;
4542                         break;
4543                 case DRM_PLANE_TYPE_PRIMARY:
4544                         plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, 0);
4545                         break;
4546                 case DRM_PLANE_TYPE_OVERLAY:
4547                         sprite = plane->plane;
4548                         plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, sprite + 1);
4549                         break;
4550                 }
4551         }
4552
4553         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4554         wm->level = VLV_WM_LEVEL_PM2;
4555
4556         if (IS_CHERRYVIEW(dev_priv)) {
4557                 mutex_lock(&dev_priv->rps.hw_lock);
4558
4559                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4560                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4561                         wm->level = VLV_WM_LEVEL_PM5;
4562
4563                 /*
4564                  * If DDR DVFS is disabled in the BIOS, Punit
4565                  * will never ack the request. So if that happens
4566                  * assume we don't have to enable/disable DDR DVFS
4567                  * dynamically. To test that just set the REQ_ACK
4568                  * bit to poke the Punit, but don't change the
4569                  * HIGH/LOW bits so that we don't actually change
4570                  * the current state.
4571                  */
4572                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4573                 val |= FORCE_DDR_FREQ_REQ_ACK;
4574                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4575
4576                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4577                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4578                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4579                                       "assuming DDR DVFS is disabled\n");
4580                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4581                 } else {
4582                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4583                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4584                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4585                 }
4586
4587                 mutex_unlock(&dev_priv->rps.hw_lock);
4588         }
4589
4590         for_each_pipe(dev_priv, pipe)
4591                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4592                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4593                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4594
4595         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4596                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4597 }
4598
4599 void ilk_wm_get_hw_state(struct drm_device *dev)
4600 {
4601         struct drm_i915_private *dev_priv = to_i915(dev);
4602         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4603         struct drm_crtc *crtc;
4604
4605         for_each_crtc(dev, crtc)
4606                 ilk_pipe_wm_get_hw_state(crtc);
4607
4608         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4609         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4610         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4611
4612         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4613         if (INTEL_INFO(dev)->gen >= 7) {
4614                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4615                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4616         }
4617
4618         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4619                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4620                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4621         else if (IS_IVYBRIDGE(dev_priv))
4622                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4623                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4624
4625         hw->enable_fbc_wm =
4626                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4627 }
4628
4629 /**
4630  * intel_update_watermarks - update FIFO watermark values based on current modes
4631  *
4632  * Calculate watermark values for the various WM regs based on current mode
4633  * and plane configuration.
4634  *
4635  * There are several cases to deal with here:
4636  *   - normal (i.e. non-self-refresh)
4637  *   - self-refresh (SR) mode
4638  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4639  *   - lines are small relative to FIFO size (buffer can hold more than 2
4640  *     lines), so need to account for TLB latency
4641  *
4642  *   The normal calculation is:
4643  *     watermark = dotclock * bytes per pixel * latency
4644  *   where latency is platform & configuration dependent (we assume pessimal
4645  *   values here).
4646  *
4647  *   The SR calculation is:
4648  *     watermark = (trunc(latency/line time)+1) * surface width *
4649  *       bytes per pixel
4650  *   where
4651  *     line time = htotal / dotclock
4652  *     surface width = hdisplay for normal plane and 64 for cursor
4653  *   and latency is assumed to be high, as above.
4654  *
4655  * The final value programmed to the register should always be rounded up,
4656  * and include an extra 2 entries to account for clock crossings.
4657  *
4658  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4659  * to set the non-SR watermarks to 8.
4660  */
4661 void intel_update_watermarks(struct intel_crtc *crtc)
4662 {
4663         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4664
4665         if (dev_priv->display.update_wm)
4666                 dev_priv->display.update_wm(crtc);
4667 }
4668
4669 /*
4670  * Lock protecting IPS related data structures
4671  */
4672 DEFINE_SPINLOCK(mchdev_lock);
4673
4674 /* Global for IPS driver to get at the current i915 device. Protected by
4675  * mchdev_lock. */
4676 static struct drm_i915_private *i915_mch_dev;
4677
4678 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4679 {
4680         u16 rgvswctl;
4681
4682         assert_spin_locked(&mchdev_lock);
4683
4684         rgvswctl = I915_READ16(MEMSWCTL);
4685         if (rgvswctl & MEMCTL_CMD_STS) {
4686                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4687                 return false; /* still busy with another command */
4688         }
4689
4690         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4691                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4692         I915_WRITE16(MEMSWCTL, rgvswctl);
4693         POSTING_READ16(MEMSWCTL);
4694
4695         rgvswctl |= MEMCTL_CMD_STS;
4696         I915_WRITE16(MEMSWCTL, rgvswctl);
4697
4698         return true;
4699 }
4700
4701 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4702 {
4703         u32 rgvmodectl;
4704         u8 fmax, fmin, fstart, vstart;
4705
4706         spin_lock_irq(&mchdev_lock);
4707
4708         rgvmodectl = I915_READ(MEMMODECTL);
4709
4710         /* Enable temp reporting */
4711         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4712         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4713
4714         /* 100ms RC evaluation intervals */
4715         I915_WRITE(RCUPEI, 100000);
4716         I915_WRITE(RCDNEI, 100000);
4717
4718         /* Set max/min thresholds to 90ms and 80ms respectively */
4719         I915_WRITE(RCBMAXAVG, 90000);
4720         I915_WRITE(RCBMINAVG, 80000);
4721
4722         I915_WRITE(MEMIHYST, 1);
4723
4724         /* Set up min, max, and cur for interrupt handling */
4725         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4726         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4727         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4728                 MEMMODE_FSTART_SHIFT;
4729
4730         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4731                 PXVFREQ_PX_SHIFT;
4732
4733         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4734         dev_priv->ips.fstart = fstart;
4735
4736         dev_priv->ips.max_delay = fstart;
4737         dev_priv->ips.min_delay = fmin;
4738         dev_priv->ips.cur_delay = fstart;
4739
4740         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4741                          fmax, fmin, fstart);
4742
4743         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4744
4745         /*
4746          * Interrupts will be enabled in ironlake_irq_postinstall
4747          */
4748
4749         I915_WRITE(VIDSTART, vstart);
4750         POSTING_READ(VIDSTART);
4751
4752         rgvmodectl |= MEMMODE_SWMODE_EN;
4753         I915_WRITE(MEMMODECTL, rgvmodectl);
4754
4755         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4756                 DRM_ERROR("stuck trying to change perf mode\n");
4757         mdelay(1);
4758
4759         ironlake_set_drps(dev_priv, fstart);
4760
4761         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4762                 I915_READ(DDREC) + I915_READ(CSIEC);
4763         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4764         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4765         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4766
4767         spin_unlock_irq(&mchdev_lock);
4768 }
4769
4770 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4771 {
4772         u16 rgvswctl;
4773
4774         spin_lock_irq(&mchdev_lock);
4775
4776         rgvswctl = I915_READ16(MEMSWCTL);
4777
4778         /* Ack interrupts, disable EFC interrupt */
4779         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4780         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4781         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4782         I915_WRITE(DEIIR, DE_PCU_EVENT);
4783         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4784
4785         /* Go back to the starting frequency */
4786         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4787         mdelay(1);
4788         rgvswctl |= MEMCTL_CMD_STS;
4789         I915_WRITE(MEMSWCTL, rgvswctl);
4790         mdelay(1);
4791
4792         spin_unlock_irq(&mchdev_lock);
4793 }
4794
4795 /* There's a funny hw issue where the hw returns all 0 when reading from
4796  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4797  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4798  * all limits and the gpu stuck at whatever frequency it is at atm).
4799  */
4800 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4801 {
4802         u32 limits;
4803
4804         /* Only set the down limit when we've reached the lowest level to avoid
4805          * getting more interrupts, otherwise leave this clear. This prevents a
4806          * race in the hw when coming out of rc6: There's a tiny window where
4807          * the hw runs at the minimal clock before selecting the desired
4808          * frequency, if the down threshold expires in that window we will not
4809          * receive a down interrupt. */
4810         if (IS_GEN9(dev_priv)) {
4811                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4812                 if (val <= dev_priv->rps.min_freq_softlimit)
4813                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4814         } else {
4815                 limits = dev_priv->rps.max_freq_softlimit << 24;
4816                 if (val <= dev_priv->rps.min_freq_softlimit)
4817                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4818         }
4819
4820         return limits;
4821 }
4822
4823 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4824 {
4825         int new_power;
4826         u32 threshold_up = 0, threshold_down = 0; /* in % */
4827         u32 ei_up = 0, ei_down = 0;
4828
4829         new_power = dev_priv->rps.power;
4830         switch (dev_priv->rps.power) {
4831         case LOW_POWER:
4832                 if (val > dev_priv->rps.efficient_freq + 1 &&
4833                     val > dev_priv->rps.cur_freq)
4834                         new_power = BETWEEN;
4835                 break;
4836
4837         case BETWEEN:
4838                 if (val <= dev_priv->rps.efficient_freq &&
4839                     val < dev_priv->rps.cur_freq)
4840                         new_power = LOW_POWER;
4841                 else if (val >= dev_priv->rps.rp0_freq &&
4842                          val > dev_priv->rps.cur_freq)
4843                         new_power = HIGH_POWER;
4844                 break;
4845
4846         case HIGH_POWER:
4847                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4848                     val < dev_priv->rps.cur_freq)
4849                         new_power = BETWEEN;
4850                 break;
4851         }
4852         /* Max/min bins are special */
4853         if (val <= dev_priv->rps.min_freq_softlimit)
4854                 new_power = LOW_POWER;
4855         if (val >= dev_priv->rps.max_freq_softlimit)
4856                 new_power = HIGH_POWER;
4857         if (new_power == dev_priv->rps.power)
4858                 return;
4859
4860         /* Note the units here are not exactly 1us, but 1280ns. */
4861         switch (new_power) {
4862         case LOW_POWER:
4863                 /* Upclock if more than 95% busy over 16ms */
4864                 ei_up = 16000;
4865                 threshold_up = 95;
4866
4867                 /* Downclock if less than 85% busy over 32ms */
4868                 ei_down = 32000;
4869                 threshold_down = 85;
4870                 break;
4871
4872         case BETWEEN:
4873                 /* Upclock if more than 90% busy over 13ms */
4874                 ei_up = 13000;
4875                 threshold_up = 90;
4876
4877                 /* Downclock if less than 75% busy over 32ms */
4878                 ei_down = 32000;
4879                 threshold_down = 75;
4880                 break;
4881
4882         case HIGH_POWER:
4883                 /* Upclock if more than 85% busy over 10ms */
4884                 ei_up = 10000;
4885                 threshold_up = 85;
4886
4887                 /* Downclock if less than 60% busy over 32ms */
4888                 ei_down = 32000;
4889                 threshold_down = 60;
4890                 break;
4891         }
4892
4893         I915_WRITE(GEN6_RP_UP_EI,
4894                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
4895         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4896                    GT_INTERVAL_FROM_US(dev_priv,
4897                                        ei_up * threshold_up / 100));
4898
4899         I915_WRITE(GEN6_RP_DOWN_EI,
4900                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
4901         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4902                    GT_INTERVAL_FROM_US(dev_priv,
4903                                        ei_down * threshold_down / 100));
4904
4905         I915_WRITE(GEN6_RP_CONTROL,
4906                    GEN6_RP_MEDIA_TURBO |
4907                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4908                    GEN6_RP_MEDIA_IS_GFX |
4909                    GEN6_RP_ENABLE |
4910                    GEN6_RP_UP_BUSY_AVG |
4911                    GEN6_RP_DOWN_IDLE_AVG);
4912
4913         dev_priv->rps.power = new_power;
4914         dev_priv->rps.up_threshold = threshold_up;
4915         dev_priv->rps.down_threshold = threshold_down;
4916         dev_priv->rps.last_adj = 0;
4917 }
4918
4919 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4920 {
4921         u32 mask = 0;
4922
4923         if (val > dev_priv->rps.min_freq_softlimit)
4924                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4925         if (val < dev_priv->rps.max_freq_softlimit)
4926                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4927
4928         mask &= dev_priv->pm_rps_events;
4929
4930         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4931 }
4932
4933 /* gen6_set_rps is called to update the frequency request, but should also be
4934  * called when the range (min_delay and max_delay) is modified so that we can
4935  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4936 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4937 {
4938         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4939         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4940                 return;
4941
4942         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4943         WARN_ON(val > dev_priv->rps.max_freq);
4944         WARN_ON(val < dev_priv->rps.min_freq);
4945
4946         /* min/max delay may still have been modified so be sure to
4947          * write the limits value.
4948          */
4949         if (val != dev_priv->rps.cur_freq) {
4950                 gen6_set_rps_thresholds(dev_priv, val);
4951
4952                 if (IS_GEN9(dev_priv))
4953                         I915_WRITE(GEN6_RPNSWREQ,
4954                                    GEN9_FREQUENCY(val));
4955                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4956                         I915_WRITE(GEN6_RPNSWREQ,
4957                                    HSW_FREQUENCY(val));
4958                 else
4959                         I915_WRITE(GEN6_RPNSWREQ,
4960                                    GEN6_FREQUENCY(val) |
4961                                    GEN6_OFFSET(0) |
4962                                    GEN6_AGGRESSIVE_TURBO);
4963         }
4964
4965         /* Make sure we continue to get interrupts
4966          * until we hit the minimum or maximum frequencies.
4967          */
4968         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4969         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4970
4971         POSTING_READ(GEN6_RPNSWREQ);
4972
4973         dev_priv->rps.cur_freq = val;
4974         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4975 }
4976
4977 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4978 {
4979         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4980         WARN_ON(val > dev_priv->rps.max_freq);
4981         WARN_ON(val < dev_priv->rps.min_freq);
4982
4983         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4984                       "Odd GPU freq value\n"))
4985                 val &= ~1;
4986
4987         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4988
4989         if (val != dev_priv->rps.cur_freq) {
4990                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4991                 if (!IS_CHERRYVIEW(dev_priv))
4992                         gen6_set_rps_thresholds(dev_priv, val);
4993         }
4994
4995         dev_priv->rps.cur_freq = val;
4996         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4997 }
4998
4999 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
5000  *
5001  * * If Gfx is Idle, then
5002  * 1. Forcewake Media well.
5003  * 2. Request idle freq.
5004  * 3. Release Forcewake of Media well.
5005 */
5006 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5007 {
5008         u32 val = dev_priv->rps.idle_freq;
5009
5010         if (dev_priv->rps.cur_freq <= val)
5011                 return;
5012
5013         /* Wake up the media well, as that takes a lot less
5014          * power than the Render well. */
5015         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5016         valleyview_set_rps(dev_priv, val);
5017         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5018 }
5019
5020 void gen6_rps_busy(struct drm_i915_private *dev_priv)
5021 {
5022         mutex_lock(&dev_priv->rps.hw_lock);
5023         if (dev_priv->rps.enabled) {
5024                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5025                         gen6_rps_reset_ei(dev_priv);
5026                 I915_WRITE(GEN6_PMINTRMSK,
5027                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5028
5029                 gen6_enable_rps_interrupts(dev_priv);
5030
5031                 /* Ensure we start at the user's desired frequency */
5032                 intel_set_rps(dev_priv,
5033                               clamp(dev_priv->rps.cur_freq,
5034                                     dev_priv->rps.min_freq_softlimit,
5035                                     dev_priv->rps.max_freq_softlimit));
5036         }
5037         mutex_unlock(&dev_priv->rps.hw_lock);
5038 }
5039
5040 void gen6_rps_idle(struct drm_i915_private *dev_priv)
5041 {
5042         /* Flush our bottom-half so that it does not race with us
5043          * setting the idle frequency and so that it is bounded by
5044          * our rpm wakeref. And then disable the interrupts to stop any
5045          * futher RPS reclocking whilst we are asleep.
5046          */
5047         gen6_disable_rps_interrupts(dev_priv);
5048
5049         mutex_lock(&dev_priv->rps.hw_lock);
5050         if (dev_priv->rps.enabled) {
5051                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5052                         vlv_set_rps_idle(dev_priv);
5053                 else
5054                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5055                 dev_priv->rps.last_adj = 0;
5056                 I915_WRITE(GEN6_PMINTRMSK,
5057                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5058         }
5059         mutex_unlock(&dev_priv->rps.hw_lock);
5060
5061         spin_lock(&dev_priv->rps.client_lock);
5062         while (!list_empty(&dev_priv->rps.clients))
5063                 list_del_init(dev_priv->rps.clients.next);
5064         spin_unlock(&dev_priv->rps.client_lock);
5065 }
5066
5067 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5068                     struct intel_rps_client *rps,
5069                     unsigned long submitted)
5070 {
5071         /* This is intentionally racy! We peek at the state here, then
5072          * validate inside the RPS worker.
5073          */
5074         if (!(dev_priv->gt.awake &&
5075               dev_priv->rps.enabled &&
5076               dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5077                 return;
5078
5079         /* Force a RPS boost (and don't count it against the client) if
5080          * the GPU is severely congested.
5081          */
5082         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5083                 rps = NULL;
5084
5085         spin_lock(&dev_priv->rps.client_lock);
5086         if (rps == NULL || list_empty(&rps->link)) {
5087                 spin_lock_irq(&dev_priv->irq_lock);
5088                 if (dev_priv->rps.interrupts_enabled) {
5089                         dev_priv->rps.client_boost = true;
5090                         schedule_work(&dev_priv->rps.work);
5091                 }
5092                 spin_unlock_irq(&dev_priv->irq_lock);
5093
5094                 if (rps != NULL) {
5095                         list_add(&rps->link, &dev_priv->rps.clients);
5096                         rps->boosts++;
5097                 } else
5098                         dev_priv->rps.boosts++;
5099         }
5100         spin_unlock(&dev_priv->rps.client_lock);
5101 }
5102
5103 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5104 {
5105         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5106                 valleyview_set_rps(dev_priv, val);
5107         else
5108                 gen6_set_rps(dev_priv, val);
5109 }
5110
5111 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5112 {
5113         I915_WRITE(GEN6_RC_CONTROL, 0);
5114         I915_WRITE(GEN9_PG_ENABLE, 0);
5115 }
5116
5117 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5118 {
5119         I915_WRITE(GEN6_RP_CONTROL, 0);
5120 }
5121
5122 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5123 {
5124         I915_WRITE(GEN6_RC_CONTROL, 0);
5125         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5126         I915_WRITE(GEN6_RP_CONTROL, 0);
5127 }
5128
5129 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5130 {
5131         I915_WRITE(GEN6_RC_CONTROL, 0);
5132 }
5133
5134 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5135 {
5136         /* we're doing forcewake before Disabling RC6,
5137          * This what the BIOS expects when going into suspend */
5138         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5139
5140         I915_WRITE(GEN6_RC_CONTROL, 0);
5141
5142         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5143 }
5144
5145 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5146 {
5147         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5148                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5149                         mode = GEN6_RC_CTL_RC6_ENABLE;
5150                 else
5151                         mode = 0;
5152         }
5153         if (HAS_RC6p(dev_priv))
5154                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5155                                  "RC6 %s RC6p %s RC6pp %s\n",
5156                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5157                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5158                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5159
5160         else
5161                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5162                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5163 }
5164
5165 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5166 {
5167         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5168         bool enable_rc6 = true;
5169         unsigned long rc6_ctx_base;
5170         u32 rc_ctl;
5171         int rc_sw_target;
5172
5173         rc_ctl = I915_READ(GEN6_RC_CONTROL);
5174         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5175                        RC_SW_TARGET_STATE_SHIFT;
5176         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5177                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5178                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5179                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5180                          rc_sw_target);
5181
5182         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5183                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5184                 enable_rc6 = false;
5185         }
5186
5187         /*
5188          * The exact context size is not known for BXT, so assume a page size
5189          * for this check.
5190          */
5191         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5192         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5193               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5194                                         ggtt->stolen_reserved_size))) {
5195                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5196                 enable_rc6 = false;
5197         }
5198
5199         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5200               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5201               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5202               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5203                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5204                 enable_rc6 = false;
5205         }
5206
5207         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5208             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5209             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5210                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5211                 enable_rc6 = false;
5212         }
5213
5214         if (!I915_READ(GEN6_GFXPAUSE)) {
5215                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5216                 enable_rc6 = false;
5217         }
5218
5219         if (!I915_READ(GEN8_MISC_CTRL0)) {
5220                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5221                 enable_rc6 = false;
5222         }
5223
5224         return enable_rc6;
5225 }
5226
5227 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5228 {
5229         /* No RC6 before Ironlake and code is gone for ilk. */
5230         if (INTEL_INFO(dev_priv)->gen < 6)
5231                 return 0;
5232
5233         if (!enable_rc6)
5234                 return 0;
5235
5236         if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5237                 DRM_INFO("RC6 disabled by BIOS\n");
5238                 return 0;
5239         }
5240
5241         /* Respect the kernel parameter if it is set */
5242         if (enable_rc6 >= 0) {
5243                 int mask;
5244
5245                 if (HAS_RC6p(dev_priv))
5246                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5247                                INTEL_RC6pp_ENABLE;
5248                 else
5249                         mask = INTEL_RC6_ENABLE;
5250
5251                 if ((enable_rc6 & mask) != enable_rc6)
5252                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5253                                          "(requested %d, valid %d)\n",
5254                                          enable_rc6 & mask, enable_rc6, mask);
5255
5256                 return enable_rc6 & mask;
5257         }
5258
5259         if (IS_IVYBRIDGE(dev_priv))
5260                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5261
5262         return INTEL_RC6_ENABLE;
5263 }
5264
5265 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5266 {
5267         /* All of these values are in units of 50MHz */
5268
5269         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5270         if (IS_BROXTON(dev_priv)) {
5271                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5272                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5273                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5274                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
5275         } else {
5276                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5277                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
5278                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5279                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5280         }
5281         /* hw_max = RP0 until we check for overclocking */
5282         dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5283
5284         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5285         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5286             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5287                 u32 ddcc_status = 0;
5288
5289                 if (sandybridge_pcode_read(dev_priv,
5290                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5291                                            &ddcc_status) == 0)
5292                         dev_priv->rps.efficient_freq =
5293                                 clamp_t(u8,
5294                                         ((ddcc_status >> 8) & 0xff),
5295                                         dev_priv->rps.min_freq,
5296                                         dev_priv->rps.max_freq);
5297         }
5298
5299         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5300                 /* Store the frequency values in 16.66 MHZ units, which is
5301                  * the natural hardware unit for SKL
5302                  */
5303                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5304                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5305                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5306                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5307                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5308         }
5309 }
5310
5311 static void reset_rps(struct drm_i915_private *dev_priv,
5312                       void (*set)(struct drm_i915_private *, u8))
5313 {
5314         u8 freq = dev_priv->rps.cur_freq;
5315
5316         /* force a reset */
5317         dev_priv->rps.power = -1;
5318         dev_priv->rps.cur_freq = -1;
5319
5320         set(dev_priv, freq);
5321 }
5322
5323 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5324 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5325 {
5326         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5327
5328         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5329         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5330                 /*
5331                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
5332                  * clear out the Control register just to avoid inconsitency
5333                  * with debugfs interface, which will show  Turbo as enabled
5334                  * only and that is not expected by the User after adding the
5335                  * WaGsvDisableTurbo. Apart from this there is no problem even
5336                  * if the Turbo is left enabled in the Control register, as the
5337                  * Up/Down interrupts would remain masked.
5338                  */
5339                 gen9_disable_rps(dev_priv);
5340                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5341                 return;
5342         }
5343
5344         /* Program defaults and thresholds for RPS*/
5345         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5346                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5347
5348         /* 1 second timeout*/
5349         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5350                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5351
5352         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5353
5354         /* Leaning on the below call to gen6_set_rps to program/setup the
5355          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5356          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5357         reset_rps(dev_priv, gen6_set_rps);
5358
5359         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5360 }
5361
5362 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5363 {
5364         struct intel_engine_cs *engine;
5365         enum intel_engine_id id;
5366         uint32_t rc6_mask = 0;
5367
5368         /* 1a: Software RC state - RC0 */
5369         I915_WRITE(GEN6_RC_STATE, 0);
5370
5371         /* 1b: Get forcewake during program sequence. Although the driver
5372          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5373         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5374
5375         /* 2a: Disable RC states. */
5376         I915_WRITE(GEN6_RC_CONTROL, 0);
5377
5378         /* 2b: Program RC6 thresholds.*/
5379
5380         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5381         if (IS_SKYLAKE(dev_priv))
5382                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5383         else
5384                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5385         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5386         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5387         for_each_engine(engine, dev_priv, id)
5388                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5389
5390         if (HAS_GUC(dev_priv))
5391                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5392
5393         I915_WRITE(GEN6_RC_SLEEP, 0);
5394
5395         /* 2c: Program Coarse Power Gating Policies. */
5396         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5397         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5398
5399         /* 3a: Enable RC6 */
5400         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5401                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5402         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5403         /* WaRsUseTimeoutMode:bxt */
5404         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5405                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5406                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5407                            GEN7_RC_CTL_TO_MODE |
5408                            rc6_mask);
5409         } else {
5410                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5411                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5412                            GEN6_RC_CTL_EI_MODE(1) |
5413                            rc6_mask);
5414         }
5415
5416         /*
5417          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5418          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5419          */
5420         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5421                 I915_WRITE(GEN9_PG_ENABLE, 0);
5422         else
5423                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5424                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5425
5426         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5427 }
5428
5429 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5430 {
5431         struct intel_engine_cs *engine;
5432         enum intel_engine_id id;
5433         uint32_t rc6_mask = 0;
5434
5435         /* 1a: Software RC state - RC0 */
5436         I915_WRITE(GEN6_RC_STATE, 0);
5437
5438         /* 1c & 1d: Get forcewake during program sequence. Although the driver
5439          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5440         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5441
5442         /* 2a: Disable RC states. */
5443         I915_WRITE(GEN6_RC_CONTROL, 0);
5444
5445         /* 2b: Program RC6 thresholds.*/
5446         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5447         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5448         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5449         for_each_engine(engine, dev_priv, id)
5450                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5451         I915_WRITE(GEN6_RC_SLEEP, 0);
5452         if (IS_BROADWELL(dev_priv))
5453                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5454         else
5455                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5456
5457         /* 3: Enable RC6 */
5458         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5459                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5460         intel_print_rc6_info(dev_priv, rc6_mask);
5461         if (IS_BROADWELL(dev_priv))
5462                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5463                                 GEN7_RC_CTL_TO_MODE |
5464                                 rc6_mask);
5465         else
5466                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5467                                 GEN6_RC_CTL_EI_MODE(1) |
5468                                 rc6_mask);
5469
5470         /* 4 Program defaults and thresholds for RPS*/
5471         I915_WRITE(GEN6_RPNSWREQ,
5472                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5473         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5474                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5475         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5476         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5477
5478         /* Docs recommend 900MHz, and 300 MHz respectively */
5479         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5480                    dev_priv->rps.max_freq_softlimit << 24 |
5481                    dev_priv->rps.min_freq_softlimit << 16);
5482
5483         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5484         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5485         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5486         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5487
5488         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5489
5490         /* 5: Enable RPS */
5491         I915_WRITE(GEN6_RP_CONTROL,
5492                    GEN6_RP_MEDIA_TURBO |
5493                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5494                    GEN6_RP_MEDIA_IS_GFX |
5495                    GEN6_RP_ENABLE |
5496                    GEN6_RP_UP_BUSY_AVG |
5497                    GEN6_RP_DOWN_IDLE_AVG);
5498
5499         /* 6: Ring frequency + overclocking (our driver does this later */
5500
5501         reset_rps(dev_priv, gen6_set_rps);
5502
5503         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5504 }
5505
5506 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5507 {
5508         struct intel_engine_cs *engine;
5509         enum intel_engine_id id;
5510         u32 rc6vids, rc6_mask = 0;
5511         u32 gtfifodbg;
5512         int rc6_mode;
5513         int ret;
5514
5515         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5516
5517         /* Here begins a magic sequence of register writes to enable
5518          * auto-downclocking.
5519          *
5520          * Perhaps there might be some value in exposing these to
5521          * userspace...
5522          */
5523         I915_WRITE(GEN6_RC_STATE, 0);
5524
5525         /* Clear the DBG now so we don't confuse earlier errors */
5526         gtfifodbg = I915_READ(GTFIFODBG);
5527         if (gtfifodbg) {
5528                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5529                 I915_WRITE(GTFIFODBG, gtfifodbg);
5530         }
5531
5532         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5533
5534         /* disable the counters and set deterministic thresholds */
5535         I915_WRITE(GEN6_RC_CONTROL, 0);
5536
5537         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5538         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5539         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5540         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5541         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5542
5543         for_each_engine(engine, dev_priv, id)
5544                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5545
5546         I915_WRITE(GEN6_RC_SLEEP, 0);
5547         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5548         if (IS_IVYBRIDGE(dev_priv))
5549                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5550         else
5551                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5552         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5553         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5554
5555         /* Check if we are enabling RC6 */
5556         rc6_mode = intel_enable_rc6();
5557         if (rc6_mode & INTEL_RC6_ENABLE)
5558                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5559
5560         /* We don't use those on Haswell */
5561         if (!IS_HASWELL(dev_priv)) {
5562                 if (rc6_mode & INTEL_RC6p_ENABLE)
5563                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5564
5565                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5566                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5567         }
5568
5569         intel_print_rc6_info(dev_priv, rc6_mask);
5570
5571         I915_WRITE(GEN6_RC_CONTROL,
5572                    rc6_mask |
5573                    GEN6_RC_CTL_EI_MODE(1) |
5574                    GEN6_RC_CTL_HW_ENABLE);
5575
5576         /* Power down if completely idle for over 50ms */
5577         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5578         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5579
5580         reset_rps(dev_priv, gen6_set_rps);
5581
5582         rc6vids = 0;
5583         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5584         if (IS_GEN6(dev_priv) && ret) {
5585                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5586         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5587                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5588                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5589                 rc6vids &= 0xffff00;
5590                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5591                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5592                 if (ret)
5593                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5594         }
5595
5596         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5597 }
5598
5599 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5600 {
5601         int min_freq = 15;
5602         unsigned int gpu_freq;
5603         unsigned int max_ia_freq, min_ring_freq;
5604         unsigned int max_gpu_freq, min_gpu_freq;
5605         int scaling_factor = 180;
5606         struct cpufreq_policy *policy;
5607
5608         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5609
5610         policy = cpufreq_cpu_get(0);
5611         if (policy) {
5612                 max_ia_freq = policy->cpuinfo.max_freq;
5613                 cpufreq_cpu_put(policy);
5614         } else {
5615                 /*
5616                  * Default to measured freq if none found, PCU will ensure we
5617                  * don't go over
5618                  */
5619                 max_ia_freq = tsc_khz;
5620         }
5621
5622         /* Convert from kHz to MHz */
5623         max_ia_freq /= 1000;
5624
5625         min_ring_freq = I915_READ(DCLK) & 0xf;
5626         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5627         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5628
5629         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5630                 /* Convert GT frequency to 50 HZ units */
5631                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5632                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5633         } else {
5634                 min_gpu_freq = dev_priv->rps.min_freq;
5635                 max_gpu_freq = dev_priv->rps.max_freq;
5636         }
5637
5638         /*
5639          * For each potential GPU frequency, load a ring frequency we'd like
5640          * to use for memory access.  We do this by specifying the IA frequency
5641          * the PCU should use as a reference to determine the ring frequency.
5642          */
5643         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5644                 int diff = max_gpu_freq - gpu_freq;
5645                 unsigned int ia_freq = 0, ring_freq = 0;
5646
5647                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5648                         /*
5649                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5650                          * No floor required for ring frequency on SKL.
5651                          */
5652                         ring_freq = gpu_freq;
5653                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5654                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5655                         ring_freq = max(min_ring_freq, gpu_freq);
5656                 } else if (IS_HASWELL(dev_priv)) {
5657                         ring_freq = mult_frac(gpu_freq, 5, 4);
5658                         ring_freq = max(min_ring_freq, ring_freq);
5659                         /* leave ia_freq as the default, chosen by cpufreq */
5660                 } else {
5661                         /* On older processors, there is no separate ring
5662                          * clock domain, so in order to boost the bandwidth
5663                          * of the ring, we need to upclock the CPU (ia_freq).
5664                          *
5665                          * For GPU frequencies less than 750MHz,
5666                          * just use the lowest ring freq.
5667                          */
5668                         if (gpu_freq < min_freq)
5669                                 ia_freq = 800;
5670                         else
5671                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5672                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5673                 }
5674
5675                 sandybridge_pcode_write(dev_priv,
5676                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5677                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5678                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5679                                         gpu_freq);
5680         }
5681 }
5682
5683 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5684 {
5685         u32 val, rp0;
5686
5687         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5688
5689         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5690         case 8:
5691                 /* (2 * 4) config */
5692                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5693                 break;
5694         case 12:
5695                 /* (2 * 6) config */
5696                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5697                 break;
5698         case 16:
5699                 /* (2 * 8) config */
5700         default:
5701                 /* Setting (2 * 8) Min RP0 for any other combination */
5702                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5703                 break;
5704         }
5705
5706         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5707
5708         return rp0;
5709 }
5710
5711 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5712 {
5713         u32 val, rpe;
5714
5715         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5716         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5717
5718         return rpe;
5719 }
5720
5721 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5722 {
5723         u32 val, rp1;
5724
5725         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5726         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5727
5728         return rp1;
5729 }
5730
5731 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5732 {
5733         u32 val, rp1;
5734
5735         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5736
5737         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5738
5739         return rp1;
5740 }
5741
5742 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5743 {
5744         u32 val, rp0;
5745
5746         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5747
5748         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5749         /* Clamp to max */
5750         rp0 = min_t(u32, rp0, 0xea);
5751
5752         return rp0;
5753 }
5754
5755 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5756 {
5757         u32 val, rpe;
5758
5759         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5760         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5761         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5762         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5763
5764         return rpe;
5765 }
5766
5767 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5768 {
5769         u32 val;
5770
5771         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5772         /*
5773          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5774          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5775          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5776          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5777          * to make sure it matches what Punit accepts.
5778          */
5779         return max_t(u32, val, 0xc0);
5780 }
5781
5782 /* Check that the pctx buffer wasn't move under us. */
5783 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5784 {
5785         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5786
5787         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5788                              dev_priv->vlv_pctx->stolen->start);
5789 }
5790
5791
5792 /* Check that the pcbr address is not empty. */
5793 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5794 {
5795         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5796
5797         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5798 }
5799
5800 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5801 {
5802         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5803         unsigned long pctx_paddr, paddr;
5804         u32 pcbr;
5805         int pctx_size = 32*1024;
5806
5807         pcbr = I915_READ(VLV_PCBR);
5808         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5809                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5810                 paddr = (dev_priv->mm.stolen_base +
5811                          (ggtt->stolen_size - pctx_size));
5812
5813                 pctx_paddr = (paddr & (~4095));
5814                 I915_WRITE(VLV_PCBR, pctx_paddr);
5815         }
5816
5817         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5818 }
5819
5820 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5821 {
5822         struct drm_i915_gem_object *pctx;
5823         unsigned long pctx_paddr;
5824         u32 pcbr;
5825         int pctx_size = 24*1024;
5826
5827         pcbr = I915_READ(VLV_PCBR);
5828         if (pcbr) {
5829                 /* BIOS set it up already, grab the pre-alloc'd space */
5830                 int pcbr_offset;
5831
5832                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5833                 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
5834                                                                       pcbr_offset,
5835                                                                       I915_GTT_OFFSET_NONE,
5836                                                                       pctx_size);
5837                 goto out;
5838         }
5839
5840         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5841
5842         /*
5843          * From the Gunit register HAS:
5844          * The Gfx driver is expected to program this register and ensure
5845          * proper allocation within Gfx stolen memory.  For example, this
5846          * register should be programmed such than the PCBR range does not
5847          * overlap with other ranges, such as the frame buffer, protected
5848          * memory, or any other relevant ranges.
5849          */
5850         pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
5851         if (!pctx) {
5852                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5853                 goto out;
5854         }
5855
5856         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5857         I915_WRITE(VLV_PCBR, pctx_paddr);
5858
5859 out:
5860         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5861         dev_priv->vlv_pctx = pctx;
5862 }
5863
5864 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5865 {
5866         if (WARN_ON(!dev_priv->vlv_pctx))
5867                 return;
5868
5869         i915_gem_object_put(dev_priv->vlv_pctx);
5870         dev_priv->vlv_pctx = NULL;
5871 }
5872
5873 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5874 {
5875         dev_priv->rps.gpll_ref_freq =
5876                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5877                                   CCK_GPLL_CLOCK_CONTROL,
5878                                   dev_priv->czclk_freq);
5879
5880         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5881                          dev_priv->rps.gpll_ref_freq);
5882 }
5883
5884 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5885 {
5886         u32 val;
5887
5888         valleyview_setup_pctx(dev_priv);
5889
5890         vlv_init_gpll_ref_freq(dev_priv);
5891
5892         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5893         switch ((val >> 6) & 3) {
5894         case 0:
5895         case 1:
5896                 dev_priv->mem_freq = 800;
5897                 break;
5898         case 2:
5899                 dev_priv->mem_freq = 1066;
5900                 break;
5901         case 3:
5902                 dev_priv->mem_freq = 1333;
5903                 break;
5904         }
5905         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5906
5907         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5908         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5909         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5910                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5911                          dev_priv->rps.max_freq);
5912
5913         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5914         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5915                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5916                          dev_priv->rps.efficient_freq);
5917
5918         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5919         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5920                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5921                          dev_priv->rps.rp1_freq);
5922
5923         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5924         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5925                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5926                          dev_priv->rps.min_freq);
5927 }
5928
5929 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5930 {
5931         u32 val;
5932
5933         cherryview_setup_pctx(dev_priv);
5934
5935         vlv_init_gpll_ref_freq(dev_priv);
5936
5937         mutex_lock(&dev_priv->sb_lock);
5938         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5939         mutex_unlock(&dev_priv->sb_lock);
5940
5941         switch ((val >> 2) & 0x7) {
5942         case 3:
5943                 dev_priv->mem_freq = 2000;
5944                 break;
5945         default:
5946                 dev_priv->mem_freq = 1600;
5947                 break;
5948         }
5949         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5950
5951         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5952         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5953         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5954                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5955                          dev_priv->rps.max_freq);
5956
5957         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5958         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5959                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5960                          dev_priv->rps.efficient_freq);
5961
5962         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5963         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5964                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5965                          dev_priv->rps.rp1_freq);
5966
5967         /* PUnit validated range is only [RPe, RP0] */
5968         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5969         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5970                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5971                          dev_priv->rps.min_freq);
5972
5973         WARN_ONCE((dev_priv->rps.max_freq |
5974                    dev_priv->rps.efficient_freq |
5975                    dev_priv->rps.rp1_freq |
5976                    dev_priv->rps.min_freq) & 1,
5977                   "Odd GPU freq values\n");
5978 }
5979
5980 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5981 {
5982         valleyview_cleanup_pctx(dev_priv);
5983 }
5984
5985 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5986 {
5987         struct intel_engine_cs *engine;
5988         enum intel_engine_id id;
5989         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5990
5991         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5992
5993         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5994                                              GT_FIFO_FREE_ENTRIES_CHV);
5995         if (gtfifodbg) {
5996                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5997                                  gtfifodbg);
5998                 I915_WRITE(GTFIFODBG, gtfifodbg);
5999         }
6000
6001         cherryview_check_pctx(dev_priv);
6002
6003         /* 1a & 1b: Get forcewake during program sequence. Although the driver
6004          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6005         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6006
6007         /*  Disable RC states. */
6008         I915_WRITE(GEN6_RC_CONTROL, 0);
6009
6010         /* 2a: Program RC6 thresholds.*/
6011         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6012         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6013         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6014
6015         for_each_engine(engine, dev_priv, id)
6016                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6017         I915_WRITE(GEN6_RC_SLEEP, 0);
6018
6019         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6020         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6021
6022         /* allows RC6 residency counter to work */
6023         I915_WRITE(VLV_COUNTER_CONTROL,
6024                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6025                                       VLV_MEDIA_RC6_COUNT_EN |
6026                                       VLV_RENDER_RC6_COUNT_EN));
6027
6028         /* For now we assume BIOS is allocating and populating the PCBR  */
6029         pcbr = I915_READ(VLV_PCBR);
6030
6031         /* 3: Enable RC6 */
6032         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6033             (pcbr >> VLV_PCBR_ADDR_SHIFT))
6034                 rc6_mode = GEN7_RC_CTL_TO_MODE;
6035
6036         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6037
6038         /* 4 Program defaults and thresholds for RPS*/
6039         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6040         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6041         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6042         I915_WRITE(GEN6_RP_UP_EI, 66000);
6043         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6044
6045         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6046
6047         /* 5: Enable RPS */
6048         I915_WRITE(GEN6_RP_CONTROL,
6049                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6050                    GEN6_RP_MEDIA_IS_GFX |
6051                    GEN6_RP_ENABLE |
6052                    GEN6_RP_UP_BUSY_AVG |
6053                    GEN6_RP_DOWN_IDLE_AVG);
6054
6055         /* Setting Fixed Bias */
6056         val = VLV_OVERRIDE_EN |
6057                   VLV_SOC_TDP_EN |
6058                   CHV_BIAS_CPU_50_SOC_50;
6059         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6060
6061         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6062
6063         /* RPS code assumes GPLL is used */
6064         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6065
6066         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6067         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6068
6069         reset_rps(dev_priv, valleyview_set_rps);
6070
6071         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6072 }
6073
6074 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6075 {
6076         struct intel_engine_cs *engine;
6077         enum intel_engine_id id;
6078         u32 gtfifodbg, val, rc6_mode = 0;
6079
6080         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6081
6082         valleyview_check_pctx(dev_priv);
6083
6084         gtfifodbg = I915_READ(GTFIFODBG);
6085         if (gtfifodbg) {
6086                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6087                                  gtfifodbg);
6088                 I915_WRITE(GTFIFODBG, gtfifodbg);
6089         }
6090
6091         /* If VLV, Forcewake all wells, else re-direct to regular path */
6092         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6093
6094         /*  Disable RC states. */
6095         I915_WRITE(GEN6_RC_CONTROL, 0);
6096
6097         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6098         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6099         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6100         I915_WRITE(GEN6_RP_UP_EI, 66000);
6101         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6102
6103         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6104
6105         I915_WRITE(GEN6_RP_CONTROL,
6106                    GEN6_RP_MEDIA_TURBO |
6107                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6108                    GEN6_RP_MEDIA_IS_GFX |
6109                    GEN6_RP_ENABLE |
6110                    GEN6_RP_UP_BUSY_AVG |
6111                    GEN6_RP_DOWN_IDLE_CONT);
6112
6113         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6114         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6115         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6116
6117         for_each_engine(engine, dev_priv, id)
6118                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6119
6120         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6121
6122         /* allows RC6 residency counter to work */
6123         I915_WRITE(VLV_COUNTER_CONTROL,
6124                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6125                                       VLV_RENDER_RC0_COUNT_EN |
6126                                       VLV_MEDIA_RC6_COUNT_EN |
6127                                       VLV_RENDER_RC6_COUNT_EN));
6128
6129         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6130                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6131
6132         intel_print_rc6_info(dev_priv, rc6_mode);
6133
6134         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6135
6136         /* Setting Fixed Bias */
6137         val = VLV_OVERRIDE_EN |
6138                   VLV_SOC_TDP_EN |
6139                   VLV_BIAS_CPU_125_SOC_875;
6140         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6141
6142         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6143
6144         /* RPS code assumes GPLL is used */
6145         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6146
6147         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6148         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6149
6150         reset_rps(dev_priv, valleyview_set_rps);
6151
6152         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6153 }
6154
6155 static unsigned long intel_pxfreq(u32 vidfreq)
6156 {
6157         unsigned long freq;
6158         int div = (vidfreq & 0x3f0000) >> 16;
6159         int post = (vidfreq & 0x3000) >> 12;
6160         int pre = (vidfreq & 0x7);
6161
6162         if (!pre)
6163                 return 0;
6164
6165         freq = ((div * 133333) / ((1<<post) * pre));
6166
6167         return freq;
6168 }
6169
6170 static const struct cparams {
6171         u16 i;
6172         u16 t;
6173         u16 m;
6174         u16 c;
6175 } cparams[] = {
6176         { 1, 1333, 301, 28664 },
6177         { 1, 1066, 294, 24460 },
6178         { 1, 800, 294, 25192 },
6179         { 0, 1333, 276, 27605 },
6180         { 0, 1066, 276, 27605 },
6181         { 0, 800, 231, 23784 },
6182 };
6183
6184 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6185 {
6186         u64 total_count, diff, ret;
6187         u32 count1, count2, count3, m = 0, c = 0;
6188         unsigned long now = jiffies_to_msecs(jiffies), diff1;
6189         int i;
6190
6191         assert_spin_locked(&mchdev_lock);
6192
6193         diff1 = now - dev_priv->ips.last_time1;
6194
6195         /* Prevent division-by-zero if we are asking too fast.
6196          * Also, we don't get interesting results if we are polling
6197          * faster than once in 10ms, so just return the saved value
6198          * in such cases.
6199          */
6200         if (diff1 <= 10)
6201                 return dev_priv->ips.chipset_power;
6202
6203         count1 = I915_READ(DMIEC);
6204         count2 = I915_READ(DDREC);
6205         count3 = I915_READ(CSIEC);
6206
6207         total_count = count1 + count2 + count3;
6208
6209         /* FIXME: handle per-counter overflow */
6210         if (total_count < dev_priv->ips.last_count1) {
6211                 diff = ~0UL - dev_priv->ips.last_count1;
6212                 diff += total_count;
6213         } else {
6214                 diff = total_count - dev_priv->ips.last_count1;
6215         }
6216
6217         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6218                 if (cparams[i].i == dev_priv->ips.c_m &&
6219                     cparams[i].t == dev_priv->ips.r_t) {
6220                         m = cparams[i].m;
6221                         c = cparams[i].c;
6222                         break;
6223                 }
6224         }
6225
6226         diff = div_u64(diff, diff1);
6227         ret = ((m * diff) + c);
6228         ret = div_u64(ret, 10);
6229
6230         dev_priv->ips.last_count1 = total_count;
6231         dev_priv->ips.last_time1 = now;
6232
6233         dev_priv->ips.chipset_power = ret;
6234
6235         return ret;
6236 }
6237
6238 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6239 {
6240         unsigned long val;
6241
6242         if (INTEL_INFO(dev_priv)->gen != 5)
6243                 return 0;
6244
6245         spin_lock_irq(&mchdev_lock);
6246
6247         val = __i915_chipset_val(dev_priv);
6248
6249         spin_unlock_irq(&mchdev_lock);
6250
6251         return val;
6252 }
6253
6254 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6255 {
6256         unsigned long m, x, b;
6257         u32 tsfs;
6258
6259         tsfs = I915_READ(TSFS);
6260
6261         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6262         x = I915_READ8(TR1);
6263
6264         b = tsfs & TSFS_INTR_MASK;
6265
6266         return ((m * x) / 127) - b;
6267 }
6268
6269 static int _pxvid_to_vd(u8 pxvid)
6270 {
6271         if (pxvid == 0)
6272                 return 0;
6273
6274         if (pxvid >= 8 && pxvid < 31)
6275                 pxvid = 31;
6276
6277         return (pxvid + 2) * 125;
6278 }
6279
6280 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6281 {
6282         const int vd = _pxvid_to_vd(pxvid);
6283         const int vm = vd - 1125;
6284
6285         if (INTEL_INFO(dev_priv)->is_mobile)
6286                 return vm > 0 ? vm : 0;
6287
6288         return vd;
6289 }
6290
6291 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6292 {
6293         u64 now, diff, diffms;
6294         u32 count;
6295
6296         assert_spin_locked(&mchdev_lock);
6297
6298         now = ktime_get_raw_ns();
6299         diffms = now - dev_priv->ips.last_time2;
6300         do_div(diffms, NSEC_PER_MSEC);
6301
6302         /* Don't divide by 0 */
6303         if (!diffms)
6304                 return;
6305
6306         count = I915_READ(GFXEC);
6307
6308         if (count < dev_priv->ips.last_count2) {
6309                 diff = ~0UL - dev_priv->ips.last_count2;
6310                 diff += count;
6311         } else {
6312                 diff = count - dev_priv->ips.last_count2;
6313         }
6314
6315         dev_priv->ips.last_count2 = count;
6316         dev_priv->ips.last_time2 = now;
6317
6318         /* More magic constants... */
6319         diff = diff * 1181;
6320         diff = div_u64(diff, diffms * 10);
6321         dev_priv->ips.gfx_power = diff;
6322 }
6323
6324 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6325 {
6326         if (INTEL_INFO(dev_priv)->gen != 5)
6327                 return;
6328
6329         spin_lock_irq(&mchdev_lock);
6330
6331         __i915_update_gfx_val(dev_priv);
6332
6333         spin_unlock_irq(&mchdev_lock);
6334 }
6335
6336 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6337 {
6338         unsigned long t, corr, state1, corr2, state2;
6339         u32 pxvid, ext_v;
6340
6341         assert_spin_locked(&mchdev_lock);
6342
6343         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6344         pxvid = (pxvid >> 24) & 0x7f;
6345         ext_v = pvid_to_extvid(dev_priv, pxvid);
6346
6347         state1 = ext_v;
6348
6349         t = i915_mch_val(dev_priv);
6350
6351         /* Revel in the empirically derived constants */
6352
6353         /* Correction factor in 1/100000 units */
6354         if (t > 80)
6355                 corr = ((t * 2349) + 135940);
6356         else if (t >= 50)
6357                 corr = ((t * 964) + 29317);
6358         else /* < 50 */
6359                 corr = ((t * 301) + 1004);
6360
6361         corr = corr * ((150142 * state1) / 10000 - 78642);
6362         corr /= 100000;
6363         corr2 = (corr * dev_priv->ips.corr);
6364
6365         state2 = (corr2 * state1) / 10000;
6366         state2 /= 100; /* convert to mW */
6367
6368         __i915_update_gfx_val(dev_priv);
6369
6370         return dev_priv->ips.gfx_power + state2;
6371 }
6372
6373 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6374 {
6375         unsigned long val;
6376
6377         if (INTEL_INFO(dev_priv)->gen != 5)
6378                 return 0;
6379
6380         spin_lock_irq(&mchdev_lock);
6381
6382         val = __i915_gfx_val(dev_priv);
6383
6384         spin_unlock_irq(&mchdev_lock);
6385
6386         return val;
6387 }
6388
6389 /**
6390  * i915_read_mch_val - return value for IPS use
6391  *
6392  * Calculate and return a value for the IPS driver to use when deciding whether
6393  * we have thermal and power headroom to increase CPU or GPU power budget.
6394  */
6395 unsigned long i915_read_mch_val(void)
6396 {
6397         struct drm_i915_private *dev_priv;
6398         unsigned long chipset_val, graphics_val, ret = 0;
6399
6400         spin_lock_irq(&mchdev_lock);
6401         if (!i915_mch_dev)
6402                 goto out_unlock;
6403         dev_priv = i915_mch_dev;
6404
6405         chipset_val = __i915_chipset_val(dev_priv);
6406         graphics_val = __i915_gfx_val(dev_priv);
6407
6408         ret = chipset_val + graphics_val;
6409
6410 out_unlock:
6411         spin_unlock_irq(&mchdev_lock);
6412
6413         return ret;
6414 }
6415 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6416
6417 /**
6418  * i915_gpu_raise - raise GPU frequency limit
6419  *
6420  * Raise the limit; IPS indicates we have thermal headroom.
6421  */
6422 bool i915_gpu_raise(void)
6423 {
6424         struct drm_i915_private *dev_priv;
6425         bool ret = true;
6426
6427         spin_lock_irq(&mchdev_lock);
6428         if (!i915_mch_dev) {
6429                 ret = false;
6430                 goto out_unlock;
6431         }
6432         dev_priv = i915_mch_dev;
6433
6434         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6435                 dev_priv->ips.max_delay--;
6436
6437 out_unlock:
6438         spin_unlock_irq(&mchdev_lock);
6439
6440         return ret;
6441 }
6442 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6443
6444 /**
6445  * i915_gpu_lower - lower GPU frequency limit
6446  *
6447  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6448  * frequency maximum.
6449  */
6450 bool i915_gpu_lower(void)
6451 {
6452         struct drm_i915_private *dev_priv;
6453         bool ret = true;
6454
6455         spin_lock_irq(&mchdev_lock);
6456         if (!i915_mch_dev) {
6457                 ret = false;
6458                 goto out_unlock;
6459         }
6460         dev_priv = i915_mch_dev;
6461
6462         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6463                 dev_priv->ips.max_delay++;
6464
6465 out_unlock:
6466         spin_unlock_irq(&mchdev_lock);
6467
6468         return ret;
6469 }
6470 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6471
6472 /**
6473  * i915_gpu_busy - indicate GPU business to IPS
6474  *
6475  * Tell the IPS driver whether or not the GPU is busy.
6476  */
6477 bool i915_gpu_busy(void)
6478 {
6479         bool ret = false;
6480
6481         spin_lock_irq(&mchdev_lock);
6482         if (i915_mch_dev)
6483                 ret = i915_mch_dev->gt.awake;
6484         spin_unlock_irq(&mchdev_lock);
6485
6486         return ret;
6487 }
6488 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6489
6490 /**
6491  * i915_gpu_turbo_disable - disable graphics turbo
6492  *
6493  * Disable graphics turbo by resetting the max frequency and setting the
6494  * current frequency to the default.
6495  */
6496 bool i915_gpu_turbo_disable(void)
6497 {
6498         struct drm_i915_private *dev_priv;
6499         bool ret = true;
6500
6501         spin_lock_irq(&mchdev_lock);
6502         if (!i915_mch_dev) {
6503                 ret = false;
6504                 goto out_unlock;
6505         }
6506         dev_priv = i915_mch_dev;
6507
6508         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6509
6510         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6511                 ret = false;
6512
6513 out_unlock:
6514         spin_unlock_irq(&mchdev_lock);
6515
6516         return ret;
6517 }
6518 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6519
6520 /**
6521  * Tells the intel_ips driver that the i915 driver is now loaded, if
6522  * IPS got loaded first.
6523  *
6524  * This awkward dance is so that neither module has to depend on the
6525  * other in order for IPS to do the appropriate communication of
6526  * GPU turbo limits to i915.
6527  */
6528 static void
6529 ips_ping_for_i915_load(void)
6530 {
6531         void (*link)(void);
6532
6533         link = symbol_get(ips_link_to_i915_driver);
6534         if (link) {
6535                 link();
6536                 symbol_put(ips_link_to_i915_driver);
6537         }
6538 }
6539
6540 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6541 {
6542         /* We only register the i915 ips part with intel-ips once everything is
6543          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6544         spin_lock_irq(&mchdev_lock);
6545         i915_mch_dev = dev_priv;
6546         spin_unlock_irq(&mchdev_lock);
6547
6548         ips_ping_for_i915_load();
6549 }
6550
6551 void intel_gpu_ips_teardown(void)
6552 {
6553         spin_lock_irq(&mchdev_lock);
6554         i915_mch_dev = NULL;
6555         spin_unlock_irq(&mchdev_lock);
6556 }
6557
6558 static void intel_init_emon(struct drm_i915_private *dev_priv)
6559 {
6560         u32 lcfuse;
6561         u8 pxw[16];
6562         int i;
6563
6564         /* Disable to program */
6565         I915_WRITE(ECR, 0);
6566         POSTING_READ(ECR);
6567
6568         /* Program energy weights for various events */
6569         I915_WRITE(SDEW, 0x15040d00);
6570         I915_WRITE(CSIEW0, 0x007f0000);
6571         I915_WRITE(CSIEW1, 0x1e220004);
6572         I915_WRITE(CSIEW2, 0x04000004);
6573
6574         for (i = 0; i < 5; i++)
6575                 I915_WRITE(PEW(i), 0);
6576         for (i = 0; i < 3; i++)
6577                 I915_WRITE(DEW(i), 0);
6578
6579         /* Program P-state weights to account for frequency power adjustment */
6580         for (i = 0; i < 16; i++) {
6581                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6582                 unsigned long freq = intel_pxfreq(pxvidfreq);
6583                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6584                         PXVFREQ_PX_SHIFT;
6585                 unsigned long val;
6586
6587                 val = vid * vid;
6588                 val *= (freq / 1000);
6589                 val *= 255;
6590                 val /= (127*127*900);
6591                 if (val > 0xff)
6592                         DRM_ERROR("bad pxval: %ld\n", val);
6593                 pxw[i] = val;
6594         }
6595         /* Render standby states get 0 weight */
6596         pxw[14] = 0;
6597         pxw[15] = 0;
6598
6599         for (i = 0; i < 4; i++) {
6600                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6601                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6602                 I915_WRITE(PXW(i), val);
6603         }
6604
6605         /* Adjust magic regs to magic values (more experimental results) */
6606         I915_WRITE(OGW0, 0);
6607         I915_WRITE(OGW1, 0);
6608         I915_WRITE(EG0, 0x00007f00);
6609         I915_WRITE(EG1, 0x0000000e);
6610         I915_WRITE(EG2, 0x000e0000);
6611         I915_WRITE(EG3, 0x68000300);
6612         I915_WRITE(EG4, 0x42000000);
6613         I915_WRITE(EG5, 0x00140031);
6614         I915_WRITE(EG6, 0);
6615         I915_WRITE(EG7, 0);
6616
6617         for (i = 0; i < 8; i++)
6618                 I915_WRITE(PXWL(i), 0);
6619
6620         /* Enable PMON + select events */
6621         I915_WRITE(ECR, 0x80000019);
6622
6623         lcfuse = I915_READ(LCFUSE02);
6624
6625         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6626 }
6627
6628 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6629 {
6630         /*
6631          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6632          * requirement.
6633          */
6634         if (!i915.enable_rc6) {
6635                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6636                 intel_runtime_pm_get(dev_priv);
6637         }
6638
6639         mutex_lock(&dev_priv->drm.struct_mutex);
6640         mutex_lock(&dev_priv->rps.hw_lock);
6641
6642         /* Initialize RPS limits (for userspace) */
6643         if (IS_CHERRYVIEW(dev_priv))
6644                 cherryview_init_gt_powersave(dev_priv);
6645         else if (IS_VALLEYVIEW(dev_priv))
6646                 valleyview_init_gt_powersave(dev_priv);
6647         else if (INTEL_GEN(dev_priv) >= 6)
6648                 gen6_init_rps_frequencies(dev_priv);
6649
6650         /* Derive initial user preferences/limits from the hardware limits */
6651         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6652         dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6653
6654         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6655         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6656
6657         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6658                 dev_priv->rps.min_freq_softlimit =
6659                         max_t(int,
6660                               dev_priv->rps.efficient_freq,
6661                               intel_freq_opcode(dev_priv, 450));
6662
6663         /* After setting max-softlimit, find the overclock max freq */
6664         if (IS_GEN6(dev_priv) ||
6665             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6666                 u32 params = 0;
6667
6668                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6669                 if (params & BIT(31)) { /* OC supported */
6670                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6671                                          (dev_priv->rps.max_freq & 0xff) * 50,
6672                                          (params & 0xff) * 50);
6673                         dev_priv->rps.max_freq = params & 0xff;
6674                 }
6675         }
6676
6677         /* Finally allow us to boost to max by default */
6678         dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6679
6680         mutex_unlock(&dev_priv->rps.hw_lock);
6681         mutex_unlock(&dev_priv->drm.struct_mutex);
6682
6683         intel_autoenable_gt_powersave(dev_priv);
6684 }
6685
6686 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6687 {
6688         if (IS_VALLEYVIEW(dev_priv))
6689                 valleyview_cleanup_gt_powersave(dev_priv);
6690
6691         if (!i915.enable_rc6)
6692                 intel_runtime_pm_put(dev_priv);
6693 }
6694
6695 /**
6696  * intel_suspend_gt_powersave - suspend PM work and helper threads
6697  * @dev_priv: i915 device
6698  *
6699  * We don't want to disable RC6 or other features here, we just want
6700  * to make sure any work we've queued has finished and won't bother
6701  * us while we're suspended.
6702  */
6703 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6704 {
6705         if (INTEL_GEN(dev_priv) < 6)
6706                 return;
6707
6708         if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6709                 intel_runtime_pm_put(dev_priv);
6710
6711         /* gen6_rps_idle() will be called later to disable interrupts */
6712 }
6713
6714 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6715 {
6716         dev_priv->rps.enabled = true; /* force disabling */
6717         intel_disable_gt_powersave(dev_priv);
6718
6719         gen6_reset_rps_interrupts(dev_priv);
6720 }
6721
6722 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6723 {
6724         if (!READ_ONCE(dev_priv->rps.enabled))
6725                 return;
6726
6727         mutex_lock(&dev_priv->rps.hw_lock);
6728
6729         if (INTEL_GEN(dev_priv) >= 9) {
6730                 gen9_disable_rc6(dev_priv);
6731                 gen9_disable_rps(dev_priv);
6732         } else if (IS_CHERRYVIEW(dev_priv)) {
6733                 cherryview_disable_rps(dev_priv);
6734         } else if (IS_VALLEYVIEW(dev_priv)) {
6735                 valleyview_disable_rps(dev_priv);
6736         } else if (INTEL_GEN(dev_priv) >= 6) {
6737                 gen6_disable_rps(dev_priv);
6738         }  else if (IS_IRONLAKE_M(dev_priv)) {
6739                 ironlake_disable_drps(dev_priv);
6740         }
6741
6742         dev_priv->rps.enabled = false;
6743         mutex_unlock(&dev_priv->rps.hw_lock);
6744 }
6745
6746 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6747 {
6748         /* We shouldn't be disabling as we submit, so this should be less
6749          * racy than it appears!
6750          */
6751         if (READ_ONCE(dev_priv->rps.enabled))
6752                 return;
6753
6754         /* Powersaving is controlled by the host when inside a VM */
6755         if (intel_vgpu_active(dev_priv))
6756                 return;
6757
6758         mutex_lock(&dev_priv->rps.hw_lock);
6759
6760         if (IS_CHERRYVIEW(dev_priv)) {
6761                 cherryview_enable_rps(dev_priv);
6762         } else if (IS_VALLEYVIEW(dev_priv)) {
6763                 valleyview_enable_rps(dev_priv);
6764         } else if (INTEL_GEN(dev_priv) >= 9) {
6765                 gen9_enable_rc6(dev_priv);
6766                 gen9_enable_rps(dev_priv);
6767                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6768                         gen6_update_ring_freq(dev_priv);
6769         } else if (IS_BROADWELL(dev_priv)) {
6770                 gen8_enable_rps(dev_priv);
6771                 gen6_update_ring_freq(dev_priv);
6772         } else if (INTEL_GEN(dev_priv) >= 6) {
6773                 gen6_enable_rps(dev_priv);
6774                 gen6_update_ring_freq(dev_priv);
6775         } else if (IS_IRONLAKE_M(dev_priv)) {
6776                 ironlake_enable_drps(dev_priv);
6777                 intel_init_emon(dev_priv);
6778         }
6779
6780         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6781         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6782
6783         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6784         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6785
6786         dev_priv->rps.enabled = true;
6787         mutex_unlock(&dev_priv->rps.hw_lock);
6788 }
6789
6790 static void __intel_autoenable_gt_powersave(struct work_struct *work)
6791 {
6792         struct drm_i915_private *dev_priv =
6793                 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6794         struct intel_engine_cs *rcs;
6795         struct drm_i915_gem_request *req;
6796
6797         if (READ_ONCE(dev_priv->rps.enabled))
6798                 goto out;
6799
6800         rcs = dev_priv->engine[RCS];
6801         if (rcs->last_context)
6802                 goto out;
6803
6804         if (!rcs->init_context)
6805                 goto out;
6806
6807         mutex_lock(&dev_priv->drm.struct_mutex);
6808
6809         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6810         if (IS_ERR(req))
6811                 goto unlock;
6812
6813         if (!i915.enable_execlists && i915_switch_context(req) == 0)
6814                 rcs->init_context(req);
6815
6816         /* Mark the device busy, calling intel_enable_gt_powersave() */
6817         i915_add_request_no_flush(req);
6818
6819 unlock:
6820         mutex_unlock(&dev_priv->drm.struct_mutex);
6821 out:
6822         intel_runtime_pm_put(dev_priv);
6823 }
6824
6825 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6826 {
6827         if (READ_ONCE(dev_priv->rps.enabled))
6828                 return;
6829
6830         if (IS_IRONLAKE_M(dev_priv)) {
6831                 ironlake_enable_drps(dev_priv);
6832                 intel_init_emon(dev_priv);
6833         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6834                 /*
6835                  * PCU communication is slow and this doesn't need to be
6836                  * done at any specific time, so do this out of our fast path
6837                  * to make resume and init faster.
6838                  *
6839                  * We depend on the HW RC6 power context save/restore
6840                  * mechanism when entering D3 through runtime PM suspend. So
6841                  * disable RPM until RPS/RC6 is properly setup. We can only
6842                  * get here via the driver load/system resume/runtime resume
6843                  * paths, so the _noresume version is enough (and in case of
6844                  * runtime resume it's necessary).
6845                  */
6846                 if (queue_delayed_work(dev_priv->wq,
6847                                        &dev_priv->rps.autoenable_work,
6848                                        round_jiffies_up_relative(HZ)))
6849                         intel_runtime_pm_get_noresume(dev_priv);
6850         }
6851 }
6852
6853 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
6854 {
6855         /*
6856          * On Ibex Peak and Cougar Point, we need to disable clock
6857          * gating for the panel power sequencer or it will fail to
6858          * start up when no ports are active.
6859          */
6860         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6861 }
6862
6863 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
6864 {
6865         enum pipe pipe;
6866
6867         for_each_pipe(dev_priv, pipe) {
6868                 I915_WRITE(DSPCNTR(pipe),
6869                            I915_READ(DSPCNTR(pipe)) |
6870                            DISPPLANE_TRICKLE_FEED_DISABLE);
6871
6872                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6873                 POSTING_READ(DSPSURF(pipe));
6874         }
6875 }
6876
6877 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
6878 {
6879         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6880         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6881         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6882
6883         /*
6884          * Don't touch WM1S_LP_EN here.
6885          * Doing so could cause underruns.
6886          */
6887 }
6888
6889 static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
6890 {
6891         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6892
6893         /*
6894          * Required for FBC
6895          * WaFbcDisableDpfcClockGating:ilk
6896          */
6897         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6898                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6899                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6900
6901         I915_WRITE(PCH_3DCGDIS0,
6902                    MARIUNIT_CLOCK_GATE_DISABLE |
6903                    SVSMUNIT_CLOCK_GATE_DISABLE);
6904         I915_WRITE(PCH_3DCGDIS1,
6905                    VFMUNIT_CLOCK_GATE_DISABLE);
6906
6907         /*
6908          * According to the spec the following bits should be set in
6909          * order to enable memory self-refresh
6910          * The bit 22/21 of 0x42004
6911          * The bit 5 of 0x42020
6912          * The bit 15 of 0x45000
6913          */
6914         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6915                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6916                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6917         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6918         I915_WRITE(DISP_ARB_CTL,
6919                    (I915_READ(DISP_ARB_CTL) |
6920                     DISP_FBC_WM_DIS));
6921
6922         ilk_init_lp_watermarks(dev_priv);
6923
6924         /*
6925          * Based on the document from hardware guys the following bits
6926          * should be set unconditionally in order to enable FBC.
6927          * The bit 22 of 0x42000
6928          * The bit 22 of 0x42004
6929          * The bit 7,8,9 of 0x42020.
6930          */
6931         if (IS_IRONLAKE_M(dev_priv)) {
6932                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6933                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6934                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6935                            ILK_FBCQ_DIS);
6936                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6937                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6938                            ILK_DPARB_GATE);
6939         }
6940
6941         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6942
6943         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6944                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6945                    ILK_ELPIN_409_SELECT);
6946         I915_WRITE(_3D_CHICKEN2,
6947                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6948                    _3D_CHICKEN2_WM_READ_PIPELINED);
6949
6950         /* WaDisableRenderCachePipelinedFlush:ilk */
6951         I915_WRITE(CACHE_MODE_0,
6952                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6953
6954         /* WaDisable_RenderCache_OperationalFlush:ilk */
6955         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6956
6957         g4x_disable_trickle_feed(dev_priv);
6958
6959         ibx_init_clock_gating(dev_priv);
6960 }
6961
6962 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
6963 {
6964         int pipe;
6965         uint32_t val;
6966
6967         /*
6968          * On Ibex Peak and Cougar Point, we need to disable clock
6969          * gating for the panel power sequencer or it will fail to
6970          * start up when no ports are active.
6971          */
6972         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6973                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6974                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6975         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6976                    DPLS_EDP_PPS_FIX_DIS);
6977         /* The below fixes the weird display corruption, a few pixels shifted
6978          * downward, on (only) LVDS of some HP laptops with IVY.
6979          */
6980         for_each_pipe(dev_priv, pipe) {
6981                 val = I915_READ(TRANS_CHICKEN2(pipe));
6982                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6983                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6984                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6985                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6986                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6987                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6988                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6989                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6990         }
6991         /* WADP0ClockGatingDisable */
6992         for_each_pipe(dev_priv, pipe) {
6993                 I915_WRITE(TRANS_CHICKEN1(pipe),
6994                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6995         }
6996 }
6997
6998 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
6999 {
7000         uint32_t tmp;
7001
7002         tmp = I915_READ(MCH_SSKPD);
7003         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7004                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7005                               tmp);
7006 }
7007
7008 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
7009 {
7010         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7011
7012         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7013
7014         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7015                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7016                    ILK_ELPIN_409_SELECT);
7017
7018         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7019         I915_WRITE(_3D_CHICKEN,
7020                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7021
7022         /* WaDisable_RenderCache_OperationalFlush:snb */
7023         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7024
7025         /*
7026          * BSpec recoomends 8x4 when MSAA is used,
7027          * however in practice 16x4 seems fastest.
7028          *
7029          * Note that PS/WM thread counts depend on the WIZ hashing
7030          * disable bit, which we don't touch here, but it's good
7031          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7032          */
7033         I915_WRITE(GEN6_GT_MODE,
7034                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7035
7036         ilk_init_lp_watermarks(dev_priv);
7037
7038         I915_WRITE(CACHE_MODE_0,
7039                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7040
7041         I915_WRITE(GEN6_UCGCTL1,
7042                    I915_READ(GEN6_UCGCTL1) |
7043                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7044                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7045
7046         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7047          * gating disable must be set.  Failure to set it results in
7048          * flickering pixels due to Z write ordering failures after
7049          * some amount of runtime in the Mesa "fire" demo, and Unigine
7050          * Sanctuary and Tropics, and apparently anything else with
7051          * alpha test or pixel discard.
7052          *
7053          * According to the spec, bit 11 (RCCUNIT) must also be set,
7054          * but we didn't debug actual testcases to find it out.
7055          *
7056          * WaDisableRCCUnitClockGating:snb
7057          * WaDisableRCPBUnitClockGating:snb
7058          */
7059         I915_WRITE(GEN6_UCGCTL2,
7060                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7061                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7062
7063         /* WaStripsFansDisableFastClipPerformanceFix:snb */
7064         I915_WRITE(_3D_CHICKEN3,
7065                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7066
7067         /*
7068          * Bspec says:
7069          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7070          * 3DSTATE_SF number of SF output attributes is more than 16."
7071          */
7072         I915_WRITE(_3D_CHICKEN3,
7073                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7074
7075         /*
7076          * According to the spec the following bits should be
7077          * set in order to enable memory self-refresh and fbc:
7078          * The bit21 and bit22 of 0x42000
7079          * The bit21 and bit22 of 0x42004
7080          * The bit5 and bit7 of 0x42020
7081          * The bit14 of 0x70180
7082          * The bit14 of 0x71180
7083          *
7084          * WaFbcAsynchFlipDisableFbcQueue:snb
7085          */
7086         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7087                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7088                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7089         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7090                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7091                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7092         I915_WRITE(ILK_DSPCLK_GATE_D,
7093                    I915_READ(ILK_DSPCLK_GATE_D) |
7094                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7095                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7096
7097         g4x_disable_trickle_feed(dev_priv);
7098
7099         cpt_init_clock_gating(dev_priv);
7100
7101         gen6_check_mch_setup(dev_priv);
7102 }
7103
7104 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7105 {
7106         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7107
7108         /*
7109          * WaVSThreadDispatchOverride:ivb,vlv
7110          *
7111          * This actually overrides the dispatch
7112          * mode for all thread types.
7113          */
7114         reg &= ~GEN7_FF_SCHED_MASK;
7115         reg |= GEN7_FF_TS_SCHED_HW;
7116         reg |= GEN7_FF_VS_SCHED_HW;
7117         reg |= GEN7_FF_DS_SCHED_HW;
7118
7119         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7120 }
7121
7122 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
7123 {
7124         /*
7125          * TODO: this bit should only be enabled when really needed, then
7126          * disabled when not needed anymore in order to save power.
7127          */
7128         if (HAS_PCH_LPT_LP(dev_priv))
7129                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7130                            I915_READ(SOUTH_DSPCLK_GATE_D) |
7131                            PCH_LP_PARTITION_LEVEL_DISABLE);
7132
7133         /* WADPOClockGatingDisable:hsw */
7134         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7135                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7136                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7137 }
7138
7139 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7140 {
7141         if (HAS_PCH_LPT_LP(dev_priv)) {
7142                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7143
7144                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7145                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7146         }
7147 }
7148
7149 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7150                                    int general_prio_credits,
7151                                    int high_prio_credits)
7152 {
7153         u32 misccpctl;
7154
7155         /* WaTempDisableDOPClkGating:bdw */
7156         misccpctl = I915_READ(GEN7_MISCCPCTL);
7157         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7158
7159         I915_WRITE(GEN8_L3SQCREG1,
7160                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7161                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
7162
7163         /*
7164          * Wait at least 100 clocks before re-enabling clock gating.
7165          * See the definition of L3SQCREG1 in BSpec.
7166          */
7167         POSTING_READ(GEN8_L3SQCREG1);
7168         udelay(1);
7169         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7170 }
7171
7172 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
7173 {
7174         gen9_init_clock_gating(dev_priv);
7175
7176         /* WaDisableSDEUnitClockGating:kbl */
7177         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7178                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7179                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7180
7181         /* WaDisableGamClockGating:kbl */
7182         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7183                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7184                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7185
7186         /* WaFbcNukeOnHostModify:kbl */
7187         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7188                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7189 }
7190
7191 static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
7192 {
7193         gen9_init_clock_gating(dev_priv);
7194
7195         /* WAC6entrylatency:skl */
7196         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7197                    FBC_LLC_FULLY_OPEN);
7198
7199         /* WaFbcNukeOnHostModify:skl */
7200         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7201                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7202 }
7203
7204 static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
7205 {
7206         enum pipe pipe;
7207
7208         ilk_init_lp_watermarks(dev_priv);
7209
7210         /* WaSwitchSolVfFArbitrationPriority:bdw */
7211         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7212
7213         /* WaPsrDPAMaskVBlankInSRD:bdw */
7214         I915_WRITE(CHICKEN_PAR1_1,
7215                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7216
7217         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7218         for_each_pipe(dev_priv, pipe) {
7219                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7220                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
7221                            BDW_DPRS_MASK_VBLANK_SRD);
7222         }
7223
7224         /* WaVSRefCountFullforceMissDisable:bdw */
7225         /* WaDSRefCountFullforceMissDisable:bdw */
7226         I915_WRITE(GEN7_FF_THREAD_MODE,
7227                    I915_READ(GEN7_FF_THREAD_MODE) &
7228                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7229
7230         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7231                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7232
7233         /* WaDisableSDEUnitClockGating:bdw */
7234         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7235                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7236
7237         /* WaProgramL3SqcReg1Default:bdw */
7238         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7239
7240         /*
7241          * WaGttCachingOffByDefault:bdw
7242          * GTT cache may not work with big pages, so if those
7243          * are ever enabled GTT cache may need to be disabled.
7244          */
7245         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7246
7247         /* WaKVMNotificationOnConfigChange:bdw */
7248         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7249                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7250
7251         lpt_init_clock_gating(dev_priv);
7252 }
7253
7254 static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
7255 {
7256         ilk_init_lp_watermarks(dev_priv);
7257
7258         /* L3 caching of data atomics doesn't work -- disable it. */
7259         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7260         I915_WRITE(HSW_ROW_CHICKEN3,
7261                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7262
7263         /* This is required by WaCatErrorRejectionIssue:hsw */
7264         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7265                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7266                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7267
7268         /* WaVSRefCountFullforceMissDisable:hsw */
7269         I915_WRITE(GEN7_FF_THREAD_MODE,
7270                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7271
7272         /* WaDisable_RenderCache_OperationalFlush:hsw */
7273         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7274
7275         /* enable HiZ Raw Stall Optimization */
7276         I915_WRITE(CACHE_MODE_0_GEN7,
7277                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7278
7279         /* WaDisable4x2SubspanOptimization:hsw */
7280         I915_WRITE(CACHE_MODE_1,
7281                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7282
7283         /*
7284          * BSpec recommends 8x4 when MSAA is used,
7285          * however in practice 16x4 seems fastest.
7286          *
7287          * Note that PS/WM thread counts depend on the WIZ hashing
7288          * disable bit, which we don't touch here, but it's good
7289          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7290          */
7291         I915_WRITE(GEN7_GT_MODE,
7292                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7293
7294         /* WaSampleCChickenBitEnable:hsw */
7295         I915_WRITE(HALF_SLICE_CHICKEN3,
7296                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7297
7298         /* WaSwitchSolVfFArbitrationPriority:hsw */
7299         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7300
7301         /* WaRsPkgCStateDisplayPMReq:hsw */
7302         I915_WRITE(CHICKEN_PAR1_1,
7303                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7304
7305         lpt_init_clock_gating(dev_priv);
7306 }
7307
7308 static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
7309 {
7310         uint32_t snpcr;
7311
7312         ilk_init_lp_watermarks(dev_priv);
7313
7314         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7315
7316         /* WaDisableEarlyCull:ivb */
7317         I915_WRITE(_3D_CHICKEN3,
7318                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7319
7320         /* WaDisableBackToBackFlipFix:ivb */
7321         I915_WRITE(IVB_CHICKEN3,
7322                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7323                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7324
7325         /* WaDisablePSDDualDispatchEnable:ivb */
7326         if (IS_IVB_GT1(dev_priv))
7327                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7328                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7329
7330         /* WaDisable_RenderCache_OperationalFlush:ivb */
7331         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7332
7333         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7334         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7335                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7336
7337         /* WaApplyL3ControlAndL3ChickenMode:ivb */
7338         I915_WRITE(GEN7_L3CNTLREG1,
7339                         GEN7_WA_FOR_GEN7_L3_CONTROL);
7340         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7341                    GEN7_WA_L3_CHICKEN_MODE);
7342         if (IS_IVB_GT1(dev_priv))
7343                 I915_WRITE(GEN7_ROW_CHICKEN2,
7344                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7345         else {
7346                 /* must write both registers */
7347                 I915_WRITE(GEN7_ROW_CHICKEN2,
7348                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7349                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7350                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7351         }
7352
7353         /* WaForceL3Serialization:ivb */
7354         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7355                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7356
7357         /*
7358          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7359          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7360          */
7361         I915_WRITE(GEN6_UCGCTL2,
7362                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7363
7364         /* This is required by WaCatErrorRejectionIssue:ivb */
7365         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7366                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7367                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7368
7369         g4x_disable_trickle_feed(dev_priv);
7370
7371         gen7_setup_fixed_func_scheduler(dev_priv);
7372
7373         if (0) { /* causes HiZ corruption on ivb:gt1 */
7374                 /* enable HiZ Raw Stall Optimization */
7375                 I915_WRITE(CACHE_MODE_0_GEN7,
7376                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7377         }
7378
7379         /* WaDisable4x2SubspanOptimization:ivb */
7380         I915_WRITE(CACHE_MODE_1,
7381                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7382
7383         /*
7384          * BSpec recommends 8x4 when MSAA is used,
7385          * however in practice 16x4 seems fastest.
7386          *
7387          * Note that PS/WM thread counts depend on the WIZ hashing
7388          * disable bit, which we don't touch here, but it's good
7389          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7390          */
7391         I915_WRITE(GEN7_GT_MODE,
7392                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7393
7394         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7395         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7396         snpcr |= GEN6_MBC_SNPCR_MED;
7397         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7398
7399         if (!HAS_PCH_NOP(dev_priv))
7400                 cpt_init_clock_gating(dev_priv);
7401
7402         gen6_check_mch_setup(dev_priv);
7403 }
7404
7405 static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
7406 {
7407         /* WaDisableEarlyCull:vlv */
7408         I915_WRITE(_3D_CHICKEN3,
7409                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7410
7411         /* WaDisableBackToBackFlipFix:vlv */
7412         I915_WRITE(IVB_CHICKEN3,
7413                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7414                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7415
7416         /* WaPsdDispatchEnable:vlv */
7417         /* WaDisablePSDDualDispatchEnable:vlv */
7418         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7419                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7420                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7421
7422         /* WaDisable_RenderCache_OperationalFlush:vlv */
7423         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7424
7425         /* WaForceL3Serialization:vlv */
7426         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7427                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7428
7429         /* WaDisableDopClockGating:vlv */
7430         I915_WRITE(GEN7_ROW_CHICKEN2,
7431                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7432
7433         /* This is required by WaCatErrorRejectionIssue:vlv */
7434         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7435                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7436                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7437
7438         gen7_setup_fixed_func_scheduler(dev_priv);
7439
7440         /*
7441          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7442          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7443          */
7444         I915_WRITE(GEN6_UCGCTL2,
7445                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7446
7447         /* WaDisableL3Bank2xClockGate:vlv
7448          * Disabling L3 clock gating- MMIO 940c[25] = 1
7449          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7450         I915_WRITE(GEN7_UCGCTL4,
7451                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7452
7453         /*
7454          * BSpec says this must be set, even though
7455          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7456          */
7457         I915_WRITE(CACHE_MODE_1,
7458                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7459
7460         /*
7461          * BSpec recommends 8x4 when MSAA is used,
7462          * however in practice 16x4 seems fastest.
7463          *
7464          * Note that PS/WM thread counts depend on the WIZ hashing
7465          * disable bit, which we don't touch here, but it's good
7466          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7467          */
7468         I915_WRITE(GEN7_GT_MODE,
7469                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7470
7471         /*
7472          * WaIncreaseL3CreditsForVLVB0:vlv
7473          * This is the hardware default actually.
7474          */
7475         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7476
7477         /*
7478          * WaDisableVLVClockGating_VBIIssue:vlv
7479          * Disable clock gating on th GCFG unit to prevent a delay
7480          * in the reporting of vblank events.
7481          */
7482         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7483 }
7484
7485 static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
7486 {
7487         /* WaVSRefCountFullforceMissDisable:chv */
7488         /* WaDSRefCountFullforceMissDisable:chv */
7489         I915_WRITE(GEN7_FF_THREAD_MODE,
7490                    I915_READ(GEN7_FF_THREAD_MODE) &
7491                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7492
7493         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7494         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7495                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7496
7497         /* WaDisableCSUnitClockGating:chv */
7498         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7499                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7500
7501         /* WaDisableSDEUnitClockGating:chv */
7502         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7503                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7504
7505         /*
7506          * WaProgramL3SqcReg1Default:chv
7507          * See gfxspecs/Related Documents/Performance Guide/
7508          * LSQC Setting Recommendations.
7509          */
7510         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7511
7512         /*
7513          * GTT cache may not work with big pages, so if those
7514          * are ever enabled GTT cache may need to be disabled.
7515          */
7516         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7517 }
7518
7519 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
7520 {
7521         uint32_t dspclk_gate;
7522
7523         I915_WRITE(RENCLK_GATE_D1, 0);
7524         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7525                    GS_UNIT_CLOCK_GATE_DISABLE |
7526                    CL_UNIT_CLOCK_GATE_DISABLE);
7527         I915_WRITE(RAMCLK_GATE_D, 0);
7528         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7529                 OVRUNIT_CLOCK_GATE_DISABLE |
7530                 OVCUNIT_CLOCK_GATE_DISABLE;
7531         if (IS_GM45(dev_priv))
7532                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7533         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7534
7535         /* WaDisableRenderCachePipelinedFlush */
7536         I915_WRITE(CACHE_MODE_0,
7537                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7538
7539         /* WaDisable_RenderCache_OperationalFlush:g4x */
7540         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7541
7542         g4x_disable_trickle_feed(dev_priv);
7543 }
7544
7545 static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
7546 {
7547         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7548         I915_WRITE(RENCLK_GATE_D2, 0);
7549         I915_WRITE(DSPCLK_GATE_D, 0);
7550         I915_WRITE(RAMCLK_GATE_D, 0);
7551         I915_WRITE16(DEUC, 0);
7552         I915_WRITE(MI_ARB_STATE,
7553                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7554
7555         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7556         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7557 }
7558
7559 static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
7560 {
7561         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7562                    I965_RCC_CLOCK_GATE_DISABLE |
7563                    I965_RCPB_CLOCK_GATE_DISABLE |
7564                    I965_ISC_CLOCK_GATE_DISABLE |
7565                    I965_FBC_CLOCK_GATE_DISABLE);
7566         I915_WRITE(RENCLK_GATE_D2, 0);
7567         I915_WRITE(MI_ARB_STATE,
7568                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7569
7570         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7571         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7572 }
7573
7574 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
7575 {
7576         u32 dstate = I915_READ(D_STATE);
7577
7578         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7579                 DSTATE_DOT_CLOCK_GATING;
7580         I915_WRITE(D_STATE, dstate);
7581
7582         if (IS_PINEVIEW(dev_priv))
7583                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7584
7585         /* IIR "flip pending" means done if this bit is set */
7586         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7587
7588         /* interrupts should cause a wake up from C3 */
7589         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7590
7591         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7592         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7593
7594         I915_WRITE(MI_ARB_STATE,
7595                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7596 }
7597
7598 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
7599 {
7600         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7601
7602         /* interrupts should cause a wake up from C3 */
7603         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7604                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7605
7606         I915_WRITE(MEM_MODE,
7607                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7608 }
7609
7610 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
7611 {
7612         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7613
7614         I915_WRITE(MEM_MODE,
7615                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7616                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7617 }
7618
7619 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
7620 {
7621         dev_priv->display.init_clock_gating(dev_priv);
7622 }
7623
7624 void intel_suspend_hw(struct drm_i915_private *dev_priv)
7625 {
7626         if (HAS_PCH_LPT(dev_priv))
7627                 lpt_suspend_hw(dev_priv);
7628 }
7629
7630 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
7631 {
7632         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7633 }
7634
7635 /**
7636  * intel_init_clock_gating_hooks - setup the clock gating hooks
7637  * @dev_priv: device private
7638  *
7639  * Setup the hooks that configure which clocks of a given platform can be
7640  * gated and also apply various GT and display specific workarounds for these
7641  * platforms. Note that some GT specific workarounds are applied separately
7642  * when GPU contexts or batchbuffers start their execution.
7643  */
7644 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7645 {
7646         if (IS_SKYLAKE(dev_priv))
7647                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7648         else if (IS_KABYLAKE(dev_priv))
7649                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7650         else if (IS_BROXTON(dev_priv))
7651                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7652         else if (IS_BROADWELL(dev_priv))
7653                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7654         else if (IS_CHERRYVIEW(dev_priv))
7655                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7656         else if (IS_HASWELL(dev_priv))
7657                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7658         else if (IS_IVYBRIDGE(dev_priv))
7659                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7660         else if (IS_VALLEYVIEW(dev_priv))
7661                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7662         else if (IS_GEN6(dev_priv))
7663                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7664         else if (IS_GEN5(dev_priv))
7665                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7666         else if (IS_G4X(dev_priv))
7667                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7668         else if (IS_CRESTLINE(dev_priv))
7669                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7670         else if (IS_BROADWATER(dev_priv))
7671                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7672         else if (IS_GEN3(dev_priv))
7673                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7674         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7675                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7676         else if (IS_GEN2(dev_priv))
7677                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7678         else {
7679                 MISSING_CASE(INTEL_DEVID(dev_priv));
7680                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7681         }
7682 }
7683
7684 /* Set up chip specific power management-related functions */
7685 void intel_init_pm(struct drm_i915_private *dev_priv)
7686 {
7687         intel_fbc_init(dev_priv);
7688
7689         /* For cxsr */
7690         if (IS_PINEVIEW(dev_priv))
7691                 i915_pineview_get_mem_freq(dev_priv);
7692         else if (IS_GEN5(dev_priv))
7693                 i915_ironlake_get_mem_freq(dev_priv);
7694
7695         /* For FIFO watermark updates */
7696         if (INTEL_GEN(dev_priv) >= 9) {
7697                 skl_setup_wm_latency(dev_priv);
7698                 dev_priv->display.initial_watermarks = skl_initial_wm;
7699                 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
7700                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7701         } else if (HAS_PCH_SPLIT(dev_priv)) {
7702                 ilk_setup_wm_latency(dev_priv);
7703
7704                 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
7705                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7706                     (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
7707                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7708                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7709                         dev_priv->display.compute_intermediate_wm =
7710                                 ilk_compute_intermediate_wm;
7711                         dev_priv->display.initial_watermarks =
7712                                 ilk_initial_watermarks;
7713                         dev_priv->display.optimize_watermarks =
7714                                 ilk_optimize_watermarks;
7715                 } else {
7716                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7717                                       "Disable CxSR\n");
7718                 }
7719         } else if (IS_CHERRYVIEW(dev_priv)) {
7720                 vlv_setup_wm_latency(dev_priv);
7721                 dev_priv->display.update_wm = vlv_update_wm;
7722         } else if (IS_VALLEYVIEW(dev_priv)) {
7723                 vlv_setup_wm_latency(dev_priv);
7724                 dev_priv->display.update_wm = vlv_update_wm;
7725         } else if (IS_PINEVIEW(dev_priv)) {
7726                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
7727                                             dev_priv->is_ddr3,
7728                                             dev_priv->fsb_freq,
7729                                             dev_priv->mem_freq)) {
7730                         DRM_INFO("failed to find known CxSR latency "
7731                                  "(found ddr%s fsb freq %d, mem freq %d), "
7732                                  "disabling CxSR\n",
7733                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7734                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7735                         /* Disable CxSR and never update its watermark again */
7736                         intel_set_memory_cxsr(dev_priv, false);
7737                         dev_priv->display.update_wm = NULL;
7738                 } else
7739                         dev_priv->display.update_wm = pineview_update_wm;
7740         } else if (IS_G4X(dev_priv)) {
7741                 dev_priv->display.update_wm = g4x_update_wm;
7742         } else if (IS_GEN4(dev_priv)) {
7743                 dev_priv->display.update_wm = i965_update_wm;
7744         } else if (IS_GEN3(dev_priv)) {
7745                 dev_priv->display.update_wm = i9xx_update_wm;
7746                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7747         } else if (IS_GEN2(dev_priv)) {
7748                 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
7749                         dev_priv->display.update_wm = i845_update_wm;
7750                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7751                 } else {
7752                         dev_priv->display.update_wm = i9xx_update_wm;
7753                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7754                 }
7755         } else {
7756                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7757         }
7758 }
7759
7760 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7761 {
7762         uint32_t flags =
7763                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7764
7765         switch (flags) {
7766         case GEN6_PCODE_SUCCESS:
7767                 return 0;
7768         case GEN6_PCODE_UNIMPLEMENTED_CMD:
7769         case GEN6_PCODE_ILLEGAL_CMD:
7770                 return -ENXIO;
7771         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7772         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7773                 return -EOVERFLOW;
7774         case GEN6_PCODE_TIMEOUT:
7775                 return -ETIMEDOUT;
7776         default:
7777                 MISSING_CASE(flags)
7778                 return 0;
7779         }
7780 }
7781
7782 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7783 {
7784         uint32_t flags =
7785                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7786
7787         switch (flags) {
7788         case GEN6_PCODE_SUCCESS:
7789                 return 0;
7790         case GEN6_PCODE_ILLEGAL_CMD:
7791                 return -ENXIO;
7792         case GEN7_PCODE_TIMEOUT:
7793                 return -ETIMEDOUT;
7794         case GEN7_PCODE_ILLEGAL_DATA:
7795                 return -EINVAL;
7796         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7797                 return -EOVERFLOW;
7798         default:
7799                 MISSING_CASE(flags);
7800                 return 0;
7801         }
7802 }
7803
7804 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7805 {
7806         int status;
7807
7808         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7809
7810         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7811          * use te fw I915_READ variants to reduce the amount of work
7812          * required when reading/writing.
7813          */
7814
7815         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7816                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7817                 return -EAGAIN;
7818         }
7819
7820         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7821         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7822         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7823
7824         if (intel_wait_for_register_fw(dev_priv,
7825                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7826                                        500)) {
7827                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7828                 return -ETIMEDOUT;
7829         }
7830
7831         *val = I915_READ_FW(GEN6_PCODE_DATA);
7832         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7833
7834         if (INTEL_GEN(dev_priv) > 6)
7835                 status = gen7_check_mailbox_status(dev_priv);
7836         else
7837                 status = gen6_check_mailbox_status(dev_priv);
7838
7839         if (status) {
7840                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7841                                  status);
7842                 return status;
7843         }
7844
7845         return 0;
7846 }
7847
7848 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7849                             u32 mbox, u32 val)
7850 {
7851         int status;
7852
7853         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7854
7855         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7856          * use te fw I915_READ variants to reduce the amount of work
7857          * required when reading/writing.
7858          */
7859
7860         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7861                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7862                 return -EAGAIN;
7863         }
7864
7865         I915_WRITE_FW(GEN6_PCODE_DATA, val);
7866         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7867
7868         if (intel_wait_for_register_fw(dev_priv,
7869                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7870                                        500)) {
7871                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7872                 return -ETIMEDOUT;
7873         }
7874
7875         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7876
7877         if (INTEL_GEN(dev_priv) > 6)
7878                 status = gen7_check_mailbox_status(dev_priv);
7879         else
7880                 status = gen6_check_mailbox_status(dev_priv);
7881
7882         if (status) {
7883                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7884                                  status);
7885                 return status;
7886         }
7887
7888         return 0;
7889 }
7890
7891 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7892 {
7893         /*
7894          * N = val - 0xb7
7895          * Slow = Fast = GPLL ref * N
7896          */
7897         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7898 }
7899
7900 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7901 {
7902         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7903 }
7904
7905 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7906 {
7907         /*
7908          * N = val / 2
7909          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7910          */
7911         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7912 }
7913
7914 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7915 {
7916         /* CHV needs even values */
7917         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7918 }
7919
7920 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7921 {
7922         if (IS_GEN9(dev_priv))
7923                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7924                                          GEN9_FREQ_SCALER);
7925         else if (IS_CHERRYVIEW(dev_priv))
7926                 return chv_gpu_freq(dev_priv, val);
7927         else if (IS_VALLEYVIEW(dev_priv))
7928                 return byt_gpu_freq(dev_priv, val);
7929         else
7930                 return val * GT_FREQUENCY_MULTIPLIER;
7931 }
7932
7933 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7934 {
7935         if (IS_GEN9(dev_priv))
7936                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7937                                          GT_FREQUENCY_MULTIPLIER);
7938         else if (IS_CHERRYVIEW(dev_priv))
7939                 return chv_freq_opcode(dev_priv, val);
7940         else if (IS_VALLEYVIEW(dev_priv))
7941                 return byt_freq_opcode(dev_priv, val);
7942         else
7943                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7944 }
7945
7946 struct request_boost {
7947         struct work_struct work;
7948         struct drm_i915_gem_request *req;
7949 };
7950
7951 static void __intel_rps_boost_work(struct work_struct *work)
7952 {
7953         struct request_boost *boost = container_of(work, struct request_boost, work);
7954         struct drm_i915_gem_request *req = boost->req;
7955
7956         if (!i915_gem_request_completed(req))
7957                 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7958
7959         i915_gem_request_put(req);
7960         kfree(boost);
7961 }
7962
7963 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
7964 {
7965         struct request_boost *boost;
7966
7967         if (req == NULL || INTEL_GEN(req->i915) < 6)
7968                 return;
7969
7970         if (i915_gem_request_completed(req))
7971                 return;
7972
7973         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7974         if (boost == NULL)
7975                 return;
7976
7977         boost->req = i915_gem_request_get(req);
7978
7979         INIT_WORK(&boost->work, __intel_rps_boost_work);
7980         queue_work(req->i915->wq, &boost->work);
7981 }
7982
7983 void intel_pm_setup(struct drm_device *dev)
7984 {
7985         struct drm_i915_private *dev_priv = to_i915(dev);
7986
7987         mutex_init(&dev_priv->rps.hw_lock);
7988         spin_lock_init(&dev_priv->rps.client_lock);
7989
7990         INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
7991                           __intel_autoenable_gt_powersave);
7992         INIT_LIST_HEAD(&dev_priv->rps.clients);
7993
7994         dev_priv->pm.suspended = false;
7995         atomic_set(&dev_priv->pm.wakeref_count, 0);
7996 }