drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34 #include <drm/drm_atomic_helper.h>
  35
  36 /**
  37  * DOC: RC6
  38  *
  39  * RC6 is a special power stage which allows the GPU to enter an very
  40  * low-voltage mode when idle, using down to 0V while at this stage.  This
  41  * stage is entered automatically when the GPU is idle when RC6 support is
  42  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  43  *
  44  * There are different RC6 modes available in Intel GPU, which differentiate
  45  * among each other with the latency required to enter and leave RC6 and
  46  * voltage consumed by the GPU in different states.
  47  *
  48  * The combination of the following flags define which states GPU is allowed
  49  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  50  * RC6pp is deepest RC6. Their support by hardware varies according to the
  51  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  52  * which brings the most power savings; deeper states save more power, but
  53  * require higher latency to switch to and wake up.
  54  */
  55 #define INTEL_RC6_ENABLE                        (1<<0)
  56 #define INTEL_RC6p_ENABLE                       (1<<1)
  57 #define INTEL_RC6pp_ENABLE                      (1<<2)
  58
  59 static void gen9_init_clock_gating(struct drm_device *dev)
  60 {
  61         struct drm_i915_private *dev_priv = dev->dev_private;
  62
  63         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
  64         I915_WRITE(CHICKEN_PAR1_1,
  65                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  66
  67         I915_WRITE(GEN8_CONFIG0,
  68                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  69
  70         /* WaEnableChickenDCPR:skl,bxt,kbl */
  71         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  72                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  73
  74         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
  75         /* WaFbcWakeMemOn:skl,bxt,kbl */
  76         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  77                    DISP_FBC_WM_DIS |
  78                    DISP_FBC_MEMORY_WAKE);
  79
  80         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
  81         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  82                    ILK_DPFC_DISABLE_DUMMY0);
  83 }
  84
  85 static void bxt_init_clock_gating(struct drm_device *dev)
  86 {
  87         struct drm_i915_private *dev_priv = to_i915(dev);
  88
  89         gen9_init_clock_gating(dev);
  90
  91         /* WaDisableSDEUnitClockGating:bxt */
  92         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  93                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  94
  95         /*
  96          * FIXME:
  97          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  98          */
  99         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 100                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 101
 102         /*
 103          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 104          * to stay fully on.
 105          */
 106         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
 107                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 108                            PWM1_GATING_DIS | PWM2_GATING_DIS);
 109 }
 110
 111 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 112 {
 113         struct drm_i915_private *dev_priv = to_i915(dev);
 114         u32 tmp;
 115
 116         tmp = I915_READ(CLKCFG);
 117
 118         switch (tmp & CLKCFG_FSB_MASK) {
 119         case CLKCFG_FSB_533:
 120                 dev_priv->fsb_freq = 533; /* 133*4 */
 121                 break;
 122         case CLKCFG_FSB_800:
 123                 dev_priv->fsb_freq = 800; /* 200*4 */
 124                 break;
 125         case CLKCFG_FSB_667:
 126                 dev_priv->fsb_freq =  667; /* 167*4 */
 127                 break;
 128         case CLKCFG_FSB_400:
 129                 dev_priv->fsb_freq = 400; /* 100*4 */
 130                 break;
 131         }
 132
 133         switch (tmp & CLKCFG_MEM_MASK) {
 134         case CLKCFG_MEM_533:
 135                 dev_priv->mem_freq = 533;
 136                 break;
 137         case CLKCFG_MEM_667:
 138                 dev_priv->mem_freq = 667;
 139                 break;
 140         case CLKCFG_MEM_800:
 141                 dev_priv->mem_freq = 800;
 142                 break;
 143         }
 144
 145         /* detect pineview DDR3 setting */
 146         tmp = I915_READ(CSHRDDR3CTL);
 147         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 148 }
 149
 150 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 151 {
 152         struct drm_i915_private *dev_priv = to_i915(dev);
 153         u16 ddrpll, csipll;
 154
 155         ddrpll = I915_READ16(DDRMPLL1);
 156         csipll = I915_READ16(CSIPLL0);
 157
 158         switch (ddrpll & 0xff) {
 159         case 0xc:
 160                 dev_priv->mem_freq = 800;
 161                 break;
 162         case 0x10:
 163                 dev_priv->mem_freq = 1066;
 164                 break;
 165         case 0x14:
 166                 dev_priv->mem_freq = 1333;
 167                 break;
 168         case 0x18:
 169                 dev_priv->mem_freq = 1600;
 170                 break;
 171         default:
 172                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 173                                  ddrpll & 0xff);
 174                 dev_priv->mem_freq = 0;
 175                 break;
 176         }
 177
 178         dev_priv->ips.r_t = dev_priv->mem_freq;
 179
 180         switch (csipll & 0x3ff) {
 181         case 0x00c:
 182                 dev_priv->fsb_freq = 3200;
 183                 break;
 184         case 0x00e:
 185                 dev_priv->fsb_freq = 3733;
 186                 break;
 187         case 0x010:
 188                 dev_priv->fsb_freq = 4266;
 189                 break;
 190         case 0x012:
 191                 dev_priv->fsb_freq = 4800;
 192                 break;
 193         case 0x014:
 194                 dev_priv->fsb_freq = 5333;
 195                 break;
 196         case 0x016:
 197                 dev_priv->fsb_freq = 5866;
 198                 break;
 199         case 0x018:
 200                 dev_priv->fsb_freq = 6400;
 201                 break;
 202         default:
 203                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 204                                  csipll & 0x3ff);
 205                 dev_priv->fsb_freq = 0;
 206                 break;
 207         }
 208
 209         if (dev_priv->fsb_freq == 3200) {
 210                 dev_priv->ips.c_m = 0;
 211         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 212                 dev_priv->ips.c_m = 1;
 213         } else {
 214                 dev_priv->ips.c_m = 2;
 215         }
 216 }
 217
 218 static const struct cxsr_latency cxsr_latency_table[] = {
 219         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 220         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 221         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 222         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 223         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 224
 225         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 226         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 227         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 228         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 229         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 230
 231         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 232         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 233         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 234         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 235         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 236
 237         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 238         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 239         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 240         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 241         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 242
 243         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 244         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 245         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 246         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 247         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 248
 249         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 250         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 251         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 252         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 253         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 254 };
 255
 256 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 257                                                          bool is_ddr3,
 258                                                          int fsb,
 259                                                          int mem)
 260 {
 261         const struct cxsr_latency *latency;
 262         int i;
 263
 264         if (fsb == 0 || mem == 0)
 265                 return NULL;
 266
 267         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 268                 latency = &cxsr_latency_table[i];
 269                 if (is_desktop == latency->is_desktop &&
 270                     is_ddr3 == latency->is_ddr3 &&
 271                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 272                         return latency;
 273         }
 274
 275         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 276
 277         return NULL;
 278 }
 279
 280 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 281 {
 282         u32 val;
 283
 284         mutex_lock(&dev_priv->rps.hw_lock);
 285
 286         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 287         if (enable)
 288                 val &= ~FORCE_DDR_HIGH_FREQ;
 289         else
 290                 val |= FORCE_DDR_HIGH_FREQ;
 291         val &= ~FORCE_DDR_LOW_FREQ;
 292         val |= FORCE_DDR_FREQ_REQ_ACK;
 293         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 294
 295         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 296                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 297                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 298
 299         mutex_unlock(&dev_priv->rps.hw_lock);
 300 }
 301
 302 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 303 {
 304         u32 val;
 305
 306         mutex_lock(&dev_priv->rps.hw_lock);
 307
 308         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 309         if (enable)
 310                 val |= DSP_MAXFIFO_PM5_ENABLE;
 311         else
 312                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 313         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 314
 315         mutex_unlock(&dev_priv->rps.hw_lock);
 316 }
 317
 318 #define FW_WM(value, plane) \
 319         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 320
 321 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 322 {
 323         struct drm_device *dev = &dev_priv->drm;
 324         u32 val;
 325
 326         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 327                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 328                 POSTING_READ(FW_BLC_SELF_VLV);
 329                 dev_priv->wm.vlv.cxsr = enable;
 330         } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
 331                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 332                 POSTING_READ(FW_BLC_SELF);
 333         } else if (IS_PINEVIEW(dev)) {
 334                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 335                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 336                 I915_WRITE(DSPFW3, val);
 337                 POSTING_READ(DSPFW3);
 338         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 339                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 340                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 341                 I915_WRITE(FW_BLC_SELF, val);
 342                 POSTING_READ(FW_BLC_SELF);
 343         } else if (IS_I915GM(dev_priv)) {
 344                 /*
 345                  * FIXME can't find a bit like this for 915G, and
 346                  * and yet it does have the related watermark in
 347                  * FW_BLC_SELF. What's going on?
 348                  */
 349                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 350                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 351                 I915_WRITE(INSTPM, val);
 352                 POSTING_READ(INSTPM);
 353         } else {
 354                 return;
 355         }
 356
 357         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 358                       enable ? "enabled" : "disabled");
 359 }
 360
 361
 362 /*
 363  * Latency for FIFO fetches is dependent on several factors:
 364  *   - memory configuration (speed, channels)
 365  *   - chipset
 366  *   - current MCH state
 367  * It can be fairly high in some situations, so here we assume a fairly
 368  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 369  * set this value too high, the FIFO will fetch frequently to stay full)
 370  * and power consumption (set it too low to save power and we might see
 371  * FIFO underruns and display "flicker").
 372  *
 373  * A value of 5us seems to be a good balance; safe for very low end
 374  * platforms but not overly aggressive on lower latency configs.
 375  */
 376 static const int pessimal_latency_ns = 5000;
 377
 378 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 379         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 380
 381 static int vlv_get_fifo_size(struct drm_device *dev,
 382                               enum pipe pipe, int plane)
 383 {
 384         struct drm_i915_private *dev_priv = to_i915(dev);
 385         int sprite0_start, sprite1_start, size;
 386
 387         switch (pipe) {
 388                 uint32_t dsparb, dsparb2, dsparb3;
 389         case PIPE_A:
 390                 dsparb = I915_READ(DSPARB);
 391                 dsparb2 = I915_READ(DSPARB2);
 392                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 393                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 394                 break;
 395         case PIPE_B:
 396                 dsparb = I915_READ(DSPARB);
 397                 dsparb2 = I915_READ(DSPARB2);
 398                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 399                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 400                 break;
 401         case PIPE_C:
 402                 dsparb2 = I915_READ(DSPARB2);
 403                 dsparb3 = I915_READ(DSPARB3);
 404                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 405                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 406                 break;
 407         default:
 408                 return 0;
 409         }
 410
 411         switch (plane) {
 412         case 0:
 413                 size = sprite0_start;
 414                 break;
 415         case 1:
 416                 size = sprite1_start - sprite0_start;
 417                 break;
 418         case 2:
 419                 size = 512 - 1 - sprite1_start;
 420                 break;
 421         default:
 422                 return 0;
 423         }
 424
 425         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 426                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 427                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 428                       size);
 429
 430         return size;
 431 }
 432
 433 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 434 {
 435         struct drm_i915_private *dev_priv = to_i915(dev);
 436         uint32_t dsparb = I915_READ(DSPARB);
 437         int size;
 438
 439         size = dsparb & 0x7f;
 440         if (plane)
 441                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 442
 443         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 444                       plane ? "B" : "A", size);
 445
 446         return size;
 447 }
 448
 449 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 450 {
 451         struct drm_i915_private *dev_priv = to_i915(dev);
 452         uint32_t dsparb = I915_READ(DSPARB);
 453         int size;
 454
 455         size = dsparb & 0x1ff;
 456         if (plane)
 457                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 458         size >>= 1; /* Convert to cachelines */
 459
 460         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 461                       plane ? "B" : "A", size);
 462
 463         return size;
 464 }
 465
 466 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 467 {
 468         struct drm_i915_private *dev_priv = to_i915(dev);
 469         uint32_t dsparb = I915_READ(DSPARB);
 470         int size;
 471
 472         size = dsparb & 0x7f;
 473         size >>= 2; /* Convert to cachelines */
 474
 475         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 476                       plane ? "B" : "A",
 477                       size);
 478
 479         return size;
 480 }
 481
 482 /* Pineview has different values for various configs */
 483 static const struct intel_watermark_params pineview_display_wm = {
 484         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 485         .max_wm = PINEVIEW_MAX_WM,
 486         .default_wm = PINEVIEW_DFT_WM,
 487         .guard_size = PINEVIEW_GUARD_WM,
 488         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 489 };
 490 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 491         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 492         .max_wm = PINEVIEW_MAX_WM,
 493         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 494         .guard_size = PINEVIEW_GUARD_WM,
 495         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 496 };
 497 static const struct intel_watermark_params pineview_cursor_wm = {
 498         .fifo_size = PINEVIEW_CURSOR_FIFO,
 499         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 500         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 501         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 502         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 503 };
 504 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 505         .fifo_size = PINEVIEW_CURSOR_FIFO,
 506         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 507         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 508         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 509         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 510 };
 511 static const struct intel_watermark_params g4x_wm_info = {
 512         .fifo_size = G4X_FIFO_SIZE,
 513         .max_wm = G4X_MAX_WM,
 514         .default_wm = G4X_MAX_WM,
 515         .guard_size = 2,
 516         .cacheline_size = G4X_FIFO_LINE_SIZE,
 517 };
 518 static const struct intel_watermark_params g4x_cursor_wm_info = {
 519         .fifo_size = I965_CURSOR_FIFO,
 520         .max_wm = I965_CURSOR_MAX_WM,
 521         .default_wm = I965_CURSOR_DFT_WM,
 522         .guard_size = 2,
 523         .cacheline_size = G4X_FIFO_LINE_SIZE,
 524 };
 525 static const struct intel_watermark_params i965_cursor_wm_info = {
 526         .fifo_size = I965_CURSOR_FIFO,
 527         .max_wm = I965_CURSOR_MAX_WM,
 528         .default_wm = I965_CURSOR_DFT_WM,
 529         .guard_size = 2,
 530         .cacheline_size = I915_FIFO_LINE_SIZE,
 531 };
 532 static const struct intel_watermark_params i945_wm_info = {
 533         .fifo_size = I945_FIFO_SIZE,
 534         .max_wm = I915_MAX_WM,
 535         .default_wm = 1,
 536         .guard_size = 2,
 537         .cacheline_size = I915_FIFO_LINE_SIZE,
 538 };
 539 static const struct intel_watermark_params i915_wm_info = {
 540         .fifo_size = I915_FIFO_SIZE,
 541         .max_wm = I915_MAX_WM,
 542         .default_wm = 1,
 543         .guard_size = 2,
 544         .cacheline_size = I915_FIFO_LINE_SIZE,
 545 };
 546 static const struct intel_watermark_params i830_a_wm_info = {
 547         .fifo_size = I855GM_FIFO_SIZE,
 548         .max_wm = I915_MAX_WM,
 549         .default_wm = 1,
 550         .guard_size = 2,
 551         .cacheline_size = I830_FIFO_LINE_SIZE,
 552 };
 553 static const struct intel_watermark_params i830_bc_wm_info = {
 554         .fifo_size = I855GM_FIFO_SIZE,
 555         .max_wm = I915_MAX_WM/2,
 556         .default_wm = 1,
 557         .guard_size = 2,
 558         .cacheline_size = I830_FIFO_LINE_SIZE,
 559 };
 560 static const struct intel_watermark_params i845_wm_info = {
 561         .fifo_size = I830_FIFO_SIZE,
 562         .max_wm = I915_MAX_WM,
 563         .default_wm = 1,
 564         .guard_size = 2,
 565         .cacheline_size = I830_FIFO_LINE_SIZE,
 566 };
 567
 568 /**
 569  * intel_calculate_wm - calculate watermark level
 570  * @clock_in_khz: pixel clock
 571  * @wm: chip FIFO params
 572  * @cpp: bytes per pixel
 573  * @latency_ns: memory latency for the platform
 574  *
 575  * Calculate the watermark level (the level at which the display plane will
 576  * start fetching from memory again).  Each chip has a different display
 577  * FIFO size and allocation, so the caller needs to figure that out and pass
 578  * in the correct intel_watermark_params structure.
 579  *
 580  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 581  * on the pixel size.  When it reaches the watermark level, it'll start
 582  * fetching FIFO line sized based chunks from memory until the FIFO fills
 583  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 584  * will occur, and a display engine hang could result.
 585  */
 586 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 587                                         const struct intel_watermark_params *wm,
 588                                         int fifo_size, int cpp,
 589                                         unsigned long latency_ns)
 590 {
 591         long entries_required, wm_size;
 592
 593         /*
 594          * Note: we need to make sure we don't overflow for various clock &
 595          * latency values.
 596          * clocks go from a few thousand to several hundred thousand.
 597          * latency is usually a few thousand
 598          */
 599         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 600                 1000;
 601         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 602
 603         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 604
 605         wm_size = fifo_size - (entries_required + wm->guard_size);
 606
 607         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 608
 609         /* Don't promote wm_size to unsigned... */
 610         if (wm_size > (long)wm->max_wm)
 611                 wm_size = wm->max_wm;
 612         if (wm_size <= 0)
 613                 wm_size = wm->default_wm;
 614
 615         /*
 616          * Bspec seems to indicate that the value shouldn't be lower than
 617          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 618          * Lets go for 8 which is the burst size since certain platforms
 619          * already use a hardcoded 8 (which is what the spec says should be
 620          * done).
 621          */
 622         if (wm_size <= 8)
 623                 wm_size = 8;
 624
 625         return wm_size;
 626 }
 627
 628 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 629 {
 630         struct drm_crtc *crtc, *enabled = NULL;
 631
 632         for_each_crtc(dev, crtc) {
 633                 if (intel_crtc_active(crtc)) {
 634                         if (enabled)
 635                                 return NULL;
 636                         enabled = crtc;
 637                 }
 638         }
 639
 640         return enabled;
 641 }
 642
 643 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 644 {
 645         struct drm_device *dev = unused_crtc->dev;
 646         struct drm_i915_private *dev_priv = to_i915(dev);
 647         struct drm_crtc *crtc;
 648         const struct cxsr_latency *latency;
 649         u32 reg;
 650         unsigned long wm;
 651
 652         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 653                                          dev_priv->is_ddr3,
 654                                          dev_priv->fsb_freq,
 655                                          dev_priv->mem_freq);
 656         if (!latency) {
 657                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 658                 intel_set_memory_cxsr(dev_priv, false);
 659                 return;
 660         }
 661
 662         crtc = single_enabled_crtc(dev);
 663         if (crtc) {
 664                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 665                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 666                 int clock = adjusted_mode->crtc_clock;
 667
 668                 /* Display SR */
 669                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 670                                         pineview_display_wm.fifo_size,
 671                                         cpp, latency->display_sr);
 672                 reg = I915_READ(DSPFW1);
 673                 reg &= ~DSPFW_SR_MASK;
 674                 reg |= FW_WM(wm, SR);
 675                 I915_WRITE(DSPFW1, reg);
 676                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 677
 678                 /* cursor SR */
 679                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 680                                         pineview_display_wm.fifo_size,
 681                                         cpp, latency->cursor_sr);
 682                 reg = I915_READ(DSPFW3);
 683                 reg &= ~DSPFW_CURSOR_SR_MASK;
 684                 reg |= FW_WM(wm, CURSOR_SR);
 685                 I915_WRITE(DSPFW3, reg);
 686
 687                 /* Display HPLL off SR */
 688                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 689                                         pineview_display_hplloff_wm.fifo_size,
 690                                         cpp, latency->display_hpll_disable);
 691                 reg = I915_READ(DSPFW3);
 692                 reg &= ~DSPFW_HPLL_SR_MASK;
 693                 reg |= FW_WM(wm, HPLL_SR);
 694                 I915_WRITE(DSPFW3, reg);
 695
 696                 /* cursor HPLL off SR */
 697                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 698                                         pineview_display_hplloff_wm.fifo_size,
 699                                         cpp, latency->cursor_hpll_disable);
 700                 reg = I915_READ(DSPFW3);
 701                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 702                 reg |= FW_WM(wm, HPLL_CURSOR);
 703                 I915_WRITE(DSPFW3, reg);
 704                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 705
 706                 intel_set_memory_cxsr(dev_priv, true);
 707         } else {
 708                 intel_set_memory_cxsr(dev_priv, false);
 709         }
 710 }
 711
 712 static bool g4x_compute_wm0(struct drm_device *dev,
 713                             int plane,
 714                             const struct intel_watermark_params *display,
 715                             int display_latency_ns,
 716                             const struct intel_watermark_params *cursor,
 717                             int cursor_latency_ns,
 718                             int *plane_wm,
 719                             int *cursor_wm)
 720 {
 721         struct drm_crtc *crtc;
 722         const struct drm_display_mode *adjusted_mode;
 723         int htotal, hdisplay, clock, cpp;
 724         int line_time_us, line_count;
 725         int entries, tlb_miss;
 726
 727         crtc = intel_get_crtc_for_plane(dev, plane);
 728         if (!intel_crtc_active(crtc)) {
 729                 *cursor_wm = cursor->guard_size;
 730                 *plane_wm = display->guard_size;
 731                 return false;
 732         }
 733
 734         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 735         clock = adjusted_mode->crtc_clock;
 736         htotal = adjusted_mode->crtc_htotal;
 737         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 738         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 739
 740         /* Use the small buffer method to calculate plane watermark */
 741         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 742         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 743         if (tlb_miss > 0)
 744                 entries += tlb_miss;
 745         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 746         *plane_wm = entries + display->guard_size;
 747         if (*plane_wm > (int)display->max_wm)
 748                 *plane_wm = display->max_wm;
 749
 750         /* Use the large buffer method to calculate cursor watermark */
 751         line_time_us = max(htotal * 1000 / clock, 1);
 752         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 753         entries = line_count * crtc->cursor->state->crtc_w * cpp;
 754         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 755         if (tlb_miss > 0)
 756                 entries += tlb_miss;
 757         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 758         *cursor_wm = entries + cursor->guard_size;
 759         if (*cursor_wm > (int)cursor->max_wm)
 760                 *cursor_wm = (int)cursor->max_wm;
 761
 762         return true;
 763 }
 764
 765 /*
 766  * Check the wm result.
 767  *
 768  * If any calculated watermark values is larger than the maximum value that
 769  * can be programmed into the associated watermark register, that watermark
 770  * must be disabled.
 771  */
 772 static bool g4x_check_srwm(struct drm_device *dev,
 773                            int display_wm, int cursor_wm,
 774                            const struct intel_watermark_params *display,
 775                            const struct intel_watermark_params *cursor)
 776 {
 777         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 778                       display_wm, cursor_wm);
 779
 780         if (display_wm > display->max_wm) {
 781                 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
 782                               display_wm, display->max_wm);
 783                 return false;
 784         }
 785
 786         if (cursor_wm > cursor->max_wm) {
 787                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
 788                               cursor_wm, cursor->max_wm);
 789                 return false;
 790         }
 791
 792         if (!(display_wm || cursor_wm)) {
 793                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 794                 return false;
 795         }
 796
 797         return true;
 798 }
 799
 800 static bool g4x_compute_srwm(struct drm_device *dev,
 801                              int plane,
 802                              int latency_ns,
 803                              const struct intel_watermark_params *display,
 804                              const struct intel_watermark_params *cursor,
 805                              int *display_wm, int *cursor_wm)
 806 {
 807         struct drm_crtc *crtc;
 808         const struct drm_display_mode *adjusted_mode;
 809         int hdisplay, htotal, cpp, clock;
 810         unsigned long line_time_us;
 811         int line_count, line_size;
 812         int small, large;
 813         int entries;
 814
 815         if (!latency_ns) {
 816                 *display_wm = *cursor_wm = 0;
 817                 return false;
 818         }
 819
 820         crtc = intel_get_crtc_for_plane(dev, plane);
 821         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 822         clock = adjusted_mode->crtc_clock;
 823         htotal = adjusted_mode->crtc_htotal;
 824         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 825         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 826
 827         line_time_us = max(htotal * 1000 / clock, 1);
 828         line_count = (latency_ns / line_time_us + 1000) / 1000;
 829         line_size = hdisplay * cpp;
 830
 831         /* Use the minimum of the small and large buffer method for primary */
 832         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 833         large = line_count * line_size;
 834
 835         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 836         *display_wm = entries + display->guard_size;
 837
 838         /* calculate the self-refresh watermark for display cursor */
 839         entries = line_count * cpp * crtc->cursor->state->crtc_w;
 840         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 841         *cursor_wm = entries + cursor->guard_size;
 842
 843         return g4x_check_srwm(dev,
 844                               *display_wm, *cursor_wm,
 845                               display, cursor);
 846 }
 847
 848 #define FW_WM_VLV(value, plane) \
 849         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 850
 851 static void vlv_write_wm_values(struct intel_crtc *crtc,
 852                                 const struct vlv_wm_values *wm)
 853 {
 854         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 855         enum pipe pipe = crtc->pipe;
 856
 857         I915_WRITE(VLV_DDL(pipe),
 858                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 859                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 860                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 861                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 862
 863         I915_WRITE(DSPFW1,
 864                    FW_WM(wm->sr.plane, SR) |
 865                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 866                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 867                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 868         I915_WRITE(DSPFW2,
 869                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 870                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 871                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 872         I915_WRITE(DSPFW3,
 873                    FW_WM(wm->sr.cursor, CURSOR_SR));
 874
 875         if (IS_CHERRYVIEW(dev_priv)) {
 876                 I915_WRITE(DSPFW7_CHV,
 877                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 878                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 879                 I915_WRITE(DSPFW8_CHV,
 880                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 881                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 882                 I915_WRITE(DSPFW9_CHV,
 883                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 884                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 885                 I915_WRITE(DSPHOWM,
 886                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 887                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 888                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 889                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 890                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 891                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 892                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 893                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 894                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 895                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 896         } else {
 897                 I915_WRITE(DSPFW7,
 898                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 899                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 900                 I915_WRITE(DSPHOWM,
 901                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 902                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 903                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 904                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 905                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 906                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 907                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 908         }
 909
 910         /* zero (unused) WM1 watermarks */
 911         I915_WRITE(DSPFW4, 0);
 912         I915_WRITE(DSPFW5, 0);
 913         I915_WRITE(DSPFW6, 0);
 914         I915_WRITE(DSPHOWM1, 0);
 915
 916         POSTING_READ(DSPFW1);
 917 }
 918
 919 #undef FW_WM_VLV
 920
 921 enum vlv_wm_level {
 922         VLV_WM_LEVEL_PM2,
 923         VLV_WM_LEVEL_PM5,
 924         VLV_WM_LEVEL_DDR_DVFS,
 925 };
 926
 927 /* latency must be in 0.1us units. */
 928 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 929                                    unsigned int pipe_htotal,
 930                                    unsigned int horiz_pixels,
 931                                    unsigned int cpp,
 932                                    unsigned int latency)
 933 {
 934         unsigned int ret;
 935
 936         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 937         ret = (ret + 1) * horiz_pixels * cpp;
 938         ret = DIV_ROUND_UP(ret, 64);
 939
 940         return ret;
 941 }
 942
 943 static void vlv_setup_wm_latency(struct drm_device *dev)
 944 {
 945         struct drm_i915_private *dev_priv = to_i915(dev);
 946
 947         /* all latencies in usec */
 948         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 949
 950         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 951
 952         if (IS_CHERRYVIEW(dev_priv)) {
 953                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 954                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 955
 956                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 957         }
 958 }
 959
 960 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 961                                      struct intel_crtc *crtc,
 962                                      const struct intel_plane_state *state,
 963                                      int level)
 964 {
 965         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 966         int clock, htotal, cpp, width, wm;
 967
 968         if (dev_priv->wm.pri_latency[level] == 0)
 969                 return USHRT_MAX;
 970
 971         if (!state->base.visible)
 972                 return 0;
 973
 974         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 975         clock = crtc->config->base.adjusted_mode.crtc_clock;
 976         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 977         width = crtc->config->pipe_src_w;
 978         if (WARN_ON(htotal == 0))
 979                 htotal = 1;
 980
 981         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 982                 /*
 983                  * FIXME the formula gives values that are
 984                  * too big for the cursor FIFO, and hence we
 985                  * would never be able to use cursors. For
 986                  * now just hardcode the watermark.
 987                  */
 988                 wm = 63;
 989         } else {
 990                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 991                                     dev_priv->wm.pri_latency[level] * 10);
 992         }
 993
 994         return min_t(int, wm, USHRT_MAX);
 995 }
 996
 997 static void vlv_compute_fifo(struct intel_crtc *crtc)
 998 {
 999         struct drm_device *dev = crtc->base.dev;
1000         struct vlv_wm_state *wm_state = &crtc->wm_state;
1001         struct intel_plane *plane;
1002         unsigned int total_rate = 0;
1003         const int fifo_size = 512 - 1;
1004         int fifo_extra, fifo_left = fifo_size;
1005
1006         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1007                 struct intel_plane_state *state =
1008                         to_intel_plane_state(plane->base.state);
1009
1010                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1011                         continue;
1012
1013                 if (state->base.visible) {
1014                         wm_state->num_active_planes++;
1015                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1016                 }
1017         }
1018
1019         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1020                 struct intel_plane_state *state =
1021                         to_intel_plane_state(plane->base.state);
1022                 unsigned int rate;
1023
1024                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1025                         plane->wm.fifo_size = 63;
1026                         continue;
1027                 }
1028
1029                 if (!state->base.visible) {
1030                         plane->wm.fifo_size = 0;
1031                         continue;
1032                 }
1033
1034                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1035                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1036                 fifo_left -= plane->wm.fifo_size;
1037         }
1038
1039         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1040
1041         /* spread the remainder evenly */
1042         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1043                 int plane_extra;
1044
1045                 if (fifo_left == 0)
1046                         break;
1047
1048                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1049                         continue;
1050
1051                 /* give it all to the first plane if none are active */
1052                 if (plane->wm.fifo_size == 0 &&
1053                     wm_state->num_active_planes)
1054                         continue;
1055
1056                 plane_extra = min(fifo_extra, fifo_left);
1057                 plane->wm.fifo_size += plane_extra;
1058                 fifo_left -= plane_extra;
1059         }
1060
1061         WARN_ON(fifo_left != 0);
1062 }
1063
1064 static void vlv_invert_wms(struct intel_crtc *crtc)
1065 {
1066         struct vlv_wm_state *wm_state = &crtc->wm_state;
1067         int level;
1068
1069         for (level = 0; level < wm_state->num_levels; level++) {
1070                 struct drm_device *dev = crtc->base.dev;
1071                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1072                 struct intel_plane *plane;
1073
1074                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1075                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1076
1077                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1078                         switch (plane->base.type) {
1079                                 int sprite;
1080                         case DRM_PLANE_TYPE_CURSOR:
1081                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1082                                         wm_state->wm[level].cursor;
1083                                 break;
1084                         case DRM_PLANE_TYPE_PRIMARY:
1085                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1086                                         wm_state->wm[level].primary;
1087                                 break;
1088                         case DRM_PLANE_TYPE_OVERLAY:
1089                                 sprite = plane->plane;
1090                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1091                                         wm_state->wm[level].sprite[sprite];
1092                                 break;
1093                         }
1094                 }
1095         }
1096 }
1097
1098 static void vlv_compute_wm(struct intel_crtc *crtc)
1099 {
1100         struct drm_device *dev = crtc->base.dev;
1101         struct vlv_wm_state *wm_state = &crtc->wm_state;
1102         struct intel_plane *plane;
1103         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1104         int level;
1105
1106         memset(wm_state, 0, sizeof(*wm_state));
1107
1108         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1109         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1110
1111         wm_state->num_active_planes = 0;
1112
1113         vlv_compute_fifo(crtc);
1114
1115         if (wm_state->num_active_planes != 1)
1116                 wm_state->cxsr = false;
1117
1118         if (wm_state->cxsr) {
1119                 for (level = 0; level < wm_state->num_levels; level++) {
1120                         wm_state->sr[level].plane = sr_fifo_size;
1121                         wm_state->sr[level].cursor = 63;
1122                 }
1123         }
1124
1125         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1126                 struct intel_plane_state *state =
1127                         to_intel_plane_state(plane->base.state);
1128
1129                 if (!state->base.visible)
1130                         continue;
1131
1132                 /* normal watermarks */
1133                 for (level = 0; level < wm_state->num_levels; level++) {
1134                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1135                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1136
1137                         /* hack */
1138                         if (WARN_ON(level == 0 && wm > max_wm))
1139                                 wm = max_wm;
1140
1141                         if (wm > plane->wm.fifo_size)
1142                                 break;
1143
1144                         switch (plane->base.type) {
1145                                 int sprite;
1146                         case DRM_PLANE_TYPE_CURSOR:
1147                                 wm_state->wm[level].cursor = wm;
1148                                 break;
1149                         case DRM_PLANE_TYPE_PRIMARY:
1150                                 wm_state->wm[level].primary = wm;
1151                                 break;
1152                         case DRM_PLANE_TYPE_OVERLAY:
1153                                 sprite = plane->plane;
1154                                 wm_state->wm[level].sprite[sprite] = wm;
1155                                 break;
1156                         }
1157                 }
1158
1159                 wm_state->num_levels = level;
1160
1161                 if (!wm_state->cxsr)
1162                         continue;
1163
1164                 /* maxfifo watermarks */
1165                 switch (plane->base.type) {
1166                         int sprite, level;
1167                 case DRM_PLANE_TYPE_CURSOR:
1168                         for (level = 0; level < wm_state->num_levels; level++)
1169                                 wm_state->sr[level].cursor =
1170                                         wm_state->wm[level].cursor;
1171                         break;
1172                 case DRM_PLANE_TYPE_PRIMARY:
1173                         for (level = 0; level < wm_state->num_levels; level++)
1174                                 wm_state->sr[level].plane =
1175                                         min(wm_state->sr[level].plane,
1176                                             wm_state->wm[level].primary);
1177                         break;
1178                 case DRM_PLANE_TYPE_OVERLAY:
1179                         sprite = plane->plane;
1180                         for (level = 0; level < wm_state->num_levels; level++)
1181                                 wm_state->sr[level].plane =
1182                                         min(wm_state->sr[level].plane,
1183                                             wm_state->wm[level].sprite[sprite]);
1184                         break;
1185                 }
1186         }
1187
1188         /* clear any (partially) filled invalid levels */
1189         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1190                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1191                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1192         }
1193
1194         vlv_invert_wms(crtc);
1195 }
1196
1197 #define VLV_FIFO(plane, value) \
1198         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1199
1200 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1201 {
1202         struct drm_device *dev = crtc->base.dev;
1203         struct drm_i915_private *dev_priv = to_i915(dev);
1204         struct intel_plane *plane;
1205         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1206
1207         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1208                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1209                         WARN_ON(plane->wm.fifo_size != 63);
1210                         continue;
1211                 }
1212
1213                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1214                         sprite0_start = plane->wm.fifo_size;
1215                 else if (plane->plane == 0)
1216                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1217                 else
1218                         fifo_size = sprite1_start + plane->wm.fifo_size;
1219         }
1220
1221         WARN_ON(fifo_size != 512 - 1);
1222
1223         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1224                       pipe_name(crtc->pipe), sprite0_start,
1225                       sprite1_start, fifo_size);
1226
1227         switch (crtc->pipe) {
1228                 uint32_t dsparb, dsparb2, dsparb3;
1229         case PIPE_A:
1230                 dsparb = I915_READ(DSPARB);
1231                 dsparb2 = I915_READ(DSPARB2);
1232
1233                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1234                             VLV_FIFO(SPRITEB, 0xff));
1235                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1236                            VLV_FIFO(SPRITEB, sprite1_start));
1237
1238                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1239                              VLV_FIFO(SPRITEB_HI, 0x1));
1240                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1241                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1242
1243                 I915_WRITE(DSPARB, dsparb);
1244                 I915_WRITE(DSPARB2, dsparb2);
1245                 break;
1246         case PIPE_B:
1247                 dsparb = I915_READ(DSPARB);
1248                 dsparb2 = I915_READ(DSPARB2);
1249
1250                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1251                             VLV_FIFO(SPRITED, 0xff));
1252                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1253                            VLV_FIFO(SPRITED, sprite1_start));
1254
1255                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1256                              VLV_FIFO(SPRITED_HI, 0xff));
1257                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1258                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1259
1260                 I915_WRITE(DSPARB, dsparb);
1261                 I915_WRITE(DSPARB2, dsparb2);
1262                 break;
1263         case PIPE_C:
1264                 dsparb3 = I915_READ(DSPARB3);
1265                 dsparb2 = I915_READ(DSPARB2);
1266
1267                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1268                              VLV_FIFO(SPRITEF, 0xff));
1269                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1270                             VLV_FIFO(SPRITEF, sprite1_start));
1271
1272                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1273                              VLV_FIFO(SPRITEF_HI, 0xff));
1274                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1275                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1276
1277                 I915_WRITE(DSPARB3, dsparb3);
1278                 I915_WRITE(DSPARB2, dsparb2);
1279                 break;
1280         default:
1281                 break;
1282         }
1283 }
1284
1285 #undef VLV_FIFO
1286
1287 static void vlv_merge_wm(struct drm_device *dev,
1288                          struct vlv_wm_values *wm)
1289 {
1290         struct intel_crtc *crtc;
1291         int num_active_crtcs = 0;
1292
1293         wm->level = to_i915(dev)->wm.max_level;
1294         wm->cxsr = true;
1295
1296         for_each_intel_crtc(dev, crtc) {
1297                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1298
1299                 if (!crtc->active)
1300                         continue;
1301
1302                 if (!wm_state->cxsr)
1303                         wm->cxsr = false;
1304
1305                 num_active_crtcs++;
1306                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1307         }
1308
1309         if (num_active_crtcs != 1)
1310                 wm->cxsr = false;
1311
1312         if (num_active_crtcs > 1)
1313                 wm->level = VLV_WM_LEVEL_PM2;
1314
1315         for_each_intel_crtc(dev, crtc) {
1316                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1317                 enum pipe pipe = crtc->pipe;
1318
1319                 if (!crtc->active)
1320                         continue;
1321
1322                 wm->pipe[pipe] = wm_state->wm[wm->level];
1323                 if (wm->cxsr)
1324                         wm->sr = wm_state->sr[wm->level];
1325
1326                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1327                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1328                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1329                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1330         }
1331 }
1332
1333 static void vlv_update_wm(struct drm_crtc *crtc)
1334 {
1335         struct drm_device *dev = crtc->dev;
1336         struct drm_i915_private *dev_priv = to_i915(dev);
1337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1338         enum pipe pipe = intel_crtc->pipe;
1339         struct vlv_wm_values wm = {};
1340
1341         vlv_compute_wm(intel_crtc);
1342         vlv_merge_wm(dev, &wm);
1343
1344         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1345                 /* FIXME should be part of crtc atomic commit */
1346                 vlv_pipe_set_fifo_size(intel_crtc);
1347                 return;
1348         }
1349
1350         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1351             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1352                 chv_set_memory_dvfs(dev_priv, false);
1353
1354         if (wm.level < VLV_WM_LEVEL_PM5 &&
1355             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1356                 chv_set_memory_pm5(dev_priv, false);
1357
1358         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1359                 intel_set_memory_cxsr(dev_priv, false);
1360
1361         /* FIXME should be part of crtc atomic commit */
1362         vlv_pipe_set_fifo_size(intel_crtc);
1363
1364         vlv_write_wm_values(intel_crtc, &wm);
1365
1366         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1367                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1368                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1369                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1370                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1371
1372         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1373                 intel_set_memory_cxsr(dev_priv, true);
1374
1375         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1376             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1377                 chv_set_memory_pm5(dev_priv, true);
1378
1379         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1380             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1381                 chv_set_memory_dvfs(dev_priv, true);
1382
1383         dev_priv->wm.vlv = wm;
1384 }
1385
1386 #define single_plane_enabled(mask) is_power_of_2(mask)
1387
1388 static void g4x_update_wm(struct drm_crtc *crtc)
1389 {
1390         struct drm_device *dev = crtc->dev;
1391         static const int sr_latency_ns = 12000;
1392         struct drm_i915_private *dev_priv = to_i915(dev);
1393         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1394         int plane_sr, cursor_sr;
1395         unsigned int enabled = 0;
1396         bool cxsr_enabled;
1397
1398         if (g4x_compute_wm0(dev, PIPE_A,
1399                             &g4x_wm_info, pessimal_latency_ns,
1400                             &g4x_cursor_wm_info, pessimal_latency_ns,
1401                             &planea_wm, &cursora_wm))
1402                 enabled |= 1 << PIPE_A;
1403
1404         if (g4x_compute_wm0(dev, PIPE_B,
1405                             &g4x_wm_info, pessimal_latency_ns,
1406                             &g4x_cursor_wm_info, pessimal_latency_ns,
1407                             &planeb_wm, &cursorb_wm))
1408                 enabled |= 1 << PIPE_B;
1409
1410         if (single_plane_enabled(enabled) &&
1411             g4x_compute_srwm(dev, ffs(enabled) - 1,
1412                              sr_latency_ns,
1413                              &g4x_wm_info,
1414                              &g4x_cursor_wm_info,
1415                              &plane_sr, &cursor_sr)) {
1416                 cxsr_enabled = true;
1417         } else {
1418                 cxsr_enabled = false;
1419                 intel_set_memory_cxsr(dev_priv, false);
1420                 plane_sr = cursor_sr = 0;
1421         }
1422
1423         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1424                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1425                       planea_wm, cursora_wm,
1426                       planeb_wm, cursorb_wm,
1427                       plane_sr, cursor_sr);
1428
1429         I915_WRITE(DSPFW1,
1430                    FW_WM(plane_sr, SR) |
1431                    FW_WM(cursorb_wm, CURSORB) |
1432                    FW_WM(planeb_wm, PLANEB) |
1433                    FW_WM(planea_wm, PLANEA));
1434         I915_WRITE(DSPFW2,
1435                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1436                    FW_WM(cursora_wm, CURSORA));
1437         /* HPLL off in SR has some issues on G4x... disable it */
1438         I915_WRITE(DSPFW3,
1439                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1440                    FW_WM(cursor_sr, CURSOR_SR));
1441
1442         if (cxsr_enabled)
1443                 intel_set_memory_cxsr(dev_priv, true);
1444 }
1445
1446 static void i965_update_wm(struct drm_crtc *unused_crtc)
1447 {
1448         struct drm_device *dev = unused_crtc->dev;
1449         struct drm_i915_private *dev_priv = to_i915(dev);
1450         struct drm_crtc *crtc;
1451         int srwm = 1;
1452         int cursor_sr = 16;
1453         bool cxsr_enabled;
1454
1455         /* Calc sr entries for one plane configs */
1456         crtc = single_enabled_crtc(dev);
1457         if (crtc) {
1458                 /* self-refresh has much higher latency */
1459                 static const int sr_latency_ns = 12000;
1460                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1461                 int clock = adjusted_mode->crtc_clock;
1462                 int htotal = adjusted_mode->crtc_htotal;
1463                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1464                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1465                 unsigned long line_time_us;
1466                 int entries;
1467
1468                 line_time_us = max(htotal * 1000 / clock, 1);
1469
1470                 /* Use ns/us then divide to preserve precision */
1471                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1472                         cpp * hdisplay;
1473                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1474                 srwm = I965_FIFO_SIZE - entries;
1475                 if (srwm < 0)
1476                         srwm = 1;
1477                 srwm &= 0x1ff;
1478                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1479                               entries, srwm);
1480
1481                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1482                         cpp * crtc->cursor->state->crtc_w;
1483                 entries = DIV_ROUND_UP(entries,
1484                                           i965_cursor_wm_info.cacheline_size);
1485                 cursor_sr = i965_cursor_wm_info.fifo_size -
1486                         (entries + i965_cursor_wm_info.guard_size);
1487
1488                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1489                         cursor_sr = i965_cursor_wm_info.max_wm;
1490
1491                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1492                               "cursor %d\n", srwm, cursor_sr);
1493
1494                 cxsr_enabled = true;
1495         } else {
1496                 cxsr_enabled = false;
1497                 /* Turn off self refresh if both pipes are enabled */
1498                 intel_set_memory_cxsr(dev_priv, false);
1499         }
1500
1501         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1502                       srwm);
1503
1504         /* 965 has limitations... */
1505         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1506                    FW_WM(8, CURSORB) |
1507                    FW_WM(8, PLANEB) |
1508                    FW_WM(8, PLANEA));
1509         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1510                    FW_WM(8, PLANEC_OLD));
1511         /* update cursor SR watermark */
1512         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1513
1514         if (cxsr_enabled)
1515                 intel_set_memory_cxsr(dev_priv, true);
1516 }
1517
1518 #undef FW_WM
1519
1520 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1521 {
1522         struct drm_device *dev = unused_crtc->dev;
1523         struct drm_i915_private *dev_priv = to_i915(dev);
1524         const struct intel_watermark_params *wm_info;
1525         uint32_t fwater_lo;
1526         uint32_t fwater_hi;
1527         int cwm, srwm = 1;
1528         int fifo_size;
1529         int planea_wm, planeb_wm;
1530         struct drm_crtc *crtc, *enabled = NULL;
1531
1532         if (IS_I945GM(dev))
1533                 wm_info = &i945_wm_info;
1534         else if (!IS_GEN2(dev_priv))
1535                 wm_info = &i915_wm_info;
1536         else
1537                 wm_info = &i830_a_wm_info;
1538
1539         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1540         crtc = intel_get_crtc_for_plane(dev, 0);
1541         if (intel_crtc_active(crtc)) {
1542                 const struct drm_display_mode *adjusted_mode;
1543                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1544                 if (IS_GEN2(dev_priv))
1545                         cpp = 4;
1546
1547                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1548                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1549                                                wm_info, fifo_size, cpp,
1550                                                pessimal_latency_ns);
1551                 enabled = crtc;
1552         } else {
1553                 planea_wm = fifo_size - wm_info->guard_size;
1554                 if (planea_wm > (long)wm_info->max_wm)
1555                         planea_wm = wm_info->max_wm;
1556         }
1557
1558         if (IS_GEN2(dev_priv))
1559                 wm_info = &i830_bc_wm_info;
1560
1561         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1562         crtc = intel_get_crtc_for_plane(dev, 1);
1563         if (intel_crtc_active(crtc)) {
1564                 const struct drm_display_mode *adjusted_mode;
1565                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1566                 if (IS_GEN2(dev_priv))
1567                         cpp = 4;
1568
1569                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1570                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1571                                                wm_info, fifo_size, cpp,
1572                                                pessimal_latency_ns);
1573                 if (enabled == NULL)
1574                         enabled = crtc;
1575                 else
1576                         enabled = NULL;
1577         } else {
1578                 planeb_wm = fifo_size - wm_info->guard_size;
1579                 if (planeb_wm > (long)wm_info->max_wm)
1580                         planeb_wm = wm_info->max_wm;
1581         }
1582
1583         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1584
1585         if (IS_I915GM(dev_priv) && enabled) {
1586                 struct drm_i915_gem_object *obj;
1587
1588                 obj = intel_fb_obj(enabled->primary->state->fb);
1589
1590                 /* self-refresh seems busted with untiled */
1591                 if (!i915_gem_object_is_tiled(obj))
1592                         enabled = NULL;
1593         }
1594
1595         /*
1596          * Overlay gets an aggressive default since video jitter is bad.
1597          */
1598         cwm = 2;
1599
1600         /* Play safe and disable self-refresh before adjusting watermarks. */
1601         intel_set_memory_cxsr(dev_priv, false);
1602
1603         /* Calc sr entries for one plane configs */
1604         if (HAS_FW_BLC(dev) && enabled) {
1605                 /* self-refresh has much higher latency */
1606                 static const int sr_latency_ns = 6000;
1607                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1608                 int clock = adjusted_mode->crtc_clock;
1609                 int htotal = adjusted_mode->crtc_htotal;
1610                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1611                 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1612                 unsigned long line_time_us;
1613                 int entries;
1614
1615                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
1616                         cpp = 4;
1617
1618                 line_time_us = max(htotal * 1000 / clock, 1);
1619
1620                 /* Use ns/us then divide to preserve precision */
1621                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1622                         cpp * hdisplay;
1623                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1624                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1625                 srwm = wm_info->fifo_size - entries;
1626                 if (srwm < 0)
1627                         srwm = 1;
1628
1629                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1630                         I915_WRITE(FW_BLC_SELF,
1631                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1632                 else
1633                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1634         }
1635
1636         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1637                       planea_wm, planeb_wm, cwm, srwm);
1638
1639         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1640         fwater_hi = (cwm & 0x1f);
1641
1642         /* Set request length to 8 cachelines per fetch */
1643         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1644         fwater_hi = fwater_hi | (1 << 8);
1645
1646         I915_WRITE(FW_BLC, fwater_lo);
1647         I915_WRITE(FW_BLC2, fwater_hi);
1648
1649         if (enabled)
1650                 intel_set_memory_cxsr(dev_priv, true);
1651 }
1652
1653 static void i845_update_wm(struct drm_crtc *unused_crtc)
1654 {
1655         struct drm_device *dev = unused_crtc->dev;
1656         struct drm_i915_private *dev_priv = to_i915(dev);
1657         struct drm_crtc *crtc;
1658         const struct drm_display_mode *adjusted_mode;
1659         uint32_t fwater_lo;
1660         int planea_wm;
1661
1662         crtc = single_enabled_crtc(dev);
1663         if (crtc == NULL)
1664                 return;
1665
1666         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1667         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1668                                        &i845_wm_info,
1669                                        dev_priv->display.get_fifo_size(dev, 0),
1670                                        4, pessimal_latency_ns);
1671         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1672         fwater_lo |= (3<<8) | planea_wm;
1673
1674         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1675
1676         I915_WRITE(FW_BLC, fwater_lo);
1677 }
1678
1679 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1680 {
1681         uint32_t pixel_rate;
1682
1683         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1684
1685         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1686          * adjust the pixel_rate here. */
1687
1688         if (pipe_config->pch_pfit.enabled) {
1689                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1690                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1691
1692                 pipe_w = pipe_config->pipe_src_w;
1693                 pipe_h = pipe_config->pipe_src_h;
1694
1695                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1696                 pfit_h = pfit_size & 0xFFFF;
1697                 if (pipe_w < pfit_w)
1698                         pipe_w = pfit_w;
1699                 if (pipe_h < pfit_h)
1700                         pipe_h = pfit_h;
1701
1702                 if (WARN_ON(!pfit_w || !pfit_h))
1703                         return pixel_rate;
1704
1705                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1706                                      pfit_w * pfit_h);
1707         }
1708
1709         return pixel_rate;
1710 }
1711
1712 /* latency must be in 0.1us units. */
1713 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1714 {
1715         uint64_t ret;
1716
1717         if (WARN(latency == 0, "Latency value missing\n"))
1718                 return UINT_MAX;
1719
1720         ret = (uint64_t) pixel_rate * cpp * latency;
1721         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1722
1723         return ret;
1724 }
1725
1726 /* latency must be in 0.1us units. */
1727 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1728                                uint32_t horiz_pixels, uint8_t cpp,
1729                                uint32_t latency)
1730 {
1731         uint32_t ret;
1732
1733         if (WARN(latency == 0, "Latency value missing\n"))
1734                 return UINT_MAX;
1735         if (WARN_ON(!pipe_htotal))
1736                 return UINT_MAX;
1737
1738         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1739         ret = (ret + 1) * horiz_pixels * cpp;
1740         ret = DIV_ROUND_UP(ret, 64) + 2;
1741         return ret;
1742 }
1743
1744 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1745                            uint8_t cpp)
1746 {
1747         /*
1748          * Neither of these should be possible since this function shouldn't be
1749          * called if the CRTC is off or the plane is invisible.  But let's be
1750          * extra paranoid to avoid a potential divide-by-zero if we screw up
1751          * elsewhere in the driver.
1752          */
1753         if (WARN_ON(!cpp))
1754                 return 0;
1755         if (WARN_ON(!horiz_pixels))
1756                 return 0;
1757
1758         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1759 }
1760
1761 struct ilk_wm_maximums {
1762         uint16_t pri;
1763         uint16_t spr;
1764         uint16_t cur;
1765         uint16_t fbc;
1766 };
1767
1768 /*
1769  * For both WM_PIPE and WM_LP.
1770  * mem_value must be in 0.1us units.
1771  */
1772 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1773                                    const struct intel_plane_state *pstate,
1774                                    uint32_t mem_value,
1775                                    bool is_lp)
1776 {
1777         int cpp = pstate->base.fb ?
1778                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1779         uint32_t method1, method2;
1780
1781         if (!cstate->base.active || !pstate->base.visible)
1782                 return 0;
1783
1784         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1785
1786         if (!is_lp)
1787                 return method1;
1788
1789         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1790                                  cstate->base.adjusted_mode.crtc_htotal,
1791                                  drm_rect_width(&pstate->base.dst),
1792                                  cpp, mem_value);
1793
1794         return min(method1, method2);
1795 }
1796
1797 /*
1798  * For both WM_PIPE and WM_LP.
1799  * mem_value must be in 0.1us units.
1800  */
1801 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1802                                    const struct intel_plane_state *pstate,
1803                                    uint32_t mem_value)
1804 {
1805         int cpp = pstate->base.fb ?
1806                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1807         uint32_t method1, method2;
1808
1809         if (!cstate->base.active || !pstate->base.visible)
1810                 return 0;
1811
1812         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1813         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1814                                  cstate->base.adjusted_mode.crtc_htotal,
1815                                  drm_rect_width(&pstate->base.dst),
1816                                  cpp, mem_value);
1817         return min(method1, method2);
1818 }
1819
1820 /*
1821  * For both WM_PIPE and WM_LP.
1822  * mem_value must be in 0.1us units.
1823  */
1824 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1825                                    const struct intel_plane_state *pstate,
1826                                    uint32_t mem_value)
1827 {
1828         /*
1829          * We treat the cursor plane as always-on for the purposes of watermark
1830          * calculation.  Until we have two-stage watermark programming merged,
1831          * this is necessary to avoid flickering.
1832          */
1833         int cpp = 4;
1834         int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1835
1836         if (!cstate->base.active)
1837                 return 0;
1838
1839         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1840                               cstate->base.adjusted_mode.crtc_htotal,
1841                               width, cpp, mem_value);
1842 }
1843
1844 /* Only for WM_LP. */
1845 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1846                                    const struct intel_plane_state *pstate,
1847                                    uint32_t pri_val)
1848 {
1849         int cpp = pstate->base.fb ?
1850                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1851
1852         if (!cstate->base.active || !pstate->base.visible)
1853                 return 0;
1854
1855         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1856 }
1857
1858 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1859 {
1860         if (INTEL_INFO(dev)->gen >= 8)
1861                 return 3072;
1862         else if (INTEL_INFO(dev)->gen >= 7)
1863                 return 768;
1864         else
1865                 return 512;
1866 }
1867
1868 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1869                                          int level, bool is_sprite)
1870 {
1871         if (INTEL_INFO(dev)->gen >= 8)
1872                 /* BDW primary/sprite plane watermarks */
1873                 return level == 0 ? 255 : 2047;
1874         else if (INTEL_INFO(dev)->gen >= 7)
1875                 /* IVB/HSW primary/sprite plane watermarks */
1876                 return level == 0 ? 127 : 1023;
1877         else if (!is_sprite)
1878                 /* ILK/SNB primary plane watermarks */
1879                 return level == 0 ? 127 : 511;
1880         else
1881                 /* ILK/SNB sprite plane watermarks */
1882                 return level == 0 ? 63 : 255;
1883 }
1884
1885 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1886                                           int level)
1887 {
1888         if (INTEL_INFO(dev)->gen >= 7)
1889                 return level == 0 ? 63 : 255;
1890         else
1891                 return level == 0 ? 31 : 63;
1892 }
1893
1894 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1895 {
1896         if (INTEL_INFO(dev)->gen >= 8)
1897                 return 31;
1898         else
1899                 return 15;
1900 }
1901
1902 /* Calculate the maximum primary/sprite plane watermark */
1903 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1904                                      int level,
1905                                      const struct intel_wm_config *config,
1906                                      enum intel_ddb_partitioning ddb_partitioning,
1907                                      bool is_sprite)
1908 {
1909         unsigned int fifo_size = ilk_display_fifo_size(dev);
1910
1911         /* if sprites aren't enabled, sprites get nothing */
1912         if (is_sprite && !config->sprites_enabled)
1913                 return 0;
1914
1915         /* HSW allows LP1+ watermarks even with multiple pipes */
1916         if (level == 0 || config->num_pipes_active > 1) {
1917                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1918
1919                 /*
1920                  * For some reason the non self refresh
1921                  * FIFO size is only half of the self
1922                  * refresh FIFO size on ILK/SNB.
1923                  */
1924                 if (INTEL_INFO(dev)->gen <= 6)
1925                         fifo_size /= 2;
1926         }
1927
1928         if (config->sprites_enabled) {
1929                 /* level 0 is always calculated with 1:1 split */
1930                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1931                         if (is_sprite)
1932                                 fifo_size *= 5;
1933                         fifo_size /= 6;
1934                 } else {
1935                         fifo_size /= 2;
1936                 }
1937         }
1938
1939         /* clamp to max that the registers can hold */
1940         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1941 }
1942
1943 /* Calculate the maximum cursor plane watermark */
1944 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1945                                       int level,
1946                                       const struct intel_wm_config *config)
1947 {
1948         /* HSW LP1+ watermarks w/ multiple pipes */
1949         if (level > 0 && config->num_pipes_active > 1)
1950                 return 64;
1951
1952         /* otherwise just report max that registers can hold */
1953         return ilk_cursor_wm_reg_max(dev, level);
1954 }
1955
1956 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1957                                     int level,
1958                                     const struct intel_wm_config *config,
1959                                     enum intel_ddb_partitioning ddb_partitioning,
1960                                     struct ilk_wm_maximums *max)
1961 {
1962         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1963         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1964         max->cur = ilk_cursor_wm_max(dev, level, config);
1965         max->fbc = ilk_fbc_wm_reg_max(dev);
1966 }
1967
1968 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1969                                         int level,
1970                                         struct ilk_wm_maximums *max)
1971 {
1972         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1973         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1974         max->cur = ilk_cursor_wm_reg_max(dev, level);
1975         max->fbc = ilk_fbc_wm_reg_max(dev);
1976 }
1977
1978 static bool ilk_validate_wm_level(int level,
1979                                   const struct ilk_wm_maximums *max,
1980                                   struct intel_wm_level *result)
1981 {
1982         bool ret;
1983
1984         /* already determined to be invalid? */
1985         if (!result->enable)
1986                 return false;
1987
1988         result->enable = result->pri_val <= max->pri &&
1989                          result->spr_val <= max->spr &&
1990                          result->cur_val <= max->cur;
1991
1992         ret = result->enable;
1993
1994         /*
1995          * HACK until we can pre-compute everything,
1996          * and thus fail gracefully if LP0 watermarks
1997          * are exceeded...
1998          */
1999         if (level == 0 && !result->enable) {
2000                 if (result->pri_val > max->pri)
2001                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2002                                       level, result->pri_val, max->pri);
2003                 if (result->spr_val > max->spr)
2004                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2005                                       level, result->spr_val, max->spr);
2006                 if (result->cur_val > max->cur)
2007                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2008                                       level, result->cur_val, max->cur);
2009
2010                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2011                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2012                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2013                 result->enable = true;
2014         }
2015
2016         return ret;
2017 }
2018
2019 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2020                                  const struct intel_crtc *intel_crtc,
2021                                  int level,
2022                                  struct intel_crtc_state *cstate,
2023                                  struct intel_plane_state *pristate,
2024                                  struct intel_plane_state *sprstate,
2025                                  struct intel_plane_state *curstate,
2026                                  struct intel_wm_level *result)
2027 {
2028         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2029         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2030         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2031
2032         /* WM1+ latency values stored in 0.5us units */
2033         if (level > 0) {
2034                 pri_latency *= 5;
2035                 spr_latency *= 5;
2036                 cur_latency *= 5;
2037         }
2038
2039         if (pristate) {
2040                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2041                                                      pri_latency, level);
2042                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2043         }
2044
2045         if (sprstate)
2046                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2047
2048         if (curstate)
2049                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2050
2051         result->enable = true;
2052 }
2053
2054 static uint32_t
2055 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2056 {
2057         const struct intel_atomic_state *intel_state =
2058                 to_intel_atomic_state(cstate->base.state);
2059         const struct drm_display_mode *adjusted_mode =
2060                 &cstate->base.adjusted_mode;
2061         u32 linetime, ips_linetime;
2062
2063         if (!cstate->base.active)
2064                 return 0;
2065         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2066                 return 0;
2067         if (WARN_ON(intel_state->cdclk == 0))
2068                 return 0;
2069
2070         /* The WM are computed with base on how long it takes to fill a single
2071          * row at the given clock rate, multiplied by 8.
2072          * */
2073         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2074                                      adjusted_mode->crtc_clock);
2075         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2076                                          intel_state->cdclk);
2077
2078         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2079                PIPE_WM_LINETIME_TIME(linetime);
2080 }
2081
2082 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2083 {
2084         struct drm_i915_private *dev_priv = to_i915(dev);
2085
2086         if (IS_GEN9(dev_priv)) {
2087                 uint32_t val;
2088                 int ret, i;
2089                 int level, max_level = ilk_wm_max_level(dev_priv);
2090
2091                 /* read the first set of memory latencies[0:3] */
2092                 val = 0; /* data0 to be programmed to 0 for first set */
2093                 mutex_lock(&dev_priv->rps.hw_lock);
2094                 ret = sandybridge_pcode_read(dev_priv,
2095                                              GEN9_PCODE_READ_MEM_LATENCY,
2096                                              &val);
2097                 mutex_unlock(&dev_priv->rps.hw_lock);
2098
2099                 if (ret) {
2100                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2101                         return;
2102                 }
2103
2104                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2105                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2106                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2107                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2108                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2109                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2110                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2111
2112                 /* read the second set of memory latencies[4:7] */
2113                 val = 1; /* data0 to be programmed to 1 for second set */
2114                 mutex_lock(&dev_priv->rps.hw_lock);
2115                 ret = sandybridge_pcode_read(dev_priv,
2116                                              GEN9_PCODE_READ_MEM_LATENCY,
2117                                              &val);
2118                 mutex_unlock(&dev_priv->rps.hw_lock);
2119                 if (ret) {
2120                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2121                         return;
2122                 }
2123
2124                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2125                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2126                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2127                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2128                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2129                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2130                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2131
2132                 /*
2133                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2134                  * need to be disabled. We make sure to sanitize the values out
2135                  * of the punit to satisfy this requirement.
2136                  */
2137                 for (level = 1; level <= max_level; level++) {
2138                         if (wm[level] == 0) {
2139                                 for (i = level + 1; i <= max_level; i++)
2140                                         wm[i] = 0;
2141                                 break;
2142                         }
2143                 }
2144
2145                 /*
2146                  * WaWmMemoryReadLatency:skl
2147                  *
2148                  * punit doesn't take into account the read latency so we need
2149                  * to add 2us to the various latency levels we retrieve from the
2150                  * punit when level 0 response data us 0us.
2151                  */
2152                 if (wm[0] == 0) {
2153                         wm[0] += 2;
2154                         for (level = 1; level <= max_level; level++) {
2155                                 if (wm[level] == 0)
2156                                         break;
2157                                 wm[level] += 2;
2158                         }
2159                 }
2160
2161         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2162                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2163
2164                 wm[0] = (sskpd >> 56) & 0xFF;
2165                 if (wm[0] == 0)
2166                         wm[0] = sskpd & 0xF;
2167                 wm[1] = (sskpd >> 4) & 0xFF;
2168                 wm[2] = (sskpd >> 12) & 0xFF;
2169                 wm[3] = (sskpd >> 20) & 0x1FF;
2170                 wm[4] = (sskpd >> 32) & 0x1FF;
2171         } else if (INTEL_INFO(dev)->gen >= 6) {
2172                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2173
2174                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2175                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2176                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2177                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2178         } else if (INTEL_INFO(dev)->gen >= 5) {
2179                 uint32_t mltr = I915_READ(MLTR_ILK);
2180
2181                 /* ILK primary LP0 latency is 700 ns */
2182                 wm[0] = 7;
2183                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2184                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2185         }
2186 }
2187
2188 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2189                                        uint16_t wm[5])
2190 {
2191         /* ILK sprite LP0 latency is 1300 ns */
2192         if (IS_GEN5(dev_priv))
2193                 wm[0] = 13;
2194 }
2195
2196 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2197                                        uint16_t wm[5])
2198 {
2199         /* ILK cursor LP0 latency is 1300 ns */
2200         if (IS_GEN5(dev_priv))
2201                 wm[0] = 13;
2202
2203         /* WaDoubleCursorLP3Latency:ivb */
2204         if (IS_IVYBRIDGE(dev_priv))
2205                 wm[3] *= 2;
2206 }
2207
2208 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2209 {
2210         /* how many WM levels are we expecting */
2211         if (INTEL_GEN(dev_priv) >= 9)
2212                 return 7;
2213         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2214                 return 4;
2215         else if (INTEL_GEN(dev_priv) >= 6)
2216                 return 3;
2217         else
2218                 return 2;
2219 }
2220
2221 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2222                                    const char *name,
2223                                    const uint16_t wm[8])
2224 {
2225         int level, max_level = ilk_wm_max_level(dev_priv);
2226
2227         for (level = 0; level <= max_level; level++) {
2228                 unsigned int latency = wm[level];
2229
2230                 if (latency == 0) {
2231                         DRM_ERROR("%s WM%d latency not provided\n",
2232                                   name, level);
2233                         continue;
2234                 }
2235
2236                 /*
2237                  * - latencies are in us on gen9.
2238                  * - before then, WM1+ latency values are in 0.5us units
2239                  */
2240                 if (IS_GEN9(dev_priv))
2241                         latency *= 10;
2242                 else if (level > 0)
2243                         latency *= 5;
2244
2245                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2246                               name, level, wm[level],
2247                               latency / 10, latency % 10);
2248         }
2249 }
2250
2251 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2252                                     uint16_t wm[5], uint16_t min)
2253 {
2254         int level, max_level = ilk_wm_max_level(dev_priv);
2255
2256         if (wm[0] >= min)
2257                 return false;
2258
2259         wm[0] = max(wm[0], min);
2260         for (level = 1; level <= max_level; level++)
2261                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2262
2263         return true;
2264 }
2265
2266 static void snb_wm_latency_quirk(struct drm_device *dev)
2267 {
2268         struct drm_i915_private *dev_priv = to_i915(dev);
2269         bool changed;
2270
2271         /*
2272          * The BIOS provided WM memory latency values are often
2273          * inadequate for high resolution displays. Adjust them.
2274          */
2275         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2276                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2277                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2278
2279         if (!changed)
2280                 return;
2281
2282         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2283         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2284         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2285         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2286 }
2287
2288 static void ilk_setup_wm_latency(struct drm_device *dev)
2289 {
2290         struct drm_i915_private *dev_priv = to_i915(dev);
2291
2292         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2293
2294         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2295                sizeof(dev_priv->wm.pri_latency));
2296         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2297                sizeof(dev_priv->wm.pri_latency));
2298
2299         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2300         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2301
2302         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2303         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2304         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2305
2306         if (IS_GEN6(dev_priv))
2307                 snb_wm_latency_quirk(dev);
2308 }
2309
2310 static void skl_setup_wm_latency(struct drm_device *dev)
2311 {
2312         struct drm_i915_private *dev_priv = to_i915(dev);
2313
2314         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2315         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2316 }
2317
2318 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2319                                  struct intel_pipe_wm *pipe_wm)
2320 {
2321         /* LP0 watermark maximums depend on this pipe alone */
2322         const struct intel_wm_config config = {
2323                 .num_pipes_active = 1,
2324                 .sprites_enabled = pipe_wm->sprites_enabled,
2325                 .sprites_scaled = pipe_wm->sprites_scaled,
2326         };
2327         struct ilk_wm_maximums max;
2328
2329         /* LP0 watermarks always use 1/2 DDB partitioning */
2330         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2331
2332         /* At least LP0 must be valid */
2333         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2334                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2335                 return false;
2336         }
2337
2338         return true;
2339 }
2340
2341 /* Compute new watermarks for the pipe */
2342 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2343 {
2344         struct drm_atomic_state *state = cstate->base.state;
2345         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2346         struct intel_pipe_wm *pipe_wm;
2347         struct drm_device *dev = state->dev;
2348         const struct drm_i915_private *dev_priv = to_i915(dev);
2349         struct intel_plane *intel_plane;
2350         struct intel_plane_state *pristate = NULL;
2351         struct intel_plane_state *sprstate = NULL;
2352         struct intel_plane_state *curstate = NULL;
2353         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
2354         struct ilk_wm_maximums max;
2355
2356         pipe_wm = &cstate->wm.ilk.optimal;
2357
2358         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2359                 struct intel_plane_state *ps;
2360
2361                 ps = intel_atomic_get_existing_plane_state(state,
2362                                                            intel_plane);
2363                 if (!ps)
2364                         continue;
2365
2366                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2367                         pristate = ps;
2368                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2369                         sprstate = ps;
2370                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2371                         curstate = ps;
2372         }
2373
2374         pipe_wm->pipe_enabled = cstate->base.active;
2375         if (sprstate) {
2376                 pipe_wm->sprites_enabled = sprstate->base.visible;
2377                 pipe_wm->sprites_scaled = sprstate->base.visible &&
2378                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2379                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2380         }
2381
2382         usable_level = max_level;
2383
2384         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2385         if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2386                 usable_level = 1;
2387
2388         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2389         if (pipe_wm->sprites_scaled)
2390                 usable_level = 0;
2391
2392         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2393                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2394
2395         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2396         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2397
2398         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2399                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2400
2401         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2402                 return -EINVAL;
2403
2404         ilk_compute_wm_reg_maximums(dev, 1, &max);
2405
2406         for (level = 1; level <= max_level; level++) {
2407                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2408
2409                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2410                                      pristate, sprstate, curstate, wm);
2411
2412                 /*
2413                  * Disable any watermark level that exceeds the
2414                  * register maximums since such watermarks are
2415                  * always invalid.
2416                  */
2417                 if (level > usable_level)
2418                         continue;
2419
2420                 if (ilk_validate_wm_level(level, &max, wm))
2421                         pipe_wm->wm[level] = *wm;
2422                 else
2423                         usable_level = level;
2424         }
2425
2426         return 0;
2427 }
2428
2429 /*
2430  * Build a set of 'intermediate' watermark values that satisfy both the old
2431  * state and the new state.  These can be programmed to the hardware
2432  * immediately.
2433  */
2434 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2435                                        struct intel_crtc *intel_crtc,
2436                                        struct intel_crtc_state *newstate)
2437 {
2438         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2439         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2440         int level, max_level = ilk_wm_max_level(to_i915(dev));
2441
2442         /*
2443          * Start with the final, target watermarks, then combine with the
2444          * currently active watermarks to get values that are safe both before
2445          * and after the vblank.
2446          */
2447         *a = newstate->wm.ilk.optimal;
2448         a->pipe_enabled |= b->pipe_enabled;
2449         a->sprites_enabled |= b->sprites_enabled;
2450         a->sprites_scaled |= b->sprites_scaled;
2451
2452         for (level = 0; level <= max_level; level++) {
2453                 struct intel_wm_level *a_wm = &a->wm[level];
2454                 const struct intel_wm_level *b_wm = &b->wm[level];
2455
2456                 a_wm->enable &= b_wm->enable;
2457                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2458                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2459                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2460                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2461         }
2462
2463         /*
2464          * We need to make sure that these merged watermark values are
2465          * actually a valid configuration themselves.  If they're not,
2466          * there's no safe way to transition from the old state to
2467          * the new state, so we need to fail the atomic transaction.
2468          */
2469         if (!ilk_validate_pipe_wm(dev, a))
2470                 return -EINVAL;
2471
2472         /*
2473          * If our intermediate WM are identical to the final WM, then we can
2474          * omit the post-vblank programming; only update if it's different.
2475          */
2476         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2477                 newstate->wm.need_postvbl_update = false;
2478
2479         return 0;
2480 }
2481
2482 /*
2483  * Merge the watermarks from all active pipes for a specific level.
2484  */
2485 static void ilk_merge_wm_level(struct drm_device *dev,
2486                                int level,
2487                                struct intel_wm_level *ret_wm)
2488 {
2489         const struct intel_crtc *intel_crtc;
2490
2491         ret_wm->enable = true;
2492
2493         for_each_intel_crtc(dev, intel_crtc) {
2494                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2495                 const struct intel_wm_level *wm = &active->wm[level];
2496
2497                 if (!active->pipe_enabled)
2498                         continue;
2499
2500                 /*
2501                  * The watermark values may have been used in the past,
2502                  * so we must maintain them in the registers for some
2503                  * time even if the level is now disabled.
2504                  */
2505                 if (!wm->enable)
2506                         ret_wm->enable = false;
2507
2508                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2509                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2510                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2511                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2512         }
2513 }
2514
2515 /*
2516  * Merge all low power watermarks for all active pipes.
2517  */
2518 static void ilk_wm_merge(struct drm_device *dev,
2519                          const struct intel_wm_config *config,
2520                          const struct ilk_wm_maximums *max,
2521                          struct intel_pipe_wm *merged)
2522 {
2523         struct drm_i915_private *dev_priv = to_i915(dev);
2524         int level, max_level = ilk_wm_max_level(dev_priv);
2525         int last_enabled_level = max_level;
2526
2527         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2528         if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
2529             config->num_pipes_active > 1)
2530                 last_enabled_level = 0;
2531
2532         /* ILK: FBC WM must be disabled always */
2533         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2534
2535         /* merge each WM1+ level */
2536         for (level = 1; level <= max_level; level++) {
2537                 struct intel_wm_level *wm = &merged->wm[level];
2538
2539                 ilk_merge_wm_level(dev, level, wm);
2540
2541                 if (level > last_enabled_level)
2542                         wm->enable = false;
2543                 else if (!ilk_validate_wm_level(level, max, wm))
2544                         /* make sure all following levels get disabled */
2545                         last_enabled_level = level - 1;
2546
2547                 /*
2548                  * The spec says it is preferred to disable
2549                  * FBC WMs instead of disabling a WM level.
2550                  */
2551                 if (wm->fbc_val > max->fbc) {
2552                         if (wm->enable)
2553                                 merged->fbc_wm_enabled = false;
2554                         wm->fbc_val = 0;
2555                 }
2556         }
2557
2558         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2559         /*
2560          * FIXME this is racy. FBC might get enabled later.
2561          * What we should check here is whether FBC can be
2562          * enabled sometime later.
2563          */
2564         if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
2565             intel_fbc_is_active(dev_priv)) {
2566                 for (level = 2; level <= max_level; level++) {
2567                         struct intel_wm_level *wm = &merged->wm[level];
2568
2569                         wm->enable = false;
2570                 }
2571         }
2572 }
2573
2574 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2575 {
2576         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2577         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2578 }
2579
2580 /* The value we need to program into the WM_LPx latency field */
2581 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2582 {
2583         struct drm_i915_private *dev_priv = to_i915(dev);
2584
2585         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2586                 return 2 * level;
2587         else
2588                 return dev_priv->wm.pri_latency[level];
2589 }
2590
2591 static void ilk_compute_wm_results(struct drm_device *dev,
2592                                    const struct intel_pipe_wm *merged,
2593                                    enum intel_ddb_partitioning partitioning,
2594                                    struct ilk_wm_values *results)
2595 {
2596         struct intel_crtc *intel_crtc;
2597         int level, wm_lp;
2598
2599         results->enable_fbc_wm = merged->fbc_wm_enabled;
2600         results->partitioning = partitioning;
2601
2602         /* LP1+ register values */
2603         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2604                 const struct intel_wm_level *r;
2605
2606                 level = ilk_wm_lp_to_level(wm_lp, merged);
2607
2608                 r = &merged->wm[level];
2609
2610                 /*
2611                  * Maintain the watermark values even if the level is
2612                  * disabled. Doing otherwise could cause underruns.
2613                  */
2614                 results->wm_lp[wm_lp - 1] =
2615                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2616                         (r->pri_val << WM1_LP_SR_SHIFT) |
2617                         r->cur_val;
2618
2619                 if (r->enable)
2620                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2621
2622                 if (INTEL_INFO(dev)->gen >= 8)
2623                         results->wm_lp[wm_lp - 1] |=
2624                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2625                 else
2626                         results->wm_lp[wm_lp - 1] |=
2627                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2628
2629                 /*
2630                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2631                  * level is disabled. Doing otherwise could cause underruns.
2632                  */
2633                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2634                         WARN_ON(wm_lp != 1);
2635                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2636                 } else
2637                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2638         }
2639
2640         /* LP0 register values */
2641         for_each_intel_crtc(dev, intel_crtc) {
2642                 enum pipe pipe = intel_crtc->pipe;
2643                 const struct intel_wm_level *r =
2644                         &intel_crtc->wm.active.ilk.wm[0];
2645
2646                 if (WARN_ON(!r->enable))
2647                         continue;
2648
2649                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2650
2651                 results->wm_pipe[pipe] =
2652                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2653                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2654                         r->cur_val;
2655         }
2656 }
2657
2658 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2659  * case both are at the same level. Prefer r1 in case they're the same. */
2660 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2661                                                   struct intel_pipe_wm *r1,
2662                                                   struct intel_pipe_wm *r2)
2663 {
2664         int level, max_level = ilk_wm_max_level(to_i915(dev));
2665         int level1 = 0, level2 = 0;
2666
2667         for (level = 1; level <= max_level; level++) {
2668                 if (r1->wm[level].enable)
2669                         level1 = level;
2670                 if (r2->wm[level].enable)
2671                         level2 = level;
2672         }
2673
2674         if (level1 == level2) {
2675                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2676                         return r2;
2677                 else
2678                         return r1;
2679         } else if (level1 > level2) {
2680                 return r1;
2681         } else {
2682                 return r2;
2683         }
2684 }
2685
2686 /* dirty bits used to track which watermarks need changes */
2687 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2688 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2689 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2690 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2691 #define WM_DIRTY_FBC (1 << 24)
2692 #define WM_DIRTY_DDB (1 << 25)
2693
2694 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2695                                          const struct ilk_wm_values *old,
2696                                          const struct ilk_wm_values *new)
2697 {
2698         unsigned int dirty = 0;
2699         enum pipe pipe;
2700         int wm_lp;
2701
2702         for_each_pipe(dev_priv, pipe) {
2703                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2704                         dirty |= WM_DIRTY_LINETIME(pipe);
2705                         /* Must disable LP1+ watermarks too */
2706                         dirty |= WM_DIRTY_LP_ALL;
2707                 }
2708
2709                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2710                         dirty |= WM_DIRTY_PIPE(pipe);
2711                         /* Must disable LP1+ watermarks too */
2712                         dirty |= WM_DIRTY_LP_ALL;
2713                 }
2714         }
2715
2716         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2717                 dirty |= WM_DIRTY_FBC;
2718                 /* Must disable LP1+ watermarks too */
2719                 dirty |= WM_DIRTY_LP_ALL;
2720         }
2721
2722         if (old->partitioning != new->partitioning) {
2723                 dirty |= WM_DIRTY_DDB;
2724                 /* Must disable LP1+ watermarks too */
2725                 dirty |= WM_DIRTY_LP_ALL;
2726         }
2727
2728         /* LP1+ watermarks already deemed dirty, no need to continue */
2729         if (dirty & WM_DIRTY_LP_ALL)
2730                 return dirty;
2731
2732         /* Find the lowest numbered LP1+ watermark in need of an update... */
2733         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2734                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2735                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2736                         break;
2737         }
2738
2739         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2740         for (; wm_lp <= 3; wm_lp++)
2741                 dirty |= WM_DIRTY_LP(wm_lp);
2742
2743         return dirty;
2744 }
2745
2746 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2747                                unsigned int dirty)
2748 {
2749         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2750         bool changed = false;
2751
2752         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2753                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2754                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2755                 changed = true;
2756         }
2757         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2758                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2759                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2760                 changed = true;
2761         }
2762         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2763                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2764                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2765                 changed = true;
2766         }
2767
2768         /*
2769          * Don't touch WM1S_LP_EN here.
2770          * Doing so could cause underruns.
2771          */
2772
2773         return changed;
2774 }
2775
2776 /*
2777  * The spec says we shouldn't write when we don't need, because every write
2778  * causes WMs to be re-evaluated, expending some power.
2779  */
2780 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2781                                 struct ilk_wm_values *results)
2782 {
2783         struct drm_device *dev = &dev_priv->drm;
2784         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2785         unsigned int dirty;
2786         uint32_t val;
2787
2788         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2789         if (!dirty)
2790                 return;
2791
2792         _ilk_disable_lp_wm(dev_priv, dirty);
2793
2794         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2795                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2796         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2797                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2798         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2799                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2800
2801         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2802                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2803         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2804                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2805         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2806                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2807
2808         if (dirty & WM_DIRTY_DDB) {
2809                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2810                         val = I915_READ(WM_MISC);
2811                         if (results->partitioning == INTEL_DDB_PART_1_2)
2812                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2813                         else
2814                                 val |= WM_MISC_DATA_PARTITION_5_6;
2815                         I915_WRITE(WM_MISC, val);
2816                 } else {
2817                         val = I915_READ(DISP_ARB_CTL2);
2818                         if (results->partitioning == INTEL_DDB_PART_1_2)
2819                                 val &= ~DISP_DATA_PARTITION_5_6;
2820                         else
2821                                 val |= DISP_DATA_PARTITION_5_6;
2822                         I915_WRITE(DISP_ARB_CTL2, val);
2823                 }
2824         }
2825
2826         if (dirty & WM_DIRTY_FBC) {
2827                 val = I915_READ(DISP_ARB_CTL);
2828                 if (results->enable_fbc_wm)
2829                         val &= ~DISP_FBC_WM_DIS;
2830                 else
2831                         val |= DISP_FBC_WM_DIS;
2832                 I915_WRITE(DISP_ARB_CTL, val);
2833         }
2834
2835         if (dirty & WM_DIRTY_LP(1) &&
2836             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2837                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2838
2839         if (INTEL_INFO(dev)->gen >= 7) {
2840                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2841                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2842                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2843                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2844         }
2845
2846         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2847                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2848         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2849                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2850         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2851                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2852
2853         dev_priv->wm.hw = *results;
2854 }
2855
2856 bool ilk_disable_lp_wm(struct drm_device *dev)
2857 {
2858         struct drm_i915_private *dev_priv = to_i915(dev);
2859
2860         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2861 }
2862
2863 #define SKL_SAGV_BLOCK_TIME     30 /* µs */
2864
2865 /*
2866  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2867  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2868  * other universal planes are in indices 1..n.  Note that this may leave unused
2869  * indices between the top "sprite" plane and the cursor.
2870  */
2871 static int
2872 skl_wm_plane_id(const struct intel_plane *plane)
2873 {
2874         switch (plane->base.type) {
2875         case DRM_PLANE_TYPE_PRIMARY:
2876                 return 0;
2877         case DRM_PLANE_TYPE_CURSOR:
2878                 return PLANE_CURSOR;
2879         case DRM_PLANE_TYPE_OVERLAY:
2880                 return plane->plane + 1;
2881         default:
2882                 MISSING_CASE(plane->base.type);
2883                 return plane->plane;
2884         }
2885 }
2886
2887 /*
2888  * FIXME: We still don't have the proper code detect if we need to apply the WA,
2889  * so assume we'll always need it in order to avoid underruns.
2890  */
2891 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2892 {
2893         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2894
2895         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2896             IS_KABYLAKE(dev_priv))
2897                 return true;
2898
2899         return false;
2900 }
2901
2902 static bool
2903 intel_has_sagv(struct drm_i915_private *dev_priv)
2904 {
2905         if (IS_KABYLAKE(dev_priv))
2906                 return true;
2907
2908         if (IS_SKYLAKE(dev_priv) &&
2909             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2910                 return true;
2911
2912         return false;
2913 }
2914
2915 /*
2916  * SAGV dynamically adjusts the system agent voltage and clock frequencies
2917  * depending on power and performance requirements. The display engine access
2918  * to system memory is blocked during the adjustment time. Because of the
2919  * blocking time, having this enabled can cause full system hangs and/or pipe
2920  * underruns if we don't meet all of the following requirements:
2921  *
2922  *  - <= 1 pipe enabled
2923  *  - All planes can enable watermarks for latencies >= SAGV engine block time
2924  *  - We're not using an interlaced display configuration
2925  */
2926 int
2927 intel_enable_sagv(struct drm_i915_private *dev_priv)
2928 {
2929         int ret;
2930
2931         if (!intel_has_sagv(dev_priv))
2932                 return 0;
2933
2934         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
2935                 return 0;
2936
2937         DRM_DEBUG_KMS("Enabling the SAGV\n");
2938         mutex_lock(&dev_priv->rps.hw_lock);
2939
2940         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2941                                       GEN9_SAGV_ENABLE);
2942
2943         /* We don't need to wait for the SAGV when enabling */
2944         mutex_unlock(&dev_priv->rps.hw_lock);
2945
2946         /*
2947          * Some skl systems, pre-release machines in particular,
2948          * don't actually have an SAGV.
2949          */
2950         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2951                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2952                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2953                 return 0;
2954         } else if (ret < 0) {
2955                 DRM_ERROR("Failed to enable the SAGV\n");
2956                 return ret;
2957         }
2958
2959         dev_priv->sagv_status = I915_SAGV_ENABLED;
2960         return 0;
2961 }
2962
2963 static int
2964 intel_do_sagv_disable(struct drm_i915_private *dev_priv)
2965 {
2966         int ret;
2967         uint32_t temp = GEN9_SAGV_DISABLE;
2968
2969         ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2970                                      &temp);
2971         if (ret)
2972                 return ret;
2973         else
2974                 return temp & GEN9_SAGV_IS_DISABLED;
2975 }
2976
2977 int
2978 intel_disable_sagv(struct drm_i915_private *dev_priv)
2979 {
2980         int ret, result;
2981
2982         if (!intel_has_sagv(dev_priv))
2983                 return 0;
2984
2985         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
2986                 return 0;
2987
2988         DRM_DEBUG_KMS("Disabling the SAGV\n");
2989         mutex_lock(&dev_priv->rps.hw_lock);
2990
2991         /* bspec says to keep retrying for at least 1 ms */
2992         ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
2993         mutex_unlock(&dev_priv->rps.hw_lock);
2994
2995         if (ret == -ETIMEDOUT) {
2996                 DRM_ERROR("Request to disable SAGV timed out\n");
2997                 return -ETIMEDOUT;
2998         }
2999
3000         /*
3001          * Some skl systems, pre-release machines in particular,
3002          * don't actually have an SAGV.
3003          */
3004         if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
3005                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3006                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3007                 return 0;
3008         } else if (result < 0) {
3009                 DRM_ERROR("Failed to disable the SAGV\n");
3010                 return result;
3011         }
3012
3013         dev_priv->sagv_status = I915_SAGV_DISABLED;
3014         return 0;
3015 }
3016
3017 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3018 {
3019         struct drm_device *dev = state->dev;
3020         struct drm_i915_private *dev_priv = to_i915(dev);
3021         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3022         struct intel_crtc *crtc;
3023         struct intel_plane *plane;
3024         struct intel_crtc_state *cstate;
3025         struct skl_plane_wm *wm;
3026         enum pipe pipe;
3027         int level, latency;
3028
3029         if (!intel_has_sagv(dev_priv))
3030                 return false;
3031
3032         /*
3033          * SKL workaround: bspec recommends we disable the SAGV when we have
3034          * more then one pipe enabled
3035          *
3036          * If there are no active CRTCs, no additional checks need be performed
3037          */
3038         if (hweight32(intel_state->active_crtcs) == 0)
3039                 return true;
3040         else if (hweight32(intel_state->active_crtcs) > 1)
3041                 return false;
3042
3043         /* Since we're now guaranteed to only have one active CRTC... */
3044         pipe = ffs(intel_state->active_crtcs) - 1;
3045         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3046         cstate = to_intel_crtc_state(crtc->base.state);
3047
3048         if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3049                 return false;
3050
3051         for_each_intel_plane_on_crtc(dev, crtc, plane) {
3052                 wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
3053
3054                 /* Skip this plane if it's not enabled */
3055                 if (!wm->wm[0].plane_en)
3056                         continue;
3057
3058                 /* Find the highest enabled wm level for this plane */
3059                 for (level = ilk_wm_max_level(dev_priv);
3060                      !wm->wm[level].plane_en; --level)
3061                      { }
3062
3063                 latency = dev_priv->wm.skl_latency[level];
3064
3065                 if (skl_needs_memory_bw_wa(intel_state) &&
3066                     plane->base.state->fb->modifier[0] ==
3067                     I915_FORMAT_MOD_X_TILED)
3068                         latency += 15;
3069
3070                 /*
3071                  * If any of the planes on this pipe don't enable wm levels
3072                  * that incur memory latencies higher then 30µs we can't enable
3073                  * the SAGV
3074                  */
3075                 if (latency < SKL_SAGV_BLOCK_TIME)
3076                         return false;
3077         }
3078
3079         return true;
3080 }
3081
3082 static void
3083 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3084                                    const struct intel_crtc_state *cstate,
3085                                    struct skl_ddb_entry *alloc, /* out */
3086                                    int *num_active /* out */)
3087 {
3088         struct drm_atomic_state *state = cstate->base.state;
3089         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3090         struct drm_i915_private *dev_priv = to_i915(dev);
3091         struct drm_crtc *for_crtc = cstate->base.crtc;
3092         unsigned int pipe_size, ddb_size;
3093         int nth_active_pipe;
3094
3095         if (WARN_ON(!state) || !cstate->base.active) {
3096                 alloc->start = 0;
3097                 alloc->end = 0;
3098                 *num_active = hweight32(dev_priv->active_crtcs);
3099                 return;
3100         }
3101
3102         if (intel_state->active_pipe_changes)
3103                 *num_active = hweight32(intel_state->active_crtcs);
3104         else
3105                 *num_active = hweight32(dev_priv->active_crtcs);
3106
3107         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3108         WARN_ON(ddb_size == 0);
3109
3110         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3111
3112         /*
3113          * If the state doesn't change the active CRTC's, then there's
3114          * no need to recalculate; the existing pipe allocation limits
3115          * should remain unchanged.  Note that we're safe from racing
3116          * commits since any racing commit that changes the active CRTC
3117          * list would need to grab _all_ crtc locks, including the one
3118          * we currently hold.
3119          */
3120         if (!intel_state->active_pipe_changes) {
3121                 *alloc = to_intel_crtc(for_crtc)->hw_ddb;
3122                 return;
3123         }
3124
3125         nth_active_pipe = hweight32(intel_state->active_crtcs &
3126                                     (drm_crtc_mask(for_crtc) - 1));
3127         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3128         alloc->start = nth_active_pipe * ddb_size / *num_active;
3129         alloc->end = alloc->start + pipe_size;
3130 }
3131
3132 static unsigned int skl_cursor_allocation(int num_active)
3133 {
3134         if (num_active == 1)
3135                 return 32;
3136
3137         return 8;
3138 }
3139
3140 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3141 {
3142         entry->start = reg & 0x3ff;
3143         entry->end = (reg >> 16) & 0x3ff;
3144         if (entry->end)
3145                 entry->end += 1;
3146 }
3147
3148 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3149                           struct skl_ddb_allocation *ddb /* out */)
3150 {
3151         enum pipe pipe;
3152         int plane;
3153         u32 val;
3154
3155         memset(ddb, 0, sizeof(*ddb));
3156
3157         for_each_pipe(dev_priv, pipe) {
3158                 enum intel_display_power_domain power_domain;
3159
3160                 power_domain = POWER_DOMAIN_PIPE(pipe);
3161                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3162                         continue;
3163
3164                 for_each_universal_plane(dev_priv, pipe, plane) {
3165                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3166                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3167                                                    val);
3168                 }
3169
3170                 val = I915_READ(CUR_BUF_CFG(pipe));
3171                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3172                                            val);
3173
3174                 intel_display_power_put(dev_priv, power_domain);
3175         }
3176 }
3177
3178 /*
3179  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3180  * The bspec defines downscale amount as:
3181  *
3182  * """
3183  * Horizontal down scale amount = maximum[1, Horizontal source size /
3184  *                                           Horizontal destination size]
3185  * Vertical down scale amount = maximum[1, Vertical source size /
3186  *                                         Vertical destination size]
3187  * Total down scale amount = Horizontal down scale amount *
3188  *                           Vertical down scale amount
3189  * """
3190  *
3191  * Return value is provided in 16.16 fixed point form to retain fractional part.
3192  * Caller should take care of dividing & rounding off the value.
3193  */
3194 static uint32_t
3195 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3196 {
3197         uint32_t downscale_h, downscale_w;
3198         uint32_t src_w, src_h, dst_w, dst_h;
3199
3200         if (WARN_ON(!pstate->base.visible))
3201                 return DRM_PLANE_HELPER_NO_SCALING;
3202
3203         /* n.b., src is 16.16 fixed point, dst is whole integer */
3204         src_w = drm_rect_width(&pstate->base.src);
3205         src_h = drm_rect_height(&pstate->base.src);
3206         dst_w = drm_rect_width(&pstate->base.dst);
3207         dst_h = drm_rect_height(&pstate->base.dst);
3208         if (drm_rotation_90_or_270(pstate->base.rotation))
3209                 swap(dst_w, dst_h);
3210
3211         downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3212         downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3213
3214         /* Provide result in 16.16 fixed point */
3215         return (uint64_t)downscale_w * downscale_h >> 16;
3216 }
3217
3218 static unsigned int
3219 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3220                              const struct drm_plane_state *pstate,
3221                              int y)
3222 {
3223         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3224         struct drm_framebuffer *fb = pstate->fb;
3225         uint32_t down_scale_amount, data_rate;
3226         uint32_t width = 0, height = 0;
3227         unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3228
3229         if (!intel_pstate->base.visible)
3230                 return 0;
3231         if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3232                 return 0;
3233         if (y && format != DRM_FORMAT_NV12)
3234                 return 0;
3235
3236         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3237         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3238
3239         if (drm_rotation_90_or_270(pstate->rotation))
3240                 swap(width, height);
3241
3242         /* for planar format */
3243         if (format == DRM_FORMAT_NV12) {
3244                 if (y)  /* y-plane data rate */
3245                         data_rate = width * height *
3246                                 drm_format_plane_cpp(format, 0);
3247                 else    /* uv-plane data rate */
3248                         data_rate = (width / 2) * (height / 2) *
3249                                 drm_format_plane_cpp(format, 1);
3250         } else {
3251                 /* for packed formats */
3252                 data_rate = width * height * drm_format_plane_cpp(format, 0);
3253         }
3254
3255         down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3256
3257         return (uint64_t)data_rate * down_scale_amount >> 16;
3258 }
3259
3260 /*
3261  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3262  * a 8192x4096@32bpp framebuffer:
3263  *   3 * 4096 * 8192  * 4 < 2^32
3264  */
3265 static unsigned int
3266 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3267                                  unsigned *plane_data_rate,
3268                                  unsigned *plane_y_data_rate)
3269 {
3270         struct drm_crtc_state *cstate = &intel_cstate->base;
3271         struct drm_atomic_state *state = cstate->state;
3272         struct drm_plane *plane;
3273         const struct intel_plane *intel_plane;
3274         const struct drm_plane_state *pstate;
3275         unsigned int rate, total_data_rate = 0;
3276         int id;
3277
3278         if (WARN_ON(!state))
3279                 return 0;
3280
3281         /* Calculate and cache data rate for each plane */
3282         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
3283                 id = skl_wm_plane_id(to_intel_plane(plane));
3284                 intel_plane = to_intel_plane(plane);
3285
3286                 /* packed/uv */
3287                 rate = skl_plane_relative_data_rate(intel_cstate,
3288                                                     pstate, 0);
3289                 plane_data_rate[id] = rate;
3290
3291                 total_data_rate += rate;
3292
3293                 /* y-plane */
3294                 rate = skl_plane_relative_data_rate(intel_cstate,
3295                                                     pstate, 1);
3296                 plane_y_data_rate[id] = rate;
3297
3298                 total_data_rate += rate;
3299         }
3300
3301         return total_data_rate;
3302 }
3303
3304 static uint16_t
3305 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3306                   const int y)
3307 {
3308         struct drm_framebuffer *fb = pstate->fb;
3309         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3310         uint32_t src_w, src_h;
3311         uint32_t min_scanlines = 8;
3312         uint8_t plane_bpp;
3313
3314         if (WARN_ON(!fb))
3315                 return 0;
3316
3317         /* For packed formats, no y-plane, return 0 */
3318         if (y && fb->pixel_format != DRM_FORMAT_NV12)
3319                 return 0;
3320
3321         /* For Non Y-tile return 8-blocks */
3322         if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3323             fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3324                 return 8;
3325
3326         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3327         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3328
3329         if (drm_rotation_90_or_270(pstate->rotation))
3330                 swap(src_w, src_h);
3331
3332         /* Halve UV plane width and height for NV12 */
3333         if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3334                 src_w /= 2;
3335                 src_h /= 2;
3336         }
3337
3338         if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3339                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3340         else
3341                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3342
3343         if (drm_rotation_90_or_270(pstate->rotation)) {
3344                 switch (plane_bpp) {
3345                 case 1:
3346                         min_scanlines = 32;
3347                         break;
3348                 case 2:
3349                         min_scanlines = 16;
3350                         break;
3351                 case 4:
3352                         min_scanlines = 8;
3353                         break;
3354                 case 8:
3355                         min_scanlines = 4;
3356                         break;
3357                 default:
3358                         WARN(1, "Unsupported pixel depth %u for rotation",
3359                              plane_bpp);
3360                         min_scanlines = 32;
3361                 }
3362         }
3363
3364         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3365 }
3366
3367 static void
3368 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3369                  uint16_t *minimum, uint16_t *y_minimum)
3370 {
3371         const struct drm_plane_state *pstate;
3372         struct drm_plane *plane;
3373
3374         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3375                 struct intel_plane *intel_plane = to_intel_plane(plane);
3376                 int id = skl_wm_plane_id(intel_plane);
3377
3378                 if (id == PLANE_CURSOR)
3379                         continue;
3380
3381                 if (!pstate->visible)
3382                         continue;
3383
3384                 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3385                 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3386         }
3387
3388         minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3389 }
3390
3391 static int
3392 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3393                       struct skl_ddb_allocation *ddb /* out */)
3394 {
3395         struct drm_atomic_state *state = cstate->base.state;
3396         struct drm_crtc *crtc = cstate->base.crtc;
3397         struct drm_device *dev = crtc->dev;
3398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399         enum pipe pipe = intel_crtc->pipe;
3400         struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
3401         uint16_t alloc_size, start;
3402         uint16_t minimum[I915_MAX_PLANES] = {};
3403         uint16_t y_minimum[I915_MAX_PLANES] = {};
3404         unsigned int total_data_rate;
3405         int num_active;
3406         int id, i;
3407         unsigned plane_data_rate[I915_MAX_PLANES] = {};
3408         unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
3409
3410         /* Clear the partitioning for disabled planes. */
3411         memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3412         memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3413
3414         if (WARN_ON(!state))
3415                 return 0;
3416
3417         if (!cstate->base.active) {
3418                 alloc->start = alloc->end = 0;
3419                 return 0;
3420         }
3421
3422         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3423         alloc_size = skl_ddb_entry_size(alloc);
3424         if (alloc_size == 0) {
3425                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3426                 return 0;
3427         }
3428
3429         skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
3430
3431         /*
3432          * 1. Allocate the mininum required blocks for each active plane
3433          * and allocate the cursor, it doesn't require extra allocation
3434          * proportional to the data rate.
3435          */
3436
3437         for (i = 0; i < I915_MAX_PLANES; i++) {
3438                 alloc_size -= minimum[i];
3439                 alloc_size -= y_minimum[i];
3440         }
3441
3442         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3443         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3444
3445         /*
3446          * 2. Distribute the remaining space in proportion to the amount of
3447          * data each plane needs to fetch from memory.
3448          *
3449          * FIXME: we may not allocate every single block here.
3450          */
3451         total_data_rate = skl_get_total_relative_data_rate(cstate,
3452                                                            plane_data_rate,
3453                                                            plane_y_data_rate);
3454         if (total_data_rate == 0)
3455                 return 0;
3456
3457         start = alloc->start;
3458         for (id = 0; id < I915_MAX_PLANES; id++) {
3459                 unsigned int data_rate, y_data_rate;
3460                 uint16_t plane_blocks, y_plane_blocks = 0;
3461
3462                 if (id == PLANE_CURSOR)
3463                         continue;
3464
3465                 data_rate = plane_data_rate[id];
3466
3467                 /*
3468                  * allocation for (packed formats) or (uv-plane part of planar format):
3469                  * promote the expression to 64 bits to avoid overflowing, the
3470                  * result is < available as data_rate / total_data_rate < 1
3471                  */
3472                 plane_blocks = minimum[id];
3473                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3474                                         total_data_rate);
3475
3476                 /* Leave disabled planes at (0,0) */
3477                 if (data_rate) {
3478                         ddb->plane[pipe][id].start = start;
3479                         ddb->plane[pipe][id].end = start + plane_blocks;
3480                 }
3481
3482                 start += plane_blocks;
3483
3484                 /*
3485                  * allocation for y_plane part of planar format:
3486                  */
3487                 y_data_rate = plane_y_data_rate[id];
3488
3489                 y_plane_blocks = y_minimum[id];
3490                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3491                                         total_data_rate);
3492
3493                 if (y_data_rate) {
3494                         ddb->y_plane[pipe][id].start = start;
3495                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3496                 }
3497
3498                 start += y_plane_blocks;
3499         }
3500
3501         return 0;
3502 }
3503
3504 /*
3505  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3506  * for the read latency) and cpp should always be <= 8, so that
3507  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3508  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3509 */
3510 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3511 {
3512         uint32_t wm_intermediate_val, ret;
3513
3514         if (latency == 0)
3515                 return UINT_MAX;
3516
3517         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3518         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3519
3520         return ret;
3521 }
3522
3523 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3524                                uint32_t latency, uint32_t plane_blocks_per_line)
3525 {
3526         uint32_t ret;
3527         uint32_t wm_intermediate_val;
3528
3529         if (latency == 0)
3530                 return UINT_MAX;
3531
3532         wm_intermediate_val = latency * pixel_rate;
3533         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3534                                 plane_blocks_per_line;
3535
3536         return ret;
3537 }
3538
3539 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3540                                               struct intel_plane_state *pstate)
3541 {
3542         uint64_t adjusted_pixel_rate;
3543         uint64_t downscale_amount;
3544         uint64_t pixel_rate;
3545
3546         /* Shouldn't reach here on disabled planes... */
3547         if (WARN_ON(!pstate->base.visible))
3548                 return 0;
3549
3550         /*
3551          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3552          * with additional adjustments for plane-specific scaling.
3553          */
3554         adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
3555         downscale_amount = skl_plane_downscale_amount(pstate);
3556
3557         pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3558         WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3559
3560         return pixel_rate;
3561 }
3562
3563 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3564                                 struct intel_crtc_state *cstate,
3565                                 struct intel_plane_state *intel_pstate,
3566                                 uint16_t ddb_allocation,
3567                                 int level,
3568                                 uint16_t *out_blocks, /* out */
3569                                 uint8_t *out_lines, /* out */
3570                                 bool *enabled /* out */)
3571 {
3572         struct drm_plane_state *pstate = &intel_pstate->base;
3573         struct drm_framebuffer *fb = pstate->fb;
3574         uint32_t latency = dev_priv->wm.skl_latency[level];
3575         uint32_t method1, method2;
3576         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3577         uint32_t res_blocks, res_lines;
3578         uint32_t selected_result;
3579         uint8_t cpp;
3580         uint32_t width = 0, height = 0;
3581         uint32_t plane_pixel_rate;
3582         uint32_t y_tile_minimum, y_min_scanlines;
3583         struct intel_atomic_state *state =
3584                 to_intel_atomic_state(cstate->base.state);
3585         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
3586
3587         if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3588                 *enabled = false;
3589                 return 0;
3590         }
3591
3592         if (apply_memory_bw_wa && fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3593                 latency += 15;
3594
3595         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3596         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3597
3598         if (drm_rotation_90_or_270(pstate->rotation))
3599                 swap(width, height);
3600
3601         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3602         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3603
3604         if (drm_rotation_90_or_270(pstate->rotation)) {
3605                 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3606                         drm_format_plane_cpp(fb->pixel_format, 1) :
3607                         drm_format_plane_cpp(fb->pixel_format, 0);
3608
3609                 switch (cpp) {
3610                 case 1:
3611                         y_min_scanlines = 16;
3612                         break;
3613                 case 2:
3614                         y_min_scanlines = 8;
3615                         break;
3616                 case 4:
3617                         y_min_scanlines = 4;
3618                         break;
3619                 default:
3620                         MISSING_CASE(cpp);
3621                         return -EINVAL;
3622                 }
3623         } else {
3624                 y_min_scanlines = 4;
3625         }
3626
3627         plane_bytes_per_line = width * cpp;
3628         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3629             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3630                 plane_blocks_per_line =
3631                       DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3632                 plane_blocks_per_line /= y_min_scanlines;
3633         } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3634                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3635                                         + 1;
3636         } else {
3637                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3638         }
3639
3640         method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3641         method2 = skl_wm_method2(plane_pixel_rate,
3642                                  cstate->base.adjusted_mode.crtc_htotal,
3643                                  latency,
3644                                  plane_blocks_per_line);
3645
3646         y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3647         if (apply_memory_bw_wa)
3648                 y_tile_minimum *= 2;
3649
3650         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3651             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3652                 selected_result = max(method2, y_tile_minimum);
3653         } else {
3654                 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3655                     (plane_bytes_per_line / 512 < 1))
3656                         selected_result = method2;
3657                 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
3658                         selected_result = min(method1, method2);
3659                 else
3660                         selected_result = method1;
3661         }
3662
3663         res_blocks = selected_result + 1;
3664         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3665
3666         if (level >= 1 && level <= 7) {
3667                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3668                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3669                         res_blocks += y_tile_minimum;
3670                         res_lines += y_min_scanlines;
3671                 } else {
3672                         res_blocks++;
3673                 }
3674         }
3675
3676         if (res_blocks >= ddb_allocation || res_lines > 31) {
3677                 *enabled = false;
3678
3679                 /*
3680                  * If there are no valid level 0 watermarks, then we can't
3681                  * support this display configuration.
3682                  */
3683                 if (level) {
3684                         return 0;
3685                 } else {
3686                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3687                         DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3688                                       to_intel_crtc(cstate->base.crtc)->pipe,
3689                                       skl_wm_plane_id(to_intel_plane(pstate->plane)),
3690                                       res_blocks, ddb_allocation, res_lines);
3691
3692                         return -EINVAL;
3693                 }
3694         }
3695
3696         *out_blocks = res_blocks;
3697         *out_lines = res_lines;
3698         *enabled = true;
3699
3700         return 0;
3701 }
3702
3703 static int
3704 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3705                      struct skl_ddb_allocation *ddb,
3706                      struct intel_crtc_state *cstate,
3707                      struct intel_plane *intel_plane,
3708                      int level,
3709                      struct skl_wm_level *result)
3710 {
3711         struct drm_atomic_state *state = cstate->base.state;
3712         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3713         struct drm_plane *plane = &intel_plane->base;
3714         struct intel_plane_state *intel_pstate = NULL;
3715         uint16_t ddb_blocks;
3716         enum pipe pipe = intel_crtc->pipe;
3717         int ret;
3718         int i = skl_wm_plane_id(intel_plane);
3719
3720         if (state)
3721                 intel_pstate =
3722                         intel_atomic_get_existing_plane_state(state,
3723                                                               intel_plane);
3724
3725         /*
3726          * Note: If we start supporting multiple pending atomic commits against
3727          * the same planes/CRTC's in the future, plane->state will no longer be
3728          * the correct pre-state to use for the calculations here and we'll
3729          * need to change where we get the 'unchanged' plane data from.
3730          *
3731          * For now this is fine because we only allow one queued commit against
3732          * a CRTC.  Even if the plane isn't modified by this transaction and we
3733          * don't have a plane lock, we still have the CRTC's lock, so we know
3734          * that no other transactions are racing with us to update it.
3735          */
3736         if (!intel_pstate)
3737                 intel_pstate = to_intel_plane_state(plane->state);
3738
3739         WARN_ON(!intel_pstate->base.fb);
3740
3741         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3742
3743         ret = skl_compute_plane_wm(dev_priv,
3744                                    cstate,
3745                                    intel_pstate,
3746                                    ddb_blocks,
3747                                    level,
3748                                    &result->plane_res_b,
3749                                    &result->plane_res_l,
3750                                    &result->plane_en);
3751         if (ret)
3752                 return ret;
3753
3754         return 0;
3755 }
3756
3757 static uint32_t
3758 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3759 {
3760         uint32_t pixel_rate;
3761
3762         if (!cstate->base.active)
3763                 return 0;
3764
3765         pixel_rate = ilk_pipe_pixel_rate(cstate);
3766
3767         if (WARN_ON(pixel_rate == 0))
3768                 return 0;
3769
3770         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3771                             pixel_rate);
3772 }
3773
3774 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3775                                       struct skl_wm_level *trans_wm /* out */)
3776 {
3777         if (!cstate->base.active)
3778                 return;
3779
3780         /* Until we know more, just disable transition WMs */
3781         trans_wm->plane_en = false;
3782 }
3783
3784 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3785                              struct skl_ddb_allocation *ddb,
3786                              struct skl_pipe_wm *pipe_wm)
3787 {
3788         struct drm_device *dev = cstate->base.crtc->dev;
3789         const struct drm_i915_private *dev_priv = to_i915(dev);
3790         struct intel_plane *intel_plane;
3791         struct skl_plane_wm *wm;
3792         int level, max_level = ilk_wm_max_level(dev_priv);
3793         int ret;
3794
3795         /*
3796          * We'll only calculate watermarks for planes that are actually
3797          * enabled, so make sure all other planes are set as disabled.
3798          */
3799         memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3800
3801         for_each_intel_plane_mask(&dev_priv->drm,
3802                                   intel_plane,
3803                                   cstate->base.plane_mask) {
3804                 wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
3805
3806                 for (level = 0; level <= max_level; level++) {
3807                         ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3808                                                    intel_plane, level,
3809                                                    &wm->wm[level]);
3810                         if (ret)
3811                                 return ret;
3812                 }
3813                 skl_compute_transition_wm(cstate, &wm->trans_wm);
3814         }
3815         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3816
3817         return 0;
3818 }
3819
3820 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3821                                 i915_reg_t reg,
3822                                 const struct skl_ddb_entry *entry)
3823 {
3824         if (entry->end)
3825                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3826         else
3827                 I915_WRITE(reg, 0);
3828 }
3829
3830 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3831                                i915_reg_t reg,
3832                                const struct skl_wm_level *level)
3833 {
3834         uint32_t val = 0;
3835
3836         if (level->plane_en) {
3837                 val |= PLANE_WM_EN;
3838                 val |= level->plane_res_b;
3839                 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3840         }
3841
3842         I915_WRITE(reg, val);
3843 }
3844
3845 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3846                         const struct skl_plane_wm *wm,
3847                         const struct skl_ddb_allocation *ddb,
3848                         int plane)
3849 {
3850         struct drm_crtc *crtc = &intel_crtc->base;
3851         struct drm_device *dev = crtc->dev;
3852         struct drm_i915_private *dev_priv = to_i915(dev);
3853         int level, max_level = ilk_wm_max_level(dev_priv);
3854         enum pipe pipe = intel_crtc->pipe;
3855
3856         for (level = 0; level <= max_level; level++) {
3857                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane, level),
3858                                    &wm->wm[level]);
3859         }
3860         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
3861                            &wm->trans_wm);
3862
3863         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3864                             &ddb->plane[pipe][plane]);
3865         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3866                             &ddb->y_plane[pipe][plane]);
3867 }
3868
3869 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3870                          const struct skl_plane_wm *wm,
3871                          const struct skl_ddb_allocation *ddb)
3872 {
3873         struct drm_crtc *crtc = &intel_crtc->base;
3874         struct drm_device *dev = crtc->dev;
3875         struct drm_i915_private *dev_priv = to_i915(dev);
3876         int level, max_level = ilk_wm_max_level(dev_priv);
3877         enum pipe pipe = intel_crtc->pipe;
3878
3879         for (level = 0; level <= max_level; level++) {
3880                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3881                                    &wm->wm[level]);
3882         }
3883         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
3884
3885         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3886                             &ddb->plane[pipe][PLANE_CURSOR]);
3887 }
3888
3889 bool skl_wm_level_equals(const struct skl_wm_level *l1,
3890                          const struct skl_wm_level *l2)
3891 {
3892         if (l1->plane_en != l2->plane_en)
3893                 return false;
3894
3895         /* If both planes aren't enabled, the rest shouldn't matter */
3896         if (!l1->plane_en)
3897                 return true;
3898
3899         return (l1->plane_res_l == l2->plane_res_l &&
3900                 l1->plane_res_b == l2->plane_res_b);
3901 }
3902
3903 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3904                                            const struct skl_ddb_entry *b)
3905 {
3906         return a->start < b->end && b->start < a->end;
3907 }
3908
3909 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
3910                                  struct intel_crtc *intel_crtc)
3911 {
3912         struct drm_crtc *other_crtc;
3913         struct drm_crtc_state *other_cstate;
3914         struct intel_crtc *other_intel_crtc;
3915         const struct skl_ddb_entry *ddb =
3916                 &to_intel_crtc_state(intel_crtc->base.state)->wm.skl.ddb;
3917         int i;
3918
3919         for_each_crtc_in_state(state, other_crtc, other_cstate, i) {
3920                 other_intel_crtc = to_intel_crtc(other_crtc);
3921
3922                 if (other_intel_crtc == intel_crtc)
3923                         continue;
3924
3925                 if (skl_ddb_entries_overlap(ddb, &other_intel_crtc->hw_ddb))
3926                         return true;
3927         }
3928
3929         return false;
3930 }
3931
3932 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3933                               struct skl_ddb_allocation *ddb, /* out */
3934                               struct skl_pipe_wm *pipe_wm, /* out */
3935                               bool *changed /* out */)
3936 {
3937         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3938         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3939         int ret;
3940
3941         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3942         if (ret)
3943                 return ret;
3944
3945         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3946                 *changed = false;
3947         else
3948                 *changed = true;
3949
3950         return 0;
3951 }
3952
3953 static uint32_t
3954 pipes_modified(struct drm_atomic_state *state)
3955 {
3956         struct drm_crtc *crtc;
3957         struct drm_crtc_state *cstate;
3958         uint32_t i, ret = 0;
3959
3960         for_each_crtc_in_state(state, crtc, cstate, i)
3961                 ret |= drm_crtc_mask(crtc);
3962
3963         return ret;
3964 }
3965
3966 static int
3967 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3968 {
3969         struct drm_atomic_state *state = cstate->base.state;
3970         struct drm_device *dev = state->dev;
3971         struct drm_crtc *crtc = cstate->base.crtc;
3972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3973         struct drm_i915_private *dev_priv = to_i915(dev);
3974         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3975         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3976         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3977         struct drm_plane_state *plane_state;
3978         struct drm_plane *plane;
3979         enum pipe pipe = intel_crtc->pipe;
3980         int id;
3981
3982         WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3983
3984         drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
3985                 id = skl_wm_plane_id(to_intel_plane(plane));
3986
3987                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3988                                         &new_ddb->plane[pipe][id]) &&
3989                     skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3990                                         &new_ddb->y_plane[pipe][id]))
3991                         continue;
3992
3993                 plane_state = drm_atomic_get_plane_state(state, plane);
3994                 if (IS_ERR(plane_state))
3995                         return PTR_ERR(plane_state);
3996         }
3997
3998         return 0;
3999 }
4000
4001 static int
4002 skl_compute_ddb(struct drm_atomic_state *state)
4003 {
4004         struct drm_device *dev = state->dev;
4005         struct drm_i915_private *dev_priv = to_i915(dev);
4006         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4007         struct intel_crtc *intel_crtc;
4008         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4009         uint32_t realloc_pipes = pipes_modified(state);
4010         int ret;
4011
4012         /*
4013          * If this is our first atomic update following hardware readout,
4014          * we can't trust the DDB that the BIOS programmed for us.  Let's
4015          * pretend that all pipes switched active status so that we'll
4016          * ensure a full DDB recompute.
4017          */
4018         if (dev_priv->wm.distrust_bios_wm) {
4019                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4020                                        state->acquire_ctx);
4021                 if (ret)
4022                         return ret;
4023
4024                 intel_state->active_pipe_changes = ~0;
4025
4026                 /*
4027                  * We usually only initialize intel_state->active_crtcs if we
4028                  * we're doing a modeset; make sure this field is always
4029                  * initialized during the sanitization process that happens
4030                  * on the first commit too.
4031                  */
4032                 if (!intel_state->modeset)
4033                         intel_state->active_crtcs = dev_priv->active_crtcs;
4034         }
4035
4036         /*
4037          * If the modeset changes which CRTC's are active, we need to
4038          * recompute the DDB allocation for *all* active pipes, even
4039          * those that weren't otherwise being modified in any way by this
4040          * atomic commit.  Due to the shrinking of the per-pipe allocations
4041          * when new active CRTC's are added, it's possible for a pipe that
4042          * we were already using and aren't changing at all here to suddenly
4043          * become invalid if its DDB needs exceeds its new allocation.
4044          *
4045          * Note that if we wind up doing a full DDB recompute, we can't let
4046          * any other display updates race with this transaction, so we need
4047          * to grab the lock on *all* CRTC's.
4048          */
4049         if (intel_state->active_pipe_changes) {
4050                 realloc_pipes = ~0;
4051                 intel_state->wm_results.dirty_pipes = ~0;
4052         }
4053
4054         /*
4055          * We're not recomputing for the pipes not included in the commit, so
4056          * make sure we start with the current state.
4057          */
4058         memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4059
4060         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4061                 struct intel_crtc_state *cstate;
4062
4063                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4064                 if (IS_ERR(cstate))
4065                         return PTR_ERR(cstate);
4066
4067                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4068                 if (ret)
4069                         return ret;
4070
4071                 ret = skl_ddb_add_affected_planes(cstate);
4072                 if (ret)
4073                         return ret;
4074         }
4075
4076         return 0;
4077 }
4078
4079 static void
4080 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4081                      struct skl_wm_values *src,
4082                      enum pipe pipe)
4083 {
4084         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4085                sizeof(dst->ddb.y_plane[pipe]));
4086         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4087                sizeof(dst->ddb.plane[pipe]));
4088 }
4089
4090 static void
4091 skl_print_wm_changes(const struct drm_atomic_state *state)
4092 {
4093         const struct drm_device *dev = state->dev;
4094         const struct drm_i915_private *dev_priv = to_i915(dev);
4095         const struct intel_atomic_state *intel_state =
4096                 to_intel_atomic_state(state);
4097         const struct drm_crtc *crtc;
4098         const struct drm_crtc_state *cstate;
4099         const struct intel_plane *intel_plane;
4100         const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4101         const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4102         int id;
4103         int i;
4104
4105         for_each_crtc_in_state(state, crtc, cstate, i) {
4106                 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4107                 enum pipe pipe = intel_crtc->pipe;
4108
4109                 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4110                         const struct skl_ddb_entry *old, *new;
4111
4112                         id = skl_wm_plane_id(intel_plane);
4113                         old = &old_ddb->plane[pipe][id];
4114                         new = &new_ddb->plane[pipe][id];
4115
4116                         if (skl_ddb_entry_equal(old, new))
4117                                 continue;
4118
4119                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4120                                          intel_plane->base.base.id,
4121                                          intel_plane->base.name,
4122                                          old->start, old->end,
4123                                          new->start, new->end);
4124                 }
4125         }
4126 }
4127
4128 static int
4129 skl_compute_wm(struct drm_atomic_state *state)
4130 {
4131         struct drm_crtc *crtc;
4132         struct drm_crtc_state *cstate;
4133         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4134         struct skl_wm_values *results = &intel_state->wm_results;
4135         struct skl_pipe_wm *pipe_wm;
4136         bool changed = false;
4137         int ret, i;
4138
4139         /*
4140          * If this transaction isn't actually touching any CRTC's, don't
4141          * bother with watermark calculation.  Note that if we pass this
4142          * test, we're guaranteed to hold at least one CRTC state mutex,
4143          * which means we can safely use values like dev_priv->active_crtcs
4144          * since any racing commits that want to update them would need to
4145          * hold _all_ CRTC state mutexes.
4146          */
4147         for_each_crtc_in_state(state, crtc, cstate, i)
4148                 changed = true;
4149         if (!changed)
4150                 return 0;
4151
4152         /* Clear all dirty flags */
4153         results->dirty_pipes = 0;
4154
4155         ret = skl_compute_ddb(state);
4156         if (ret)
4157                 return ret;
4158
4159         /*
4160          * Calculate WM's for all pipes that are part of this transaction.
4161          * Note that the DDB allocation above may have added more CRTC's that
4162          * weren't otherwise being modified (and set bits in dirty_pipes) if
4163          * pipe allocations had to change.
4164          *
4165          * FIXME:  Now that we're doing this in the atomic check phase, we
4166          * should allow skl_update_pipe_wm() to return failure in cases where
4167          * no suitable watermark values can be found.
4168          */
4169         for_each_crtc_in_state(state, crtc, cstate, i) {
4170                 struct intel_crtc_state *intel_cstate =
4171                         to_intel_crtc_state(cstate);
4172
4173                 pipe_wm = &intel_cstate->wm.skl.optimal;
4174                 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4175                                          &changed);
4176                 if (ret)
4177                         return ret;
4178
4179                 if (changed)
4180                         results->dirty_pipes |= drm_crtc_mask(crtc);
4181
4182                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4183                         /* This pipe's WM's did not change */
4184                         continue;
4185
4186                 intel_cstate->update_wm_pre = true;
4187         }
4188
4189         skl_print_wm_changes(state);
4190
4191         return 0;
4192 }
4193
4194 static void skl_update_wm(struct drm_crtc *crtc)
4195 {
4196         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4197         struct drm_device *dev = crtc->dev;
4198         struct drm_i915_private *dev_priv = to_i915(dev);
4199         struct skl_wm_values *results = &dev_priv->wm.skl_results;
4200         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4201         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4202         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4203         enum pipe pipe = intel_crtc->pipe;
4204
4205         if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4206                 return;
4207
4208         intel_crtc->wm.active.skl = *pipe_wm;
4209
4210         mutex_lock(&dev_priv->wm.wm_mutex);
4211
4212         /*
4213          * If this pipe isn't active already, we're going to be enabling it
4214          * very soon. Since it's safe to update a pipe's ddb allocation while
4215          * the pipe's shut off, just do so here. Already active pipes will have
4216          * their watermarks updated once we update their planes.
4217          */
4218         if (crtc->state->active_changed) {
4219                 int plane;
4220
4221                 for_each_universal_plane(dev_priv, pipe, plane)
4222                         skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane],
4223                                            &results->ddb, plane);
4224
4225                 skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[PLANE_CURSOR],
4226                                     &results->ddb);
4227         }
4228
4229         skl_copy_wm_for_pipe(hw_vals, results, pipe);
4230
4231         intel_crtc->hw_ddb = cstate->wm.skl.ddb;
4232
4233         mutex_unlock(&dev_priv->wm.wm_mutex);
4234 }
4235
4236 static void ilk_compute_wm_config(struct drm_device *dev,
4237                                   struct intel_wm_config *config)
4238 {
4239         struct intel_crtc *crtc;
4240
4241         /* Compute the currently _active_ config */
4242         for_each_intel_crtc(dev, crtc) {
4243                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4244
4245                 if (!wm->pipe_enabled)
4246                         continue;
4247
4248                 config->sprites_enabled |= wm->sprites_enabled;
4249                 config->sprites_scaled |= wm->sprites_scaled;
4250                 config->num_pipes_active++;
4251         }
4252 }
4253
4254 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4255 {
4256         struct drm_device *dev = &dev_priv->drm;
4257         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4258         struct ilk_wm_maximums max;
4259         struct intel_wm_config config = {};
4260         struct ilk_wm_values results = {};
4261         enum intel_ddb_partitioning partitioning;
4262
4263         ilk_compute_wm_config(dev, &config);
4264
4265         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4266         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4267
4268         /* 5/6 split only in single pipe config on IVB+ */
4269         if (INTEL_INFO(dev)->gen >= 7 &&
4270             config.num_pipes_active == 1 && config.sprites_enabled) {
4271                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4272                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4273
4274                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4275         } else {
4276                 best_lp_wm = &lp_wm_1_2;
4277         }
4278
4279         partitioning = (best_lp_wm == &lp_wm_1_2) ?
4280                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4281
4282         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4283
4284         ilk_write_wm_values(dev_priv, &results);
4285 }
4286
4287 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
4288 {
4289         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4290         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4291
4292         mutex_lock(&dev_priv->wm.wm_mutex);
4293         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4294         ilk_program_watermarks(dev_priv);
4295         mutex_unlock(&dev_priv->wm.wm_mutex);
4296 }
4297
4298 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4299 {
4300         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4301         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4302
4303         mutex_lock(&dev_priv->wm.wm_mutex);
4304         if (cstate->wm.need_postvbl_update) {
4305                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4306                 ilk_program_watermarks(dev_priv);
4307         }
4308         mutex_unlock(&dev_priv->wm.wm_mutex);
4309 }
4310
4311 static inline void skl_wm_level_from_reg_val(uint32_t val,
4312                                              struct skl_wm_level *level)
4313 {
4314         level->plane_en = val & PLANE_WM_EN;
4315         level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4316         level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4317                 PLANE_WM_LINES_MASK;
4318 }
4319
4320 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4321                               struct skl_pipe_wm *out)
4322 {
4323         struct drm_device *dev = crtc->dev;
4324         struct drm_i915_private *dev_priv = to_i915(dev);
4325         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4326         struct intel_plane *intel_plane;
4327         struct skl_plane_wm *wm;
4328         enum pipe pipe = intel_crtc->pipe;
4329         int level, id, max_level;
4330         uint32_t val;
4331
4332         max_level = ilk_wm_max_level(dev_priv);
4333
4334         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4335                 id = skl_wm_plane_id(intel_plane);
4336                 wm = &out->planes[id];
4337
4338                 for (level = 0; level <= max_level; level++) {
4339                         if (id != PLANE_CURSOR)
4340                                 val = I915_READ(PLANE_WM(pipe, id, level));
4341                         else
4342                                 val = I915_READ(CUR_WM(pipe, level));
4343
4344                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
4345                 }
4346
4347                 if (id != PLANE_CURSOR)
4348                         val = I915_READ(PLANE_WM_TRANS(pipe, id));
4349                 else
4350                         val = I915_READ(CUR_WM_TRANS(pipe));
4351
4352                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
4353         }
4354
4355         if (!intel_crtc->active)
4356                 return;
4357
4358         out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
4359 }
4360
4361 void skl_wm_get_hw_state(struct drm_device *dev)
4362 {
4363         struct drm_i915_private *dev_priv = to_i915(dev);
4364         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4365         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4366         struct drm_crtc *crtc;
4367         struct intel_crtc *intel_crtc;
4368         struct intel_crtc_state *cstate;
4369
4370         skl_ddb_get_hw_state(dev_priv, ddb);
4371         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4372                 intel_crtc = to_intel_crtc(crtc);
4373                 cstate = to_intel_crtc_state(crtc->state);
4374
4375                 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4376
4377                 if (intel_crtc->active) {
4378                         hw->dirty_pipes |= drm_crtc_mask(crtc);
4379                         intel_crtc->wm.active.skl = cstate->wm.skl.optimal;
4380                 }
4381         }
4382
4383         if (dev_priv->active_crtcs) {
4384                 /* Fully recompute DDB on first atomic commit */
4385                 dev_priv->wm.distrust_bios_wm = true;
4386         } else {
4387                 /* Easy/common case; just sanitize DDB now if everything off */
4388                 memset(ddb, 0, sizeof(*ddb));
4389         }
4390 }
4391
4392 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4393 {
4394         struct drm_device *dev = crtc->dev;
4395         struct drm_i915_private *dev_priv = to_i915(dev);
4396         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4398         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4399         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4400         enum pipe pipe = intel_crtc->pipe;
4401         static const i915_reg_t wm0_pipe_reg[] = {
4402                 [PIPE_A] = WM0_PIPEA_ILK,
4403                 [PIPE_B] = WM0_PIPEB_ILK,
4404                 [PIPE_C] = WM0_PIPEC_IVB,
4405         };
4406
4407         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4408         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4409                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4410
4411         memset(active, 0, sizeof(*active));
4412
4413         active->pipe_enabled = intel_crtc->active;
4414
4415         if (active->pipe_enabled) {
4416                 u32 tmp = hw->wm_pipe[pipe];
4417
4418                 /*
4419                  * For active pipes LP0 watermark is marked as
4420                  * enabled, and LP1+ watermaks as disabled since
4421                  * we can't really reverse compute them in case
4422                  * multiple pipes are active.
4423                  */
4424                 active->wm[0].enable = true;
4425                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4426                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4427                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4428                 active->linetime = hw->wm_linetime[pipe];
4429         } else {
4430                 int level, max_level = ilk_wm_max_level(dev_priv);
4431
4432                 /*
4433                  * For inactive pipes, all watermark levels
4434                  * should be marked as enabled but zeroed,
4435                  * which is what we'd compute them to.
4436                  */
4437                 for (level = 0; level <= max_level; level++)
4438                         active->wm[level].enable = true;
4439         }
4440
4441         intel_crtc->wm.active.ilk = *active;
4442 }
4443
4444 #define _FW_WM(value, plane) \
4445         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4446 #define _FW_WM_VLV(value, plane) \
4447         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4448
4449 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4450                                struct vlv_wm_values *wm)
4451 {
4452         enum pipe pipe;
4453         uint32_t tmp;
4454
4455         for_each_pipe(dev_priv, pipe) {
4456                 tmp = I915_READ(VLV_DDL(pipe));
4457
4458                 wm->ddl[pipe].primary =
4459                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4460                 wm->ddl[pipe].cursor =
4461                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4462                 wm->ddl[pipe].sprite[0] =
4463                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4464                 wm->ddl[pipe].sprite[1] =
4465                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4466         }
4467
4468         tmp = I915_READ(DSPFW1);
4469         wm->sr.plane = _FW_WM(tmp, SR);
4470         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4471         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4472         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4473
4474         tmp = I915_READ(DSPFW2);
4475         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4476         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4477         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4478
4479         tmp = I915_READ(DSPFW3);
4480         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4481
4482         if (IS_CHERRYVIEW(dev_priv)) {
4483                 tmp = I915_READ(DSPFW7_CHV);
4484                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4485                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4486
4487                 tmp = I915_READ(DSPFW8_CHV);
4488                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4489                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4490
4491                 tmp = I915_READ(DSPFW9_CHV);
4492                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4493                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4494
4495                 tmp = I915_READ(DSPHOWM);
4496                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4497                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4498                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4499                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4500                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4501                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4502                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4503                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4504                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4505                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4506         } else {
4507                 tmp = I915_READ(DSPFW7);
4508                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4509                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4510
4511                 tmp = I915_READ(DSPHOWM);
4512                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4513                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4514                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4515                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4516                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4517                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4518                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4519         }
4520 }
4521
4522 #undef _FW_WM
4523 #undef _FW_WM_VLV
4524
4525 void vlv_wm_get_hw_state(struct drm_device *dev)
4526 {
4527         struct drm_i915_private *dev_priv = to_i915(dev);
4528         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4529         struct intel_plane *plane;
4530         enum pipe pipe;
4531         u32 val;
4532
4533         vlv_read_wm_values(dev_priv, wm);
4534
4535         for_each_intel_plane(dev, plane) {
4536                 switch (plane->base.type) {
4537                         int sprite;
4538                 case DRM_PLANE_TYPE_CURSOR:
4539                         plane->wm.fifo_size = 63;
4540                         break;
4541                 case DRM_PLANE_TYPE_PRIMARY:
4542                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4543                         break;
4544                 case DRM_PLANE_TYPE_OVERLAY:
4545                         sprite = plane->plane;
4546                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4547                         break;
4548                 }
4549         }
4550
4551         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4552         wm->level = VLV_WM_LEVEL_PM2;
4553
4554         if (IS_CHERRYVIEW(dev_priv)) {
4555                 mutex_lock(&dev_priv->rps.hw_lock);
4556
4557                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4558                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4559                         wm->level = VLV_WM_LEVEL_PM5;
4560
4561                 /*
4562                  * If DDR DVFS is disabled in the BIOS, Punit
4563                  * will never ack the request. So if that happens
4564                  * assume we don't have to enable/disable DDR DVFS
4565                  * dynamically. To test that just set the REQ_ACK
4566                  * bit to poke the Punit, but don't change the
4567                  * HIGH/LOW bits so that we don't actually change
4568                  * the current state.
4569                  */
4570                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4571                 val |= FORCE_DDR_FREQ_REQ_ACK;
4572                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4573
4574                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4575                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4576                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4577                                       "assuming DDR DVFS is disabled\n");
4578                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4579                 } else {
4580                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4581                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4582                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4583                 }
4584
4585                 mutex_unlock(&dev_priv->rps.hw_lock);
4586         }
4587
4588         for_each_pipe(dev_priv, pipe)
4589                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4590                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4591                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4592
4593         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4594                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4595 }
4596
4597 void ilk_wm_get_hw_state(struct drm_device *dev)
4598 {
4599         struct drm_i915_private *dev_priv = to_i915(dev);
4600         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4601         struct drm_crtc *crtc;
4602
4603         for_each_crtc(dev, crtc)
4604                 ilk_pipe_wm_get_hw_state(crtc);
4605
4606         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4607         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4608         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4609
4610         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4611         if (INTEL_INFO(dev)->gen >= 7) {
4612                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4613                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4614         }
4615
4616         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4617                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4618                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4619         else if (IS_IVYBRIDGE(dev_priv))
4620                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4621                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4622
4623         hw->enable_fbc_wm =
4624                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4625 }
4626
4627 /**
4628  * intel_update_watermarks - update FIFO watermark values based on current modes
4629  *
4630  * Calculate watermark values for the various WM regs based on current mode
4631  * and plane configuration.
4632  *
4633  * There are several cases to deal with here:
4634  *   - normal (i.e. non-self-refresh)
4635  *   - self-refresh (SR) mode
4636  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4637  *   - lines are small relative to FIFO size (buffer can hold more than 2
4638  *     lines), so need to account for TLB latency
4639  *
4640  *   The normal calculation is:
4641  *     watermark = dotclock * bytes per pixel * latency
4642  *   where latency is platform & configuration dependent (we assume pessimal
4643  *   values here).
4644  *
4645  *   The SR calculation is:
4646  *     watermark = (trunc(latency/line time)+1) * surface width *
4647  *       bytes per pixel
4648  *   where
4649  *     line time = htotal / dotclock
4650  *     surface width = hdisplay for normal plane and 64 for cursor
4651  *   and latency is assumed to be high, as above.
4652  *
4653  * The final value programmed to the register should always be rounded up,
4654  * and include an extra 2 entries to account for clock crossings.
4655  *
4656  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4657  * to set the non-SR watermarks to 8.
4658  */
4659 void intel_update_watermarks(struct drm_crtc *crtc)
4660 {
4661         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4662
4663         if (dev_priv->display.update_wm)
4664                 dev_priv->display.update_wm(crtc);
4665 }
4666
4667 /*
4668  * Lock protecting IPS related data structures
4669  */
4670 DEFINE_SPINLOCK(mchdev_lock);
4671
4672 /* Global for IPS driver to get at the current i915 device. Protected by
4673  * mchdev_lock. */
4674 static struct drm_i915_private *i915_mch_dev;
4675
4676 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4677 {
4678         u16 rgvswctl;
4679
4680         assert_spin_locked(&mchdev_lock);
4681
4682         rgvswctl = I915_READ16(MEMSWCTL);
4683         if (rgvswctl & MEMCTL_CMD_STS) {
4684                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4685                 return false; /* still busy with another command */
4686         }
4687
4688         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4689                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4690         I915_WRITE16(MEMSWCTL, rgvswctl);
4691         POSTING_READ16(MEMSWCTL);
4692
4693         rgvswctl |= MEMCTL_CMD_STS;
4694         I915_WRITE16(MEMSWCTL, rgvswctl);
4695
4696         return true;
4697 }
4698
4699 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4700 {
4701         u32 rgvmodectl;
4702         u8 fmax, fmin, fstart, vstart;
4703
4704         spin_lock_irq(&mchdev_lock);
4705
4706         rgvmodectl = I915_READ(MEMMODECTL);
4707
4708         /* Enable temp reporting */
4709         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4710         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4711
4712         /* 100ms RC evaluation intervals */
4713         I915_WRITE(RCUPEI, 100000);
4714         I915_WRITE(RCDNEI, 100000);
4715
4716         /* Set max/min thresholds to 90ms and 80ms respectively */
4717         I915_WRITE(RCBMAXAVG, 90000);
4718         I915_WRITE(RCBMINAVG, 80000);
4719
4720         I915_WRITE(MEMIHYST, 1);
4721
4722         /* Set up min, max, and cur for interrupt handling */
4723         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4724         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4725         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4726                 MEMMODE_FSTART_SHIFT;
4727
4728         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4729                 PXVFREQ_PX_SHIFT;
4730
4731         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4732         dev_priv->ips.fstart = fstart;
4733
4734         dev_priv->ips.max_delay = fstart;
4735         dev_priv->ips.min_delay = fmin;
4736         dev_priv->ips.cur_delay = fstart;
4737
4738         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4739                          fmax, fmin, fstart);
4740
4741         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4742
4743         /*
4744          * Interrupts will be enabled in ironlake_irq_postinstall
4745          */
4746
4747         I915_WRITE(VIDSTART, vstart);
4748         POSTING_READ(VIDSTART);
4749
4750         rgvmodectl |= MEMMODE_SWMODE_EN;
4751         I915_WRITE(MEMMODECTL, rgvmodectl);
4752
4753         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4754                 DRM_ERROR("stuck trying to change perf mode\n");
4755         mdelay(1);
4756
4757         ironlake_set_drps(dev_priv, fstart);
4758
4759         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4760                 I915_READ(DDREC) + I915_READ(CSIEC);
4761         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4762         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4763         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4764
4765         spin_unlock_irq(&mchdev_lock);
4766 }
4767
4768 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4769 {
4770         u16 rgvswctl;
4771
4772         spin_lock_irq(&mchdev_lock);
4773
4774         rgvswctl = I915_READ16(MEMSWCTL);
4775
4776         /* Ack interrupts, disable EFC interrupt */
4777         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4778         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4779         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4780         I915_WRITE(DEIIR, DE_PCU_EVENT);
4781         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4782
4783         /* Go back to the starting frequency */
4784         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4785         mdelay(1);
4786         rgvswctl |= MEMCTL_CMD_STS;
4787         I915_WRITE(MEMSWCTL, rgvswctl);
4788         mdelay(1);
4789
4790         spin_unlock_irq(&mchdev_lock);
4791 }
4792
4793 /* There's a funny hw issue where the hw returns all 0 when reading from
4794  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4795  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4796  * all limits and the gpu stuck at whatever frequency it is at atm).
4797  */
4798 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4799 {
4800         u32 limits;
4801
4802         /* Only set the down limit when we've reached the lowest level to avoid
4803          * getting more interrupts, otherwise leave this clear. This prevents a
4804          * race in the hw when coming out of rc6: There's a tiny window where
4805          * the hw runs at the minimal clock before selecting the desired
4806          * frequency, if the down threshold expires in that window we will not
4807          * receive a down interrupt. */
4808         if (IS_GEN9(dev_priv)) {
4809                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4810                 if (val <= dev_priv->rps.min_freq_softlimit)
4811                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4812         } else {
4813                 limits = dev_priv->rps.max_freq_softlimit << 24;
4814                 if (val <= dev_priv->rps.min_freq_softlimit)
4815                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4816         }
4817
4818         return limits;
4819 }
4820
4821 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4822 {
4823         int new_power;
4824         u32 threshold_up = 0, threshold_down = 0; /* in % */
4825         u32 ei_up = 0, ei_down = 0;
4826
4827         new_power = dev_priv->rps.power;
4828         switch (dev_priv->rps.power) {
4829         case LOW_POWER:
4830                 if (val > dev_priv->rps.efficient_freq + 1 &&
4831                     val > dev_priv->rps.cur_freq)
4832                         new_power = BETWEEN;
4833                 break;
4834
4835         case BETWEEN:
4836                 if (val <= dev_priv->rps.efficient_freq &&
4837                     val < dev_priv->rps.cur_freq)
4838                         new_power = LOW_POWER;
4839                 else if (val >= dev_priv->rps.rp0_freq &&
4840                          val > dev_priv->rps.cur_freq)
4841                         new_power = HIGH_POWER;
4842                 break;
4843
4844         case HIGH_POWER:
4845                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4846                     val < dev_priv->rps.cur_freq)
4847                         new_power = BETWEEN;
4848                 break;
4849         }
4850         /* Max/min bins are special */
4851         if (val <= dev_priv->rps.min_freq_softlimit)
4852                 new_power = LOW_POWER;
4853         if (val >= dev_priv->rps.max_freq_softlimit)
4854                 new_power = HIGH_POWER;
4855         if (new_power == dev_priv->rps.power)
4856                 return;
4857
4858         /* Note the units here are not exactly 1us, but 1280ns. */
4859         switch (new_power) {
4860         case LOW_POWER:
4861                 /* Upclock if more than 95% busy over 16ms */
4862                 ei_up = 16000;
4863                 threshold_up = 95;
4864
4865                 /* Downclock if less than 85% busy over 32ms */
4866                 ei_down = 32000;
4867                 threshold_down = 85;
4868                 break;
4869
4870         case BETWEEN:
4871                 /* Upclock if more than 90% busy over 13ms */
4872                 ei_up = 13000;
4873                 threshold_up = 90;
4874
4875                 /* Downclock if less than 75% busy over 32ms */
4876                 ei_down = 32000;
4877                 threshold_down = 75;
4878                 break;
4879
4880         case HIGH_POWER:
4881                 /* Upclock if more than 85% busy over 10ms */
4882                 ei_up = 10000;
4883                 threshold_up = 85;
4884
4885                 /* Downclock if less than 60% busy over 32ms */
4886                 ei_down = 32000;
4887                 threshold_down = 60;
4888                 break;
4889         }
4890
4891         I915_WRITE(GEN6_RP_UP_EI,
4892                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
4893         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4894                    GT_INTERVAL_FROM_US(dev_priv,
4895                                        ei_up * threshold_up / 100));
4896
4897         I915_WRITE(GEN6_RP_DOWN_EI,
4898                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
4899         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4900                    GT_INTERVAL_FROM_US(dev_priv,
4901                                        ei_down * threshold_down / 100));
4902
4903         I915_WRITE(GEN6_RP_CONTROL,
4904                    GEN6_RP_MEDIA_TURBO |
4905                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4906                    GEN6_RP_MEDIA_IS_GFX |
4907                    GEN6_RP_ENABLE |
4908                    GEN6_RP_UP_BUSY_AVG |
4909                    GEN6_RP_DOWN_IDLE_AVG);
4910
4911         dev_priv->rps.power = new_power;
4912         dev_priv->rps.up_threshold = threshold_up;
4913         dev_priv->rps.down_threshold = threshold_down;
4914         dev_priv->rps.last_adj = 0;
4915 }
4916
4917 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4918 {
4919         u32 mask = 0;
4920
4921         if (val > dev_priv->rps.min_freq_softlimit)
4922                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4923         if (val < dev_priv->rps.max_freq_softlimit)
4924                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4925
4926         mask &= dev_priv->pm_rps_events;
4927
4928         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4929 }
4930
4931 /* gen6_set_rps is called to update the frequency request, but should also be
4932  * called when the range (min_delay and max_delay) is modified so that we can
4933  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4934 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4935 {
4936         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4937         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4938                 return;
4939
4940         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4941         WARN_ON(val > dev_priv->rps.max_freq);
4942         WARN_ON(val < dev_priv->rps.min_freq);
4943
4944         /* min/max delay may still have been modified so be sure to
4945          * write the limits value.
4946          */
4947         if (val != dev_priv->rps.cur_freq) {
4948                 gen6_set_rps_thresholds(dev_priv, val);
4949
4950                 if (IS_GEN9(dev_priv))
4951                         I915_WRITE(GEN6_RPNSWREQ,
4952                                    GEN9_FREQUENCY(val));
4953                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4954                         I915_WRITE(GEN6_RPNSWREQ,
4955                                    HSW_FREQUENCY(val));
4956                 else
4957                         I915_WRITE(GEN6_RPNSWREQ,
4958                                    GEN6_FREQUENCY(val) |
4959                                    GEN6_OFFSET(0) |
4960                                    GEN6_AGGRESSIVE_TURBO);
4961         }
4962
4963         /* Make sure we continue to get interrupts
4964          * until we hit the minimum or maximum frequencies.
4965          */
4966         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4967         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4968
4969         POSTING_READ(GEN6_RPNSWREQ);
4970
4971         dev_priv->rps.cur_freq = val;
4972         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4973 }
4974
4975 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4976 {
4977         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4978         WARN_ON(val > dev_priv->rps.max_freq);
4979         WARN_ON(val < dev_priv->rps.min_freq);
4980
4981         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4982                       "Odd GPU freq value\n"))
4983                 val &= ~1;
4984
4985         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4986
4987         if (val != dev_priv->rps.cur_freq) {
4988                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4989                 if (!IS_CHERRYVIEW(dev_priv))
4990                         gen6_set_rps_thresholds(dev_priv, val);
4991         }
4992
4993         dev_priv->rps.cur_freq = val;
4994         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4995 }
4996
4997 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4998  *
4999  * * If Gfx is Idle, then
5000  * 1. Forcewake Media well.
5001  * 2. Request idle freq.
5002  * 3. Release Forcewake of Media well.
5003 */
5004 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5005 {
5006         u32 val = dev_priv->rps.idle_freq;
5007
5008         if (dev_priv->rps.cur_freq <= val)
5009                 return;
5010
5011         /* Wake up the media well, as that takes a lot less
5012          * power than the Render well. */
5013         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5014         valleyview_set_rps(dev_priv, val);
5015         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5016 }
5017
5018 void gen6_rps_busy(struct drm_i915_private *dev_priv)
5019 {
5020         mutex_lock(&dev_priv->rps.hw_lock);
5021         if (dev_priv->rps.enabled) {
5022                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5023                         gen6_rps_reset_ei(dev_priv);
5024                 I915_WRITE(GEN6_PMINTRMSK,
5025                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5026
5027                 gen6_enable_rps_interrupts(dev_priv);
5028
5029                 /* Ensure we start at the user's desired frequency */
5030                 intel_set_rps(dev_priv,
5031                               clamp(dev_priv->rps.cur_freq,
5032                                     dev_priv->rps.min_freq_softlimit,
5033                                     dev_priv->rps.max_freq_softlimit));
5034         }
5035         mutex_unlock(&dev_priv->rps.hw_lock);
5036 }
5037
5038 void gen6_rps_idle(struct drm_i915_private *dev_priv)
5039 {
5040         /* Flush our bottom-half so that it does not race with us
5041          * setting the idle frequency and so that it is bounded by
5042          * our rpm wakeref. And then disable the interrupts to stop any
5043          * futher RPS reclocking whilst we are asleep.
5044          */
5045         gen6_disable_rps_interrupts(dev_priv);
5046
5047         mutex_lock(&dev_priv->rps.hw_lock);
5048         if (dev_priv->rps.enabled) {
5049                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5050                         vlv_set_rps_idle(dev_priv);
5051                 else
5052                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5053                 dev_priv->rps.last_adj = 0;
5054                 I915_WRITE(GEN6_PMINTRMSK,
5055                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5056         }
5057         mutex_unlock(&dev_priv->rps.hw_lock);
5058
5059         spin_lock(&dev_priv->rps.client_lock);
5060         while (!list_empty(&dev_priv->rps.clients))
5061                 list_del_init(dev_priv->rps.clients.next);
5062         spin_unlock(&dev_priv->rps.client_lock);
5063 }
5064
5065 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5066                     struct intel_rps_client *rps,
5067                     unsigned long submitted)
5068 {
5069         /* This is intentionally racy! We peek at the state here, then
5070          * validate inside the RPS worker.
5071          */
5072         if (!(dev_priv->gt.awake &&
5073               dev_priv->rps.enabled &&
5074               dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5075                 return;
5076
5077         /* Force a RPS boost (and don't count it against the client) if
5078          * the GPU is severely congested.
5079          */
5080         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5081                 rps = NULL;
5082
5083         spin_lock(&dev_priv->rps.client_lock);
5084         if (rps == NULL || list_empty(&rps->link)) {
5085                 spin_lock_irq(&dev_priv->irq_lock);
5086                 if (dev_priv->rps.interrupts_enabled) {
5087                         dev_priv->rps.client_boost = true;
5088                         schedule_work(&dev_priv->rps.work);
5089                 }
5090                 spin_unlock_irq(&dev_priv->irq_lock);
5091
5092                 if (rps != NULL) {
5093                         list_add(&rps->link, &dev_priv->rps.clients);
5094                         rps->boosts++;
5095                 } else
5096                         dev_priv->rps.boosts++;
5097         }
5098         spin_unlock(&dev_priv->rps.client_lock);
5099 }
5100
5101 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5102 {
5103         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5104                 valleyview_set_rps(dev_priv, val);
5105         else
5106                 gen6_set_rps(dev_priv, val);
5107 }
5108
5109 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5110 {
5111         I915_WRITE(GEN6_RC_CONTROL, 0);
5112         I915_WRITE(GEN9_PG_ENABLE, 0);
5113 }
5114
5115 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5116 {
5117         I915_WRITE(GEN6_RP_CONTROL, 0);
5118 }
5119
5120 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5121 {
5122         I915_WRITE(GEN6_RC_CONTROL, 0);
5123         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5124         I915_WRITE(GEN6_RP_CONTROL, 0);
5125 }
5126
5127 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5128 {
5129         I915_WRITE(GEN6_RC_CONTROL, 0);
5130 }
5131
5132 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5133 {
5134         /* we're doing forcewake before Disabling RC6,
5135          * This what the BIOS expects when going into suspend */
5136         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5137
5138         I915_WRITE(GEN6_RC_CONTROL, 0);
5139
5140         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5141 }
5142
5143 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5144 {
5145         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5146                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5147                         mode = GEN6_RC_CTL_RC6_ENABLE;
5148                 else
5149                         mode = 0;
5150         }
5151         if (HAS_RC6p(dev_priv))
5152                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5153                                  "RC6 %s RC6p %s RC6pp %s\n",
5154                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5155                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5156                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5157
5158         else
5159                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5160                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5161 }
5162
5163 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5164 {
5165         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5166         bool enable_rc6 = true;
5167         unsigned long rc6_ctx_base;
5168         u32 rc_ctl;
5169         int rc_sw_target;
5170
5171         rc_ctl = I915_READ(GEN6_RC_CONTROL);
5172         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5173                        RC_SW_TARGET_STATE_SHIFT;
5174         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5175                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5176                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5177                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5178                          rc_sw_target);
5179
5180         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5181                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5182                 enable_rc6 = false;
5183         }
5184
5185         /*
5186          * The exact context size is not known for BXT, so assume a page size
5187          * for this check.
5188          */
5189         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5190         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5191               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5192                                         ggtt->stolen_reserved_size))) {
5193                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5194                 enable_rc6 = false;
5195         }
5196
5197         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5198               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5199               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5200               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5201                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5202                 enable_rc6 = false;
5203         }
5204
5205         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5206             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5207             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5208                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5209                 enable_rc6 = false;
5210         }
5211
5212         if (!I915_READ(GEN6_GFXPAUSE)) {
5213                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5214                 enable_rc6 = false;
5215         }
5216
5217         if (!I915_READ(GEN8_MISC_CTRL0)) {
5218                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5219                 enable_rc6 = false;
5220         }
5221
5222         return enable_rc6;
5223 }
5224
5225 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5226 {
5227         /* No RC6 before Ironlake and code is gone for ilk. */
5228         if (INTEL_INFO(dev_priv)->gen < 6)
5229                 return 0;
5230
5231         if (!enable_rc6)
5232                 return 0;
5233
5234         if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5235                 DRM_INFO("RC6 disabled by BIOS\n");
5236                 return 0;
5237         }
5238
5239         /* Respect the kernel parameter if it is set */
5240         if (enable_rc6 >= 0) {
5241                 int mask;
5242
5243                 if (HAS_RC6p(dev_priv))
5244                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5245                                INTEL_RC6pp_ENABLE;
5246                 else
5247                         mask = INTEL_RC6_ENABLE;
5248
5249                 if ((enable_rc6 & mask) != enable_rc6)
5250                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5251                                          "(requested %d, valid %d)\n",
5252                                          enable_rc6 & mask, enable_rc6, mask);
5253
5254                 return enable_rc6 & mask;
5255         }
5256
5257         if (IS_IVYBRIDGE(dev_priv))
5258                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5259
5260         return INTEL_RC6_ENABLE;
5261 }
5262
5263 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5264 {
5265         /* All of these values are in units of 50MHz */
5266
5267         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5268         if (IS_BROXTON(dev_priv)) {
5269                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5270                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5271                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5272                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
5273         } else {
5274                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5275                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
5276                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5277                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5278         }
5279         /* hw_max = RP0 until we check for overclocking */
5280         dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5281
5282         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5283         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5284             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5285                 u32 ddcc_status = 0;
5286
5287                 if (sandybridge_pcode_read(dev_priv,
5288                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5289                                            &ddcc_status) == 0)
5290                         dev_priv->rps.efficient_freq =
5291                                 clamp_t(u8,
5292                                         ((ddcc_status >> 8) & 0xff),
5293                                         dev_priv->rps.min_freq,
5294                                         dev_priv->rps.max_freq);
5295         }
5296
5297         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5298                 /* Store the frequency values in 16.66 MHZ units, which is
5299                  * the natural hardware unit for SKL
5300                  */
5301                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5302                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5303                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5304                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5305                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5306         }
5307 }
5308
5309 static void reset_rps(struct drm_i915_private *dev_priv,
5310                       void (*set)(struct drm_i915_private *, u8))
5311 {
5312         u8 freq = dev_priv->rps.cur_freq;
5313
5314         /* force a reset */
5315         dev_priv->rps.power = -1;
5316         dev_priv->rps.cur_freq = -1;
5317
5318         set(dev_priv, freq);
5319 }
5320
5321 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5322 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5323 {
5324         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5325
5326         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5327         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5328                 /*
5329                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
5330                  * clear out the Control register just to avoid inconsitency
5331                  * with debugfs interface, which will show  Turbo as enabled
5332                  * only and that is not expected by the User after adding the
5333                  * WaGsvDisableTurbo. Apart from this there is no problem even
5334                  * if the Turbo is left enabled in the Control register, as the
5335                  * Up/Down interrupts would remain masked.
5336                  */
5337                 gen9_disable_rps(dev_priv);
5338                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5339                 return;
5340         }
5341
5342         /* Program defaults and thresholds for RPS*/
5343         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5344                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5345
5346         /* 1 second timeout*/
5347         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5348                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5349
5350         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5351
5352         /* Leaning on the below call to gen6_set_rps to program/setup the
5353          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5354          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5355         reset_rps(dev_priv, gen6_set_rps);
5356
5357         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5358 }
5359
5360 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5361 {
5362         struct intel_engine_cs *engine;
5363         enum intel_engine_id id;
5364         uint32_t rc6_mask = 0;
5365
5366         /* 1a: Software RC state - RC0 */
5367         I915_WRITE(GEN6_RC_STATE, 0);
5368
5369         /* 1b: Get forcewake during program sequence. Although the driver
5370          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5371         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5372
5373         /* 2a: Disable RC states. */
5374         I915_WRITE(GEN6_RC_CONTROL, 0);
5375
5376         /* 2b: Program RC6 thresholds.*/
5377
5378         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5379         if (IS_SKYLAKE(dev_priv))
5380                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5381         else
5382                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5383         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5384         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5385         for_each_engine(engine, dev_priv, id)
5386                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5387
5388         if (HAS_GUC(dev_priv))
5389                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5390
5391         I915_WRITE(GEN6_RC_SLEEP, 0);
5392
5393         /* 2c: Program Coarse Power Gating Policies. */
5394         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5395         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5396
5397         /* 3a: Enable RC6 */
5398         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5399                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5400         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5401         /* WaRsUseTimeoutMode:bxt */
5402         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5403                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5404                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5405                            GEN7_RC_CTL_TO_MODE |
5406                            rc6_mask);
5407         } else {
5408                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5409                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5410                            GEN6_RC_CTL_EI_MODE(1) |
5411                            rc6_mask);
5412         }
5413
5414         /*
5415          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5416          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5417          */
5418         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5419                 I915_WRITE(GEN9_PG_ENABLE, 0);
5420         else
5421                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5422                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5423
5424         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5425 }
5426
5427 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5428 {
5429         struct intel_engine_cs *engine;
5430         enum intel_engine_id id;
5431         uint32_t rc6_mask = 0;
5432
5433         /* 1a: Software RC state - RC0 */
5434         I915_WRITE(GEN6_RC_STATE, 0);
5435
5436         /* 1c & 1d: Get forcewake during program sequence. Although the driver
5437          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5438         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5439
5440         /* 2a: Disable RC states. */
5441         I915_WRITE(GEN6_RC_CONTROL, 0);
5442
5443         /* 2b: Program RC6 thresholds.*/
5444         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5445         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5446         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5447         for_each_engine(engine, dev_priv, id)
5448                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5449         I915_WRITE(GEN6_RC_SLEEP, 0);
5450         if (IS_BROADWELL(dev_priv))
5451                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5452         else
5453                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5454
5455         /* 3: Enable RC6 */
5456         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5457                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5458         intel_print_rc6_info(dev_priv, rc6_mask);
5459         if (IS_BROADWELL(dev_priv))
5460                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5461                                 GEN7_RC_CTL_TO_MODE |
5462                                 rc6_mask);
5463         else
5464                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5465                                 GEN6_RC_CTL_EI_MODE(1) |
5466                                 rc6_mask);
5467
5468         /* 4 Program defaults and thresholds for RPS*/
5469         I915_WRITE(GEN6_RPNSWREQ,
5470                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5471         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5472                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5473         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5474         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5475
5476         /* Docs recommend 900MHz, and 300 MHz respectively */
5477         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5478                    dev_priv->rps.max_freq_softlimit << 24 |
5479                    dev_priv->rps.min_freq_softlimit << 16);
5480
5481         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5482         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5483         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5484         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5485
5486         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5487
5488         /* 5: Enable RPS */
5489         I915_WRITE(GEN6_RP_CONTROL,
5490                    GEN6_RP_MEDIA_TURBO |
5491                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5492                    GEN6_RP_MEDIA_IS_GFX |
5493                    GEN6_RP_ENABLE |
5494                    GEN6_RP_UP_BUSY_AVG |
5495                    GEN6_RP_DOWN_IDLE_AVG);
5496
5497         /* 6: Ring frequency + overclocking (our driver does this later */
5498
5499         reset_rps(dev_priv, gen6_set_rps);
5500
5501         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5502 }
5503
5504 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5505 {
5506         struct intel_engine_cs *engine;
5507         enum intel_engine_id id;
5508         u32 rc6vids, rc6_mask = 0;
5509         u32 gtfifodbg;
5510         int rc6_mode;
5511         int ret;
5512
5513         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5514
5515         /* Here begins a magic sequence of register writes to enable
5516          * auto-downclocking.
5517          *
5518          * Perhaps there might be some value in exposing these to
5519          * userspace...
5520          */
5521         I915_WRITE(GEN6_RC_STATE, 0);
5522
5523         /* Clear the DBG now so we don't confuse earlier errors */
5524         gtfifodbg = I915_READ(GTFIFODBG);
5525         if (gtfifodbg) {
5526                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5527                 I915_WRITE(GTFIFODBG, gtfifodbg);
5528         }
5529
5530         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5531
5532         /* disable the counters and set deterministic thresholds */
5533         I915_WRITE(GEN6_RC_CONTROL, 0);
5534
5535         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5536         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5537         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5538         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5539         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5540
5541         for_each_engine(engine, dev_priv, id)
5542                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5543
5544         I915_WRITE(GEN6_RC_SLEEP, 0);
5545         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5546         if (IS_IVYBRIDGE(dev_priv))
5547                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5548         else
5549                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5550         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5551         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5552
5553         /* Check if we are enabling RC6 */
5554         rc6_mode = intel_enable_rc6();
5555         if (rc6_mode & INTEL_RC6_ENABLE)
5556                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5557
5558         /* We don't use those on Haswell */
5559         if (!IS_HASWELL(dev_priv)) {
5560                 if (rc6_mode & INTEL_RC6p_ENABLE)
5561                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5562
5563                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5564                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5565         }
5566
5567         intel_print_rc6_info(dev_priv, rc6_mask);
5568
5569         I915_WRITE(GEN6_RC_CONTROL,
5570                    rc6_mask |
5571                    GEN6_RC_CTL_EI_MODE(1) |
5572                    GEN6_RC_CTL_HW_ENABLE);
5573
5574         /* Power down if completely idle for over 50ms */
5575         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5576         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5577
5578         reset_rps(dev_priv, gen6_set_rps);
5579
5580         rc6vids = 0;
5581         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5582         if (IS_GEN6(dev_priv) && ret) {
5583                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5584         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5585                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5586                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5587                 rc6vids &= 0xffff00;
5588                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5589                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5590                 if (ret)
5591                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5592         }
5593
5594         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5595 }
5596
5597 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5598 {
5599         int min_freq = 15;
5600         unsigned int gpu_freq;
5601         unsigned int max_ia_freq, min_ring_freq;
5602         unsigned int max_gpu_freq, min_gpu_freq;
5603         int scaling_factor = 180;
5604         struct cpufreq_policy *policy;
5605
5606         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5607
5608         policy = cpufreq_cpu_get(0);
5609         if (policy) {
5610                 max_ia_freq = policy->cpuinfo.max_freq;
5611                 cpufreq_cpu_put(policy);
5612         } else {
5613                 /*
5614                  * Default to measured freq if none found, PCU will ensure we
5615                  * don't go over
5616                  */
5617                 max_ia_freq = tsc_khz;
5618         }
5619
5620         /* Convert from kHz to MHz */
5621         max_ia_freq /= 1000;
5622
5623         min_ring_freq = I915_READ(DCLK) & 0xf;
5624         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5625         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5626
5627         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5628                 /* Convert GT frequency to 50 HZ units */
5629                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5630                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5631         } else {
5632                 min_gpu_freq = dev_priv->rps.min_freq;
5633                 max_gpu_freq = dev_priv->rps.max_freq;
5634         }
5635
5636         /*
5637          * For each potential GPU frequency, load a ring frequency we'd like
5638          * to use for memory access.  We do this by specifying the IA frequency
5639          * the PCU should use as a reference to determine the ring frequency.
5640          */
5641         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5642                 int diff = max_gpu_freq - gpu_freq;
5643                 unsigned int ia_freq = 0, ring_freq = 0;
5644
5645                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5646                         /*
5647                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5648                          * No floor required for ring frequency on SKL.
5649                          */
5650                         ring_freq = gpu_freq;
5651                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5652                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5653                         ring_freq = max(min_ring_freq, gpu_freq);
5654                 } else if (IS_HASWELL(dev_priv)) {
5655                         ring_freq = mult_frac(gpu_freq, 5, 4);
5656                         ring_freq = max(min_ring_freq, ring_freq);
5657                         /* leave ia_freq as the default, chosen by cpufreq */
5658                 } else {
5659                         /* On older processors, there is no separate ring
5660                          * clock domain, so in order to boost the bandwidth
5661                          * of the ring, we need to upclock the CPU (ia_freq).
5662                          *
5663                          * For GPU frequencies less than 750MHz,
5664                          * just use the lowest ring freq.
5665                          */
5666                         if (gpu_freq < min_freq)
5667                                 ia_freq = 800;
5668                         else
5669                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5670                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5671                 }
5672
5673                 sandybridge_pcode_write(dev_priv,
5674                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5675                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5676                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5677                                         gpu_freq);
5678         }
5679 }
5680
5681 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5682 {
5683         u32 val, rp0;
5684
5685         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5686
5687         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5688         case 8:
5689                 /* (2 * 4) config */
5690                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5691                 break;
5692         case 12:
5693                 /* (2 * 6) config */
5694                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5695                 break;
5696         case 16:
5697                 /* (2 * 8) config */
5698         default:
5699                 /* Setting (2 * 8) Min RP0 for any other combination */
5700                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5701                 break;
5702         }
5703
5704         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5705
5706         return rp0;
5707 }
5708
5709 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5710 {
5711         u32 val, rpe;
5712
5713         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5714         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5715
5716         return rpe;
5717 }
5718
5719 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5720 {
5721         u32 val, rp1;
5722
5723         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5724         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5725
5726         return rp1;
5727 }
5728
5729 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5730 {
5731         u32 val, rp1;
5732
5733         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5734
5735         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5736
5737         return rp1;
5738 }
5739
5740 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5741 {
5742         u32 val, rp0;
5743
5744         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5745
5746         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5747         /* Clamp to max */
5748         rp0 = min_t(u32, rp0, 0xea);
5749
5750         return rp0;
5751 }
5752
5753 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5754 {
5755         u32 val, rpe;
5756
5757         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5758         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5759         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5760         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5761
5762         return rpe;
5763 }
5764
5765 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5766 {
5767         u32 val;
5768
5769         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5770         /*
5771          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5772          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5773          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5774          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5775          * to make sure it matches what Punit accepts.
5776          */
5777         return max_t(u32, val, 0xc0);
5778 }
5779
5780 /* Check that the pctx buffer wasn't move under us. */
5781 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5782 {
5783         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5784
5785         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5786                              dev_priv->vlv_pctx->stolen->start);
5787 }
5788
5789
5790 /* Check that the pcbr address is not empty. */
5791 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5792 {
5793         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5794
5795         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5796 }
5797
5798 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5799 {
5800         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5801         unsigned long pctx_paddr, paddr;
5802         u32 pcbr;
5803         int pctx_size = 32*1024;
5804
5805         pcbr = I915_READ(VLV_PCBR);
5806         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5807                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5808                 paddr = (dev_priv->mm.stolen_base +
5809                          (ggtt->stolen_size - pctx_size));
5810
5811                 pctx_paddr = (paddr & (~4095));
5812                 I915_WRITE(VLV_PCBR, pctx_paddr);
5813         }
5814
5815         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5816 }
5817
5818 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5819 {
5820         struct drm_i915_gem_object *pctx;
5821         unsigned long pctx_paddr;
5822         u32 pcbr;
5823         int pctx_size = 24*1024;
5824
5825         pcbr = I915_READ(VLV_PCBR);
5826         if (pcbr) {
5827                 /* BIOS set it up already, grab the pre-alloc'd space */
5828                 int pcbr_offset;
5829
5830                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5831                 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
5832                                                                       pcbr_offset,
5833                                                                       I915_GTT_OFFSET_NONE,
5834                                                                       pctx_size);
5835                 goto out;
5836         }
5837
5838         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5839
5840         /*
5841          * From the Gunit register HAS:
5842          * The Gfx driver is expected to program this register and ensure
5843          * proper allocation within Gfx stolen memory.  For example, this
5844          * register should be programmed such than the PCBR range does not
5845          * overlap with other ranges, such as the frame buffer, protected
5846          * memory, or any other relevant ranges.
5847          */
5848         pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
5849         if (!pctx) {
5850                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5851                 goto out;
5852         }
5853
5854         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5855         I915_WRITE(VLV_PCBR, pctx_paddr);
5856
5857 out:
5858         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5859         dev_priv->vlv_pctx = pctx;
5860 }
5861
5862 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5863 {
5864         if (WARN_ON(!dev_priv->vlv_pctx))
5865                 return;
5866
5867         i915_gem_object_put(dev_priv->vlv_pctx);
5868         dev_priv->vlv_pctx = NULL;
5869 }
5870
5871 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5872 {
5873         dev_priv->rps.gpll_ref_freq =
5874                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5875                                   CCK_GPLL_CLOCK_CONTROL,
5876                                   dev_priv->czclk_freq);
5877
5878         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5879                          dev_priv->rps.gpll_ref_freq);
5880 }
5881
5882 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5883 {
5884         u32 val;
5885
5886         valleyview_setup_pctx(dev_priv);
5887
5888         vlv_init_gpll_ref_freq(dev_priv);
5889
5890         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5891         switch ((val >> 6) & 3) {
5892         case 0:
5893         case 1:
5894                 dev_priv->mem_freq = 800;
5895                 break;
5896         case 2:
5897                 dev_priv->mem_freq = 1066;
5898                 break;
5899         case 3:
5900                 dev_priv->mem_freq = 1333;
5901                 break;
5902         }
5903         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5904
5905         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5906         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5907         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5908                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5909                          dev_priv->rps.max_freq);
5910
5911         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5912         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5913                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5914                          dev_priv->rps.efficient_freq);
5915
5916         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5917         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5918                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5919                          dev_priv->rps.rp1_freq);
5920
5921         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5922         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5923                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5924                          dev_priv->rps.min_freq);
5925 }
5926
5927 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5928 {
5929         u32 val;
5930
5931         cherryview_setup_pctx(dev_priv);
5932
5933         vlv_init_gpll_ref_freq(dev_priv);
5934
5935         mutex_lock(&dev_priv->sb_lock);
5936         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5937         mutex_unlock(&dev_priv->sb_lock);
5938
5939         switch ((val >> 2) & 0x7) {
5940         case 3:
5941                 dev_priv->mem_freq = 2000;
5942                 break;
5943         default:
5944                 dev_priv->mem_freq = 1600;
5945                 break;
5946         }
5947         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5948
5949         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5950         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5951         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5952                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5953                          dev_priv->rps.max_freq);
5954
5955         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5956         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5957                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5958                          dev_priv->rps.efficient_freq);
5959
5960         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5961         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5962                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5963                          dev_priv->rps.rp1_freq);
5964
5965         /* PUnit validated range is only [RPe, RP0] */
5966         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5967         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5968                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5969                          dev_priv->rps.min_freq);
5970
5971         WARN_ONCE((dev_priv->rps.max_freq |
5972                    dev_priv->rps.efficient_freq |
5973                    dev_priv->rps.rp1_freq |
5974                    dev_priv->rps.min_freq) & 1,
5975                   "Odd GPU freq values\n");
5976 }
5977
5978 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5979 {
5980         valleyview_cleanup_pctx(dev_priv);
5981 }
5982
5983 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5984 {
5985         struct intel_engine_cs *engine;
5986         enum intel_engine_id id;
5987         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5988
5989         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5990
5991         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5992                                              GT_FIFO_FREE_ENTRIES_CHV);
5993         if (gtfifodbg) {
5994                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5995                                  gtfifodbg);
5996                 I915_WRITE(GTFIFODBG, gtfifodbg);
5997         }
5998
5999         cherryview_check_pctx(dev_priv);
6000
6001         /* 1a & 1b: Get forcewake during program sequence. Although the driver
6002          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6003         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6004
6005         /*  Disable RC states. */
6006         I915_WRITE(GEN6_RC_CONTROL, 0);
6007
6008         /* 2a: Program RC6 thresholds.*/
6009         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6010         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6011         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6012
6013         for_each_engine(engine, dev_priv, id)
6014                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6015         I915_WRITE(GEN6_RC_SLEEP, 0);
6016
6017         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6018         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6019
6020         /* allows RC6 residency counter to work */
6021         I915_WRITE(VLV_COUNTER_CONTROL,
6022                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6023                                       VLV_MEDIA_RC6_COUNT_EN |
6024                                       VLV_RENDER_RC6_COUNT_EN));
6025
6026         /* For now we assume BIOS is allocating and populating the PCBR  */
6027         pcbr = I915_READ(VLV_PCBR);
6028
6029         /* 3: Enable RC6 */
6030         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6031             (pcbr >> VLV_PCBR_ADDR_SHIFT))
6032                 rc6_mode = GEN7_RC_CTL_TO_MODE;
6033
6034         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6035
6036         /* 4 Program defaults and thresholds for RPS*/
6037         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6038         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6039         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6040         I915_WRITE(GEN6_RP_UP_EI, 66000);
6041         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6042
6043         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6044
6045         /* 5: Enable RPS */
6046         I915_WRITE(GEN6_RP_CONTROL,
6047                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6048                    GEN6_RP_MEDIA_IS_GFX |
6049                    GEN6_RP_ENABLE |
6050                    GEN6_RP_UP_BUSY_AVG |
6051                    GEN6_RP_DOWN_IDLE_AVG);
6052
6053         /* Setting Fixed Bias */
6054         val = VLV_OVERRIDE_EN |
6055                   VLV_SOC_TDP_EN |
6056                   CHV_BIAS_CPU_50_SOC_50;
6057         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6058
6059         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6060
6061         /* RPS code assumes GPLL is used */
6062         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6063
6064         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6065         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6066
6067         reset_rps(dev_priv, valleyview_set_rps);
6068
6069         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6070 }
6071
6072 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6073 {
6074         struct intel_engine_cs *engine;
6075         enum intel_engine_id id;
6076         u32 gtfifodbg, val, rc6_mode = 0;
6077
6078         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6079
6080         valleyview_check_pctx(dev_priv);
6081
6082         gtfifodbg = I915_READ(GTFIFODBG);
6083         if (gtfifodbg) {
6084                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6085                                  gtfifodbg);
6086                 I915_WRITE(GTFIFODBG, gtfifodbg);
6087         }
6088
6089         /* If VLV, Forcewake all wells, else re-direct to regular path */
6090         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6091
6092         /*  Disable RC states. */
6093         I915_WRITE(GEN6_RC_CONTROL, 0);
6094
6095         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6096         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6097         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6098         I915_WRITE(GEN6_RP_UP_EI, 66000);
6099         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6100
6101         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6102
6103         I915_WRITE(GEN6_RP_CONTROL,
6104                    GEN6_RP_MEDIA_TURBO |
6105                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6106                    GEN6_RP_MEDIA_IS_GFX |
6107                    GEN6_RP_ENABLE |
6108                    GEN6_RP_UP_BUSY_AVG |
6109                    GEN6_RP_DOWN_IDLE_CONT);
6110
6111         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6112         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6113         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6114
6115         for_each_engine(engine, dev_priv, id)
6116                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6117
6118         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6119
6120         /* allows RC6 residency counter to work */
6121         I915_WRITE(VLV_COUNTER_CONTROL,
6122                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6123                                       VLV_RENDER_RC0_COUNT_EN |
6124                                       VLV_MEDIA_RC6_COUNT_EN |
6125                                       VLV_RENDER_RC6_COUNT_EN));
6126
6127         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6128                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6129
6130         intel_print_rc6_info(dev_priv, rc6_mode);
6131
6132         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6133
6134         /* Setting Fixed Bias */
6135         val = VLV_OVERRIDE_EN |
6136                   VLV_SOC_TDP_EN |
6137                   VLV_BIAS_CPU_125_SOC_875;
6138         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6139
6140         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6141
6142         /* RPS code assumes GPLL is used */
6143         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6144
6145         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6146         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6147
6148         reset_rps(dev_priv, valleyview_set_rps);
6149
6150         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6151 }
6152
6153 static unsigned long intel_pxfreq(u32 vidfreq)
6154 {
6155         unsigned long freq;
6156         int div = (vidfreq & 0x3f0000) >> 16;
6157         int post = (vidfreq & 0x3000) >> 12;
6158         int pre = (vidfreq & 0x7);
6159
6160         if (!pre)
6161                 return 0;
6162
6163         freq = ((div * 133333) / ((1<<post) * pre));
6164
6165         return freq;
6166 }
6167
6168 static const struct cparams {
6169         u16 i;
6170         u16 t;
6171         u16 m;
6172         u16 c;
6173 } cparams[] = {
6174         { 1, 1333, 301, 28664 },
6175         { 1, 1066, 294, 24460 },
6176         { 1, 800, 294, 25192 },
6177         { 0, 1333, 276, 27605 },
6178         { 0, 1066, 276, 27605 },
6179         { 0, 800, 231, 23784 },
6180 };
6181
6182 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6183 {
6184         u64 total_count, diff, ret;
6185         u32 count1, count2, count3, m = 0, c = 0;
6186         unsigned long now = jiffies_to_msecs(jiffies), diff1;
6187         int i;
6188
6189         assert_spin_locked(&mchdev_lock);
6190
6191         diff1 = now - dev_priv->ips.last_time1;
6192
6193         /* Prevent division-by-zero if we are asking too fast.
6194          * Also, we don't get interesting results if we are polling
6195          * faster than once in 10ms, so just return the saved value
6196          * in such cases.
6197          */
6198         if (diff1 <= 10)
6199                 return dev_priv->ips.chipset_power;
6200
6201         count1 = I915_READ(DMIEC);
6202         count2 = I915_READ(DDREC);
6203         count3 = I915_READ(CSIEC);
6204
6205         total_count = count1 + count2 + count3;
6206
6207         /* FIXME: handle per-counter overflow */
6208         if (total_count < dev_priv->ips.last_count1) {
6209                 diff = ~0UL - dev_priv->ips.last_count1;
6210                 diff += total_count;
6211         } else {
6212                 diff = total_count - dev_priv->ips.last_count1;
6213         }
6214
6215         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6216                 if (cparams[i].i == dev_priv->ips.c_m &&
6217                     cparams[i].t == dev_priv->ips.r_t) {
6218                         m = cparams[i].m;
6219                         c = cparams[i].c;
6220                         break;
6221                 }
6222         }
6223
6224         diff = div_u64(diff, diff1);
6225         ret = ((m * diff) + c);
6226         ret = div_u64(ret, 10);
6227
6228         dev_priv->ips.last_count1 = total_count;
6229         dev_priv->ips.last_time1 = now;
6230
6231         dev_priv->ips.chipset_power = ret;
6232
6233         return ret;
6234 }
6235
6236 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6237 {
6238         unsigned long val;
6239
6240         if (INTEL_INFO(dev_priv)->gen != 5)
6241                 return 0;
6242
6243         spin_lock_irq(&mchdev_lock);
6244
6245         val = __i915_chipset_val(dev_priv);
6246
6247         spin_unlock_irq(&mchdev_lock);
6248
6249         return val;
6250 }
6251
6252 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6253 {
6254         unsigned long m, x, b;
6255         u32 tsfs;
6256
6257         tsfs = I915_READ(TSFS);
6258
6259         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6260         x = I915_READ8(TR1);
6261
6262         b = tsfs & TSFS_INTR_MASK;
6263
6264         return ((m * x) / 127) - b;
6265 }
6266
6267 static int _pxvid_to_vd(u8 pxvid)
6268 {
6269         if (pxvid == 0)
6270                 return 0;
6271
6272         if (pxvid >= 8 && pxvid < 31)
6273                 pxvid = 31;
6274
6275         return (pxvid + 2) * 125;
6276 }
6277
6278 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6279 {
6280         const int vd = _pxvid_to_vd(pxvid);
6281         const int vm = vd - 1125;
6282
6283         if (INTEL_INFO(dev_priv)->is_mobile)
6284                 return vm > 0 ? vm : 0;
6285
6286         return vd;
6287 }
6288
6289 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6290 {
6291         u64 now, diff, diffms;
6292         u32 count;
6293
6294         assert_spin_locked(&mchdev_lock);
6295
6296         now = ktime_get_raw_ns();
6297         diffms = now - dev_priv->ips.last_time2;
6298         do_div(diffms, NSEC_PER_MSEC);
6299
6300         /* Don't divide by 0 */
6301         if (!diffms)
6302                 return;
6303
6304         count = I915_READ(GFXEC);
6305
6306         if (count < dev_priv->ips.last_count2) {
6307                 diff = ~0UL - dev_priv->ips.last_count2;
6308                 diff += count;
6309         } else {
6310                 diff = count - dev_priv->ips.last_count2;
6311         }
6312
6313         dev_priv->ips.last_count2 = count;
6314         dev_priv->ips.last_time2 = now;
6315
6316         /* More magic constants... */
6317         diff = diff * 1181;
6318         diff = div_u64(diff, diffms * 10);
6319         dev_priv->ips.gfx_power = diff;
6320 }
6321
6322 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6323 {
6324         if (INTEL_INFO(dev_priv)->gen != 5)
6325                 return;
6326
6327         spin_lock_irq(&mchdev_lock);
6328
6329         __i915_update_gfx_val(dev_priv);
6330
6331         spin_unlock_irq(&mchdev_lock);
6332 }
6333
6334 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6335 {
6336         unsigned long t, corr, state1, corr2, state2;
6337         u32 pxvid, ext_v;
6338
6339         assert_spin_locked(&mchdev_lock);
6340
6341         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6342         pxvid = (pxvid >> 24) & 0x7f;
6343         ext_v = pvid_to_extvid(dev_priv, pxvid);
6344
6345         state1 = ext_v;
6346
6347         t = i915_mch_val(dev_priv);
6348
6349         /* Revel in the empirically derived constants */
6350
6351         /* Correction factor in 1/100000 units */
6352         if (t > 80)
6353                 corr = ((t * 2349) + 135940);
6354         else if (t >= 50)
6355                 corr = ((t * 964) + 29317);
6356         else /* < 50 */
6357                 corr = ((t * 301) + 1004);
6358
6359         corr = corr * ((150142 * state1) / 10000 - 78642);
6360         corr /= 100000;
6361         corr2 = (corr * dev_priv->ips.corr);
6362
6363         state2 = (corr2 * state1) / 10000;
6364         state2 /= 100; /* convert to mW */
6365
6366         __i915_update_gfx_val(dev_priv);
6367
6368         return dev_priv->ips.gfx_power + state2;
6369 }
6370
6371 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6372 {
6373         unsigned long val;
6374
6375         if (INTEL_INFO(dev_priv)->gen != 5)
6376                 return 0;
6377
6378         spin_lock_irq(&mchdev_lock);
6379
6380         val = __i915_gfx_val(dev_priv);
6381
6382         spin_unlock_irq(&mchdev_lock);
6383
6384         return val;
6385 }
6386
6387 /**
6388  * i915_read_mch_val - return value for IPS use
6389  *
6390  * Calculate and return a value for the IPS driver to use when deciding whether
6391  * we have thermal and power headroom to increase CPU or GPU power budget.
6392  */
6393 unsigned long i915_read_mch_val(void)
6394 {
6395         struct drm_i915_private *dev_priv;
6396         unsigned long chipset_val, graphics_val, ret = 0;
6397
6398         spin_lock_irq(&mchdev_lock);
6399         if (!i915_mch_dev)
6400                 goto out_unlock;
6401         dev_priv = i915_mch_dev;
6402
6403         chipset_val = __i915_chipset_val(dev_priv);
6404         graphics_val = __i915_gfx_val(dev_priv);
6405
6406         ret = chipset_val + graphics_val;
6407
6408 out_unlock:
6409         spin_unlock_irq(&mchdev_lock);
6410
6411         return ret;
6412 }
6413 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6414
6415 /**
6416  * i915_gpu_raise - raise GPU frequency limit
6417  *
6418  * Raise the limit; IPS indicates we have thermal headroom.
6419  */
6420 bool i915_gpu_raise(void)
6421 {
6422         struct drm_i915_private *dev_priv;
6423         bool ret = true;
6424
6425         spin_lock_irq(&mchdev_lock);
6426         if (!i915_mch_dev) {
6427                 ret = false;
6428                 goto out_unlock;
6429         }
6430         dev_priv = i915_mch_dev;
6431
6432         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6433                 dev_priv->ips.max_delay--;
6434
6435 out_unlock:
6436         spin_unlock_irq(&mchdev_lock);
6437
6438         return ret;
6439 }
6440 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6441
6442 /**
6443  * i915_gpu_lower - lower GPU frequency limit
6444  *
6445  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6446  * frequency maximum.
6447  */
6448 bool i915_gpu_lower(void)
6449 {
6450         struct drm_i915_private *dev_priv;
6451         bool ret = true;
6452
6453         spin_lock_irq(&mchdev_lock);
6454         if (!i915_mch_dev) {
6455                 ret = false;
6456                 goto out_unlock;
6457         }
6458         dev_priv = i915_mch_dev;
6459
6460         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6461                 dev_priv->ips.max_delay++;
6462
6463 out_unlock:
6464         spin_unlock_irq(&mchdev_lock);
6465
6466         return ret;
6467 }
6468 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6469
6470 /**
6471  * i915_gpu_busy - indicate GPU business to IPS
6472  *
6473  * Tell the IPS driver whether or not the GPU is busy.
6474  */
6475 bool i915_gpu_busy(void)
6476 {
6477         bool ret = false;
6478
6479         spin_lock_irq(&mchdev_lock);
6480         if (i915_mch_dev)
6481                 ret = i915_mch_dev->gt.awake;
6482         spin_unlock_irq(&mchdev_lock);
6483
6484         return ret;
6485 }
6486 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6487
6488 /**
6489  * i915_gpu_turbo_disable - disable graphics turbo
6490  *
6491  * Disable graphics turbo by resetting the max frequency and setting the
6492  * current frequency to the default.
6493  */
6494 bool i915_gpu_turbo_disable(void)
6495 {
6496         struct drm_i915_private *dev_priv;
6497         bool ret = true;
6498
6499         spin_lock_irq(&mchdev_lock);
6500         if (!i915_mch_dev) {
6501                 ret = false;
6502                 goto out_unlock;
6503         }
6504         dev_priv = i915_mch_dev;
6505
6506         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6507
6508         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6509                 ret = false;
6510
6511 out_unlock:
6512         spin_unlock_irq(&mchdev_lock);
6513
6514         return ret;
6515 }
6516 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6517
6518 /**
6519  * Tells the intel_ips driver that the i915 driver is now loaded, if
6520  * IPS got loaded first.
6521  *
6522  * This awkward dance is so that neither module has to depend on the
6523  * other in order for IPS to do the appropriate communication of
6524  * GPU turbo limits to i915.
6525  */
6526 static void
6527 ips_ping_for_i915_load(void)
6528 {
6529         void (*link)(void);
6530
6531         link = symbol_get(ips_link_to_i915_driver);
6532         if (link) {
6533                 link();
6534                 symbol_put(ips_link_to_i915_driver);
6535         }
6536 }
6537
6538 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6539 {
6540         /* We only register the i915 ips part with intel-ips once everything is
6541          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6542         spin_lock_irq(&mchdev_lock);
6543         i915_mch_dev = dev_priv;
6544         spin_unlock_irq(&mchdev_lock);
6545
6546         ips_ping_for_i915_load();
6547 }
6548
6549 void intel_gpu_ips_teardown(void)
6550 {
6551         spin_lock_irq(&mchdev_lock);
6552         i915_mch_dev = NULL;
6553         spin_unlock_irq(&mchdev_lock);
6554 }
6555
6556 static void intel_init_emon(struct drm_i915_private *dev_priv)
6557 {
6558         u32 lcfuse;
6559         u8 pxw[16];
6560         int i;
6561
6562         /* Disable to program */
6563         I915_WRITE(ECR, 0);
6564         POSTING_READ(ECR);
6565
6566         /* Program energy weights for various events */
6567         I915_WRITE(SDEW, 0x15040d00);
6568         I915_WRITE(CSIEW0, 0x007f0000);
6569         I915_WRITE(CSIEW1, 0x1e220004);
6570         I915_WRITE(CSIEW2, 0x04000004);
6571
6572         for (i = 0; i < 5; i++)
6573                 I915_WRITE(PEW(i), 0);
6574         for (i = 0; i < 3; i++)
6575                 I915_WRITE(DEW(i), 0);
6576
6577         /* Program P-state weights to account for frequency power adjustment */
6578         for (i = 0; i < 16; i++) {
6579                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6580                 unsigned long freq = intel_pxfreq(pxvidfreq);
6581                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6582                         PXVFREQ_PX_SHIFT;
6583                 unsigned long val;
6584
6585                 val = vid * vid;
6586                 val *= (freq / 1000);
6587                 val *= 255;
6588                 val /= (127*127*900);
6589                 if (val > 0xff)
6590                         DRM_ERROR("bad pxval: %ld\n", val);
6591                 pxw[i] = val;
6592         }
6593         /* Render standby states get 0 weight */
6594         pxw[14] = 0;
6595         pxw[15] = 0;
6596
6597         for (i = 0; i < 4; i++) {
6598                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6599                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6600                 I915_WRITE(PXW(i), val);
6601         }
6602
6603         /* Adjust magic regs to magic values (more experimental results) */
6604         I915_WRITE(OGW0, 0);
6605         I915_WRITE(OGW1, 0);
6606         I915_WRITE(EG0, 0x00007f00);
6607         I915_WRITE(EG1, 0x0000000e);
6608         I915_WRITE(EG2, 0x000e0000);
6609         I915_WRITE(EG3, 0x68000300);
6610         I915_WRITE(EG4, 0x42000000);
6611         I915_WRITE(EG5, 0x00140031);
6612         I915_WRITE(EG6, 0);
6613         I915_WRITE(EG7, 0);
6614
6615         for (i = 0; i < 8; i++)
6616                 I915_WRITE(PXWL(i), 0);
6617
6618         /* Enable PMON + select events */
6619         I915_WRITE(ECR, 0x80000019);
6620
6621         lcfuse = I915_READ(LCFUSE02);
6622
6623         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6624 }
6625
6626 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6627 {
6628         /*
6629          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6630          * requirement.
6631          */
6632         if (!i915.enable_rc6) {
6633                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6634                 intel_runtime_pm_get(dev_priv);
6635         }
6636
6637         mutex_lock(&dev_priv->drm.struct_mutex);
6638         mutex_lock(&dev_priv->rps.hw_lock);
6639
6640         /* Initialize RPS limits (for userspace) */
6641         if (IS_CHERRYVIEW(dev_priv))
6642                 cherryview_init_gt_powersave(dev_priv);
6643         else if (IS_VALLEYVIEW(dev_priv))
6644                 valleyview_init_gt_powersave(dev_priv);
6645         else if (INTEL_GEN(dev_priv) >= 6)
6646                 gen6_init_rps_frequencies(dev_priv);
6647
6648         /* Derive initial user preferences/limits from the hardware limits */
6649         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6650         dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6651
6652         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6653         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6654
6655         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6656                 dev_priv->rps.min_freq_softlimit =
6657                         max_t(int,
6658                               dev_priv->rps.efficient_freq,
6659                               intel_freq_opcode(dev_priv, 450));
6660
6661         /* After setting max-softlimit, find the overclock max freq */
6662         if (IS_GEN6(dev_priv) ||
6663             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6664                 u32 params = 0;
6665
6666                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6667                 if (params & BIT(31)) { /* OC supported */
6668                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6669                                          (dev_priv->rps.max_freq & 0xff) * 50,
6670                                          (params & 0xff) * 50);
6671                         dev_priv->rps.max_freq = params & 0xff;
6672                 }
6673         }
6674
6675         /* Finally allow us to boost to max by default */
6676         dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6677
6678         mutex_unlock(&dev_priv->rps.hw_lock);
6679         mutex_unlock(&dev_priv->drm.struct_mutex);
6680
6681         intel_autoenable_gt_powersave(dev_priv);
6682 }
6683
6684 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6685 {
6686         if (IS_VALLEYVIEW(dev_priv))
6687                 valleyview_cleanup_gt_powersave(dev_priv);
6688
6689         if (!i915.enable_rc6)
6690                 intel_runtime_pm_put(dev_priv);
6691 }
6692
6693 /**
6694  * intel_suspend_gt_powersave - suspend PM work and helper threads
6695  * @dev_priv: i915 device
6696  *
6697  * We don't want to disable RC6 or other features here, we just want
6698  * to make sure any work we've queued has finished and won't bother
6699  * us while we're suspended.
6700  */
6701 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6702 {
6703         if (INTEL_GEN(dev_priv) < 6)
6704                 return;
6705
6706         if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6707                 intel_runtime_pm_put(dev_priv);
6708
6709         /* gen6_rps_idle() will be called later to disable interrupts */
6710 }
6711
6712 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6713 {
6714         dev_priv->rps.enabled = true; /* force disabling */
6715         intel_disable_gt_powersave(dev_priv);
6716
6717         gen6_reset_rps_interrupts(dev_priv);
6718 }
6719
6720 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6721 {
6722         if (!READ_ONCE(dev_priv->rps.enabled))
6723                 return;
6724
6725         mutex_lock(&dev_priv->rps.hw_lock);
6726
6727         if (INTEL_GEN(dev_priv) >= 9) {
6728                 gen9_disable_rc6(dev_priv);
6729                 gen9_disable_rps(dev_priv);
6730         } else if (IS_CHERRYVIEW(dev_priv)) {
6731                 cherryview_disable_rps(dev_priv);
6732         } else if (IS_VALLEYVIEW(dev_priv)) {
6733                 valleyview_disable_rps(dev_priv);
6734         } else if (INTEL_GEN(dev_priv) >= 6) {
6735                 gen6_disable_rps(dev_priv);
6736         }  else if (IS_IRONLAKE_M(dev_priv)) {
6737                 ironlake_disable_drps(dev_priv);
6738         }
6739
6740         dev_priv->rps.enabled = false;
6741         mutex_unlock(&dev_priv->rps.hw_lock);
6742 }
6743
6744 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6745 {
6746         /* We shouldn't be disabling as we submit, so this should be less
6747          * racy than it appears!
6748          */
6749         if (READ_ONCE(dev_priv->rps.enabled))
6750                 return;
6751
6752         /* Powersaving is controlled by the host when inside a VM */
6753         if (intel_vgpu_active(dev_priv))
6754                 return;
6755
6756         mutex_lock(&dev_priv->rps.hw_lock);
6757
6758         if (IS_CHERRYVIEW(dev_priv)) {
6759                 cherryview_enable_rps(dev_priv);
6760         } else if (IS_VALLEYVIEW(dev_priv)) {
6761                 valleyview_enable_rps(dev_priv);
6762         } else if (INTEL_GEN(dev_priv) >= 9) {
6763                 gen9_enable_rc6(dev_priv);
6764                 gen9_enable_rps(dev_priv);
6765                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6766                         gen6_update_ring_freq(dev_priv);
6767         } else if (IS_BROADWELL(dev_priv)) {
6768                 gen8_enable_rps(dev_priv);
6769                 gen6_update_ring_freq(dev_priv);
6770         } else if (INTEL_GEN(dev_priv) >= 6) {
6771                 gen6_enable_rps(dev_priv);
6772                 gen6_update_ring_freq(dev_priv);
6773         } else if (IS_IRONLAKE_M(dev_priv)) {
6774                 ironlake_enable_drps(dev_priv);
6775                 intel_init_emon(dev_priv);
6776         }
6777
6778         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6779         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6780
6781         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6782         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6783
6784         dev_priv->rps.enabled = true;
6785         mutex_unlock(&dev_priv->rps.hw_lock);
6786 }
6787
6788 static void __intel_autoenable_gt_powersave(struct work_struct *work)
6789 {
6790         struct drm_i915_private *dev_priv =
6791                 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6792         struct intel_engine_cs *rcs;
6793         struct drm_i915_gem_request *req;
6794
6795         if (READ_ONCE(dev_priv->rps.enabled))
6796                 goto out;
6797
6798         rcs = dev_priv->engine[RCS];
6799         if (rcs->last_context)
6800                 goto out;
6801
6802         if (!rcs->init_context)
6803                 goto out;
6804
6805         mutex_lock(&dev_priv->drm.struct_mutex);
6806
6807         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6808         if (IS_ERR(req))
6809                 goto unlock;
6810
6811         if (!i915.enable_execlists && i915_switch_context(req) == 0)
6812                 rcs->init_context(req);
6813
6814         /* Mark the device busy, calling intel_enable_gt_powersave() */
6815         i915_add_request_no_flush(req);
6816
6817 unlock:
6818         mutex_unlock(&dev_priv->drm.struct_mutex);
6819 out:
6820         intel_runtime_pm_put(dev_priv);
6821 }
6822
6823 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6824 {
6825         if (READ_ONCE(dev_priv->rps.enabled))
6826                 return;
6827
6828         if (IS_IRONLAKE_M(dev_priv)) {
6829                 ironlake_enable_drps(dev_priv);
6830                 intel_init_emon(dev_priv);
6831         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6832                 /*
6833                  * PCU communication is slow and this doesn't need to be
6834                  * done at any specific time, so do this out of our fast path
6835                  * to make resume and init faster.
6836                  *
6837                  * We depend on the HW RC6 power context save/restore
6838                  * mechanism when entering D3 through runtime PM suspend. So
6839                  * disable RPM until RPS/RC6 is properly setup. We can only
6840                  * get here via the driver load/system resume/runtime resume
6841                  * paths, so the _noresume version is enough (and in case of
6842                  * runtime resume it's necessary).
6843                  */
6844                 if (queue_delayed_work(dev_priv->wq,
6845                                        &dev_priv->rps.autoenable_work,
6846                                        round_jiffies_up_relative(HZ)))
6847                         intel_runtime_pm_get_noresume(dev_priv);
6848         }
6849 }
6850
6851 static void ibx_init_clock_gating(struct drm_device *dev)
6852 {
6853         struct drm_i915_private *dev_priv = to_i915(dev);
6854
6855         /*
6856          * On Ibex Peak and Cougar Point, we need to disable clock
6857          * gating for the panel power sequencer or it will fail to
6858          * start up when no ports are active.
6859          */
6860         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6861 }
6862
6863 static void g4x_disable_trickle_feed(struct drm_device *dev)
6864 {
6865         struct drm_i915_private *dev_priv = to_i915(dev);
6866         enum pipe pipe;
6867
6868         for_each_pipe(dev_priv, pipe) {
6869                 I915_WRITE(DSPCNTR(pipe),
6870                            I915_READ(DSPCNTR(pipe)) |
6871                            DISPPLANE_TRICKLE_FEED_DISABLE);
6872
6873                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6874                 POSTING_READ(DSPSURF(pipe));
6875         }
6876 }
6877
6878 static void ilk_init_lp_watermarks(struct drm_device *dev)
6879 {
6880         struct drm_i915_private *dev_priv = to_i915(dev);
6881
6882         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6883         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6884         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6885
6886         /*
6887          * Don't touch WM1S_LP_EN here.
6888          * Doing so could cause underruns.
6889          */
6890 }
6891
6892 static void ironlake_init_clock_gating(struct drm_device *dev)
6893 {
6894         struct drm_i915_private *dev_priv = to_i915(dev);
6895         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6896
6897         /*
6898          * Required for FBC
6899          * WaFbcDisableDpfcClockGating:ilk
6900          */
6901         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6902                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6903                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6904
6905         I915_WRITE(PCH_3DCGDIS0,
6906                    MARIUNIT_CLOCK_GATE_DISABLE |
6907                    SVSMUNIT_CLOCK_GATE_DISABLE);
6908         I915_WRITE(PCH_3DCGDIS1,
6909                    VFMUNIT_CLOCK_GATE_DISABLE);
6910
6911         /*
6912          * According to the spec the following bits should be set in
6913          * order to enable memory self-refresh
6914          * The bit 22/21 of 0x42004
6915          * The bit 5 of 0x42020
6916          * The bit 15 of 0x45000
6917          */
6918         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6919                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6920                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6921         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6922         I915_WRITE(DISP_ARB_CTL,
6923                    (I915_READ(DISP_ARB_CTL) |
6924                     DISP_FBC_WM_DIS));
6925
6926         ilk_init_lp_watermarks(dev);
6927
6928         /*
6929          * Based on the document from hardware guys the following bits
6930          * should be set unconditionally in order to enable FBC.
6931          * The bit 22 of 0x42000
6932          * The bit 22 of 0x42004
6933          * The bit 7,8,9 of 0x42020.
6934          */
6935         if (IS_IRONLAKE_M(dev_priv)) {
6936                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6937                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6938                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6939                            ILK_FBCQ_DIS);
6940                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6941                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6942                            ILK_DPARB_GATE);
6943         }
6944
6945         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6946
6947         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6948                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6949                    ILK_ELPIN_409_SELECT);
6950         I915_WRITE(_3D_CHICKEN2,
6951                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6952                    _3D_CHICKEN2_WM_READ_PIPELINED);
6953
6954         /* WaDisableRenderCachePipelinedFlush:ilk */
6955         I915_WRITE(CACHE_MODE_0,
6956                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6957
6958         /* WaDisable_RenderCache_OperationalFlush:ilk */
6959         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6960
6961         g4x_disable_trickle_feed(dev);
6962
6963         ibx_init_clock_gating(dev);
6964 }
6965
6966 static void cpt_init_clock_gating(struct drm_device *dev)
6967 {
6968         struct drm_i915_private *dev_priv = to_i915(dev);
6969         int pipe;
6970         uint32_t val;
6971
6972         /*
6973          * On Ibex Peak and Cougar Point, we need to disable clock
6974          * gating for the panel power sequencer or it will fail to
6975          * start up when no ports are active.
6976          */
6977         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6978                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6979                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6980         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6981                    DPLS_EDP_PPS_FIX_DIS);
6982         /* The below fixes the weird display corruption, a few pixels shifted
6983          * downward, on (only) LVDS of some HP laptops with IVY.
6984          */
6985         for_each_pipe(dev_priv, pipe) {
6986                 val = I915_READ(TRANS_CHICKEN2(pipe));
6987                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6988                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6989                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6990                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6991                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6992                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6993                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6994                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6995         }
6996         /* WADP0ClockGatingDisable */
6997         for_each_pipe(dev_priv, pipe) {
6998                 I915_WRITE(TRANS_CHICKEN1(pipe),
6999                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7000         }
7001 }
7002
7003 static void gen6_check_mch_setup(struct drm_device *dev)
7004 {
7005         struct drm_i915_private *dev_priv = to_i915(dev);
7006         uint32_t tmp;
7007
7008         tmp = I915_READ(MCH_SSKPD);
7009         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7010                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7011                               tmp);
7012 }
7013
7014 static void gen6_init_clock_gating(struct drm_device *dev)
7015 {
7016         struct drm_i915_private *dev_priv = to_i915(dev);
7017         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7018
7019         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7020
7021         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7022                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7023                    ILK_ELPIN_409_SELECT);
7024
7025         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7026         I915_WRITE(_3D_CHICKEN,
7027                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7028
7029         /* WaDisable_RenderCache_OperationalFlush:snb */
7030         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7031
7032         /*
7033          * BSpec recoomends 8x4 when MSAA is used,
7034          * however in practice 16x4 seems fastest.
7035          *
7036          * Note that PS/WM thread counts depend on the WIZ hashing
7037          * disable bit, which we don't touch here, but it's good
7038          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7039          */
7040         I915_WRITE(GEN6_GT_MODE,
7041                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7042
7043         ilk_init_lp_watermarks(dev);
7044
7045         I915_WRITE(CACHE_MODE_0,
7046                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7047
7048         I915_WRITE(GEN6_UCGCTL1,
7049                    I915_READ(GEN6_UCGCTL1) |
7050                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7051                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7052
7053         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7054          * gating disable must be set.  Failure to set it results in
7055          * flickering pixels due to Z write ordering failures after
7056          * some amount of runtime in the Mesa "fire" demo, and Unigine
7057          * Sanctuary and Tropics, and apparently anything else with
7058          * alpha test or pixel discard.
7059          *
7060          * According to the spec, bit 11 (RCCUNIT) must also be set,
7061          * but we didn't debug actual testcases to find it out.
7062          *
7063          * WaDisableRCCUnitClockGating:snb
7064          * WaDisableRCPBUnitClockGating:snb
7065          */
7066         I915_WRITE(GEN6_UCGCTL2,
7067                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7068                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7069
7070         /* WaStripsFansDisableFastClipPerformanceFix:snb */
7071         I915_WRITE(_3D_CHICKEN3,
7072                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7073
7074         /*
7075          * Bspec says:
7076          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7077          * 3DSTATE_SF number of SF output attributes is more than 16."
7078          */
7079         I915_WRITE(_3D_CHICKEN3,
7080                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7081
7082         /*
7083          * According to the spec the following bits should be
7084          * set in order to enable memory self-refresh and fbc:
7085          * The bit21 and bit22 of 0x42000
7086          * The bit21 and bit22 of 0x42004
7087          * The bit5 and bit7 of 0x42020
7088          * The bit14 of 0x70180
7089          * The bit14 of 0x71180
7090          *
7091          * WaFbcAsynchFlipDisableFbcQueue:snb
7092          */
7093         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7094                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7095                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7096         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7097                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7098                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7099         I915_WRITE(ILK_DSPCLK_GATE_D,
7100                    I915_READ(ILK_DSPCLK_GATE_D) |
7101                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7102                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7103
7104         g4x_disable_trickle_feed(dev);
7105
7106         cpt_init_clock_gating(dev);
7107
7108         gen6_check_mch_setup(dev);
7109 }
7110
7111 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7112 {
7113         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7114
7115         /*
7116          * WaVSThreadDispatchOverride:ivb,vlv
7117          *
7118          * This actually overrides the dispatch
7119          * mode for all thread types.
7120          */
7121         reg &= ~GEN7_FF_SCHED_MASK;
7122         reg |= GEN7_FF_TS_SCHED_HW;
7123         reg |= GEN7_FF_VS_SCHED_HW;
7124         reg |= GEN7_FF_DS_SCHED_HW;
7125
7126         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7127 }
7128
7129 static void lpt_init_clock_gating(struct drm_device *dev)
7130 {
7131         struct drm_i915_private *dev_priv = to_i915(dev);
7132
7133         /*
7134          * TODO: this bit should only be enabled when really needed, then
7135          * disabled when not needed anymore in order to save power.
7136          */
7137         if (HAS_PCH_LPT_LP(dev_priv))
7138                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7139                            I915_READ(SOUTH_DSPCLK_GATE_D) |
7140                            PCH_LP_PARTITION_LEVEL_DISABLE);
7141
7142         /* WADPOClockGatingDisable:hsw */
7143         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7144                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7145                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7146 }
7147
7148 static void lpt_suspend_hw(struct drm_device *dev)
7149 {
7150         struct drm_i915_private *dev_priv = to_i915(dev);
7151
7152         if (HAS_PCH_LPT_LP(dev_priv)) {
7153                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7154
7155                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7156                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7157         }
7158 }
7159
7160 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7161                                    int general_prio_credits,
7162                                    int high_prio_credits)
7163 {
7164         u32 misccpctl;
7165
7166         /* WaTempDisableDOPClkGating:bdw */
7167         misccpctl = I915_READ(GEN7_MISCCPCTL);
7168         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7169
7170         I915_WRITE(GEN8_L3SQCREG1,
7171                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7172                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
7173
7174         /*
7175          * Wait at least 100 clocks before re-enabling clock gating.
7176          * See the definition of L3SQCREG1 in BSpec.
7177          */
7178         POSTING_READ(GEN8_L3SQCREG1);
7179         udelay(1);
7180         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7181 }
7182
7183 static void kabylake_init_clock_gating(struct drm_device *dev)
7184 {
7185         struct drm_i915_private *dev_priv = dev->dev_private;
7186
7187         gen9_init_clock_gating(dev);
7188
7189         /* WaDisableSDEUnitClockGating:kbl */
7190         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7191                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7192                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7193
7194         /* WaDisableGamClockGating:kbl */
7195         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7196                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7197                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7198
7199         /* WaFbcNukeOnHostModify:kbl */
7200         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7201                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7202 }
7203
7204 static void skylake_init_clock_gating(struct drm_device *dev)
7205 {
7206         struct drm_i915_private *dev_priv = dev->dev_private;
7207
7208         gen9_init_clock_gating(dev);
7209
7210         /* WAC6entrylatency:skl */
7211         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7212                    FBC_LLC_FULLY_OPEN);
7213
7214         /* WaFbcNukeOnHostModify:skl */
7215         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7216                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7217 }
7218
7219 static void broadwell_init_clock_gating(struct drm_device *dev)
7220 {
7221         struct drm_i915_private *dev_priv = to_i915(dev);
7222         enum pipe pipe;
7223
7224         ilk_init_lp_watermarks(dev);
7225
7226         /* WaSwitchSolVfFArbitrationPriority:bdw */
7227         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7228
7229         /* WaPsrDPAMaskVBlankInSRD:bdw */
7230         I915_WRITE(CHICKEN_PAR1_1,
7231                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7232
7233         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7234         for_each_pipe(dev_priv, pipe) {
7235                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7236                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
7237                            BDW_DPRS_MASK_VBLANK_SRD);
7238         }
7239
7240         /* WaVSRefCountFullforceMissDisable:bdw */
7241         /* WaDSRefCountFullforceMissDisable:bdw */
7242         I915_WRITE(GEN7_FF_THREAD_MODE,
7243                    I915_READ(GEN7_FF_THREAD_MODE) &
7244                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7245
7246         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7247                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7248
7249         /* WaDisableSDEUnitClockGating:bdw */
7250         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7251                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7252
7253         /* WaProgramL3SqcReg1Default:bdw */
7254         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7255
7256         /*
7257          * WaGttCachingOffByDefault:bdw
7258          * GTT cache may not work with big pages, so if those
7259          * are ever enabled GTT cache may need to be disabled.
7260          */
7261         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7262
7263         /* WaKVMNotificationOnConfigChange:bdw */
7264         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7265                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7266
7267         lpt_init_clock_gating(dev);
7268 }
7269
7270 static void haswell_init_clock_gating(struct drm_device *dev)
7271 {
7272         struct drm_i915_private *dev_priv = to_i915(dev);
7273
7274         ilk_init_lp_watermarks(dev);
7275
7276         /* L3 caching of data atomics doesn't work -- disable it. */
7277         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7278         I915_WRITE(HSW_ROW_CHICKEN3,
7279                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7280
7281         /* This is required by WaCatErrorRejectionIssue:hsw */
7282         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7283                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7284                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7285
7286         /* WaVSRefCountFullforceMissDisable:hsw */
7287         I915_WRITE(GEN7_FF_THREAD_MODE,
7288                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7289
7290         /* WaDisable_RenderCache_OperationalFlush:hsw */
7291         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7292
7293         /* enable HiZ Raw Stall Optimization */
7294         I915_WRITE(CACHE_MODE_0_GEN7,
7295                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7296
7297         /* WaDisable4x2SubspanOptimization:hsw */
7298         I915_WRITE(CACHE_MODE_1,
7299                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7300
7301         /*
7302          * BSpec recommends 8x4 when MSAA is used,
7303          * however in practice 16x4 seems fastest.
7304          *
7305          * Note that PS/WM thread counts depend on the WIZ hashing
7306          * disable bit, which we don't touch here, but it's good
7307          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7308          */
7309         I915_WRITE(GEN7_GT_MODE,
7310                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7311
7312         /* WaSampleCChickenBitEnable:hsw */
7313         I915_WRITE(HALF_SLICE_CHICKEN3,
7314                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7315
7316         /* WaSwitchSolVfFArbitrationPriority:hsw */
7317         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7318
7319         /* WaRsPkgCStateDisplayPMReq:hsw */
7320         I915_WRITE(CHICKEN_PAR1_1,
7321                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7322
7323         lpt_init_clock_gating(dev);
7324 }
7325
7326 static void ivybridge_init_clock_gating(struct drm_device *dev)
7327 {
7328         struct drm_i915_private *dev_priv = to_i915(dev);
7329         uint32_t snpcr;
7330
7331         ilk_init_lp_watermarks(dev);
7332
7333         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7334
7335         /* WaDisableEarlyCull:ivb */
7336         I915_WRITE(_3D_CHICKEN3,
7337                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7338
7339         /* WaDisableBackToBackFlipFix:ivb */
7340         I915_WRITE(IVB_CHICKEN3,
7341                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7342                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7343
7344         /* WaDisablePSDDualDispatchEnable:ivb */
7345         if (IS_IVB_GT1(dev_priv))
7346                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7347                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7348
7349         /* WaDisable_RenderCache_OperationalFlush:ivb */
7350         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7351
7352         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7353         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7354                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7355
7356         /* WaApplyL3ControlAndL3ChickenMode:ivb */
7357         I915_WRITE(GEN7_L3CNTLREG1,
7358                         GEN7_WA_FOR_GEN7_L3_CONTROL);
7359         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7360                    GEN7_WA_L3_CHICKEN_MODE);
7361         if (IS_IVB_GT1(dev_priv))
7362                 I915_WRITE(GEN7_ROW_CHICKEN2,
7363                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7364         else {
7365                 /* must write both registers */
7366                 I915_WRITE(GEN7_ROW_CHICKEN2,
7367                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7368                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7369                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7370         }
7371
7372         /* WaForceL3Serialization:ivb */
7373         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7374                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7375
7376         /*
7377          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7378          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7379          */
7380         I915_WRITE(GEN6_UCGCTL2,
7381                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7382
7383         /* This is required by WaCatErrorRejectionIssue:ivb */
7384         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7385                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7386                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7387
7388         g4x_disable_trickle_feed(dev);
7389
7390         gen7_setup_fixed_func_scheduler(dev_priv);
7391
7392         if (0) { /* causes HiZ corruption on ivb:gt1 */
7393                 /* enable HiZ Raw Stall Optimization */
7394                 I915_WRITE(CACHE_MODE_0_GEN7,
7395                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7396         }
7397
7398         /* WaDisable4x2SubspanOptimization:ivb */
7399         I915_WRITE(CACHE_MODE_1,
7400                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7401
7402         /*
7403          * BSpec recommends 8x4 when MSAA is used,
7404          * however in practice 16x4 seems fastest.
7405          *
7406          * Note that PS/WM thread counts depend on the WIZ hashing
7407          * disable bit, which we don't touch here, but it's good
7408          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7409          */
7410         I915_WRITE(GEN7_GT_MODE,
7411                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7412
7413         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7414         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7415         snpcr |= GEN6_MBC_SNPCR_MED;
7416         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7417
7418         if (!HAS_PCH_NOP(dev_priv))
7419                 cpt_init_clock_gating(dev);
7420
7421         gen6_check_mch_setup(dev);
7422 }
7423
7424 static void valleyview_init_clock_gating(struct drm_device *dev)
7425 {
7426         struct drm_i915_private *dev_priv = to_i915(dev);
7427
7428         /* WaDisableEarlyCull:vlv */
7429         I915_WRITE(_3D_CHICKEN3,
7430                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7431
7432         /* WaDisableBackToBackFlipFix:vlv */
7433         I915_WRITE(IVB_CHICKEN3,
7434                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7435                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7436
7437         /* WaPsdDispatchEnable:vlv */
7438         /* WaDisablePSDDualDispatchEnable:vlv */
7439         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7440                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7441                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7442
7443         /* WaDisable_RenderCache_OperationalFlush:vlv */
7444         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7445
7446         /* WaForceL3Serialization:vlv */
7447         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7448                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7449
7450         /* WaDisableDopClockGating:vlv */
7451         I915_WRITE(GEN7_ROW_CHICKEN2,
7452                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7453
7454         /* This is required by WaCatErrorRejectionIssue:vlv */
7455         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7456                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7457                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7458
7459         gen7_setup_fixed_func_scheduler(dev_priv);
7460
7461         /*
7462          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7463          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7464          */
7465         I915_WRITE(GEN6_UCGCTL2,
7466                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7467
7468         /* WaDisableL3Bank2xClockGate:vlv
7469          * Disabling L3 clock gating- MMIO 940c[25] = 1
7470          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7471         I915_WRITE(GEN7_UCGCTL4,
7472                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7473
7474         /*
7475          * BSpec says this must be set, even though
7476          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7477          */
7478         I915_WRITE(CACHE_MODE_1,
7479                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7480
7481         /*
7482          * BSpec recommends 8x4 when MSAA is used,
7483          * however in practice 16x4 seems fastest.
7484          *
7485          * Note that PS/WM thread counts depend on the WIZ hashing
7486          * disable bit, which we don't touch here, but it's good
7487          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7488          */
7489         I915_WRITE(GEN7_GT_MODE,
7490                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7491
7492         /*
7493          * WaIncreaseL3CreditsForVLVB0:vlv
7494          * This is the hardware default actually.
7495          */
7496         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7497
7498         /*
7499          * WaDisableVLVClockGating_VBIIssue:vlv
7500          * Disable clock gating on th GCFG unit to prevent a delay
7501          * in the reporting of vblank events.
7502          */
7503         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7504 }
7505
7506 static void cherryview_init_clock_gating(struct drm_device *dev)
7507 {
7508         struct drm_i915_private *dev_priv = to_i915(dev);
7509
7510         /* WaVSRefCountFullforceMissDisable:chv */
7511         /* WaDSRefCountFullforceMissDisable:chv */
7512         I915_WRITE(GEN7_FF_THREAD_MODE,
7513                    I915_READ(GEN7_FF_THREAD_MODE) &
7514                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7515
7516         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7517         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7518                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7519
7520         /* WaDisableCSUnitClockGating:chv */
7521         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7522                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7523
7524         /* WaDisableSDEUnitClockGating:chv */
7525         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7526                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7527
7528         /*
7529          * WaProgramL3SqcReg1Default:chv
7530          * See gfxspecs/Related Documents/Performance Guide/
7531          * LSQC Setting Recommendations.
7532          */
7533         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7534
7535         /*
7536          * GTT cache may not work with big pages, so if those
7537          * are ever enabled GTT cache may need to be disabled.
7538          */
7539         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7540 }
7541
7542 static void g4x_init_clock_gating(struct drm_device *dev)
7543 {
7544         struct drm_i915_private *dev_priv = to_i915(dev);
7545         uint32_t dspclk_gate;
7546
7547         I915_WRITE(RENCLK_GATE_D1, 0);
7548         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7549                    GS_UNIT_CLOCK_GATE_DISABLE |
7550                    CL_UNIT_CLOCK_GATE_DISABLE);
7551         I915_WRITE(RAMCLK_GATE_D, 0);
7552         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7553                 OVRUNIT_CLOCK_GATE_DISABLE |
7554                 OVCUNIT_CLOCK_GATE_DISABLE;
7555         if (IS_GM45(dev_priv))
7556                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7557         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7558
7559         /* WaDisableRenderCachePipelinedFlush */
7560         I915_WRITE(CACHE_MODE_0,
7561                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7562
7563         /* WaDisable_RenderCache_OperationalFlush:g4x */
7564         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7565
7566         g4x_disable_trickle_feed(dev);
7567 }
7568
7569 static void crestline_init_clock_gating(struct drm_device *dev)
7570 {
7571         struct drm_i915_private *dev_priv = to_i915(dev);
7572
7573         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7574         I915_WRITE(RENCLK_GATE_D2, 0);
7575         I915_WRITE(DSPCLK_GATE_D, 0);
7576         I915_WRITE(RAMCLK_GATE_D, 0);
7577         I915_WRITE16(DEUC, 0);
7578         I915_WRITE(MI_ARB_STATE,
7579                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7580
7581         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7582         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7583 }
7584
7585 static void broadwater_init_clock_gating(struct drm_device *dev)
7586 {
7587         struct drm_i915_private *dev_priv = to_i915(dev);
7588
7589         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7590                    I965_RCC_CLOCK_GATE_DISABLE |
7591                    I965_RCPB_CLOCK_GATE_DISABLE |
7592                    I965_ISC_CLOCK_GATE_DISABLE |
7593                    I965_FBC_CLOCK_GATE_DISABLE);
7594         I915_WRITE(RENCLK_GATE_D2, 0);
7595         I915_WRITE(MI_ARB_STATE,
7596                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7597
7598         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7599         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7600 }
7601
7602 static void gen3_init_clock_gating(struct drm_device *dev)
7603 {
7604         struct drm_i915_private *dev_priv = to_i915(dev);
7605         u32 dstate = I915_READ(D_STATE);
7606
7607         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7608                 DSTATE_DOT_CLOCK_GATING;
7609         I915_WRITE(D_STATE, dstate);
7610
7611         if (IS_PINEVIEW(dev))
7612                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7613
7614         /* IIR "flip pending" means done if this bit is set */
7615         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7616
7617         /* interrupts should cause a wake up from C3 */
7618         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7619
7620         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7621         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7622
7623         I915_WRITE(MI_ARB_STATE,
7624                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7625 }
7626
7627 static void i85x_init_clock_gating(struct drm_device *dev)
7628 {
7629         struct drm_i915_private *dev_priv = to_i915(dev);
7630
7631         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7632
7633         /* interrupts should cause a wake up from C3 */
7634         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7635                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7636
7637         I915_WRITE(MEM_MODE,
7638                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7639 }
7640
7641 static void i830_init_clock_gating(struct drm_device *dev)
7642 {
7643         struct drm_i915_private *dev_priv = to_i915(dev);
7644
7645         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7646
7647         I915_WRITE(MEM_MODE,
7648                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7649                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7650 }
7651
7652 void intel_init_clock_gating(struct drm_device *dev)
7653 {
7654         struct drm_i915_private *dev_priv = to_i915(dev);
7655
7656         dev_priv->display.init_clock_gating(dev);
7657 }
7658
7659 void intel_suspend_hw(struct drm_device *dev)
7660 {
7661         if (HAS_PCH_LPT(to_i915(dev)))
7662                 lpt_suspend_hw(dev);
7663 }
7664
7665 static void nop_init_clock_gating(struct drm_device *dev)
7666 {
7667         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7668 }
7669
7670 /**
7671  * intel_init_clock_gating_hooks - setup the clock gating hooks
7672  * @dev_priv: device private
7673  *
7674  * Setup the hooks that configure which clocks of a given platform can be
7675  * gated and also apply various GT and display specific workarounds for these
7676  * platforms. Note that some GT specific workarounds are applied separately
7677  * when GPU contexts or batchbuffers start their execution.
7678  */
7679 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7680 {
7681         if (IS_SKYLAKE(dev_priv))
7682                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7683         else if (IS_KABYLAKE(dev_priv))
7684                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7685         else if (IS_BROXTON(dev_priv))
7686                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7687         else if (IS_BROADWELL(dev_priv))
7688                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7689         else if (IS_CHERRYVIEW(dev_priv))
7690                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7691         else if (IS_HASWELL(dev_priv))
7692                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7693         else if (IS_IVYBRIDGE(dev_priv))
7694                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7695         else if (IS_VALLEYVIEW(dev_priv))
7696                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7697         else if (IS_GEN6(dev_priv))
7698                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7699         else if (IS_GEN5(dev_priv))
7700                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7701         else if (IS_G4X(dev_priv))
7702                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7703         else if (IS_CRESTLINE(dev_priv))
7704                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7705         else if (IS_BROADWATER(dev_priv))
7706                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7707         else if (IS_GEN3(dev_priv))
7708                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7709         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7710                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7711         else if (IS_GEN2(dev_priv))
7712                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7713         else {
7714                 MISSING_CASE(INTEL_DEVID(dev_priv));
7715                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7716         }
7717 }
7718
7719 /* Set up chip specific power management-related functions */
7720 void intel_init_pm(struct drm_device *dev)
7721 {
7722         struct drm_i915_private *dev_priv = to_i915(dev);
7723
7724         intel_fbc_init(dev_priv);
7725
7726         /* For cxsr */
7727         if (IS_PINEVIEW(dev))
7728                 i915_pineview_get_mem_freq(dev);
7729         else if (IS_GEN5(dev_priv))
7730                 i915_ironlake_get_mem_freq(dev);
7731
7732         /* For FIFO watermark updates */
7733         if (INTEL_INFO(dev)->gen >= 9) {
7734                 skl_setup_wm_latency(dev);
7735                 dev_priv->display.update_wm = skl_update_wm;
7736                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7737         } else if (HAS_PCH_SPLIT(dev_priv)) {
7738                 ilk_setup_wm_latency(dev);
7739
7740                 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
7741                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7742                     (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
7743                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7744                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7745                         dev_priv->display.compute_intermediate_wm =
7746                                 ilk_compute_intermediate_wm;
7747                         dev_priv->display.initial_watermarks =
7748                                 ilk_initial_watermarks;
7749                         dev_priv->display.optimize_watermarks =
7750                                 ilk_optimize_watermarks;
7751                 } else {
7752                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7753                                       "Disable CxSR\n");
7754                 }
7755         } else if (IS_CHERRYVIEW(dev_priv)) {
7756                 vlv_setup_wm_latency(dev);
7757                 dev_priv->display.update_wm = vlv_update_wm;
7758         } else if (IS_VALLEYVIEW(dev_priv)) {
7759                 vlv_setup_wm_latency(dev);
7760                 dev_priv->display.update_wm = vlv_update_wm;
7761         } else if (IS_PINEVIEW(dev)) {
7762                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
7763                                             dev_priv->is_ddr3,
7764                                             dev_priv->fsb_freq,
7765                                             dev_priv->mem_freq)) {
7766                         DRM_INFO("failed to find known CxSR latency "
7767                                  "(found ddr%s fsb freq %d, mem freq %d), "
7768                                  "disabling CxSR\n",
7769                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7770                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7771                         /* Disable CxSR and never update its watermark again */
7772                         intel_set_memory_cxsr(dev_priv, false);
7773                         dev_priv->display.update_wm = NULL;
7774                 } else
7775                         dev_priv->display.update_wm = pineview_update_wm;
7776         } else if (IS_G4X(dev_priv)) {
7777                 dev_priv->display.update_wm = g4x_update_wm;
7778         } else if (IS_GEN4(dev_priv)) {
7779                 dev_priv->display.update_wm = i965_update_wm;
7780         } else if (IS_GEN3(dev_priv)) {
7781                 dev_priv->display.update_wm = i9xx_update_wm;
7782                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7783         } else if (IS_GEN2(dev_priv)) {
7784                 if (INTEL_INFO(dev)->num_pipes == 1) {
7785                         dev_priv->display.update_wm = i845_update_wm;
7786                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7787                 } else {
7788                         dev_priv->display.update_wm = i9xx_update_wm;
7789                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7790                 }
7791         } else {
7792                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7793         }
7794 }
7795
7796 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7797 {
7798         uint32_t flags =
7799                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7800
7801         switch (flags) {
7802         case GEN6_PCODE_SUCCESS:
7803                 return 0;
7804         case GEN6_PCODE_UNIMPLEMENTED_CMD:
7805         case GEN6_PCODE_ILLEGAL_CMD:
7806                 return -ENXIO;
7807         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7808         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7809                 return -EOVERFLOW;
7810         case GEN6_PCODE_TIMEOUT:
7811                 return -ETIMEDOUT;
7812         default:
7813                 MISSING_CASE(flags)
7814                 return 0;
7815         }
7816 }
7817
7818 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7819 {
7820         uint32_t flags =
7821                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7822
7823         switch (flags) {
7824         case GEN6_PCODE_SUCCESS:
7825                 return 0;
7826         case GEN6_PCODE_ILLEGAL_CMD:
7827                 return -ENXIO;
7828         case GEN7_PCODE_TIMEOUT:
7829                 return -ETIMEDOUT;
7830         case GEN7_PCODE_ILLEGAL_DATA:
7831                 return -EINVAL;
7832         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7833                 return -EOVERFLOW;
7834         default:
7835                 MISSING_CASE(flags);
7836                 return 0;
7837         }
7838 }
7839
7840 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7841 {
7842         int status;
7843
7844         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7845
7846         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7847          * use te fw I915_READ variants to reduce the amount of work
7848          * required when reading/writing.
7849          */
7850
7851         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7852                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7853                 return -EAGAIN;
7854         }
7855
7856         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7857         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7858         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7859
7860         if (intel_wait_for_register_fw(dev_priv,
7861                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7862                                        500)) {
7863                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7864                 return -ETIMEDOUT;
7865         }
7866
7867         *val = I915_READ_FW(GEN6_PCODE_DATA);
7868         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7869
7870         if (INTEL_GEN(dev_priv) > 6)
7871                 status = gen7_check_mailbox_status(dev_priv);
7872         else
7873                 status = gen6_check_mailbox_status(dev_priv);
7874
7875         if (status) {
7876                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7877                                  status);
7878                 return status;
7879         }
7880
7881         return 0;
7882 }
7883
7884 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7885                             u32 mbox, u32 val)
7886 {
7887         int status;
7888
7889         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7890
7891         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7892          * use te fw I915_READ variants to reduce the amount of work
7893          * required when reading/writing.
7894          */
7895
7896         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7897                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7898                 return -EAGAIN;
7899         }
7900
7901         I915_WRITE_FW(GEN6_PCODE_DATA, val);
7902         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7903
7904         if (intel_wait_for_register_fw(dev_priv,
7905                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7906                                        500)) {
7907                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7908                 return -ETIMEDOUT;
7909         }
7910
7911         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7912
7913         if (INTEL_GEN(dev_priv) > 6)
7914                 status = gen7_check_mailbox_status(dev_priv);
7915         else
7916                 status = gen6_check_mailbox_status(dev_priv);
7917
7918         if (status) {
7919                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7920                                  status);
7921                 return status;
7922         }
7923
7924         return 0;
7925 }
7926
7927 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7928 {
7929         /*
7930          * N = val - 0xb7
7931          * Slow = Fast = GPLL ref * N
7932          */
7933         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7934 }
7935
7936 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7937 {
7938         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7939 }
7940
7941 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7942 {
7943         /*
7944          * N = val / 2
7945          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7946          */
7947         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7948 }
7949
7950 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7951 {
7952         /* CHV needs even values */
7953         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7954 }
7955
7956 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7957 {
7958         if (IS_GEN9(dev_priv))
7959                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7960                                          GEN9_FREQ_SCALER);
7961         else if (IS_CHERRYVIEW(dev_priv))
7962                 return chv_gpu_freq(dev_priv, val);
7963         else if (IS_VALLEYVIEW(dev_priv))
7964                 return byt_gpu_freq(dev_priv, val);
7965         else
7966                 return val * GT_FREQUENCY_MULTIPLIER;
7967 }
7968
7969 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7970 {
7971         if (IS_GEN9(dev_priv))
7972                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7973                                          GT_FREQUENCY_MULTIPLIER);
7974         else if (IS_CHERRYVIEW(dev_priv))
7975                 return chv_freq_opcode(dev_priv, val);
7976         else if (IS_VALLEYVIEW(dev_priv))
7977                 return byt_freq_opcode(dev_priv, val);
7978         else
7979                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7980 }
7981
7982 struct request_boost {
7983         struct work_struct work;
7984         struct drm_i915_gem_request *req;
7985 };
7986
7987 static void __intel_rps_boost_work(struct work_struct *work)
7988 {
7989         struct request_boost *boost = container_of(work, struct request_boost, work);
7990         struct drm_i915_gem_request *req = boost->req;
7991
7992         if (!i915_gem_request_completed(req))
7993                 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7994
7995         i915_gem_request_put(req);
7996         kfree(boost);
7997 }
7998
7999 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
8000 {
8001         struct request_boost *boost;
8002
8003         if (req == NULL || INTEL_GEN(req->i915) < 6)
8004                 return;
8005
8006         if (i915_gem_request_completed(req))
8007                 return;
8008
8009         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8010         if (boost == NULL)
8011                 return;
8012
8013         boost->req = i915_gem_request_get(req);
8014
8015         INIT_WORK(&boost->work, __intel_rps_boost_work);
8016         queue_work(req->i915->wq, &boost->work);
8017 }
8018
8019 void intel_pm_setup(struct drm_device *dev)
8020 {
8021         struct drm_i915_private *dev_priv = to_i915(dev);
8022
8023         mutex_init(&dev_priv->rps.hw_lock);
8024         spin_lock_init(&dev_priv->rps.client_lock);
8025
8026         INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8027                           __intel_autoenable_gt_powersave);
8028         INIT_LIST_HEAD(&dev_priv->rps.clients);
8029
8030         dev_priv->pm.suspended = false;
8031         atomic_set(&dev_priv->pm.wakeref_count, 0);
8032 }