drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34 #include <drm/drm_atomic_helper.h>
  35
  36 /**
  37  * DOC: RC6
  38  *
  39  * RC6 is a special power stage which allows the GPU to enter an very
  40  * low-voltage mode when idle, using down to 0V while at this stage.  This
  41  * stage is entered automatically when the GPU is idle when RC6 support is
  42  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  43  *
  44  * There are different RC6 modes available in Intel GPU, which differentiate
  45  * among each other with the latency required to enter and leave RC6 and
  46  * voltage consumed by the GPU in different states.
  47  *
  48  * The combination of the following flags define which states GPU is allowed
  49  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  50  * RC6pp is deepest RC6. Their support by hardware varies according to the
  51  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  52  * which brings the most power savings; deeper states save more power, but
  53  * require higher latency to switch to and wake up.
  54  */
  55 #define INTEL_RC6_ENABLE                        (1<<0)
  56 #define INTEL_RC6p_ENABLE                       (1<<1)
  57 #define INTEL_RC6pp_ENABLE                      (1<<2)
  58
  59 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
  60 {
  61         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
  62         I915_WRITE(CHICKEN_PAR1_1,
  63                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  64
  65         I915_WRITE(GEN8_CONFIG0,
  66                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  67
  68         /* WaEnableChickenDCPR:skl,bxt,kbl */
  69         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  70                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  71
  72         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
  73         /* WaFbcWakeMemOn:skl,bxt,kbl */
  74         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  75                    DISP_FBC_WM_DIS |
  76                    DISP_FBC_MEMORY_WAKE);
  77
  78         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
  79         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  80                    ILK_DPFC_DISABLE_DUMMY0);
  81 }
  82
  83 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
  84 {
  85         gen9_init_clock_gating(dev_priv);
  86
  87         /* WaDisableSDEUnitClockGating:bxt */
  88         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  89                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  90
  91         /*
  92          * FIXME:
  93          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  94          */
  95         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  96                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  97
  98         /*
  99          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 100          * to stay fully on.
 101          */
 102         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
 103                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 104                            PWM1_GATING_DIS | PWM2_GATING_DIS);
 105 }
 106
 107 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
 108 {
 109         u32 tmp;
 110
 111         tmp = I915_READ(CLKCFG);
 112
 113         switch (tmp & CLKCFG_FSB_MASK) {
 114         case CLKCFG_FSB_533:
 115                 dev_priv->fsb_freq = 533; /* 133*4 */
 116                 break;
 117         case CLKCFG_FSB_800:
 118                 dev_priv->fsb_freq = 800; /* 200*4 */
 119                 break;
 120         case CLKCFG_FSB_667:
 121                 dev_priv->fsb_freq =  667; /* 167*4 */
 122                 break;
 123         case CLKCFG_FSB_400:
 124                 dev_priv->fsb_freq = 400; /* 100*4 */
 125                 break;
 126         }
 127
 128         switch (tmp & CLKCFG_MEM_MASK) {
 129         case CLKCFG_MEM_533:
 130                 dev_priv->mem_freq = 533;
 131                 break;
 132         case CLKCFG_MEM_667:
 133                 dev_priv->mem_freq = 667;
 134                 break;
 135         case CLKCFG_MEM_800:
 136                 dev_priv->mem_freq = 800;
 137                 break;
 138         }
 139
 140         /* detect pineview DDR3 setting */
 141         tmp = I915_READ(CSHRDDR3CTL);
 142         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 143 }
 144
 145 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
 146 {
 147         u16 ddrpll, csipll;
 148
 149         ddrpll = I915_READ16(DDRMPLL1);
 150         csipll = I915_READ16(CSIPLL0);
 151
 152         switch (ddrpll & 0xff) {
 153         case 0xc:
 154                 dev_priv->mem_freq = 800;
 155                 break;
 156         case 0x10:
 157                 dev_priv->mem_freq = 1066;
 158                 break;
 159         case 0x14:
 160                 dev_priv->mem_freq = 1333;
 161                 break;
 162         case 0x18:
 163                 dev_priv->mem_freq = 1600;
 164                 break;
 165         default:
 166                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 167                                  ddrpll & 0xff);
 168                 dev_priv->mem_freq = 0;
 169                 break;
 170         }
 171
 172         dev_priv->ips.r_t = dev_priv->mem_freq;
 173
 174         switch (csipll & 0x3ff) {
 175         case 0x00c:
 176                 dev_priv->fsb_freq = 3200;
 177                 break;
 178         case 0x00e:
 179                 dev_priv->fsb_freq = 3733;
 180                 break;
 181         case 0x010:
 182                 dev_priv->fsb_freq = 4266;
 183                 break;
 184         case 0x012:
 185                 dev_priv->fsb_freq = 4800;
 186                 break;
 187         case 0x014:
 188                 dev_priv->fsb_freq = 5333;
 189                 break;
 190         case 0x016:
 191                 dev_priv->fsb_freq = 5866;
 192                 break;
 193         case 0x018:
 194                 dev_priv->fsb_freq = 6400;
 195                 break;
 196         default:
 197                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 198                                  csipll & 0x3ff);
 199                 dev_priv->fsb_freq = 0;
 200                 break;
 201         }
 202
 203         if (dev_priv->fsb_freq == 3200) {
 204                 dev_priv->ips.c_m = 0;
 205         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 206                 dev_priv->ips.c_m = 1;
 207         } else {
 208                 dev_priv->ips.c_m = 2;
 209         }
 210 }
 211
 212 static const struct cxsr_latency cxsr_latency_table[] = {
 213         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 214         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 215         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 216         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 217         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 218
 219         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 220         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 221         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 222         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 223         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 224
 225         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 226         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 227         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 228         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 229         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 230
 231         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 232         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 233         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 234         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 235         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 236
 237         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 238         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 239         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 240         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 241         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 242
 243         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 244         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 245         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 246         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 247         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 248 };
 249
 250 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 251                                                          bool is_ddr3,
 252                                                          int fsb,
 253                                                          int mem)
 254 {
 255         const struct cxsr_latency *latency;
 256         int i;
 257
 258         if (fsb == 0 || mem == 0)
 259                 return NULL;
 260
 261         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 262                 latency = &cxsr_latency_table[i];
 263                 if (is_desktop == latency->is_desktop &&
 264                     is_ddr3 == latency->is_ddr3 &&
 265                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 266                         return latency;
 267         }
 268
 269         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 270
 271         return NULL;
 272 }
 273
 274 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 275 {
 276         u32 val;
 277
 278         mutex_lock(&dev_priv->rps.hw_lock);
 279
 280         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 281         if (enable)
 282                 val &= ~FORCE_DDR_HIGH_FREQ;
 283         else
 284                 val |= FORCE_DDR_HIGH_FREQ;
 285         val &= ~FORCE_DDR_LOW_FREQ;
 286         val |= FORCE_DDR_FREQ_REQ_ACK;
 287         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 288
 289         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 290                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 291                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 292
 293         mutex_unlock(&dev_priv->rps.hw_lock);
 294 }
 295
 296 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 297 {
 298         u32 val;
 299
 300         mutex_lock(&dev_priv->rps.hw_lock);
 301
 302         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 303         if (enable)
 304                 val |= DSP_MAXFIFO_PM5_ENABLE;
 305         else
 306                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 307         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 308
 309         mutex_unlock(&dev_priv->rps.hw_lock);
 310 }
 311
 312 #define FW_WM(value, plane) \
 313         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 314
 315 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 316 {
 317         u32 val;
 318
 319         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 320                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 321                 POSTING_READ(FW_BLC_SELF_VLV);
 322                 dev_priv->wm.vlv.cxsr = enable;
 323         } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
 324                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 325                 POSTING_READ(FW_BLC_SELF);
 326         } else if (IS_PINEVIEW(dev_priv)) {
 327                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 328                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 329                 I915_WRITE(DSPFW3, val);
 330                 POSTING_READ(DSPFW3);
 331         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 332                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 333                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 334                 I915_WRITE(FW_BLC_SELF, val);
 335                 POSTING_READ(FW_BLC_SELF);
 336         } else if (IS_I915GM(dev_priv)) {
 337                 /*
 338                  * FIXME can't find a bit like this for 915G, and
 339                  * and yet it does have the related watermark in
 340                  * FW_BLC_SELF. What's going on?
 341                  */
 342                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 343                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 344                 I915_WRITE(INSTPM, val);
 345                 POSTING_READ(INSTPM);
 346         } else {
 347                 return;
 348         }
 349
 350         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 351                       enable ? "enabled" : "disabled");
 352 }
 353
 354
 355 /*
 356  * Latency for FIFO fetches is dependent on several factors:
 357  *   - memory configuration (speed, channels)
 358  *   - chipset
 359  *   - current MCH state
 360  * It can be fairly high in some situations, so here we assume a fairly
 361  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 362  * set this value too high, the FIFO will fetch frequently to stay full)
 363  * and power consumption (set it too low to save power and we might see
 364  * FIFO underruns and display "flicker").
 365  *
 366  * A value of 5us seems to be a good balance; safe for very low end
 367  * platforms but not overly aggressive on lower latency configs.
 368  */
 369 static const int pessimal_latency_ns = 5000;
 370
 371 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 372         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 373
 374 static int vlv_get_fifo_size(struct drm_i915_private *dev_priv,
 375                               enum pipe pipe, int plane)
 376 {
 377         int sprite0_start, sprite1_start, size;
 378
 379         switch (pipe) {
 380                 uint32_t dsparb, dsparb2, dsparb3;
 381         case PIPE_A:
 382                 dsparb = I915_READ(DSPARB);
 383                 dsparb2 = I915_READ(DSPARB2);
 384                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 385                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 386                 break;
 387         case PIPE_B:
 388                 dsparb = I915_READ(DSPARB);
 389                 dsparb2 = I915_READ(DSPARB2);
 390                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 391                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 392                 break;
 393         case PIPE_C:
 394                 dsparb2 = I915_READ(DSPARB2);
 395                 dsparb3 = I915_READ(DSPARB3);
 396                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 397                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 398                 break;
 399         default:
 400                 return 0;
 401         }
 402
 403         switch (plane) {
 404         case 0:
 405                 size = sprite0_start;
 406                 break;
 407         case 1:
 408                 size = sprite1_start - sprite0_start;
 409                 break;
 410         case 2:
 411                 size = 512 - 1 - sprite1_start;
 412                 break;
 413         default:
 414                 return 0;
 415         }
 416
 417         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 418                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 419                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 420                       size);
 421
 422         return size;
 423 }
 424
 425 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 426 {
 427         uint32_t dsparb = I915_READ(DSPARB);
 428         int size;
 429
 430         size = dsparb & 0x7f;
 431         if (plane)
 432                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 433
 434         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 435                       plane ? "B" : "A", size);
 436
 437         return size;
 438 }
 439
 440 static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 441 {
 442         uint32_t dsparb = I915_READ(DSPARB);
 443         int size;
 444
 445         size = dsparb & 0x1ff;
 446         if (plane)
 447                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 448         size >>= 1; /* Convert to cachelines */
 449
 450         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 451                       plane ? "B" : "A", size);
 452
 453         return size;
 454 }
 455
 456 static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 457 {
 458         uint32_t dsparb = I915_READ(DSPARB);
 459         int size;
 460
 461         size = dsparb & 0x7f;
 462         size >>= 2; /* Convert to cachelines */
 463
 464         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 465                       plane ? "B" : "A",
 466                       size);
 467
 468         return size;
 469 }
 470
 471 /* Pineview has different values for various configs */
 472 static const struct intel_watermark_params pineview_display_wm = {
 473         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 474         .max_wm = PINEVIEW_MAX_WM,
 475         .default_wm = PINEVIEW_DFT_WM,
 476         .guard_size = PINEVIEW_GUARD_WM,
 477         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 478 };
 479 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 480         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 481         .max_wm = PINEVIEW_MAX_WM,
 482         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 483         .guard_size = PINEVIEW_GUARD_WM,
 484         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 485 };
 486 static const struct intel_watermark_params pineview_cursor_wm = {
 487         .fifo_size = PINEVIEW_CURSOR_FIFO,
 488         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 489         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 490         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 491         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 492 };
 493 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 494         .fifo_size = PINEVIEW_CURSOR_FIFO,
 495         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 496         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 497         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 498         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 499 };
 500 static const struct intel_watermark_params g4x_wm_info = {
 501         .fifo_size = G4X_FIFO_SIZE,
 502         .max_wm = G4X_MAX_WM,
 503         .default_wm = G4X_MAX_WM,
 504         .guard_size = 2,
 505         .cacheline_size = G4X_FIFO_LINE_SIZE,
 506 };
 507 static const struct intel_watermark_params g4x_cursor_wm_info = {
 508         .fifo_size = I965_CURSOR_FIFO,
 509         .max_wm = I965_CURSOR_MAX_WM,
 510         .default_wm = I965_CURSOR_DFT_WM,
 511         .guard_size = 2,
 512         .cacheline_size = G4X_FIFO_LINE_SIZE,
 513 };
 514 static const struct intel_watermark_params i965_cursor_wm_info = {
 515         .fifo_size = I965_CURSOR_FIFO,
 516         .max_wm = I965_CURSOR_MAX_WM,
 517         .default_wm = I965_CURSOR_DFT_WM,
 518         .guard_size = 2,
 519         .cacheline_size = I915_FIFO_LINE_SIZE,
 520 };
 521 static const struct intel_watermark_params i945_wm_info = {
 522         .fifo_size = I945_FIFO_SIZE,
 523         .max_wm = I915_MAX_WM,
 524         .default_wm = 1,
 525         .guard_size = 2,
 526         .cacheline_size = I915_FIFO_LINE_SIZE,
 527 };
 528 static const struct intel_watermark_params i915_wm_info = {
 529         .fifo_size = I915_FIFO_SIZE,
 530         .max_wm = I915_MAX_WM,
 531         .default_wm = 1,
 532         .guard_size = 2,
 533         .cacheline_size = I915_FIFO_LINE_SIZE,
 534 };
 535 static const struct intel_watermark_params i830_a_wm_info = {
 536         .fifo_size = I855GM_FIFO_SIZE,
 537         .max_wm = I915_MAX_WM,
 538         .default_wm = 1,
 539         .guard_size = 2,
 540         .cacheline_size = I830_FIFO_LINE_SIZE,
 541 };
 542 static const struct intel_watermark_params i830_bc_wm_info = {
 543         .fifo_size = I855GM_FIFO_SIZE,
 544         .max_wm = I915_MAX_WM/2,
 545         .default_wm = 1,
 546         .guard_size = 2,
 547         .cacheline_size = I830_FIFO_LINE_SIZE,
 548 };
 549 static const struct intel_watermark_params i845_wm_info = {
 550         .fifo_size = I830_FIFO_SIZE,
 551         .max_wm = I915_MAX_WM,
 552         .default_wm = 1,
 553         .guard_size = 2,
 554         .cacheline_size = I830_FIFO_LINE_SIZE,
 555 };
 556
 557 /**
 558  * intel_calculate_wm - calculate watermark level
 559  * @clock_in_khz: pixel clock
 560  * @wm: chip FIFO params
 561  * @cpp: bytes per pixel
 562  * @latency_ns: memory latency for the platform
 563  *
 564  * Calculate the watermark level (the level at which the display plane will
 565  * start fetching from memory again).  Each chip has a different display
 566  * FIFO size and allocation, so the caller needs to figure that out and pass
 567  * in the correct intel_watermark_params structure.
 568  *
 569  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 570  * on the pixel size.  When it reaches the watermark level, it'll start
 571  * fetching FIFO line sized based chunks from memory until the FIFO fills
 572  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 573  * will occur, and a display engine hang could result.
 574  */
 575 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 576                                         const struct intel_watermark_params *wm,
 577                                         int fifo_size, int cpp,
 578                                         unsigned long latency_ns)
 579 {
 580         long entries_required, wm_size;
 581
 582         /*
 583          * Note: we need to make sure we don't overflow for various clock &
 584          * latency values.
 585          * clocks go from a few thousand to several hundred thousand.
 586          * latency is usually a few thousand
 587          */
 588         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 589                 1000;
 590         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 591
 592         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 593
 594         wm_size = fifo_size - (entries_required + wm->guard_size);
 595
 596         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 597
 598         /* Don't promote wm_size to unsigned... */
 599         if (wm_size > (long)wm->max_wm)
 600                 wm_size = wm->max_wm;
 601         if (wm_size <= 0)
 602                 wm_size = wm->default_wm;
 603
 604         /*
 605          * Bspec seems to indicate that the value shouldn't be lower than
 606          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 607          * Lets go for 8 which is the burst size since certain platforms
 608          * already use a hardcoded 8 (which is what the spec says should be
 609          * done).
 610          */
 611         if (wm_size <= 8)
 612                 wm_size = 8;
 613
 614         return wm_size;
 615 }
 616
 617 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 618 {
 619         struct intel_crtc *crtc, *enabled = NULL;
 620
 621         for_each_intel_crtc(&dev_priv->drm, crtc) {
 622                 if (intel_crtc_active(crtc)) {
 623                         if (enabled)
 624                                 return NULL;
 625                         enabled = crtc;
 626                 }
 627         }
 628
 629         return enabled;
 630 }
 631
 632 static void pineview_update_wm(struct intel_crtc *unused_crtc)
 633 {
 634         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 635         struct intel_crtc *crtc;
 636         const struct cxsr_latency *latency;
 637         u32 reg;
 638         unsigned long wm;
 639
 640         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 641                                          dev_priv->is_ddr3,
 642                                          dev_priv->fsb_freq,
 643                                          dev_priv->mem_freq);
 644         if (!latency) {
 645                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 646                 intel_set_memory_cxsr(dev_priv, false);
 647                 return;
 648         }
 649
 650         crtc = single_enabled_crtc(dev_priv);
 651         if (crtc) {
 652                 const struct drm_display_mode *adjusted_mode =
 653                         &crtc->config->base.adjusted_mode;
 654                 const struct drm_framebuffer *fb =
 655                         crtc->base.primary->state->fb;
 656                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 657                 int clock = adjusted_mode->crtc_clock;
 658
 659                 /* Display SR */
 660                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 661                                         pineview_display_wm.fifo_size,
 662                                         cpp, latency->display_sr);
 663                 reg = I915_READ(DSPFW1);
 664                 reg &= ~DSPFW_SR_MASK;
 665                 reg |= FW_WM(wm, SR);
 666                 I915_WRITE(DSPFW1, reg);
 667                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 668
 669                 /* cursor SR */
 670                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 671                                         pineview_display_wm.fifo_size,
 672                                         cpp, latency->cursor_sr);
 673                 reg = I915_READ(DSPFW3);
 674                 reg &= ~DSPFW_CURSOR_SR_MASK;
 675                 reg |= FW_WM(wm, CURSOR_SR);
 676                 I915_WRITE(DSPFW3, reg);
 677
 678                 /* Display HPLL off SR */
 679                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 680                                         pineview_display_hplloff_wm.fifo_size,
 681                                         cpp, latency->display_hpll_disable);
 682                 reg = I915_READ(DSPFW3);
 683                 reg &= ~DSPFW_HPLL_SR_MASK;
 684                 reg |= FW_WM(wm, HPLL_SR);
 685                 I915_WRITE(DSPFW3, reg);
 686
 687                 /* cursor HPLL off SR */
 688                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 689                                         pineview_display_hplloff_wm.fifo_size,
 690                                         cpp, latency->cursor_hpll_disable);
 691                 reg = I915_READ(DSPFW3);
 692                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 693                 reg |= FW_WM(wm, HPLL_CURSOR);
 694                 I915_WRITE(DSPFW3, reg);
 695                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 696
 697                 intel_set_memory_cxsr(dev_priv, true);
 698         } else {
 699                 intel_set_memory_cxsr(dev_priv, false);
 700         }
 701 }
 702
 703 static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
 704                             int plane,
 705                             const struct intel_watermark_params *display,
 706                             int display_latency_ns,
 707                             const struct intel_watermark_params *cursor,
 708                             int cursor_latency_ns,
 709                             int *plane_wm,
 710                             int *cursor_wm)
 711 {
 712         struct intel_crtc *crtc;
 713         const struct drm_display_mode *adjusted_mode;
 714         const struct drm_framebuffer *fb;
 715         int htotal, hdisplay, clock, cpp;
 716         int line_time_us, line_count;
 717         int entries, tlb_miss;
 718
 719         crtc = intel_get_crtc_for_plane(dev_priv, plane);
 720         if (!intel_crtc_active(crtc)) {
 721                 *cursor_wm = cursor->guard_size;
 722                 *plane_wm = display->guard_size;
 723                 return false;
 724         }
 725
 726         adjusted_mode = &crtc->config->base.adjusted_mode;
 727         fb = crtc->base.primary->state->fb;
 728         clock = adjusted_mode->crtc_clock;
 729         htotal = adjusted_mode->crtc_htotal;
 730         hdisplay = crtc->config->pipe_src_w;
 731         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 732
 733         /* Use the small buffer method to calculate plane watermark */
 734         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 735         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 736         if (tlb_miss > 0)
 737                 entries += tlb_miss;
 738         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 739         *plane_wm = entries + display->guard_size;
 740         if (*plane_wm > (int)display->max_wm)
 741                 *plane_wm = display->max_wm;
 742
 743         /* Use the large buffer method to calculate cursor watermark */
 744         line_time_us = max(htotal * 1000 / clock, 1);
 745         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 746         entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
 747         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 748         if (tlb_miss > 0)
 749                 entries += tlb_miss;
 750         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 751         *cursor_wm = entries + cursor->guard_size;
 752         if (*cursor_wm > (int)cursor->max_wm)
 753                 *cursor_wm = (int)cursor->max_wm;
 754
 755         return true;
 756 }
 757
 758 /*
 759  * Check the wm result.
 760  *
 761  * If any calculated watermark values is larger than the maximum value that
 762  * can be programmed into the associated watermark register, that watermark
 763  * must be disabled.
 764  */
 765 static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
 766                            int display_wm, int cursor_wm,
 767                            const struct intel_watermark_params *display,
 768                            const struct intel_watermark_params *cursor)
 769 {
 770         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 771                       display_wm, cursor_wm);
 772
 773         if (display_wm > display->max_wm) {
 774                 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
 775                               display_wm, display->max_wm);
 776                 return false;
 777         }
 778
 779         if (cursor_wm > cursor->max_wm) {
 780                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
 781                               cursor_wm, cursor->max_wm);
 782                 return false;
 783         }
 784
 785         if (!(display_wm || cursor_wm)) {
 786                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 787                 return false;
 788         }
 789
 790         return true;
 791 }
 792
 793 static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
 794                              int plane,
 795                              int latency_ns,
 796                              const struct intel_watermark_params *display,
 797                              const struct intel_watermark_params *cursor,
 798                              int *display_wm, int *cursor_wm)
 799 {
 800         struct intel_crtc *crtc;
 801         const struct drm_display_mode *adjusted_mode;
 802         const struct drm_framebuffer *fb;
 803         int hdisplay, htotal, cpp, clock;
 804         unsigned long line_time_us;
 805         int line_count, line_size;
 806         int small, large;
 807         int entries;
 808
 809         if (!latency_ns) {
 810                 *display_wm = *cursor_wm = 0;
 811                 return false;
 812         }
 813
 814         crtc = intel_get_crtc_for_plane(dev_priv, plane);
 815         adjusted_mode = &crtc->config->base.adjusted_mode;
 816         fb = crtc->base.primary->state->fb;
 817         clock = adjusted_mode->crtc_clock;
 818         htotal = adjusted_mode->crtc_htotal;
 819         hdisplay = crtc->config->pipe_src_w;
 820         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 821
 822         line_time_us = max(htotal * 1000 / clock, 1);
 823         line_count = (latency_ns / line_time_us + 1000) / 1000;
 824         line_size = hdisplay * cpp;
 825
 826         /* Use the minimum of the small and large buffer method for primary */
 827         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 828         large = line_count * line_size;
 829
 830         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 831         *display_wm = entries + display->guard_size;
 832
 833         /* calculate the self-refresh watermark for display cursor */
 834         entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
 835         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 836         *cursor_wm = entries + cursor->guard_size;
 837
 838         return g4x_check_srwm(dev_priv,
 839                               *display_wm, *cursor_wm,
 840                               display, cursor);
 841 }
 842
 843 #define FW_WM_VLV(value, plane) \
 844         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 845
 846 static void vlv_write_wm_values(struct intel_crtc *crtc,
 847                                 const struct vlv_wm_values *wm)
 848 {
 849         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 850         enum pipe pipe = crtc->pipe;
 851
 852         I915_WRITE(VLV_DDL(pipe),
 853                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 854                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 855                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 856                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 857
 858         I915_WRITE(DSPFW1,
 859                    FW_WM(wm->sr.plane, SR) |
 860                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 861                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 862                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 863         I915_WRITE(DSPFW2,
 864                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 865                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 866                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 867         I915_WRITE(DSPFW3,
 868                    FW_WM(wm->sr.cursor, CURSOR_SR));
 869
 870         if (IS_CHERRYVIEW(dev_priv)) {
 871                 I915_WRITE(DSPFW7_CHV,
 872                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 873                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 874                 I915_WRITE(DSPFW8_CHV,
 875                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 876                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 877                 I915_WRITE(DSPFW9_CHV,
 878                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 879                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 880                 I915_WRITE(DSPHOWM,
 881                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 882                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 883                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 884                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 885                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 886                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 887                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 888                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 889                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 890                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 891         } else {
 892                 I915_WRITE(DSPFW7,
 893                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 894                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 895                 I915_WRITE(DSPHOWM,
 896                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 897                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 898                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 899                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 900                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 901                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 902                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 903         }
 904
 905         /* zero (unused) WM1 watermarks */
 906         I915_WRITE(DSPFW4, 0);
 907         I915_WRITE(DSPFW5, 0);
 908         I915_WRITE(DSPFW6, 0);
 909         I915_WRITE(DSPHOWM1, 0);
 910
 911         POSTING_READ(DSPFW1);
 912 }
 913
 914 #undef FW_WM_VLV
 915
 916 enum vlv_wm_level {
 917         VLV_WM_LEVEL_PM2,
 918         VLV_WM_LEVEL_PM5,
 919         VLV_WM_LEVEL_DDR_DVFS,
 920 };
 921
 922 /* latency must be in 0.1us units. */
 923 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 924                                    unsigned int pipe_htotal,
 925                                    unsigned int horiz_pixels,
 926                                    unsigned int cpp,
 927                                    unsigned int latency)
 928 {
 929         unsigned int ret;
 930
 931         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 932         ret = (ret + 1) * horiz_pixels * cpp;
 933         ret = DIV_ROUND_UP(ret, 64);
 934
 935         return ret;
 936 }
 937
 938 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
 939 {
 940         /* all latencies in usec */
 941         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 942
 943         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 944
 945         if (IS_CHERRYVIEW(dev_priv)) {
 946                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 947                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 948
 949                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 950         }
 951 }
 952
 953 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 954                                      struct intel_crtc *crtc,
 955                                      const struct intel_plane_state *state,
 956                                      int level)
 957 {
 958         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 959         int clock, htotal, cpp, width, wm;
 960
 961         if (dev_priv->wm.pri_latency[level] == 0)
 962                 return USHRT_MAX;
 963
 964         if (!state->base.visible)
 965                 return 0;
 966
 967         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 968         clock = crtc->config->base.adjusted_mode.crtc_clock;
 969         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 970         width = crtc->config->pipe_src_w;
 971         if (WARN_ON(htotal == 0))
 972                 htotal = 1;
 973
 974         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 975                 /*
 976                  * FIXME the formula gives values that are
 977                  * too big for the cursor FIFO, and hence we
 978                  * would never be able to use cursors. For
 979                  * now just hardcode the watermark.
 980                  */
 981                 wm = 63;
 982         } else {
 983                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 984                                     dev_priv->wm.pri_latency[level] * 10);
 985         }
 986
 987         return min_t(int, wm, USHRT_MAX);
 988 }
 989
 990 static void vlv_compute_fifo(struct intel_crtc *crtc)
 991 {
 992         struct drm_device *dev = crtc->base.dev;
 993         struct vlv_wm_state *wm_state = &crtc->wm_state;
 994         struct intel_plane *plane;
 995         unsigned int total_rate = 0;
 996         const int fifo_size = 512 - 1;
 997         int fifo_extra, fifo_left = fifo_size;
 998
 999         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1000                 struct intel_plane_state *state =
1001                         to_intel_plane_state(plane->base.state);
1002
1003                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1004                         continue;
1005
1006                 if (state->base.visible) {
1007                         wm_state->num_active_planes++;
1008                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1009                 }
1010         }
1011
1012         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1013                 struct intel_plane_state *state =
1014                         to_intel_plane_state(plane->base.state);
1015                 unsigned int rate;
1016
1017                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1018                         plane->wm.fifo_size = 63;
1019                         continue;
1020                 }
1021
1022                 if (!state->base.visible) {
1023                         plane->wm.fifo_size = 0;
1024                         continue;
1025                 }
1026
1027                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1028                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1029                 fifo_left -= plane->wm.fifo_size;
1030         }
1031
1032         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1033
1034         /* spread the remainder evenly */
1035         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1036                 int plane_extra;
1037
1038                 if (fifo_left == 0)
1039                         break;
1040
1041                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1042                         continue;
1043
1044                 /* give it all to the first plane if none are active */
1045                 if (plane->wm.fifo_size == 0 &&
1046                     wm_state->num_active_planes)
1047                         continue;
1048
1049                 plane_extra = min(fifo_extra, fifo_left);
1050                 plane->wm.fifo_size += plane_extra;
1051                 fifo_left -= plane_extra;
1052         }
1053
1054         WARN_ON(fifo_left != 0);
1055 }
1056
1057 static void vlv_invert_wms(struct intel_crtc *crtc)
1058 {
1059         struct vlv_wm_state *wm_state = &crtc->wm_state;
1060         int level;
1061
1062         for (level = 0; level < wm_state->num_levels; level++) {
1063                 struct drm_device *dev = crtc->base.dev;
1064                 const int sr_fifo_size =
1065                         INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
1066                 struct intel_plane *plane;
1067
1068                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1069                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1070
1071                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1072                         switch (plane->base.type) {
1073                                 int sprite;
1074                         case DRM_PLANE_TYPE_CURSOR:
1075                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1076                                         wm_state->wm[level].cursor;
1077                                 break;
1078                         case DRM_PLANE_TYPE_PRIMARY:
1079                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1080                                         wm_state->wm[level].primary;
1081                                 break;
1082                         case DRM_PLANE_TYPE_OVERLAY:
1083                                 sprite = plane->plane;
1084                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1085                                         wm_state->wm[level].sprite[sprite];
1086                                 break;
1087                         }
1088                 }
1089         }
1090 }
1091
1092 static void vlv_compute_wm(struct intel_crtc *crtc)
1093 {
1094         struct drm_device *dev = crtc->base.dev;
1095         struct drm_i915_private *dev_priv = to_i915(dev);
1096         struct vlv_wm_state *wm_state = &crtc->wm_state;
1097         struct intel_plane *plane;
1098         int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1099         int level;
1100
1101         memset(wm_state, 0, sizeof(*wm_state));
1102
1103         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1104         wm_state->num_levels = dev_priv->wm.max_level + 1;
1105
1106         wm_state->num_active_planes = 0;
1107
1108         vlv_compute_fifo(crtc);
1109
1110         if (wm_state->num_active_planes != 1)
1111                 wm_state->cxsr = false;
1112
1113         if (wm_state->cxsr) {
1114                 for (level = 0; level < wm_state->num_levels; level++) {
1115                         wm_state->sr[level].plane = sr_fifo_size;
1116                         wm_state->sr[level].cursor = 63;
1117                 }
1118         }
1119
1120         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1121                 struct intel_plane_state *state =
1122                         to_intel_plane_state(plane->base.state);
1123
1124                 if (!state->base.visible)
1125                         continue;
1126
1127                 /* normal watermarks */
1128                 for (level = 0; level < wm_state->num_levels; level++) {
1129                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1130                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1131
1132                         /* hack */
1133                         if (WARN_ON(level == 0 && wm > max_wm))
1134                                 wm = max_wm;
1135
1136                         if (wm > plane->wm.fifo_size)
1137                                 break;
1138
1139                         switch (plane->base.type) {
1140                                 int sprite;
1141                         case DRM_PLANE_TYPE_CURSOR:
1142                                 wm_state->wm[level].cursor = wm;
1143                                 break;
1144                         case DRM_PLANE_TYPE_PRIMARY:
1145                                 wm_state->wm[level].primary = wm;
1146                                 break;
1147                         case DRM_PLANE_TYPE_OVERLAY:
1148                                 sprite = plane->plane;
1149                                 wm_state->wm[level].sprite[sprite] = wm;
1150                                 break;
1151                         }
1152                 }
1153
1154                 wm_state->num_levels = level;
1155
1156                 if (!wm_state->cxsr)
1157                         continue;
1158
1159                 /* maxfifo watermarks */
1160                 switch (plane->base.type) {
1161                         int sprite, level;
1162                 case DRM_PLANE_TYPE_CURSOR:
1163                         for (level = 0; level < wm_state->num_levels; level++)
1164                                 wm_state->sr[level].cursor =
1165                                         wm_state->wm[level].cursor;
1166                         break;
1167                 case DRM_PLANE_TYPE_PRIMARY:
1168                         for (level = 0; level < wm_state->num_levels; level++)
1169                                 wm_state->sr[level].plane =
1170                                         min(wm_state->sr[level].plane,
1171                                             wm_state->wm[level].primary);
1172                         break;
1173                 case DRM_PLANE_TYPE_OVERLAY:
1174                         sprite = plane->plane;
1175                         for (level = 0; level < wm_state->num_levels; level++)
1176                                 wm_state->sr[level].plane =
1177                                         min(wm_state->sr[level].plane,
1178                                             wm_state->wm[level].sprite[sprite]);
1179                         break;
1180                 }
1181         }
1182
1183         /* clear any (partially) filled invalid levels */
1184         for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
1185                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1186                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1187         }
1188
1189         vlv_invert_wms(crtc);
1190 }
1191
1192 #define VLV_FIFO(plane, value) \
1193         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1194
1195 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1196 {
1197         struct drm_device *dev = crtc->base.dev;
1198         struct drm_i915_private *dev_priv = to_i915(dev);
1199         struct intel_plane *plane;
1200         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1201
1202         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1203                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1204                         WARN_ON(plane->wm.fifo_size != 63);
1205                         continue;
1206                 }
1207
1208                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1209                         sprite0_start = plane->wm.fifo_size;
1210                 else if (plane->plane == 0)
1211                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1212                 else
1213                         fifo_size = sprite1_start + plane->wm.fifo_size;
1214         }
1215
1216         WARN_ON(fifo_size != 512 - 1);
1217
1218         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1219                       pipe_name(crtc->pipe), sprite0_start,
1220                       sprite1_start, fifo_size);
1221
1222         switch (crtc->pipe) {
1223                 uint32_t dsparb, dsparb2, dsparb3;
1224         case PIPE_A:
1225                 dsparb = I915_READ(DSPARB);
1226                 dsparb2 = I915_READ(DSPARB2);
1227
1228                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1229                             VLV_FIFO(SPRITEB, 0xff));
1230                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1231                            VLV_FIFO(SPRITEB, sprite1_start));
1232
1233                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1234                              VLV_FIFO(SPRITEB_HI, 0x1));
1235                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1236                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1237
1238                 I915_WRITE(DSPARB, dsparb);
1239                 I915_WRITE(DSPARB2, dsparb2);
1240                 break;
1241         case PIPE_B:
1242                 dsparb = I915_READ(DSPARB);
1243                 dsparb2 = I915_READ(DSPARB2);
1244
1245                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1246                             VLV_FIFO(SPRITED, 0xff));
1247                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1248                            VLV_FIFO(SPRITED, sprite1_start));
1249
1250                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1251                              VLV_FIFO(SPRITED_HI, 0xff));
1252                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1253                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1254
1255                 I915_WRITE(DSPARB, dsparb);
1256                 I915_WRITE(DSPARB2, dsparb2);
1257                 break;
1258         case PIPE_C:
1259                 dsparb3 = I915_READ(DSPARB3);
1260                 dsparb2 = I915_READ(DSPARB2);
1261
1262                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1263                              VLV_FIFO(SPRITEF, 0xff));
1264                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1265                             VLV_FIFO(SPRITEF, sprite1_start));
1266
1267                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1268                              VLV_FIFO(SPRITEF_HI, 0xff));
1269                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1270                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1271
1272                 I915_WRITE(DSPARB3, dsparb3);
1273                 I915_WRITE(DSPARB2, dsparb2);
1274                 break;
1275         default:
1276                 break;
1277         }
1278 }
1279
1280 #undef VLV_FIFO
1281
1282 static void vlv_merge_wm(struct drm_device *dev,
1283                          struct vlv_wm_values *wm)
1284 {
1285         struct intel_crtc *crtc;
1286         int num_active_crtcs = 0;
1287
1288         wm->level = to_i915(dev)->wm.max_level;
1289         wm->cxsr = true;
1290
1291         for_each_intel_crtc(dev, crtc) {
1292                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1293
1294                 if (!crtc->active)
1295                         continue;
1296
1297                 if (!wm_state->cxsr)
1298                         wm->cxsr = false;
1299
1300                 num_active_crtcs++;
1301                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1302         }
1303
1304         if (num_active_crtcs != 1)
1305                 wm->cxsr = false;
1306
1307         if (num_active_crtcs > 1)
1308                 wm->level = VLV_WM_LEVEL_PM2;
1309
1310         for_each_intel_crtc(dev, crtc) {
1311                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1312                 enum pipe pipe = crtc->pipe;
1313
1314                 if (!crtc->active)
1315                         continue;
1316
1317                 wm->pipe[pipe] = wm_state->wm[wm->level];
1318                 if (wm->cxsr)
1319                         wm->sr = wm_state->sr[wm->level];
1320
1321                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1322                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1323                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1324                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1325         }
1326 }
1327
1328 static void vlv_update_wm(struct intel_crtc *crtc)
1329 {
1330         struct drm_device *dev = crtc->base.dev;
1331         struct drm_i915_private *dev_priv = to_i915(dev);
1332         enum pipe pipe = crtc->pipe;
1333         struct vlv_wm_values wm = {};
1334
1335         vlv_compute_wm(crtc);
1336         vlv_merge_wm(dev, &wm);
1337
1338         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1339                 /* FIXME should be part of crtc atomic commit */
1340                 vlv_pipe_set_fifo_size(crtc);
1341                 return;
1342         }
1343
1344         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1345             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1346                 chv_set_memory_dvfs(dev_priv, false);
1347
1348         if (wm.level < VLV_WM_LEVEL_PM5 &&
1349             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1350                 chv_set_memory_pm5(dev_priv, false);
1351
1352         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1353                 intel_set_memory_cxsr(dev_priv, false);
1354
1355         /* FIXME should be part of crtc atomic commit */
1356         vlv_pipe_set_fifo_size(crtc);
1357
1358         vlv_write_wm_values(crtc, &wm);
1359
1360         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1361                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1362                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1363                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1364                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1365
1366         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1367                 intel_set_memory_cxsr(dev_priv, true);
1368
1369         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1370             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1371                 chv_set_memory_pm5(dev_priv, true);
1372
1373         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1374             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1375                 chv_set_memory_dvfs(dev_priv, true);
1376
1377         dev_priv->wm.vlv = wm;
1378 }
1379
1380 #define single_plane_enabled(mask) is_power_of_2(mask)
1381
1382 static void g4x_update_wm(struct intel_crtc *crtc)
1383 {
1384         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1385         static const int sr_latency_ns = 12000;
1386         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1387         int plane_sr, cursor_sr;
1388         unsigned int enabled = 0;
1389         bool cxsr_enabled;
1390
1391         if (g4x_compute_wm0(dev_priv, PIPE_A,
1392                             &g4x_wm_info, pessimal_latency_ns,
1393                             &g4x_cursor_wm_info, pessimal_latency_ns,
1394                             &planea_wm, &cursora_wm))
1395                 enabled |= 1 << PIPE_A;
1396
1397         if (g4x_compute_wm0(dev_priv, PIPE_B,
1398                             &g4x_wm_info, pessimal_latency_ns,
1399                             &g4x_cursor_wm_info, pessimal_latency_ns,
1400                             &planeb_wm, &cursorb_wm))
1401                 enabled |= 1 << PIPE_B;
1402
1403         if (single_plane_enabled(enabled) &&
1404             g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
1405                              sr_latency_ns,
1406                              &g4x_wm_info,
1407                              &g4x_cursor_wm_info,
1408                              &plane_sr, &cursor_sr)) {
1409                 cxsr_enabled = true;
1410         } else {
1411                 cxsr_enabled = false;
1412                 intel_set_memory_cxsr(dev_priv, false);
1413                 plane_sr = cursor_sr = 0;
1414         }
1415
1416         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1417                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1418                       planea_wm, cursora_wm,
1419                       planeb_wm, cursorb_wm,
1420                       plane_sr, cursor_sr);
1421
1422         I915_WRITE(DSPFW1,
1423                    FW_WM(plane_sr, SR) |
1424                    FW_WM(cursorb_wm, CURSORB) |
1425                    FW_WM(planeb_wm, PLANEB) |
1426                    FW_WM(planea_wm, PLANEA));
1427         I915_WRITE(DSPFW2,
1428                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1429                    FW_WM(cursora_wm, CURSORA));
1430         /* HPLL off in SR has some issues on G4x... disable it */
1431         I915_WRITE(DSPFW3,
1432                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1433                    FW_WM(cursor_sr, CURSOR_SR));
1434
1435         if (cxsr_enabled)
1436                 intel_set_memory_cxsr(dev_priv, true);
1437 }
1438
1439 static void i965_update_wm(struct intel_crtc *unused_crtc)
1440 {
1441         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1442         struct intel_crtc *crtc;
1443         int srwm = 1;
1444         int cursor_sr = 16;
1445         bool cxsr_enabled;
1446
1447         /* Calc sr entries for one plane configs */
1448         crtc = single_enabled_crtc(dev_priv);
1449         if (crtc) {
1450                 /* self-refresh has much higher latency */
1451                 static const int sr_latency_ns = 12000;
1452                 const struct drm_display_mode *adjusted_mode =
1453                         &crtc->config->base.adjusted_mode;
1454                 const struct drm_framebuffer *fb =
1455                         crtc->base.primary->state->fb;
1456                 int clock = adjusted_mode->crtc_clock;
1457                 int htotal = adjusted_mode->crtc_htotal;
1458                 int hdisplay = crtc->config->pipe_src_w;
1459                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1460                 unsigned long line_time_us;
1461                 int entries;
1462
1463                 line_time_us = max(htotal * 1000 / clock, 1);
1464
1465                 /* Use ns/us then divide to preserve precision */
1466                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1467                         cpp * hdisplay;
1468                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1469                 srwm = I965_FIFO_SIZE - entries;
1470                 if (srwm < 0)
1471                         srwm = 1;
1472                 srwm &= 0x1ff;
1473                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1474                               entries, srwm);
1475
1476                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1477                         cpp * crtc->base.cursor->state->crtc_w;
1478                 entries = DIV_ROUND_UP(entries,
1479                                           i965_cursor_wm_info.cacheline_size);
1480                 cursor_sr = i965_cursor_wm_info.fifo_size -
1481                         (entries + i965_cursor_wm_info.guard_size);
1482
1483                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1484                         cursor_sr = i965_cursor_wm_info.max_wm;
1485
1486                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1487                               "cursor %d\n", srwm, cursor_sr);
1488
1489                 cxsr_enabled = true;
1490         } else {
1491                 cxsr_enabled = false;
1492                 /* Turn off self refresh if both pipes are enabled */
1493                 intel_set_memory_cxsr(dev_priv, false);
1494         }
1495
1496         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1497                       srwm);
1498
1499         /* 965 has limitations... */
1500         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1501                    FW_WM(8, CURSORB) |
1502                    FW_WM(8, PLANEB) |
1503                    FW_WM(8, PLANEA));
1504         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1505                    FW_WM(8, PLANEC_OLD));
1506         /* update cursor SR watermark */
1507         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1508
1509         if (cxsr_enabled)
1510                 intel_set_memory_cxsr(dev_priv, true);
1511 }
1512
1513 #undef FW_WM
1514
1515 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
1516 {
1517         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1518         const struct intel_watermark_params *wm_info;
1519         uint32_t fwater_lo;
1520         uint32_t fwater_hi;
1521         int cwm, srwm = 1;
1522         int fifo_size;
1523         int planea_wm, planeb_wm;
1524         struct intel_crtc *crtc, *enabled = NULL;
1525
1526         if (IS_I945GM(dev_priv))
1527                 wm_info = &i945_wm_info;
1528         else if (!IS_GEN2(dev_priv))
1529                 wm_info = &i915_wm_info;
1530         else
1531                 wm_info = &i830_a_wm_info;
1532
1533         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
1534         crtc = intel_get_crtc_for_plane(dev_priv, 0);
1535         if (intel_crtc_active(crtc)) {
1536                 const struct drm_display_mode *adjusted_mode =
1537                         &crtc->config->base.adjusted_mode;
1538                 const struct drm_framebuffer *fb =
1539                         crtc->base.primary->state->fb;
1540                 int cpp;
1541
1542                 if (IS_GEN2(dev_priv))
1543                         cpp = 4;
1544                 else
1545                         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1546
1547                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1548                                                wm_info, fifo_size, cpp,
1549                                                pessimal_latency_ns);
1550                 enabled = crtc;
1551         } else {
1552                 planea_wm = fifo_size - wm_info->guard_size;
1553                 if (planea_wm > (long)wm_info->max_wm)
1554                         planea_wm = wm_info->max_wm;
1555         }
1556
1557         if (IS_GEN2(dev_priv))
1558                 wm_info = &i830_bc_wm_info;
1559
1560         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
1561         crtc = intel_get_crtc_for_plane(dev_priv, 1);
1562         if (intel_crtc_active(crtc)) {
1563                 const struct drm_display_mode *adjusted_mode =
1564                         &crtc->config->base.adjusted_mode;
1565                 const struct drm_framebuffer *fb =
1566                         crtc->base.primary->state->fb;
1567                 int cpp;
1568
1569                 if (IS_GEN2(dev_priv))
1570                         cpp = 4;
1571                 else
1572                         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1573
1574                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1575                                                wm_info, fifo_size, cpp,
1576                                                pessimal_latency_ns);
1577                 if (enabled == NULL)
1578                         enabled = crtc;
1579                 else
1580                         enabled = NULL;
1581         } else {
1582                 planeb_wm = fifo_size - wm_info->guard_size;
1583                 if (planeb_wm > (long)wm_info->max_wm)
1584                         planeb_wm = wm_info->max_wm;
1585         }
1586
1587         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1588
1589         if (IS_I915GM(dev_priv) && enabled) {
1590                 struct drm_i915_gem_object *obj;
1591
1592                 obj = intel_fb_obj(enabled->base.primary->state->fb);
1593
1594                 /* self-refresh seems busted with untiled */
1595                 if (!i915_gem_object_is_tiled(obj))
1596                         enabled = NULL;
1597         }
1598
1599         /*
1600          * Overlay gets an aggressive default since video jitter is bad.
1601          */
1602         cwm = 2;
1603
1604         /* Play safe and disable self-refresh before adjusting watermarks. */
1605         intel_set_memory_cxsr(dev_priv, false);
1606
1607         /* Calc sr entries for one plane configs */
1608         if (HAS_FW_BLC(dev_priv) && enabled) {
1609                 /* self-refresh has much higher latency */
1610                 static const int sr_latency_ns = 6000;
1611                 const struct drm_display_mode *adjusted_mode =
1612                         &enabled->config->base.adjusted_mode;
1613                 const struct drm_framebuffer *fb =
1614                         enabled->base.primary->state->fb;
1615                 int clock = adjusted_mode->crtc_clock;
1616                 int htotal = adjusted_mode->crtc_htotal;
1617                 int hdisplay = enabled->config->pipe_src_w;
1618                 int cpp;
1619                 unsigned long line_time_us;
1620                 int entries;
1621
1622                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
1623                         cpp = 4;
1624                 else
1625                         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1626
1627                 line_time_us = max(htotal * 1000 / clock, 1);
1628
1629                 /* Use ns/us then divide to preserve precision */
1630                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1631                         cpp * hdisplay;
1632                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1633                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1634                 srwm = wm_info->fifo_size - entries;
1635                 if (srwm < 0)
1636                         srwm = 1;
1637
1638                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1639                         I915_WRITE(FW_BLC_SELF,
1640                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1641                 else
1642                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1643         }
1644
1645         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1646                       planea_wm, planeb_wm, cwm, srwm);
1647
1648         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1649         fwater_hi = (cwm & 0x1f);
1650
1651         /* Set request length to 8 cachelines per fetch */
1652         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1653         fwater_hi = fwater_hi | (1 << 8);
1654
1655         I915_WRITE(FW_BLC, fwater_lo);
1656         I915_WRITE(FW_BLC2, fwater_hi);
1657
1658         if (enabled)
1659                 intel_set_memory_cxsr(dev_priv, true);
1660 }
1661
1662 static void i845_update_wm(struct intel_crtc *unused_crtc)
1663 {
1664         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
1665         struct intel_crtc *crtc;
1666         const struct drm_display_mode *adjusted_mode;
1667         uint32_t fwater_lo;
1668         int planea_wm;
1669
1670         crtc = single_enabled_crtc(dev_priv);
1671         if (crtc == NULL)
1672                 return;
1673
1674         adjusted_mode = &crtc->config->base.adjusted_mode;
1675         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1676                                        &i845_wm_info,
1677                                        dev_priv->display.get_fifo_size(dev_priv, 0),
1678                                        4, pessimal_latency_ns);
1679         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1680         fwater_lo |= (3<<8) | planea_wm;
1681
1682         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1683
1684         I915_WRITE(FW_BLC, fwater_lo);
1685 }
1686
1687 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1688 {
1689         uint32_t pixel_rate;
1690
1691         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1692
1693         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1694          * adjust the pixel_rate here. */
1695
1696         if (pipe_config->pch_pfit.enabled) {
1697                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1698                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1699
1700                 pipe_w = pipe_config->pipe_src_w;
1701                 pipe_h = pipe_config->pipe_src_h;
1702
1703                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1704                 pfit_h = pfit_size & 0xFFFF;
1705                 if (pipe_w < pfit_w)
1706                         pipe_w = pfit_w;
1707                 if (pipe_h < pfit_h)
1708                         pipe_h = pfit_h;
1709
1710                 if (WARN_ON(!pfit_w || !pfit_h))
1711                         return pixel_rate;
1712
1713                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1714                                      pfit_w * pfit_h);
1715         }
1716
1717         return pixel_rate;
1718 }
1719
1720 /* latency must be in 0.1us units. */
1721 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1722 {
1723         uint64_t ret;
1724
1725         if (WARN(latency == 0, "Latency value missing\n"))
1726                 return UINT_MAX;
1727
1728         ret = (uint64_t) pixel_rate * cpp * latency;
1729         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1730
1731         return ret;
1732 }
1733
1734 /* latency must be in 0.1us units. */
1735 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1736                                uint32_t horiz_pixels, uint8_t cpp,
1737                                uint32_t latency)
1738 {
1739         uint32_t ret;
1740
1741         if (WARN(latency == 0, "Latency value missing\n"))
1742                 return UINT_MAX;
1743         if (WARN_ON(!pipe_htotal))
1744                 return UINT_MAX;
1745
1746         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1747         ret = (ret + 1) * horiz_pixels * cpp;
1748         ret = DIV_ROUND_UP(ret, 64) + 2;
1749         return ret;
1750 }
1751
1752 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1753                            uint8_t cpp)
1754 {
1755         /*
1756          * Neither of these should be possible since this function shouldn't be
1757          * called if the CRTC is off or the plane is invisible.  But let's be
1758          * extra paranoid to avoid a potential divide-by-zero if we screw up
1759          * elsewhere in the driver.
1760          */
1761         if (WARN_ON(!cpp))
1762                 return 0;
1763         if (WARN_ON(!horiz_pixels))
1764                 return 0;
1765
1766         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1767 }
1768
1769 struct ilk_wm_maximums {
1770         uint16_t pri;
1771         uint16_t spr;
1772         uint16_t cur;
1773         uint16_t fbc;
1774 };
1775
1776 /*
1777  * For both WM_PIPE and WM_LP.
1778  * mem_value must be in 0.1us units.
1779  */
1780 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1781                                    const struct intel_plane_state *pstate,
1782                                    uint32_t mem_value,
1783                                    bool is_lp)
1784 {
1785         int cpp = pstate->base.fb ?
1786                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1787         uint32_t method1, method2;
1788
1789         if (!cstate->base.active || !pstate->base.visible)
1790                 return 0;
1791
1792         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1793
1794         if (!is_lp)
1795                 return method1;
1796
1797         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1798                                  cstate->base.adjusted_mode.crtc_htotal,
1799                                  drm_rect_width(&pstate->base.dst),
1800                                  cpp, mem_value);
1801
1802         return min(method1, method2);
1803 }
1804
1805 /*
1806  * For both WM_PIPE and WM_LP.
1807  * mem_value must be in 0.1us units.
1808  */
1809 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1810                                    const struct intel_plane_state *pstate,
1811                                    uint32_t mem_value)
1812 {
1813         int cpp = pstate->base.fb ?
1814                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1815         uint32_t method1, method2;
1816
1817         if (!cstate->base.active || !pstate->base.visible)
1818                 return 0;
1819
1820         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1821         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1822                                  cstate->base.adjusted_mode.crtc_htotal,
1823                                  drm_rect_width(&pstate->base.dst),
1824                                  cpp, mem_value);
1825         return min(method1, method2);
1826 }
1827
1828 /*
1829  * For both WM_PIPE and WM_LP.
1830  * mem_value must be in 0.1us units.
1831  */
1832 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1833                                    const struct intel_plane_state *pstate,
1834                                    uint32_t mem_value)
1835 {
1836         /*
1837          * We treat the cursor plane as always-on for the purposes of watermark
1838          * calculation.  Until we have two-stage watermark programming merged,
1839          * this is necessary to avoid flickering.
1840          */
1841         int cpp = 4;
1842         int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1843
1844         if (!cstate->base.active)
1845                 return 0;
1846
1847         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1848                               cstate->base.adjusted_mode.crtc_htotal,
1849                               width, cpp, mem_value);
1850 }
1851
1852 /* Only for WM_LP. */
1853 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1854                                    const struct intel_plane_state *pstate,
1855                                    uint32_t pri_val)
1856 {
1857         int cpp = pstate->base.fb ?
1858                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1859
1860         if (!cstate->base.active || !pstate->base.visible)
1861                 return 0;
1862
1863         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1864 }
1865
1866 static unsigned int
1867 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
1868 {
1869         if (INTEL_GEN(dev_priv) >= 8)
1870                 return 3072;
1871         else if (INTEL_GEN(dev_priv) >= 7)
1872                 return 768;
1873         else
1874                 return 512;
1875 }
1876
1877 static unsigned int
1878 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
1879                      int level, bool is_sprite)
1880 {
1881         if (INTEL_GEN(dev_priv) >= 8)
1882                 /* BDW primary/sprite plane watermarks */
1883                 return level == 0 ? 255 : 2047;
1884         else if (INTEL_GEN(dev_priv) >= 7)
1885                 /* IVB/HSW primary/sprite plane watermarks */
1886                 return level == 0 ? 127 : 1023;
1887         else if (!is_sprite)
1888                 /* ILK/SNB primary plane watermarks */
1889                 return level == 0 ? 127 : 511;
1890         else
1891                 /* ILK/SNB sprite plane watermarks */
1892                 return level == 0 ? 63 : 255;
1893 }
1894
1895 static unsigned int
1896 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
1897 {
1898         if (INTEL_GEN(dev_priv) >= 7)
1899                 return level == 0 ? 63 : 255;
1900         else
1901                 return level == 0 ? 31 : 63;
1902 }
1903
1904 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
1905 {
1906         if (INTEL_GEN(dev_priv) >= 8)
1907                 return 31;
1908         else
1909                 return 15;
1910 }
1911
1912 /* Calculate the maximum primary/sprite plane watermark */
1913 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1914                                      int level,
1915                                      const struct intel_wm_config *config,
1916                                      enum intel_ddb_partitioning ddb_partitioning,
1917                                      bool is_sprite)
1918 {
1919         struct drm_i915_private *dev_priv = to_i915(dev);
1920         unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
1921
1922         /* if sprites aren't enabled, sprites get nothing */
1923         if (is_sprite && !config->sprites_enabled)
1924                 return 0;
1925
1926         /* HSW allows LP1+ watermarks even with multiple pipes */
1927         if (level == 0 || config->num_pipes_active > 1) {
1928                 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
1929
1930                 /*
1931                  * For some reason the non self refresh
1932                  * FIFO size is only half of the self
1933                  * refresh FIFO size on ILK/SNB.
1934                  */
1935                 if (INTEL_GEN(dev_priv) <= 6)
1936                         fifo_size /= 2;
1937         }
1938
1939         if (config->sprites_enabled) {
1940                 /* level 0 is always calculated with 1:1 split */
1941                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1942                         if (is_sprite)
1943                                 fifo_size *= 5;
1944                         fifo_size /= 6;
1945                 } else {
1946                         fifo_size /= 2;
1947                 }
1948         }
1949
1950         /* clamp to max that the registers can hold */
1951         return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
1952 }
1953
1954 /* Calculate the maximum cursor plane watermark */
1955 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1956                                       int level,
1957                                       const struct intel_wm_config *config)
1958 {
1959         /* HSW LP1+ watermarks w/ multiple pipes */
1960         if (level > 0 && config->num_pipes_active > 1)
1961                 return 64;
1962
1963         /* otherwise just report max that registers can hold */
1964         return ilk_cursor_wm_reg_max(to_i915(dev), level);
1965 }
1966
1967 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1968                                     int level,
1969                                     const struct intel_wm_config *config,
1970                                     enum intel_ddb_partitioning ddb_partitioning,
1971                                     struct ilk_wm_maximums *max)
1972 {
1973         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1974         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1975         max->cur = ilk_cursor_wm_max(dev, level, config);
1976         max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
1977 }
1978
1979 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
1980                                         int level,
1981                                         struct ilk_wm_maximums *max)
1982 {
1983         max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
1984         max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
1985         max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
1986         max->fbc = ilk_fbc_wm_reg_max(dev_priv);
1987 }
1988
1989 static bool ilk_validate_wm_level(int level,
1990                                   const struct ilk_wm_maximums *max,
1991                                   struct intel_wm_level *result)
1992 {
1993         bool ret;
1994
1995         /* already determined to be invalid? */
1996         if (!result->enable)
1997                 return false;
1998
1999         result->enable = result->pri_val <= max->pri &&
2000                          result->spr_val <= max->spr &&
2001                          result->cur_val <= max->cur;
2002
2003         ret = result->enable;
2004
2005         /*
2006          * HACK until we can pre-compute everything,
2007          * and thus fail gracefully if LP0 watermarks
2008          * are exceeded...
2009          */
2010         if (level == 0 && !result->enable) {
2011                 if (result->pri_val > max->pri)
2012                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2013                                       level, result->pri_val, max->pri);
2014                 if (result->spr_val > max->spr)
2015                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2016                                       level, result->spr_val, max->spr);
2017                 if (result->cur_val > max->cur)
2018                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2019                                       level, result->cur_val, max->cur);
2020
2021                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2022                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2023                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2024                 result->enable = true;
2025         }
2026
2027         return ret;
2028 }
2029
2030 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2031                                  const struct intel_crtc *intel_crtc,
2032                                  int level,
2033                                  struct intel_crtc_state *cstate,
2034                                  struct intel_plane_state *pristate,
2035                                  struct intel_plane_state *sprstate,
2036                                  struct intel_plane_state *curstate,
2037                                  struct intel_wm_level *result)
2038 {
2039         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2040         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2041         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2042
2043         /* WM1+ latency values stored in 0.5us units */
2044         if (level > 0) {
2045                 pri_latency *= 5;
2046                 spr_latency *= 5;
2047                 cur_latency *= 5;
2048         }
2049
2050         if (pristate) {
2051                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2052                                                      pri_latency, level);
2053                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2054         }
2055
2056         if (sprstate)
2057                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2058
2059         if (curstate)
2060                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2061
2062         result->enable = true;
2063 }
2064
2065 static uint32_t
2066 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2067 {
2068         const struct intel_atomic_state *intel_state =
2069                 to_intel_atomic_state(cstate->base.state);
2070         const struct drm_display_mode *adjusted_mode =
2071                 &cstate->base.adjusted_mode;
2072         u32 linetime, ips_linetime;
2073
2074         if (!cstate->base.active)
2075                 return 0;
2076         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2077                 return 0;
2078         if (WARN_ON(intel_state->cdclk == 0))
2079                 return 0;
2080
2081         /* The WM are computed with base on how long it takes to fill a single
2082          * row at the given clock rate, multiplied by 8.
2083          * */
2084         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2085                                      adjusted_mode->crtc_clock);
2086         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2087                                          intel_state->cdclk);
2088
2089         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2090                PIPE_WM_LINETIME_TIME(linetime);
2091 }
2092
2093 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2094                                   uint16_t wm[8])
2095 {
2096         if (IS_GEN9(dev_priv)) {
2097                 uint32_t val;
2098                 int ret, i;
2099                 int level, max_level = ilk_wm_max_level(dev_priv);
2100
2101                 /* read the first set of memory latencies[0:3] */
2102                 val = 0; /* data0 to be programmed to 0 for first set */
2103                 mutex_lock(&dev_priv->rps.hw_lock);
2104                 ret = sandybridge_pcode_read(dev_priv,
2105                                              GEN9_PCODE_READ_MEM_LATENCY,
2106                                              &val);
2107                 mutex_unlock(&dev_priv->rps.hw_lock);
2108
2109                 if (ret) {
2110                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2111                         return;
2112                 }
2113
2114                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2115                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2116                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2117                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2118                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2119                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2120                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2121
2122                 /* read the second set of memory latencies[4:7] */
2123                 val = 1; /* data0 to be programmed to 1 for second set */
2124                 mutex_lock(&dev_priv->rps.hw_lock);
2125                 ret = sandybridge_pcode_read(dev_priv,
2126                                              GEN9_PCODE_READ_MEM_LATENCY,
2127                                              &val);
2128                 mutex_unlock(&dev_priv->rps.hw_lock);
2129                 if (ret) {
2130                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2131                         return;
2132                 }
2133
2134                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2135                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2136                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2137                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2138                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2139                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2140                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2141
2142                 /*
2143                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2144                  * need to be disabled. We make sure to sanitize the values out
2145                  * of the punit to satisfy this requirement.
2146                  */
2147                 for (level = 1; level <= max_level; level++) {
2148                         if (wm[level] == 0) {
2149                                 for (i = level + 1; i <= max_level; i++)
2150                                         wm[i] = 0;
2151                                 break;
2152                         }
2153                 }
2154
2155                 /*
2156                  * WaWmMemoryReadLatency:skl
2157                  *
2158                  * punit doesn't take into account the read latency so we need
2159                  * to add 2us to the various latency levels we retrieve from the
2160                  * punit when level 0 response data us 0us.
2161                  */
2162                 if (wm[0] == 0) {
2163                         wm[0] += 2;
2164                         for (level = 1; level <= max_level; level++) {
2165                                 if (wm[level] == 0)
2166                                         break;
2167                                 wm[level] += 2;
2168                         }
2169                 }
2170
2171         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2172                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2173
2174                 wm[0] = (sskpd >> 56) & 0xFF;
2175                 if (wm[0] == 0)
2176                         wm[0] = sskpd & 0xF;
2177                 wm[1] = (sskpd >> 4) & 0xFF;
2178                 wm[2] = (sskpd >> 12) & 0xFF;
2179                 wm[3] = (sskpd >> 20) & 0x1FF;
2180                 wm[4] = (sskpd >> 32) & 0x1FF;
2181         } else if (INTEL_GEN(dev_priv) >= 6) {
2182                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2183
2184                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2185                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2186                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2187                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2188         } else if (INTEL_GEN(dev_priv) >= 5) {
2189                 uint32_t mltr = I915_READ(MLTR_ILK);
2190
2191                 /* ILK primary LP0 latency is 700 ns */
2192                 wm[0] = 7;
2193                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2194                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2195         }
2196 }
2197
2198 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2199                                        uint16_t wm[5])
2200 {
2201         /* ILK sprite LP0 latency is 1300 ns */
2202         if (IS_GEN5(dev_priv))
2203                 wm[0] = 13;
2204 }
2205
2206 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2207                                        uint16_t wm[5])
2208 {
2209         /* ILK cursor LP0 latency is 1300 ns */
2210         if (IS_GEN5(dev_priv))
2211                 wm[0] = 13;
2212
2213         /* WaDoubleCursorLP3Latency:ivb */
2214         if (IS_IVYBRIDGE(dev_priv))
2215                 wm[3] *= 2;
2216 }
2217
2218 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2219 {
2220         /* how many WM levels are we expecting */
2221         if (INTEL_GEN(dev_priv) >= 9)
2222                 return 7;
2223         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2224                 return 4;
2225         else if (INTEL_GEN(dev_priv) >= 6)
2226                 return 3;
2227         else
2228                 return 2;
2229 }
2230
2231 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2232                                    const char *name,
2233                                    const uint16_t wm[8])
2234 {
2235         int level, max_level = ilk_wm_max_level(dev_priv);
2236
2237         for (level = 0; level <= max_level; level++) {
2238                 unsigned int latency = wm[level];
2239
2240                 if (latency == 0) {
2241                         DRM_ERROR("%s WM%d latency not provided\n",
2242                                   name, level);
2243                         continue;
2244                 }
2245
2246                 /*
2247                  * - latencies are in us on gen9.
2248                  * - before then, WM1+ latency values are in 0.5us units
2249                  */
2250                 if (IS_GEN9(dev_priv))
2251                         latency *= 10;
2252                 else if (level > 0)
2253                         latency *= 5;
2254
2255                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2256                               name, level, wm[level],
2257                               latency / 10, latency % 10);
2258         }
2259 }
2260
2261 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2262                                     uint16_t wm[5], uint16_t min)
2263 {
2264         int level, max_level = ilk_wm_max_level(dev_priv);
2265
2266         if (wm[0] >= min)
2267                 return false;
2268
2269         wm[0] = max(wm[0], min);
2270         for (level = 1; level <= max_level; level++)
2271                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2272
2273         return true;
2274 }
2275
2276 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2277 {
2278         bool changed;
2279
2280         /*
2281          * The BIOS provided WM memory latency values are often
2282          * inadequate for high resolution displays. Adjust them.
2283          */
2284         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2285                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2286                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2287
2288         if (!changed)
2289                 return;
2290
2291         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2292         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2293         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2294         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2295 }
2296
2297 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
2298 {
2299         intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
2300
2301         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2302                sizeof(dev_priv->wm.pri_latency));
2303         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2304                sizeof(dev_priv->wm.pri_latency));
2305
2306         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2307         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
2308
2309         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2310         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2311         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2312
2313         if (IS_GEN6(dev_priv))
2314                 snb_wm_latency_quirk(dev_priv);
2315 }
2316
2317 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
2318 {
2319         intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
2320         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2321 }
2322
2323 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2324                                  struct intel_pipe_wm *pipe_wm)
2325 {
2326         /* LP0 watermark maximums depend on this pipe alone */
2327         const struct intel_wm_config config = {
2328                 .num_pipes_active = 1,
2329                 .sprites_enabled = pipe_wm->sprites_enabled,
2330                 .sprites_scaled = pipe_wm->sprites_scaled,
2331         };
2332         struct ilk_wm_maximums max;
2333
2334         /* LP0 watermarks always use 1/2 DDB partitioning */
2335         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2336
2337         /* At least LP0 must be valid */
2338         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2339                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2340                 return false;
2341         }
2342
2343         return true;
2344 }
2345
2346 /* Compute new watermarks for the pipe */
2347 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2348 {
2349         struct drm_atomic_state *state = cstate->base.state;
2350         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2351         struct intel_pipe_wm *pipe_wm;
2352         struct drm_device *dev = state->dev;
2353         const struct drm_i915_private *dev_priv = to_i915(dev);
2354         struct intel_plane *intel_plane;
2355         struct intel_plane_state *pristate = NULL;
2356         struct intel_plane_state *sprstate = NULL;
2357         struct intel_plane_state *curstate = NULL;
2358         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
2359         struct ilk_wm_maximums max;
2360
2361         pipe_wm = &cstate->wm.ilk.optimal;
2362
2363         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2364                 struct intel_plane_state *ps;
2365
2366                 ps = intel_atomic_get_existing_plane_state(state,
2367                                                            intel_plane);
2368                 if (!ps)
2369                         continue;
2370
2371                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2372                         pristate = ps;
2373                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2374                         sprstate = ps;
2375                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2376                         curstate = ps;
2377         }
2378
2379         pipe_wm->pipe_enabled = cstate->base.active;
2380         if (sprstate) {
2381                 pipe_wm->sprites_enabled = sprstate->base.visible;
2382                 pipe_wm->sprites_scaled = sprstate->base.visible &&
2383                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2384                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2385         }
2386
2387         usable_level = max_level;
2388
2389         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2390         if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
2391                 usable_level = 1;
2392
2393         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2394         if (pipe_wm->sprites_scaled)
2395                 usable_level = 0;
2396
2397         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2398                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2399
2400         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2401         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2402
2403         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2404                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2405
2406         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2407                 return -EINVAL;
2408
2409         ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
2410
2411         for (level = 1; level <= max_level; level++) {
2412                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2413
2414                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2415                                      pristate, sprstate, curstate, wm);
2416
2417                 /*
2418                  * Disable any watermark level that exceeds the
2419                  * register maximums since such watermarks are
2420                  * always invalid.
2421                  */
2422                 if (level > usable_level)
2423                         continue;
2424
2425                 if (ilk_validate_wm_level(level, &max, wm))
2426                         pipe_wm->wm[level] = *wm;
2427                 else
2428                         usable_level = level;
2429         }
2430
2431         return 0;
2432 }
2433
2434 /*
2435  * Build a set of 'intermediate' watermark values that satisfy both the old
2436  * state and the new state.  These can be programmed to the hardware
2437  * immediately.
2438  */
2439 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2440                                        struct intel_crtc *intel_crtc,
2441                                        struct intel_crtc_state *newstate)
2442 {
2443         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2444         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2445         int level, max_level = ilk_wm_max_level(to_i915(dev));
2446
2447         /*
2448          * Start with the final, target watermarks, then combine with the
2449          * currently active watermarks to get values that are safe both before
2450          * and after the vblank.
2451          */
2452         *a = newstate->wm.ilk.optimal;
2453         a->pipe_enabled |= b->pipe_enabled;
2454         a->sprites_enabled |= b->sprites_enabled;
2455         a->sprites_scaled |= b->sprites_scaled;
2456
2457         for (level = 0; level <= max_level; level++) {
2458                 struct intel_wm_level *a_wm = &a->wm[level];
2459                 const struct intel_wm_level *b_wm = &b->wm[level];
2460
2461                 a_wm->enable &= b_wm->enable;
2462                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2463                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2464                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2465                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2466         }
2467
2468         /*
2469          * We need to make sure that these merged watermark values are
2470          * actually a valid configuration themselves.  If they're not,
2471          * there's no safe way to transition from the old state to
2472          * the new state, so we need to fail the atomic transaction.
2473          */
2474         if (!ilk_validate_pipe_wm(dev, a))
2475                 return -EINVAL;
2476
2477         /*
2478          * If our intermediate WM are identical to the final WM, then we can
2479          * omit the post-vblank programming; only update if it's different.
2480          */
2481         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2482                 newstate->wm.need_postvbl_update = false;
2483
2484         return 0;
2485 }
2486
2487 /*
2488  * Merge the watermarks from all active pipes for a specific level.
2489  */
2490 static void ilk_merge_wm_level(struct drm_device *dev,
2491                                int level,
2492                                struct intel_wm_level *ret_wm)
2493 {
2494         const struct intel_crtc *intel_crtc;
2495
2496         ret_wm->enable = true;
2497
2498         for_each_intel_crtc(dev, intel_crtc) {
2499                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2500                 const struct intel_wm_level *wm = &active->wm[level];
2501
2502                 if (!active->pipe_enabled)
2503                         continue;
2504
2505                 /*
2506                  * The watermark values may have been used in the past,
2507                  * so we must maintain them in the registers for some
2508                  * time even if the level is now disabled.
2509                  */
2510                 if (!wm->enable)
2511                         ret_wm->enable = false;
2512
2513                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2514                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2515                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2516                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2517         }
2518 }
2519
2520 /*
2521  * Merge all low power watermarks for all active pipes.
2522  */
2523 static void ilk_wm_merge(struct drm_device *dev,
2524                          const struct intel_wm_config *config,
2525                          const struct ilk_wm_maximums *max,
2526                          struct intel_pipe_wm *merged)
2527 {
2528         struct drm_i915_private *dev_priv = to_i915(dev);
2529         int level, max_level = ilk_wm_max_level(dev_priv);
2530         int last_enabled_level = max_level;
2531
2532         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2533         if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
2534             config->num_pipes_active > 1)
2535                 last_enabled_level = 0;
2536
2537         /* ILK: FBC WM must be disabled always */
2538         merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
2539
2540         /* merge each WM1+ level */
2541         for (level = 1; level <= max_level; level++) {
2542                 struct intel_wm_level *wm = &merged->wm[level];
2543
2544                 ilk_merge_wm_level(dev, level, wm);
2545
2546                 if (level > last_enabled_level)
2547                         wm->enable = false;
2548                 else if (!ilk_validate_wm_level(level, max, wm))
2549                         /* make sure all following levels get disabled */
2550                         last_enabled_level = level - 1;
2551
2552                 /*
2553                  * The spec says it is preferred to disable
2554                  * FBC WMs instead of disabling a WM level.
2555                  */
2556                 if (wm->fbc_val > max->fbc) {
2557                         if (wm->enable)
2558                                 merged->fbc_wm_enabled = false;
2559                         wm->fbc_val = 0;
2560                 }
2561         }
2562
2563         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2564         /*
2565          * FIXME this is racy. FBC might get enabled later.
2566          * What we should check here is whether FBC can be
2567          * enabled sometime later.
2568          */
2569         if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
2570             intel_fbc_is_active(dev_priv)) {
2571                 for (level = 2; level <= max_level; level++) {
2572                         struct intel_wm_level *wm = &merged->wm[level];
2573
2574                         wm->enable = false;
2575                 }
2576         }
2577 }
2578
2579 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2580 {
2581         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2582         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2583 }
2584
2585 /* The value we need to program into the WM_LPx latency field */
2586 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2587 {
2588         struct drm_i915_private *dev_priv = to_i915(dev);
2589
2590         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2591                 return 2 * level;
2592         else
2593                 return dev_priv->wm.pri_latency[level];
2594 }
2595
2596 static void ilk_compute_wm_results(struct drm_device *dev,
2597                                    const struct intel_pipe_wm *merged,
2598                                    enum intel_ddb_partitioning partitioning,
2599                                    struct ilk_wm_values *results)
2600 {
2601         struct drm_i915_private *dev_priv = to_i915(dev);
2602         struct intel_crtc *intel_crtc;
2603         int level, wm_lp;
2604
2605         results->enable_fbc_wm = merged->fbc_wm_enabled;
2606         results->partitioning = partitioning;
2607
2608         /* LP1+ register values */
2609         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2610                 const struct intel_wm_level *r;
2611
2612                 level = ilk_wm_lp_to_level(wm_lp, merged);
2613
2614                 r = &merged->wm[level];
2615
2616                 /*
2617                  * Maintain the watermark values even if the level is
2618                  * disabled. Doing otherwise could cause underruns.
2619                  */
2620                 results->wm_lp[wm_lp - 1] =
2621                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2622                         (r->pri_val << WM1_LP_SR_SHIFT) |
2623                         r->cur_val;
2624
2625                 if (r->enable)
2626                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2627
2628                 if (INTEL_GEN(dev_priv) >= 8)
2629                         results->wm_lp[wm_lp - 1] |=
2630                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2631                 else
2632                         results->wm_lp[wm_lp - 1] |=
2633                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2634
2635                 /*
2636                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2637                  * level is disabled. Doing otherwise could cause underruns.
2638                  */
2639                 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
2640                         WARN_ON(wm_lp != 1);
2641                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2642                 } else
2643                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2644         }
2645
2646         /* LP0 register values */
2647         for_each_intel_crtc(dev, intel_crtc) {
2648                 enum pipe pipe = intel_crtc->pipe;
2649                 const struct intel_wm_level *r =
2650                         &intel_crtc->wm.active.ilk.wm[0];
2651
2652                 if (WARN_ON(!r->enable))
2653                         continue;
2654
2655                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2656
2657                 results->wm_pipe[pipe] =
2658                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2659                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2660                         r->cur_val;
2661         }
2662 }
2663
2664 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2665  * case both are at the same level. Prefer r1 in case they're the same. */
2666 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2667                                                   struct intel_pipe_wm *r1,
2668                                                   struct intel_pipe_wm *r2)
2669 {
2670         int level, max_level = ilk_wm_max_level(to_i915(dev));
2671         int level1 = 0, level2 = 0;
2672
2673         for (level = 1; level <= max_level; level++) {
2674                 if (r1->wm[level].enable)
2675                         level1 = level;
2676                 if (r2->wm[level].enable)
2677                         level2 = level;
2678         }
2679
2680         if (level1 == level2) {
2681                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2682                         return r2;
2683                 else
2684                         return r1;
2685         } else if (level1 > level2) {
2686                 return r1;
2687         } else {
2688                 return r2;
2689         }
2690 }
2691
2692 /* dirty bits used to track which watermarks need changes */
2693 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2694 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2695 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2696 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2697 #define WM_DIRTY_FBC (1 << 24)
2698 #define WM_DIRTY_DDB (1 << 25)
2699
2700 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2701                                          const struct ilk_wm_values *old,
2702                                          const struct ilk_wm_values *new)
2703 {
2704         unsigned int dirty = 0;
2705         enum pipe pipe;
2706         int wm_lp;
2707
2708         for_each_pipe(dev_priv, pipe) {
2709                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2710                         dirty |= WM_DIRTY_LINETIME(pipe);
2711                         /* Must disable LP1+ watermarks too */
2712                         dirty |= WM_DIRTY_LP_ALL;
2713                 }
2714
2715                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2716                         dirty |= WM_DIRTY_PIPE(pipe);
2717                         /* Must disable LP1+ watermarks too */
2718                         dirty |= WM_DIRTY_LP_ALL;
2719                 }
2720         }
2721
2722         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2723                 dirty |= WM_DIRTY_FBC;
2724                 /* Must disable LP1+ watermarks too */
2725                 dirty |= WM_DIRTY_LP_ALL;
2726         }
2727
2728         if (old->partitioning != new->partitioning) {
2729                 dirty |= WM_DIRTY_DDB;
2730                 /* Must disable LP1+ watermarks too */
2731                 dirty |= WM_DIRTY_LP_ALL;
2732         }
2733
2734         /* LP1+ watermarks already deemed dirty, no need to continue */
2735         if (dirty & WM_DIRTY_LP_ALL)
2736                 return dirty;
2737
2738         /* Find the lowest numbered LP1+ watermark in need of an update... */
2739         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2740                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2741                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2742                         break;
2743         }
2744
2745         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2746         for (; wm_lp <= 3; wm_lp++)
2747                 dirty |= WM_DIRTY_LP(wm_lp);
2748
2749         return dirty;
2750 }
2751
2752 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2753                                unsigned int dirty)
2754 {
2755         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2756         bool changed = false;
2757
2758         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2759                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2760                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2761                 changed = true;
2762         }
2763         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2764                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2765                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2766                 changed = true;
2767         }
2768         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2769                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2770                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2771                 changed = true;
2772         }
2773
2774         /*
2775          * Don't touch WM1S_LP_EN here.
2776          * Doing so could cause underruns.
2777          */
2778
2779         return changed;
2780 }
2781
2782 /*
2783  * The spec says we shouldn't write when we don't need, because every write
2784  * causes WMs to be re-evaluated, expending some power.
2785  */
2786 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2787                                 struct ilk_wm_values *results)
2788 {
2789         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2790         unsigned int dirty;
2791         uint32_t val;
2792
2793         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2794         if (!dirty)
2795                 return;
2796
2797         _ilk_disable_lp_wm(dev_priv, dirty);
2798
2799         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2800                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2801         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2802                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2803         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2804                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2805
2806         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2807                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2808         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2809                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2810         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2811                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2812
2813         if (dirty & WM_DIRTY_DDB) {
2814                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2815                         val = I915_READ(WM_MISC);
2816                         if (results->partitioning == INTEL_DDB_PART_1_2)
2817                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2818                         else
2819                                 val |= WM_MISC_DATA_PARTITION_5_6;
2820                         I915_WRITE(WM_MISC, val);
2821                 } else {
2822                         val = I915_READ(DISP_ARB_CTL2);
2823                         if (results->partitioning == INTEL_DDB_PART_1_2)
2824                                 val &= ~DISP_DATA_PARTITION_5_6;
2825                         else
2826                                 val |= DISP_DATA_PARTITION_5_6;
2827                         I915_WRITE(DISP_ARB_CTL2, val);
2828                 }
2829         }
2830
2831         if (dirty & WM_DIRTY_FBC) {
2832                 val = I915_READ(DISP_ARB_CTL);
2833                 if (results->enable_fbc_wm)
2834                         val &= ~DISP_FBC_WM_DIS;
2835                 else
2836                         val |= DISP_FBC_WM_DIS;
2837                 I915_WRITE(DISP_ARB_CTL, val);
2838         }
2839
2840         if (dirty & WM_DIRTY_LP(1) &&
2841             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2842                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2843
2844         if (INTEL_GEN(dev_priv) >= 7) {
2845                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2846                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2847                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2848                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2849         }
2850
2851         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2852                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2853         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2854                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2855         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2856                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2857
2858         dev_priv->wm.hw = *results;
2859 }
2860
2861 bool ilk_disable_lp_wm(struct drm_device *dev)
2862 {
2863         struct drm_i915_private *dev_priv = to_i915(dev);
2864
2865         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2866 }
2867
2868 #define SKL_SAGV_BLOCK_TIME     30 /* µs */
2869
2870 /*
2871  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2872  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2873  * other universal planes are in indices 1..n.  Note that this may leave unused
2874  * indices between the top "sprite" plane and the cursor.
2875  */
2876 static int
2877 skl_wm_plane_id(const struct intel_plane *plane)
2878 {
2879         switch (plane->base.type) {
2880         case DRM_PLANE_TYPE_PRIMARY:
2881                 return 0;
2882         case DRM_PLANE_TYPE_CURSOR:
2883                 return PLANE_CURSOR;
2884         case DRM_PLANE_TYPE_OVERLAY:
2885                 return plane->plane + 1;
2886         default:
2887                 MISSING_CASE(plane->base.type);
2888                 return plane->plane;
2889         }
2890 }
2891
2892 /*
2893  * FIXME: We still don't have the proper code detect if we need to apply the WA,
2894  * so assume we'll always need it in order to avoid underruns.
2895  */
2896 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2897 {
2898         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2899
2900         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2901             IS_KABYLAKE(dev_priv))
2902                 return true;
2903
2904         return false;
2905 }
2906
2907 static bool
2908 intel_has_sagv(struct drm_i915_private *dev_priv)
2909 {
2910         if (IS_KABYLAKE(dev_priv))
2911                 return true;
2912
2913         if (IS_SKYLAKE(dev_priv) &&
2914             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2915                 return true;
2916
2917         return false;
2918 }
2919
2920 /*
2921  * SAGV dynamically adjusts the system agent voltage and clock frequencies
2922  * depending on power and performance requirements. The display engine access
2923  * to system memory is blocked during the adjustment time. Because of the
2924  * blocking time, having this enabled can cause full system hangs and/or pipe
2925  * underruns if we don't meet all of the following requirements:
2926  *
2927  *  - <= 1 pipe enabled
2928  *  - All planes can enable watermarks for latencies >= SAGV engine block time
2929  *  - We're not using an interlaced display configuration
2930  */
2931 int
2932 intel_enable_sagv(struct drm_i915_private *dev_priv)
2933 {
2934         int ret;
2935
2936         if (!intel_has_sagv(dev_priv))
2937                 return 0;
2938
2939         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
2940                 return 0;
2941
2942         DRM_DEBUG_KMS("Enabling the SAGV\n");
2943         mutex_lock(&dev_priv->rps.hw_lock);
2944
2945         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2946                                       GEN9_SAGV_ENABLE);
2947
2948         /* We don't need to wait for the SAGV when enabling */
2949         mutex_unlock(&dev_priv->rps.hw_lock);
2950
2951         /*
2952          * Some skl systems, pre-release machines in particular,
2953          * don't actually have an SAGV.
2954          */
2955         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
2956                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2957                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
2958                 return 0;
2959         } else if (ret < 0) {
2960                 DRM_ERROR("Failed to enable the SAGV\n");
2961                 return ret;
2962         }
2963
2964         dev_priv->sagv_status = I915_SAGV_ENABLED;
2965         return 0;
2966 }
2967
2968 static int
2969 intel_do_sagv_disable(struct drm_i915_private *dev_priv)
2970 {
2971         int ret;
2972         uint32_t temp = GEN9_SAGV_DISABLE;
2973
2974         ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2975                                      &temp);
2976         if (ret)
2977                 return ret;
2978         else
2979                 return temp & GEN9_SAGV_IS_DISABLED;
2980 }
2981
2982 int
2983 intel_disable_sagv(struct drm_i915_private *dev_priv)
2984 {
2985         int ret, result;
2986
2987         if (!intel_has_sagv(dev_priv))
2988                 return 0;
2989
2990         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
2991                 return 0;
2992
2993         DRM_DEBUG_KMS("Disabling the SAGV\n");
2994         mutex_lock(&dev_priv->rps.hw_lock);
2995
2996         /* bspec says to keep retrying for at least 1 ms */
2997         ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
2998         mutex_unlock(&dev_priv->rps.hw_lock);
2999
3000         if (ret == -ETIMEDOUT) {
3001                 DRM_ERROR("Request to disable SAGV timed out\n");
3002                 return -ETIMEDOUT;
3003         }
3004
3005         /*
3006          * Some skl systems, pre-release machines in particular,
3007          * don't actually have an SAGV.
3008          */
3009         if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
3010                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3011                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3012                 return 0;
3013         } else if (result < 0) {
3014                 DRM_ERROR("Failed to disable the SAGV\n");
3015                 return result;
3016         }
3017
3018         dev_priv->sagv_status = I915_SAGV_DISABLED;
3019         return 0;
3020 }
3021
3022 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3023 {
3024         struct drm_device *dev = state->dev;
3025         struct drm_i915_private *dev_priv = to_i915(dev);
3026         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3027         struct intel_crtc *crtc;
3028         struct intel_plane *plane;
3029         struct intel_crtc_state *cstate;
3030         struct skl_plane_wm *wm;
3031         enum pipe pipe;
3032         int level, latency;
3033
3034         if (!intel_has_sagv(dev_priv))
3035                 return false;
3036
3037         /*
3038          * SKL workaround: bspec recommends we disable the SAGV when we have
3039          * more then one pipe enabled
3040          *
3041          * If there are no active CRTCs, no additional checks need be performed
3042          */
3043         if (hweight32(intel_state->active_crtcs) == 0)
3044                 return true;
3045         else if (hweight32(intel_state->active_crtcs) > 1)
3046                 return false;
3047
3048         /* Since we're now guaranteed to only have one active CRTC... */
3049         pipe = ffs(intel_state->active_crtcs) - 1;
3050         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3051         cstate = to_intel_crtc_state(crtc->base.state);
3052
3053         if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3054                 return false;
3055
3056         for_each_intel_plane_on_crtc(dev, crtc, plane) {
3057                 wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
3058
3059                 /* Skip this plane if it's not enabled */
3060                 if (!wm->wm[0].plane_en)
3061                         continue;
3062
3063                 /* Find the highest enabled wm level for this plane */
3064                 for (level = ilk_wm_max_level(dev_priv);
3065                      !wm->wm[level].plane_en; --level)
3066                      { }
3067
3068                 latency = dev_priv->wm.skl_latency[level];
3069
3070                 if (skl_needs_memory_bw_wa(intel_state) &&
3071                     plane->base.state->fb->modifier[0] ==
3072                     I915_FORMAT_MOD_X_TILED)
3073                         latency += 15;
3074
3075                 /*
3076                  * If any of the planes on this pipe don't enable wm levels
3077                  * that incur memory latencies higher then 30µs we can't enable
3078                  * the SAGV
3079                  */
3080                 if (latency < SKL_SAGV_BLOCK_TIME)
3081                         return false;
3082         }
3083
3084         return true;
3085 }
3086
3087 static void
3088 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3089                                    const struct intel_crtc_state *cstate,
3090                                    struct skl_ddb_entry *alloc, /* out */
3091                                    int *num_active /* out */)
3092 {
3093         struct drm_atomic_state *state = cstate->base.state;
3094         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3095         struct drm_i915_private *dev_priv = to_i915(dev);
3096         struct drm_crtc *for_crtc = cstate->base.crtc;
3097         unsigned int pipe_size, ddb_size;
3098         int nth_active_pipe;
3099
3100         if (WARN_ON(!state) || !cstate->base.active) {
3101                 alloc->start = 0;
3102                 alloc->end = 0;
3103                 *num_active = hweight32(dev_priv->active_crtcs);
3104                 return;
3105         }
3106
3107         if (intel_state->active_pipe_changes)
3108                 *num_active = hweight32(intel_state->active_crtcs);
3109         else
3110                 *num_active = hweight32(dev_priv->active_crtcs);
3111
3112         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3113         WARN_ON(ddb_size == 0);
3114
3115         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3116
3117         /*
3118          * If the state doesn't change the active CRTC's, then there's
3119          * no need to recalculate; the existing pipe allocation limits
3120          * should remain unchanged.  Note that we're safe from racing
3121          * commits since any racing commit that changes the active CRTC
3122          * list would need to grab _all_ crtc locks, including the one
3123          * we currently hold.
3124          */
3125         if (!intel_state->active_pipe_changes) {
3126                 /*
3127                  * alloc may be cleared by clear_intel_crtc_state,
3128                  * copy from old state to be sure
3129                  */
3130                 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3131                 return;
3132         }
3133
3134         nth_active_pipe = hweight32(intel_state->active_crtcs &
3135                                     (drm_crtc_mask(for_crtc) - 1));
3136         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3137         alloc->start = nth_active_pipe * ddb_size / *num_active;
3138         alloc->end = alloc->start + pipe_size;
3139 }
3140
3141 static unsigned int skl_cursor_allocation(int num_active)
3142 {
3143         if (num_active == 1)
3144                 return 32;
3145
3146         return 8;
3147 }
3148
3149 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3150 {
3151         entry->start = reg & 0x3ff;
3152         entry->end = (reg >> 16) & 0x3ff;
3153         if (entry->end)
3154                 entry->end += 1;
3155 }
3156
3157 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3158                           struct skl_ddb_allocation *ddb /* out */)
3159 {
3160         enum pipe pipe;
3161         int plane;
3162         u32 val;
3163
3164         memset(ddb, 0, sizeof(*ddb));
3165
3166         for_each_pipe(dev_priv, pipe) {
3167                 enum intel_display_power_domain power_domain;
3168
3169                 power_domain = POWER_DOMAIN_PIPE(pipe);
3170                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3171                         continue;
3172
3173                 for_each_universal_plane(dev_priv, pipe, plane) {
3174                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3175                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3176                                                    val);
3177                 }
3178
3179                 val = I915_READ(CUR_BUF_CFG(pipe));
3180                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3181                                            val);
3182
3183                 intel_display_power_put(dev_priv, power_domain);
3184         }
3185 }
3186
3187 /*
3188  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3189  * The bspec defines downscale amount as:
3190  *
3191  * """
3192  * Horizontal down scale amount = maximum[1, Horizontal source size /
3193  *                                           Horizontal destination size]
3194  * Vertical down scale amount = maximum[1, Vertical source size /
3195  *                                         Vertical destination size]
3196  * Total down scale amount = Horizontal down scale amount *
3197  *                           Vertical down scale amount
3198  * """
3199  *
3200  * Return value is provided in 16.16 fixed point form to retain fractional part.
3201  * Caller should take care of dividing & rounding off the value.
3202  */
3203 static uint32_t
3204 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3205 {
3206         uint32_t downscale_h, downscale_w;
3207         uint32_t src_w, src_h, dst_w, dst_h;
3208
3209         if (WARN_ON(!pstate->base.visible))
3210                 return DRM_PLANE_HELPER_NO_SCALING;
3211
3212         /* n.b., src is 16.16 fixed point, dst is whole integer */
3213         src_w = drm_rect_width(&pstate->base.src);
3214         src_h = drm_rect_height(&pstate->base.src);
3215         dst_w = drm_rect_width(&pstate->base.dst);
3216         dst_h = drm_rect_height(&pstate->base.dst);
3217         if (drm_rotation_90_or_270(pstate->base.rotation))
3218                 swap(dst_w, dst_h);
3219
3220         downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3221         downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3222
3223         /* Provide result in 16.16 fixed point */
3224         return (uint64_t)downscale_w * downscale_h >> 16;
3225 }
3226
3227 static unsigned int
3228 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3229                              const struct drm_plane_state *pstate,
3230                              int y)
3231 {
3232         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3233         struct drm_framebuffer *fb = pstate->fb;
3234         uint32_t down_scale_amount, data_rate;
3235         uint32_t width = 0, height = 0;
3236         unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3237
3238         if (!intel_pstate->base.visible)
3239                 return 0;
3240         if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3241                 return 0;
3242         if (y && format != DRM_FORMAT_NV12)
3243                 return 0;
3244
3245         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3246         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3247
3248         if (drm_rotation_90_or_270(pstate->rotation))
3249                 swap(width, height);
3250
3251         /* for planar format */
3252         if (format == DRM_FORMAT_NV12) {
3253                 if (y)  /* y-plane data rate */
3254                         data_rate = width * height *
3255                                 drm_format_plane_cpp(format, 0);
3256                 else    /* uv-plane data rate */
3257                         data_rate = (width / 2) * (height / 2) *
3258                                 drm_format_plane_cpp(format, 1);
3259         } else {
3260                 /* for packed formats */
3261                 data_rate = width * height * drm_format_plane_cpp(format, 0);
3262         }
3263
3264         down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3265
3266         return (uint64_t)data_rate * down_scale_amount >> 16;
3267 }
3268
3269 /*
3270  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3271  * a 8192x4096@32bpp framebuffer:
3272  *   3 * 4096 * 8192  * 4 < 2^32
3273  */
3274 static unsigned int
3275 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3276                                  unsigned *plane_data_rate,
3277                                  unsigned *plane_y_data_rate)
3278 {
3279         struct drm_crtc_state *cstate = &intel_cstate->base;
3280         struct drm_atomic_state *state = cstate->state;
3281         struct drm_plane *plane;
3282         const struct intel_plane *intel_plane;
3283         const struct drm_plane_state *pstate;
3284         unsigned int rate, total_data_rate = 0;
3285         int id;
3286
3287         if (WARN_ON(!state))
3288                 return 0;
3289
3290         /* Calculate and cache data rate for each plane */
3291         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
3292                 id = skl_wm_plane_id(to_intel_plane(plane));
3293                 intel_plane = to_intel_plane(plane);
3294
3295                 /* packed/uv */
3296                 rate = skl_plane_relative_data_rate(intel_cstate,
3297                                                     pstate, 0);
3298                 plane_data_rate[id] = rate;
3299
3300                 total_data_rate += rate;
3301
3302                 /* y-plane */
3303                 rate = skl_plane_relative_data_rate(intel_cstate,
3304                                                     pstate, 1);
3305                 plane_y_data_rate[id] = rate;
3306
3307                 total_data_rate += rate;
3308         }
3309
3310         return total_data_rate;
3311 }
3312
3313 static uint16_t
3314 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3315                   const int y)
3316 {
3317         struct drm_framebuffer *fb = pstate->fb;
3318         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3319         uint32_t src_w, src_h;
3320         uint32_t min_scanlines = 8;
3321         uint8_t plane_bpp;
3322
3323         if (WARN_ON(!fb))
3324                 return 0;
3325
3326         /* For packed formats, no y-plane, return 0 */
3327         if (y && fb->pixel_format != DRM_FORMAT_NV12)
3328                 return 0;
3329
3330         /* For Non Y-tile return 8-blocks */
3331         if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3332             fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3333                 return 8;
3334
3335         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3336         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3337
3338         if (drm_rotation_90_or_270(pstate->rotation))
3339                 swap(src_w, src_h);
3340
3341         /* Halve UV plane width and height for NV12 */
3342         if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3343                 src_w /= 2;
3344                 src_h /= 2;
3345         }
3346
3347         if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3348                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3349         else
3350                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3351
3352         if (drm_rotation_90_or_270(pstate->rotation)) {
3353                 switch (plane_bpp) {
3354                 case 1:
3355                         min_scanlines = 32;
3356                         break;
3357                 case 2:
3358                         min_scanlines = 16;
3359                         break;
3360                 case 4:
3361                         min_scanlines = 8;
3362                         break;
3363                 case 8:
3364                         min_scanlines = 4;
3365                         break;
3366                 default:
3367                         WARN(1, "Unsupported pixel depth %u for rotation",
3368                              plane_bpp);
3369                         min_scanlines = 32;
3370                 }
3371         }
3372
3373         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3374 }
3375
3376 static void
3377 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3378                  uint16_t *minimum, uint16_t *y_minimum)
3379 {
3380         const struct drm_plane_state *pstate;
3381         struct drm_plane *plane;
3382
3383         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3384                 struct intel_plane *intel_plane = to_intel_plane(plane);
3385                 int id = skl_wm_plane_id(intel_plane);
3386
3387                 if (id == PLANE_CURSOR)
3388                         continue;
3389
3390                 if (!pstate->visible)
3391                         continue;
3392
3393                 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3394                 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3395         }
3396
3397         minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3398 }
3399
3400 static int
3401 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3402                       struct skl_ddb_allocation *ddb /* out */)
3403 {
3404         struct drm_atomic_state *state = cstate->base.state;
3405         struct drm_crtc *crtc = cstate->base.crtc;
3406         struct drm_device *dev = crtc->dev;
3407         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3408         enum pipe pipe = intel_crtc->pipe;
3409         struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
3410         uint16_t alloc_size, start;
3411         uint16_t minimum[I915_MAX_PLANES] = {};
3412         uint16_t y_minimum[I915_MAX_PLANES] = {};
3413         unsigned int total_data_rate;
3414         int num_active;
3415         int id, i;
3416         unsigned plane_data_rate[I915_MAX_PLANES] = {};
3417         unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
3418
3419         /* Clear the partitioning for disabled planes. */
3420         memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3421         memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3422
3423         if (WARN_ON(!state))
3424                 return 0;
3425
3426         if (!cstate->base.active) {
3427                 alloc->start = alloc->end = 0;
3428                 return 0;
3429         }
3430
3431         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3432         alloc_size = skl_ddb_entry_size(alloc);
3433         if (alloc_size == 0) {
3434                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3435                 return 0;
3436         }
3437
3438         skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
3439
3440         /*
3441          * 1. Allocate the mininum required blocks for each active plane
3442          * and allocate the cursor, it doesn't require extra allocation
3443          * proportional to the data rate.
3444          */
3445
3446         for (i = 0; i < I915_MAX_PLANES; i++) {
3447                 alloc_size -= minimum[i];
3448                 alloc_size -= y_minimum[i];
3449         }
3450
3451         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3452         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3453
3454         /*
3455          * 2. Distribute the remaining space in proportion to the amount of
3456          * data each plane needs to fetch from memory.
3457          *
3458          * FIXME: we may not allocate every single block here.
3459          */
3460         total_data_rate = skl_get_total_relative_data_rate(cstate,
3461                                                            plane_data_rate,
3462                                                            plane_y_data_rate);
3463         if (total_data_rate == 0)
3464                 return 0;
3465
3466         start = alloc->start;
3467         for (id = 0; id < I915_MAX_PLANES; id++) {
3468                 unsigned int data_rate, y_data_rate;
3469                 uint16_t plane_blocks, y_plane_blocks = 0;
3470
3471                 if (id == PLANE_CURSOR)
3472                         continue;
3473
3474                 data_rate = plane_data_rate[id];
3475
3476                 /*
3477                  * allocation for (packed formats) or (uv-plane part of planar format):
3478                  * promote the expression to 64 bits to avoid overflowing, the
3479                  * result is < available as data_rate / total_data_rate < 1
3480                  */
3481                 plane_blocks = minimum[id];
3482                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3483                                         total_data_rate);
3484
3485                 /* Leave disabled planes at (0,0) */
3486                 if (data_rate) {
3487                         ddb->plane[pipe][id].start = start;
3488                         ddb->plane[pipe][id].end = start + plane_blocks;
3489                 }
3490
3491                 start += plane_blocks;
3492
3493                 /*
3494                  * allocation for y_plane part of planar format:
3495                  */
3496                 y_data_rate = plane_y_data_rate[id];
3497
3498                 y_plane_blocks = y_minimum[id];
3499                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3500                                         total_data_rate);
3501
3502                 if (y_data_rate) {
3503                         ddb->y_plane[pipe][id].start = start;
3504                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3505                 }
3506
3507                 start += y_plane_blocks;
3508         }
3509
3510         return 0;
3511 }
3512
3513 /*
3514  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3515  * for the read latency) and cpp should always be <= 8, so that
3516  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3517  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3518 */
3519 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3520 {
3521         uint32_t wm_intermediate_val, ret;
3522
3523         if (latency == 0)
3524                 return UINT_MAX;
3525
3526         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3527         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3528
3529         return ret;
3530 }
3531
3532 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3533                                uint32_t latency, uint32_t plane_blocks_per_line)
3534 {
3535         uint32_t ret;
3536         uint32_t wm_intermediate_val;
3537
3538         if (latency == 0)
3539                 return UINT_MAX;
3540
3541         wm_intermediate_val = latency * pixel_rate;
3542         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3543                                 plane_blocks_per_line;
3544
3545         return ret;
3546 }
3547
3548 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3549                                               struct intel_plane_state *pstate)
3550 {
3551         uint64_t adjusted_pixel_rate;
3552         uint64_t downscale_amount;
3553         uint64_t pixel_rate;
3554
3555         /* Shouldn't reach here on disabled planes... */
3556         if (WARN_ON(!pstate->base.visible))
3557                 return 0;
3558
3559         /*
3560          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3561          * with additional adjustments for plane-specific scaling.
3562          */
3563         adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
3564         downscale_amount = skl_plane_downscale_amount(pstate);
3565
3566         pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3567         WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3568
3569         return pixel_rate;
3570 }
3571
3572 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3573                                 struct intel_crtc_state *cstate,
3574                                 struct intel_plane_state *intel_pstate,
3575                                 uint16_t ddb_allocation,
3576                                 int level,
3577                                 uint16_t *out_blocks, /* out */
3578                                 uint8_t *out_lines, /* out */
3579                                 bool *enabled /* out */)
3580 {
3581         struct drm_plane_state *pstate = &intel_pstate->base;
3582         struct drm_framebuffer *fb = pstate->fb;
3583         uint32_t latency = dev_priv->wm.skl_latency[level];
3584         uint32_t method1, method2;
3585         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3586         uint32_t res_blocks, res_lines;
3587         uint32_t selected_result;
3588         uint8_t cpp;
3589         uint32_t width = 0, height = 0;
3590         uint32_t plane_pixel_rate;
3591         uint32_t y_tile_minimum, y_min_scanlines;
3592         struct intel_atomic_state *state =
3593                 to_intel_atomic_state(cstate->base.state);
3594         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
3595
3596         if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3597                 *enabled = false;
3598                 return 0;
3599         }
3600
3601         if (apply_memory_bw_wa && fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3602                 latency += 15;
3603
3604         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3605         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3606
3607         if (drm_rotation_90_or_270(pstate->rotation))
3608                 swap(width, height);
3609
3610         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3611         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3612
3613         if (drm_rotation_90_or_270(pstate->rotation)) {
3614                 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3615                         drm_format_plane_cpp(fb->pixel_format, 1) :
3616                         drm_format_plane_cpp(fb->pixel_format, 0);
3617
3618                 switch (cpp) {
3619                 case 1:
3620                         y_min_scanlines = 16;
3621                         break;
3622                 case 2:
3623                         y_min_scanlines = 8;
3624                         break;
3625                 case 4:
3626                         y_min_scanlines = 4;
3627                         break;
3628                 default:
3629                         MISSING_CASE(cpp);
3630                         return -EINVAL;
3631                 }
3632         } else {
3633                 y_min_scanlines = 4;
3634         }
3635
3636         if (apply_memory_bw_wa)
3637                 y_min_scanlines *= 2;
3638
3639         plane_bytes_per_line = width * cpp;
3640         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3641             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3642                 plane_blocks_per_line =
3643                       DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3644                 plane_blocks_per_line /= y_min_scanlines;
3645         } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3646                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3647                                         + 1;
3648         } else {
3649                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3650         }
3651
3652         method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3653         method2 = skl_wm_method2(plane_pixel_rate,
3654                                  cstate->base.adjusted_mode.crtc_htotal,
3655                                  latency,
3656                                  plane_blocks_per_line);
3657
3658         y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3659
3660         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3661             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3662                 selected_result = max(method2, y_tile_minimum);
3663         } else {
3664                 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3665                     (plane_bytes_per_line / 512 < 1))
3666                         selected_result = method2;
3667                 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
3668                         selected_result = min(method1, method2);
3669                 else
3670                         selected_result = method1;
3671         }
3672
3673         res_blocks = selected_result + 1;
3674         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3675
3676         if (level >= 1 && level <= 7) {
3677                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3678                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3679                         res_blocks += y_tile_minimum;
3680                         res_lines += y_min_scanlines;
3681                 } else {
3682                         res_blocks++;
3683                 }
3684         }
3685
3686         if (res_blocks >= ddb_allocation || res_lines > 31) {
3687                 *enabled = false;
3688
3689                 /*
3690                  * If there are no valid level 0 watermarks, then we can't
3691                  * support this display configuration.
3692                  */
3693                 if (level) {
3694                         return 0;
3695                 } else {
3696                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3697                         DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3698                                       to_intel_crtc(cstate->base.crtc)->pipe,
3699                                       skl_wm_plane_id(to_intel_plane(pstate->plane)),
3700                                       res_blocks, ddb_allocation, res_lines);
3701
3702                         return -EINVAL;
3703                 }
3704         }
3705
3706         *out_blocks = res_blocks;
3707         *out_lines = res_lines;
3708         *enabled = true;
3709
3710         return 0;
3711 }
3712
3713 static int
3714 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3715                      struct skl_ddb_allocation *ddb,
3716                      struct intel_crtc_state *cstate,
3717                      struct intel_plane *intel_plane,
3718                      int level,
3719                      struct skl_wm_level *result)
3720 {
3721         struct drm_atomic_state *state = cstate->base.state;
3722         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3723         struct drm_plane *plane = &intel_plane->base;
3724         struct intel_plane_state *intel_pstate = NULL;
3725         uint16_t ddb_blocks;
3726         enum pipe pipe = intel_crtc->pipe;
3727         int ret;
3728         int i = skl_wm_plane_id(intel_plane);
3729
3730         if (state)
3731                 intel_pstate =
3732                         intel_atomic_get_existing_plane_state(state,
3733                                                               intel_plane);
3734
3735         /*
3736          * Note: If we start supporting multiple pending atomic commits against
3737          * the same planes/CRTC's in the future, plane->state will no longer be
3738          * the correct pre-state to use for the calculations here and we'll
3739          * need to change where we get the 'unchanged' plane data from.
3740          *
3741          * For now this is fine because we only allow one queued commit against
3742          * a CRTC.  Even if the plane isn't modified by this transaction and we
3743          * don't have a plane lock, we still have the CRTC's lock, so we know
3744          * that no other transactions are racing with us to update it.
3745          */
3746         if (!intel_pstate)
3747                 intel_pstate = to_intel_plane_state(plane->state);
3748
3749         WARN_ON(!intel_pstate->base.fb);
3750
3751         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3752
3753         ret = skl_compute_plane_wm(dev_priv,
3754                                    cstate,
3755                                    intel_pstate,
3756                                    ddb_blocks,
3757                                    level,
3758                                    &result->plane_res_b,
3759                                    &result->plane_res_l,
3760                                    &result->plane_en);
3761         if (ret)
3762                 return ret;
3763
3764         return 0;
3765 }
3766
3767 static uint32_t
3768 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3769 {
3770         uint32_t pixel_rate;
3771
3772         if (!cstate->base.active)
3773                 return 0;
3774
3775         pixel_rate = ilk_pipe_pixel_rate(cstate);
3776
3777         if (WARN_ON(pixel_rate == 0))
3778                 return 0;
3779
3780         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3781                             pixel_rate);
3782 }
3783
3784 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3785                                       struct skl_wm_level *trans_wm /* out */)
3786 {
3787         if (!cstate->base.active)
3788                 return;
3789
3790         /* Until we know more, just disable transition WMs */
3791         trans_wm->plane_en = false;
3792 }
3793
3794 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3795                              struct skl_ddb_allocation *ddb,
3796                              struct skl_pipe_wm *pipe_wm)
3797 {
3798         struct drm_device *dev = cstate->base.crtc->dev;
3799         const struct drm_i915_private *dev_priv = to_i915(dev);
3800         struct intel_plane *intel_plane;
3801         struct skl_plane_wm *wm;
3802         int level, max_level = ilk_wm_max_level(dev_priv);
3803         int ret;
3804
3805         /*
3806          * We'll only calculate watermarks for planes that are actually
3807          * enabled, so make sure all other planes are set as disabled.
3808          */
3809         memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3810
3811         for_each_intel_plane_mask(&dev_priv->drm,
3812                                   intel_plane,
3813                                   cstate->base.plane_mask) {
3814                 wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
3815
3816                 for (level = 0; level <= max_level; level++) {
3817                         ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3818                                                    intel_plane, level,
3819                                                    &wm->wm[level]);
3820                         if (ret)
3821                                 return ret;
3822                 }
3823                 skl_compute_transition_wm(cstate, &wm->trans_wm);
3824         }
3825         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3826
3827         return 0;
3828 }
3829
3830 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3831                                 i915_reg_t reg,
3832                                 const struct skl_ddb_entry *entry)
3833 {
3834         if (entry->end)
3835                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3836         else
3837                 I915_WRITE(reg, 0);
3838 }
3839
3840 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3841                                i915_reg_t reg,
3842                                const struct skl_wm_level *level)
3843 {
3844         uint32_t val = 0;
3845
3846         if (level->plane_en) {
3847                 val |= PLANE_WM_EN;
3848                 val |= level->plane_res_b;
3849                 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3850         }
3851
3852         I915_WRITE(reg, val);
3853 }
3854
3855 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3856                         const struct skl_plane_wm *wm,
3857                         const struct skl_ddb_allocation *ddb,
3858                         int plane)
3859 {
3860         struct drm_crtc *crtc = &intel_crtc->base;
3861         struct drm_device *dev = crtc->dev;
3862         struct drm_i915_private *dev_priv = to_i915(dev);
3863         int level, max_level = ilk_wm_max_level(dev_priv);
3864         enum pipe pipe = intel_crtc->pipe;
3865
3866         for (level = 0; level <= max_level; level++) {
3867                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane, level),
3868                                    &wm->wm[level]);
3869         }
3870         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
3871                            &wm->trans_wm);
3872
3873         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3874                             &ddb->plane[pipe][plane]);
3875         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3876                             &ddb->y_plane[pipe][plane]);
3877 }
3878
3879 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3880                          const struct skl_plane_wm *wm,
3881                          const struct skl_ddb_allocation *ddb)
3882 {
3883         struct drm_crtc *crtc = &intel_crtc->base;
3884         struct drm_device *dev = crtc->dev;
3885         struct drm_i915_private *dev_priv = to_i915(dev);
3886         int level, max_level = ilk_wm_max_level(dev_priv);
3887         enum pipe pipe = intel_crtc->pipe;
3888
3889         for (level = 0; level <= max_level; level++) {
3890                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3891                                    &wm->wm[level]);
3892         }
3893         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
3894
3895         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3896                             &ddb->plane[pipe][PLANE_CURSOR]);
3897 }
3898
3899 bool skl_wm_level_equals(const struct skl_wm_level *l1,
3900                          const struct skl_wm_level *l2)
3901 {
3902         if (l1->plane_en != l2->plane_en)
3903                 return false;
3904
3905         /* If both planes aren't enabled, the rest shouldn't matter */
3906         if (!l1->plane_en)
3907                 return true;
3908
3909         return (l1->plane_res_l == l2->plane_res_l &&
3910                 l1->plane_res_b == l2->plane_res_b);
3911 }
3912
3913 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3914                                            const struct skl_ddb_entry *b)
3915 {
3916         return a->start < b->end && b->start < a->end;
3917 }
3918
3919 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
3920                                  const struct skl_ddb_entry *ddb,
3921                                  int ignore)
3922 {
3923         int i;
3924
3925         for (i = 0; i < I915_MAX_PIPES; i++)
3926                 if (i != ignore && entries[i] &&
3927                     skl_ddb_entries_overlap(ddb, entries[i]))
3928                         return true;
3929
3930         return false;
3931 }
3932
3933 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3934                               const struct skl_pipe_wm *old_pipe_wm,
3935                               struct skl_pipe_wm *pipe_wm, /* out */
3936                               struct skl_ddb_allocation *ddb, /* out */
3937                               bool *changed /* out */)
3938 {
3939         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3940         int ret;
3941
3942         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3943         if (ret)
3944                 return ret;
3945
3946         if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
3947                 *changed = false;
3948         else
3949                 *changed = true;
3950
3951         return 0;
3952 }
3953
3954 static uint32_t
3955 pipes_modified(struct drm_atomic_state *state)
3956 {
3957         struct drm_crtc *crtc;
3958         struct drm_crtc_state *cstate;
3959         uint32_t i, ret = 0;
3960
3961         for_each_crtc_in_state(state, crtc, cstate, i)
3962                 ret |= drm_crtc_mask(crtc);
3963
3964         return ret;
3965 }
3966
3967 static int
3968 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3969 {
3970         struct drm_atomic_state *state = cstate->base.state;
3971         struct drm_device *dev = state->dev;
3972         struct drm_crtc *crtc = cstate->base.crtc;
3973         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3974         struct drm_i915_private *dev_priv = to_i915(dev);
3975         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3976         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3977         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3978         struct drm_plane_state *plane_state;
3979         struct drm_plane *plane;
3980         enum pipe pipe = intel_crtc->pipe;
3981         int id;
3982
3983         WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3984
3985         drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
3986                 id = skl_wm_plane_id(to_intel_plane(plane));
3987
3988                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3989                                         &new_ddb->plane[pipe][id]) &&
3990                     skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3991                                         &new_ddb->y_plane[pipe][id]))
3992                         continue;
3993
3994                 plane_state = drm_atomic_get_plane_state(state, plane);
3995                 if (IS_ERR(plane_state))
3996                         return PTR_ERR(plane_state);
3997         }
3998
3999         return 0;
4000 }
4001
4002 static int
4003 skl_compute_ddb(struct drm_atomic_state *state)
4004 {
4005         struct drm_device *dev = state->dev;
4006         struct drm_i915_private *dev_priv = to_i915(dev);
4007         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4008         struct intel_crtc *intel_crtc;
4009         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4010         uint32_t realloc_pipes = pipes_modified(state);
4011         int ret;
4012
4013         /*
4014          * If this is our first atomic update following hardware readout,
4015          * we can't trust the DDB that the BIOS programmed for us.  Let's
4016          * pretend that all pipes switched active status so that we'll
4017          * ensure a full DDB recompute.
4018          */
4019         if (dev_priv->wm.distrust_bios_wm) {
4020                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4021                                        state->acquire_ctx);
4022                 if (ret)
4023                         return ret;
4024
4025                 intel_state->active_pipe_changes = ~0;
4026
4027                 /*
4028                  * We usually only initialize intel_state->active_crtcs if we
4029                  * we're doing a modeset; make sure this field is always
4030                  * initialized during the sanitization process that happens
4031                  * on the first commit too.
4032                  */
4033                 if (!intel_state->modeset)
4034                         intel_state->active_crtcs = dev_priv->active_crtcs;
4035         }
4036
4037         /*
4038          * If the modeset changes which CRTC's are active, we need to
4039          * recompute the DDB allocation for *all* active pipes, even
4040          * those that weren't otherwise being modified in any way by this
4041          * atomic commit.  Due to the shrinking of the per-pipe allocations
4042          * when new active CRTC's are added, it's possible for a pipe that
4043          * we were already using and aren't changing at all here to suddenly
4044          * become invalid if its DDB needs exceeds its new allocation.
4045          *
4046          * Note that if we wind up doing a full DDB recompute, we can't let
4047          * any other display updates race with this transaction, so we need
4048          * to grab the lock on *all* CRTC's.
4049          */
4050         if (intel_state->active_pipe_changes) {
4051                 realloc_pipes = ~0;
4052                 intel_state->wm_results.dirty_pipes = ~0;
4053         }
4054
4055         /*
4056          * We're not recomputing for the pipes not included in the commit, so
4057          * make sure we start with the current state.
4058          */
4059         memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4060
4061         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4062                 struct intel_crtc_state *cstate;
4063
4064                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4065                 if (IS_ERR(cstate))
4066                         return PTR_ERR(cstate);
4067
4068                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4069                 if (ret)
4070                         return ret;
4071
4072                 ret = skl_ddb_add_affected_planes(cstate);
4073                 if (ret)
4074                         return ret;
4075         }
4076
4077         return 0;
4078 }
4079
4080 static void
4081 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4082                      struct skl_wm_values *src,
4083                      enum pipe pipe)
4084 {
4085         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4086                sizeof(dst->ddb.y_plane[pipe]));
4087         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4088                sizeof(dst->ddb.plane[pipe]));
4089 }
4090
4091 static void
4092 skl_print_wm_changes(const struct drm_atomic_state *state)
4093 {
4094         const struct drm_device *dev = state->dev;
4095         const struct drm_i915_private *dev_priv = to_i915(dev);
4096         const struct intel_atomic_state *intel_state =
4097                 to_intel_atomic_state(state);
4098         const struct drm_crtc *crtc;
4099         const struct drm_crtc_state *cstate;
4100         const struct intel_plane *intel_plane;
4101         const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4102         const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4103         int id;
4104         int i;
4105
4106         for_each_crtc_in_state(state, crtc, cstate, i) {
4107                 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4108                 enum pipe pipe = intel_crtc->pipe;
4109
4110                 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4111                         const struct skl_ddb_entry *old, *new;
4112
4113                         id = skl_wm_plane_id(intel_plane);
4114                         old = &old_ddb->plane[pipe][id];
4115                         new = &new_ddb->plane[pipe][id];
4116
4117                         if (skl_ddb_entry_equal(old, new))
4118                                 continue;
4119
4120                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4121                                          intel_plane->base.base.id,
4122                                          intel_plane->base.name,
4123                                          old->start, old->end,
4124                                          new->start, new->end);
4125                 }
4126         }
4127 }
4128
4129 static int
4130 skl_compute_wm(struct drm_atomic_state *state)
4131 {
4132         struct drm_crtc *crtc;
4133         struct drm_crtc_state *cstate;
4134         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4135         struct skl_wm_values *results = &intel_state->wm_results;
4136         struct skl_pipe_wm *pipe_wm;
4137         bool changed = false;
4138         int ret, i;
4139
4140         /*
4141          * If this transaction isn't actually touching any CRTC's, don't
4142          * bother with watermark calculation.  Note that if we pass this
4143          * test, we're guaranteed to hold at least one CRTC state mutex,
4144          * which means we can safely use values like dev_priv->active_crtcs
4145          * since any racing commits that want to update them would need to
4146          * hold _all_ CRTC state mutexes.
4147          */
4148         for_each_crtc_in_state(state, crtc, cstate, i)
4149                 changed = true;
4150         if (!changed)
4151                 return 0;
4152
4153         /* Clear all dirty flags */
4154         results->dirty_pipes = 0;
4155
4156         ret = skl_compute_ddb(state);
4157         if (ret)
4158                 return ret;
4159
4160         /*
4161          * Calculate WM's for all pipes that are part of this transaction.
4162          * Note that the DDB allocation above may have added more CRTC's that
4163          * weren't otherwise being modified (and set bits in dirty_pipes) if
4164          * pipe allocations had to change.
4165          *
4166          * FIXME:  Now that we're doing this in the atomic check phase, we
4167          * should allow skl_update_pipe_wm() to return failure in cases where
4168          * no suitable watermark values can be found.
4169          */
4170         for_each_crtc_in_state(state, crtc, cstate, i) {
4171                 struct intel_crtc_state *intel_cstate =
4172                         to_intel_crtc_state(cstate);
4173                 const struct skl_pipe_wm *old_pipe_wm =
4174                         &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
4175
4176                 pipe_wm = &intel_cstate->wm.skl.optimal;
4177                 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4178                                          &results->ddb, &changed);
4179                 if (ret)
4180                         return ret;
4181
4182                 if (changed)
4183                         results->dirty_pipes |= drm_crtc_mask(crtc);
4184
4185                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4186                         /* This pipe's WM's did not change */
4187                         continue;
4188
4189                 intel_cstate->update_wm_pre = true;
4190         }
4191
4192         skl_print_wm_changes(state);
4193
4194         return 0;
4195 }
4196
4197 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
4198                                       struct intel_crtc_state *cstate)
4199 {
4200         struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
4201         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4202         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4203         const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
4204         enum pipe pipe = crtc->pipe;
4205         int plane;
4206
4207         if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
4208                 return;
4209
4210         I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
4211
4212         for_each_universal_plane(dev_priv, pipe, plane)
4213                 skl_write_plane_wm(crtc, &pipe_wm->planes[plane], ddb, plane);
4214
4215         skl_write_cursor_wm(crtc, &pipe_wm->planes[PLANE_CURSOR], ddb);
4216 }
4217
4218 static void skl_initial_wm(struct intel_atomic_state *state,
4219                            struct intel_crtc_state *cstate)
4220 {
4221         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4222         struct drm_device *dev = intel_crtc->base.dev;
4223         struct drm_i915_private *dev_priv = to_i915(dev);
4224         struct skl_wm_values *results = &state->wm_results;
4225         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4226         enum pipe pipe = intel_crtc->pipe;
4227
4228         if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
4229                 return;
4230
4231         mutex_lock(&dev_priv->wm.wm_mutex);
4232
4233         if (cstate->base.active_changed)
4234                 skl_atomic_update_crtc_wm(state, cstate);
4235
4236         skl_copy_wm_for_pipe(hw_vals, results, pipe);
4237
4238         mutex_unlock(&dev_priv->wm.wm_mutex);
4239 }
4240
4241 static void ilk_compute_wm_config(struct drm_device *dev,
4242                                   struct intel_wm_config *config)
4243 {
4244         struct intel_crtc *crtc;
4245
4246         /* Compute the currently _active_ config */
4247         for_each_intel_crtc(dev, crtc) {
4248                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4249
4250                 if (!wm->pipe_enabled)
4251                         continue;
4252
4253                 config->sprites_enabled |= wm->sprites_enabled;
4254                 config->sprites_scaled |= wm->sprites_scaled;
4255                 config->num_pipes_active++;
4256         }
4257 }
4258
4259 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4260 {
4261         struct drm_device *dev = &dev_priv->drm;
4262         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4263         struct ilk_wm_maximums max;
4264         struct intel_wm_config config = {};
4265         struct ilk_wm_values results = {};
4266         enum intel_ddb_partitioning partitioning;
4267
4268         ilk_compute_wm_config(dev, &config);
4269
4270         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4271         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4272
4273         /* 5/6 split only in single pipe config on IVB+ */
4274         if (INTEL_GEN(dev_priv) >= 7 &&
4275             config.num_pipes_active == 1 && config.sprites_enabled) {
4276                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4277                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4278
4279                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4280         } else {
4281                 best_lp_wm = &lp_wm_1_2;
4282         }
4283
4284         partitioning = (best_lp_wm == &lp_wm_1_2) ?
4285                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4286
4287         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4288
4289         ilk_write_wm_values(dev_priv, &results);
4290 }
4291
4292 static void ilk_initial_watermarks(struct intel_atomic_state *state,
4293                                    struct intel_crtc_state *cstate)
4294 {
4295         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4296         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4297
4298         mutex_lock(&dev_priv->wm.wm_mutex);
4299         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4300         ilk_program_watermarks(dev_priv);
4301         mutex_unlock(&dev_priv->wm.wm_mutex);
4302 }
4303
4304 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
4305                                     struct intel_crtc_state *cstate)
4306 {
4307         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4308         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4309
4310         mutex_lock(&dev_priv->wm.wm_mutex);
4311         if (cstate->wm.need_postvbl_update) {
4312                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4313                 ilk_program_watermarks(dev_priv);
4314         }
4315         mutex_unlock(&dev_priv->wm.wm_mutex);
4316 }
4317
4318 static inline void skl_wm_level_from_reg_val(uint32_t val,
4319                                              struct skl_wm_level *level)
4320 {
4321         level->plane_en = val & PLANE_WM_EN;
4322         level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4323         level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4324                 PLANE_WM_LINES_MASK;
4325 }
4326
4327 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4328                               struct skl_pipe_wm *out)
4329 {
4330         struct drm_device *dev = crtc->dev;
4331         struct drm_i915_private *dev_priv = to_i915(dev);
4332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4333         struct intel_plane *intel_plane;
4334         struct skl_plane_wm *wm;
4335         enum pipe pipe = intel_crtc->pipe;
4336         int level, id, max_level;
4337         uint32_t val;
4338
4339         max_level = ilk_wm_max_level(dev_priv);
4340
4341         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4342                 id = skl_wm_plane_id(intel_plane);
4343                 wm = &out->planes[id];
4344
4345                 for (level = 0; level <= max_level; level++) {
4346                         if (id != PLANE_CURSOR)
4347                                 val = I915_READ(PLANE_WM(pipe, id, level));
4348                         else
4349                                 val = I915_READ(CUR_WM(pipe, level));
4350
4351                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
4352                 }
4353
4354                 if (id != PLANE_CURSOR)
4355                         val = I915_READ(PLANE_WM_TRANS(pipe, id));
4356                 else
4357                         val = I915_READ(CUR_WM_TRANS(pipe));
4358
4359                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
4360         }
4361
4362         if (!intel_crtc->active)
4363                 return;
4364
4365         out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
4366 }
4367
4368 void skl_wm_get_hw_state(struct drm_device *dev)
4369 {
4370         struct drm_i915_private *dev_priv = to_i915(dev);
4371         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4372         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4373         struct drm_crtc *crtc;
4374         struct intel_crtc *intel_crtc;
4375         struct intel_crtc_state *cstate;
4376
4377         skl_ddb_get_hw_state(dev_priv, ddb);
4378         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4379                 intel_crtc = to_intel_crtc(crtc);
4380                 cstate = to_intel_crtc_state(crtc->state);
4381
4382                 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4383
4384                 if (intel_crtc->active)
4385                         hw->dirty_pipes |= drm_crtc_mask(crtc);
4386         }
4387
4388         if (dev_priv->active_crtcs) {
4389                 /* Fully recompute DDB on first atomic commit */
4390                 dev_priv->wm.distrust_bios_wm = true;
4391         } else {
4392                 /* Easy/common case; just sanitize DDB now if everything off */
4393                 memset(ddb, 0, sizeof(*ddb));
4394         }
4395 }
4396
4397 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4398 {
4399         struct drm_device *dev = crtc->dev;
4400         struct drm_i915_private *dev_priv = to_i915(dev);
4401         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4403         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4404         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4405         enum pipe pipe = intel_crtc->pipe;
4406         static const i915_reg_t wm0_pipe_reg[] = {
4407                 [PIPE_A] = WM0_PIPEA_ILK,
4408                 [PIPE_B] = WM0_PIPEB_ILK,
4409                 [PIPE_C] = WM0_PIPEC_IVB,
4410         };
4411
4412         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4413         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4414                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4415
4416         memset(active, 0, sizeof(*active));
4417
4418         active->pipe_enabled = intel_crtc->active;
4419
4420         if (active->pipe_enabled) {
4421                 u32 tmp = hw->wm_pipe[pipe];
4422
4423                 /*
4424                  * For active pipes LP0 watermark is marked as
4425                  * enabled, and LP1+ watermaks as disabled since
4426                  * we can't really reverse compute them in case
4427                  * multiple pipes are active.
4428                  */
4429                 active->wm[0].enable = true;
4430                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4431                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4432                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4433                 active->linetime = hw->wm_linetime[pipe];
4434         } else {
4435                 int level, max_level = ilk_wm_max_level(dev_priv);
4436
4437                 /*
4438                  * For inactive pipes, all watermark levels
4439                  * should be marked as enabled but zeroed,
4440                  * which is what we'd compute them to.
4441                  */
4442                 for (level = 0; level <= max_level; level++)
4443                         active->wm[level].enable = true;
4444         }
4445
4446         intel_crtc->wm.active.ilk = *active;
4447 }
4448
4449 #define _FW_WM(value, plane) \
4450         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4451 #define _FW_WM_VLV(value, plane) \
4452         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4453
4454 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4455                                struct vlv_wm_values *wm)
4456 {
4457         enum pipe pipe;
4458         uint32_t tmp;
4459
4460         for_each_pipe(dev_priv, pipe) {
4461                 tmp = I915_READ(VLV_DDL(pipe));
4462
4463                 wm->ddl[pipe].primary =
4464                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4465                 wm->ddl[pipe].cursor =
4466                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4467                 wm->ddl[pipe].sprite[0] =
4468                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4469                 wm->ddl[pipe].sprite[1] =
4470                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4471         }
4472
4473         tmp = I915_READ(DSPFW1);
4474         wm->sr.plane = _FW_WM(tmp, SR);
4475         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4476         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4477         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4478
4479         tmp = I915_READ(DSPFW2);
4480         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4481         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4482         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4483
4484         tmp = I915_READ(DSPFW3);
4485         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4486
4487         if (IS_CHERRYVIEW(dev_priv)) {
4488                 tmp = I915_READ(DSPFW7_CHV);
4489                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4490                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4491
4492                 tmp = I915_READ(DSPFW8_CHV);
4493                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4494                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4495
4496                 tmp = I915_READ(DSPFW9_CHV);
4497                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4498                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4499
4500                 tmp = I915_READ(DSPHOWM);
4501                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4502                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4503                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4504                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4505                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4506                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4507                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4508                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4509                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4510                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4511         } else {
4512                 tmp = I915_READ(DSPFW7);
4513                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4514                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4515
4516                 tmp = I915_READ(DSPHOWM);
4517                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4518                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4519                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4520                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4521                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4522                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4523                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4524         }
4525 }
4526
4527 #undef _FW_WM
4528 #undef _FW_WM_VLV
4529
4530 void vlv_wm_get_hw_state(struct drm_device *dev)
4531 {
4532         struct drm_i915_private *dev_priv = to_i915(dev);
4533         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4534         struct intel_plane *plane;
4535         enum pipe pipe;
4536         u32 val;
4537
4538         vlv_read_wm_values(dev_priv, wm);
4539
4540         for_each_intel_plane(dev, plane) {
4541                 switch (plane->base.type) {
4542                         int sprite;
4543                 case DRM_PLANE_TYPE_CURSOR:
4544                         plane->wm.fifo_size = 63;
4545                         break;
4546                 case DRM_PLANE_TYPE_PRIMARY:
4547                         plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, 0);
4548                         break;
4549                 case DRM_PLANE_TYPE_OVERLAY:
4550                         sprite = plane->plane;
4551                         plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, sprite + 1);
4552                         break;
4553                 }
4554         }
4555
4556         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4557         wm->level = VLV_WM_LEVEL_PM2;
4558
4559         if (IS_CHERRYVIEW(dev_priv)) {
4560                 mutex_lock(&dev_priv->rps.hw_lock);
4561
4562                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4563                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4564                         wm->level = VLV_WM_LEVEL_PM5;
4565
4566                 /*
4567                  * If DDR DVFS is disabled in the BIOS, Punit
4568                  * will never ack the request. So if that happens
4569                  * assume we don't have to enable/disable DDR DVFS
4570                  * dynamically. To test that just set the REQ_ACK
4571                  * bit to poke the Punit, but don't change the
4572                  * HIGH/LOW bits so that we don't actually change
4573                  * the current state.
4574                  */
4575                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4576                 val |= FORCE_DDR_FREQ_REQ_ACK;
4577                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4578
4579                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4580                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4581                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4582                                       "assuming DDR DVFS is disabled\n");
4583                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4584                 } else {
4585                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4586                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4587                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4588                 }
4589
4590                 mutex_unlock(&dev_priv->rps.hw_lock);
4591         }
4592
4593         for_each_pipe(dev_priv, pipe)
4594                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4595                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4596                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4597
4598         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4599                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4600 }
4601
4602 void ilk_wm_get_hw_state(struct drm_device *dev)
4603 {
4604         struct drm_i915_private *dev_priv = to_i915(dev);
4605         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4606         struct drm_crtc *crtc;
4607
4608         for_each_crtc(dev, crtc)
4609                 ilk_pipe_wm_get_hw_state(crtc);
4610
4611         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4612         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4613         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4614
4615         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4616         if (INTEL_GEN(dev_priv) >= 7) {
4617                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4618                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4619         }
4620
4621         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4622                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4623                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4624         else if (IS_IVYBRIDGE(dev_priv))
4625                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4626                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4627
4628         hw->enable_fbc_wm =
4629                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4630 }
4631
4632 /**
4633  * intel_update_watermarks - update FIFO watermark values based on current modes
4634  *
4635  * Calculate watermark values for the various WM regs based on current mode
4636  * and plane configuration.
4637  *
4638  * There are several cases to deal with here:
4639  *   - normal (i.e. non-self-refresh)
4640  *   - self-refresh (SR) mode
4641  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4642  *   - lines are small relative to FIFO size (buffer can hold more than 2
4643  *     lines), so need to account for TLB latency
4644  *
4645  *   The normal calculation is:
4646  *     watermark = dotclock * bytes per pixel * latency
4647  *   where latency is platform & configuration dependent (we assume pessimal
4648  *   values here).
4649  *
4650  *   The SR calculation is:
4651  *     watermark = (trunc(latency/line time)+1) * surface width *
4652  *       bytes per pixel
4653  *   where
4654  *     line time = htotal / dotclock
4655  *     surface width = hdisplay for normal plane and 64 for cursor
4656  *   and latency is assumed to be high, as above.
4657  *
4658  * The final value programmed to the register should always be rounded up,
4659  * and include an extra 2 entries to account for clock crossings.
4660  *
4661  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4662  * to set the non-SR watermarks to 8.
4663  */
4664 void intel_update_watermarks(struct intel_crtc *crtc)
4665 {
4666         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4667
4668         if (dev_priv->display.update_wm)
4669                 dev_priv->display.update_wm(crtc);
4670 }
4671
4672 /*
4673  * Lock protecting IPS related data structures
4674  */
4675 DEFINE_SPINLOCK(mchdev_lock);
4676
4677 /* Global for IPS driver to get at the current i915 device. Protected by
4678  * mchdev_lock. */
4679 static struct drm_i915_private *i915_mch_dev;
4680
4681 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4682 {
4683         u16 rgvswctl;
4684
4685         assert_spin_locked(&mchdev_lock);
4686
4687         rgvswctl = I915_READ16(MEMSWCTL);
4688         if (rgvswctl & MEMCTL_CMD_STS) {
4689                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4690                 return false; /* still busy with another command */
4691         }
4692
4693         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4694                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4695         I915_WRITE16(MEMSWCTL, rgvswctl);
4696         POSTING_READ16(MEMSWCTL);
4697
4698         rgvswctl |= MEMCTL_CMD_STS;
4699         I915_WRITE16(MEMSWCTL, rgvswctl);
4700
4701         return true;
4702 }
4703
4704 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4705 {
4706         u32 rgvmodectl;
4707         u8 fmax, fmin, fstart, vstart;
4708
4709         spin_lock_irq(&mchdev_lock);
4710
4711         rgvmodectl = I915_READ(MEMMODECTL);
4712
4713         /* Enable temp reporting */
4714         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4715         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4716
4717         /* 100ms RC evaluation intervals */
4718         I915_WRITE(RCUPEI, 100000);
4719         I915_WRITE(RCDNEI, 100000);
4720
4721         /* Set max/min thresholds to 90ms and 80ms respectively */
4722         I915_WRITE(RCBMAXAVG, 90000);
4723         I915_WRITE(RCBMINAVG, 80000);
4724
4725         I915_WRITE(MEMIHYST, 1);
4726
4727         /* Set up min, max, and cur for interrupt handling */
4728         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4729         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4730         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4731                 MEMMODE_FSTART_SHIFT;
4732
4733         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4734                 PXVFREQ_PX_SHIFT;
4735
4736         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4737         dev_priv->ips.fstart = fstart;
4738
4739         dev_priv->ips.max_delay = fstart;
4740         dev_priv->ips.min_delay = fmin;
4741         dev_priv->ips.cur_delay = fstart;
4742
4743         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4744                          fmax, fmin, fstart);
4745
4746         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4747
4748         /*
4749          * Interrupts will be enabled in ironlake_irq_postinstall
4750          */
4751
4752         I915_WRITE(VIDSTART, vstart);
4753         POSTING_READ(VIDSTART);
4754
4755         rgvmodectl |= MEMMODE_SWMODE_EN;
4756         I915_WRITE(MEMMODECTL, rgvmodectl);
4757
4758         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4759                 DRM_ERROR("stuck trying to change perf mode\n");
4760         mdelay(1);
4761
4762         ironlake_set_drps(dev_priv, fstart);
4763
4764         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4765                 I915_READ(DDREC) + I915_READ(CSIEC);
4766         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4767         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4768         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4769
4770         spin_unlock_irq(&mchdev_lock);
4771 }
4772
4773 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4774 {
4775         u16 rgvswctl;
4776
4777         spin_lock_irq(&mchdev_lock);
4778
4779         rgvswctl = I915_READ16(MEMSWCTL);
4780
4781         /* Ack interrupts, disable EFC interrupt */
4782         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4783         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4784         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4785         I915_WRITE(DEIIR, DE_PCU_EVENT);
4786         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4787
4788         /* Go back to the starting frequency */
4789         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4790         mdelay(1);
4791         rgvswctl |= MEMCTL_CMD_STS;
4792         I915_WRITE(MEMSWCTL, rgvswctl);
4793         mdelay(1);
4794
4795         spin_unlock_irq(&mchdev_lock);
4796 }
4797
4798 /* There's a funny hw issue where the hw returns all 0 when reading from
4799  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4800  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4801  * all limits and the gpu stuck at whatever frequency it is at atm).
4802  */
4803 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4804 {
4805         u32 limits;
4806
4807         /* Only set the down limit when we've reached the lowest level to avoid
4808          * getting more interrupts, otherwise leave this clear. This prevents a
4809          * race in the hw when coming out of rc6: There's a tiny window where
4810          * the hw runs at the minimal clock before selecting the desired
4811          * frequency, if the down threshold expires in that window we will not
4812          * receive a down interrupt. */
4813         if (IS_GEN9(dev_priv)) {
4814                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4815                 if (val <= dev_priv->rps.min_freq_softlimit)
4816                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4817         } else {
4818                 limits = dev_priv->rps.max_freq_softlimit << 24;
4819                 if (val <= dev_priv->rps.min_freq_softlimit)
4820                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4821         }
4822
4823         return limits;
4824 }
4825
4826 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4827 {
4828         int new_power;
4829         u32 threshold_up = 0, threshold_down = 0; /* in % */
4830         u32 ei_up = 0, ei_down = 0;
4831
4832         new_power = dev_priv->rps.power;
4833         switch (dev_priv->rps.power) {
4834         case LOW_POWER:
4835                 if (val > dev_priv->rps.efficient_freq + 1 &&
4836                     val > dev_priv->rps.cur_freq)
4837                         new_power = BETWEEN;
4838                 break;
4839
4840         case BETWEEN:
4841                 if (val <= dev_priv->rps.efficient_freq &&
4842                     val < dev_priv->rps.cur_freq)
4843                         new_power = LOW_POWER;
4844                 else if (val >= dev_priv->rps.rp0_freq &&
4845                          val > dev_priv->rps.cur_freq)
4846                         new_power = HIGH_POWER;
4847                 break;
4848
4849         case HIGH_POWER:
4850                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4851                     val < dev_priv->rps.cur_freq)
4852                         new_power = BETWEEN;
4853                 break;
4854         }
4855         /* Max/min bins are special */
4856         if (val <= dev_priv->rps.min_freq_softlimit)
4857                 new_power = LOW_POWER;
4858         if (val >= dev_priv->rps.max_freq_softlimit)
4859                 new_power = HIGH_POWER;
4860         if (new_power == dev_priv->rps.power)
4861                 return;
4862
4863         /* Note the units here are not exactly 1us, but 1280ns. */
4864         switch (new_power) {
4865         case LOW_POWER:
4866                 /* Upclock if more than 95% busy over 16ms */
4867                 ei_up = 16000;
4868                 threshold_up = 95;
4869
4870                 /* Downclock if less than 85% busy over 32ms */
4871                 ei_down = 32000;
4872                 threshold_down = 85;
4873                 break;
4874
4875         case BETWEEN:
4876                 /* Upclock if more than 90% busy over 13ms */
4877                 ei_up = 13000;
4878                 threshold_up = 90;
4879
4880                 /* Downclock if less than 75% busy over 32ms */
4881                 ei_down = 32000;
4882                 threshold_down = 75;
4883                 break;
4884
4885         case HIGH_POWER:
4886                 /* Upclock if more than 85% busy over 10ms */
4887                 ei_up = 10000;
4888                 threshold_up = 85;
4889
4890                 /* Downclock if less than 60% busy over 32ms */
4891                 ei_down = 32000;
4892                 threshold_down = 60;
4893                 break;
4894         }
4895
4896         I915_WRITE(GEN6_RP_UP_EI,
4897                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
4898         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4899                    GT_INTERVAL_FROM_US(dev_priv,
4900                                        ei_up * threshold_up / 100));
4901
4902         I915_WRITE(GEN6_RP_DOWN_EI,
4903                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
4904         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4905                    GT_INTERVAL_FROM_US(dev_priv,
4906                                        ei_down * threshold_down / 100));
4907
4908         I915_WRITE(GEN6_RP_CONTROL,
4909                    GEN6_RP_MEDIA_TURBO |
4910                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4911                    GEN6_RP_MEDIA_IS_GFX |
4912                    GEN6_RP_ENABLE |
4913                    GEN6_RP_UP_BUSY_AVG |
4914                    GEN6_RP_DOWN_IDLE_AVG);
4915
4916         dev_priv->rps.power = new_power;
4917         dev_priv->rps.up_threshold = threshold_up;
4918         dev_priv->rps.down_threshold = threshold_down;
4919         dev_priv->rps.last_adj = 0;
4920 }
4921
4922 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4923 {
4924         u32 mask = 0;
4925
4926         if (val > dev_priv->rps.min_freq_softlimit)
4927                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4928         if (val < dev_priv->rps.max_freq_softlimit)
4929                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4930
4931         mask &= dev_priv->pm_rps_events;
4932
4933         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4934 }
4935
4936 /* gen6_set_rps is called to update the frequency request, but should also be
4937  * called when the range (min_delay and max_delay) is modified so that we can
4938  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4939 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4940 {
4941         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4942         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4943                 return;
4944
4945         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4946         WARN_ON(val > dev_priv->rps.max_freq);
4947         WARN_ON(val < dev_priv->rps.min_freq);
4948
4949         /* min/max delay may still have been modified so be sure to
4950          * write the limits value.
4951          */
4952         if (val != dev_priv->rps.cur_freq) {
4953                 gen6_set_rps_thresholds(dev_priv, val);
4954
4955                 if (IS_GEN9(dev_priv))
4956                         I915_WRITE(GEN6_RPNSWREQ,
4957                                    GEN9_FREQUENCY(val));
4958                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4959                         I915_WRITE(GEN6_RPNSWREQ,
4960                                    HSW_FREQUENCY(val));
4961                 else
4962                         I915_WRITE(GEN6_RPNSWREQ,
4963                                    GEN6_FREQUENCY(val) |
4964                                    GEN6_OFFSET(0) |
4965                                    GEN6_AGGRESSIVE_TURBO);
4966         }
4967
4968         /* Make sure we continue to get interrupts
4969          * until we hit the minimum or maximum frequencies.
4970          */
4971         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4972         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4973
4974         POSTING_READ(GEN6_RPNSWREQ);
4975
4976         dev_priv->rps.cur_freq = val;
4977         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4978 }
4979
4980 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4981 {
4982         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4983         WARN_ON(val > dev_priv->rps.max_freq);
4984         WARN_ON(val < dev_priv->rps.min_freq);
4985
4986         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4987                       "Odd GPU freq value\n"))
4988                 val &= ~1;
4989
4990         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4991
4992         if (val != dev_priv->rps.cur_freq) {
4993                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4994                 if (!IS_CHERRYVIEW(dev_priv))
4995                         gen6_set_rps_thresholds(dev_priv, val);
4996         }
4997
4998         dev_priv->rps.cur_freq = val;
4999         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
5000 }
5001
5002 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
5003  *
5004  * * If Gfx is Idle, then
5005  * 1. Forcewake Media well.
5006  * 2. Request idle freq.
5007  * 3. Release Forcewake of Media well.
5008 */
5009 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5010 {
5011         u32 val = dev_priv->rps.idle_freq;
5012
5013         if (dev_priv->rps.cur_freq <= val)
5014                 return;
5015
5016         /* Wake up the media well, as that takes a lot less
5017          * power than the Render well. */
5018         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
5019         valleyview_set_rps(dev_priv, val);
5020         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
5021 }
5022
5023 void gen6_rps_busy(struct drm_i915_private *dev_priv)
5024 {
5025         mutex_lock(&dev_priv->rps.hw_lock);
5026         if (dev_priv->rps.enabled) {
5027                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5028                         gen6_rps_reset_ei(dev_priv);
5029                 I915_WRITE(GEN6_PMINTRMSK,
5030                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
5031
5032                 gen6_enable_rps_interrupts(dev_priv);
5033
5034                 /* Ensure we start at the user's desired frequency */
5035                 intel_set_rps(dev_priv,
5036                               clamp(dev_priv->rps.cur_freq,
5037                                     dev_priv->rps.min_freq_softlimit,
5038                                     dev_priv->rps.max_freq_softlimit));
5039         }
5040         mutex_unlock(&dev_priv->rps.hw_lock);
5041 }
5042
5043 void gen6_rps_idle(struct drm_i915_private *dev_priv)
5044 {
5045         /* Flush our bottom-half so that it does not race with us
5046          * setting the idle frequency and so that it is bounded by
5047          * our rpm wakeref. And then disable the interrupts to stop any
5048          * futher RPS reclocking whilst we are asleep.
5049          */
5050         gen6_disable_rps_interrupts(dev_priv);
5051
5052         mutex_lock(&dev_priv->rps.hw_lock);
5053         if (dev_priv->rps.enabled) {
5054                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5055                         vlv_set_rps_idle(dev_priv);
5056                 else
5057                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
5058                 dev_priv->rps.last_adj = 0;
5059                 I915_WRITE(GEN6_PMINTRMSK,
5060                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
5061         }
5062         mutex_unlock(&dev_priv->rps.hw_lock);
5063
5064         spin_lock(&dev_priv->rps.client_lock);
5065         while (!list_empty(&dev_priv->rps.clients))
5066                 list_del_init(dev_priv->rps.clients.next);
5067         spin_unlock(&dev_priv->rps.client_lock);
5068 }
5069
5070 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5071                     struct intel_rps_client *rps,
5072                     unsigned long submitted)
5073 {
5074         /* This is intentionally racy! We peek at the state here, then
5075          * validate inside the RPS worker.
5076          */
5077         if (!(dev_priv->gt.awake &&
5078               dev_priv->rps.enabled &&
5079               dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5080                 return;
5081
5082         /* Force a RPS boost (and don't count it against the client) if
5083          * the GPU is severely congested.
5084          */
5085         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5086                 rps = NULL;
5087
5088         spin_lock(&dev_priv->rps.client_lock);
5089         if (rps == NULL || list_empty(&rps->link)) {
5090                 spin_lock_irq(&dev_priv->irq_lock);
5091                 if (dev_priv->rps.interrupts_enabled) {
5092                         dev_priv->rps.client_boost = true;
5093                         schedule_work(&dev_priv->rps.work);
5094                 }
5095                 spin_unlock_irq(&dev_priv->irq_lock);
5096
5097                 if (rps != NULL) {
5098                         list_add(&rps->link, &dev_priv->rps.clients);
5099                         rps->boosts++;
5100                 } else
5101                         dev_priv->rps.boosts++;
5102         }
5103         spin_unlock(&dev_priv->rps.client_lock);
5104 }
5105
5106 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5107 {
5108         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5109                 valleyview_set_rps(dev_priv, val);
5110         else
5111                 gen6_set_rps(dev_priv, val);
5112 }
5113
5114 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5115 {
5116         I915_WRITE(GEN6_RC_CONTROL, 0);
5117         I915_WRITE(GEN9_PG_ENABLE, 0);
5118 }
5119
5120 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5121 {
5122         I915_WRITE(GEN6_RP_CONTROL, 0);
5123 }
5124
5125 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5126 {
5127         I915_WRITE(GEN6_RC_CONTROL, 0);
5128         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5129         I915_WRITE(GEN6_RP_CONTROL, 0);
5130 }
5131
5132 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5133 {
5134         I915_WRITE(GEN6_RC_CONTROL, 0);
5135 }
5136
5137 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5138 {
5139         /* we're doing forcewake before Disabling RC6,
5140          * This what the BIOS expects when going into suspend */
5141         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5142
5143         I915_WRITE(GEN6_RC_CONTROL, 0);
5144
5145         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5146 }
5147
5148 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5149 {
5150         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5151                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5152                         mode = GEN6_RC_CTL_RC6_ENABLE;
5153                 else
5154                         mode = 0;
5155         }
5156         if (HAS_RC6p(dev_priv))
5157                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5158                                  "RC6 %s RC6p %s RC6pp %s\n",
5159                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5160                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5161                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5162
5163         else
5164                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5165                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5166 }
5167
5168 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5169 {
5170         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5171         bool enable_rc6 = true;
5172         unsigned long rc6_ctx_base;
5173         u32 rc_ctl;
5174         int rc_sw_target;
5175
5176         rc_ctl = I915_READ(GEN6_RC_CONTROL);
5177         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5178                        RC_SW_TARGET_STATE_SHIFT;
5179         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5180                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5181                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5182                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5183                          rc_sw_target);
5184
5185         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5186                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5187                 enable_rc6 = false;
5188         }
5189
5190         /*
5191          * The exact context size is not known for BXT, so assume a page size
5192          * for this check.
5193          */
5194         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5195         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5196               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5197                                         ggtt->stolen_reserved_size))) {
5198                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5199                 enable_rc6 = false;
5200         }
5201
5202         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5203               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5204               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5205               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5206                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5207                 enable_rc6 = false;
5208         }
5209
5210         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5211             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5212             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5213                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5214                 enable_rc6 = false;
5215         }
5216
5217         if (!I915_READ(GEN6_GFXPAUSE)) {
5218                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5219                 enable_rc6 = false;
5220         }
5221
5222         if (!I915_READ(GEN8_MISC_CTRL0)) {
5223                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5224                 enable_rc6 = false;
5225         }
5226
5227         return enable_rc6;
5228 }
5229
5230 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5231 {
5232         /* No RC6 before Ironlake and code is gone for ilk. */
5233         if (INTEL_INFO(dev_priv)->gen < 6)
5234                 return 0;
5235
5236         if (!enable_rc6)
5237                 return 0;
5238
5239         if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5240                 DRM_INFO("RC6 disabled by BIOS\n");
5241                 return 0;
5242         }
5243
5244         /* Respect the kernel parameter if it is set */
5245         if (enable_rc6 >= 0) {
5246                 int mask;
5247
5248                 if (HAS_RC6p(dev_priv))
5249                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5250                                INTEL_RC6pp_ENABLE;
5251                 else
5252                         mask = INTEL_RC6_ENABLE;
5253
5254                 if ((enable_rc6 & mask) != enable_rc6)
5255                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5256                                          "(requested %d, valid %d)\n",
5257                                          enable_rc6 & mask, enable_rc6, mask);
5258
5259                 return enable_rc6 & mask;
5260         }
5261
5262         if (IS_IVYBRIDGE(dev_priv))
5263                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5264
5265         return INTEL_RC6_ENABLE;
5266 }
5267
5268 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5269 {
5270         /* All of these values are in units of 50MHz */
5271
5272         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5273         if (IS_BROXTON(dev_priv)) {
5274                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5275                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5276                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5277                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
5278         } else {
5279                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5280                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
5281                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5282                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5283         }
5284         /* hw_max = RP0 until we check for overclocking */
5285         dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5286
5287         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5288         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5289             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5290                 u32 ddcc_status = 0;
5291
5292                 if (sandybridge_pcode_read(dev_priv,
5293                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5294                                            &ddcc_status) == 0)
5295                         dev_priv->rps.efficient_freq =
5296                                 clamp_t(u8,
5297                                         ((ddcc_status >> 8) & 0xff),
5298                                         dev_priv->rps.min_freq,
5299                                         dev_priv->rps.max_freq);
5300         }
5301
5302         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5303                 /* Store the frequency values in 16.66 MHZ units, which is
5304                  * the natural hardware unit for SKL
5305                  */
5306                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5307                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5308                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5309                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5310                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5311         }
5312 }
5313
5314 static void reset_rps(struct drm_i915_private *dev_priv,
5315                       void (*set)(struct drm_i915_private *, u8))
5316 {
5317         u8 freq = dev_priv->rps.cur_freq;
5318
5319         /* force a reset */
5320         dev_priv->rps.power = -1;
5321         dev_priv->rps.cur_freq = -1;
5322
5323         set(dev_priv, freq);
5324 }
5325
5326 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5327 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5328 {
5329         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5330
5331         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5332         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5333                 /*
5334                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
5335                  * clear out the Control register just to avoid inconsitency
5336                  * with debugfs interface, which will show  Turbo as enabled
5337                  * only and that is not expected by the User after adding the
5338                  * WaGsvDisableTurbo. Apart from this there is no problem even
5339                  * if the Turbo is left enabled in the Control register, as the
5340                  * Up/Down interrupts would remain masked.
5341                  */
5342                 gen9_disable_rps(dev_priv);
5343                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5344                 return;
5345         }
5346
5347         /* Program defaults and thresholds for RPS*/
5348         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5349                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5350
5351         /* 1 second timeout*/
5352         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5353                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5354
5355         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5356
5357         /* Leaning on the below call to gen6_set_rps to program/setup the
5358          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5359          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5360         reset_rps(dev_priv, gen6_set_rps);
5361
5362         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5363 }
5364
5365 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5366 {
5367         struct intel_engine_cs *engine;
5368         enum intel_engine_id id;
5369         uint32_t rc6_mask = 0;
5370
5371         /* 1a: Software RC state - RC0 */
5372         I915_WRITE(GEN6_RC_STATE, 0);
5373
5374         /* 1b: Get forcewake during program sequence. Although the driver
5375          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5376         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5377
5378         /* 2a: Disable RC states. */
5379         I915_WRITE(GEN6_RC_CONTROL, 0);
5380
5381         /* 2b: Program RC6 thresholds.*/
5382
5383         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5384         if (IS_SKYLAKE(dev_priv))
5385                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5386         else
5387                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5388         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5389         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5390         for_each_engine(engine, dev_priv, id)
5391                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5392
5393         if (HAS_GUC(dev_priv))
5394                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5395
5396         I915_WRITE(GEN6_RC_SLEEP, 0);
5397
5398         /* 2c: Program Coarse Power Gating Policies. */
5399         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5400         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5401
5402         /* 3a: Enable RC6 */
5403         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5404                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5405         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5406         /* WaRsUseTimeoutMode:bxt */
5407         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5408                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5409                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5410                            GEN7_RC_CTL_TO_MODE |
5411                            rc6_mask);
5412         } else {
5413                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5414                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5415                            GEN6_RC_CTL_EI_MODE(1) |
5416                            rc6_mask);
5417         }
5418
5419         /*
5420          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5421          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5422          */
5423         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5424                 I915_WRITE(GEN9_PG_ENABLE, 0);
5425         else
5426                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5427                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5428
5429         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5430 }
5431
5432 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5433 {
5434         struct intel_engine_cs *engine;
5435         enum intel_engine_id id;
5436         uint32_t rc6_mask = 0;
5437
5438         /* 1a: Software RC state - RC0 */
5439         I915_WRITE(GEN6_RC_STATE, 0);
5440
5441         /* 1c & 1d: Get forcewake during program sequence. Although the driver
5442          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5443         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5444
5445         /* 2a: Disable RC states. */
5446         I915_WRITE(GEN6_RC_CONTROL, 0);
5447
5448         /* 2b: Program RC6 thresholds.*/
5449         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5450         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5451         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5452         for_each_engine(engine, dev_priv, id)
5453                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5454         I915_WRITE(GEN6_RC_SLEEP, 0);
5455         if (IS_BROADWELL(dev_priv))
5456                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5457         else
5458                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5459
5460         /* 3: Enable RC6 */
5461         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5462                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5463         intel_print_rc6_info(dev_priv, rc6_mask);
5464         if (IS_BROADWELL(dev_priv))
5465                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5466                                 GEN7_RC_CTL_TO_MODE |
5467                                 rc6_mask);
5468         else
5469                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5470                                 GEN6_RC_CTL_EI_MODE(1) |
5471                                 rc6_mask);
5472
5473         /* 4 Program defaults and thresholds for RPS*/
5474         I915_WRITE(GEN6_RPNSWREQ,
5475                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5476         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5477                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5478         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5479         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5480
5481         /* Docs recommend 900MHz, and 300 MHz respectively */
5482         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5483                    dev_priv->rps.max_freq_softlimit << 24 |
5484                    dev_priv->rps.min_freq_softlimit << 16);
5485
5486         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5487         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5488         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5489         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5490
5491         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5492
5493         /* 5: Enable RPS */
5494         I915_WRITE(GEN6_RP_CONTROL,
5495                    GEN6_RP_MEDIA_TURBO |
5496                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5497                    GEN6_RP_MEDIA_IS_GFX |
5498                    GEN6_RP_ENABLE |
5499                    GEN6_RP_UP_BUSY_AVG |
5500                    GEN6_RP_DOWN_IDLE_AVG);
5501
5502         /* 6: Ring frequency + overclocking (our driver does this later */
5503
5504         reset_rps(dev_priv, gen6_set_rps);
5505
5506         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5507 }
5508
5509 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5510 {
5511         struct intel_engine_cs *engine;
5512         enum intel_engine_id id;
5513         u32 rc6vids, rc6_mask = 0;
5514         u32 gtfifodbg;
5515         int rc6_mode;
5516         int ret;
5517
5518         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5519
5520         /* Here begins a magic sequence of register writes to enable
5521          * auto-downclocking.
5522          *
5523          * Perhaps there might be some value in exposing these to
5524          * userspace...
5525          */
5526         I915_WRITE(GEN6_RC_STATE, 0);
5527
5528         /* Clear the DBG now so we don't confuse earlier errors */
5529         gtfifodbg = I915_READ(GTFIFODBG);
5530         if (gtfifodbg) {
5531                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5532                 I915_WRITE(GTFIFODBG, gtfifodbg);
5533         }
5534
5535         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5536
5537         /* disable the counters and set deterministic thresholds */
5538         I915_WRITE(GEN6_RC_CONTROL, 0);
5539
5540         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5541         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5542         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5543         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5544         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5545
5546         for_each_engine(engine, dev_priv, id)
5547                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5548
5549         I915_WRITE(GEN6_RC_SLEEP, 0);
5550         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5551         if (IS_IVYBRIDGE(dev_priv))
5552                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5553         else
5554                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5555         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5556         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5557
5558         /* Check if we are enabling RC6 */
5559         rc6_mode = intel_enable_rc6();
5560         if (rc6_mode & INTEL_RC6_ENABLE)
5561                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5562
5563         /* We don't use those on Haswell */
5564         if (!IS_HASWELL(dev_priv)) {
5565                 if (rc6_mode & INTEL_RC6p_ENABLE)
5566                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5567
5568                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5569                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5570         }
5571
5572         intel_print_rc6_info(dev_priv, rc6_mask);
5573
5574         I915_WRITE(GEN6_RC_CONTROL,
5575                    rc6_mask |
5576                    GEN6_RC_CTL_EI_MODE(1) |
5577                    GEN6_RC_CTL_HW_ENABLE);
5578
5579         /* Power down if completely idle for over 50ms */
5580         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5581         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5582
5583         reset_rps(dev_priv, gen6_set_rps);
5584
5585         rc6vids = 0;
5586         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5587         if (IS_GEN6(dev_priv) && ret) {
5588                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5589         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5590                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5591                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5592                 rc6vids &= 0xffff00;
5593                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5594                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5595                 if (ret)
5596                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5597         }
5598
5599         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5600 }
5601
5602 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5603 {
5604         int min_freq = 15;
5605         unsigned int gpu_freq;
5606         unsigned int max_ia_freq, min_ring_freq;
5607         unsigned int max_gpu_freq, min_gpu_freq;
5608         int scaling_factor = 180;
5609         struct cpufreq_policy *policy;
5610
5611         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5612
5613         policy = cpufreq_cpu_get(0);
5614         if (policy) {
5615                 max_ia_freq = policy->cpuinfo.max_freq;
5616                 cpufreq_cpu_put(policy);
5617         } else {
5618                 /*
5619                  * Default to measured freq if none found, PCU will ensure we
5620                  * don't go over
5621                  */
5622                 max_ia_freq = tsc_khz;
5623         }
5624
5625         /* Convert from kHz to MHz */
5626         max_ia_freq /= 1000;
5627
5628         min_ring_freq = I915_READ(DCLK) & 0xf;
5629         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5630         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5631
5632         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5633                 /* Convert GT frequency to 50 HZ units */
5634                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5635                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5636         } else {
5637                 min_gpu_freq = dev_priv->rps.min_freq;
5638                 max_gpu_freq = dev_priv->rps.max_freq;
5639         }
5640
5641         /*
5642          * For each potential GPU frequency, load a ring frequency we'd like
5643          * to use for memory access.  We do this by specifying the IA frequency
5644          * the PCU should use as a reference to determine the ring frequency.
5645          */
5646         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5647                 int diff = max_gpu_freq - gpu_freq;
5648                 unsigned int ia_freq = 0, ring_freq = 0;
5649
5650                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5651                         /*
5652                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5653                          * No floor required for ring frequency on SKL.
5654                          */
5655                         ring_freq = gpu_freq;
5656                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5657                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5658                         ring_freq = max(min_ring_freq, gpu_freq);
5659                 } else if (IS_HASWELL(dev_priv)) {
5660                         ring_freq = mult_frac(gpu_freq, 5, 4);
5661                         ring_freq = max(min_ring_freq, ring_freq);
5662                         /* leave ia_freq as the default, chosen by cpufreq */
5663                 } else {
5664                         /* On older processors, there is no separate ring
5665                          * clock domain, so in order to boost the bandwidth
5666                          * of the ring, we need to upclock the CPU (ia_freq).
5667                          *
5668                          * For GPU frequencies less than 750MHz,
5669                          * just use the lowest ring freq.
5670                          */
5671                         if (gpu_freq < min_freq)
5672                                 ia_freq = 800;
5673                         else
5674                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5675                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5676                 }
5677
5678                 sandybridge_pcode_write(dev_priv,
5679                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5680                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5681                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5682                                         gpu_freq);
5683         }
5684 }
5685
5686 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5687 {
5688         u32 val, rp0;
5689
5690         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5691
5692         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5693         case 8:
5694                 /* (2 * 4) config */
5695                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5696                 break;
5697         case 12:
5698                 /* (2 * 6) config */
5699                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5700                 break;
5701         case 16:
5702                 /* (2 * 8) config */
5703         default:
5704                 /* Setting (2 * 8) Min RP0 for any other combination */
5705                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5706                 break;
5707         }
5708
5709         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5710
5711         return rp0;
5712 }
5713
5714 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5715 {
5716         u32 val, rpe;
5717
5718         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5719         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5720
5721         return rpe;
5722 }
5723
5724 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5725 {
5726         u32 val, rp1;
5727
5728         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5729         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5730
5731         return rp1;
5732 }
5733
5734 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5735 {
5736         u32 val, rp1;
5737
5738         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5739
5740         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5741
5742         return rp1;
5743 }
5744
5745 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5746 {
5747         u32 val, rp0;
5748
5749         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5750
5751         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5752         /* Clamp to max */
5753         rp0 = min_t(u32, rp0, 0xea);
5754
5755         return rp0;
5756 }
5757
5758 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5759 {
5760         u32 val, rpe;
5761
5762         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5763         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5764         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5765         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5766
5767         return rpe;
5768 }
5769
5770 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5771 {
5772         u32 val;
5773
5774         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5775         /*
5776          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5777          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5778          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5779          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5780          * to make sure it matches what Punit accepts.
5781          */
5782         return max_t(u32, val, 0xc0);
5783 }
5784
5785 /* Check that the pctx buffer wasn't move under us. */
5786 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5787 {
5788         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5789
5790         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5791                              dev_priv->vlv_pctx->stolen->start);
5792 }
5793
5794
5795 /* Check that the pcbr address is not empty. */
5796 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5797 {
5798         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5799
5800         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5801 }
5802
5803 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5804 {
5805         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5806         unsigned long pctx_paddr, paddr;
5807         u32 pcbr;
5808         int pctx_size = 32*1024;
5809
5810         pcbr = I915_READ(VLV_PCBR);
5811         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5812                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5813                 paddr = (dev_priv->mm.stolen_base +
5814                          (ggtt->stolen_size - pctx_size));
5815
5816                 pctx_paddr = (paddr & (~4095));
5817                 I915_WRITE(VLV_PCBR, pctx_paddr);
5818         }
5819
5820         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5821 }
5822
5823 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5824 {
5825         struct drm_i915_gem_object *pctx;
5826         unsigned long pctx_paddr;
5827         u32 pcbr;
5828         int pctx_size = 24*1024;
5829
5830         pcbr = I915_READ(VLV_PCBR);
5831         if (pcbr) {
5832                 /* BIOS set it up already, grab the pre-alloc'd space */
5833                 int pcbr_offset;
5834
5835                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5836                 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
5837                                                                       pcbr_offset,
5838                                                                       I915_GTT_OFFSET_NONE,
5839                                                                       pctx_size);
5840                 goto out;
5841         }
5842
5843         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5844
5845         /*
5846          * From the Gunit register HAS:
5847          * The Gfx driver is expected to program this register and ensure
5848          * proper allocation within Gfx stolen memory.  For example, this
5849          * register should be programmed such than the PCBR range does not
5850          * overlap with other ranges, such as the frame buffer, protected
5851          * memory, or any other relevant ranges.
5852          */
5853         pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
5854         if (!pctx) {
5855                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5856                 goto out;
5857         }
5858
5859         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5860         I915_WRITE(VLV_PCBR, pctx_paddr);
5861
5862 out:
5863         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5864         dev_priv->vlv_pctx = pctx;
5865 }
5866
5867 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5868 {
5869         if (WARN_ON(!dev_priv->vlv_pctx))
5870                 return;
5871
5872         i915_gem_object_put(dev_priv->vlv_pctx);
5873         dev_priv->vlv_pctx = NULL;
5874 }
5875
5876 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5877 {
5878         dev_priv->rps.gpll_ref_freq =
5879                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5880                                   CCK_GPLL_CLOCK_CONTROL,
5881                                   dev_priv->czclk_freq);
5882
5883         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5884                          dev_priv->rps.gpll_ref_freq);
5885 }
5886
5887 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5888 {
5889         u32 val;
5890
5891         valleyview_setup_pctx(dev_priv);
5892
5893         vlv_init_gpll_ref_freq(dev_priv);
5894
5895         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5896         switch ((val >> 6) & 3) {
5897         case 0:
5898         case 1:
5899                 dev_priv->mem_freq = 800;
5900                 break;
5901         case 2:
5902                 dev_priv->mem_freq = 1066;
5903                 break;
5904         case 3:
5905                 dev_priv->mem_freq = 1333;
5906                 break;
5907         }
5908         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5909
5910         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5911         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5912         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5913                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5914                          dev_priv->rps.max_freq);
5915
5916         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5917         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5918                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5919                          dev_priv->rps.efficient_freq);
5920
5921         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5922         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5923                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5924                          dev_priv->rps.rp1_freq);
5925
5926         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5927         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5928                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5929                          dev_priv->rps.min_freq);
5930 }
5931
5932 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5933 {
5934         u32 val;
5935
5936         cherryview_setup_pctx(dev_priv);
5937
5938         vlv_init_gpll_ref_freq(dev_priv);
5939
5940         mutex_lock(&dev_priv->sb_lock);
5941         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5942         mutex_unlock(&dev_priv->sb_lock);
5943
5944         switch ((val >> 2) & 0x7) {
5945         case 3:
5946                 dev_priv->mem_freq = 2000;
5947                 break;
5948         default:
5949                 dev_priv->mem_freq = 1600;
5950                 break;
5951         }
5952         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5953
5954         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5955         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5956         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5957                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5958                          dev_priv->rps.max_freq);
5959
5960         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5961         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5962                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5963                          dev_priv->rps.efficient_freq);
5964
5965         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5966         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5967                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5968                          dev_priv->rps.rp1_freq);
5969
5970         /* PUnit validated range is only [RPe, RP0] */
5971         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5972         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5973                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5974                          dev_priv->rps.min_freq);
5975
5976         WARN_ONCE((dev_priv->rps.max_freq |
5977                    dev_priv->rps.efficient_freq |
5978                    dev_priv->rps.rp1_freq |
5979                    dev_priv->rps.min_freq) & 1,
5980                   "Odd GPU freq values\n");
5981 }
5982
5983 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5984 {
5985         valleyview_cleanup_pctx(dev_priv);
5986 }
5987
5988 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5989 {
5990         struct intel_engine_cs *engine;
5991         enum intel_engine_id id;
5992         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5993
5994         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5995
5996         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5997                                              GT_FIFO_FREE_ENTRIES_CHV);
5998         if (gtfifodbg) {
5999                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6000                                  gtfifodbg);
6001                 I915_WRITE(GTFIFODBG, gtfifodbg);
6002         }
6003
6004         cherryview_check_pctx(dev_priv);
6005
6006         /* 1a & 1b: Get forcewake during program sequence. Although the driver
6007          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6008         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6009
6010         /*  Disable RC states. */
6011         I915_WRITE(GEN6_RC_CONTROL, 0);
6012
6013         /* 2a: Program RC6 thresholds.*/
6014         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6015         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6016         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6017
6018         for_each_engine(engine, dev_priv, id)
6019                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6020         I915_WRITE(GEN6_RC_SLEEP, 0);
6021
6022         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6023         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
6024
6025         /* allows RC6 residency counter to work */
6026         I915_WRITE(VLV_COUNTER_CONTROL,
6027                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6028                                       VLV_MEDIA_RC6_COUNT_EN |
6029                                       VLV_RENDER_RC6_COUNT_EN));
6030
6031         /* For now we assume BIOS is allocating and populating the PCBR  */
6032         pcbr = I915_READ(VLV_PCBR);
6033
6034         /* 3: Enable RC6 */
6035         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6036             (pcbr >> VLV_PCBR_ADDR_SHIFT))
6037                 rc6_mode = GEN7_RC_CTL_TO_MODE;
6038
6039         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6040
6041         /* 4 Program defaults and thresholds for RPS*/
6042         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6043         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6044         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6045         I915_WRITE(GEN6_RP_UP_EI, 66000);
6046         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6047
6048         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6049
6050         /* 5: Enable RPS */
6051         I915_WRITE(GEN6_RP_CONTROL,
6052                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6053                    GEN6_RP_MEDIA_IS_GFX |
6054                    GEN6_RP_ENABLE |
6055                    GEN6_RP_UP_BUSY_AVG |
6056                    GEN6_RP_DOWN_IDLE_AVG);
6057
6058         /* Setting Fixed Bias */
6059         val = VLV_OVERRIDE_EN |
6060                   VLV_SOC_TDP_EN |
6061                   CHV_BIAS_CPU_50_SOC_50;
6062         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6063
6064         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6065
6066         /* RPS code assumes GPLL is used */
6067         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6068
6069         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6070         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6071
6072         reset_rps(dev_priv, valleyview_set_rps);
6073
6074         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6075 }
6076
6077 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6078 {
6079         struct intel_engine_cs *engine;
6080         enum intel_engine_id id;
6081         u32 gtfifodbg, val, rc6_mode = 0;
6082
6083         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6084
6085         valleyview_check_pctx(dev_priv);
6086
6087         gtfifodbg = I915_READ(GTFIFODBG);
6088         if (gtfifodbg) {
6089                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6090                                  gtfifodbg);
6091                 I915_WRITE(GTFIFODBG, gtfifodbg);
6092         }
6093
6094         /* If VLV, Forcewake all wells, else re-direct to regular path */
6095         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6096
6097         /*  Disable RC states. */
6098         I915_WRITE(GEN6_RC_CONTROL, 0);
6099
6100         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6101         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6102         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6103         I915_WRITE(GEN6_RP_UP_EI, 66000);
6104         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6105
6106         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6107
6108         I915_WRITE(GEN6_RP_CONTROL,
6109                    GEN6_RP_MEDIA_TURBO |
6110                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6111                    GEN6_RP_MEDIA_IS_GFX |
6112                    GEN6_RP_ENABLE |
6113                    GEN6_RP_UP_BUSY_AVG |
6114                    GEN6_RP_DOWN_IDLE_CONT);
6115
6116         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6117         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6118         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6119
6120         for_each_engine(engine, dev_priv, id)
6121                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6122
6123         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6124
6125         /* allows RC6 residency counter to work */
6126         I915_WRITE(VLV_COUNTER_CONTROL,
6127                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6128                                       VLV_RENDER_RC0_COUNT_EN |
6129                                       VLV_MEDIA_RC6_COUNT_EN |
6130                                       VLV_RENDER_RC6_COUNT_EN));
6131
6132         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6133                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6134
6135         intel_print_rc6_info(dev_priv, rc6_mode);
6136
6137         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6138
6139         /* Setting Fixed Bias */
6140         val = VLV_OVERRIDE_EN |
6141                   VLV_SOC_TDP_EN |
6142                   VLV_BIAS_CPU_125_SOC_875;
6143         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6144
6145         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6146
6147         /* RPS code assumes GPLL is used */
6148         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6149
6150         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6151         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6152
6153         reset_rps(dev_priv, valleyview_set_rps);
6154
6155         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6156 }
6157
6158 static unsigned long intel_pxfreq(u32 vidfreq)
6159 {
6160         unsigned long freq;
6161         int div = (vidfreq & 0x3f0000) >> 16;
6162         int post = (vidfreq & 0x3000) >> 12;
6163         int pre = (vidfreq & 0x7);
6164
6165         if (!pre)
6166                 return 0;
6167
6168         freq = ((div * 133333) / ((1<<post) * pre));
6169
6170         return freq;
6171 }
6172
6173 static const struct cparams {
6174         u16 i;
6175         u16 t;
6176         u16 m;
6177         u16 c;
6178 } cparams[] = {
6179         { 1, 1333, 301, 28664 },
6180         { 1, 1066, 294, 24460 },
6181         { 1, 800, 294, 25192 },
6182         { 0, 1333, 276, 27605 },
6183         { 0, 1066, 276, 27605 },
6184         { 0, 800, 231, 23784 },
6185 };
6186
6187 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6188 {
6189         u64 total_count, diff, ret;
6190         u32 count1, count2, count3, m = 0, c = 0;
6191         unsigned long now = jiffies_to_msecs(jiffies), diff1;
6192         int i;
6193
6194         assert_spin_locked(&mchdev_lock);
6195
6196         diff1 = now - dev_priv->ips.last_time1;
6197
6198         /* Prevent division-by-zero if we are asking too fast.
6199          * Also, we don't get interesting results if we are polling
6200          * faster than once in 10ms, so just return the saved value
6201          * in such cases.
6202          */
6203         if (diff1 <= 10)
6204                 return dev_priv->ips.chipset_power;
6205
6206         count1 = I915_READ(DMIEC);
6207         count2 = I915_READ(DDREC);
6208         count3 = I915_READ(CSIEC);
6209
6210         total_count = count1 + count2 + count3;
6211
6212         /* FIXME: handle per-counter overflow */
6213         if (total_count < dev_priv->ips.last_count1) {
6214                 diff = ~0UL - dev_priv->ips.last_count1;
6215                 diff += total_count;
6216         } else {
6217                 diff = total_count - dev_priv->ips.last_count1;
6218         }
6219
6220         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6221                 if (cparams[i].i == dev_priv->ips.c_m &&
6222                     cparams[i].t == dev_priv->ips.r_t) {
6223                         m = cparams[i].m;
6224                         c = cparams[i].c;
6225                         break;
6226                 }
6227         }
6228
6229         diff = div_u64(diff, diff1);
6230         ret = ((m * diff) + c);
6231         ret = div_u64(ret, 10);
6232
6233         dev_priv->ips.last_count1 = total_count;
6234         dev_priv->ips.last_time1 = now;
6235
6236         dev_priv->ips.chipset_power = ret;
6237
6238         return ret;
6239 }
6240
6241 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6242 {
6243         unsigned long val;
6244
6245         if (INTEL_INFO(dev_priv)->gen != 5)
6246                 return 0;
6247
6248         spin_lock_irq(&mchdev_lock);
6249
6250         val = __i915_chipset_val(dev_priv);
6251
6252         spin_unlock_irq(&mchdev_lock);
6253
6254         return val;
6255 }
6256
6257 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6258 {
6259         unsigned long m, x, b;
6260         u32 tsfs;
6261
6262         tsfs = I915_READ(TSFS);
6263
6264         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6265         x = I915_READ8(TR1);
6266
6267         b = tsfs & TSFS_INTR_MASK;
6268
6269         return ((m * x) / 127) - b;
6270 }
6271
6272 static int _pxvid_to_vd(u8 pxvid)
6273 {
6274         if (pxvid == 0)
6275                 return 0;
6276
6277         if (pxvid >= 8 && pxvid < 31)
6278                 pxvid = 31;
6279
6280         return (pxvid + 2) * 125;
6281 }
6282
6283 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6284 {
6285         const int vd = _pxvid_to_vd(pxvid);
6286         const int vm = vd - 1125;
6287
6288         if (INTEL_INFO(dev_priv)->is_mobile)
6289                 return vm > 0 ? vm : 0;
6290
6291         return vd;
6292 }
6293
6294 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6295 {
6296         u64 now, diff, diffms;
6297         u32 count;
6298
6299         assert_spin_locked(&mchdev_lock);
6300
6301         now = ktime_get_raw_ns();
6302         diffms = now - dev_priv->ips.last_time2;
6303         do_div(diffms, NSEC_PER_MSEC);
6304
6305         /* Don't divide by 0 */
6306         if (!diffms)
6307                 return;
6308
6309         count = I915_READ(GFXEC);
6310
6311         if (count < dev_priv->ips.last_count2) {
6312                 diff = ~0UL - dev_priv->ips.last_count2;
6313                 diff += count;
6314         } else {
6315                 diff = count - dev_priv->ips.last_count2;
6316         }
6317
6318         dev_priv->ips.last_count2 = count;
6319         dev_priv->ips.last_time2 = now;
6320
6321         /* More magic constants... */
6322         diff = diff * 1181;
6323         diff = div_u64(diff, diffms * 10);
6324         dev_priv->ips.gfx_power = diff;
6325 }
6326
6327 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6328 {
6329         if (INTEL_INFO(dev_priv)->gen != 5)
6330                 return;
6331
6332         spin_lock_irq(&mchdev_lock);
6333
6334         __i915_update_gfx_val(dev_priv);
6335
6336         spin_unlock_irq(&mchdev_lock);
6337 }
6338
6339 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6340 {
6341         unsigned long t, corr, state1, corr2, state2;
6342         u32 pxvid, ext_v;
6343
6344         assert_spin_locked(&mchdev_lock);
6345
6346         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6347         pxvid = (pxvid >> 24) & 0x7f;
6348         ext_v = pvid_to_extvid(dev_priv, pxvid);
6349
6350         state1 = ext_v;
6351
6352         t = i915_mch_val(dev_priv);
6353
6354         /* Revel in the empirically derived constants */
6355
6356         /* Correction factor in 1/100000 units */
6357         if (t > 80)
6358                 corr = ((t * 2349) + 135940);
6359         else if (t >= 50)
6360                 corr = ((t * 964) + 29317);
6361         else /* < 50 */
6362                 corr = ((t * 301) + 1004);
6363
6364         corr = corr * ((150142 * state1) / 10000 - 78642);
6365         corr /= 100000;
6366         corr2 = (corr * dev_priv->ips.corr);
6367
6368         state2 = (corr2 * state1) / 10000;
6369         state2 /= 100; /* convert to mW */
6370
6371         __i915_update_gfx_val(dev_priv);
6372
6373         return dev_priv->ips.gfx_power + state2;
6374 }
6375
6376 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6377 {
6378         unsigned long val;
6379
6380         if (INTEL_INFO(dev_priv)->gen != 5)
6381                 return 0;
6382
6383         spin_lock_irq(&mchdev_lock);
6384
6385         val = __i915_gfx_val(dev_priv);
6386
6387         spin_unlock_irq(&mchdev_lock);
6388
6389         return val;
6390 }
6391
6392 /**
6393  * i915_read_mch_val - return value for IPS use
6394  *
6395  * Calculate and return a value for the IPS driver to use when deciding whether
6396  * we have thermal and power headroom to increase CPU or GPU power budget.
6397  */
6398 unsigned long i915_read_mch_val(void)
6399 {
6400         struct drm_i915_private *dev_priv;
6401         unsigned long chipset_val, graphics_val, ret = 0;
6402
6403         spin_lock_irq(&mchdev_lock);
6404         if (!i915_mch_dev)
6405                 goto out_unlock;
6406         dev_priv = i915_mch_dev;
6407
6408         chipset_val = __i915_chipset_val(dev_priv);
6409         graphics_val = __i915_gfx_val(dev_priv);
6410
6411         ret = chipset_val + graphics_val;
6412
6413 out_unlock:
6414         spin_unlock_irq(&mchdev_lock);
6415
6416         return ret;
6417 }
6418 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6419
6420 /**
6421  * i915_gpu_raise - raise GPU frequency limit
6422  *
6423  * Raise the limit; IPS indicates we have thermal headroom.
6424  */
6425 bool i915_gpu_raise(void)
6426 {
6427         struct drm_i915_private *dev_priv;
6428         bool ret = true;
6429
6430         spin_lock_irq(&mchdev_lock);
6431         if (!i915_mch_dev) {
6432                 ret = false;
6433                 goto out_unlock;
6434         }
6435         dev_priv = i915_mch_dev;
6436
6437         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6438                 dev_priv->ips.max_delay--;
6439
6440 out_unlock:
6441         spin_unlock_irq(&mchdev_lock);
6442
6443         return ret;
6444 }
6445 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6446
6447 /**
6448  * i915_gpu_lower - lower GPU frequency limit
6449  *
6450  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6451  * frequency maximum.
6452  */
6453 bool i915_gpu_lower(void)
6454 {
6455         struct drm_i915_private *dev_priv;
6456         bool ret = true;
6457
6458         spin_lock_irq(&mchdev_lock);
6459         if (!i915_mch_dev) {
6460                 ret = false;
6461                 goto out_unlock;
6462         }
6463         dev_priv = i915_mch_dev;
6464
6465         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6466                 dev_priv->ips.max_delay++;
6467
6468 out_unlock:
6469         spin_unlock_irq(&mchdev_lock);
6470
6471         return ret;
6472 }
6473 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6474
6475 /**
6476  * i915_gpu_busy - indicate GPU business to IPS
6477  *
6478  * Tell the IPS driver whether or not the GPU is busy.
6479  */
6480 bool i915_gpu_busy(void)
6481 {
6482         bool ret = false;
6483
6484         spin_lock_irq(&mchdev_lock);
6485         if (i915_mch_dev)
6486                 ret = i915_mch_dev->gt.awake;
6487         spin_unlock_irq(&mchdev_lock);
6488
6489         return ret;
6490 }
6491 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6492
6493 /**
6494  * i915_gpu_turbo_disable - disable graphics turbo
6495  *
6496  * Disable graphics turbo by resetting the max frequency and setting the
6497  * current frequency to the default.
6498  */
6499 bool i915_gpu_turbo_disable(void)
6500 {
6501         struct drm_i915_private *dev_priv;
6502         bool ret = true;
6503
6504         spin_lock_irq(&mchdev_lock);
6505         if (!i915_mch_dev) {
6506                 ret = false;
6507                 goto out_unlock;
6508         }
6509         dev_priv = i915_mch_dev;
6510
6511         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6512
6513         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6514                 ret = false;
6515
6516 out_unlock:
6517         spin_unlock_irq(&mchdev_lock);
6518
6519         return ret;
6520 }
6521 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6522
6523 /**
6524  * Tells the intel_ips driver that the i915 driver is now loaded, if
6525  * IPS got loaded first.
6526  *
6527  * This awkward dance is so that neither module has to depend on the
6528  * other in order for IPS to do the appropriate communication of
6529  * GPU turbo limits to i915.
6530  */
6531 static void
6532 ips_ping_for_i915_load(void)
6533 {
6534         void (*link)(void);
6535
6536         link = symbol_get(ips_link_to_i915_driver);
6537         if (link) {
6538                 link();
6539                 symbol_put(ips_link_to_i915_driver);
6540         }
6541 }
6542
6543 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6544 {
6545         /* We only register the i915 ips part with intel-ips once everything is
6546          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6547         spin_lock_irq(&mchdev_lock);
6548         i915_mch_dev = dev_priv;
6549         spin_unlock_irq(&mchdev_lock);
6550
6551         ips_ping_for_i915_load();
6552 }
6553
6554 void intel_gpu_ips_teardown(void)
6555 {
6556         spin_lock_irq(&mchdev_lock);
6557         i915_mch_dev = NULL;
6558         spin_unlock_irq(&mchdev_lock);
6559 }
6560
6561 static void intel_init_emon(struct drm_i915_private *dev_priv)
6562 {
6563         u32 lcfuse;
6564         u8 pxw[16];
6565         int i;
6566
6567         /* Disable to program */
6568         I915_WRITE(ECR, 0);
6569         POSTING_READ(ECR);
6570
6571         /* Program energy weights for various events */
6572         I915_WRITE(SDEW, 0x15040d00);
6573         I915_WRITE(CSIEW0, 0x007f0000);
6574         I915_WRITE(CSIEW1, 0x1e220004);
6575         I915_WRITE(CSIEW2, 0x04000004);
6576
6577         for (i = 0; i < 5; i++)
6578                 I915_WRITE(PEW(i), 0);
6579         for (i = 0; i < 3; i++)
6580                 I915_WRITE(DEW(i), 0);
6581
6582         /* Program P-state weights to account for frequency power adjustment */
6583         for (i = 0; i < 16; i++) {
6584                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6585                 unsigned long freq = intel_pxfreq(pxvidfreq);
6586                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6587                         PXVFREQ_PX_SHIFT;
6588                 unsigned long val;
6589
6590                 val = vid * vid;
6591                 val *= (freq / 1000);
6592                 val *= 255;
6593                 val /= (127*127*900);
6594                 if (val > 0xff)
6595                         DRM_ERROR("bad pxval: %ld\n", val);
6596                 pxw[i] = val;
6597         }
6598         /* Render standby states get 0 weight */
6599         pxw[14] = 0;
6600         pxw[15] = 0;
6601
6602         for (i = 0; i < 4; i++) {
6603                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6604                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6605                 I915_WRITE(PXW(i), val);
6606         }
6607
6608         /* Adjust magic regs to magic values (more experimental results) */
6609         I915_WRITE(OGW0, 0);
6610         I915_WRITE(OGW1, 0);
6611         I915_WRITE(EG0, 0x00007f00);
6612         I915_WRITE(EG1, 0x0000000e);
6613         I915_WRITE(EG2, 0x000e0000);
6614         I915_WRITE(EG3, 0x68000300);
6615         I915_WRITE(EG4, 0x42000000);
6616         I915_WRITE(EG5, 0x00140031);
6617         I915_WRITE(EG6, 0);
6618         I915_WRITE(EG7, 0);
6619
6620         for (i = 0; i < 8; i++)
6621                 I915_WRITE(PXWL(i), 0);
6622
6623         /* Enable PMON + select events */
6624         I915_WRITE(ECR, 0x80000019);
6625
6626         lcfuse = I915_READ(LCFUSE02);
6627
6628         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6629 }
6630
6631 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6632 {
6633         /*
6634          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6635          * requirement.
6636          */
6637         if (!i915.enable_rc6) {
6638                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6639                 intel_runtime_pm_get(dev_priv);
6640         }
6641
6642         mutex_lock(&dev_priv->drm.struct_mutex);
6643         mutex_lock(&dev_priv->rps.hw_lock);
6644
6645         /* Initialize RPS limits (for userspace) */
6646         if (IS_CHERRYVIEW(dev_priv))
6647                 cherryview_init_gt_powersave(dev_priv);
6648         else if (IS_VALLEYVIEW(dev_priv))
6649                 valleyview_init_gt_powersave(dev_priv);
6650         else if (INTEL_GEN(dev_priv) >= 6)
6651                 gen6_init_rps_frequencies(dev_priv);
6652
6653         /* Derive initial user preferences/limits from the hardware limits */
6654         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6655         dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6656
6657         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6658         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6659
6660         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6661                 dev_priv->rps.min_freq_softlimit =
6662                         max_t(int,
6663                               dev_priv->rps.efficient_freq,
6664                               intel_freq_opcode(dev_priv, 450));
6665
6666         /* After setting max-softlimit, find the overclock max freq */
6667         if (IS_GEN6(dev_priv) ||
6668             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6669                 u32 params = 0;
6670
6671                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6672                 if (params & BIT(31)) { /* OC supported */
6673                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6674                                          (dev_priv->rps.max_freq & 0xff) * 50,
6675                                          (params & 0xff) * 50);
6676                         dev_priv->rps.max_freq = params & 0xff;
6677                 }
6678         }
6679
6680         /* Finally allow us to boost to max by default */
6681         dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6682
6683         mutex_unlock(&dev_priv->rps.hw_lock);
6684         mutex_unlock(&dev_priv->drm.struct_mutex);
6685
6686         intel_autoenable_gt_powersave(dev_priv);
6687 }
6688
6689 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6690 {
6691         if (IS_VALLEYVIEW(dev_priv))
6692                 valleyview_cleanup_gt_powersave(dev_priv);
6693
6694         if (!i915.enable_rc6)
6695                 intel_runtime_pm_put(dev_priv);
6696 }
6697
6698 /**
6699  * intel_suspend_gt_powersave - suspend PM work and helper threads
6700  * @dev_priv: i915 device
6701  *
6702  * We don't want to disable RC6 or other features here, we just want
6703  * to make sure any work we've queued has finished and won't bother
6704  * us while we're suspended.
6705  */
6706 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6707 {
6708         if (INTEL_GEN(dev_priv) < 6)
6709                 return;
6710
6711         if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6712                 intel_runtime_pm_put(dev_priv);
6713
6714         /* gen6_rps_idle() will be called later to disable interrupts */
6715 }
6716
6717 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6718 {
6719         dev_priv->rps.enabled = true; /* force disabling */
6720         intel_disable_gt_powersave(dev_priv);
6721
6722         gen6_reset_rps_interrupts(dev_priv);
6723 }
6724
6725 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6726 {
6727         if (!READ_ONCE(dev_priv->rps.enabled))
6728                 return;
6729
6730         mutex_lock(&dev_priv->rps.hw_lock);
6731
6732         if (INTEL_GEN(dev_priv) >= 9) {
6733                 gen9_disable_rc6(dev_priv);
6734                 gen9_disable_rps(dev_priv);
6735         } else if (IS_CHERRYVIEW(dev_priv)) {
6736                 cherryview_disable_rps(dev_priv);
6737         } else if (IS_VALLEYVIEW(dev_priv)) {
6738                 valleyview_disable_rps(dev_priv);
6739         } else if (INTEL_GEN(dev_priv) >= 6) {
6740                 gen6_disable_rps(dev_priv);
6741         }  else if (IS_IRONLAKE_M(dev_priv)) {
6742                 ironlake_disable_drps(dev_priv);
6743         }
6744
6745         dev_priv->rps.enabled = false;
6746         mutex_unlock(&dev_priv->rps.hw_lock);
6747 }
6748
6749 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6750 {
6751         /* We shouldn't be disabling as we submit, so this should be less
6752          * racy than it appears!
6753          */
6754         if (READ_ONCE(dev_priv->rps.enabled))
6755                 return;
6756
6757         /* Powersaving is controlled by the host when inside a VM */
6758         if (intel_vgpu_active(dev_priv))
6759                 return;
6760
6761         mutex_lock(&dev_priv->rps.hw_lock);
6762
6763         if (IS_CHERRYVIEW(dev_priv)) {
6764                 cherryview_enable_rps(dev_priv);
6765         } else if (IS_VALLEYVIEW(dev_priv)) {
6766                 valleyview_enable_rps(dev_priv);
6767         } else if (INTEL_GEN(dev_priv) >= 9) {
6768                 gen9_enable_rc6(dev_priv);
6769                 gen9_enable_rps(dev_priv);
6770                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6771                         gen6_update_ring_freq(dev_priv);
6772         } else if (IS_BROADWELL(dev_priv)) {
6773                 gen8_enable_rps(dev_priv);
6774                 gen6_update_ring_freq(dev_priv);
6775         } else if (INTEL_GEN(dev_priv) >= 6) {
6776                 gen6_enable_rps(dev_priv);
6777                 gen6_update_ring_freq(dev_priv);
6778         } else if (IS_IRONLAKE_M(dev_priv)) {
6779                 ironlake_enable_drps(dev_priv);
6780                 intel_init_emon(dev_priv);
6781         }
6782
6783         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6784         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6785
6786         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6787         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6788
6789         dev_priv->rps.enabled = true;
6790         mutex_unlock(&dev_priv->rps.hw_lock);
6791 }
6792
6793 static void __intel_autoenable_gt_powersave(struct work_struct *work)
6794 {
6795         struct drm_i915_private *dev_priv =
6796                 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6797         struct intel_engine_cs *rcs;
6798         struct drm_i915_gem_request *req;
6799
6800         if (READ_ONCE(dev_priv->rps.enabled))
6801                 goto out;
6802
6803         rcs = dev_priv->engine[RCS];
6804         if (rcs->last_context)
6805                 goto out;
6806
6807         if (!rcs->init_context)
6808                 goto out;
6809
6810         mutex_lock(&dev_priv->drm.struct_mutex);
6811
6812         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6813         if (IS_ERR(req))
6814                 goto unlock;
6815
6816         if (!i915.enable_execlists && i915_switch_context(req) == 0)
6817                 rcs->init_context(req);
6818
6819         /* Mark the device busy, calling intel_enable_gt_powersave() */
6820         i915_add_request_no_flush(req);
6821
6822 unlock:
6823         mutex_unlock(&dev_priv->drm.struct_mutex);
6824 out:
6825         intel_runtime_pm_put(dev_priv);
6826 }
6827
6828 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6829 {
6830         if (READ_ONCE(dev_priv->rps.enabled))
6831                 return;
6832
6833         if (IS_IRONLAKE_M(dev_priv)) {
6834                 ironlake_enable_drps(dev_priv);
6835                 intel_init_emon(dev_priv);
6836         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6837                 /*
6838                  * PCU communication is slow and this doesn't need to be
6839                  * done at any specific time, so do this out of our fast path
6840                  * to make resume and init faster.
6841                  *
6842                  * We depend on the HW RC6 power context save/restore
6843                  * mechanism when entering D3 through runtime PM suspend. So
6844                  * disable RPM until RPS/RC6 is properly setup. We can only
6845                  * get here via the driver load/system resume/runtime resume
6846                  * paths, so the _noresume version is enough (and in case of
6847                  * runtime resume it's necessary).
6848                  */
6849                 if (queue_delayed_work(dev_priv->wq,
6850                                        &dev_priv->rps.autoenable_work,
6851                                        round_jiffies_up_relative(HZ)))
6852                         intel_runtime_pm_get_noresume(dev_priv);
6853         }
6854 }
6855
6856 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
6857 {
6858         /*
6859          * On Ibex Peak and Cougar Point, we need to disable clock
6860          * gating for the panel power sequencer or it will fail to
6861          * start up when no ports are active.
6862          */
6863         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6864 }
6865
6866 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
6867 {
6868         enum pipe pipe;
6869
6870         for_each_pipe(dev_priv, pipe) {
6871                 I915_WRITE(DSPCNTR(pipe),
6872                            I915_READ(DSPCNTR(pipe)) |
6873                            DISPPLANE_TRICKLE_FEED_DISABLE);
6874
6875                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6876                 POSTING_READ(DSPSURF(pipe));
6877         }
6878 }
6879
6880 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
6881 {
6882         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6883         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6884         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6885
6886         /*
6887          * Don't touch WM1S_LP_EN here.
6888          * Doing so could cause underruns.
6889          */
6890 }
6891
6892 static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
6893 {
6894         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6895
6896         /*
6897          * Required for FBC
6898          * WaFbcDisableDpfcClockGating:ilk
6899          */
6900         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6901                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6902                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6903
6904         I915_WRITE(PCH_3DCGDIS0,
6905                    MARIUNIT_CLOCK_GATE_DISABLE |
6906                    SVSMUNIT_CLOCK_GATE_DISABLE);
6907         I915_WRITE(PCH_3DCGDIS1,
6908                    VFMUNIT_CLOCK_GATE_DISABLE);
6909
6910         /*
6911          * According to the spec the following bits should be set in
6912          * order to enable memory self-refresh
6913          * The bit 22/21 of 0x42004
6914          * The bit 5 of 0x42020
6915          * The bit 15 of 0x45000
6916          */
6917         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6918                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6919                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6920         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6921         I915_WRITE(DISP_ARB_CTL,
6922                    (I915_READ(DISP_ARB_CTL) |
6923                     DISP_FBC_WM_DIS));
6924
6925         ilk_init_lp_watermarks(dev_priv);
6926
6927         /*
6928          * Based on the document from hardware guys the following bits
6929          * should be set unconditionally in order to enable FBC.
6930          * The bit 22 of 0x42000
6931          * The bit 22 of 0x42004
6932          * The bit 7,8,9 of 0x42020.
6933          */
6934         if (IS_IRONLAKE_M(dev_priv)) {
6935                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6936                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6937                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6938                            ILK_FBCQ_DIS);
6939                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6940                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6941                            ILK_DPARB_GATE);
6942         }
6943
6944         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6945
6946         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6947                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6948                    ILK_ELPIN_409_SELECT);
6949         I915_WRITE(_3D_CHICKEN2,
6950                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6951                    _3D_CHICKEN2_WM_READ_PIPELINED);
6952
6953         /* WaDisableRenderCachePipelinedFlush:ilk */
6954         I915_WRITE(CACHE_MODE_0,
6955                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6956
6957         /* WaDisable_RenderCache_OperationalFlush:ilk */
6958         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6959
6960         g4x_disable_trickle_feed(dev_priv);
6961
6962         ibx_init_clock_gating(dev_priv);
6963 }
6964
6965 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
6966 {
6967         int pipe;
6968         uint32_t val;
6969
6970         /*
6971          * On Ibex Peak and Cougar Point, we need to disable clock
6972          * gating for the panel power sequencer or it will fail to
6973          * start up when no ports are active.
6974          */
6975         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6976                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6977                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6978         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6979                    DPLS_EDP_PPS_FIX_DIS);
6980         /* The below fixes the weird display corruption, a few pixels shifted
6981          * downward, on (only) LVDS of some HP laptops with IVY.
6982          */
6983         for_each_pipe(dev_priv, pipe) {
6984                 val = I915_READ(TRANS_CHICKEN2(pipe));
6985                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6986                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6987                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6988                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6989                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6990                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6991                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6992                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6993         }
6994         /* WADP0ClockGatingDisable */
6995         for_each_pipe(dev_priv, pipe) {
6996                 I915_WRITE(TRANS_CHICKEN1(pipe),
6997                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6998         }
6999 }
7000
7001 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
7002 {
7003         uint32_t tmp;
7004
7005         tmp = I915_READ(MCH_SSKPD);
7006         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7007                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7008                               tmp);
7009 }
7010
7011 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
7012 {
7013         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7014
7015         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
7016
7017         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7018                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7019                    ILK_ELPIN_409_SELECT);
7020
7021         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7022         I915_WRITE(_3D_CHICKEN,
7023                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7024
7025         /* WaDisable_RenderCache_OperationalFlush:snb */
7026         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7027
7028         /*
7029          * BSpec recoomends 8x4 when MSAA is used,
7030          * however in practice 16x4 seems fastest.
7031          *
7032          * Note that PS/WM thread counts depend on the WIZ hashing
7033          * disable bit, which we don't touch here, but it's good
7034          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7035          */
7036         I915_WRITE(GEN6_GT_MODE,
7037                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7038
7039         ilk_init_lp_watermarks(dev_priv);
7040
7041         I915_WRITE(CACHE_MODE_0,
7042                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
7043
7044         I915_WRITE(GEN6_UCGCTL1,
7045                    I915_READ(GEN6_UCGCTL1) |
7046                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7047                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7048
7049         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7050          * gating disable must be set.  Failure to set it results in
7051          * flickering pixels due to Z write ordering failures after
7052          * some amount of runtime in the Mesa "fire" demo, and Unigine
7053          * Sanctuary and Tropics, and apparently anything else with
7054          * alpha test or pixel discard.
7055          *
7056          * According to the spec, bit 11 (RCCUNIT) must also be set,
7057          * but we didn't debug actual testcases to find it out.
7058          *
7059          * WaDisableRCCUnitClockGating:snb
7060          * WaDisableRCPBUnitClockGating:snb
7061          */
7062         I915_WRITE(GEN6_UCGCTL2,
7063                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7064                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7065
7066         /* WaStripsFansDisableFastClipPerformanceFix:snb */
7067         I915_WRITE(_3D_CHICKEN3,
7068                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7069
7070         /*
7071          * Bspec says:
7072          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7073          * 3DSTATE_SF number of SF output attributes is more than 16."
7074          */
7075         I915_WRITE(_3D_CHICKEN3,
7076                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7077
7078         /*
7079          * According to the spec the following bits should be
7080          * set in order to enable memory self-refresh and fbc:
7081          * The bit21 and bit22 of 0x42000
7082          * The bit21 and bit22 of 0x42004
7083          * The bit5 and bit7 of 0x42020
7084          * The bit14 of 0x70180
7085          * The bit14 of 0x71180
7086          *
7087          * WaFbcAsynchFlipDisableFbcQueue:snb
7088          */
7089         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7090                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7091                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7092         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7093                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7094                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7095         I915_WRITE(ILK_DSPCLK_GATE_D,
7096                    I915_READ(ILK_DSPCLK_GATE_D) |
7097                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7098                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7099
7100         g4x_disable_trickle_feed(dev_priv);
7101
7102         cpt_init_clock_gating(dev_priv);
7103
7104         gen6_check_mch_setup(dev_priv);
7105 }
7106
7107 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7108 {
7109         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7110
7111         /*
7112          * WaVSThreadDispatchOverride:ivb,vlv
7113          *
7114          * This actually overrides the dispatch
7115          * mode for all thread types.
7116          */
7117         reg &= ~GEN7_FF_SCHED_MASK;
7118         reg |= GEN7_FF_TS_SCHED_HW;
7119         reg |= GEN7_FF_VS_SCHED_HW;
7120         reg |= GEN7_FF_DS_SCHED_HW;
7121
7122         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7123 }
7124
7125 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
7126 {
7127         /*
7128          * TODO: this bit should only be enabled when really needed, then
7129          * disabled when not needed anymore in order to save power.
7130          */
7131         if (HAS_PCH_LPT_LP(dev_priv))
7132                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7133                            I915_READ(SOUTH_DSPCLK_GATE_D) |
7134                            PCH_LP_PARTITION_LEVEL_DISABLE);
7135
7136         /* WADPOClockGatingDisable:hsw */
7137         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7138                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7139                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7140 }
7141
7142 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7143 {
7144         if (HAS_PCH_LPT_LP(dev_priv)) {
7145                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7146
7147                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7148                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7149         }
7150 }
7151
7152 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7153                                    int general_prio_credits,
7154                                    int high_prio_credits)
7155 {
7156         u32 misccpctl;
7157
7158         /* WaTempDisableDOPClkGating:bdw */
7159         misccpctl = I915_READ(GEN7_MISCCPCTL);
7160         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7161
7162         I915_WRITE(GEN8_L3SQCREG1,
7163                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7164                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
7165
7166         /*
7167          * Wait at least 100 clocks before re-enabling clock gating.
7168          * See the definition of L3SQCREG1 in BSpec.
7169          */
7170         POSTING_READ(GEN8_L3SQCREG1);
7171         udelay(1);
7172         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7173 }
7174
7175 static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
7176 {
7177         gen9_init_clock_gating(dev_priv);
7178
7179         /* WaDisableSDEUnitClockGating:kbl */
7180         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7181                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7182                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7183
7184         /* WaDisableGamClockGating:kbl */
7185         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7186                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7187                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7188
7189         /* WaFbcNukeOnHostModify:kbl */
7190         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7191                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7192 }
7193
7194 static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
7195 {
7196         gen9_init_clock_gating(dev_priv);
7197
7198         /* WAC6entrylatency:skl */
7199         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7200                    FBC_LLC_FULLY_OPEN);
7201
7202         /* WaFbcNukeOnHostModify:skl */
7203         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7204                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7205 }
7206
7207 static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
7208 {
7209         enum pipe pipe;
7210
7211         ilk_init_lp_watermarks(dev_priv);
7212
7213         /* WaSwitchSolVfFArbitrationPriority:bdw */
7214         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7215
7216         /* WaPsrDPAMaskVBlankInSRD:bdw */
7217         I915_WRITE(CHICKEN_PAR1_1,
7218                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7219
7220         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7221         for_each_pipe(dev_priv, pipe) {
7222                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7223                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
7224                            BDW_DPRS_MASK_VBLANK_SRD);
7225         }
7226
7227         /* WaVSRefCountFullforceMissDisable:bdw */
7228         /* WaDSRefCountFullforceMissDisable:bdw */
7229         I915_WRITE(GEN7_FF_THREAD_MODE,
7230                    I915_READ(GEN7_FF_THREAD_MODE) &
7231                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7232
7233         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7234                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7235
7236         /* WaDisableSDEUnitClockGating:bdw */
7237         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7238                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7239
7240         /* WaProgramL3SqcReg1Default:bdw */
7241         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7242
7243         /*
7244          * WaGttCachingOffByDefault:bdw
7245          * GTT cache may not work with big pages, so if those
7246          * are ever enabled GTT cache may need to be disabled.
7247          */
7248         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7249
7250         /* WaKVMNotificationOnConfigChange:bdw */
7251         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7252                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7253
7254         lpt_init_clock_gating(dev_priv);
7255 }
7256
7257 static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
7258 {
7259         ilk_init_lp_watermarks(dev_priv);
7260
7261         /* L3 caching of data atomics doesn't work -- disable it. */
7262         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7263         I915_WRITE(HSW_ROW_CHICKEN3,
7264                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7265
7266         /* This is required by WaCatErrorRejectionIssue:hsw */
7267         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7268                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7269                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7270
7271         /* WaVSRefCountFullforceMissDisable:hsw */
7272         I915_WRITE(GEN7_FF_THREAD_MODE,
7273                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7274
7275         /* WaDisable_RenderCache_OperationalFlush:hsw */
7276         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7277
7278         /* enable HiZ Raw Stall Optimization */
7279         I915_WRITE(CACHE_MODE_0_GEN7,
7280                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7281
7282         /* WaDisable4x2SubspanOptimization:hsw */
7283         I915_WRITE(CACHE_MODE_1,
7284                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7285
7286         /*
7287          * BSpec recommends 8x4 when MSAA is used,
7288          * however in practice 16x4 seems fastest.
7289          *
7290          * Note that PS/WM thread counts depend on the WIZ hashing
7291          * disable bit, which we don't touch here, but it's good
7292          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7293          */
7294         I915_WRITE(GEN7_GT_MODE,
7295                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7296
7297         /* WaSampleCChickenBitEnable:hsw */
7298         I915_WRITE(HALF_SLICE_CHICKEN3,
7299                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7300
7301         /* WaSwitchSolVfFArbitrationPriority:hsw */
7302         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7303
7304         /* WaRsPkgCStateDisplayPMReq:hsw */
7305         I915_WRITE(CHICKEN_PAR1_1,
7306                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7307
7308         lpt_init_clock_gating(dev_priv);
7309 }
7310
7311 static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
7312 {
7313         uint32_t snpcr;
7314
7315         ilk_init_lp_watermarks(dev_priv);
7316
7317         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7318
7319         /* WaDisableEarlyCull:ivb */
7320         I915_WRITE(_3D_CHICKEN3,
7321                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7322
7323         /* WaDisableBackToBackFlipFix:ivb */
7324         I915_WRITE(IVB_CHICKEN3,
7325                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7326                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7327
7328         /* WaDisablePSDDualDispatchEnable:ivb */
7329         if (IS_IVB_GT1(dev_priv))
7330                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7331                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7332
7333         /* WaDisable_RenderCache_OperationalFlush:ivb */
7334         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7335
7336         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7337         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7338                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7339
7340         /* WaApplyL3ControlAndL3ChickenMode:ivb */
7341         I915_WRITE(GEN7_L3CNTLREG1,
7342                         GEN7_WA_FOR_GEN7_L3_CONTROL);
7343         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7344                    GEN7_WA_L3_CHICKEN_MODE);
7345         if (IS_IVB_GT1(dev_priv))
7346                 I915_WRITE(GEN7_ROW_CHICKEN2,
7347                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7348         else {
7349                 /* must write both registers */
7350                 I915_WRITE(GEN7_ROW_CHICKEN2,
7351                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7352                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7353                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7354         }
7355
7356         /* WaForceL3Serialization:ivb */
7357         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7358                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7359
7360         /*
7361          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7362          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7363          */
7364         I915_WRITE(GEN6_UCGCTL2,
7365                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7366
7367         /* This is required by WaCatErrorRejectionIssue:ivb */
7368         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7369                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7370                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7371
7372         g4x_disable_trickle_feed(dev_priv);
7373
7374         gen7_setup_fixed_func_scheduler(dev_priv);
7375
7376         if (0) { /* causes HiZ corruption on ivb:gt1 */
7377                 /* enable HiZ Raw Stall Optimization */
7378                 I915_WRITE(CACHE_MODE_0_GEN7,
7379                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7380         }
7381
7382         /* WaDisable4x2SubspanOptimization:ivb */
7383         I915_WRITE(CACHE_MODE_1,
7384                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7385
7386         /*
7387          * BSpec recommends 8x4 when MSAA is used,
7388          * however in practice 16x4 seems fastest.
7389          *
7390          * Note that PS/WM thread counts depend on the WIZ hashing
7391          * disable bit, which we don't touch here, but it's good
7392          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7393          */
7394         I915_WRITE(GEN7_GT_MODE,
7395                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7396
7397         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7398         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7399         snpcr |= GEN6_MBC_SNPCR_MED;
7400         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7401
7402         if (!HAS_PCH_NOP(dev_priv))
7403                 cpt_init_clock_gating(dev_priv);
7404
7405         gen6_check_mch_setup(dev_priv);
7406 }
7407
7408 static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
7409 {
7410         /* WaDisableEarlyCull:vlv */
7411         I915_WRITE(_3D_CHICKEN3,
7412                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7413
7414         /* WaDisableBackToBackFlipFix:vlv */
7415         I915_WRITE(IVB_CHICKEN3,
7416                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7417                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7418
7419         /* WaPsdDispatchEnable:vlv */
7420         /* WaDisablePSDDualDispatchEnable:vlv */
7421         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7422                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7423                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7424
7425         /* WaDisable_RenderCache_OperationalFlush:vlv */
7426         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7427
7428         /* WaForceL3Serialization:vlv */
7429         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7430                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7431
7432         /* WaDisableDopClockGating:vlv */
7433         I915_WRITE(GEN7_ROW_CHICKEN2,
7434                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7435
7436         /* This is required by WaCatErrorRejectionIssue:vlv */
7437         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7438                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7439                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7440
7441         gen7_setup_fixed_func_scheduler(dev_priv);
7442
7443         /*
7444          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7445          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7446          */
7447         I915_WRITE(GEN6_UCGCTL2,
7448                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7449
7450         /* WaDisableL3Bank2xClockGate:vlv
7451          * Disabling L3 clock gating- MMIO 940c[25] = 1
7452          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7453         I915_WRITE(GEN7_UCGCTL4,
7454                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7455
7456         /*
7457          * BSpec says this must be set, even though
7458          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7459          */
7460         I915_WRITE(CACHE_MODE_1,
7461                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7462
7463         /*
7464          * BSpec recommends 8x4 when MSAA is used,
7465          * however in practice 16x4 seems fastest.
7466          *
7467          * Note that PS/WM thread counts depend on the WIZ hashing
7468          * disable bit, which we don't touch here, but it's good
7469          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7470          */
7471         I915_WRITE(GEN7_GT_MODE,
7472                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7473
7474         /*
7475          * WaIncreaseL3CreditsForVLVB0:vlv
7476          * This is the hardware default actually.
7477          */
7478         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7479
7480         /*
7481          * WaDisableVLVClockGating_VBIIssue:vlv
7482          * Disable clock gating on th GCFG unit to prevent a delay
7483          * in the reporting of vblank events.
7484          */
7485         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7486 }
7487
7488 static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
7489 {
7490         /* WaVSRefCountFullforceMissDisable:chv */
7491         /* WaDSRefCountFullforceMissDisable:chv */
7492         I915_WRITE(GEN7_FF_THREAD_MODE,
7493                    I915_READ(GEN7_FF_THREAD_MODE) &
7494                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7495
7496         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7497         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7498                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7499
7500         /* WaDisableCSUnitClockGating:chv */
7501         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7502                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7503
7504         /* WaDisableSDEUnitClockGating:chv */
7505         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7506                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7507
7508         /*
7509          * WaProgramL3SqcReg1Default:chv
7510          * See gfxspecs/Related Documents/Performance Guide/
7511          * LSQC Setting Recommendations.
7512          */
7513         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7514
7515         /*
7516          * GTT cache may not work with big pages, so if those
7517          * are ever enabled GTT cache may need to be disabled.
7518          */
7519         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7520 }
7521
7522 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
7523 {
7524         uint32_t dspclk_gate;
7525
7526         I915_WRITE(RENCLK_GATE_D1, 0);
7527         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7528                    GS_UNIT_CLOCK_GATE_DISABLE |
7529                    CL_UNIT_CLOCK_GATE_DISABLE);
7530         I915_WRITE(RAMCLK_GATE_D, 0);
7531         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7532                 OVRUNIT_CLOCK_GATE_DISABLE |
7533                 OVCUNIT_CLOCK_GATE_DISABLE;
7534         if (IS_GM45(dev_priv))
7535                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7536         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7537
7538         /* WaDisableRenderCachePipelinedFlush */
7539         I915_WRITE(CACHE_MODE_0,
7540                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7541
7542         /* WaDisable_RenderCache_OperationalFlush:g4x */
7543         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7544
7545         g4x_disable_trickle_feed(dev_priv);
7546 }
7547
7548 static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
7549 {
7550         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7551         I915_WRITE(RENCLK_GATE_D2, 0);
7552         I915_WRITE(DSPCLK_GATE_D, 0);
7553         I915_WRITE(RAMCLK_GATE_D, 0);
7554         I915_WRITE16(DEUC, 0);
7555         I915_WRITE(MI_ARB_STATE,
7556                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7557
7558         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7559         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7560 }
7561
7562 static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
7563 {
7564         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7565                    I965_RCC_CLOCK_GATE_DISABLE |
7566                    I965_RCPB_CLOCK_GATE_DISABLE |
7567                    I965_ISC_CLOCK_GATE_DISABLE |
7568                    I965_FBC_CLOCK_GATE_DISABLE);
7569         I915_WRITE(RENCLK_GATE_D2, 0);
7570         I915_WRITE(MI_ARB_STATE,
7571                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7572
7573         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7574         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7575 }
7576
7577 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
7578 {
7579         u32 dstate = I915_READ(D_STATE);
7580
7581         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7582                 DSTATE_DOT_CLOCK_GATING;
7583         I915_WRITE(D_STATE, dstate);
7584
7585         if (IS_PINEVIEW(dev_priv))
7586                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7587
7588         /* IIR "flip pending" means done if this bit is set */
7589         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7590
7591         /* interrupts should cause a wake up from C3 */
7592         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7593
7594         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7595         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7596
7597         I915_WRITE(MI_ARB_STATE,
7598                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7599 }
7600
7601 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
7602 {
7603         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7604
7605         /* interrupts should cause a wake up from C3 */
7606         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7607                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7608
7609         I915_WRITE(MEM_MODE,
7610                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7611 }
7612
7613 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
7614 {
7615         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7616
7617         I915_WRITE(MEM_MODE,
7618                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7619                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7620 }
7621
7622 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
7623 {
7624         dev_priv->display.init_clock_gating(dev_priv);
7625 }
7626
7627 void intel_suspend_hw(struct drm_i915_private *dev_priv)
7628 {
7629         if (HAS_PCH_LPT(dev_priv))
7630                 lpt_suspend_hw(dev_priv);
7631 }
7632
7633 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
7634 {
7635         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7636 }
7637
7638 /**
7639  * intel_init_clock_gating_hooks - setup the clock gating hooks
7640  * @dev_priv: device private
7641  *
7642  * Setup the hooks that configure which clocks of a given platform can be
7643  * gated and also apply various GT and display specific workarounds for these
7644  * platforms. Note that some GT specific workarounds are applied separately
7645  * when GPU contexts or batchbuffers start their execution.
7646  */
7647 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7648 {
7649         if (IS_SKYLAKE(dev_priv))
7650                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7651         else if (IS_KABYLAKE(dev_priv))
7652                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7653         else if (IS_BROXTON(dev_priv))
7654                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7655         else if (IS_BROADWELL(dev_priv))
7656                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7657         else if (IS_CHERRYVIEW(dev_priv))
7658                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7659         else if (IS_HASWELL(dev_priv))
7660                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7661         else if (IS_IVYBRIDGE(dev_priv))
7662                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7663         else if (IS_VALLEYVIEW(dev_priv))
7664                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7665         else if (IS_GEN6(dev_priv))
7666                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7667         else if (IS_GEN5(dev_priv))
7668                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7669         else if (IS_G4X(dev_priv))
7670                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7671         else if (IS_CRESTLINE(dev_priv))
7672                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7673         else if (IS_BROADWATER(dev_priv))
7674                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7675         else if (IS_GEN3(dev_priv))
7676                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7677         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7678                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7679         else if (IS_GEN2(dev_priv))
7680                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7681         else {
7682                 MISSING_CASE(INTEL_DEVID(dev_priv));
7683                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7684         }
7685 }
7686
7687 /* Set up chip specific power management-related functions */
7688 void intel_init_pm(struct drm_i915_private *dev_priv)
7689 {
7690         intel_fbc_init(dev_priv);
7691
7692         /* For cxsr */
7693         if (IS_PINEVIEW(dev_priv))
7694                 i915_pineview_get_mem_freq(dev_priv);
7695         else if (IS_GEN5(dev_priv))
7696                 i915_ironlake_get_mem_freq(dev_priv);
7697
7698         /* For FIFO watermark updates */
7699         if (INTEL_GEN(dev_priv) >= 9) {
7700                 skl_setup_wm_latency(dev_priv);
7701                 dev_priv->display.initial_watermarks = skl_initial_wm;
7702                 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
7703                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7704         } else if (HAS_PCH_SPLIT(dev_priv)) {
7705                 ilk_setup_wm_latency(dev_priv);
7706
7707                 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
7708                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7709                     (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
7710                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7711                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7712                         dev_priv->display.compute_intermediate_wm =
7713                                 ilk_compute_intermediate_wm;
7714                         dev_priv->display.initial_watermarks =
7715                                 ilk_initial_watermarks;
7716                         dev_priv->display.optimize_watermarks =
7717                                 ilk_optimize_watermarks;
7718                 } else {
7719                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7720                                       "Disable CxSR\n");
7721                 }
7722         } else if (IS_CHERRYVIEW(dev_priv)) {
7723                 vlv_setup_wm_latency(dev_priv);
7724                 dev_priv->display.update_wm = vlv_update_wm;
7725         } else if (IS_VALLEYVIEW(dev_priv)) {
7726                 vlv_setup_wm_latency(dev_priv);
7727                 dev_priv->display.update_wm = vlv_update_wm;
7728         } else if (IS_PINEVIEW(dev_priv)) {
7729                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
7730                                             dev_priv->is_ddr3,
7731                                             dev_priv->fsb_freq,
7732                                             dev_priv->mem_freq)) {
7733                         DRM_INFO("failed to find known CxSR latency "
7734                                  "(found ddr%s fsb freq %d, mem freq %d), "
7735                                  "disabling CxSR\n",
7736                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7737                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7738                         /* Disable CxSR and never update its watermark again */
7739                         intel_set_memory_cxsr(dev_priv, false);
7740                         dev_priv->display.update_wm = NULL;
7741                 } else
7742                         dev_priv->display.update_wm = pineview_update_wm;
7743         } else if (IS_G4X(dev_priv)) {
7744                 dev_priv->display.update_wm = g4x_update_wm;
7745         } else if (IS_GEN4(dev_priv)) {
7746                 dev_priv->display.update_wm = i965_update_wm;
7747         } else if (IS_GEN3(dev_priv)) {
7748                 dev_priv->display.update_wm = i9xx_update_wm;
7749                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7750         } else if (IS_GEN2(dev_priv)) {
7751                 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
7752                         dev_priv->display.update_wm = i845_update_wm;
7753                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7754                 } else {
7755                         dev_priv->display.update_wm = i9xx_update_wm;
7756                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7757                 }
7758         } else {
7759                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7760         }
7761 }
7762
7763 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7764 {
7765         uint32_t flags =
7766                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7767
7768         switch (flags) {
7769         case GEN6_PCODE_SUCCESS:
7770                 return 0;
7771         case GEN6_PCODE_UNIMPLEMENTED_CMD:
7772         case GEN6_PCODE_ILLEGAL_CMD:
7773                 return -ENXIO;
7774         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7775         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7776                 return -EOVERFLOW;
7777         case GEN6_PCODE_TIMEOUT:
7778                 return -ETIMEDOUT;
7779         default:
7780                 MISSING_CASE(flags)
7781                 return 0;
7782         }
7783 }
7784
7785 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7786 {
7787         uint32_t flags =
7788                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7789
7790         switch (flags) {
7791         case GEN6_PCODE_SUCCESS:
7792                 return 0;
7793         case GEN6_PCODE_ILLEGAL_CMD:
7794                 return -ENXIO;
7795         case GEN7_PCODE_TIMEOUT:
7796                 return -ETIMEDOUT;
7797         case GEN7_PCODE_ILLEGAL_DATA:
7798                 return -EINVAL;
7799         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7800                 return -EOVERFLOW;
7801         default:
7802                 MISSING_CASE(flags);
7803                 return 0;
7804         }
7805 }
7806
7807 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7808 {
7809         int status;
7810
7811         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7812
7813         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7814          * use te fw I915_READ variants to reduce the amount of work
7815          * required when reading/writing.
7816          */
7817
7818         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7819                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7820                 return -EAGAIN;
7821         }
7822
7823         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7824         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7825         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7826
7827         if (intel_wait_for_register_fw(dev_priv,
7828                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7829                                        500)) {
7830                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7831                 return -ETIMEDOUT;
7832         }
7833
7834         *val = I915_READ_FW(GEN6_PCODE_DATA);
7835         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7836
7837         if (INTEL_GEN(dev_priv) > 6)
7838                 status = gen7_check_mailbox_status(dev_priv);
7839         else
7840                 status = gen6_check_mailbox_status(dev_priv);
7841
7842         if (status) {
7843                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7844                                  status);
7845                 return status;
7846         }
7847
7848         return 0;
7849 }
7850
7851 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7852                             u32 mbox, u32 val)
7853 {
7854         int status;
7855
7856         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7857
7858         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7859          * use te fw I915_READ variants to reduce the amount of work
7860          * required when reading/writing.
7861          */
7862
7863         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7864                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7865                 return -EAGAIN;
7866         }
7867
7868         I915_WRITE_FW(GEN6_PCODE_DATA, val);
7869         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7870
7871         if (intel_wait_for_register_fw(dev_priv,
7872                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7873                                        500)) {
7874                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7875                 return -ETIMEDOUT;
7876         }
7877
7878         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7879
7880         if (INTEL_GEN(dev_priv) > 6)
7881                 status = gen7_check_mailbox_status(dev_priv);
7882         else
7883                 status = gen6_check_mailbox_status(dev_priv);
7884
7885         if (status) {
7886                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7887                                  status);
7888                 return status;
7889         }
7890
7891         return 0;
7892 }
7893
7894 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7895 {
7896         /*
7897          * N = val - 0xb7
7898          * Slow = Fast = GPLL ref * N
7899          */
7900         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7901 }
7902
7903 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7904 {
7905         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7906 }
7907
7908 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7909 {
7910         /*
7911          * N = val / 2
7912          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7913          */
7914         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7915 }
7916
7917 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7918 {
7919         /* CHV needs even values */
7920         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7921 }
7922
7923 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7924 {
7925         if (IS_GEN9(dev_priv))
7926                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7927                                          GEN9_FREQ_SCALER);
7928         else if (IS_CHERRYVIEW(dev_priv))
7929                 return chv_gpu_freq(dev_priv, val);
7930         else if (IS_VALLEYVIEW(dev_priv))
7931                 return byt_gpu_freq(dev_priv, val);
7932         else
7933                 return val * GT_FREQUENCY_MULTIPLIER;
7934 }
7935
7936 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7937 {
7938         if (IS_GEN9(dev_priv))
7939                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7940                                          GT_FREQUENCY_MULTIPLIER);
7941         else if (IS_CHERRYVIEW(dev_priv))
7942                 return chv_freq_opcode(dev_priv, val);
7943         else if (IS_VALLEYVIEW(dev_priv))
7944                 return byt_freq_opcode(dev_priv, val);
7945         else
7946                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7947 }
7948
7949 struct request_boost {
7950         struct work_struct work;
7951         struct drm_i915_gem_request *req;
7952 };
7953
7954 static void __intel_rps_boost_work(struct work_struct *work)
7955 {
7956         struct request_boost *boost = container_of(work, struct request_boost, work);
7957         struct drm_i915_gem_request *req = boost->req;
7958
7959         if (!i915_gem_request_completed(req))
7960                 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7961
7962         i915_gem_request_put(req);
7963         kfree(boost);
7964 }
7965
7966 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
7967 {
7968         struct request_boost *boost;
7969
7970         if (req == NULL || INTEL_GEN(req->i915) < 6)
7971                 return;
7972
7973         if (i915_gem_request_completed(req))
7974                 return;
7975
7976         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7977         if (boost == NULL)
7978                 return;
7979
7980         boost->req = i915_gem_request_get(req);
7981
7982         INIT_WORK(&boost->work, __intel_rps_boost_work);
7983         queue_work(req->i915->wq, &boost->work);
7984 }
7985
7986 void intel_pm_setup(struct drm_device *dev)
7987 {
7988         struct drm_i915_private *dev_priv = to_i915(dev);
7989
7990         mutex_init(&dev_priv->rps.hw_lock);
7991         spin_lock_init(&dev_priv->rps.client_lock);
7992
7993         INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
7994                           __intel_autoenable_gt_powersave);
7995         INIT_LIST_HEAD(&dev_priv->rps.clients);
7996
7997         dev_priv->pm.suspended = false;
7998         atomic_set(&dev_priv->pm.wakeref_count, 0);
7999 }