drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/pm_runtime.h>
  30
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_fourcc.h>
  33 #include <drm/drm_plane_helper.h>
  34
  35 #include "display/intel_atomic.h"
  36 #include "display/intel_bw.h"
  37 #include "display/intel_display_types.h"
  38 #include "display/intel_fbc.h"
  39 #include "display/intel_sprite.h"
  40
  41 #include "gt/intel_llc.h"
  42
  43 #include "i915_drv.h"
  44 #include "i915_fixed.h"
  45 #include "i915_irq.h"
  46 #include "i915_trace.h"
  47 #include "intel_pm.h"
  48 #include "intel_sideband.h"
  49 #include "../../../platform/x86/intel_ips.h"
  50
  51 /* Stores plane specific WM parameters */
  52 struct skl_wm_params {
  53         bool x_tiled, y_tiled;
  54         bool rc_surface;
  55         bool is_planar;
  56         u32 width;
  57         u8 cpp;
  58         u32 plane_pixel_rate;
  59         u32 y_min_scanlines;
  60         u32 plane_bytes_per_line;
  61         uint_fixed_16_16_t plane_blocks_per_line;
  62         uint_fixed_16_16_t y_tile_minimum;
  63         u32 linetime_us;
  64         u32 dbuf_block_size;
  65 };
  66
  67 /* used in computing the new watermarks state */
  68 struct intel_wm_config {
  69         unsigned int num_pipes_active;
  70         bool sprites_enabled;
  71         bool sprites_scaled;
  72 };
  73
  74 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
  75 {
  76         if (HAS_LLC(dev_priv)) {
  77                 /*
  78                  * WaCompressedResourceDisplayNewHashMode:skl,kbl
  79                  * Display WA #0390: skl,kbl
  80                  *
  81                  * Must match Sampler, Pixel Back End, and Media. See
  82                  * WaCompressedResourceSamplerPbeMediaNewHashMode.
  83                  */
  84                 I915_WRITE(CHICKEN_PAR1_1,
  85                            I915_READ(CHICKEN_PAR1_1) |
  86                            SKL_DE_COMPRESSED_HASH_MODE);
  87         }
  88
  89         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
  90         I915_WRITE(CHICKEN_PAR1_1,
  91                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  92
  93         /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
  94         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  95                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  96
  97         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
  98         /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
  99         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
 100                    DISP_FBC_WM_DIS |
 101                    DISP_FBC_MEMORY_WAKE);
 102
 103         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
 104         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
 105                    ILK_DPFC_DISABLE_DUMMY0);
 106
 107         if (IS_SKYLAKE(dev_priv)) {
 108                 /* WaDisableDopClockGating */
 109                 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
 110                            & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 111         }
 112 }
 113
 114 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
 115 {
 116         gen9_init_clock_gating(dev_priv);
 117
 118         /* WaDisableSDEUnitClockGating:bxt */
 119         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 120                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 121
 122         /*
 123          * FIXME:
 124          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 125          */
 126         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 127                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 128
 129         /*
 130          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 131          * to stay fully on.
 132          */
 133         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 134                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 135
 136         /*
 137          * Lower the display internal timeout.
 138          * This is needed to avoid any hard hangs when DSI port PLL
 139          * is off and a MMIO access is attempted by any privilege
 140          * application, using batch buffers or any other means.
 141          */
 142         I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950));
 143 }
 144
 145 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
 146 {
 147         gen9_init_clock_gating(dev_priv);
 148
 149         /*
 150          * WaDisablePWMClockGating:glk
 151          * Backlight PWM may stop in the asserted state, causing backlight
 152          * to stay fully on.
 153          */
 154         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 155                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 156 }
 157
 158 static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)
 159 {
 160         u32 tmp;
 161
 162         tmp = I915_READ(CLKCFG);
 163
 164         switch (tmp & CLKCFG_FSB_MASK) {
 165         case CLKCFG_FSB_533:
 166                 dev_priv->fsb_freq = 533; /* 133*4 */
 167                 break;
 168         case CLKCFG_FSB_800:
 169                 dev_priv->fsb_freq = 800; /* 200*4 */
 170                 break;
 171         case CLKCFG_FSB_667:
 172                 dev_priv->fsb_freq =  667; /* 167*4 */
 173                 break;
 174         case CLKCFG_FSB_400:
 175                 dev_priv->fsb_freq = 400; /* 100*4 */
 176                 break;
 177         }
 178
 179         switch (tmp & CLKCFG_MEM_MASK) {
 180         case CLKCFG_MEM_533:
 181                 dev_priv->mem_freq = 533;
 182                 break;
 183         case CLKCFG_MEM_667:
 184                 dev_priv->mem_freq = 667;
 185                 break;
 186         case CLKCFG_MEM_800:
 187                 dev_priv->mem_freq = 800;
 188                 break;
 189         }
 190
 191         /* detect pineview DDR3 setting */
 192         tmp = I915_READ(CSHRDDR3CTL);
 193         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 194 }
 195
 196 static void ilk_get_mem_freq(struct drm_i915_private *dev_priv)
 197 {
 198         u16 ddrpll, csipll;
 199
 200         ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
 201         csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0);
 202
 203         switch (ddrpll & 0xff) {
 204         case 0xc:
 205                 dev_priv->mem_freq = 800;
 206                 break;
 207         case 0x10:
 208                 dev_priv->mem_freq = 1066;
 209                 break;
 210         case 0x14:
 211                 dev_priv->mem_freq = 1333;
 212                 break;
 213         case 0x18:
 214                 dev_priv->mem_freq = 1600;
 215                 break;
 216         default:
 217                 drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
 218                         ddrpll & 0xff);
 219                 dev_priv->mem_freq = 0;
 220                 break;
 221         }
 222
 223         switch (csipll & 0x3ff) {
 224         case 0x00c:
 225                 dev_priv->fsb_freq = 3200;
 226                 break;
 227         case 0x00e:
 228                 dev_priv->fsb_freq = 3733;
 229                 break;
 230         case 0x010:
 231                 dev_priv->fsb_freq = 4266;
 232                 break;
 233         case 0x012:
 234                 dev_priv->fsb_freq = 4800;
 235                 break;
 236         case 0x014:
 237                 dev_priv->fsb_freq = 5333;
 238                 break;
 239         case 0x016:
 240                 dev_priv->fsb_freq = 5866;
 241                 break;
 242         case 0x018:
 243                 dev_priv->fsb_freq = 6400;
 244                 break;
 245         default:
 246                 drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n",
 247                         csipll & 0x3ff);
 248                 dev_priv->fsb_freq = 0;
 249                 break;
 250         }
 251 }
 252
 253 static const struct cxsr_latency cxsr_latency_table[] = {
 254         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 255         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 256         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 257         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 258         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 259
 260         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 261         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 262         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 263         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 264         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 265
 266         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 267         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 268         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 269         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 270         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 271
 272         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 273         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 274         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 275         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 276         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 277
 278         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 279         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 280         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 281         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 282         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 283
 284         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 285         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 286         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 287         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 288         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 289 };
 290
 291 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 292                                                          bool is_ddr3,
 293                                                          int fsb,
 294                                                          int mem)
 295 {
 296         const struct cxsr_latency *latency;
 297         int i;
 298
 299         if (fsb == 0 || mem == 0)
 300                 return NULL;
 301
 302         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 303                 latency = &cxsr_latency_table[i];
 304                 if (is_desktop == latency->is_desktop &&
 305                     is_ddr3 == latency->is_ddr3 &&
 306                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 307                         return latency;
 308         }
 309
 310         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 311
 312         return NULL;
 313 }
 314
 315 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 316 {
 317         u32 val;
 318
 319         vlv_punit_get(dev_priv);
 320
 321         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 322         if (enable)
 323                 val &= ~FORCE_DDR_HIGH_FREQ;
 324         else
 325                 val |= FORCE_DDR_HIGH_FREQ;
 326         val &= ~FORCE_DDR_LOW_FREQ;
 327         val |= FORCE_DDR_FREQ_REQ_ACK;
 328         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 329
 330         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 331                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 332                 drm_err(&dev_priv->drm,
 333                         "timed out waiting for Punit DDR DVFS request\n");
 334
 335         vlv_punit_put(dev_priv);
 336 }
 337
 338 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 339 {
 340         u32 val;
 341
 342         vlv_punit_get(dev_priv);
 343
 344         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 345         if (enable)
 346                 val |= DSP_MAXFIFO_PM5_ENABLE;
 347         else
 348                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 349         vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
 350
 351         vlv_punit_put(dev_priv);
 352 }
 353
 354 #define FW_WM(value, plane) \
 355         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 356
 357 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 358 {
 359         bool was_enabled;
 360         u32 val;
 361
 362         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 363                 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 364                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 365                 POSTING_READ(FW_BLC_SELF_VLV);
 366         } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
 367                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 368                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 369                 POSTING_READ(FW_BLC_SELF);
 370         } else if (IS_PINEVIEW(dev_priv)) {
 371                 val = I915_READ(DSPFW3);
 372                 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
 373                 if (enable)
 374                         val |= PINEVIEW_SELF_REFRESH_EN;
 375                 else
 376                         val &= ~PINEVIEW_SELF_REFRESH_EN;
 377                 I915_WRITE(DSPFW3, val);
 378                 POSTING_READ(DSPFW3);
 379         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 380                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 381                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 382                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 383                 I915_WRITE(FW_BLC_SELF, val);
 384                 POSTING_READ(FW_BLC_SELF);
 385         } else if (IS_I915GM(dev_priv)) {
 386                 /*
 387                  * FIXME can't find a bit like this for 915G, and
 388                  * and yet it does have the related watermark in
 389                  * FW_BLC_SELF. What's going on?
 390                  */
 391                 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
 392                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 393                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 394                 I915_WRITE(INSTPM, val);
 395                 POSTING_READ(INSTPM);
 396         } else {
 397                 return false;
 398         }
 399
 400         trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
 401
 402         drm_dbg_kms(&dev_priv->drm, "memory self-refresh is %s (was %s)\n",
 403                     enableddisabled(enable),
 404                     enableddisabled(was_enabled));
 405
 406         return was_enabled;
 407 }
 408
 409 /**
 410  * intel_set_memory_cxsr - Configure CxSR state
 411  * @dev_priv: i915 device
 412  * @enable: Allow vs. disallow CxSR
 413  *
 414  * Allow or disallow the system to enter a special CxSR
 415  * (C-state self refresh) state. What typically happens in CxSR mode
 416  * is that several display FIFOs may get combined into a single larger
 417  * FIFO for a particular plane (so called max FIFO mode) to allow the
 418  * system to defer memory fetches longer, and the memory will enter
 419  * self refresh.
 420  *
 421  * Note that enabling CxSR does not guarantee that the system enter
 422  * this special mode, nor does it guarantee that the system stays
 423  * in that mode once entered. So this just allows/disallows the system
 424  * to autonomously utilize the CxSR mode. Other factors such as core
 425  * C-states will affect when/if the system actually enters/exits the
 426  * CxSR mode.
 427  *
 428  * Note that on VLV/CHV this actually only controls the max FIFO mode,
 429  * and the system is free to enter/exit memory self refresh at any time
 430  * even when the use of CxSR has been disallowed.
 431  *
 432  * While the system is actually in the CxSR/max FIFO mode, some plane
 433  * control registers will not get latched on vblank. Thus in order to
 434  * guarantee the system will respond to changes in the plane registers
 435  * we must always disallow CxSR prior to making changes to those registers.
 436  * Unfortunately the system will re-evaluate the CxSR conditions at
 437  * frame start which happens after vblank start (which is when the plane
 438  * registers would get latched), so we can't proceed with the plane update
 439  * during the same frame where we disallowed CxSR.
 440  *
 441  * Certain platforms also have a deeper HPLL SR mode. Fortunately the
 442  * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
 443  * the hardware w.r.t. HPLL SR when writing to plane registers.
 444  * Disallowing just CxSR is sufficient.
 445  */
 446 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 447 {
 448         bool ret;
 449
 450         mutex_lock(&dev_priv->wm.wm_mutex);
 451         ret = _intel_set_memory_cxsr(dev_priv, enable);
 452         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 453                 dev_priv->wm.vlv.cxsr = enable;
 454         else if (IS_G4X(dev_priv))
 455                 dev_priv->wm.g4x.cxsr = enable;
 456         mutex_unlock(&dev_priv->wm.wm_mutex);
 457
 458         return ret;
 459 }
 460
 461 /*
 462  * Latency for FIFO fetches is dependent on several factors:
 463  *   - memory configuration (speed, channels)
 464  *   - chipset
 465  *   - current MCH state
 466  * It can be fairly high in some situations, so here we assume a fairly
 467  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 468  * set this value too high, the FIFO will fetch frequently to stay full)
 469  * and power consumption (set it too low to save power and we might see
 470  * FIFO underruns and display "flicker").
 471  *
 472  * A value of 5us seems to be a good balance; safe for very low end
 473  * platforms but not overly aggressive on lower latency configs.
 474  */
 475 static const int pessimal_latency_ns = 5000;
 476
 477 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 478         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 479
 480 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 481 {
 482         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 483         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 484         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
 485         enum pipe pipe = crtc->pipe;
 486         int sprite0_start, sprite1_start;
 487         u32 dsparb, dsparb2, dsparb3;
 488
 489         switch (pipe) {
 490         case PIPE_A:
 491                 dsparb = I915_READ(DSPARB);
 492                 dsparb2 = I915_READ(DSPARB2);
 493                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 494                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 495                 break;
 496         case PIPE_B:
 497                 dsparb = I915_READ(DSPARB);
 498                 dsparb2 = I915_READ(DSPARB2);
 499                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 500                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 501                 break;
 502         case PIPE_C:
 503                 dsparb2 = I915_READ(DSPARB2);
 504                 dsparb3 = I915_READ(DSPARB3);
 505                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 506                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 507                 break;
 508         default:
 509                 MISSING_CASE(pipe);
 510                 return;
 511         }
 512
 513         fifo_state->plane[PLANE_PRIMARY] = sprite0_start;
 514         fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start;
 515         fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start;
 516         fifo_state->plane[PLANE_CURSOR] = 63;
 517 }
 518
 519 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
 520                               enum i9xx_plane_id i9xx_plane)
 521 {
 522         u32 dsparb = I915_READ(DSPARB);
 523         int size;
 524
 525         size = dsparb & 0x7f;
 526         if (i9xx_plane == PLANE_B)
 527                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 528
 529         drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
 530                     dsparb, plane_name(i9xx_plane), size);
 531
 532         return size;
 533 }
 534
 535 static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
 536                               enum i9xx_plane_id i9xx_plane)
 537 {
 538         u32 dsparb = I915_READ(DSPARB);
 539         int size;
 540
 541         size = dsparb & 0x1ff;
 542         if (i9xx_plane == PLANE_B)
 543                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 544         size >>= 1; /* Convert to cachelines */
 545
 546         drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
 547                     dsparb, plane_name(i9xx_plane), size);
 548
 549         return size;
 550 }
 551
 552 static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
 553                               enum i9xx_plane_id i9xx_plane)
 554 {
 555         u32 dsparb = I915_READ(DSPARB);
 556         int size;
 557
 558         size = dsparb & 0x7f;
 559         size >>= 2; /* Convert to cachelines */
 560
 561         drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
 562                     dsparb, plane_name(i9xx_plane), size);
 563
 564         return size;
 565 }
 566
 567 /* Pineview has different values for various configs */
 568 static const struct intel_watermark_params pnv_display_wm = {
 569         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 570         .max_wm = PINEVIEW_MAX_WM,
 571         .default_wm = PINEVIEW_DFT_WM,
 572         .guard_size = PINEVIEW_GUARD_WM,
 573         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 574 };
 575
 576 static const struct intel_watermark_params pnv_display_hplloff_wm = {
 577         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 578         .max_wm = PINEVIEW_MAX_WM,
 579         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 580         .guard_size = PINEVIEW_GUARD_WM,
 581         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 582 };
 583
 584 static const struct intel_watermark_params pnv_cursor_wm = {
 585         .fifo_size = PINEVIEW_CURSOR_FIFO,
 586         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 587         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 588         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 589         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 590 };
 591
 592 static const struct intel_watermark_params pnv_cursor_hplloff_wm = {
 593         .fifo_size = PINEVIEW_CURSOR_FIFO,
 594         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 595         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 596         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 597         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 598 };
 599
 600 static const struct intel_watermark_params i965_cursor_wm_info = {
 601         .fifo_size = I965_CURSOR_FIFO,
 602         .max_wm = I965_CURSOR_MAX_WM,
 603         .default_wm = I965_CURSOR_DFT_WM,
 604         .guard_size = 2,
 605         .cacheline_size = I915_FIFO_LINE_SIZE,
 606 };
 607
 608 static const struct intel_watermark_params i945_wm_info = {
 609         .fifo_size = I945_FIFO_SIZE,
 610         .max_wm = I915_MAX_WM,
 611         .default_wm = 1,
 612         .guard_size = 2,
 613         .cacheline_size = I915_FIFO_LINE_SIZE,
 614 };
 615
 616 static const struct intel_watermark_params i915_wm_info = {
 617         .fifo_size = I915_FIFO_SIZE,
 618         .max_wm = I915_MAX_WM,
 619         .default_wm = 1,
 620         .guard_size = 2,
 621         .cacheline_size = I915_FIFO_LINE_SIZE,
 622 };
 623
 624 static const struct intel_watermark_params i830_a_wm_info = {
 625         .fifo_size = I855GM_FIFO_SIZE,
 626         .max_wm = I915_MAX_WM,
 627         .default_wm = 1,
 628         .guard_size = 2,
 629         .cacheline_size = I830_FIFO_LINE_SIZE,
 630 };
 631
 632 static const struct intel_watermark_params i830_bc_wm_info = {
 633         .fifo_size = I855GM_FIFO_SIZE,
 634         .max_wm = I915_MAX_WM/2,
 635         .default_wm = 1,
 636         .guard_size = 2,
 637         .cacheline_size = I830_FIFO_LINE_SIZE,
 638 };
 639
 640 static const struct intel_watermark_params i845_wm_info = {
 641         .fifo_size = I830_FIFO_SIZE,
 642         .max_wm = I915_MAX_WM,
 643         .default_wm = 1,
 644         .guard_size = 2,
 645         .cacheline_size = I830_FIFO_LINE_SIZE,
 646 };
 647
 648 /**
 649  * intel_wm_method1 - Method 1 / "small buffer" watermark formula
 650  * @pixel_rate: Pipe pixel rate in kHz
 651  * @cpp: Plane bytes per pixel
 652  * @latency: Memory wakeup latency in 0.1us units
 653  *
 654  * Compute the watermark using the method 1 or "small buffer"
 655  * formula. The caller may additonally add extra cachelines
 656  * to account for TLB misses and clock crossings.
 657  *
 658  * This method is concerned with the short term drain rate
 659  * of the FIFO, ie. it does not account for blanking periods
 660  * which would effectively reduce the average drain rate across
 661  * a longer period. The name "small" refers to the fact the
 662  * FIFO is relatively small compared to the amount of data
 663  * fetched.
 664  *
 665  * The FIFO level vs. time graph might look something like:
 666  *
 667  *   |\   |\
 668  *   | \  | \
 669  * __---__---__ (- plane active, _ blanking)
 670  * -> time
 671  *
 672  * or perhaps like this:
 673  *
 674  *   |\|\  |\|\
 675  * __----__----__ (- plane active, _ blanking)
 676  * -> time
 677  *
 678  * Returns:
 679  * The watermark in bytes
 680  */
 681 static unsigned int intel_wm_method1(unsigned int pixel_rate,
 682                                      unsigned int cpp,
 683                                      unsigned int latency)
 684 {
 685         u64 ret;
 686
 687         ret = mul_u32_u32(pixel_rate, cpp * latency);
 688         ret = DIV_ROUND_UP_ULL(ret, 10000);
 689
 690         return ret;
 691 }
 692
 693 /**
 694  * intel_wm_method2 - Method 2 / "large buffer" watermark formula
 695  * @pixel_rate: Pipe pixel rate in kHz
 696  * @htotal: Pipe horizontal total
 697  * @width: Plane width in pixels
 698  * @cpp: Plane bytes per pixel
 699  * @latency: Memory wakeup latency in 0.1us units
 700  *
 701  * Compute the watermark using the method 2 or "large buffer"
 702  * formula. The caller may additonally add extra cachelines
 703  * to account for TLB misses and clock crossings.
 704  *
 705  * This method is concerned with the long term drain rate
 706  * of the FIFO, ie. it does account for blanking periods
 707  * which effectively reduce the average drain rate across
 708  * a longer period. The name "large" refers to the fact the
 709  * FIFO is relatively large compared to the amount of data
 710  * fetched.
 711  *
 712  * The FIFO level vs. time graph might look something like:
 713  *
 714  *    |\___       |\___
 715  *    |    \___   |    \___
 716  *    |        \  |        \
 717  * __ --__--__--__--__--__--__ (- plane active, _ blanking)
 718  * -> time
 719  *
 720  * Returns:
 721  * The watermark in bytes
 722  */
 723 static unsigned int intel_wm_method2(unsigned int pixel_rate,
 724                                      unsigned int htotal,
 725                                      unsigned int width,
 726                                      unsigned int cpp,
 727                                      unsigned int latency)
 728 {
 729         unsigned int ret;
 730
 731         /*
 732          * FIXME remove once all users are computing
 733          * watermarks in the correct place.
 734          */
 735         if (WARN_ON_ONCE(htotal == 0))
 736                 htotal = 1;
 737
 738         ret = (latency * pixel_rate) / (htotal * 10000);
 739         ret = (ret + 1) * width * cpp;
 740
 741         return ret;
 742 }
 743
 744 /**
 745  * intel_calculate_wm - calculate watermark level
 746  * @pixel_rate: pixel clock
 747  * @wm: chip FIFO params
 748  * @fifo_size: size of the FIFO buffer
 749  * @cpp: bytes per pixel
 750  * @latency_ns: memory latency for the platform
 751  *
 752  * Calculate the watermark level (the level at which the display plane will
 753  * start fetching from memory again).  Each chip has a different display
 754  * FIFO size and allocation, so the caller needs to figure that out and pass
 755  * in the correct intel_watermark_params structure.
 756  *
 757  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 758  * on the pixel size.  When it reaches the watermark level, it'll start
 759  * fetching FIFO line sized based chunks from memory until the FIFO fills
 760  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 761  * will occur, and a display engine hang could result.
 762  */
 763 static unsigned int intel_calculate_wm(int pixel_rate,
 764                                        const struct intel_watermark_params *wm,
 765                                        int fifo_size, int cpp,
 766                                        unsigned int latency_ns)
 767 {
 768         int entries, wm_size;
 769
 770         /*
 771          * Note: we need to make sure we don't overflow for various clock &
 772          * latency values.
 773          * clocks go from a few thousand to several hundred thousand.
 774          * latency is usually a few thousand
 775          */
 776         entries = intel_wm_method1(pixel_rate, cpp,
 777                                    latency_ns / 100);
 778         entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
 779                 wm->guard_size;
 780         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries);
 781
 782         wm_size = fifo_size - entries;
 783         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
 784
 785         /* Don't promote wm_size to unsigned... */
 786         if (wm_size > wm->max_wm)
 787                 wm_size = wm->max_wm;
 788         if (wm_size <= 0)
 789                 wm_size = wm->default_wm;
 790
 791         /*
 792          * Bspec seems to indicate that the value shouldn't be lower than
 793          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 794          * Lets go for 8 which is the burst size since certain platforms
 795          * already use a hardcoded 8 (which is what the spec says should be
 796          * done).
 797          */
 798         if (wm_size <= 8)
 799                 wm_size = 8;
 800
 801         return wm_size;
 802 }
 803
 804 static bool is_disabling(int old, int new, int threshold)
 805 {
 806         return old >= threshold && new < threshold;
 807 }
 808
 809 static bool is_enabling(int old, int new, int threshold)
 810 {
 811         return old < threshold && new >= threshold;
 812 }
 813
 814 static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
 815 {
 816         return dev_priv->wm.max_level + 1;
 817 }
 818
 819 static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
 820                                    const struct intel_plane_state *plane_state)
 821 {
 822         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 823
 824         /* FIXME check the 'enable' instead */
 825         if (!crtc_state->hw.active)
 826                 return false;
 827
 828         /*
 829          * Treat cursor with fb as always visible since cursor updates
 830          * can happen faster than the vrefresh rate, and the current
 831          * watermark code doesn't handle that correctly. Cursor updates
 832          * which set/clear the fb or change the cursor size are going
 833          * to get throttled by intel_legacy_cursor_update() to work
 834          * around this problem with the watermark code.
 835          */
 836         if (plane->id == PLANE_CURSOR)
 837                 return plane_state->hw.fb != NULL;
 838         else
 839                 return plane_state->uapi.visible;
 840 }
 841
 842 static bool intel_crtc_active(struct intel_crtc *crtc)
 843 {
 844         /* Be paranoid as we can arrive here with only partial
 845          * state retrieved from the hardware during setup.
 846          *
 847          * We can ditch the adjusted_mode.crtc_clock check as soon
 848          * as Haswell has gained clock readout/fastboot support.
 849          *
 850          * We can ditch the crtc->primary->state->fb check as soon as we can
 851          * properly reconstruct framebuffers.
 852          *
 853          * FIXME: The intel_crtc->active here should be switched to
 854          * crtc->state->active once we have proper CRTC states wired up
 855          * for atomic.
 856          */
 857         return crtc->active && crtc->base.primary->state->fb &&
 858                 crtc->config->hw.adjusted_mode.crtc_clock;
 859 }
 860
 861 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 862 {
 863         struct intel_crtc *crtc, *enabled = NULL;
 864
 865         for_each_intel_crtc(&dev_priv->drm, crtc) {
 866                 if (intel_crtc_active(crtc)) {
 867                         if (enabled)
 868                                 return NULL;
 869                         enabled = crtc;
 870                 }
 871         }
 872
 873         return enabled;
 874 }
 875
 876 static void pnv_update_wm(struct intel_crtc *unused_crtc)
 877 {
 878         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 879         struct intel_crtc *crtc;
 880         const struct cxsr_latency *latency;
 881         u32 reg;
 882         unsigned int wm;
 883
 884         latency = intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
 885                                          dev_priv->is_ddr3,
 886                                          dev_priv->fsb_freq,
 887                                          dev_priv->mem_freq);
 888         if (!latency) {
 889                 drm_dbg_kms(&dev_priv->drm,
 890                             "Unknown FSB/MEM found, disable CxSR\n");
 891                 intel_set_memory_cxsr(dev_priv, false);
 892                 return;
 893         }
 894
 895         crtc = single_enabled_crtc(dev_priv);
 896         if (crtc) {
 897                 const struct drm_display_mode *adjusted_mode =
 898                         &crtc->config->hw.adjusted_mode;
 899                 const struct drm_framebuffer *fb =
 900                         crtc->base.primary->state->fb;
 901                 int cpp = fb->format->cpp[0];
 902                 int clock = adjusted_mode->crtc_clock;
 903
 904                 /* Display SR */
 905                 wm = intel_calculate_wm(clock, &pnv_display_wm,
 906                                         pnv_display_wm.fifo_size,
 907                                         cpp, latency->display_sr);
 908                 reg = I915_READ(DSPFW1);
 909                 reg &= ~DSPFW_SR_MASK;
 910                 reg |= FW_WM(wm, SR);
 911                 I915_WRITE(DSPFW1, reg);
 912                 drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
 913
 914                 /* cursor SR */
 915                 wm = intel_calculate_wm(clock, &pnv_cursor_wm,
 916                                         pnv_display_wm.fifo_size,
 917                                         4, latency->cursor_sr);
 918                 reg = I915_READ(DSPFW3);
 919                 reg &= ~DSPFW_CURSOR_SR_MASK;
 920                 reg |= FW_WM(wm, CURSOR_SR);
 921                 I915_WRITE(DSPFW3, reg);
 922
 923                 /* Display HPLL off SR */
 924                 wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm,
 925                                         pnv_display_hplloff_wm.fifo_size,
 926                                         cpp, latency->display_hpll_disable);
 927                 reg = I915_READ(DSPFW3);
 928                 reg &= ~DSPFW_HPLL_SR_MASK;
 929                 reg |= FW_WM(wm, HPLL_SR);
 930                 I915_WRITE(DSPFW3, reg);
 931
 932                 /* cursor HPLL off SR */
 933                 wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm,
 934                                         pnv_display_hplloff_wm.fifo_size,
 935                                         4, latency->cursor_hpll_disable);
 936                 reg = I915_READ(DSPFW3);
 937                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 938                 reg |= FW_WM(wm, HPLL_CURSOR);
 939                 I915_WRITE(DSPFW3, reg);
 940                 drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
 941
 942                 intel_set_memory_cxsr(dev_priv, true);
 943         } else {
 944                 intel_set_memory_cxsr(dev_priv, false);
 945         }
 946 }
 947
 948 /*
 949  * Documentation says:
 950  * "If the line size is small, the TLB fetches can get in the way of the
 951  *  data fetches, causing some lag in the pixel data return which is not
 952  *  accounted for in the above formulas. The following adjustment only
 953  *  needs to be applied if eight whole lines fit in the buffer at once.
 954  *  The WM is adjusted upwards by the difference between the FIFO size
 955  *  and the size of 8 whole lines. This adjustment is always performed
 956  *  in the actual pixel depth regardless of whether FBC is enabled or not."
 957  */
 958 static unsigned int g4x_tlb_miss_wa(int fifo_size, int width, int cpp)
 959 {
 960         int tlb_miss = fifo_size * 64 - width * cpp * 8;
 961
 962         return max(0, tlb_miss);
 963 }
 964
 965 static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
 966                                 const struct g4x_wm_values *wm)
 967 {
 968         enum pipe pipe;
 969
 970         for_each_pipe(dev_priv, pipe)
 971                 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
 972
 973         I915_WRITE(DSPFW1,
 974                    FW_WM(wm->sr.plane, SR) |
 975                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 976                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 977                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
 978         I915_WRITE(DSPFW2,
 979                    (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
 980                    FW_WM(wm->sr.fbc, FBC_SR) |
 981                    FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
 982                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
 983                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 984                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
 985         I915_WRITE(DSPFW3,
 986                    (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
 987                    FW_WM(wm->sr.cursor, CURSOR_SR) |
 988                    FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
 989                    FW_WM(wm->hpll.plane, HPLL_SR));
 990
 991         POSTING_READ(DSPFW1);
 992 }
 993
 994 #define FW_WM_VLV(value, plane) \
 995         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 996
 997 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 998                                 const struct vlv_wm_values *wm)
 999 {
1000         enum pipe pipe;
1001
1002         for_each_pipe(dev_priv, pipe) {
1003                 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
1004
1005                 I915_WRITE(VLV_DDL(pipe),
1006                            (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
1007                            (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
1008                            (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
1009                            (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
1010         }
1011
1012         /*
1013          * Zero the (unused) WM1 watermarks, and also clear all the
1014          * high order bits so that there are no out of bounds values
1015          * present in the registers during the reprogramming.
1016          */
1017         I915_WRITE(DSPHOWM, 0);
1018         I915_WRITE(DSPHOWM1, 0);
1019         I915_WRITE(DSPFW4, 0);
1020         I915_WRITE(DSPFW5, 0);
1021         I915_WRITE(DSPFW6, 0);
1022
1023         I915_WRITE(DSPFW1,
1024                    FW_WM(wm->sr.plane, SR) |
1025                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
1026                    FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
1027                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
1028         I915_WRITE(DSPFW2,
1029                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
1030                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
1031                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
1032         I915_WRITE(DSPFW3,
1033                    FW_WM(wm->sr.cursor, CURSOR_SR));
1034
1035         if (IS_CHERRYVIEW(dev_priv)) {
1036                 I915_WRITE(DSPFW7_CHV,
1037                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1038                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1039                 I915_WRITE(DSPFW8_CHV,
1040                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
1041                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
1042                 I915_WRITE(DSPFW9_CHV,
1043                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
1044                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
1045                 I915_WRITE(DSPHOWM,
1046                            FW_WM(wm->sr.plane >> 9, SR_HI) |
1047                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
1048                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
1049                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
1050                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1051                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1052                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1053                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1054                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1055                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1056         } else {
1057                 I915_WRITE(DSPFW7,
1058                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1059                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1060                 I915_WRITE(DSPHOWM,
1061                            FW_WM(wm->sr.plane >> 9, SR_HI) |
1062                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1063                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1064                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1065                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1066                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1067                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1068         }
1069
1070         POSTING_READ(DSPFW1);
1071 }
1072
1073 #undef FW_WM_VLV
1074
1075 static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
1076 {
1077         /* all latencies in usec */
1078         dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
1079         dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
1080         dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
1081
1082         dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
1083 }
1084
1085 static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
1086 {
1087         /*
1088          * DSPCNTR[13] supposedly controls whether the
1089          * primary plane can use the FIFO space otherwise
1090          * reserved for the sprite plane. It's not 100% clear
1091          * what the actual FIFO size is, but it looks like we
1092          * can happily set both primary and sprite watermarks
1093          * up to 127 cachelines. So that would seem to mean
1094          * that either DSPCNTR[13] doesn't do anything, or that
1095          * the total FIFO is >= 256 cachelines in size. Either
1096          * way, we don't seem to have to worry about this
1097          * repartitioning as the maximum watermark value the
1098          * register can hold for each plane is lower than the
1099          * minimum FIFO size.
1100          */
1101         switch (plane_id) {
1102         case PLANE_CURSOR:
1103                 return 63;
1104         case PLANE_PRIMARY:
1105                 return level == G4X_WM_LEVEL_NORMAL ? 127 : 511;
1106         case PLANE_SPRITE0:
1107                 return level == G4X_WM_LEVEL_NORMAL ? 127 : 0;
1108         default:
1109                 MISSING_CASE(plane_id);
1110                 return 0;
1111         }
1112 }
1113
1114 static int g4x_fbc_fifo_size(int level)
1115 {
1116         switch (level) {
1117         case G4X_WM_LEVEL_SR:
1118                 return 7;
1119         case G4X_WM_LEVEL_HPLL:
1120                 return 15;
1121         default:
1122                 MISSING_CASE(level);
1123                 return 0;
1124         }
1125 }
1126
1127 static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
1128                           const struct intel_plane_state *plane_state,
1129                           int level)
1130 {
1131         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1132         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1133         const struct drm_display_mode *adjusted_mode =
1134                 &crtc_state->hw.adjusted_mode;
1135         unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
1136         unsigned int clock, htotal, cpp, width, wm;
1137
1138         if (latency == 0)
1139                 return USHRT_MAX;
1140
1141         if (!intel_wm_plane_visible(crtc_state, plane_state))
1142                 return 0;
1143
1144         cpp = plane_state->hw.fb->format->cpp[0];
1145
1146         /*
1147          * Not 100% sure which way ELK should go here as the
1148          * spec only says CL/CTG should assume 32bpp and BW
1149          * doesn't need to. But as these things followed the
1150          * mobile vs. desktop lines on gen3 as well, let's
1151          * assume ELK doesn't need this.
1152          *
1153          * The spec also fails to list such a restriction for
1154          * the HPLL watermark, which seems a little strange.
1155          * Let's use 32bpp for the HPLL watermark as well.
1156          */
1157         if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY &&
1158             level != G4X_WM_LEVEL_NORMAL)
1159                 cpp = max(cpp, 4u);
1160
1161         clock = adjusted_mode->crtc_clock;
1162         htotal = adjusted_mode->crtc_htotal;
1163
1164         width = drm_rect_width(&plane_state->uapi.dst);
1165
1166         if (plane->id == PLANE_CURSOR) {
1167                 wm = intel_wm_method2(clock, htotal, width, cpp, latency);
1168         } else if (plane->id == PLANE_PRIMARY &&
1169                    level == G4X_WM_LEVEL_NORMAL) {
1170                 wm = intel_wm_method1(clock, cpp, latency);
1171         } else {
1172                 unsigned int small, large;
1173
1174                 small = intel_wm_method1(clock, cpp, latency);
1175                 large = intel_wm_method2(clock, htotal, width, cpp, latency);
1176
1177                 wm = min(small, large);
1178         }
1179
1180         wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level),
1181                               width, cpp);
1182
1183         wm = DIV_ROUND_UP(wm, 64) + 2;
1184
1185         return min_t(unsigned int, wm, USHRT_MAX);
1186 }
1187
1188 static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1189                                  int level, enum plane_id plane_id, u16 value)
1190 {
1191         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1192         bool dirty = false;
1193
1194         for (; level < intel_wm_num_levels(dev_priv); level++) {
1195                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1196
1197                 dirty |= raw->plane[plane_id] != value;
1198                 raw->plane[plane_id] = value;
1199         }
1200
1201         return dirty;
1202 }
1203
1204 static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
1205                                int level, u16 value)
1206 {
1207         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1208         bool dirty = false;
1209
1210         /* NORMAL level doesn't have an FBC watermark */
1211         level = max(level, G4X_WM_LEVEL_SR);
1212
1213         for (; level < intel_wm_num_levels(dev_priv); level++) {
1214                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1215
1216                 dirty |= raw->fbc != value;
1217                 raw->fbc = value;
1218         }
1219
1220         return dirty;
1221 }
1222
1223 static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
1224                               const struct intel_plane_state *plane_state,
1225                               u32 pri_val);
1226
1227 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1228                                      const struct intel_plane_state *plane_state)
1229 {
1230         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1231         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1232         int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1233         enum plane_id plane_id = plane->id;
1234         bool dirty = false;
1235         int level;
1236
1237         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1238                 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1239                 if (plane_id == PLANE_PRIMARY)
1240                         dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0);
1241                 goto out;
1242         }
1243
1244         for (level = 0; level < num_levels; level++) {
1245                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1246                 int wm, max_wm;
1247
1248                 wm = g4x_compute_wm(crtc_state, plane_state, level);
1249                 max_wm = g4x_plane_fifo_size(plane_id, level);
1250
1251                 if (wm > max_wm)
1252                         break;
1253
1254                 dirty |= raw->plane[plane_id] != wm;
1255                 raw->plane[plane_id] = wm;
1256
1257                 if (plane_id != PLANE_PRIMARY ||
1258                     level == G4X_WM_LEVEL_NORMAL)
1259                         continue;
1260
1261                 wm = ilk_compute_fbc_wm(crtc_state, plane_state,
1262                                         raw->plane[plane_id]);
1263                 max_wm = g4x_fbc_fifo_size(level);
1264
1265                 /*
1266                  * FBC wm is not mandatory as we
1267                  * can always just disable its use.
1268                  */
1269                 if (wm > max_wm)
1270                         wm = USHRT_MAX;
1271
1272                 dirty |= raw->fbc != wm;
1273                 raw->fbc = wm;
1274         }
1275
1276         /* mark watermarks as invalid */
1277         dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1278
1279         if (plane_id == PLANE_PRIMARY)
1280                 dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
1281
1282  out:
1283         if (dirty) {
1284                 drm_dbg_kms(&dev_priv->drm,
1285                             "%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1286                             plane->base.name,
1287                             crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
1288                             crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
1289                             crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
1290
1291                 if (plane_id == PLANE_PRIMARY)
1292                         drm_dbg_kms(&dev_priv->drm,
1293                                     "FBC watermarks: SR=%d, HPLL=%d\n",
1294                                     crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
1295                                     crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
1296         }
1297
1298         return dirty;
1299 }
1300
1301 static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1302                                       enum plane_id plane_id, int level)
1303 {
1304         const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1305
1306         return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);
1307 }
1308
1309 static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
1310                                      int level)
1311 {
1312         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1313
1314         if (level > dev_priv->wm.max_level)
1315                 return false;
1316
1317         return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1318                 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1319                 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1320 }
1321
1322 /* mark all levels starting from 'level' as invalid */
1323 static void g4x_invalidate_wms(struct intel_crtc *crtc,
1324                                struct g4x_wm_state *wm_state, int level)
1325 {
1326         if (level <= G4X_WM_LEVEL_NORMAL) {
1327                 enum plane_id plane_id;
1328
1329                 for_each_plane_id_on_crtc(crtc, plane_id)
1330                         wm_state->wm.plane[plane_id] = USHRT_MAX;
1331         }
1332
1333         if (level <= G4X_WM_LEVEL_SR) {
1334                 wm_state->cxsr = false;
1335                 wm_state->sr.cursor = USHRT_MAX;
1336                 wm_state->sr.plane = USHRT_MAX;
1337                 wm_state->sr.fbc = USHRT_MAX;
1338         }
1339
1340         if (level <= G4X_WM_LEVEL_HPLL) {
1341                 wm_state->hpll_en = false;
1342                 wm_state->hpll.cursor = USHRT_MAX;
1343                 wm_state->hpll.plane = USHRT_MAX;
1344                 wm_state->hpll.fbc = USHRT_MAX;
1345         }
1346 }
1347
1348 static bool g4x_compute_fbc_en(const struct g4x_wm_state *wm_state,
1349                                int level)
1350 {
1351         if (level < G4X_WM_LEVEL_SR)
1352                 return false;
1353
1354         if (level >= G4X_WM_LEVEL_SR &&
1355             wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
1356                 return false;
1357
1358         if (level >= G4X_WM_LEVEL_HPLL &&
1359             wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
1360                 return false;
1361
1362         return true;
1363 }
1364
1365 static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1366 {
1367         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1368         struct intel_atomic_state *state =
1369                 to_intel_atomic_state(crtc_state->uapi.state);
1370         struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
1371         int num_active_planes = hweight8(crtc_state->active_planes &
1372                                          ~BIT(PLANE_CURSOR));
1373         const struct g4x_pipe_wm *raw;
1374         const struct intel_plane_state *old_plane_state;
1375         const struct intel_plane_state *new_plane_state;
1376         struct intel_plane *plane;
1377         enum plane_id plane_id;
1378         int i, level;
1379         unsigned int dirty = 0;
1380
1381         for_each_oldnew_intel_plane_in_state(state, plane,
1382                                              old_plane_state,
1383                                              new_plane_state, i) {
1384                 if (new_plane_state->hw.crtc != &crtc->base &&
1385                     old_plane_state->hw.crtc != &crtc->base)
1386                         continue;
1387
1388                 if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
1389                         dirty |= BIT(plane->id);
1390         }
1391
1392         if (!dirty)
1393                 return 0;
1394
1395         level = G4X_WM_LEVEL_NORMAL;
1396         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1397                 goto out;
1398
1399         raw = &crtc_state->wm.g4x.raw[level];
1400         for_each_plane_id_on_crtc(crtc, plane_id)
1401                 wm_state->wm.plane[plane_id] = raw->plane[plane_id];
1402
1403         level = G4X_WM_LEVEL_SR;
1404         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1405                 goto out;
1406
1407         raw = &crtc_state->wm.g4x.raw[level];
1408         wm_state->sr.plane = raw->plane[PLANE_PRIMARY];
1409         wm_state->sr.cursor = raw->plane[PLANE_CURSOR];
1410         wm_state->sr.fbc = raw->fbc;
1411
1412         wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);
1413
1414         level = G4X_WM_LEVEL_HPLL;
1415         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1416                 goto out;
1417
1418         raw = &crtc_state->wm.g4x.raw[level];
1419         wm_state->hpll.plane = raw->plane[PLANE_PRIMARY];
1420         wm_state->hpll.cursor = raw->plane[PLANE_CURSOR];
1421         wm_state->hpll.fbc = raw->fbc;
1422
1423         wm_state->hpll_en = wm_state->cxsr;
1424
1425         level++;
1426
1427  out:
1428         if (level == G4X_WM_LEVEL_NORMAL)
1429                 return -EINVAL;
1430
1431         /* invalidate the higher levels */
1432         g4x_invalidate_wms(crtc, wm_state, level);
1433
1434         /*
1435          * Determine if the FBC watermark(s) can be used. IF
1436          * this isn't the case we prefer to disable the FBC
1437          * watermark(s) rather than disable the SR/HPLL
1438          * level(s) entirely. 'level-1' is the highest valid
1439          * level here.
1440          */
1441         wm_state->fbc_en = g4x_compute_fbc_en(wm_state, level - 1);
1442
1443         return 0;
1444 }
1445
1446 static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
1447 {
1448         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1449         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450         struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
1451         const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
1452         struct intel_atomic_state *intel_state =
1453                 to_intel_atomic_state(new_crtc_state->uapi.state);
1454         const struct intel_crtc_state *old_crtc_state =
1455                 intel_atomic_get_old_crtc_state(intel_state, crtc);
1456         const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
1457         enum plane_id plane_id;
1458
1459         if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
1460                 *intermediate = *optimal;
1461
1462                 intermediate->cxsr = false;
1463                 intermediate->hpll_en = false;
1464                 goto out;
1465         }
1466
1467         intermediate->cxsr = optimal->cxsr && active->cxsr &&
1468                 !new_crtc_state->disable_cxsr;
1469         intermediate->hpll_en = optimal->hpll_en && active->hpll_en &&
1470                 !new_crtc_state->disable_cxsr;
1471         intermediate->fbc_en = optimal->fbc_en && active->fbc_en;
1472
1473         for_each_plane_id_on_crtc(crtc, plane_id) {
1474                 intermediate->wm.plane[plane_id] =
1475                         max(optimal->wm.plane[plane_id],
1476                             active->wm.plane[plane_id]);
1477
1478                 drm_WARN_ON(&dev_priv->drm, intermediate->wm.plane[plane_id] >
1479                             g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
1480         }
1481
1482         intermediate->sr.plane = max(optimal->sr.plane,
1483                                      active->sr.plane);
1484         intermediate->sr.cursor = max(optimal->sr.cursor,
1485                                       active->sr.cursor);
1486         intermediate->sr.fbc = max(optimal->sr.fbc,
1487                                    active->sr.fbc);
1488
1489         intermediate->hpll.plane = max(optimal->hpll.plane,
1490                                        active->hpll.plane);
1491         intermediate->hpll.cursor = max(optimal->hpll.cursor,
1492                                         active->hpll.cursor);
1493         intermediate->hpll.fbc = max(optimal->hpll.fbc,
1494                                      active->hpll.fbc);
1495
1496         drm_WARN_ON(&dev_priv->drm,
1497                     (intermediate->sr.plane >
1498                      g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||
1499                      intermediate->sr.cursor >
1500                      g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&
1501                     intermediate->cxsr);
1502         drm_WARN_ON(&dev_priv->drm,
1503                     (intermediate->sr.plane >
1504                      g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
1505                      intermediate->sr.cursor >
1506                      g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
1507                     intermediate->hpll_en);
1508
1509         drm_WARN_ON(&dev_priv->drm,
1510                     intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
1511                     intermediate->fbc_en && intermediate->cxsr);
1512         drm_WARN_ON(&dev_priv->drm,
1513                     intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
1514                     intermediate->fbc_en && intermediate->hpll_en);
1515
1516 out:
1517         /*
1518          * If our intermediate WM are identical to the final WM, then we can
1519          * omit the post-vblank programming; only update if it's different.
1520          */
1521         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
1522                 new_crtc_state->wm.need_postvbl_update = true;
1523
1524         return 0;
1525 }
1526
1527 static void g4x_merge_wm(struct drm_i915_private *dev_priv,
1528                          struct g4x_wm_values *wm)
1529 {
1530         struct intel_crtc *crtc;
1531         int num_active_pipes = 0;
1532
1533         wm->cxsr = true;
1534         wm->hpll_en = true;
1535         wm->fbc_en = true;
1536
1537         for_each_intel_crtc(&dev_priv->drm, crtc) {
1538                 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1539
1540                 if (!crtc->active)
1541                         continue;
1542
1543                 if (!wm_state->cxsr)
1544                         wm->cxsr = false;
1545                 if (!wm_state->hpll_en)
1546                         wm->hpll_en = false;
1547                 if (!wm_state->fbc_en)
1548                         wm->fbc_en = false;
1549
1550                 num_active_pipes++;
1551         }
1552
1553         if (num_active_pipes != 1) {
1554                 wm->cxsr = false;
1555                 wm->hpll_en = false;
1556                 wm->fbc_en = false;
1557         }
1558
1559         for_each_intel_crtc(&dev_priv->drm, crtc) {
1560                 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1561                 enum pipe pipe = crtc->pipe;
1562
1563                 wm->pipe[pipe] = wm_state->wm;
1564                 if (crtc->active && wm->cxsr)
1565                         wm->sr = wm_state->sr;
1566                 if (crtc->active && wm->hpll_en)
1567                         wm->hpll = wm_state->hpll;
1568         }
1569 }
1570
1571 static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
1572 {
1573         struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
1574         struct g4x_wm_values new_wm = {};
1575
1576         g4x_merge_wm(dev_priv, &new_wm);
1577
1578         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
1579                 return;
1580
1581         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1582                 _intel_set_memory_cxsr(dev_priv, false);
1583
1584         g4x_write_wm_values(dev_priv, &new_wm);
1585
1586         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1587                 _intel_set_memory_cxsr(dev_priv, true);
1588
1589         *old_wm = new_wm;
1590 }
1591
1592 static void g4x_initial_watermarks(struct intel_atomic_state *state,
1593                                    struct intel_crtc *crtc)
1594 {
1595         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1596         const struct intel_crtc_state *crtc_state =
1597                 intel_atomic_get_new_crtc_state(state, crtc);
1598
1599         mutex_lock(&dev_priv->wm.wm_mutex);
1600         crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
1601         g4x_program_watermarks(dev_priv);
1602         mutex_unlock(&dev_priv->wm.wm_mutex);
1603 }
1604
1605 static void g4x_optimize_watermarks(struct intel_atomic_state *state,
1606                                     struct intel_crtc *crtc)
1607 {
1608         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1609         const struct intel_crtc_state *crtc_state =
1610                 intel_atomic_get_new_crtc_state(state, crtc);
1611
1612         if (!crtc_state->wm.need_postvbl_update)
1613                 return;
1614
1615         mutex_lock(&dev_priv->wm.wm_mutex);
1616         crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
1617         g4x_program_watermarks(dev_priv);
1618         mutex_unlock(&dev_priv->wm.wm_mutex);
1619 }
1620
1621 /* latency must be in 0.1us units. */
1622 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
1623                                    unsigned int htotal,
1624                                    unsigned int width,
1625                                    unsigned int cpp,
1626                                    unsigned int latency)
1627 {
1628         unsigned int ret;
1629
1630         ret = intel_wm_method2(pixel_rate, htotal,
1631                                width, cpp, latency);
1632         ret = DIV_ROUND_UP(ret, 64);
1633
1634         return ret;
1635 }
1636
1637 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
1638 {
1639         /* all latencies in usec */
1640         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
1641
1642         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
1643
1644         if (IS_CHERRYVIEW(dev_priv)) {
1645                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
1646                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1647
1648                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
1649         }
1650 }
1651
1652 static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
1653                                 const struct intel_plane_state *plane_state,
1654                                 int level)
1655 {
1656         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1657         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1658         const struct drm_display_mode *adjusted_mode =
1659                 &crtc_state->hw.adjusted_mode;
1660         unsigned int clock, htotal, cpp, width, wm;
1661
1662         if (dev_priv->wm.pri_latency[level] == 0)
1663                 return USHRT_MAX;
1664
1665         if (!intel_wm_plane_visible(crtc_state, plane_state))
1666                 return 0;
1667
1668         cpp = plane_state->hw.fb->format->cpp[0];
1669         clock = adjusted_mode->crtc_clock;
1670         htotal = adjusted_mode->crtc_htotal;
1671         width = crtc_state->pipe_src_w;
1672
1673         if (plane->id == PLANE_CURSOR) {
1674                 /*
1675                  * FIXME the formula gives values that are
1676                  * too big for the cursor FIFO, and hence we
1677                  * would never be able to use cursors. For
1678                  * now just hardcode the watermark.
1679                  */
1680                 wm = 63;
1681         } else {
1682                 wm = vlv_wm_method2(clock, htotal, width, cpp,
1683                                     dev_priv->wm.pri_latency[level] * 10);
1684         }
1685
1686         return min_t(unsigned int, wm, USHRT_MAX);
1687 }
1688
1689 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
1690 {
1691         return (active_planes & (BIT(PLANE_SPRITE0) |
1692                                  BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1);
1693 }
1694
1695 static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
1696 {
1697         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1698         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1699         const struct g4x_pipe_wm *raw =
1700                 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
1701         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1702         unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1703         int num_active_planes = hweight8(active_planes);
1704         const int fifo_size = 511;
1705         int fifo_extra, fifo_left = fifo_size;
1706         int sprite0_fifo_extra = 0;
1707         unsigned int total_rate;
1708         enum plane_id plane_id;
1709
1710         /*
1711          * When enabling sprite0 after sprite1 has already been enabled
1712          * we tend to get an underrun unless sprite0 already has some
1713          * FIFO space allcoated. Hence we always allocate at least one
1714          * cacheline for sprite0 whenever sprite1 is enabled.
1715          *
1716          * All other plane enable sequences appear immune to this problem.
1717          */
1718         if (vlv_need_sprite0_fifo_workaround(active_planes))
1719                 sprite0_fifo_extra = 1;
1720
1721         total_rate = raw->plane[PLANE_PRIMARY] +
1722                 raw->plane[PLANE_SPRITE0] +
1723                 raw->plane[PLANE_SPRITE1] +
1724                 sprite0_fifo_extra;
1725
1726         if (total_rate > fifo_size)
1727                 return -EINVAL;
1728
1729         if (total_rate == 0)
1730                 total_rate = 1;
1731
1732         for_each_plane_id_on_crtc(crtc, plane_id) {
1733                 unsigned int rate;
1734
1735                 if ((active_planes & BIT(plane_id)) == 0) {
1736                         fifo_state->plane[plane_id] = 0;
1737                         continue;
1738                 }
1739
1740                 rate = raw->plane[plane_id];
1741                 fifo_state->plane[plane_id] = fifo_size * rate / total_rate;
1742                 fifo_left -= fifo_state->plane[plane_id];
1743         }
1744
1745         fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra;
1746         fifo_left -= sprite0_fifo_extra;
1747
1748         fifo_state->plane[PLANE_CURSOR] = 63;
1749
1750         fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1);
1751
1752         /* spread the remainder evenly */
1753         for_each_plane_id_on_crtc(crtc, plane_id) {
1754                 int plane_extra;
1755
1756                 if (fifo_left == 0)
1757                         break;
1758
1759                 if ((active_planes & BIT(plane_id)) == 0)
1760                         continue;
1761
1762                 plane_extra = min(fifo_extra, fifo_left);
1763                 fifo_state->plane[plane_id] += plane_extra;
1764                 fifo_left -= plane_extra;
1765         }
1766
1767         drm_WARN_ON(&dev_priv->drm, active_planes != 0 && fifo_left != 0);
1768
1769         /* give it all to the first plane if none are active */
1770         if (active_planes == 0) {
1771                 drm_WARN_ON(&dev_priv->drm, fifo_left != fifo_size);
1772                 fifo_state->plane[PLANE_PRIMARY] = fifo_left;
1773         }
1774
1775         return 0;
1776 }
1777
1778 /* mark all levels starting from 'level' as invalid */
1779 static void vlv_invalidate_wms(struct intel_crtc *crtc,
1780                                struct vlv_wm_state *wm_state, int level)
1781 {
1782         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1783
1784         for (; level < intel_wm_num_levels(dev_priv); level++) {
1785                 enum plane_id plane_id;
1786
1787                 for_each_plane_id_on_crtc(crtc, plane_id)
1788                         wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1789
1790                 wm_state->sr[level].cursor = USHRT_MAX;
1791                 wm_state->sr[level].plane = USHRT_MAX;
1792         }
1793 }
1794
1795 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1796 {
1797         if (wm > fifo_size)
1798                 return USHRT_MAX;
1799         else
1800                 return fifo_size - wm;
1801 }
1802
1803 /*
1804  * Starting from 'level' set all higher
1805  * levels to 'value' in the "raw" watermarks.
1806  */
1807 static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1808                                  int level, enum plane_id plane_id, u16 value)
1809 {
1810         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1811         int num_levels = intel_wm_num_levels(dev_priv);
1812         bool dirty = false;
1813
1814         for (; level < num_levels; level++) {
1815                 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1816
1817                 dirty |= raw->plane[plane_id] != value;
1818                 raw->plane[plane_id] = value;
1819         }
1820
1821         return dirty;
1822 }
1823
1824 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1825                                      const struct intel_plane_state *plane_state)
1826 {
1827         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1828         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1829         enum plane_id plane_id = plane->id;
1830         int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1831         int level;
1832         bool dirty = false;
1833
1834         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1835                 dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1836                 goto out;
1837         }
1838
1839         for (level = 0; level < num_levels; level++) {
1840                 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1841                 int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
1842                 int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
1843
1844                 if (wm > max_wm)
1845                         break;
1846
1847                 dirty |= raw->plane[plane_id] != wm;
1848                 raw->plane[plane_id] = wm;
1849         }
1850
1851         /* mark all higher levels as invalid */
1852         dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1853
1854 out:
1855         if (dirty)
1856                 drm_dbg_kms(&dev_priv->drm,
1857                             "%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
1858                             plane->base.name,
1859                             crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1860                             crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1861                             crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
1862
1863         return dirty;
1864 }
1865
1866 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1867                                       enum plane_id plane_id, int level)
1868 {
1869         const struct g4x_pipe_wm *raw =
1870                 &crtc_state->wm.vlv.raw[level];
1871         const struct vlv_fifo_state *fifo_state =
1872                 &crtc_state->wm.vlv.fifo_state;
1873
1874         return raw->plane[plane_id] <= fifo_state->plane[plane_id];
1875 }
1876
1877 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)
1878 {
1879         return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1880                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1881                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) &&
1882                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1883 }
1884
1885 static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1886 {
1887         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1888         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1889         struct intel_atomic_state *state =
1890                 to_intel_atomic_state(crtc_state->uapi.state);
1891         struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1892         const struct vlv_fifo_state *fifo_state =
1893                 &crtc_state->wm.vlv.fifo_state;
1894         int num_active_planes = hweight8(crtc_state->active_planes &
1895                                          ~BIT(PLANE_CURSOR));
1896         bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
1897         const struct intel_plane_state *old_plane_state;
1898         const struct intel_plane_state *new_plane_state;
1899         struct intel_plane *plane;
1900         enum plane_id plane_id;
1901         int level, ret, i;
1902         unsigned int dirty = 0;
1903
1904         for_each_oldnew_intel_plane_in_state(state, plane,
1905                                              old_plane_state,
1906                                              new_plane_state, i) {
1907                 if (new_plane_state->hw.crtc != &crtc->base &&
1908                     old_plane_state->hw.crtc != &crtc->base)
1909                         continue;
1910
1911                 if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
1912                         dirty |= BIT(plane->id);
1913         }
1914
1915         /*
1916          * DSPARB registers may have been reset due to the
1917          * power well being turned off. Make sure we restore
1918          * them to a consistent state even if no primary/sprite
1919          * planes are initially active.
1920          */
1921         if (needs_modeset)
1922                 crtc_state->fifo_changed = true;
1923
1924         if (!dirty)
1925                 return 0;
1926
1927         /* cursor changes don't warrant a FIFO recompute */
1928         if (dirty & ~BIT(PLANE_CURSOR)) {
1929                 const struct intel_crtc_state *old_crtc_state =
1930                         intel_atomic_get_old_crtc_state(state, crtc);
1931                 const struct vlv_fifo_state *old_fifo_state =
1932                         &old_crtc_state->wm.vlv.fifo_state;
1933
1934                 ret = vlv_compute_fifo(crtc_state);
1935                 if (ret)
1936                         return ret;
1937
1938                 if (needs_modeset ||
1939                     memcmp(old_fifo_state, fifo_state,
1940                            sizeof(*fifo_state)) != 0)
1941                         crtc_state->fifo_changed = true;
1942         }
1943
1944         /* initially allow all levels */
1945         wm_state->num_levels = intel_wm_num_levels(dev_priv);
1946         /*
1947          * Note that enabling cxsr with no primary/sprite planes
1948          * enabled can wedge the pipe. Hence we only allow cxsr
1949          * with exactly one enabled primary/sprite plane.
1950          */
1951         wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
1952
1953         for (level = 0; level < wm_state->num_levels; level++) {
1954                 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1955                 const int sr_fifo_size = INTEL_NUM_PIPES(dev_priv) * 512 - 1;
1956
1957                 if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
1958                         break;
1959
1960                 for_each_plane_id_on_crtc(crtc, plane_id) {
1961                         wm_state->wm[level].plane[plane_id] =
1962                                 vlv_invert_wm_value(raw->plane[plane_id],
1963                                                     fifo_state->plane[plane_id]);
1964                 }
1965
1966                 wm_state->sr[level].plane =
1967                         vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY],
1968                                                  raw->plane[PLANE_SPRITE0],
1969                                                  raw->plane[PLANE_SPRITE1]),
1970                                             sr_fifo_size);
1971
1972                 wm_state->sr[level].cursor =
1973                         vlv_invert_wm_value(raw->plane[PLANE_CURSOR],
1974                                             63);
1975         }
1976
1977         if (level == 0)
1978                 return -EINVAL;
1979
1980         /* limit to only levels we can actually handle */
1981         wm_state->num_levels = level;
1982
1983         /* invalidate the higher levels */
1984         vlv_invalidate_wms(crtc, wm_state, level);
1985
1986         return 0;
1987 }
1988
1989 #define VLV_FIFO(plane, value) \
1990         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1991
1992 static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
1993                                    struct intel_crtc *crtc)
1994 {
1995         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1996         struct intel_uncore *uncore = &dev_priv->uncore;
1997         const struct intel_crtc_state *crtc_state =
1998                 intel_atomic_get_new_crtc_state(state, crtc);
1999         const struct vlv_fifo_state *fifo_state =
2000                 &crtc_state->wm.vlv.fifo_state;
2001         int sprite0_start, sprite1_start, fifo_size;
2002         u32 dsparb, dsparb2, dsparb3;
2003
2004         if (!crtc_state->fifo_changed)
2005                 return;
2006
2007         sprite0_start = fifo_state->plane[PLANE_PRIMARY];
2008         sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;
2009         fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;
2010
2011         drm_WARN_ON(&dev_priv->drm, fifo_state->plane[PLANE_CURSOR] != 63);
2012         drm_WARN_ON(&dev_priv->drm, fifo_size != 511);
2013
2014         trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
2015
2016         /*
2017          * uncore.lock serves a double purpose here. It allows us to
2018          * use the less expensive I915_{READ,WRITE}_FW() functions, and
2019          * it protects the DSPARB registers from getting clobbered by
2020          * parallel updates from multiple pipes.
2021          *
2022          * intel_pipe_update_start() has already disabled interrupts
2023          * for us, so a plain spin_lock() is sufficient here.
2024          */
2025         spin_lock(&uncore->lock);
2026
2027         switch (crtc->pipe) {
2028         case PIPE_A:
2029                 dsparb = intel_uncore_read_fw(uncore, DSPARB);
2030                 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
2031
2032                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
2033                             VLV_FIFO(SPRITEB, 0xff));
2034                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
2035                            VLV_FIFO(SPRITEB, sprite1_start));
2036
2037                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
2038                              VLV_FIFO(SPRITEB_HI, 0x1));
2039                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
2040                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
2041
2042                 intel_uncore_write_fw(uncore, DSPARB, dsparb);
2043                 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2044                 break;
2045         case PIPE_B:
2046                 dsparb = intel_uncore_read_fw(uncore, DSPARB);
2047                 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
2048
2049                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
2050                             VLV_FIFO(SPRITED, 0xff));
2051                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
2052                            VLV_FIFO(SPRITED, sprite1_start));
2053
2054                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
2055                              VLV_FIFO(SPRITED_HI, 0xff));
2056                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
2057                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
2058
2059                 intel_uncore_write_fw(uncore, DSPARB, dsparb);
2060                 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2061                 break;
2062         case PIPE_C:
2063                 dsparb3 = intel_uncore_read_fw(uncore, DSPARB3);
2064                 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
2065
2066                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
2067                              VLV_FIFO(SPRITEF, 0xff));
2068                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
2069                             VLV_FIFO(SPRITEF, sprite1_start));
2070
2071                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
2072                              VLV_FIFO(SPRITEF_HI, 0xff));
2073                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
2074                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
2075
2076                 intel_uncore_write_fw(uncore, DSPARB3, dsparb3);
2077                 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2078                 break;
2079         default:
2080                 break;
2081         }
2082
2083         intel_uncore_posting_read_fw(uncore, DSPARB);
2084
2085         spin_unlock(&uncore->lock);
2086 }
2087
2088 #undef VLV_FIFO
2089
2090 static int vlv_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
2091 {
2092         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
2093         struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
2094         const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
2095         struct intel_atomic_state *intel_state =
2096                 to_intel_atomic_state(new_crtc_state->uapi.state);
2097         const struct intel_crtc_state *old_crtc_state =
2098                 intel_atomic_get_old_crtc_state(intel_state, crtc);
2099         const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
2100         int level;
2101
2102         if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
2103                 *intermediate = *optimal;
2104
2105                 intermediate->cxsr = false;
2106                 goto out;
2107         }
2108
2109         intermediate->num_levels = min(optimal->num_levels, active->num_levels);
2110         intermediate->cxsr = optimal->cxsr && active->cxsr &&
2111                 !new_crtc_state->disable_cxsr;
2112
2113         for (level = 0; level < intermediate->num_levels; level++) {
2114                 enum plane_id plane_id;
2115
2116                 for_each_plane_id_on_crtc(crtc, plane_id) {
2117                         intermediate->wm[level].plane[plane_id] =
2118                                 min(optimal->wm[level].plane[plane_id],
2119                                     active->wm[level].plane[plane_id]);
2120                 }
2121
2122                 intermediate->sr[level].plane = min(optimal->sr[level].plane,
2123                                                     active->sr[level].plane);
2124                 intermediate->sr[level].cursor = min(optimal->sr[level].cursor,
2125                                                      active->sr[level].cursor);
2126         }
2127
2128         vlv_invalidate_wms(crtc, intermediate, level);
2129
2130 out:
2131         /*
2132          * If our intermediate WM are identical to the final WM, then we can
2133          * omit the post-vblank programming; only update if it's different.
2134          */
2135         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
2136                 new_crtc_state->wm.need_postvbl_update = true;
2137
2138         return 0;
2139 }
2140
2141 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
2142                          struct vlv_wm_values *wm)
2143 {
2144         struct intel_crtc *crtc;
2145         int num_active_pipes = 0;
2146
2147         wm->level = dev_priv->wm.max_level;
2148         wm->cxsr = true;
2149
2150         for_each_intel_crtc(&dev_priv->drm, crtc) {
2151                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2152
2153                 if (!crtc->active)
2154                         continue;
2155
2156                 if (!wm_state->cxsr)
2157                         wm->cxsr = false;
2158
2159                 num_active_pipes++;
2160                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
2161         }
2162
2163         if (num_active_pipes != 1)
2164                 wm->cxsr = false;
2165
2166         if (num_active_pipes > 1)
2167                 wm->level = VLV_WM_LEVEL_PM2;
2168
2169         for_each_intel_crtc(&dev_priv->drm, crtc) {
2170                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2171                 enum pipe pipe = crtc->pipe;
2172
2173                 wm->pipe[pipe] = wm_state->wm[wm->level];
2174                 if (crtc->active && wm->cxsr)
2175                         wm->sr = wm_state->sr[wm->level];
2176
2177                 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
2178                 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
2179                 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
2180                 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
2181         }
2182 }
2183
2184 static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
2185 {
2186         struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
2187         struct vlv_wm_values new_wm = {};
2188
2189         vlv_merge_wm(dev_priv, &new_wm);
2190
2191         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
2192                 return;
2193
2194         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2195                 chv_set_memory_dvfs(dev_priv, false);
2196
2197         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2198                 chv_set_memory_pm5(dev_priv, false);
2199
2200         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
2201                 _intel_set_memory_cxsr(dev_priv, false);
2202
2203         vlv_write_wm_values(dev_priv, &new_wm);
2204
2205         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
2206                 _intel_set_memory_cxsr(dev_priv, true);
2207
2208         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2209                 chv_set_memory_pm5(dev_priv, true);
2210
2211         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2212                 chv_set_memory_dvfs(dev_priv, true);
2213
2214         *old_wm = new_wm;
2215 }
2216
2217 static void vlv_initial_watermarks(struct intel_atomic_state *state,
2218                                    struct intel_crtc *crtc)
2219 {
2220         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2221         const struct intel_crtc_state *crtc_state =
2222                 intel_atomic_get_new_crtc_state(state, crtc);
2223
2224         mutex_lock(&dev_priv->wm.wm_mutex);
2225         crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
2226         vlv_program_watermarks(dev_priv);
2227         mutex_unlock(&dev_priv->wm.wm_mutex);
2228 }
2229
2230 static void vlv_optimize_watermarks(struct intel_atomic_state *state,
2231                                     struct intel_crtc *crtc)
2232 {
2233         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2234         const struct intel_crtc_state *crtc_state =
2235                 intel_atomic_get_new_crtc_state(state, crtc);
2236
2237         if (!crtc_state->wm.need_postvbl_update)
2238                 return;
2239
2240         mutex_lock(&dev_priv->wm.wm_mutex);
2241         crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
2242         vlv_program_watermarks(dev_priv);
2243         mutex_unlock(&dev_priv->wm.wm_mutex);
2244 }
2245
2246 static void i965_update_wm(struct intel_crtc *unused_crtc)
2247 {
2248         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2249         struct intel_crtc *crtc;
2250         int srwm = 1;
2251         int cursor_sr = 16;
2252         bool cxsr_enabled;
2253
2254         /* Calc sr entries for one plane configs */
2255         crtc = single_enabled_crtc(dev_priv);
2256         if (crtc) {
2257                 /* self-refresh has much higher latency */
2258                 static const int sr_latency_ns = 12000;
2259                 const struct drm_display_mode *adjusted_mode =
2260                         &crtc->config->hw.adjusted_mode;
2261                 const struct drm_framebuffer *fb =
2262                         crtc->base.primary->state->fb;
2263                 int clock = adjusted_mode->crtc_clock;
2264                 int htotal = adjusted_mode->crtc_htotal;
2265                 int hdisplay = crtc->config->pipe_src_w;
2266                 int cpp = fb->format->cpp[0];
2267                 int entries;
2268
2269                 entries = intel_wm_method2(clock, htotal,
2270                                            hdisplay, cpp, sr_latency_ns / 100);
2271                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
2272                 srwm = I965_FIFO_SIZE - entries;
2273                 if (srwm < 0)
2274                         srwm = 1;
2275                 srwm &= 0x1ff;
2276                 drm_dbg_kms(&dev_priv->drm,
2277                             "self-refresh entries: %d, wm: %d\n",
2278                             entries, srwm);
2279
2280                 entries = intel_wm_method2(clock, htotal,
2281                                            crtc->base.cursor->state->crtc_w, 4,
2282                                            sr_latency_ns / 100);
2283                 entries = DIV_ROUND_UP(entries,
2284                                        i965_cursor_wm_info.cacheline_size) +
2285                         i965_cursor_wm_info.guard_size;
2286
2287                 cursor_sr = i965_cursor_wm_info.fifo_size - entries;
2288                 if (cursor_sr > i965_cursor_wm_info.max_wm)
2289                         cursor_sr = i965_cursor_wm_info.max_wm;
2290
2291                 drm_dbg_kms(&dev_priv->drm,
2292                             "self-refresh watermark: display plane %d "
2293                             "cursor %d\n", srwm, cursor_sr);
2294
2295                 cxsr_enabled = true;
2296         } else {
2297                 cxsr_enabled = false;
2298                 /* Turn off self refresh if both pipes are enabled */
2299                 intel_set_memory_cxsr(dev_priv, false);
2300         }
2301
2302         drm_dbg_kms(&dev_priv->drm,
2303                     "Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2304                     srwm);
2305
2306         /* 965 has limitations... */
2307         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
2308                    FW_WM(8, CURSORB) |
2309                    FW_WM(8, PLANEB) |
2310                    FW_WM(8, PLANEA));
2311         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
2312                    FW_WM(8, PLANEC_OLD));
2313         /* update cursor SR watermark */
2314         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
2315
2316         if (cxsr_enabled)
2317                 intel_set_memory_cxsr(dev_priv, true);
2318 }
2319
2320 #undef FW_WM
2321
2322 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
2323 {
2324         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2325         const struct intel_watermark_params *wm_info;
2326         u32 fwater_lo;
2327         u32 fwater_hi;
2328         int cwm, srwm = 1;
2329         int fifo_size;
2330         int planea_wm, planeb_wm;
2331         struct intel_crtc *crtc, *enabled = NULL;
2332
2333         if (IS_I945GM(dev_priv))
2334                 wm_info = &i945_wm_info;
2335         else if (!IS_GEN(dev_priv, 2))
2336                 wm_info = &i915_wm_info;
2337         else
2338                 wm_info = &i830_a_wm_info;
2339
2340         fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
2341         crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
2342         if (intel_crtc_active(crtc)) {
2343                 const struct drm_display_mode *adjusted_mode =
2344                         &crtc->config->hw.adjusted_mode;
2345                 const struct drm_framebuffer *fb =
2346                         crtc->base.primary->state->fb;
2347                 int cpp;
2348
2349                 if (IS_GEN(dev_priv, 2))
2350                         cpp = 4;
2351                 else
2352                         cpp = fb->format->cpp[0];
2353
2354                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2355                                                wm_info, fifo_size, cpp,
2356                                                pessimal_latency_ns);
2357                 enabled = crtc;
2358         } else {
2359                 planea_wm = fifo_size - wm_info->guard_size;
2360                 if (planea_wm > (long)wm_info->max_wm)
2361                         planea_wm = wm_info->max_wm;
2362         }
2363
2364         if (IS_GEN(dev_priv, 2))
2365                 wm_info = &i830_bc_wm_info;
2366
2367         fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
2368         crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
2369         if (intel_crtc_active(crtc)) {
2370                 const struct drm_display_mode *adjusted_mode =
2371                         &crtc->config->hw.adjusted_mode;
2372                 const struct drm_framebuffer *fb =
2373                         crtc->base.primary->state->fb;
2374                 int cpp;
2375
2376                 if (IS_GEN(dev_priv, 2))
2377                         cpp = 4;
2378                 else
2379                         cpp = fb->format->cpp[0];
2380
2381                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2382                                                wm_info, fifo_size, cpp,
2383                                                pessimal_latency_ns);
2384                 if (enabled == NULL)
2385                         enabled = crtc;
2386                 else
2387                         enabled = NULL;
2388         } else {
2389                 planeb_wm = fifo_size - wm_info->guard_size;
2390                 if (planeb_wm > (long)wm_info->max_wm)
2391                         planeb_wm = wm_info->max_wm;
2392         }
2393
2394         drm_dbg_kms(&dev_priv->drm,
2395                     "FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2396
2397         if (IS_I915GM(dev_priv) && enabled) {
2398                 struct drm_i915_gem_object *obj;
2399
2400                 obj = intel_fb_obj(enabled->base.primary->state->fb);
2401
2402                 /* self-refresh seems busted with untiled */
2403                 if (!i915_gem_object_is_tiled(obj))
2404                         enabled = NULL;
2405         }
2406
2407         /*
2408          * Overlay gets an aggressive default since video jitter is bad.
2409          */
2410         cwm = 2;
2411
2412         /* Play safe and disable self-refresh before adjusting watermarks. */
2413         intel_set_memory_cxsr(dev_priv, false);
2414
2415         /* Calc sr entries for one plane configs */
2416         if (HAS_FW_BLC(dev_priv) && enabled) {
2417                 /* self-refresh has much higher latency */
2418                 static const int sr_latency_ns = 6000;
2419                 const struct drm_display_mode *adjusted_mode =
2420                         &enabled->config->hw.adjusted_mode;
2421                 const struct drm_framebuffer *fb =
2422                         enabled->base.primary->state->fb;
2423                 int clock = adjusted_mode->crtc_clock;
2424                 int htotal = adjusted_mode->crtc_htotal;
2425                 int hdisplay = enabled->config->pipe_src_w;
2426                 int cpp;
2427                 int entries;
2428
2429                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2430                         cpp = 4;
2431                 else
2432                         cpp = fb->format->cpp[0];
2433
2434                 entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
2435                                            sr_latency_ns / 100);
2436                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
2437                 drm_dbg_kms(&dev_priv->drm,
2438                             "self-refresh entries: %d\n", entries);
2439                 srwm = wm_info->fifo_size - entries;
2440                 if (srwm < 0)
2441                         srwm = 1;
2442
2443                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
2444                         I915_WRITE(FW_BLC_SELF,
2445                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2446                 else
2447                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2448         }
2449
2450         drm_dbg_kms(&dev_priv->drm,
2451                     "Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2452                      planea_wm, planeb_wm, cwm, srwm);
2453
2454         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2455         fwater_hi = (cwm & 0x1f);
2456
2457         /* Set request length to 8 cachelines per fetch */
2458         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2459         fwater_hi = fwater_hi | (1 << 8);
2460
2461         I915_WRITE(FW_BLC, fwater_lo);
2462         I915_WRITE(FW_BLC2, fwater_hi);
2463
2464         if (enabled)
2465                 intel_set_memory_cxsr(dev_priv, true);
2466 }
2467
2468 static void i845_update_wm(struct intel_crtc *unused_crtc)
2469 {
2470         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2471         struct intel_crtc *crtc;
2472         const struct drm_display_mode *adjusted_mode;
2473         u32 fwater_lo;
2474         int planea_wm;
2475
2476         crtc = single_enabled_crtc(dev_priv);
2477         if (crtc == NULL)
2478                 return;
2479
2480         adjusted_mode = &crtc->config->hw.adjusted_mode;
2481         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2482                                        &i845_wm_info,
2483                                        dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
2484                                        4, pessimal_latency_ns);
2485         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2486         fwater_lo |= (3<<8) | planea_wm;
2487
2488         drm_dbg_kms(&dev_priv->drm,
2489                     "Setting FIFO watermarks - A: %d\n", planea_wm);
2490
2491         I915_WRITE(FW_BLC, fwater_lo);
2492 }
2493
2494 /* latency must be in 0.1us units. */
2495 static unsigned int ilk_wm_method1(unsigned int pixel_rate,
2496                                    unsigned int cpp,
2497                                    unsigned int latency)
2498 {
2499         unsigned int ret;
2500
2501         ret = intel_wm_method1(pixel_rate, cpp, latency);
2502         ret = DIV_ROUND_UP(ret, 64) + 2;
2503
2504         return ret;
2505 }
2506
2507 /* latency must be in 0.1us units. */
2508 static unsigned int ilk_wm_method2(unsigned int pixel_rate,
2509                                    unsigned int htotal,
2510                                    unsigned int width,
2511                                    unsigned int cpp,
2512                                    unsigned int latency)
2513 {
2514         unsigned int ret;
2515
2516         ret = intel_wm_method2(pixel_rate, htotal,
2517                                width, cpp, latency);
2518         ret = DIV_ROUND_UP(ret, 64) + 2;
2519
2520         return ret;
2521 }
2522
2523 static u32 ilk_wm_fbc(u32 pri_val, u32 horiz_pixels, u8 cpp)
2524 {
2525         /*
2526          * Neither of these should be possible since this function shouldn't be
2527          * called if the CRTC is off or the plane is invisible.  But let's be
2528          * extra paranoid to avoid a potential divide-by-zero if we screw up
2529          * elsewhere in the driver.
2530          */
2531         if (WARN_ON(!cpp))
2532                 return 0;
2533         if (WARN_ON(!horiz_pixels))
2534                 return 0;
2535
2536         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
2537 }
2538
2539 struct ilk_wm_maximums {
2540         u16 pri;
2541         u16 spr;
2542         u16 cur;
2543         u16 fbc;
2544 };
2545
2546 /*
2547  * For both WM_PIPE and WM_LP.
2548  * mem_value must be in 0.1us units.
2549  */
2550 static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
2551                               const struct intel_plane_state *plane_state,
2552                               u32 mem_value, bool is_lp)
2553 {
2554         u32 method1, method2;
2555         int cpp;
2556
2557         if (mem_value == 0)
2558                 return U32_MAX;
2559
2560         if (!intel_wm_plane_visible(crtc_state, plane_state))
2561                 return 0;
2562
2563         cpp = plane_state->hw.fb->format->cpp[0];
2564
2565         method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
2566
2567         if (!is_lp)
2568                 return method1;
2569
2570         method2 = ilk_wm_method2(crtc_state->pixel_rate,
2571                                  crtc_state->hw.adjusted_mode.crtc_htotal,
2572                                  drm_rect_width(&plane_state->uapi.dst),
2573                                  cpp, mem_value);
2574
2575         return min(method1, method2);
2576 }
2577
2578 /*
2579  * For both WM_PIPE and WM_LP.
2580  * mem_value must be in 0.1us units.
2581  */
2582 static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
2583                               const struct intel_plane_state *plane_state,
2584                               u32 mem_value)
2585 {
2586         u32 method1, method2;
2587         int cpp;
2588
2589         if (mem_value == 0)
2590                 return U32_MAX;
2591
2592         if (!intel_wm_plane_visible(crtc_state, plane_state))
2593                 return 0;
2594
2595         cpp = plane_state->hw.fb->format->cpp[0];
2596
2597         method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
2598         method2 = ilk_wm_method2(crtc_state->pixel_rate,
2599                                  crtc_state->hw.adjusted_mode.crtc_htotal,
2600                                  drm_rect_width(&plane_state->uapi.dst),
2601                                  cpp, mem_value);
2602         return min(method1, method2);
2603 }
2604
2605 /*
2606  * For both WM_PIPE and WM_LP.
2607  * mem_value must be in 0.1us units.
2608  */
2609 static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
2610                               const struct intel_plane_state *plane_state,
2611                               u32 mem_value)
2612 {
2613         int cpp;
2614
2615         if (mem_value == 0)
2616                 return U32_MAX;
2617
2618         if (!intel_wm_plane_visible(crtc_state, plane_state))
2619                 return 0;
2620
2621         cpp = plane_state->hw.fb->format->cpp[0];
2622
2623         return ilk_wm_method2(crtc_state->pixel_rate,
2624                               crtc_state->hw.adjusted_mode.crtc_htotal,
2625                               drm_rect_width(&plane_state->uapi.dst),
2626                               cpp, mem_value);
2627 }
2628
2629 /* Only for WM_LP. */
2630 static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
2631                               const struct intel_plane_state *plane_state,
2632                               u32 pri_val)
2633 {
2634         int cpp;
2635
2636         if (!intel_wm_plane_visible(crtc_state, plane_state))
2637                 return 0;
2638
2639         cpp = plane_state->hw.fb->format->cpp[0];
2640
2641         return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->uapi.dst),
2642                           cpp);
2643 }
2644
2645 static unsigned int
2646 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
2647 {
2648         if (INTEL_GEN(dev_priv) >= 8)
2649                 return 3072;
2650         else if (INTEL_GEN(dev_priv) >= 7)
2651                 return 768;
2652         else
2653                 return 512;
2654 }
2655
2656 static unsigned int
2657 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
2658                      int level, bool is_sprite)
2659 {
2660         if (INTEL_GEN(dev_priv) >= 8)
2661                 /* BDW primary/sprite plane watermarks */
2662                 return level == 0 ? 255 : 2047;
2663         else if (INTEL_GEN(dev_priv) >= 7)
2664                 /* IVB/HSW primary/sprite plane watermarks */
2665                 return level == 0 ? 127 : 1023;
2666         else if (!is_sprite)
2667                 /* ILK/SNB primary plane watermarks */
2668                 return level == 0 ? 127 : 511;
2669         else
2670                 /* ILK/SNB sprite plane watermarks */
2671                 return level == 0 ? 63 : 255;
2672 }
2673
2674 static unsigned int
2675 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
2676 {
2677         if (INTEL_GEN(dev_priv) >= 7)
2678                 return level == 0 ? 63 : 255;
2679         else
2680                 return level == 0 ? 31 : 63;
2681 }
2682
2683 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
2684 {
2685         if (INTEL_GEN(dev_priv) >= 8)
2686                 return 31;
2687         else
2688                 return 15;
2689 }
2690
2691 /* Calculate the maximum primary/sprite plane watermark */
2692 static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
2693                                      int level,
2694                                      const struct intel_wm_config *config,
2695                                      enum intel_ddb_partitioning ddb_partitioning,
2696                                      bool is_sprite)
2697 {
2698         unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
2699
2700         /* if sprites aren't enabled, sprites get nothing */
2701         if (is_sprite && !config->sprites_enabled)
2702                 return 0;
2703
2704         /* HSW allows LP1+ watermarks even with multiple pipes */
2705         if (level == 0 || config->num_pipes_active > 1) {
2706                 fifo_size /= INTEL_NUM_PIPES(dev_priv);
2707
2708                 /*
2709                  * For some reason the non self refresh
2710                  * FIFO size is only half of the self
2711                  * refresh FIFO size on ILK/SNB.
2712                  */
2713                 if (INTEL_GEN(dev_priv) <= 6)
2714                         fifo_size /= 2;
2715         }
2716
2717         if (config->sprites_enabled) {
2718                 /* level 0 is always calculated with 1:1 split */
2719                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2720                         if (is_sprite)
2721                                 fifo_size *= 5;
2722                         fifo_size /= 6;
2723                 } else {
2724                         fifo_size /= 2;
2725                 }
2726         }
2727
2728         /* clamp to max that the registers can hold */
2729         return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
2730 }
2731
2732 /* Calculate the maximum cursor plane watermark */
2733 static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
2734                                       int level,
2735                                       const struct intel_wm_config *config)
2736 {
2737         /* HSW LP1+ watermarks w/ multiple pipes */
2738         if (level > 0 && config->num_pipes_active > 1)
2739                 return 64;
2740
2741         /* otherwise just report max that registers can hold */
2742         return ilk_cursor_wm_reg_max(dev_priv, level);
2743 }
2744
2745 static void ilk_compute_wm_maximums(const struct drm_i915_private *dev_priv,
2746                                     int level,
2747                                     const struct intel_wm_config *config,
2748                                     enum intel_ddb_partitioning ddb_partitioning,
2749                                     struct ilk_wm_maximums *max)
2750 {
2751         max->pri = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, false);
2752         max->spr = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, true);
2753         max->cur = ilk_cursor_wm_max(dev_priv, level, config);
2754         max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2755 }
2756
2757 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
2758                                         int level,
2759                                         struct ilk_wm_maximums *max)
2760 {
2761         max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
2762         max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
2763         max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
2764         max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2765 }
2766
2767 static bool ilk_validate_wm_level(int level,
2768                                   const struct ilk_wm_maximums *max,
2769                                   struct intel_wm_level *result)
2770 {
2771         bool ret;
2772
2773         /* already determined to be invalid? */
2774         if (!result->enable)
2775                 return false;
2776
2777         result->enable = result->pri_val <= max->pri &&
2778                          result->spr_val <= max->spr &&
2779                          result->cur_val <= max->cur;
2780
2781         ret = result->enable;
2782
2783         /*
2784          * HACK until we can pre-compute everything,
2785          * and thus fail gracefully if LP0 watermarks
2786          * are exceeded...
2787          */
2788         if (level == 0 && !result->enable) {
2789                 if (result->pri_val > max->pri)
2790                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2791                                       level, result->pri_val, max->pri);
2792                 if (result->spr_val > max->spr)
2793                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2794                                       level, result->spr_val, max->spr);
2795                 if (result->cur_val > max->cur)
2796                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2797                                       level, result->cur_val, max->cur);
2798
2799                 result->pri_val = min_t(u32, result->pri_val, max->pri);
2800                 result->spr_val = min_t(u32, result->spr_val, max->spr);
2801                 result->cur_val = min_t(u32, result->cur_val, max->cur);
2802                 result->enable = true;
2803         }
2804
2805         return ret;
2806 }
2807
2808 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2809                                  const struct intel_crtc *crtc,
2810                                  int level,
2811                                  struct intel_crtc_state *crtc_state,
2812                                  const struct intel_plane_state *pristate,
2813                                  const struct intel_plane_state *sprstate,
2814                                  const struct intel_plane_state *curstate,
2815                                  struct intel_wm_level *result)
2816 {
2817         u16 pri_latency = dev_priv->wm.pri_latency[level];
2818         u16 spr_latency = dev_priv->wm.spr_latency[level];
2819         u16 cur_latency = dev_priv->wm.cur_latency[level];
2820
2821         /* WM1+ latency values stored in 0.5us units */
2822         if (level > 0) {
2823                 pri_latency *= 5;
2824                 spr_latency *= 5;
2825                 cur_latency *= 5;
2826         }
2827
2828         if (pristate) {
2829                 result->pri_val = ilk_compute_pri_wm(crtc_state, pristate,
2830                                                      pri_latency, level);
2831                 result->fbc_val = ilk_compute_fbc_wm(crtc_state, pristate, result->pri_val);
2832         }
2833
2834         if (sprstate)
2835                 result->spr_val = ilk_compute_spr_wm(crtc_state, sprstate, spr_latency);
2836
2837         if (curstate)
2838                 result->cur_val = ilk_compute_cur_wm(crtc_state, curstate, cur_latency);
2839
2840         result->enable = true;
2841 }
2842
2843 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2844                                   u16 wm[8])
2845 {
2846         struct intel_uncore *uncore = &dev_priv->uncore;
2847
2848         if (INTEL_GEN(dev_priv) >= 9) {
2849                 u32 val;
2850                 int ret, i;
2851                 int level, max_level = ilk_wm_max_level(dev_priv);
2852
2853                 /* read the first set of memory latencies[0:3] */
2854                 val = 0; /* data0 to be programmed to 0 for first set */
2855                 ret = sandybridge_pcode_read(dev_priv,
2856                                              GEN9_PCODE_READ_MEM_LATENCY,
2857                                              &val, NULL);
2858
2859                 if (ret) {
2860                         drm_err(&dev_priv->drm,
2861                                 "SKL Mailbox read error = %d\n", ret);
2862                         return;
2863                 }
2864
2865                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2866                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2867                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2868                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2869                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2870                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2871                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2872
2873                 /* read the second set of memory latencies[4:7] */
2874                 val = 1; /* data0 to be programmed to 1 for second set */
2875                 ret = sandybridge_pcode_read(dev_priv,
2876                                              GEN9_PCODE_READ_MEM_LATENCY,
2877                                              &val, NULL);
2878                 if (ret) {
2879                         drm_err(&dev_priv->drm,
2880                                 "SKL Mailbox read error = %d\n", ret);
2881                         return;
2882                 }
2883
2884                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2885                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2886                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2887                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2888                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2889                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2890                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2891
2892                 /*
2893                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2894                  * need to be disabled. We make sure to sanitize the values out
2895                  * of the punit to satisfy this requirement.
2896                  */
2897                 for (level = 1; level <= max_level; level++) {
2898                         if (wm[level] == 0) {
2899                                 for (i = level + 1; i <= max_level; i++)
2900                                         wm[i] = 0;
2901                                 break;
2902                         }
2903                 }
2904
2905                 /*
2906                  * WaWmMemoryReadLatency:skl+,glk
2907                  *
2908                  * punit doesn't take into account the read latency so we need
2909                  * to add 2us to the various latency levels we retrieve from the
2910                  * punit when level 0 response data us 0us.
2911                  */
2912                 if (wm[0] == 0) {
2913                         wm[0] += 2;
2914                         for (level = 1; level <= max_level; level++) {
2915                                 if (wm[level] == 0)
2916                                         break;
2917                                 wm[level] += 2;
2918                         }
2919                 }
2920
2921                 /*
2922                  * WA Level-0 adjustment for 16GB DIMMs: SKL+
2923                  * If we could not get dimm info enable this WA to prevent from
2924                  * any underrun. If not able to get Dimm info assume 16GB dimm
2925                  * to avoid any underrun.
2926                  */
2927                 if (dev_priv->dram_info.is_16gb_dimm)
2928                         wm[0] += 1;
2929
2930         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2931                 u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
2932
2933                 wm[0] = (sskpd >> 56) & 0xFF;
2934                 if (wm[0] == 0)
2935                         wm[0] = sskpd & 0xF;
2936                 wm[1] = (sskpd >> 4) & 0xFF;
2937                 wm[2] = (sskpd >> 12) & 0xFF;
2938                 wm[3] = (sskpd >> 20) & 0x1FF;
2939                 wm[4] = (sskpd >> 32) & 0x1FF;
2940         } else if (INTEL_GEN(dev_priv) >= 6) {
2941                 u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
2942
2943                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2944                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2945                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2946                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2947         } else if (INTEL_GEN(dev_priv) >= 5) {
2948                 u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
2949
2950                 /* ILK primary LP0 latency is 700 ns */
2951                 wm[0] = 7;
2952                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2953                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2954         } else {
2955                 MISSING_CASE(INTEL_DEVID(dev_priv));
2956         }
2957 }
2958
2959 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2960                                        u16 wm[5])
2961 {
2962         /* ILK sprite LP0 latency is 1300 ns */
2963         if (IS_GEN(dev_priv, 5))
2964                 wm[0] = 13;
2965 }
2966
2967 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2968                                        u16 wm[5])
2969 {
2970         /* ILK cursor LP0 latency is 1300 ns */
2971         if (IS_GEN(dev_priv, 5))
2972                 wm[0] = 13;
2973 }
2974
2975 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2976 {
2977         /* how many WM levels are we expecting */
2978         if (INTEL_GEN(dev_priv) >= 9)
2979                 return 7;
2980         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2981                 return 4;
2982         else if (INTEL_GEN(dev_priv) >= 6)
2983                 return 3;
2984         else
2985                 return 2;
2986 }
2987
2988 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2989                                    const char *name,
2990                                    const u16 wm[8])
2991 {
2992         int level, max_level = ilk_wm_max_level(dev_priv);
2993
2994         for (level = 0; level <= max_level; level++) {
2995                 unsigned int latency = wm[level];
2996
2997                 if (latency == 0) {
2998                         drm_dbg_kms(&dev_priv->drm,
2999                                     "%s WM%d latency not provided\n",
3000                                     name, level);
3001                         continue;
3002                 }
3003
3004                 /*
3005                  * - latencies are in us on gen9.
3006                  * - before then, WM1+ latency values are in 0.5us units
3007                  */
3008                 if (INTEL_GEN(dev_priv) >= 9)
3009                         latency *= 10;
3010                 else if (level > 0)
3011                         latency *= 5;
3012
3013                 drm_dbg_kms(&dev_priv->drm,
3014                             "%s WM%d latency %u (%u.%u usec)\n", name, level,
3015                             wm[level], latency / 10, latency % 10);
3016         }
3017 }
3018
3019 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
3020                                     u16 wm[5], u16 min)
3021 {
3022         int level, max_level = ilk_wm_max_level(dev_priv);
3023
3024         if (wm[0] >= min)
3025                 return false;
3026
3027         wm[0] = max(wm[0], min);
3028         for (level = 1; level <= max_level; level++)
3029                 wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5));
3030
3031         return true;
3032 }
3033
3034 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
3035 {
3036         bool changed;
3037
3038         /*
3039          * The BIOS provided WM memory latency values are often
3040          * inadequate for high resolution displays. Adjust them.
3041          */
3042         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
3043                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
3044                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
3045
3046         if (!changed)
3047                 return;
3048
3049         drm_dbg_kms(&dev_priv->drm,
3050                     "WM latency values increased to avoid potential underruns\n");
3051         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3052         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3053         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3054 }
3055
3056 static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
3057 {
3058         /*
3059          * On some SNB machines (Thinkpad X220 Tablet at least)
3060          * LP3 usage can cause vblank interrupts to be lost.
3061          * The DEIIR bit will go high but it looks like the CPU
3062          * never gets interrupted.
3063          *
3064          * It's not clear whether other interrupt source could
3065          * be affected or if this is somehow limited to vblank
3066          * interrupts only. To play it safe we disable LP3
3067          * watermarks entirely.
3068          */
3069         if (dev_priv->wm.pri_latency[3] == 0 &&
3070             dev_priv->wm.spr_latency[3] == 0 &&
3071             dev_priv->wm.cur_latency[3] == 0)
3072                 return;
3073
3074         dev_priv->wm.pri_latency[3] = 0;
3075         dev_priv->wm.spr_latency[3] = 0;
3076         dev_priv->wm.cur_latency[3] = 0;
3077
3078         drm_dbg_kms(&dev_priv->drm,
3079                     "LP3 watermarks disabled due to potential for lost interrupts\n");
3080         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3081         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3082         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3083 }
3084
3085 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
3086 {
3087         intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
3088
3089         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
3090                sizeof(dev_priv->wm.pri_latency));
3091         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
3092                sizeof(dev_priv->wm.pri_latency));
3093
3094         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
3095         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
3096
3097         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3098         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3099         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3100
3101         if (IS_GEN(dev_priv, 6)) {
3102                 snb_wm_latency_quirk(dev_priv);
3103                 snb_wm_lp3_irq_quirk(dev_priv);
3104         }
3105 }
3106
3107 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
3108 {
3109         intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
3110         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
3111 }
3112
3113 static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
3114                                  struct intel_pipe_wm *pipe_wm)
3115 {
3116         /* LP0 watermark maximums depend on this pipe alone */
3117         const struct intel_wm_config config = {
3118                 .num_pipes_active = 1,
3119                 .sprites_enabled = pipe_wm->sprites_enabled,
3120                 .sprites_scaled = pipe_wm->sprites_scaled,
3121         };
3122         struct ilk_wm_maximums max;
3123
3124         /* LP0 watermarks always use 1/2 DDB partitioning */
3125         ilk_compute_wm_maximums(dev_priv, 0, &config, INTEL_DDB_PART_1_2, &max);
3126
3127         /* At least LP0 must be valid */
3128         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
3129                 drm_dbg_kms(&dev_priv->drm, "LP0 watermark invalid\n");
3130                 return false;
3131         }
3132
3133         return true;
3134 }
3135
3136 /* Compute new watermarks for the pipe */
3137 static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
3138 {
3139         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3140         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3141         struct intel_pipe_wm *pipe_wm;
3142         struct intel_plane *plane;
3143         const struct intel_plane_state *plane_state;
3144         const struct intel_plane_state *pristate = NULL;
3145         const struct intel_plane_state *sprstate = NULL;
3146         const struct intel_plane_state *curstate = NULL;
3147         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
3148         struct ilk_wm_maximums max;
3149
3150         pipe_wm = &crtc_state->wm.ilk.optimal;
3151
3152         intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
3153                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
3154                         pristate = plane_state;
3155                 else if (plane->base.type == DRM_PLANE_TYPE_OVERLAY)
3156                         sprstate = plane_state;
3157                 else if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
3158                         curstate = plane_state;
3159         }
3160
3161         pipe_wm->pipe_enabled = crtc_state->hw.active;
3162         if (sprstate) {
3163                 pipe_wm->sprites_enabled = sprstate->uapi.visible;
3164                 pipe_wm->sprites_scaled = sprstate->uapi.visible &&
3165                         (drm_rect_width(&sprstate->uapi.dst) != drm_rect_width(&sprstate->uapi.src) >> 16 ||
3166                          drm_rect_height(&sprstate->uapi.dst) != drm_rect_height(&sprstate->uapi.src) >> 16);
3167         }
3168
3169         usable_level = max_level;
3170
3171         /* ILK/SNB: LP2+ watermarks only w/o sprites */
3172         if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
3173                 usable_level = 1;
3174
3175         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
3176         if (pipe_wm->sprites_scaled)
3177                 usable_level = 0;
3178
3179         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
3180         ilk_compute_wm_level(dev_priv, crtc, 0, crtc_state,
3181                              pristate, sprstate, curstate, &pipe_wm->wm[0]);
3182
3183         if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
3184                 return -EINVAL;
3185
3186         ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
3187
3188         for (level = 1; level <= usable_level; level++) {
3189                 struct intel_wm_level *wm = &pipe_wm->wm[level];
3190
3191                 ilk_compute_wm_level(dev_priv, crtc, level, crtc_state,
3192                                      pristate, sprstate, curstate, wm);
3193
3194                 /*
3195                  * Disable any watermark level that exceeds the
3196                  * register maximums since such watermarks are
3197                  * always invalid.
3198                  */
3199                 if (!ilk_validate_wm_level(level, &max, wm)) {
3200                         memset(wm, 0, sizeof(*wm));
3201                         break;
3202                 }
3203         }
3204
3205         return 0;
3206 }
3207
3208 /*
3209  * Build a set of 'intermediate' watermark values that satisfy both the old
3210  * state and the new state.  These can be programmed to the hardware
3211  * immediately.
3212  */
3213 static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
3214 {
3215         struct intel_crtc *intel_crtc = to_intel_crtc(newstate->uapi.crtc);
3216         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3217         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
3218         struct intel_atomic_state *intel_state =
3219                 to_intel_atomic_state(newstate->uapi.state);
3220         const struct intel_crtc_state *oldstate =
3221                 intel_atomic_get_old_crtc_state(intel_state, intel_crtc);
3222         const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal;
3223         int level, max_level = ilk_wm_max_level(dev_priv);
3224
3225         /*
3226          * Start with the final, target watermarks, then combine with the
3227          * currently active watermarks to get values that are safe both before
3228          * and after the vblank.
3229          */
3230         *a = newstate->wm.ilk.optimal;
3231         if (!newstate->hw.active || drm_atomic_crtc_needs_modeset(&newstate->uapi) ||
3232             intel_state->skip_intermediate_wm)
3233                 return 0;
3234
3235         a->pipe_enabled |= b->pipe_enabled;
3236         a->sprites_enabled |= b->sprites_enabled;
3237         a->sprites_scaled |= b->sprites_scaled;
3238
3239         for (level = 0; level <= max_level; level++) {
3240                 struct intel_wm_level *a_wm = &a->wm[level];
3241                 const struct intel_wm_level *b_wm = &b->wm[level];
3242
3243                 a_wm->enable &= b_wm->enable;
3244                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
3245                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
3246                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
3247                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
3248         }
3249
3250         /*
3251          * We need to make sure that these merged watermark values are
3252          * actually a valid configuration themselves.  If they're not,
3253          * there's no safe way to transition from the old state to
3254          * the new state, so we need to fail the atomic transaction.
3255          */
3256         if (!ilk_validate_pipe_wm(dev_priv, a))
3257                 return -EINVAL;
3258
3259         /*
3260          * If our intermediate WM are identical to the final WM, then we can
3261          * omit the post-vblank programming; only update if it's different.
3262          */
3263         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0)
3264                 newstate->wm.need_postvbl_update = true;
3265
3266         return 0;
3267 }
3268
3269 /*
3270  * Merge the watermarks from all active pipes for a specific level.
3271  */
3272 static void ilk_merge_wm_level(struct drm_i915_private *dev_priv,
3273                                int level,
3274                                struct intel_wm_level *ret_wm)
3275 {
3276         const struct intel_crtc *intel_crtc;
3277
3278         ret_wm->enable = true;
3279
3280         for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
3281                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
3282                 const struct intel_wm_level *wm = &active->wm[level];
3283
3284                 if (!active->pipe_enabled)
3285                         continue;
3286
3287                 /*
3288                  * The watermark values may have been used in the past,
3289                  * so we must maintain them in the registers for some
3290                  * time even if the level is now disabled.
3291                  */
3292                 if (!wm->enable)
3293                         ret_wm->enable = false;
3294
3295                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
3296                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
3297                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
3298                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
3299         }
3300 }
3301
3302 /*
3303  * Merge all low power watermarks for all active pipes.
3304  */
3305 static void ilk_wm_merge(struct drm_i915_private *dev_priv,
3306                          const struct intel_wm_config *config,
3307                          const struct ilk_wm_maximums *max,
3308                          struct intel_pipe_wm *merged)
3309 {
3310         int level, max_level = ilk_wm_max_level(dev_priv);
3311         int last_enabled_level = max_level;
3312
3313         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
3314         if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
3315             config->num_pipes_active > 1)
3316                 last_enabled_level = 0;
3317
3318         /* ILK: FBC WM must be disabled always */
3319         merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
3320
3321         /* merge each WM1+ level */
3322         for (level = 1; level <= max_level; level++) {
3323                 struct intel_wm_level *wm = &merged->wm[level];
3324
3325                 ilk_merge_wm_level(dev_priv, level, wm);
3326
3327                 if (level > last_enabled_level)
3328                         wm->enable = false;
3329                 else if (!ilk_validate_wm_level(level, max, wm))
3330                         /* make sure all following levels get disabled */
3331                         last_enabled_level = level - 1;
3332
3333                 /*
3334                  * The spec says it is preferred to disable
3335                  * FBC WMs instead of disabling a WM level.
3336                  */
3337                 if (wm->fbc_val > max->fbc) {
3338                         if (wm->enable)
3339                                 merged->fbc_wm_enabled = false;
3340                         wm->fbc_val = 0;
3341                 }
3342         }
3343
3344         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3345         /*
3346          * FIXME this is racy. FBC might get enabled later.
3347          * What we should check here is whether FBC can be
3348          * enabled sometime later.
3349          */
3350         if (IS_GEN(dev_priv, 5) && !merged->fbc_wm_enabled &&
3351             intel_fbc_is_active(dev_priv)) {
3352                 for (level = 2; level <= max_level; level++) {
3353                         struct intel_wm_level *wm = &merged->wm[level];
3354
3355                         wm->enable = false;
3356                 }
3357         }
3358 }
3359
3360 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
3361 {
3362         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
3363         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
3364 }
3365
3366 /* The value we need to program into the WM_LPx latency field */
3367 static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv,
3368                                       int level)
3369 {
3370         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3371                 return 2 * level;
3372         else
3373                 return dev_priv->wm.pri_latency[level];
3374 }
3375
3376 static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
3377                                    const struct intel_pipe_wm *merged,
3378                                    enum intel_ddb_partitioning partitioning,
3379                                    struct ilk_wm_values *results)
3380 {
3381         struct intel_crtc *intel_crtc;
3382         int level, wm_lp;
3383
3384         results->enable_fbc_wm = merged->fbc_wm_enabled;
3385         results->partitioning = partitioning;
3386
3387         /* LP1+ register values */
3388         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3389                 const struct intel_wm_level *r;
3390
3391                 level = ilk_wm_lp_to_level(wm_lp, merged);
3392
3393                 r = &merged->wm[level];
3394
3395                 /*
3396                  * Maintain the watermark values even if the level is
3397                  * disabled. Doing otherwise could cause underruns.
3398                  */
3399                 results->wm_lp[wm_lp - 1] =
3400                         (ilk_wm_lp_latency(dev_priv, level) << WM1_LP_LATENCY_SHIFT) |
3401                         (r->pri_val << WM1_LP_SR_SHIFT) |
3402                         r->cur_val;
3403
3404                 if (r->enable)
3405                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
3406
3407                 if (INTEL_GEN(dev_priv) >= 8)
3408                         results->wm_lp[wm_lp - 1] |=
3409                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
3410                 else
3411                         results->wm_lp[wm_lp - 1] |=
3412                                 r->fbc_val << WM1_LP_FBC_SHIFT;
3413
3414                 /*
3415                  * Always set WM1S_LP_EN when spr_val != 0, even if the
3416                  * level is disabled. Doing otherwise could cause underruns.
3417                  */
3418                 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
3419                         drm_WARN_ON(&dev_priv->drm, wm_lp != 1);
3420                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
3421                 } else
3422                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
3423         }
3424
3425         /* LP0 register values */
3426         for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
3427                 enum pipe pipe = intel_crtc->pipe;
3428                 const struct intel_pipe_wm *pipe_wm = &intel_crtc->wm.active.ilk;
3429                 const struct intel_wm_level *r = &pipe_wm->wm[0];
3430
3431                 if (drm_WARN_ON(&dev_priv->drm, !r->enable))
3432                         continue;
3433
3434                 results->wm_pipe[pipe] =
3435                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
3436                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
3437                         r->cur_val;
3438         }
3439 }
3440
3441 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
3442  * case both are at the same level. Prefer r1 in case they're the same. */
3443 static struct intel_pipe_wm *
3444 ilk_find_best_result(struct drm_i915_private *dev_priv,
3445                      struct intel_pipe_wm *r1,
3446                      struct intel_pipe_wm *r2)
3447 {
3448         int level, max_level = ilk_wm_max_level(dev_priv);
3449         int level1 = 0, level2 = 0;
3450
3451         for (level = 1; level <= max_level; level++) {
3452                 if (r1->wm[level].enable)
3453                         level1 = level;
3454                 if (r2->wm[level].enable)
3455                         level2 = level;
3456         }
3457
3458         if (level1 == level2) {
3459                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
3460                         return r2;
3461                 else
3462                         return r1;
3463         } else if (level1 > level2) {
3464                 return r1;
3465         } else {
3466                 return r2;
3467         }
3468 }
3469
3470 /* dirty bits used to track which watermarks need changes */
3471 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
3472 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
3473 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
3474 #define WM_DIRTY_FBC (1 << 24)
3475 #define WM_DIRTY_DDB (1 << 25)
3476
3477 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
3478                                          const struct ilk_wm_values *old,
3479                                          const struct ilk_wm_values *new)
3480 {
3481         unsigned int dirty = 0;
3482         enum pipe pipe;
3483         int wm_lp;
3484
3485         for_each_pipe(dev_priv, pipe) {
3486                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
3487                         dirty |= WM_DIRTY_PIPE(pipe);
3488                         /* Must disable LP1+ watermarks too */
3489                         dirty |= WM_DIRTY_LP_ALL;
3490                 }
3491         }
3492
3493         if (old->enable_fbc_wm != new->enable_fbc_wm) {
3494                 dirty |= WM_DIRTY_FBC;
3495                 /* Must disable LP1+ watermarks too */
3496                 dirty |= WM_DIRTY_LP_ALL;
3497         }
3498
3499         if (old->partitioning != new->partitioning) {
3500                 dirty |= WM_DIRTY_DDB;
3501                 /* Must disable LP1+ watermarks too */
3502                 dirty |= WM_DIRTY_LP_ALL;
3503         }
3504
3505         /* LP1+ watermarks already deemed dirty, no need to continue */
3506         if (dirty & WM_DIRTY_LP_ALL)
3507                 return dirty;
3508
3509         /* Find the lowest numbered LP1+ watermark in need of an update... */
3510         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3511                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
3512                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
3513                         break;
3514         }
3515
3516         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
3517         for (; wm_lp <= 3; wm_lp++)
3518                 dirty |= WM_DIRTY_LP(wm_lp);
3519
3520         return dirty;
3521 }
3522
3523 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
3524                                unsigned int dirty)
3525 {
3526         struct ilk_wm_values *previous = &dev_priv->wm.hw;
3527         bool changed = false;
3528
3529         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
3530                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
3531                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
3532                 changed = true;
3533         }
3534         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
3535                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
3536                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
3537                 changed = true;
3538         }
3539         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
3540                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
3541                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
3542                 changed = true;
3543         }
3544
3545         /*
3546          * Don't touch WM1S_LP_EN here.
3547          * Doing so could cause underruns.
3548          */
3549
3550         return changed;
3551 }
3552
3553 /*
3554  * The spec says we shouldn't write when we don't need, because every write
3555  * causes WMs to be re-evaluated, expending some power.
3556  */
3557 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
3558                                 struct ilk_wm_values *results)
3559 {
3560         struct ilk_wm_values *previous = &dev_priv->wm.hw;
3561         unsigned int dirty;
3562         u32 val;
3563
3564         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
3565         if (!dirty)
3566                 return;
3567
3568         _ilk_disable_lp_wm(dev_priv, dirty);
3569
3570         if (dirty & WM_DIRTY_PIPE(PIPE_A))
3571                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
3572         if (dirty & WM_DIRTY_PIPE(PIPE_B))
3573                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
3574         if (dirty & WM_DIRTY_PIPE(PIPE_C))
3575                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
3576
3577         if (dirty & WM_DIRTY_DDB) {
3578                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3579                         val = I915_READ(WM_MISC);
3580                         if (results->partitioning == INTEL_DDB_PART_1_2)
3581                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
3582                         else
3583                                 val |= WM_MISC_DATA_PARTITION_5_6;
3584                         I915_WRITE(WM_MISC, val);
3585                 } else {
3586                         val = I915_READ(DISP_ARB_CTL2);
3587                         if (results->partitioning == INTEL_DDB_PART_1_2)
3588                                 val &= ~DISP_DATA_PARTITION_5_6;
3589                         else
3590                                 val |= DISP_DATA_PARTITION_5_6;
3591                         I915_WRITE(DISP_ARB_CTL2, val);
3592                 }
3593         }
3594
3595         if (dirty & WM_DIRTY_FBC) {
3596                 val = I915_READ(DISP_ARB_CTL);
3597                 if (results->enable_fbc_wm)
3598                         val &= ~DISP_FBC_WM_DIS;
3599                 else
3600                         val |= DISP_FBC_WM_DIS;
3601                 I915_WRITE(DISP_ARB_CTL, val);
3602         }
3603
3604         if (dirty & WM_DIRTY_LP(1) &&
3605             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
3606                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
3607
3608         if (INTEL_GEN(dev_priv) >= 7) {
3609                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
3610                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
3611                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
3612                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
3613         }
3614
3615         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
3616                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
3617         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
3618                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
3619         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
3620                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
3621
3622         dev_priv->wm.hw = *results;
3623 }
3624
3625 bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
3626 {
3627         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
3628 }
3629
3630 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
3631 {
3632         int i;
3633         int max_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
3634         u8 enabled_slices_mask = 0;
3635
3636         for (i = 0; i < max_slices; i++) {
3637                 if (I915_READ(DBUF_CTL_S(i)) & DBUF_POWER_STATE)
3638                         enabled_slices_mask |= BIT(i);
3639         }
3640
3641         return enabled_slices_mask;
3642 }
3643
3644 /*
3645  * FIXME: We still don't have the proper code detect if we need to apply the WA,
3646  * so assume we'll always need it in order to avoid underruns.
3647  */
3648 static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
3649 {
3650         return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
3651 }
3652
3653 static bool
3654 intel_has_sagv(struct drm_i915_private *dev_priv)
3655 {
3656         return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
3657                 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
3658 }
3659
3660 static void
3661 skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
3662 {
3663         if (INTEL_GEN(dev_priv) >= 12) {
3664                 u32 val = 0;
3665                 int ret;
3666
3667                 ret = sandybridge_pcode_read(dev_priv,
3668                                              GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
3669                                              &val, NULL);
3670                 if (!ret) {
3671                         dev_priv->sagv_block_time_us = val;
3672                         return;
3673                 }
3674
3675                 drm_dbg(&dev_priv->drm, "Couldn't read SAGV block time!\n");
3676         } else if (IS_GEN(dev_priv, 11)) {
3677                 dev_priv->sagv_block_time_us = 10;
3678                 return;
3679         } else if (IS_GEN(dev_priv, 10)) {
3680                 dev_priv->sagv_block_time_us = 20;
3681                 return;
3682         } else if (IS_GEN(dev_priv, 9)) {
3683                 dev_priv->sagv_block_time_us = 30;
3684                 return;
3685         } else {
3686                 MISSING_CASE(INTEL_GEN(dev_priv));
3687         }
3688
3689         /* Default to an unusable block time */
3690         dev_priv->sagv_block_time_us = -1;
3691 }
3692
3693 /*
3694  * SAGV dynamically adjusts the system agent voltage and clock frequencies
3695  * depending on power and performance requirements. The display engine access
3696  * to system memory is blocked during the adjustment time. Because of the
3697  * blocking time, having this enabled can cause full system hangs and/or pipe
3698  * underruns if we don't meet all of the following requirements:
3699  *
3700  *  - <= 1 pipe enabled
3701  *  - All planes can enable watermarks for latencies >= SAGV engine block time
3702  *  - We're not using an interlaced display configuration
3703  */
3704 int
3705 intel_enable_sagv(struct drm_i915_private *dev_priv)
3706 {
3707         int ret;
3708
3709         if (!intel_has_sagv(dev_priv))
3710                 return 0;
3711
3712         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
3713                 return 0;
3714
3715         drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
3716         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3717                                       GEN9_SAGV_ENABLE);
3718
3719         /* We don't need to wait for SAGV when enabling */
3720
3721         /*
3722          * Some skl systems, pre-release machines in particular,
3723          * don't actually have SAGV.
3724          */
3725         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3726                 drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n");
3727                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3728                 return 0;
3729         } else if (ret < 0) {
3730                 drm_err(&dev_priv->drm, "Failed to enable SAGV\n");
3731                 return ret;
3732         }
3733
3734         dev_priv->sagv_status = I915_SAGV_ENABLED;
3735         return 0;
3736 }
3737
3738 int
3739 intel_disable_sagv(struct drm_i915_private *dev_priv)
3740 {
3741         int ret;
3742
3743         if (!intel_has_sagv(dev_priv))
3744                 return 0;
3745
3746         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
3747                 return 0;
3748
3749         drm_dbg_kms(&dev_priv->drm, "Disabling SAGV\n");
3750         /* bspec says to keep retrying for at least 1 ms */
3751         ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3752                                 GEN9_SAGV_DISABLE,
3753                                 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
3754                                 1);
3755         /*
3756          * Some skl systems, pre-release machines in particular,
3757          * don't actually have SAGV.
3758          */
3759         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3760                 drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n");
3761                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3762                 return 0;
3763         } else if (ret < 0) {
3764                 drm_err(&dev_priv->drm, "Failed to disable SAGV (%d)\n", ret);
3765                 return ret;
3766         }
3767
3768         dev_priv->sagv_status = I915_SAGV_DISABLED;
3769         return 0;
3770 }
3771
3772 void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
3773 {
3774         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3775         const struct intel_bw_state *new_bw_state;
3776         const struct intel_bw_state *old_bw_state;
3777         u32 new_mask = 0;
3778
3779         /*
3780          * Just return if we can't control SAGV or don't have it.
3781          * This is different from situation when we have SAGV but just can't
3782          * afford it due to DBuf limitation - in case if SAGV is completely
3783          * disabled in a BIOS, we are not even allowed to send a PCode request,
3784          * as it will throw an error. So have to check it here.
3785          */
3786         if (!intel_has_sagv(dev_priv))
3787                 return;
3788
3789         new_bw_state = intel_atomic_get_new_bw_state(state);
3790         if (!new_bw_state)
3791                 return;
3792
3793         if (INTEL_GEN(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv, new_bw_state)) {
3794                 intel_disable_sagv(dev_priv);
3795                 return;
3796         }
3797
3798         old_bw_state = intel_atomic_get_old_bw_state(state);
3799         /*
3800          * Nothing to mask
3801          */
3802         if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
3803                 return;
3804
3805         new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
3806
3807         /*
3808          * If new mask is zero - means there is nothing to mask,
3809          * we can only unmask, which should be done in unmask.
3810          */
3811         if (!new_mask)
3812                 return;
3813
3814         /*
3815          * Restrict required qgv points before updating the configuration.
3816          * According to BSpec we can't mask and unmask qgv points at the same
3817          * time. Also masking should be done before updating the configuration
3818          * and unmasking afterwards.
3819          */
3820         icl_pcode_restrict_qgv_points(dev_priv, new_mask);
3821 }
3822
3823 void intel_sagv_post_plane_update(struct intel_atomic_state *state)
3824 {
3825         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3826         const struct intel_bw_state *new_bw_state;
3827         const struct intel_bw_state *old_bw_state;
3828         u32 new_mask = 0;
3829
3830         /*
3831          * Just return if we can't control SAGV or don't have it.
3832          * This is different from situation when we have SAGV but just can't
3833          * afford it due to DBuf limitation - in case if SAGV is completely
3834          * disabled in a BIOS, we are not even allowed to send a PCode request,
3835          * as it will throw an error. So have to check it here.
3836          */
3837         if (!intel_has_sagv(dev_priv))
3838                 return;
3839
3840         new_bw_state = intel_atomic_get_new_bw_state(state);
3841         if (!new_bw_state)
3842                 return;
3843
3844         if (INTEL_GEN(dev_priv) < 11 && intel_can_enable_sagv(dev_priv, new_bw_state)) {
3845                 intel_enable_sagv(dev_priv);
3846                 return;
3847         }
3848
3849         old_bw_state = intel_atomic_get_old_bw_state(state);
3850         /*
3851          * Nothing to unmask
3852          */
3853         if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
3854                 return;
3855
3856         new_mask = new_bw_state->qgv_points_mask;
3857
3858         /*
3859          * Allow required qgv points after updating the configuration.
3860          * According to BSpec we can't mask and unmask qgv points at the same
3861          * time. Also masking should be done before updating the configuration
3862          * and unmasking afterwards.
3863          */
3864         icl_pcode_restrict_qgv_points(dev_priv, new_mask);
3865 }
3866
3867 static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
3868 {
3869         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3870         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3871         struct intel_plane *plane;
3872         const struct intel_plane_state *plane_state;
3873         int level, latency;
3874
3875         if (!intel_has_sagv(dev_priv))
3876                 return false;
3877
3878         if (!crtc_state->hw.active)
3879                 return true;
3880
3881         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3882                 return false;
3883
3884         intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
3885                 const struct skl_plane_wm *wm =
3886                         &crtc_state->wm.skl.optimal.planes[plane->id];
3887
3888                 /* Skip this plane if it's not enabled */
3889                 if (!wm->wm[0].plane_en)
3890                         continue;
3891
3892                 /* Find the highest enabled wm level for this plane */
3893                 for (level = ilk_wm_max_level(dev_priv);
3894                      !wm->wm[level].plane_en; --level)
3895                      { }
3896
3897                 latency = dev_priv->wm.skl_latency[level];
3898
3899                 if (skl_needs_memory_bw_wa(dev_priv) &&
3900                     plane_state->uapi.fb->modifier ==
3901                     I915_FORMAT_MOD_X_TILED)
3902                         latency += 15;
3903
3904                 /*
3905                  * If any of the planes on this pipe don't enable wm levels that
3906                  * incur memory latencies higher than sagv_block_time_us we
3907                  * can't enable SAGV.
3908                  */
3909                 if (latency < dev_priv->sagv_block_time_us)
3910                         return false;
3911         }
3912
3913         return true;
3914 }
3915
3916 static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
3917 {
3918         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3919         enum plane_id plane_id;
3920
3921         if (!crtc_state->hw.active)
3922                 return true;
3923
3924         for_each_plane_id_on_crtc(crtc, plane_id) {
3925                 const struct skl_ddb_entry *plane_alloc =
3926                         &crtc_state->wm.skl.plane_ddb_y[plane_id];
3927                 const struct skl_plane_wm *wm =
3928                         &crtc_state->wm.skl.optimal.planes[plane_id];
3929
3930                 if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
3931                         return false;
3932         }
3933
3934         return true;
3935 }
3936
3937 static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
3938 {
3939         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3940         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3941
3942         if (INTEL_GEN(dev_priv) >= 12)
3943                 return tgl_crtc_can_enable_sagv(crtc_state);
3944         else
3945                 return skl_crtc_can_enable_sagv(crtc_state);
3946 }
3947
3948 bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
3949                            const struct intel_bw_state *bw_state)
3950 {
3951         if (INTEL_GEN(dev_priv) < 11 &&
3952             bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
3953                 return false;
3954
3955         return bw_state->pipe_sagv_reject == 0;
3956 }
3957
3958 static int intel_compute_sagv_mask(struct intel_atomic_state *state)
3959 {
3960         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3961         int ret;
3962         struct intel_crtc *crtc;
3963         struct intel_crtc_state *new_crtc_state;
3964         struct intel_bw_state *new_bw_state = NULL;
3965         const struct intel_bw_state *old_bw_state = NULL;
3966         int i;
3967
3968         for_each_new_intel_crtc_in_state(state, crtc,
3969                                          new_crtc_state, i) {
3970                 new_bw_state = intel_atomic_get_bw_state(state);
3971                 if (IS_ERR(new_bw_state))
3972                         return PTR_ERR(new_bw_state);
3973
3974                 old_bw_state = intel_atomic_get_old_bw_state(state);
3975
3976                 if (intel_crtc_can_enable_sagv(new_crtc_state))
3977                         new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
3978                 else
3979                         new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
3980         }
3981
3982         if (!new_bw_state)
3983                 return 0;
3984
3985         new_bw_state->active_pipes =
3986                 intel_calc_active_pipes(state, old_bw_state->active_pipes);
3987
3988         if (new_bw_state->active_pipes != old_bw_state->active_pipes) {
3989                 ret = intel_atomic_lock_global_state(&new_bw_state->base);
3990                 if (ret)
3991                         return ret;
3992         }
3993
3994         for_each_new_intel_crtc_in_state(state, crtc,
3995                                          new_crtc_state, i) {
3996                 struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
3997
3998                 /*
3999                  * We store use_sagv_wm in the crtc state rather than relying on
4000                  * that bw state since we have no convenient way to get at the
4001                  * latter from the plane commit hooks (especially in the legacy
4002                  * cursor case)
4003                  */
4004                 pipe_wm->use_sagv_wm = INTEL_GEN(dev_priv) >= 12 &&
4005                                        intel_can_enable_sagv(dev_priv, new_bw_state);
4006         }
4007
4008         if (intel_can_enable_sagv(dev_priv, new_bw_state) !=
4009             intel_can_enable_sagv(dev_priv, old_bw_state)) {
4010                 ret = intel_atomic_serialize_global_state(&new_bw_state->base);
4011                 if (ret)
4012                         return ret;
4013         } else if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
4014                 ret = intel_atomic_lock_global_state(&new_bw_state->base);
4015                 if (ret)
4016                         return ret;
4017         }
4018
4019         return 0;
4020 }
4021
4022 /*
4023  * Calculate initial DBuf slice offset, based on slice size
4024  * and mask(i.e if slice size is 1024 and second slice is enabled
4025  * offset would be 1024)
4026  */
4027 static unsigned int
4028 icl_get_first_dbuf_slice_offset(u32 dbuf_slice_mask,
4029                                 u32 slice_size,
4030                                 u32 ddb_size)
4031 {
4032         unsigned int offset = 0;
4033
4034         if (!dbuf_slice_mask)
4035                 return 0;
4036
4037         offset = (ffs(dbuf_slice_mask) - 1) * slice_size;
4038
4039         WARN_ON(offset >= ddb_size);
4040         return offset;
4041 }
4042
4043 u16 intel_get_ddb_size(struct drm_i915_private *dev_priv)
4044 {
4045         u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
4046         drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
4047
4048         if (INTEL_GEN(dev_priv) < 11)
4049                 return ddb_size - 4; /* 4 blocks for bypass path allocation */
4050
4051         return ddb_size;
4052 }
4053
4054 u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
4055                             const struct skl_ddb_entry *entry)
4056 {
4057         u32 slice_mask = 0;
4058         u16 ddb_size = intel_get_ddb_size(dev_priv);
4059         u16 num_supported_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
4060         u16 slice_size = ddb_size / num_supported_slices;
4061         u16 start_slice;
4062         u16 end_slice;
4063
4064         if (!skl_ddb_entry_size(entry))
4065                 return 0;
4066
4067         start_slice = entry->start / slice_size;
4068         end_slice = (entry->end - 1) / slice_size;
4069
4070         /*
4071          * Per plane DDB entry can in a really worst case be on multiple slices
4072          * but single entry is anyway contigious.
4073          */
4074         while (start_slice <= end_slice) {
4075                 slice_mask |= BIT(start_slice);
4076                 start_slice++;
4077         }
4078
4079         return slice_mask;
4080 }
4081
4082 static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state,
4083                                   u8 active_pipes);
4084
4085 static int
4086 skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
4087                                    const struct intel_crtc_state *crtc_state,
4088                                    const u64 total_data_rate,
4089                                    struct skl_ddb_entry *alloc, /* out */
4090                                    int *num_active /* out */)
4091 {
4092         struct drm_atomic_state *state = crtc_state->uapi.state;
4093         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4094         struct drm_crtc *for_crtc = crtc_state->uapi.crtc;
4095         const struct intel_crtc *crtc;
4096         u32 pipe_width = 0, total_width_in_range = 0, width_before_pipe_in_range = 0;
4097         enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
4098         struct intel_dbuf_state *new_dbuf_state =
4099                 intel_atomic_get_new_dbuf_state(intel_state);
4100         const struct intel_dbuf_state *old_dbuf_state =
4101                 intel_atomic_get_old_dbuf_state(intel_state);
4102         u8 active_pipes = new_dbuf_state->active_pipes;
4103         u16 ddb_size;
4104         u32 ddb_range_size;
4105         u32 i;
4106         u32 dbuf_slice_mask;
4107         u32 offset;
4108         u32 slice_size;
4109         u32 total_slice_mask;
4110         u32 start, end;
4111         int ret;
4112
4113         *num_active = hweight8(active_pipes);
4114
4115         if (!crtc_state->hw.active) {
4116                 alloc->start = 0;
4117                 alloc->end = 0;
4118                 return 0;
4119         }
4120
4121         ddb_size = intel_get_ddb_size(dev_priv);
4122
4123         slice_size = ddb_size / INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
4124
4125         /*
4126          * If the state doesn't change the active CRTC's or there is no
4127          * modeset request, then there's no need to recalculate;
4128          * the existing pipe allocation limits should remain unchanged.
4129          * Note that we're safe from racing commits since any racing commit
4130          * that changes the active CRTC list or do modeset would need to
4131          * grab _all_ crtc locks, including the one we currently hold.
4132          */
4133         if (old_dbuf_state->active_pipes == new_dbuf_state->active_pipes &&
4134             !dev_priv->wm.distrust_bios_wm) {
4135                 /*
4136                  * alloc may be cleared by clear_intel_crtc_state,
4137                  * copy from old state to be sure
4138                  *
4139                  * FIXME get rid of this mess
4140                  */
4141                 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
4142                 return 0;
4143         }
4144
4145         /*
4146          * Get allowed DBuf slices for correspondent pipe and platform.
4147          */
4148         dbuf_slice_mask = skl_compute_dbuf_slices(crtc_state, active_pipes);
4149
4150         /*
4151          * Figure out at which DBuf slice we start, i.e if we start at Dbuf S2
4152          * and slice size is 1024, the offset would be 1024
4153          */
4154         offset = icl_get_first_dbuf_slice_offset(dbuf_slice_mask,
4155                                                  slice_size, ddb_size);
4156
4157         /*
4158          * Figure out total size of allowed DBuf slices, which is basically
4159          * a number of allowed slices for that pipe multiplied by slice size.
4160          * Inside of this
4161          * range ddb entries are still allocated in proportion to display width.
4162          */
4163         ddb_range_size = hweight8(dbuf_slice_mask) * slice_size;
4164
4165         /*
4166          * Watermark/ddb requirement highly depends upon width of the
4167          * framebuffer, So instead of allocating DDB equally among pipes
4168          * distribute DDB based on resolution/width of the display.
4169          */
4170         total_slice_mask = dbuf_slice_mask;
4171         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
4172                 const struct drm_display_mode *adjusted_mode =
4173                         &crtc_state->hw.adjusted_mode;
4174                 enum pipe pipe = crtc->pipe;
4175                 int hdisplay, vdisplay;
4176                 u32 pipe_dbuf_slice_mask;
4177
4178                 if (!crtc_state->hw.active)
4179                         continue;
4180
4181                 pipe_dbuf_slice_mask = skl_compute_dbuf_slices(crtc_state,
4182                                                                active_pipes);
4183
4184                 /*
4185                  * According to BSpec pipe can share one dbuf slice with another
4186                  * pipes or pipe can use multiple dbufs, in both cases we
4187                  * account for other pipes only if they have exactly same mask.
4188                  * However we need to account how many slices we should enable
4189                  * in total.
4190                  */
4191                 total_slice_mask |= pipe_dbuf_slice_mask;
4192
4193                 /*
4194                  * Do not account pipes using other slice sets
4195                  * luckily as of current BSpec slice sets do not partially
4196                  * intersect(pipes share either same one slice or same slice set
4197                  * i.e no partial intersection), so it is enough to check for
4198                  * equality for now.
4199                  */
4200                 if (dbuf_slice_mask != pipe_dbuf_slice_mask)
4201                         continue;
4202
4203                 drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
4204
4205                 total_width_in_range += hdisplay;
4206
4207                 if (pipe < for_pipe)
4208                         width_before_pipe_in_range += hdisplay;
4209                 else if (pipe == for_pipe)
4210                         pipe_width = hdisplay;
4211         }
4212
4213         /*
4214          * FIXME: For now we always enable slice S1 as per
4215          * the Bspec display initialization sequence.
4216          */
4217         new_dbuf_state->enabled_slices = total_slice_mask | BIT(DBUF_S1);
4218
4219         if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices) {
4220                 ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
4221                 if (ret)
4222                         return ret;
4223         }
4224
4225         start = ddb_range_size * width_before_pipe_in_range / total_width_in_range;
4226         end = ddb_range_size *
4227                 (width_before_pipe_in_range + pipe_width) / total_width_in_range;
4228
4229         alloc->start = offset + start;
4230         alloc->end = offset + end;
4231
4232         drm_dbg_kms(&dev_priv->drm,
4233                     "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x\n",
4234                     for_crtc->base.id, for_crtc->name,
4235                     dbuf_slice_mask, alloc->start, alloc->end, active_pipes);
4236
4237         return 0;
4238 }
4239
4240 static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
4241                                  int width, const struct drm_format_info *format,
4242                                  u64 modifier, unsigned int rotation,
4243                                  u32 plane_pixel_rate, struct skl_wm_params *wp,
4244                                  int color_plane);
4245 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
4246                                  int level,
4247                                  unsigned int latency,
4248                                  const struct skl_wm_params *wp,
4249                                  const struct skl_wm_level *result_prev,
4250                                  struct skl_wm_level *result /* out */);
4251
4252 static unsigned int
4253 skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
4254                       int num_active)
4255 {
4256         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4257         int level, max_level = ilk_wm_max_level(dev_priv);
4258         struct skl_wm_level wm = {};
4259         int ret, min_ddb_alloc = 0;
4260         struct skl_wm_params wp;
4261
4262         ret = skl_compute_wm_params(crtc_state, 256,
4263                                     drm_format_info(DRM_FORMAT_ARGB8888),
4264                                     DRM_FORMAT_MOD_LINEAR,
4265                                     DRM_MODE_ROTATE_0,
4266                                     crtc_state->pixel_rate, &wp, 0);
4267         drm_WARN_ON(&dev_priv->drm, ret);
4268
4269         for (level = 0; level <= max_level; level++) {
4270                 unsigned int latency = dev_priv->wm.skl_latency[level];
4271
4272                 skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
4273                 if (wm.min_ddb_alloc == U16_MAX)
4274                         break;
4275
4276                 min_ddb_alloc = wm.min_ddb_alloc;
4277         }
4278
4279         return max(num_active == 1 ? 32 : 8, min_ddb_alloc);
4280 }
4281
4282 static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
4283                                        struct skl_ddb_entry *entry, u32 reg)
4284 {
4285
4286         entry->start = reg & DDB_ENTRY_MASK;
4287         entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK;
4288
4289         if (entry->end)
4290                 entry->end += 1;
4291 }
4292
4293 static void
4294 skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
4295                            const enum pipe pipe,
4296                            const enum plane_id plane_id,
4297                            struct skl_ddb_entry *ddb_y,
4298                            struct skl_ddb_entry *ddb_uv)
4299 {
4300         u32 val, val2;
4301         u32 fourcc = 0;
4302
4303         /* Cursor doesn't support NV12/planar, so no extra calculation needed */
4304         if (plane_id == PLANE_CURSOR) {
4305                 val = I915_READ(CUR_BUF_CFG(pipe));
4306                 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4307                 return;
4308         }
4309
4310         val = I915_READ(PLANE_CTL(pipe, plane_id));
4311
4312         /* No DDB allocated for disabled planes */
4313         if (val & PLANE_CTL_ENABLE)
4314                 fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
4315                                               val & PLANE_CTL_ORDER_RGBX,
4316                                               val & PLANE_CTL_ALPHA_MASK);
4317
4318         if (INTEL_GEN(dev_priv) >= 11) {
4319                 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
4320                 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4321         } else {
4322                 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
4323                 val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
4324
4325                 if (fourcc &&
4326                     drm_format_info_is_yuv_semiplanar(drm_format_info(fourcc)))
4327                         swap(val, val2);
4328
4329                 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4330                 skl_ddb_entry_init_from_hw(dev_priv, ddb_uv, val2);
4331         }
4332 }
4333
4334 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
4335                                struct skl_ddb_entry *ddb_y,
4336                                struct skl_ddb_entry *ddb_uv)
4337 {
4338         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4339         enum intel_display_power_domain power_domain;
4340         enum pipe pipe = crtc->pipe;
4341         intel_wakeref_t wakeref;
4342         enum plane_id plane_id;
4343
4344         power_domain = POWER_DOMAIN_PIPE(pipe);
4345         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4346         if (!wakeref)
4347                 return;
4348
4349         for_each_plane_id_on_crtc(crtc, plane_id)
4350                 skl_ddb_get_hw_plane_state(dev_priv, pipe,
4351                                            plane_id,
4352                                            &ddb_y[plane_id],
4353                                            &ddb_uv[plane_id]);
4354
4355         intel_display_power_put(dev_priv, power_domain, wakeref);
4356 }
4357
4358 /*
4359  * Determines the downscale amount of a plane for the purposes of watermark calculations.
4360  * The bspec defines downscale amount as:
4361  *
4362  * """
4363  * Horizontal down scale amount = maximum[1, Horizontal source size /
4364  *                                           Horizontal destination size]
4365  * Vertical down scale amount = maximum[1, Vertical source size /
4366  *                                         Vertical destination size]
4367  * Total down scale amount = Horizontal down scale amount *
4368  *                           Vertical down scale amount
4369  * """
4370  *
4371  * Return value is provided in 16.16 fixed point form to retain fractional part.
4372  * Caller should take care of dividing & rounding off the value.
4373  */
4374 static uint_fixed_16_16_t
4375 skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
4376                            const struct intel_plane_state *plane_state)
4377 {
4378         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4379         u32 src_w, src_h, dst_w, dst_h;
4380         uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
4381         uint_fixed_16_16_t downscale_h, downscale_w;
4382
4383         if (drm_WARN_ON(&dev_priv->drm,
4384                         !intel_wm_plane_visible(crtc_state, plane_state)))
4385                 return u32_to_fixed16(0);
4386
4387         /*
4388          * Src coordinates are already rotated by 270 degrees for
4389          * the 90/270 degree plane rotation cases (to match the
4390          * GTT mapping), hence no need to account for rotation here.
4391          *
4392          * n.b., src is 16.16 fixed point, dst is whole integer.
4393          */
4394         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4395         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4396         dst_w = drm_rect_width(&plane_state->uapi.dst);
4397         dst_h = drm_rect_height(&plane_state->uapi.dst);
4398
4399         fp_w_ratio = div_fixed16(src_w, dst_w);
4400         fp_h_ratio = div_fixed16(src_h, dst_h);
4401         downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
4402         downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
4403
4404         return mul_fixed16(downscale_w, downscale_h);
4405 }
4406
4407 struct dbuf_slice_conf_entry {
4408         u8 active_pipes;
4409         u8 dbuf_mask[I915_MAX_PIPES];
4410 };
4411
4412 /*
4413  * Table taken from Bspec 12716
4414  * Pipes do have some preferred DBuf slice affinity,
4415  * plus there are some hardcoded requirements on how
4416  * those should be distributed for multipipe scenarios.
4417  * For more DBuf slices algorithm can get even more messy
4418  * and less readable, so decided to use a table almost
4419  * as is from BSpec itself - that way it is at least easier
4420  * to compare, change and check.
4421  */
4422 static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] =
4423 /* Autogenerated with igt/tools/intel_dbuf_map tool: */
4424 {
4425         {
4426                 .active_pipes = BIT(PIPE_A),
4427                 .dbuf_mask = {
4428                         [PIPE_A] = BIT(DBUF_S1),
4429                 },
4430         },
4431         {
4432                 .active_pipes = BIT(PIPE_B),
4433                 .dbuf_mask = {
4434                         [PIPE_B] = BIT(DBUF_S1),
4435                 },
4436         },
4437         {
4438                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
4439                 .dbuf_mask = {
4440                         [PIPE_A] = BIT(DBUF_S1),
4441                         [PIPE_B] = BIT(DBUF_S2),
4442                 },
4443         },
4444         {
4445                 .active_pipes = BIT(PIPE_C),
4446                 .dbuf_mask = {
4447                         [PIPE_C] = BIT(DBUF_S2),
4448                 },
4449         },
4450         {
4451                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
4452                 .dbuf_mask = {
4453                         [PIPE_A] = BIT(DBUF_S1),
4454                         [PIPE_C] = BIT(DBUF_S2),
4455                 },
4456         },
4457         {
4458                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
4459                 .dbuf_mask = {
4460                         [PIPE_B] = BIT(DBUF_S1),
4461                         [PIPE_C] = BIT(DBUF_S2),
4462                 },
4463         },
4464         {
4465                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
4466                 .dbuf_mask = {
4467                         [PIPE_A] = BIT(DBUF_S1),
4468                         [PIPE_B] = BIT(DBUF_S1),
4469                         [PIPE_C] = BIT(DBUF_S2),
4470                 },
4471         },
4472         {}
4473 };
4474
4475 /*
4476  * Table taken from Bspec 49255
4477  * Pipes do have some preferred DBuf slice affinity,
4478  * plus there are some hardcoded requirements on how
4479  * those should be distributed for multipipe scenarios.
4480  * For more DBuf slices algorithm can get even more messy
4481  * and less readable, so decided to use a table almost
4482  * as is from BSpec itself - that way it is at least easier
4483  * to compare, change and check.
4484  */
4485 static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] =
4486 /* Autogenerated with igt/tools/intel_dbuf_map tool: */
4487 {
4488         {
4489                 .active_pipes = BIT(PIPE_A),
4490                 .dbuf_mask = {
4491                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4492                 },
4493         },
4494         {
4495                 .active_pipes = BIT(PIPE_B),
4496                 .dbuf_mask = {
4497                         [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
4498                 },
4499         },
4500         {
4501                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
4502                 .dbuf_mask = {
4503                         [PIPE_A] = BIT(DBUF_S2),
4504                         [PIPE_B] = BIT(DBUF_S1),
4505                 },
4506         },
4507         {
4508                 .active_pipes = BIT(PIPE_C),
4509                 .dbuf_mask = {
4510                         [PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1),
4511                 },
4512         },
4513         {
4514                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
4515                 .dbuf_mask = {
4516                         [PIPE_A] = BIT(DBUF_S1),
4517                         [PIPE_C] = BIT(DBUF_S2),
4518                 },
4519         },
4520         {
4521                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
4522                 .dbuf_mask = {
4523                         [PIPE_B] = BIT(DBUF_S1),
4524                         [PIPE_C] = BIT(DBUF_S2),
4525                 },
4526         },
4527         {
4528                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
4529                 .dbuf_mask = {
4530                         [PIPE_A] = BIT(DBUF_S1),
4531                         [PIPE_B] = BIT(DBUF_S1),
4532                         [PIPE_C] = BIT(DBUF_S2),
4533                 },
4534         },
4535         {
4536                 .active_pipes = BIT(PIPE_D),
4537                 .dbuf_mask = {
4538                         [PIPE_D] = BIT(DBUF_S2) | BIT(DBUF_S1),
4539                 },
4540         },
4541         {
4542                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
4543                 .dbuf_mask = {
4544                         [PIPE_A] = BIT(DBUF_S1),
4545                         [PIPE_D] = BIT(DBUF_S2),
4546                 },
4547         },
4548         {
4549                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
4550                 .dbuf_mask = {
4551                         [PIPE_B] = BIT(DBUF_S1),
4552                         [PIPE_D] = BIT(DBUF_S2),
4553                 },
4554         },
4555         {
4556                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
4557                 .dbuf_mask = {
4558                         [PIPE_A] = BIT(DBUF_S1),
4559                         [PIPE_B] = BIT(DBUF_S1),
4560                         [PIPE_D] = BIT(DBUF_S2),
4561                 },
4562         },
4563         {
4564                 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
4565                 .dbuf_mask = {
4566                         [PIPE_C] = BIT(DBUF_S1),
4567                         [PIPE_D] = BIT(DBUF_S2),
4568                 },
4569         },
4570         {
4571                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
4572                 .dbuf_mask = {
4573                         [PIPE_A] = BIT(DBUF_S1),
4574                         [PIPE_C] = BIT(DBUF_S2),
4575                         [PIPE_D] = BIT(DBUF_S2),
4576                 },
4577         },
4578         {
4579                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
4580                 .dbuf_mask = {
4581                         [PIPE_B] = BIT(DBUF_S1),
4582                         [PIPE_C] = BIT(DBUF_S2),
4583                         [PIPE_D] = BIT(DBUF_S2),
4584                 },
4585         },
4586         {
4587                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
4588                 .dbuf_mask = {
4589                         [PIPE_A] = BIT(DBUF_S1),
4590                         [PIPE_B] = BIT(DBUF_S1),
4591                         [PIPE_C] = BIT(DBUF_S2),
4592                         [PIPE_D] = BIT(DBUF_S2),
4593                 },
4594         },
4595         {}
4596 };
4597
4598 static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes,
4599                               const struct dbuf_slice_conf_entry *dbuf_slices)
4600 {
4601         int i;
4602
4603         for (i = 0; i < dbuf_slices[i].active_pipes; i++) {
4604                 if (dbuf_slices[i].active_pipes == active_pipes)
4605                         return dbuf_slices[i].dbuf_mask[pipe];
4606         }
4607         return 0;
4608 }
4609
4610 /*
4611  * This function finds an entry with same enabled pipe configuration and
4612  * returns correspondent DBuf slice mask as stated in BSpec for particular
4613  * platform.
4614  */
4615 static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
4616 {
4617         /*
4618          * FIXME: For ICL this is still a bit unclear as prev BSpec revision
4619          * required calculating "pipe ratio" in order to determine
4620          * if one or two slices can be used for single pipe configurations
4621          * as additional constraint to the existing table.
4622          * However based on recent info, it should be not "pipe ratio"
4623          * but rather ratio between pixel_rate and cdclk with additional
4624          * constants, so for now we are using only table until this is
4625          * clarified. Also this is the reason why crtc_state param is
4626          * still here - we will need it once those additional constraints
4627          * pop up.
4628          */
4629         return compute_dbuf_slices(pipe, active_pipes, icl_allowed_dbufs);
4630 }
4631
4632 static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
4633 {
4634         return compute_dbuf_slices(pipe, active_pipes, tgl_allowed_dbufs);
4635 }
4636
4637 static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state,
4638                                   u8 active_pipes)
4639 {
4640         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4641         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4642         enum pipe pipe = crtc->pipe;
4643
4644         if (IS_GEN(dev_priv, 12))
4645                 return tgl_compute_dbuf_slices(pipe, active_pipes);
4646         else if (IS_GEN(dev_priv, 11))
4647                 return icl_compute_dbuf_slices(pipe, active_pipes);
4648         /*
4649          * For anything else just return one slice yet.
4650          * Should be extended for other platforms.
4651          */
4652         return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
4653 }
4654
4655 static u64
4656 skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
4657                              const struct intel_plane_state *plane_state,
4658                              int color_plane)
4659 {
4660         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4661         const struct drm_framebuffer *fb = plane_state->hw.fb;
4662         u32 data_rate;
4663         u32 width = 0, height = 0;
4664         uint_fixed_16_16_t down_scale_amount;
4665         u64 rate;
4666
4667         if (!plane_state->uapi.visible)
4668                 return 0;
4669
4670         if (plane->id == PLANE_CURSOR)
4671                 return 0;
4672
4673         if (color_plane == 1 &&
4674             !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
4675                 return 0;
4676
4677         /*
4678          * Src coordinates are already rotated by 270 degrees for
4679          * the 90/270 degree plane rotation cases (to match the
4680          * GTT mapping), hence no need to account for rotation here.
4681          */
4682         width = drm_rect_width(&plane_state->uapi.src) >> 16;
4683         height = drm_rect_height(&plane_state->uapi.src) >> 16;
4684
4685         /* UV plane does 1/2 pixel sub-sampling */
4686         if (color_plane == 1) {
4687                 width /= 2;
4688                 height /= 2;
4689         }
4690
4691         data_rate = width * height;
4692
4693         down_scale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
4694
4695         rate = mul_round_up_u32_fixed16(data_rate, down_scale_amount);
4696
4697         rate *= fb->format->cpp[color_plane];
4698         return rate;
4699 }
4700
4701 static u64
4702 skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
4703                                  u64 *plane_data_rate,
4704                                  u64 *uv_plane_data_rate)
4705 {
4706         struct intel_plane *plane;
4707         const struct intel_plane_state *plane_state;
4708         u64 total_data_rate = 0;
4709
4710         /* Calculate and cache data rate for each plane */
4711         intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
4712                 enum plane_id plane_id = plane->id;
4713                 u64 rate;
4714
4715                 /* packed/y */
4716                 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
4717                 plane_data_rate[plane_id] = rate;
4718                 total_data_rate += rate;
4719
4720                 /* uv-plane */
4721                 rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
4722                 uv_plane_data_rate[plane_id] = rate;
4723                 total_data_rate += rate;
4724         }
4725
4726         return total_data_rate;
4727 }
4728
4729 static u64
4730 icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
4731                                  u64 *plane_data_rate)
4732 {
4733         struct intel_plane *plane;
4734         const struct intel_plane_state *plane_state;
4735         u64 total_data_rate = 0;
4736
4737         /* Calculate and cache data rate for each plane */
4738         intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
4739                 enum plane_id plane_id = plane->id;
4740                 u64 rate;
4741
4742                 if (!plane_state->planar_linked_plane) {
4743                         rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
4744                         plane_data_rate[plane_id] = rate;
4745                         total_data_rate += rate;
4746                 } else {
4747                         enum plane_id y_plane_id;
4748
4749                         /*
4750                          * The slave plane might not iterate in
4751                          * intel_atomic_crtc_state_for_each_plane_state(),
4752                          * and needs the master plane state which may be
4753                          * NULL if we try get_new_plane_state(), so we
4754                          * always calculate from the master.
4755                          */
4756                         if (plane_state->planar_slave)
4757                                 continue;
4758
4759                         /* Y plane rate is calculated on the slave */
4760                         rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
4761                         y_plane_id = plane_state->planar_linked_plane->id;
4762                         plane_data_rate[y_plane_id] = rate;
4763                         total_data_rate += rate;
4764
4765                         rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
4766                         plane_data_rate[plane_id] = rate;
4767                         total_data_rate += rate;
4768                 }
4769         }
4770
4771         return total_data_rate;
4772 }
4773
4774 static const struct skl_wm_level *
4775 skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
4776                    enum plane_id plane_id,
4777                    int level)
4778 {
4779         const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
4780         const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
4781
4782         if (level == 0 && pipe_wm->use_sagv_wm)
4783                 return &wm->sagv_wm0;
4784
4785         return &wm->wm[level];
4786 }
4787
4788 static int
4789 skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
4790 {
4791         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4792         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4793         struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
4794         u16 alloc_size, start = 0;
4795         u16 total[I915_MAX_PLANES] = {};
4796         u16 uv_total[I915_MAX_PLANES] = {};
4797         u64 total_data_rate;
4798         enum plane_id plane_id;
4799         int num_active;
4800         u64 plane_data_rate[I915_MAX_PLANES] = {};
4801         u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
4802         u32 blocks;
4803         int level;
4804         int ret;
4805
4806         /* Clear the partitioning for disabled planes. */
4807         memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
4808         memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));
4809
4810         if (!crtc_state->hw.active) {
4811                 struct intel_atomic_state *state =
4812                         to_intel_atomic_state(crtc_state->uapi.state);
4813                 struct intel_dbuf_state *new_dbuf_state =
4814                         intel_atomic_get_new_dbuf_state(state);
4815                 const struct intel_dbuf_state *old_dbuf_state =
4816                         intel_atomic_get_old_dbuf_state(state);
4817
4818                 /*
4819                  * FIXME hack to make sure we compute this sensibly when
4820                  * turning off all the pipes. Otherwise we leave it at
4821                  * whatever we had previously, and then runtime PM will
4822                  * mess it up by turning off all but S1. Remove this
4823                  * once the dbuf state computation flow becomes sane.
4824                  */
4825                 if (new_dbuf_state->active_pipes == 0) {
4826                         new_dbuf_state->enabled_slices = BIT(DBUF_S1);
4827
4828                         if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices) {
4829                                 ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
4830                                 if (ret)
4831                                         return ret;
4832                         }
4833                 }
4834
4835                 alloc->start = alloc->end = 0;
4836                 return 0;
4837         }
4838
4839         if (INTEL_GEN(dev_priv) >= 11)
4840                 total_data_rate =
4841                         icl_get_total_relative_data_rate(crtc_state,
4842                                                          plane_data_rate);
4843         else
4844                 total_data_rate =
4845                         skl_get_total_relative_data_rate(crtc_state,
4846                                                          plane_data_rate,
4847                                                          uv_plane_data_rate);
4848
4849         ret = skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
4850                                                  total_data_rate,
4851                                                  alloc, &num_active);
4852         if (ret)
4853                 return ret;
4854
4855         alloc_size = skl_ddb_entry_size(alloc);
4856         if (alloc_size == 0)
4857                 return 0;
4858
4859         /* Allocate fixed number of blocks for cursor. */
4860         total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
4861         alloc_size -= total[PLANE_CURSOR];
4862         crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
4863                 alloc->end - total[PLANE_CURSOR];
4864         crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
4865
4866         if (total_data_rate == 0)
4867                 return 0;
4868
4869         /*
4870          * Find the highest watermark level for which we can satisfy the block
4871          * requirement of active planes.
4872          */
4873         for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
4874                 blocks = 0;
4875                 for_each_plane_id_on_crtc(crtc, plane_id) {
4876                         const struct skl_plane_wm *wm =
4877                                 &crtc_state->wm.skl.optimal.planes[plane_id];
4878
4879                         if (plane_id == PLANE_CURSOR) {
4880                                 if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
4881                                         drm_WARN_ON(&dev_priv->drm,
4882                                                     wm->wm[level].min_ddb_alloc != U16_MAX);
4883                                         blocks = U32_MAX;
4884                                         break;
4885                                 }
4886                                 continue;
4887                         }
4888
4889                         blocks += wm->wm[level].min_ddb_alloc;
4890                         blocks += wm->uv_wm[level].min_ddb_alloc;
4891                 }
4892
4893                 if (blocks <= alloc_size) {
4894                         alloc_size -= blocks;
4895                         break;
4896                 }
4897         }
4898
4899         if (level < 0) {
4900                 drm_dbg_kms(&dev_priv->drm,
4901                             "Requested display configuration exceeds system DDB limitations");
4902                 drm_dbg_kms(&dev_priv->drm, "minimum required %d/%d\n",
4903                             blocks, alloc_size);
4904                 return -EINVAL;
4905         }
4906
4907         /*
4908          * Grant each plane the blocks it requires at the highest achievable
4909          * watermark level, plus an extra share of the leftover blocks
4910          * proportional to its relative data rate.
4911          */
4912         for_each_plane_id_on_crtc(crtc, plane_id) {
4913                 const struct skl_plane_wm *wm =
4914                         &crtc_state->wm.skl.optimal.planes[plane_id];
4915                 u64 rate;
4916                 u16 extra;
4917
4918                 if (plane_id == PLANE_CURSOR)
4919                         continue;
4920
4921                 /*
4922                  * We've accounted for all active planes; remaining planes are
4923                  * all disabled.
4924                  */
4925                 if (total_data_rate == 0)
4926                         break;
4927
4928                 rate = plane_data_rate[plane_id];
4929                 extra = min_t(u16, alloc_size,
4930                               DIV64_U64_ROUND_UP(alloc_size * rate,
4931                                                  total_data_rate));
4932                 total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
4933                 alloc_size -= extra;
4934                 total_data_rate -= rate;
4935
4936                 if (total_data_rate == 0)
4937                         break;
4938
4939                 rate = uv_plane_data_rate[plane_id];
4940                 extra = min_t(u16, alloc_size,
4941                               DIV64_U64_ROUND_UP(alloc_size * rate,
4942                                                  total_data_rate));
4943                 uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
4944                 alloc_size -= extra;
4945                 total_data_rate -= rate;
4946         }
4947         drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
4948
4949         /* Set the actual DDB start/end points for each plane */
4950         start = alloc->start;
4951         for_each_plane_id_on_crtc(crtc, plane_id) {
4952                 struct skl_ddb_entry *plane_alloc =
4953                         &crtc_state->wm.skl.plane_ddb_y[plane_id];
4954                 struct skl_ddb_entry *uv_plane_alloc =
4955                         &crtc_state->wm.skl.plane_ddb_uv[plane_id];
4956
4957                 if (plane_id == PLANE_CURSOR)
4958                         continue;
4959
4960                 /* Gen11+ uses a separate plane for UV watermarks */
4961                 drm_WARN_ON(&dev_priv->drm,
4962                             INTEL_GEN(dev_priv) >= 11 && uv_total[plane_id]);
4963
4964                 /* Leave disabled planes at (0,0) */
4965                 if (total[plane_id]) {
4966                         plane_alloc->start = start;
4967                         start += total[plane_id];
4968                         plane_alloc->end = start;
4969                 }
4970
4971                 if (uv_total[plane_id]) {
4972                         uv_plane_alloc->start = start;
4973                         start += uv_total[plane_id];
4974                         uv_plane_alloc->end = start;
4975                 }
4976         }
4977
4978         /*
4979          * When we calculated watermark values we didn't know how high
4980          * of a level we'd actually be able to hit, so we just marked
4981          * all levels as "enabled."  Go back now and disable the ones
4982          * that aren't actually possible.
4983          */
4984         for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
4985                 for_each_plane_id_on_crtc(crtc, plane_id) {
4986                         struct skl_plane_wm *wm =
4987                                 &crtc_state->wm.skl.optimal.planes[plane_id];
4988
4989                         /*
4990                          * We only disable the watermarks for each plane if
4991                          * they exceed the ddb allocation of said plane. This
4992                          * is done so that we don't end up touching cursor
4993                          * watermarks needlessly when some other plane reduces
4994                          * our max possible watermark level.
4995                          *
4996                          * Bspec has this to say about the PLANE_WM enable bit:
4997                          * "All the watermarks at this level for all enabled
4998                          *  planes must be enabled before the level will be used."
4999                          * So this is actually safe to do.
5000                          */
5001                         if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
5002                             wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
5003                                 memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
5004
5005                         /*
5006                          * Wa_1408961008:icl, ehl
5007                          * Underruns with WM1+ disabled
5008                          */
5009                         if (IS_GEN(dev_priv, 11) &&
5010                             level == 1 && wm->wm[0].plane_en) {
5011                                 wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
5012                                 wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
5013                                 wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
5014                         }
5015                 }
5016         }
5017
5018         /*
5019          * Go back and disable the transition watermark if it turns out we
5020          * don't have enough DDB blocks for it.
5021          */
5022         for_each_plane_id_on_crtc(crtc, plane_id) {
5023                 struct skl_plane_wm *wm =
5024                         &crtc_state->wm.skl.optimal.planes[plane_id];
5025
5026                 if (wm->trans_wm.plane_res_b >= total[plane_id])
5027                         memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
5028         }
5029
5030         return 0;
5031 }
5032
5033 /*
5034  * The max latency should be 257 (max the punit can code is 255 and we add 2us
5035  * for the read latency) and cpp should always be <= 8, so that
5036  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
5037  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
5038 */
5039 static uint_fixed_16_16_t
5040 skl_wm_method1(const struct drm_i915_private *dev_priv, u32 pixel_rate,
5041                u8 cpp, u32 latency, u32 dbuf_block_size)
5042 {
5043         u32 wm_intermediate_val;
5044         uint_fixed_16_16_t ret;
5045
5046         if (latency == 0)
5047                 return FP_16_16_MAX;
5048
5049         wm_intermediate_val = latency * pixel_rate * cpp;
5050         ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
5051
5052         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
5053                 ret = add_fixed16_u32(ret, 1);
5054
5055         return ret;
5056 }
5057
5058 static uint_fixed_16_16_t
5059 skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
5060                uint_fixed_16_16_t plane_blocks_per_line)
5061 {
5062         u32 wm_intermediate_val;
5063         uint_fixed_16_16_t ret;
5064
5065         if (latency == 0)
5066                 return FP_16_16_MAX;
5067
5068         wm_intermediate_val = latency * pixel_rate;
5069         wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
5070                                            pipe_htotal * 1000);
5071         ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line);
5072         return ret;
5073 }
5074
5075 static uint_fixed_16_16_t
5076 intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
5077 {
5078         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5079         u32 pixel_rate;
5080         u32 crtc_htotal;
5081         uint_fixed_16_16_t linetime_us;
5082
5083         if (!crtc_state->hw.active)
5084                 return u32_to_fixed16(0);
5085
5086         pixel_rate = crtc_state->pixel_rate;
5087
5088         if (drm_WARN_ON(&dev_priv->drm, pixel_rate == 0))
5089                 return u32_to_fixed16(0);
5090
5091         crtc_htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
5092         linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
5093
5094         return linetime_us;
5095 }
5096
5097 static u32
5098 skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
5099                               const struct intel_plane_state *plane_state)
5100 {
5101         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5102         u64 adjusted_pixel_rate;
5103         uint_fixed_16_16_t downscale_amount;
5104
5105         /* Shouldn't reach here on disabled planes... */
5106         if (drm_WARN_ON(&dev_priv->drm,
5107                         !intel_wm_plane_visible(crtc_state, plane_state)))
5108                 return 0;
5109
5110         /*
5111          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
5112          * with additional adjustments for plane-specific scaling.
5113          */
5114         adjusted_pixel_rate = crtc_state->pixel_rate;
5115         downscale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
5116
5117         return mul_round_up_u32_fixed16(adjusted_pixel_rate,
5118                                             downscale_amount);
5119 }
5120
5121 static int
5122 skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
5123                       int width, const struct drm_format_info *format,
5124                       u64 modifier, unsigned int rotation,
5125                       u32 plane_pixel_rate, struct skl_wm_params *wp,
5126                       int color_plane)
5127 {
5128         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5129         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5130         u32 interm_pbpl;
5131
5132         /* only planar format has two planes */
5133         if (color_plane == 1 &&
5134             !intel_format_info_is_yuv_semiplanar(format, modifier)) {
5135                 drm_dbg_kms(&dev_priv->drm,
5136                             "Non planar format have single plane\n");
5137                 return -EINVAL;
5138         }
5139
5140         wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
5141                       modifier == I915_FORMAT_MOD_Yf_TILED ||
5142                       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
5143                       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
5144         wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED;
5145         wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
5146                          modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
5147         wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier);
5148
5149         wp->width = width;
5150         if (color_plane == 1 && wp->is_planar)
5151                 wp->width /= 2;
5152
5153         wp->cpp = format->cpp[color_plane];
5154         wp->plane_pixel_rate = plane_pixel_rate;
5155
5156         if (INTEL_GEN(dev_priv) >= 11 &&
5157             modifier == I915_FORMAT_MOD_Yf_TILED  && wp->cpp == 1)
5158                 wp->dbuf_block_size = 256;
5159         else
5160                 wp->dbuf_block_size = 512;
5161
5162         if (drm_rotation_90_or_270(rotation)) {
5163                 switch (wp->cpp) {
5164                 case 1:
5165                         wp->y_min_scanlines = 16;
5166                         break;
5167                 case 2:
5168                         wp->y_min_scanlines = 8;
5169                         break;
5170                 case 4:
5171                         wp->y_min_scanlines = 4;
5172                         break;
5173                 default:
5174                         MISSING_CASE(wp->cpp);
5175                         return -EINVAL;
5176                 }
5177         } else {
5178                 wp->y_min_scanlines = 4;
5179         }
5180
5181         if (skl_needs_memory_bw_wa(dev_priv))
5182                 wp->y_min_scanlines *= 2;
5183
5184         wp->plane_bytes_per_line = wp->width * wp->cpp;
5185         if (wp->y_tiled) {
5186                 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
5187                                            wp->y_min_scanlines,
5188                                            wp->dbuf_block_size);
5189
5190                 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
5191                         interm_pbpl++;
5192
5193                 wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
5194                                                         wp->y_min_scanlines);
5195         } else {
5196                 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
5197                                            wp->dbuf_block_size);
5198
5199                 if (!wp->x_tiled ||
5200                     INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
5201                         interm_pbpl++;
5202
5203                 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
5204         }
5205
5206         wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines,
5207                                              wp->plane_blocks_per_line);
5208
5209         wp->linetime_us = fixed16_to_u32_round_up(
5210                                         intel_get_linetime_us(crtc_state));
5211
5212         return 0;
5213 }
5214
5215 static int
5216 skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
5217                             const struct intel_plane_state *plane_state,
5218                             struct skl_wm_params *wp, int color_plane)
5219 {
5220         const struct drm_framebuffer *fb = plane_state->hw.fb;
5221         int width;
5222
5223         /*
5224          * Src coordinates are already rotated by 270 degrees for
5225          * the 90/270 degree plane rotation cases (to match the
5226          * GTT mapping), hence no need to account for rotation here.
5227          */
5228         width = drm_rect_width(&plane_state->uapi.src) >> 16;
5229
5230         return skl_compute_wm_params(crtc_state, width,
5231                                      fb->format, fb->modifier,
5232                                      plane_state->hw.rotation,
5233                                      skl_adjusted_plane_pixel_rate(crtc_state, plane_state),
5234                                      wp, color_plane);
5235 }
5236
5237 static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
5238 {
5239         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
5240                 return true;
5241
5242         /* The number of lines are ignored for the level 0 watermark. */
5243         return level > 0;
5244 }
5245
5246 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
5247                                  int level,
5248                                  unsigned int latency,
5249                                  const struct skl_wm_params *wp,
5250                                  const struct skl_wm_level *result_prev,
5251                                  struct skl_wm_level *result /* out */)
5252 {
5253         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5254         uint_fixed_16_16_t method1, method2;
5255         uint_fixed_16_16_t selected_result;
5256         u32 res_blocks, res_lines, min_ddb_alloc = 0;
5257
5258         if (latency == 0) {
5259                 /* reject it */
5260                 result->min_ddb_alloc = U16_MAX;
5261                 return;
5262         }
5263
5264         /*
5265          * WaIncreaseLatencyIPCEnabled: kbl,cfl
5266          * Display WA #1141: kbl,cfl
5267          */
5268         if ((IS_KABYLAKE(dev_priv) ||
5269              IS_COFFEELAKE(dev_priv) ||
5270              IS_COMETLAKE(dev_priv)) &&
5271             dev_priv->ipc_enabled)
5272                 latency += 4;
5273
5274         if (skl_needs_memory_bw_wa(dev_priv) && wp->x_tiled)
5275                 latency += 15;
5276
5277         method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
5278                                  wp->cpp, latency, wp->dbuf_block_size);
5279         method2 = skl_wm_method2(wp->plane_pixel_rate,
5280                                  crtc_state->hw.adjusted_mode.crtc_htotal,
5281                                  latency,
5282                                  wp->plane_blocks_per_line);
5283
5284         if (wp->y_tiled) {
5285                 selected_result = max_fixed16(method2, wp->y_tile_minimum);
5286         } else {
5287                 if ((wp->cpp * crtc_state->hw.adjusted_mode.crtc_htotal /
5288                      wp->dbuf_block_size < 1) &&
5289                      (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
5290                         selected_result = method2;
5291                 } else if (latency >= wp->linetime_us) {
5292                         if (IS_GEN(dev_priv, 9) &&
5293                             !IS_GEMINILAKE(dev_priv))
5294                                 selected_result = min_fixed16(method1, method2);
5295                         else
5296                                 selected_result = method2;
5297                 } else {
5298                         selected_result = method1;
5299                 }
5300         }
5301
5302         res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
5303         res_lines = div_round_up_fixed16(selected_result,
5304                                          wp->plane_blocks_per_line);
5305
5306         if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
5307                 /* Display WA #1125: skl,bxt,kbl */
5308                 if (level == 0 && wp->rc_surface)
5309                         res_blocks +=
5310                                 fixed16_to_u32_round_up(wp->y_tile_minimum);
5311
5312                 /* Display WA #1126: skl,bxt,kbl */
5313                 if (level >= 1 && level <= 7) {
5314                         if (wp->y_tiled) {
5315                                 res_blocks +=
5316                                     fixed16_to_u32_round_up(wp->y_tile_minimum);
5317                                 res_lines += wp->y_min_scanlines;
5318                         } else {
5319                                 res_blocks++;
5320                         }
5321
5322                         /*
5323                          * Make sure result blocks for higher latency levels are
5324                          * atleast as high as level below the current level.
5325                          * Assumption in DDB algorithm optimization for special
5326                          * cases. Also covers Display WA #1125 for RC.
5327                          */
5328                         if (result_prev->plane_res_b > res_blocks)
5329                                 res_blocks = result_prev->plane_res_b;
5330                 }
5331         }
5332
5333         if (INTEL_GEN(dev_priv) >= 11) {
5334                 if (wp->y_tiled) {
5335                         int extra_lines;
5336
5337                         if (res_lines % wp->y_min_scanlines == 0)
5338                                 extra_lines = wp->y_min_scanlines;
5339                         else
5340                                 extra_lines = wp->y_min_scanlines * 2 -
5341                                         res_lines % wp->y_min_scanlines;
5342
5343                         min_ddb_alloc = mul_round_up_u32_fixed16(res_lines + extra_lines,
5344                                                                  wp->plane_blocks_per_line);
5345                 } else {
5346                         min_ddb_alloc = res_blocks +
5347                                 DIV_ROUND_UP(res_blocks, 10);
5348                 }
5349         }
5350
5351         if (!skl_wm_has_lines(dev_priv, level))
5352                 res_lines = 0;
5353
5354         if (res_lines > 31) {
5355                 /* reject it */
5356                 result->min_ddb_alloc = U16_MAX;
5357                 return;
5358         }
5359
5360         /*
5361          * If res_lines is valid, assume we can use this watermark level
5362          * for now.  We'll come back and disable it after we calculate the
5363          * DDB allocation if it turns out we don't actually have enough
5364          * blocks to satisfy it.
5365          */
5366         result->plane_res_b = res_blocks;
5367         result->plane_res_l = res_lines;
5368         /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */
5369         result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
5370         result->plane_en = true;
5371 }
5372
5373 static void
5374 skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
5375                       const struct skl_wm_params *wm_params,
5376                       struct skl_wm_level *levels)
5377 {
5378         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5379         int level, max_level = ilk_wm_max_level(dev_priv);
5380         struct skl_wm_level *result_prev = &levels[0];
5381
5382         for (level = 0; level <= max_level; level++) {
5383                 struct skl_wm_level *result = &levels[level];
5384                 unsigned int latency = dev_priv->wm.skl_latency[level];
5385
5386                 skl_compute_plane_wm(crtc_state, level, latency,
5387                                      wm_params, result_prev, result);
5388
5389                 result_prev = result;
5390         }
5391 }
5392
5393 static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
5394                                 const struct skl_wm_params *wm_params,
5395                                 struct skl_plane_wm *plane_wm)
5396 {
5397         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5398         struct skl_wm_level *sagv_wm = &plane_wm->sagv_wm0;
5399         struct skl_wm_level *levels = plane_wm->wm;
5400         unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us;
5401
5402         skl_compute_plane_wm(crtc_state, 0, latency,
5403                              wm_params, &levels[0],
5404                              sagv_wm);
5405 }
5406
5407 static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
5408                                       const struct skl_wm_params *wp,
5409                                       struct skl_plane_wm *wm)
5410 {
5411         struct drm_device *dev = crtc_state->uapi.crtc->dev;
5412         const struct drm_i915_private *dev_priv = to_i915(dev);
5413         u16 trans_min, trans_amount, trans_y_tile_min;
5414         u16 wm0_sel_res_b, trans_offset_b, res_blocks;
5415
5416         /* Transition WM don't make any sense if ipc is disabled */
5417         if (!dev_priv->ipc_enabled)
5418                 return;
5419
5420         /*
5421          * WaDisableTWM:skl,kbl,cfl,bxt
5422          * Transition WM are not recommended by HW team for GEN9
5423          */
5424         if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
5425                 return;
5426
5427         if (INTEL_GEN(dev_priv) >= 11)
5428                 trans_min = 4;
5429         else
5430                 trans_min = 14;
5431
5432         /* Display WA #1140: glk,cnl */
5433         if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
5434                 trans_amount = 0;
5435         else
5436                 trans_amount = 10; /* This is configurable amount */
5437
5438         trans_offset_b = trans_min + trans_amount;
5439
5440         /*
5441          * The spec asks for Selected Result Blocks for wm0 (the real value),
5442          * not Result Blocks (the integer value). Pay attention to the capital
5443          * letters. The value wm_l0->plane_res_b is actually Result Blocks, but
5444          * since Result Blocks is the ceiling of Selected Result Blocks plus 1,
5445          * and since we later will have to get the ceiling of the sum in the
5446          * transition watermarks calculation, we can just pretend Selected
5447          * Result Blocks is Result Blocks minus 1 and it should work for the
5448          * current platforms.
5449          */
5450         wm0_sel_res_b = wm->wm[0].plane_res_b - 1;
5451
5452         if (wp->y_tiled) {
5453                 trans_y_tile_min =
5454                         (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum);
5455                 res_blocks = max(wm0_sel_res_b, trans_y_tile_min) +
5456                                 trans_offset_b;
5457         } else {
5458                 res_blocks = wm0_sel_res_b + trans_offset_b;
5459         }
5460
5461         /*
5462          * Just assume we can enable the transition watermark.  After
5463          * computing the DDB we'll come back and disable it if that
5464          * assumption turns out to be false.
5465          */
5466         wm->trans_wm.plane_res_b = res_blocks + 1;
5467         wm->trans_wm.plane_en = true;
5468 }
5469
5470 static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
5471                                      const struct intel_plane_state *plane_state,
5472                                      enum plane_id plane_id, int color_plane)
5473 {
5474         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5475         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5476         struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
5477         struct skl_wm_params wm_params;
5478         int ret;
5479
5480         ret = skl_compute_plane_wm_params(crtc_state, plane_state,
5481                                           &wm_params, color_plane);
5482         if (ret)
5483                 return ret;
5484
5485         skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
5486
5487         if (INTEL_GEN(dev_priv) >= 12)
5488                 tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
5489
5490         skl_compute_transition_wm(crtc_state, &wm_params, wm);
5491
5492         return 0;
5493 }
5494
5495 static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
5496                                  const struct intel_plane_state *plane_state,
5497                                  enum plane_id plane_id)
5498 {
5499         struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
5500         struct skl_wm_params wm_params;
5501         int ret;
5502
5503         wm->is_planar = true;
5504
5505         /* uv plane watermarks must also be validated for NV12/Planar */
5506         ret = skl_compute_plane_wm_params(crtc_state, plane_state,
5507                                           &wm_params, 1);
5508         if (ret)
5509                 return ret;
5510
5511         skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
5512
5513         return 0;
5514 }
5515
5516 static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
5517                               const struct intel_plane_state *plane_state)
5518 {
5519         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
5520         const struct drm_framebuffer *fb = plane_state->hw.fb;
5521         enum plane_id plane_id = plane->id;
5522         int ret;
5523
5524         if (!intel_wm_plane_visible(crtc_state, plane_state))
5525                 return 0;
5526
5527         ret = skl_build_plane_wm_single(crtc_state, plane_state,
5528                                         plane_id, 0);
5529         if (ret)
5530                 return ret;
5531
5532         if (fb->format->is_yuv && fb->format->num_planes > 1) {
5533                 ret = skl_build_plane_wm_uv(crtc_state, plane_state,
5534                                             plane_id);
5535                 if (ret)
5536                         return ret;
5537         }
5538
5539         return 0;
5540 }
5541
5542 static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
5543                               const struct intel_plane_state *plane_state)
5544 {
5545         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5546         enum plane_id plane_id = to_intel_plane(plane_state->uapi.plane)->id;
5547         int ret;
5548
5549         /* Watermarks calculated in master */
5550         if (plane_state->planar_slave)
5551                 return 0;
5552
5553         if (plane_state->planar_linked_plane) {
5554                 const struct drm_framebuffer *fb = plane_state->hw.fb;
5555                 enum plane_id y_plane_id = plane_state->planar_linked_plane->id;
5556
5557                 drm_WARN_ON(&dev_priv->drm,
5558                             !intel_wm_plane_visible(crtc_state, plane_state));
5559                 drm_WARN_ON(&dev_priv->drm, !fb->format->is_yuv ||
5560                             fb->format->num_planes == 1);
5561
5562                 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5563                                                 y_plane_id, 0);
5564                 if (ret)
5565                         return ret;
5566
5567                 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5568                                                 plane_id, 1);
5569                 if (ret)
5570                         return ret;
5571         } else if (intel_wm_plane_visible(crtc_state, plane_state)) {
5572                 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5573                                                 plane_id, 0);
5574                 if (ret)
5575                         return ret;
5576         }
5577
5578         return 0;
5579 }
5580
5581 static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
5582 {
5583         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5584         struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
5585         struct intel_plane *plane;
5586         const struct intel_plane_state *plane_state;
5587         int ret;
5588
5589         /*
5590          * We'll only calculate watermarks for planes that are actually
5591          * enabled, so make sure all other planes are set as disabled.
5592          */
5593         memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
5594
5595         intel_atomic_crtc_state_for_each_plane_state(plane, plane_state,
5596                                                      crtc_state) {
5597
5598                 if (INTEL_GEN(dev_priv) >= 11)
5599                         ret = icl_build_plane_wm(crtc_state, plane_state);
5600                 else
5601                         ret = skl_build_plane_wm(crtc_state, plane_state);
5602                 if (ret)
5603                         return ret;
5604         }
5605
5606         return 0;
5607 }
5608
5609 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
5610                                 i915_reg_t reg,
5611                                 const struct skl_ddb_entry *entry)
5612 {
5613         if (entry->end)
5614                 intel_de_write_fw(dev_priv, reg,
5615                                   (entry->end - 1) << 16 | entry->start);
5616         else
5617                 intel_de_write_fw(dev_priv, reg, 0);
5618 }
5619
5620 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
5621                                i915_reg_t reg,
5622                                const struct skl_wm_level *level)
5623 {
5624         u32 val = 0;
5625
5626         if (level->plane_en)
5627                 val |= PLANE_WM_EN;
5628         if (level->ignore_lines)
5629                 val |= PLANE_WM_IGNORE_LINES;
5630         val |= level->plane_res_b;
5631         val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
5632
5633         intel_de_write_fw(dev_priv, reg, val);
5634 }
5635
5636 void skl_write_plane_wm(struct intel_plane *plane,
5637                         const struct intel_crtc_state *crtc_state)
5638 {
5639         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5640         int level, max_level = ilk_wm_max_level(dev_priv);
5641         enum plane_id plane_id = plane->id;
5642         enum pipe pipe = plane->pipe;
5643         const struct skl_plane_wm *wm =
5644                 &crtc_state->wm.skl.optimal.planes[plane_id];
5645         const struct skl_ddb_entry *ddb_y =
5646                 &crtc_state->wm.skl.plane_ddb_y[plane_id];
5647         const struct skl_ddb_entry *ddb_uv =
5648                 &crtc_state->wm.skl.plane_ddb_uv[plane_id];
5649
5650         for (level = 0; level <= max_level; level++) {
5651                 const struct skl_wm_level *wm_level;
5652
5653                 wm_level = skl_plane_wm_level(crtc_state, plane_id, level);
5654
5655                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
5656                                    wm_level);
5657         }
5658         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
5659                            &wm->trans_wm);
5660
5661         if (INTEL_GEN(dev_priv) >= 11) {
5662                 skl_ddb_entry_write(dev_priv,
5663                                     PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5664                 return;
5665         }
5666
5667         if (wm->is_planar)
5668                 swap(ddb_y, ddb_uv);
5669
5670         skl_ddb_entry_write(dev_priv,
5671                             PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5672         skl_ddb_entry_write(dev_priv,
5673                             PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
5674 }
5675
5676 void skl_write_cursor_wm(struct intel_plane *plane,
5677                          const struct intel_crtc_state *crtc_state)
5678 {
5679         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5680         int level, max_level = ilk_wm_max_level(dev_priv);
5681         enum plane_id plane_id = plane->id;
5682         enum pipe pipe = plane->pipe;
5683         const struct skl_plane_wm *wm =
5684                 &crtc_state->wm.skl.optimal.planes[plane_id];
5685         const struct skl_ddb_entry *ddb =
5686                 &crtc_state->wm.skl.plane_ddb_y[plane_id];
5687
5688         for (level = 0; level <= max_level; level++) {
5689                 const struct skl_wm_level *wm_level;
5690
5691                 wm_level = skl_plane_wm_level(crtc_state, plane_id, level);
5692
5693                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
5694                                    wm_level);
5695         }
5696         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
5697
5698         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
5699 }
5700
5701 bool skl_wm_level_equals(const struct skl_wm_level *l1,
5702                          const struct skl_wm_level *l2)
5703 {
5704         return l1->plane_en == l2->plane_en &&
5705                 l1->ignore_lines == l2->ignore_lines &&
5706                 l1->plane_res_l == l2->plane_res_l &&
5707                 l1->plane_res_b == l2->plane_res_b;
5708 }
5709
5710 static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv,
5711                                 const struct skl_plane_wm *wm1,
5712                                 const struct skl_plane_wm *wm2)
5713 {
5714         int level, max_level = ilk_wm_max_level(dev_priv);
5715
5716         for (level = 0; level <= max_level; level++) {
5717                 /*
5718                  * We don't check uv_wm as the hardware doesn't actually
5719                  * use it. It only gets used for calculating the required
5720                  * ddb allocation.
5721                  */
5722                 if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]))
5723                         return false;
5724         }
5725
5726         return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm);
5727 }
5728
5729 static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
5730                                     const struct skl_ddb_entry *b)
5731 {
5732         return a->start < b->end && b->start < a->end;
5733 }
5734
5735 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
5736                                  const struct skl_ddb_entry *entries,
5737                                  int num_entries, int ignore_idx)
5738 {
5739         int i;
5740
5741         for (i = 0; i < num_entries; i++) {
5742                 if (i != ignore_idx &&
5743                     skl_ddb_entries_overlap(ddb, &entries[i]))
5744                         return true;
5745         }
5746
5747         return false;
5748 }
5749
5750 static int
5751 skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
5752                             struct intel_crtc_state *new_crtc_state)
5753 {
5754         struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->uapi.state);
5755         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5756         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5757         struct intel_plane *plane;
5758
5759         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5760                 struct intel_plane_state *plane_state;
5761                 enum plane_id plane_id = plane->id;
5762
5763                 if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
5764                                         &new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
5765                     skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
5766                                         &new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
5767                         continue;
5768
5769                 plane_state = intel_atomic_get_plane_state(state, plane);
5770                 if (IS_ERR(plane_state))
5771                         return PTR_ERR(plane_state);
5772
5773                 new_crtc_state->update_planes |= BIT(plane_id);
5774         }
5775
5776         return 0;
5777 }
5778
5779 static int
5780 skl_compute_ddb(struct intel_atomic_state *state)
5781 {
5782         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5783         const struct intel_dbuf_state *old_dbuf_state;
5784         const struct intel_dbuf_state *new_dbuf_state;
5785         const struct intel_crtc_state *old_crtc_state;
5786         struct intel_crtc_state *new_crtc_state;
5787         struct intel_crtc *crtc;
5788         int ret, i;
5789
5790         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5791                                             new_crtc_state, i) {
5792                 ret = skl_allocate_pipe_ddb(new_crtc_state);
5793                 if (ret)
5794                         return ret;
5795
5796                 ret = skl_ddb_add_affected_planes(old_crtc_state,
5797                                                   new_crtc_state);
5798                 if (ret)
5799                         return ret;
5800         }
5801
5802         old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
5803         new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
5804
5805         if (new_dbuf_state &&
5806             new_dbuf_state->enabled_slices != old_dbuf_state->enabled_slices)
5807                 drm_dbg_kms(&dev_priv->drm,
5808                             "Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n",
5809                             old_dbuf_state->enabled_slices,
5810                             new_dbuf_state->enabled_slices,
5811                             INTEL_INFO(dev_priv)->num_supported_dbuf_slices);
5812
5813         return 0;
5814 }
5815
5816 static char enast(bool enable)
5817 {
5818         return enable ? '*' : ' ';
5819 }
5820
5821 static void
5822 skl_print_wm_changes(struct intel_atomic_state *state)
5823 {
5824         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5825         const struct intel_crtc_state *old_crtc_state;
5826         const struct intel_crtc_state *new_crtc_state;
5827         struct intel_plane *plane;
5828         struct intel_crtc *crtc;
5829         int i;
5830
5831         if (!drm_debug_enabled(DRM_UT_KMS))
5832                 return;
5833
5834         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5835                                             new_crtc_state, i) {
5836                 const struct skl_pipe_wm *old_pipe_wm, *new_pipe_wm;
5837
5838                 old_pipe_wm = &old_crtc_state->wm.skl.optimal;
5839                 new_pipe_wm = &new_crtc_state->wm.skl.optimal;
5840
5841                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5842                         enum plane_id plane_id = plane->id;
5843                         const struct skl_ddb_entry *old, *new;
5844
5845                         old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
5846                         new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
5847
5848                         if (skl_ddb_entry_equal(old, new))
5849                                 continue;
5850
5851                         drm_dbg_kms(&dev_priv->drm,
5852                                     "[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
5853                                     plane->base.base.id, plane->base.name,
5854                                     old->start, old->end, new->start, new->end,
5855                                     skl_ddb_entry_size(old), skl_ddb_entry_size(new));
5856                 }
5857
5858                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5859                         enum plane_id plane_id = plane->id;
5860                         const struct skl_plane_wm *old_wm, *new_wm;
5861
5862                         old_wm = &old_pipe_wm->planes[plane_id];
5863                         new_wm = &new_pipe_wm->planes[plane_id];
5864
5865                         if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
5866                                 continue;
5867
5868                         drm_dbg_kms(&dev_priv->drm,
5869                                     "[PLANE:%d:%s]   level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm"
5870                                     " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm\n",
5871                                     plane->base.base.id, plane->base.name,
5872                                     enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en),
5873                                     enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en),
5874                                     enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en),
5875                                     enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en),
5876                                     enast(old_wm->trans_wm.plane_en),
5877                                     enast(old_wm->sagv_wm0.plane_en),
5878                                     enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en),
5879                                     enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en),
5880                                     enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en),
5881                                     enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en),
5882                                     enast(new_wm->trans_wm.plane_en),
5883                                     enast(new_wm->sagv_wm0.plane_en));
5884
5885                         drm_dbg_kms(&dev_priv->drm,
5886                                     "[PLANE:%d:%s]   lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
5887                                       " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d\n",
5888                                     plane->base.base.id, plane->base.name,
5889                                     enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
5890                                     enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
5891                                     enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
5892                                     enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
5893                                     enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].plane_res_l,
5894                                     enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].plane_res_l,
5895                                     enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l,
5896                                     enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
5897                                     enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
5898                                     enast(old_wm->sagv_wm0.ignore_lines), old_wm->sagv_wm0.plane_res_l,
5899
5900                                     enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
5901                                     enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
5902                                     enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
5903                                     enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
5904                                     enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].plane_res_l,
5905                                     enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l,
5906                                     enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l,
5907                                     enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
5908                                     enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l,
5909                                     enast(new_wm->sagv_wm0.ignore_lines), new_wm->sagv_wm0.plane_res_l);
5910
5911                         drm_dbg_kms(&dev_priv->drm,
5912                                     "[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
5913                                     " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
5914                                     plane->base.base.id, plane->base.name,
5915                                     old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
5916                                     old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
5917                                     old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
5918                                     old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
5919                                     old_wm->trans_wm.plane_res_b,
5920                                     old_wm->sagv_wm0.plane_res_b,
5921                                     new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
5922                                     new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
5923                                     new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
5924                                     new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
5925                                     new_wm->trans_wm.plane_res_b,
5926                                     new_wm->sagv_wm0.plane_res_b);
5927
5928                         drm_dbg_kms(&dev_priv->drm,
5929                                     "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
5930                                     " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
5931                                     plane->base.base.id, plane->base.name,
5932                                     old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
5933                                     old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
5934                                     old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
5935                                     old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
5936                                     old_wm->trans_wm.min_ddb_alloc,
5937                                     old_wm->sagv_wm0.min_ddb_alloc,
5938                                     new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
5939                                     new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
5940                                     new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
5941                                     new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
5942                                     new_wm->trans_wm.min_ddb_alloc,
5943                                     new_wm->sagv_wm0.min_ddb_alloc);
5944                 }
5945         }
5946 }
5947
5948 static int intel_add_affected_pipes(struct intel_atomic_state *state,
5949                                     u8 pipe_mask)
5950 {
5951         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5952         struct intel_crtc *crtc;
5953
5954         for_each_intel_crtc(&dev_priv->drm, crtc) {
5955                 struct intel_crtc_state *crtc_state;
5956
5957                 if ((pipe_mask & BIT(crtc->pipe)) == 0)
5958                         continue;
5959
5960                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5961                 if (IS_ERR(crtc_state))
5962                         return PTR_ERR(crtc_state);
5963         }
5964
5965         return 0;
5966 }
5967
5968 static int
5969 skl_ddb_add_affected_pipes(struct intel_atomic_state *state)
5970 {
5971         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5972         struct intel_crtc_state *crtc_state;
5973         struct intel_crtc *crtc;
5974         int i, ret;
5975
5976         if (dev_priv->wm.distrust_bios_wm) {
5977                 /*
5978                  * skl_ddb_get_pipe_allocation_limits() currently requires
5979                  * all active pipes to be included in the state so that
5980                  * it can redistribute the dbuf among them, and it really
5981                  * wants to recompute things when distrust_bios_wm is set
5982                  * so we add all the pipes to the state.
5983                  */
5984                 ret = intel_add_affected_pipes(state, ~0);
5985                 if (ret)
5986                         return ret;
5987         }
5988
5989         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5990                 struct intel_dbuf_state *new_dbuf_state;
5991                 const struct intel_dbuf_state *old_dbuf_state;
5992
5993                 new_dbuf_state = intel_atomic_get_dbuf_state(state);
5994                 if (IS_ERR(new_dbuf_state))
5995                         return PTR_ERR(new_dbuf_state);
5996
5997                 old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
5998
5999                 new_dbuf_state->active_pipes =
6000                         intel_calc_active_pipes(state, old_dbuf_state->active_pipes);
6001
6002                 if (old_dbuf_state->active_pipes == new_dbuf_state->active_pipes)
6003                         break;
6004
6005                 ret = intel_atomic_lock_global_state(&new_dbuf_state->base);
6006                 if (ret)
6007                         return ret;
6008
6009                 /*
6010                  * skl_ddb_get_pipe_allocation_limits() currently requires
6011                  * all active pipes to be included in the state so that
6012                  * it can redistribute the dbuf among them.
6013                  */
6014                 ret = intel_add_affected_pipes(state,
6015                                                new_dbuf_state->active_pipes);
6016                 if (ret)
6017                         return ret;
6018
6019                 break;
6020         }
6021
6022         return 0;
6023 }
6024
6025 /*
6026  * To make sure the cursor watermark registers are always consistent
6027  * with our computed state the following scenario needs special
6028  * treatment:
6029  *
6030  * 1. enable cursor
6031  * 2. move cursor entirely offscreen
6032  * 3. disable cursor
6033  *
6034  * Step 2. does call .disable_plane() but does not zero the watermarks
6035  * (since we consider an offscreen cursor still active for the purposes
6036  * of watermarks). Step 3. would not normally call .disable_plane()
6037  * because the actual plane visibility isn't changing, and we don't
6038  * deallocate the cursor ddb until the pipe gets disabled. So we must
6039  * force step 3. to call .disable_plane() to update the watermark
6040  * registers properly.
6041  *
6042  * Other planes do not suffer from this issues as their watermarks are
6043  * calculated based on the actual plane visibility. The only time this
6044  * can trigger for the other planes is during the initial readout as the
6045  * default value of the watermarks registers is not zero.
6046  */
6047 static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
6048                                       struct intel_crtc *crtc)
6049 {
6050         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6051         const struct intel_crtc_state *old_crtc_state =
6052                 intel_atomic_get_old_crtc_state(state, crtc);
6053         struct intel_crtc_state *new_crtc_state =
6054                 intel_atomic_get_new_crtc_state(state, crtc);
6055         struct intel_plane *plane;
6056
6057         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
6058                 struct intel_plane_state *plane_state;
6059                 enum plane_id plane_id = plane->id;
6060
6061                 /*
6062                  * Force a full wm update for every plane on modeset.
6063                  * Required because the reset value of the wm registers
6064                  * is non-zero, whereas we want all disabled planes to
6065                  * have zero watermarks. So if we turn off the relevant
6066                  * power well the hardware state will go out of sync
6067                  * with the software state.
6068                  */
6069                 if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi) &&
6070                     skl_plane_wm_equals(dev_priv,
6071                                         &old_crtc_state->wm.skl.optimal.planes[plane_id],
6072                                         &new_crtc_state->wm.skl.optimal.planes[plane_id]))
6073                         continue;
6074
6075                 plane_state = intel_atomic_get_plane_state(state, plane);
6076                 if (IS_ERR(plane_state))
6077                         return PTR_ERR(plane_state);
6078
6079                 new_crtc_state->update_planes |= BIT(plane_id);
6080         }
6081
6082         return 0;
6083 }
6084
6085 static int
6086 skl_compute_wm(struct intel_atomic_state *state)
6087 {
6088         struct intel_crtc *crtc;
6089         struct intel_crtc_state *new_crtc_state;
6090         struct intel_crtc_state *old_crtc_state;
6091         int ret, i;
6092
6093         ret = skl_ddb_add_affected_pipes(state);
6094         if (ret)
6095                 return ret;
6096
6097         /*
6098          * Calculate WM's for all pipes that are part of this transaction.
6099          * Note that skl_ddb_add_affected_pipes may have added more CRTC's that
6100          * weren't otherwise being modified if pipe allocations had to change.
6101          */
6102         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6103                                             new_crtc_state, i) {
6104                 ret = skl_build_pipe_wm(new_crtc_state);
6105                 if (ret)
6106                         return ret;
6107         }
6108
6109         ret = skl_compute_ddb(state);
6110         if (ret)
6111                 return ret;
6112
6113         ret = intel_compute_sagv_mask(state);
6114         if (ret)
6115                 return ret;
6116
6117         /*
6118          * skl_compute_ddb() will have adjusted the final watermarks
6119          * based on how much ddb is available. Now we can actually
6120          * check if the final watermarks changed.
6121          */
6122         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6123                                             new_crtc_state, i) {
6124                 ret = skl_wm_add_affected_planes(state, crtc);
6125                 if (ret)
6126                         return ret;
6127         }
6128
6129         skl_print_wm_changes(state);
6130
6131         return 0;
6132 }
6133
6134 static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
6135                                   struct intel_wm_config *config)
6136 {
6137         struct intel_crtc *crtc;
6138
6139         /* Compute the currently _active_ config */
6140         for_each_intel_crtc(&dev_priv->drm, crtc) {
6141                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
6142
6143                 if (!wm->pipe_enabled)
6144                         continue;
6145
6146                 config->sprites_enabled |= wm->sprites_enabled;
6147                 config->sprites_scaled |= wm->sprites_scaled;
6148                 config->num_pipes_active++;
6149         }
6150 }
6151
6152 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
6153 {
6154         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
6155         struct ilk_wm_maximums max;
6156         struct intel_wm_config config = {};
6157         struct ilk_wm_values results = {};
6158         enum intel_ddb_partitioning partitioning;
6159
6160         ilk_compute_wm_config(dev_priv, &config);
6161
6162         ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_1_2, &max);
6163         ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2);
6164
6165         /* 5/6 split only in single pipe config on IVB+ */
6166         if (INTEL_GEN(dev_priv) >= 7 &&
6167             config.num_pipes_active == 1 && config.sprites_enabled) {
6168                 ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_5_6, &max);
6169                 ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6);
6170
6171                 best_lp_wm = ilk_find_best_result(dev_priv, &lp_wm_1_2, &lp_wm_5_6);
6172         } else {
6173                 best_lp_wm = &lp_wm_1_2;
6174         }
6175
6176         partitioning = (best_lp_wm == &lp_wm_1_2) ?
6177                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
6178
6179         ilk_compute_wm_results(dev_priv, best_lp_wm, partitioning, &results);
6180
6181         ilk_write_wm_values(dev_priv, &results);
6182 }
6183
6184 static void ilk_initial_watermarks(struct intel_atomic_state *state,
6185                                    struct intel_crtc *crtc)
6186 {
6187         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6188         const struct intel_crtc_state *crtc_state =
6189                 intel_atomic_get_new_crtc_state(state, crtc);
6190
6191         mutex_lock(&dev_priv->wm.wm_mutex);
6192         crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
6193         ilk_program_watermarks(dev_priv);
6194         mutex_unlock(&dev_priv->wm.wm_mutex);
6195 }
6196
6197 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
6198                                     struct intel_crtc *crtc)
6199 {
6200         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6201         const struct intel_crtc_state *crtc_state =
6202                 intel_atomic_get_new_crtc_state(state, crtc);
6203
6204         if (!crtc_state->wm.need_postvbl_update)
6205                 return;
6206
6207         mutex_lock(&dev_priv->wm.wm_mutex);
6208         crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
6209         ilk_program_watermarks(dev_priv);
6210         mutex_unlock(&dev_priv->wm.wm_mutex);
6211 }
6212
6213 static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
6214 {
6215         level->plane_en = val & PLANE_WM_EN;
6216         level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
6217         level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
6218         level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
6219                 PLANE_WM_LINES_MASK;
6220 }
6221
6222 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
6223                               struct skl_pipe_wm *out)
6224 {
6225         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6226         enum pipe pipe = crtc->pipe;
6227         int level, max_level;
6228         enum plane_id plane_id;
6229         u32 val;
6230
6231         max_level = ilk_wm_max_level(dev_priv);
6232
6233         for_each_plane_id_on_crtc(crtc, plane_id) {
6234                 struct skl_plane_wm *wm = &out->planes[plane_id];
6235
6236                 for (level = 0; level <= max_level; level++) {
6237                         if (plane_id != PLANE_CURSOR)
6238                                 val = I915_READ(PLANE_WM(pipe, plane_id, level));
6239                         else
6240                                 val = I915_READ(CUR_WM(pipe, level));
6241
6242                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
6243                 }
6244
6245                 if (INTEL_GEN(dev_priv) >= 12)
6246                         wm->sagv_wm0 = wm->wm[0];
6247
6248                 if (plane_id != PLANE_CURSOR)
6249                         val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
6250                 else
6251                         val = I915_READ(CUR_WM_TRANS(pipe));
6252
6253                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
6254         }
6255
6256         if (!crtc->active)
6257                 return;
6258 }
6259
6260 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
6261 {
6262         struct intel_crtc *crtc;
6263         struct intel_crtc_state *crtc_state;
6264
6265         for_each_intel_crtc(&dev_priv->drm, crtc) {
6266                 crtc_state = to_intel_crtc_state(crtc->base.state);
6267
6268                 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
6269         }
6270
6271         if (dev_priv->active_pipes) {
6272                 /* Fully recompute DDB on first atomic commit */
6273                 dev_priv->wm.distrust_bios_wm = true;
6274         }
6275 }
6276
6277 static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
6278 {
6279         struct drm_device *dev = crtc->base.dev;
6280         struct drm_i915_private *dev_priv = to_i915(dev);
6281         struct ilk_wm_values *hw = &dev_priv->wm.hw;
6282         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
6283         struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
6284         enum pipe pipe = crtc->pipe;
6285         static const i915_reg_t wm0_pipe_reg[] = {
6286                 [PIPE_A] = WM0_PIPEA_ILK,
6287                 [PIPE_B] = WM0_PIPEB_ILK,
6288                 [PIPE_C] = WM0_PIPEC_IVB,
6289         };
6290
6291         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
6292
6293         memset(active, 0, sizeof(*active));
6294
6295         active->pipe_enabled = crtc->active;
6296
6297         if (active->pipe_enabled) {
6298                 u32 tmp = hw->wm_pipe[pipe];
6299
6300                 /*
6301                  * For active pipes LP0 watermark is marked as
6302                  * enabled, and LP1+ watermaks as disabled since
6303                  * we can't really reverse compute them in case
6304                  * multiple pipes are active.
6305                  */
6306                 active->wm[0].enable = true;
6307                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
6308                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
6309                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
6310         } else {
6311                 int level, max_level = ilk_wm_max_level(dev_priv);
6312
6313                 /*
6314                  * For inactive pipes, all watermark levels
6315                  * should be marked as enabled but zeroed,
6316                  * which is what we'd compute them to.
6317                  */
6318                 for (level = 0; level <= max_level; level++)
6319                         active->wm[level].enable = true;
6320         }
6321
6322         crtc->wm.active.ilk = *active;
6323 }
6324
6325 #define _FW_WM(value, plane) \
6326         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
6327 #define _FW_WM_VLV(value, plane) \
6328         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
6329
6330 static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
6331                                struct g4x_wm_values *wm)
6332 {
6333         u32 tmp;
6334
6335         tmp = I915_READ(DSPFW1);
6336         wm->sr.plane = _FW_WM(tmp, SR);
6337         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
6338         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
6339         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
6340
6341         tmp = I915_READ(DSPFW2);
6342         wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
6343         wm->sr.fbc = _FW_WM(tmp, FBC_SR);
6344         wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
6345         wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
6346         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
6347         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
6348
6349         tmp = I915_READ(DSPFW3);
6350         wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
6351         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
6352         wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
6353         wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
6354 }
6355
6356 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
6357                                struct vlv_wm_values *wm)
6358 {
6359         enum pipe pipe;
6360         u32 tmp;
6361
6362         for_each_pipe(dev_priv, pipe) {
6363                 tmp = I915_READ(VLV_DDL(pipe));
6364
6365                 wm->ddl[pipe].plane[PLANE_PRIMARY] =
6366                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6367                 wm->ddl[pipe].plane[PLANE_CURSOR] =
6368                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6369                 wm->ddl[pipe].plane[PLANE_SPRITE0] =
6370                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6371                 wm->ddl[pipe].plane[PLANE_SPRITE1] =
6372                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6373         }
6374
6375         tmp = I915_READ(DSPFW1);
6376         wm->sr.plane = _FW_WM(tmp, SR);
6377         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
6378         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
6379         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
6380
6381         tmp = I915_READ(DSPFW2);
6382         wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
6383         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
6384         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
6385
6386         tmp = I915_READ(DSPFW3);
6387         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
6388
6389         if (IS_CHERRYVIEW(dev_priv)) {
6390                 tmp = I915_READ(DSPFW7_CHV);
6391                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
6392                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
6393
6394                 tmp = I915_READ(DSPFW8_CHV);
6395                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
6396                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
6397
6398                 tmp = I915_READ(DSPFW9_CHV);
6399                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
6400                 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
6401
6402                 tmp = I915_READ(DSPHOWM);
6403                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
6404                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
6405                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
6406                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
6407                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
6408                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
6409                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
6410                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
6411                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
6412                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
6413         } else {
6414                 tmp = I915_READ(DSPFW7);
6415                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
6416                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
6417
6418                 tmp = I915_READ(DSPHOWM);
6419                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
6420                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
6421                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
6422                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
6423                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
6424                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
6425                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
6426         }
6427 }
6428
6429 #undef _FW_WM
6430 #undef _FW_WM_VLV
6431
6432 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
6433 {
6434         struct g4x_wm_values *wm = &dev_priv->wm.g4x;
6435         struct intel_crtc *crtc;
6436
6437         g4x_read_wm_values(dev_priv, wm);
6438
6439         wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
6440
6441         for_each_intel_crtc(&dev_priv->drm, crtc) {
6442                 struct intel_crtc_state *crtc_state =
6443                         to_intel_crtc_state(crtc->base.state);
6444                 struct g4x_wm_state *active = &crtc->wm.active.g4x;
6445                 struct g4x_pipe_wm *raw;
6446                 enum pipe pipe = crtc->pipe;
6447                 enum plane_id plane_id;
6448                 int level, max_level;
6449
6450                 active->cxsr = wm->cxsr;
6451                 active->hpll_en = wm->hpll_en;
6452                 active->fbc_en = wm->fbc_en;
6453
6454                 active->sr = wm->sr;
6455                 active->hpll = wm->hpll;
6456
6457                 for_each_plane_id_on_crtc(crtc, plane_id) {
6458                         active->wm.plane[plane_id] =
6459                                 wm->pipe[pipe].plane[plane_id];
6460                 }
6461
6462                 if (wm->cxsr && wm->hpll_en)
6463                         max_level = G4X_WM_LEVEL_HPLL;
6464                 else if (wm->cxsr)
6465                         max_level = G4X_WM_LEVEL_SR;
6466                 else
6467                         max_level = G4X_WM_LEVEL_NORMAL;
6468
6469                 level = G4X_WM_LEVEL_NORMAL;
6470                 raw = &crtc_state->wm.g4x.raw[level];
6471                 for_each_plane_id_on_crtc(crtc, plane_id)
6472                         raw->plane[plane_id] = active->wm.plane[plane_id];
6473
6474                 if (++level > max_level)
6475                         goto out;
6476
6477                 raw = &crtc_state->wm.g4x.raw[level];
6478                 raw->plane[PLANE_PRIMARY] = active->sr.plane;
6479                 raw->plane[PLANE_CURSOR] = active->sr.cursor;
6480                 raw->plane[PLANE_SPRITE0] = 0;
6481                 raw->fbc = active->sr.fbc;
6482
6483                 if (++level > max_level)
6484                         goto out;
6485
6486                 raw = &crtc_state->wm.g4x.raw[level];
6487                 raw->plane[PLANE_PRIMARY] = active->hpll.plane;
6488                 raw->plane[PLANE_CURSOR] = active->hpll.cursor;
6489                 raw->plane[PLANE_SPRITE0] = 0;
6490                 raw->fbc = active->hpll.fbc;
6491
6492         out:
6493                 for_each_plane_id_on_crtc(crtc, plane_id)
6494                         g4x_raw_plane_wm_set(crtc_state, level,
6495                                              plane_id, USHRT_MAX);
6496                 g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
6497
6498                 crtc_state->wm.g4x.optimal = *active;
6499                 crtc_state->wm.g4x.intermediate = *active;
6500
6501                 drm_dbg_kms(&dev_priv->drm,
6502                             "Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
6503                             pipe_name(pipe),
6504                             wm->pipe[pipe].plane[PLANE_PRIMARY],
6505                             wm->pipe[pipe].plane[PLANE_CURSOR],
6506                             wm->pipe[pipe].plane[PLANE_SPRITE0]);
6507         }
6508
6509         drm_dbg_kms(&dev_priv->drm,
6510                     "Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
6511                     wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
6512         drm_dbg_kms(&dev_priv->drm,
6513                     "Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
6514                     wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
6515         drm_dbg_kms(&dev_priv->drm, "Initial SR=%s HPLL=%s FBC=%s\n",
6516                     yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en));
6517 }
6518
6519 void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
6520 {
6521         struct intel_plane *plane;
6522         struct intel_crtc *crtc;
6523
6524         mutex_lock(&dev_priv->wm.wm_mutex);
6525
6526         for_each_intel_plane(&dev_priv->drm, plane) {
6527                 struct intel_crtc *crtc =
6528                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
6529                 struct intel_crtc_state *crtc_state =
6530                         to_intel_crtc_state(crtc->base.state);
6531                 struct intel_plane_state *plane_state =
6532                         to_intel_plane_state(plane->base.state);
6533                 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
6534                 enum plane_id plane_id = plane->id;
6535                 int level;
6536
6537                 if (plane_state->uapi.visible)
6538                         continue;
6539
6540                 for (level = 0; level < 3; level++) {
6541                         struct g4x_pipe_wm *raw =
6542                                 &crtc_state->wm.g4x.raw[level];
6543
6544                         raw->plane[plane_id] = 0;
6545                         wm_state->wm.plane[plane_id] = 0;
6546                 }
6547
6548                 if (plane_id == PLANE_PRIMARY) {
6549                         for (level = 0; level < 3; level++) {
6550                                 struct g4x_pipe_wm *raw =
6551                                         &crtc_state->wm.g4x.raw[level];
6552                                 raw->fbc = 0;
6553                         }
6554
6555                         wm_state->sr.fbc = 0;
6556                         wm_state->hpll.fbc = 0;
6557                         wm_state->fbc_en = false;
6558                 }
6559         }
6560
6561         for_each_intel_crtc(&dev_priv->drm, crtc) {
6562                 struct intel_crtc_state *crtc_state =
6563                         to_intel_crtc_state(crtc->base.state);
6564
6565                 crtc_state->wm.g4x.intermediate =
6566                         crtc_state->wm.g4x.optimal;
6567                 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
6568         }
6569
6570         g4x_program_watermarks(dev_priv);
6571
6572         mutex_unlock(&dev_priv->wm.wm_mutex);
6573 }
6574
6575 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
6576 {
6577         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
6578         struct intel_crtc *crtc;
6579         u32 val;
6580
6581         vlv_read_wm_values(dev_priv, wm);
6582
6583         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
6584         wm->level = VLV_WM_LEVEL_PM2;
6585
6586         if (IS_CHERRYVIEW(dev_priv)) {
6587                 vlv_punit_get(dev_priv);
6588
6589                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
6590                 if (val & DSP_MAXFIFO_PM5_ENABLE)
6591                         wm->level = VLV_WM_LEVEL_PM5;
6592
6593                 /*
6594                  * If DDR DVFS is disabled in the BIOS, Punit
6595                  * will never ack the request. So if that happens
6596                  * assume we don't have to enable/disable DDR DVFS
6597                  * dynamically. To test that just set the REQ_ACK
6598                  * bit to poke the Punit, but don't change the
6599                  * HIGH/LOW bits so that we don't actually change
6600                  * the current state.
6601                  */
6602                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
6603                 val |= FORCE_DDR_FREQ_REQ_ACK;
6604                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
6605
6606                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
6607                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
6608                         drm_dbg_kms(&dev_priv->drm,
6609                                     "Punit not acking DDR DVFS request, "
6610                                     "assuming DDR DVFS is disabled\n");
6611                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
6612                 } else {
6613                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
6614                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
6615                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
6616                 }
6617
6618                 vlv_punit_put(dev_priv);
6619         }
6620
6621         for_each_intel_crtc(&dev_priv->drm, crtc) {
6622                 struct intel_crtc_state *crtc_state =
6623                         to_intel_crtc_state(crtc->base.state);
6624                 struct vlv_wm_state *active = &crtc->wm.active.vlv;
6625                 const struct vlv_fifo_state *fifo_state =
6626                         &crtc_state->wm.vlv.fifo_state;
6627                 enum pipe pipe = crtc->pipe;
6628                 enum plane_id plane_id;
6629                 int level;
6630
6631                 vlv_get_fifo_size(crtc_state);
6632
6633                 active->num_levels = wm->level + 1;
6634                 active->cxsr = wm->cxsr;
6635
6636                 for (level = 0; level < active->num_levels; level++) {
6637                         struct g4x_pipe_wm *raw =
6638                                 &crtc_state->wm.vlv.raw[level];
6639
6640                         active->sr[level].plane = wm->sr.plane;
6641                         active->sr[level].cursor = wm->sr.cursor;
6642
6643                         for_each_plane_id_on_crtc(crtc, plane_id) {
6644                                 active->wm[level].plane[plane_id] =
6645                                         wm->pipe[pipe].plane[plane_id];
6646
6647                                 raw->plane[plane_id] =
6648                                         vlv_invert_wm_value(active->wm[level].plane[plane_id],
6649                                                             fifo_state->plane[plane_id]);
6650                         }
6651                 }
6652
6653                 for_each_plane_id_on_crtc(crtc, plane_id)
6654                         vlv_raw_plane_wm_set(crtc_state, level,
6655                                              plane_id, USHRT_MAX);
6656                 vlv_invalidate_wms(crtc, active, level);
6657
6658                 crtc_state->wm.vlv.optimal = *active;
6659                 crtc_state->wm.vlv.intermediate = *active;
6660
6661                 drm_dbg_kms(&dev_priv->drm,
6662                             "Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
6663                             pipe_name(pipe),
6664                             wm->pipe[pipe].plane[PLANE_PRIMARY],
6665                             wm->pipe[pipe].plane[PLANE_CURSOR],
6666                             wm->pipe[pipe].plane[PLANE_SPRITE0],
6667                             wm->pipe[pipe].plane[PLANE_SPRITE1]);
6668         }
6669
6670         drm_dbg_kms(&dev_priv->drm,
6671                     "Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
6672                     wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
6673 }
6674
6675 void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
6676 {
6677         struct intel_plane *plane;
6678         struct intel_crtc *crtc;
6679
6680         mutex_lock(&dev_priv->wm.wm_mutex);
6681
6682         for_each_intel_plane(&dev_priv->drm, plane) {
6683                 struct intel_crtc *crtc =
6684                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
6685                 struct intel_crtc_state *crtc_state =
6686                         to_intel_crtc_state(crtc->base.state);
6687                 struct intel_plane_state *plane_state =
6688                         to_intel_plane_state(plane->base.state);
6689                 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
6690                 const struct vlv_fifo_state *fifo_state =
6691                         &crtc_state->wm.vlv.fifo_state;
6692                 enum plane_id plane_id = plane->id;
6693                 int level;
6694
6695                 if (plane_state->uapi.visible)
6696                         continue;
6697
6698                 for (level = 0; level < wm_state->num_levels; level++) {
6699                         struct g4x_pipe_wm *raw =
6700                                 &crtc_state->wm.vlv.raw[level];
6701
6702                         raw->plane[plane_id] = 0;
6703
6704                         wm_state->wm[level].plane[plane_id] =
6705                                 vlv_invert_wm_value(raw->plane[plane_id],
6706                                                     fifo_state->plane[plane_id]);
6707                 }
6708         }
6709
6710         for_each_intel_crtc(&dev_priv->drm, crtc) {
6711                 struct intel_crtc_state *crtc_state =
6712                         to_intel_crtc_state(crtc->base.state);
6713
6714                 crtc_state->wm.vlv.intermediate =
6715                         crtc_state->wm.vlv.optimal;
6716                 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
6717         }
6718
6719         vlv_program_watermarks(dev_priv);
6720
6721         mutex_unlock(&dev_priv->wm.wm_mutex);
6722 }
6723
6724 /*
6725  * FIXME should probably kill this and improve
6726  * the real watermark readout/sanitation instead
6727  */
6728 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
6729 {
6730         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6731         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6732         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6733
6734         /*
6735          * Don't touch WM1S_LP_EN here.
6736          * Doing so could cause underruns.
6737          */
6738 }
6739
6740 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
6741 {
6742         struct ilk_wm_values *hw = &dev_priv->wm.hw;
6743         struct intel_crtc *crtc;
6744
6745         ilk_init_lp_watermarks(dev_priv);
6746
6747         for_each_intel_crtc(&dev_priv->drm, crtc)
6748                 ilk_pipe_wm_get_hw_state(crtc);
6749
6750         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
6751         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
6752         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
6753
6754         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
6755         if (INTEL_GEN(dev_priv) >= 7) {
6756                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
6757                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
6758         }
6759
6760         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6761                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
6762                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
6763         else if (IS_IVYBRIDGE(dev_priv))
6764                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
6765                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
6766
6767         hw->enable_fbc_wm =
6768                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
6769 }
6770
6771 /**
6772  * intel_update_watermarks - update FIFO watermark values based on current modes
6773  * @crtc: the #intel_crtc on which to compute the WM
6774  *
6775  * Calculate watermark values for the various WM regs based on current mode
6776  * and plane configuration.
6777  *
6778  * There are several cases to deal with here:
6779  *   - normal (i.e. non-self-refresh)
6780  *   - self-refresh (SR) mode
6781  *   - lines are large relative to FIFO size (buffer can hold up to 2)
6782  *   - lines are small relative to FIFO size (buffer can hold more than 2
6783  *     lines), so need to account for TLB latency
6784  *
6785  *   The normal calculation is:
6786  *     watermark = dotclock * bytes per pixel * latency
6787  *   where latency is platform & configuration dependent (we assume pessimal
6788  *   values here).
6789  *
6790  *   The SR calculation is:
6791  *     watermark = (trunc(latency/line time)+1) * surface width *
6792  *       bytes per pixel
6793  *   where
6794  *     line time = htotal / dotclock
6795  *     surface width = hdisplay for normal plane and 64 for cursor
6796  *   and latency is assumed to be high, as above.
6797  *
6798  * The final value programmed to the register should always be rounded up,
6799  * and include an extra 2 entries to account for clock crossings.
6800  *
6801  * We don't use the sprite, so we can ignore that.  And on Crestline we have
6802  * to set the non-SR watermarks to 8.
6803  */
6804 void intel_update_watermarks(struct intel_crtc *crtc)
6805 {
6806         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6807
6808         if (dev_priv->display.update_wm)
6809                 dev_priv->display.update_wm(crtc);
6810 }
6811
6812 void intel_enable_ipc(struct drm_i915_private *dev_priv)
6813 {
6814         u32 val;
6815
6816         if (!HAS_IPC(dev_priv))
6817                 return;
6818
6819         val = I915_READ(DISP_ARB_CTL2);
6820
6821         if (dev_priv->ipc_enabled)
6822                 val |= DISP_IPC_ENABLE;
6823         else
6824                 val &= ~DISP_IPC_ENABLE;
6825
6826         I915_WRITE(DISP_ARB_CTL2, val);
6827 }
6828
6829 static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv)
6830 {
6831         /* Display WA #0477 WaDisableIPC: skl */
6832         if (IS_SKYLAKE(dev_priv))
6833                 return false;
6834
6835         /* Display WA #1141: SKL:all KBL:all CFL */
6836         if (IS_KABYLAKE(dev_priv) ||
6837             IS_COFFEELAKE(dev_priv) ||
6838             IS_COMETLAKE(dev_priv))
6839                 return dev_priv->dram_info.symmetric_memory;
6840
6841         return true;
6842 }
6843
6844 void intel_init_ipc(struct drm_i915_private *dev_priv)
6845 {
6846         if (!HAS_IPC(dev_priv))
6847                 return;
6848
6849         dev_priv->ipc_enabled = intel_can_enable_ipc(dev_priv);
6850
6851         intel_enable_ipc(dev_priv);
6852 }
6853
6854 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
6855 {
6856         /*
6857          * On Ibex Peak and Cougar Point, we need to disable clock
6858          * gating for the panel power sequencer or it will fail to
6859          * start up when no ports are active.
6860          */
6861         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6862 }
6863
6864 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
6865 {
6866         enum pipe pipe;
6867
6868         for_each_pipe(dev_priv, pipe) {
6869                 I915_WRITE(DSPCNTR(pipe),
6870                            I915_READ(DSPCNTR(pipe)) |
6871                            DISPPLANE_TRICKLE_FEED_DISABLE);
6872
6873                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6874                 POSTING_READ(DSPSURF(pipe));
6875         }
6876 }
6877
6878 static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
6879 {
6880         u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6881
6882         /*
6883          * Required for FBC
6884          * WaFbcDisableDpfcClockGating:ilk
6885          */
6886         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6887                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6888                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6889
6890         I915_WRITE(PCH_3DCGDIS0,
6891                    MARIUNIT_CLOCK_GATE_DISABLE |
6892                    SVSMUNIT_CLOCK_GATE_DISABLE);
6893         I915_WRITE(PCH_3DCGDIS1,
6894                    VFMUNIT_CLOCK_GATE_DISABLE);
6895
6896         /*
6897          * According to the spec the following bits should be set in
6898          * order to enable memory self-refresh
6899          * The bit 22/21 of 0x42004
6900          * The bit 5 of 0x42020
6901          * The bit 15 of 0x45000
6902          */
6903         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6904                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6905                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6906         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6907         I915_WRITE(DISP_ARB_CTL,
6908                    (I915_READ(DISP_ARB_CTL) |
6909                     DISP_FBC_WM_DIS));
6910
6911         /*
6912          * Based on the document from hardware guys the following bits
6913          * should be set unconditionally in order to enable FBC.
6914          * The bit 22 of 0x42000
6915          * The bit 22 of 0x42004
6916          * The bit 7,8,9 of 0x42020.
6917          */
6918         if (IS_IRONLAKE_M(dev_priv)) {
6919                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6920                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6921                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6922                            ILK_FBCQ_DIS);
6923                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6924                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6925                            ILK_DPARB_GATE);
6926         }
6927
6928         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6929
6930         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6931                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6932                    ILK_ELPIN_409_SELECT);
6933
6934         g4x_disable_trickle_feed(dev_priv);
6935
6936         ibx_init_clock_gating(dev_priv);
6937 }
6938
6939 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
6940 {
6941         enum pipe pipe;
6942         u32 val;
6943
6944         /*
6945          * On Ibex Peak and Cougar Point, we need to disable clock
6946          * gating for the panel power sequencer or it will fail to
6947          * start up when no ports are active.
6948          */
6949         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6950                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6951                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6952         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6953                    DPLS_EDP_PPS_FIX_DIS);
6954         /* The below fixes the weird display corruption, a few pixels shifted
6955          * downward, on (only) LVDS of some HP laptops with IVY.
6956          */
6957         for_each_pipe(dev_priv, pipe) {
6958                 val = I915_READ(TRANS_CHICKEN2(pipe));
6959                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6960                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6961                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6962                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6963                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6964                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6965                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6966         }
6967         /* WADP0ClockGatingDisable */
6968         for_each_pipe(dev_priv, pipe) {
6969                 I915_WRITE(TRANS_CHICKEN1(pipe),
6970                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6971         }
6972 }
6973
6974 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
6975 {
6976         u32 tmp;
6977
6978         tmp = I915_READ(MCH_SSKPD);
6979         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6980                 drm_dbg_kms(&dev_priv->drm,
6981                             "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6982                             tmp);
6983 }
6984
6985 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
6986 {
6987         u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6988
6989         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6990
6991         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6992                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6993                    ILK_ELPIN_409_SELECT);
6994
6995         I915_WRITE(GEN6_UCGCTL1,
6996                    I915_READ(GEN6_UCGCTL1) |
6997                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6998                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6999
7000         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7001          * gating disable must be set.  Failure to set it results in
7002          * flickering pixels due to Z write ordering failures after
7003          * some amount of runtime in the Mesa "fire" demo, and Unigine
7004          * Sanctuary and Tropics, and apparently anything else with
7005          * alpha test or pixel discard.
7006          *
7007          * According to the spec, bit 11 (RCCUNIT) must also be set,
7008          * but we didn't debug actual testcases to find it out.
7009          *
7010          * WaDisableRCCUnitClockGating:snb
7011          * WaDisableRCPBUnitClockGating:snb
7012          */
7013         I915_WRITE(GEN6_UCGCTL2,
7014                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7015                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7016
7017         /*
7018          * According to the spec the following bits should be
7019          * set in order to enable memory self-refresh and fbc:
7020          * The bit21 and bit22 of 0x42000
7021          * The bit21 and bit22 of 0x42004
7022          * The bit5 and bit7 of 0x42020
7023          * The bit14 of 0x70180
7024          * The bit14 of 0x71180
7025          *
7026          * WaFbcAsynchFlipDisableFbcQueue:snb
7027          */
7028         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7029                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7030                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7031         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7032                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7033                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7034         I915_WRITE(ILK_DSPCLK_GATE_D,
7035                    I915_READ(ILK_DSPCLK_GATE_D) |
7036                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7037                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7038
7039         g4x_disable_trickle_feed(dev_priv);
7040
7041         cpt_init_clock_gating(dev_priv);
7042
7043         gen6_check_mch_setup(dev_priv);
7044 }
7045
7046 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
7047 {
7048         /*
7049          * TODO: this bit should only be enabled when really needed, then
7050          * disabled when not needed anymore in order to save power.
7051          */
7052         if (HAS_PCH_LPT_LP(dev_priv))
7053                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7054                            I915_READ(SOUTH_DSPCLK_GATE_D) |
7055                            PCH_LP_PARTITION_LEVEL_DISABLE);
7056
7057         /* WADPOClockGatingDisable:hsw */
7058         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7059                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7060                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7061 }
7062
7063 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7064 {
7065         if (HAS_PCH_LPT_LP(dev_priv)) {
7066                 u32 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7067
7068                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7069                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7070         }
7071 }
7072
7073 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7074                                    int general_prio_credits,
7075                                    int high_prio_credits)
7076 {
7077         u32 misccpctl;
7078         u32 val;
7079
7080         /* WaTempDisableDOPClkGating:bdw */
7081         misccpctl = I915_READ(GEN7_MISCCPCTL);
7082         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7083
7084         val = I915_READ(GEN8_L3SQCREG1);
7085         val &= ~L3_PRIO_CREDITS_MASK;
7086         val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
7087         val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
7088         I915_WRITE(GEN8_L3SQCREG1, val);
7089
7090         /*
7091          * Wait at least 100 clocks before re-enabling clock gating.
7092          * See the definition of L3SQCREG1 in BSpec.
7093          */
7094         POSTING_READ(GEN8_L3SQCREG1);
7095         udelay(1);
7096         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7097 }
7098
7099 static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
7100 {
7101         /* Wa_1409120013:icl,ehl */
7102         I915_WRITE(ILK_DPFC_CHICKEN,
7103                    ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
7104
7105         /* This is not an Wa. Enable to reduce Sampler power */
7106         I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
7107                    I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
7108
7109         /*Wa_14010594013:icl, ehl */
7110         intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
7111                          0, CNL_DELAY_PMRSP);
7112 }
7113
7114 static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
7115 {
7116         u32 vd_pg_enable = 0;
7117         unsigned int i;
7118
7119         /* Wa_1409120013:tgl */
7120         I915_WRITE(ILK_DPFC_CHICKEN,
7121                    ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
7122
7123         /* This is not a WA. Enable VD HCP & MFX_ENC powergate */
7124         for (i = 0; i < I915_MAX_VCS; i++) {
7125                 if (HAS_ENGINE(&dev_priv->gt, _VCS(i)))
7126                         vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |
7127                                         VDN_MFX_POWERGATE_ENABLE(i);
7128         }
7129
7130         I915_WRITE(POWERGATE_ENABLE,
7131                    I915_READ(POWERGATE_ENABLE) | vd_pg_enable);
7132
7133         /* Wa_1409825376:tgl (pre-prod)*/
7134         if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
7135                 I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
7136                            TGL_VRH_GATING_DIS);
7137
7138         /* Wa_14011059788:tgl */
7139         intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
7140                          0, DFR_DISABLE);
7141 }
7142
7143 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
7144 {
7145         if (!HAS_PCH_CNP(dev_priv))
7146                 return;
7147
7148         /* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
7149         I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
7150                    CNP_PWM_CGE_GATING_DISABLE);
7151 }
7152
7153 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
7154 {
7155         u32 val;
7156         cnp_init_clock_gating(dev_priv);
7157
7158         /* This is not an Wa. Enable for better image quality */
7159         I915_WRITE(_3D_CHICKEN3,
7160                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
7161
7162         /* WaEnableChickenDCPR:cnl */
7163         I915_WRITE(GEN8_CHICKEN_DCPR_1,
7164                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
7165
7166         /* WaFbcWakeMemOn:cnl */
7167         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
7168                    DISP_FBC_MEMORY_WAKE);
7169
7170         val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE);
7171         /* ReadHitWriteOnlyDisable:cnl */
7172         val |= RCCUNIT_CLKGATE_DIS;
7173         I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
7174
7175         /* Wa_2201832410:cnl */
7176         val = I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE);
7177         val |= GWUNIT_CLKGATE_DIS;
7178         I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE, val);
7179
7180         /* WaDisableVFclkgate:cnl */
7181         /* WaVFUnitClockGatingDisable:cnl */
7182         val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
7183         val |= VFUNIT_CLKGATE_DIS;
7184         I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val);
7185 }
7186
7187 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
7188 {
7189         cnp_init_clock_gating(dev_priv);
7190         gen9_init_clock_gating(dev_priv);
7191
7192         /* WaFbcNukeOnHostModify:cfl */
7193         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7194                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7195 }
7196
7197 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
7198 {
7199         gen9_init_clock_gating(dev_priv);
7200
7201         /* WaDisableSDEUnitClockGating:kbl */
7202         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7203                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7204                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7205
7206         /* WaDisableGamClockGating:kbl */
7207         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7208                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7209                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7210
7211         /* WaFbcNukeOnHostModify:kbl */
7212         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7213                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7214 }
7215
7216 static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
7217 {
7218         gen9_init_clock_gating(dev_priv);
7219
7220         /* WAC6entrylatency:skl */
7221         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7222                    FBC_LLC_FULLY_OPEN);
7223
7224         /* WaFbcNukeOnHostModify:skl */
7225         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7226                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7227 }
7228
7229 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
7230 {
7231         enum pipe pipe;
7232
7233         /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
7234         I915_WRITE(CHICKEN_PIPESL_1(PIPE_A),
7235                    I915_READ(CHICKEN_PIPESL_1(PIPE_A)) |
7236                    HSW_FBCQ_DIS);
7237
7238         /* WaSwitchSolVfFArbitrationPriority:bdw */
7239         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7240
7241         /* WaPsrDPAMaskVBlankInSRD:bdw */
7242         I915_WRITE(CHICKEN_PAR1_1,
7243                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7244
7245         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7246         for_each_pipe(dev_priv, pipe) {
7247                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7248                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
7249                            BDW_DPRS_MASK_VBLANK_SRD);
7250         }
7251
7252         /* WaVSRefCountFullforceMissDisable:bdw */
7253         /* WaDSRefCountFullforceMissDisable:bdw */
7254         I915_WRITE(GEN7_FF_THREAD_MODE,
7255                    I915_READ(GEN7_FF_THREAD_MODE) &
7256                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7257
7258         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7259                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7260
7261         /* WaDisableSDEUnitClockGating:bdw */
7262         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7263                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7264
7265         /* WaProgramL3SqcReg1Default:bdw */
7266         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7267
7268         /* WaKVMNotificationOnConfigChange:bdw */
7269         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7270                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7271
7272         lpt_init_clock_gating(dev_priv);
7273
7274         /* WaDisableDopClockGating:bdw
7275          *
7276          * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
7277          * clock gating.
7278          */
7279         I915_WRITE(GEN6_UCGCTL1,
7280                    I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
7281 }
7282
7283 static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
7284 {
7285         /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
7286         I915_WRITE(CHICKEN_PIPESL_1(PIPE_A),
7287                    I915_READ(CHICKEN_PIPESL_1(PIPE_A)) |
7288                    HSW_FBCQ_DIS);
7289
7290         /* This is required by WaCatErrorRejectionIssue:hsw */
7291         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7292                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7293                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7294
7295         /* WaSwitchSolVfFArbitrationPriority:hsw */
7296         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7297
7298         lpt_init_clock_gating(dev_priv);
7299 }
7300
7301 static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
7302 {
7303         u32 snpcr;
7304
7305         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7306
7307         /* WaFbcAsynchFlipDisableFbcQueue:ivb */
7308         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7309                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7310                    ILK_FBCQ_DIS);
7311
7312         /* WaDisableBackToBackFlipFix:ivb */
7313         I915_WRITE(IVB_CHICKEN3,
7314                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7315                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7316
7317         if (IS_IVB_GT1(dev_priv))
7318                 I915_WRITE(GEN7_ROW_CHICKEN2,
7319                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7320         else {
7321                 /* must write both registers */
7322                 I915_WRITE(GEN7_ROW_CHICKEN2,
7323                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7324                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7325                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7326         }
7327
7328         /*
7329          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7330          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7331          */
7332         I915_WRITE(GEN6_UCGCTL2,
7333                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7334
7335         /* This is required by WaCatErrorRejectionIssue:ivb */
7336         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7337                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7338                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7339
7340         g4x_disable_trickle_feed(dev_priv);
7341
7342         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7343         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7344         snpcr |= GEN6_MBC_SNPCR_MED;
7345         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7346
7347         if (!HAS_PCH_NOP(dev_priv))
7348                 cpt_init_clock_gating(dev_priv);
7349
7350         gen6_check_mch_setup(dev_priv);
7351 }
7352
7353 static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
7354 {
7355         /* WaDisableBackToBackFlipFix:vlv */
7356         I915_WRITE(IVB_CHICKEN3,
7357                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7358                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7359
7360         /* WaDisableDopClockGating:vlv */
7361         I915_WRITE(GEN7_ROW_CHICKEN2,
7362                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7363
7364         /* This is required by WaCatErrorRejectionIssue:vlv */
7365         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7366                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7367                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7368
7369         /*
7370          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7371          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7372          */
7373         I915_WRITE(GEN6_UCGCTL2,
7374                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7375
7376         /* WaDisableL3Bank2xClockGate:vlv
7377          * Disabling L3 clock gating- MMIO 940c[25] = 1
7378          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7379         I915_WRITE(GEN7_UCGCTL4,
7380                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7381
7382         /*
7383          * WaDisableVLVClockGating_VBIIssue:vlv
7384          * Disable clock gating on th GCFG unit to prevent a delay
7385          * in the reporting of vblank events.
7386          */
7387         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7388 }
7389
7390 static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
7391 {
7392         /* WaVSRefCountFullforceMissDisable:chv */
7393         /* WaDSRefCountFullforceMissDisable:chv */
7394         I915_WRITE(GEN7_FF_THREAD_MODE,
7395                    I915_READ(GEN7_FF_THREAD_MODE) &
7396                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7397
7398         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7399         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7400                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7401
7402         /* WaDisableCSUnitClockGating:chv */
7403         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7404                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7405
7406         /* WaDisableSDEUnitClockGating:chv */
7407         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7408                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7409
7410         /*
7411          * WaProgramL3SqcReg1Default:chv
7412          * See gfxspecs/Related Documents/Performance Guide/
7413          * LSQC Setting Recommendations.
7414          */
7415         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7416 }
7417
7418 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
7419 {
7420         u32 dspclk_gate;
7421
7422         I915_WRITE(RENCLK_GATE_D1, 0);
7423         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7424                    GS_UNIT_CLOCK_GATE_DISABLE |
7425                    CL_UNIT_CLOCK_GATE_DISABLE);
7426         I915_WRITE(RAMCLK_GATE_D, 0);
7427         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7428                 OVRUNIT_CLOCK_GATE_DISABLE |
7429                 OVCUNIT_CLOCK_GATE_DISABLE;
7430         if (IS_GM45(dev_priv))
7431                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7432         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7433
7434         g4x_disable_trickle_feed(dev_priv);
7435 }
7436
7437 static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
7438 {
7439         struct intel_uncore *uncore = &dev_priv->uncore;
7440
7441         intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7442         intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
7443         intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
7444         intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
7445         intel_uncore_write16(uncore, DEUC, 0);
7446         intel_uncore_write(uncore,
7447                            MI_ARB_STATE,
7448                            _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7449 }
7450
7451 static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
7452 {
7453         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7454                    I965_RCC_CLOCK_GATE_DISABLE |
7455                    I965_RCPB_CLOCK_GATE_DISABLE |
7456                    I965_ISC_CLOCK_GATE_DISABLE |
7457                    I965_FBC_CLOCK_GATE_DISABLE);
7458         I915_WRITE(RENCLK_GATE_D2, 0);
7459         I915_WRITE(MI_ARB_STATE,
7460                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7461 }
7462
7463 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
7464 {
7465         u32 dstate = I915_READ(D_STATE);
7466
7467         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7468                 DSTATE_DOT_CLOCK_GATING;
7469         I915_WRITE(D_STATE, dstate);
7470
7471         if (IS_PINEVIEW(dev_priv))
7472                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7473
7474         /* IIR "flip pending" means done if this bit is set */
7475         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7476
7477         /* interrupts should cause a wake up from C3 */
7478         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7479
7480         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7481         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7482
7483         I915_WRITE(MI_ARB_STATE,
7484                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7485 }
7486
7487 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
7488 {
7489         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7490
7491         /* interrupts should cause a wake up from C3 */
7492         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7493                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7494
7495         I915_WRITE(MEM_MODE,
7496                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7497
7498         /*
7499          * Have FBC ignore 3D activity since we use software
7500          * render tracking, and otherwise a pure 3D workload
7501          * (even if it just renders a single frame and then does
7502          * abosultely nothing) would not allow FBC to recompress
7503          * until a 2D blit occurs.
7504          */
7505         I915_WRITE(SCPD0,
7506                    _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
7507 }
7508
7509 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
7510 {
7511         I915_WRITE(MEM_MODE,
7512                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7513                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7514 }
7515
7516 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
7517 {
7518         dev_priv->display.init_clock_gating(dev_priv);
7519 }
7520
7521 void intel_suspend_hw(struct drm_i915_private *dev_priv)
7522 {
7523         if (HAS_PCH_LPT(dev_priv))
7524                 lpt_suspend_hw(dev_priv);
7525 }
7526
7527 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
7528 {
7529         drm_dbg_kms(&dev_priv->drm,
7530                     "No clock gating settings or workarounds applied.\n");
7531 }
7532
7533 /**
7534  * intel_init_clock_gating_hooks - setup the clock gating hooks
7535  * @dev_priv: device private
7536  *
7537  * Setup the hooks that configure which clocks of a given platform can be
7538  * gated and also apply various GT and display specific workarounds for these
7539  * platforms. Note that some GT specific workarounds are applied separately
7540  * when GPU contexts or batchbuffers start their execution.
7541  */
7542 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7543 {
7544         if (IS_GEN(dev_priv, 12))
7545                 dev_priv->display.init_clock_gating = tgl_init_clock_gating;
7546         else if (IS_GEN(dev_priv, 11))
7547                 dev_priv->display.init_clock_gating = icl_init_clock_gating;
7548         else if (IS_CANNONLAKE(dev_priv))
7549                 dev_priv->display.init_clock_gating = cnl_init_clock_gating;
7550         else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
7551                 dev_priv->display.init_clock_gating = cfl_init_clock_gating;
7552         else if (IS_SKYLAKE(dev_priv))
7553                 dev_priv->display.init_clock_gating = skl_init_clock_gating;
7554         else if (IS_KABYLAKE(dev_priv))
7555                 dev_priv->display.init_clock_gating = kbl_init_clock_gating;
7556         else if (IS_BROXTON(dev_priv))
7557                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7558         else if (IS_GEMINILAKE(dev_priv))
7559                 dev_priv->display.init_clock_gating = glk_init_clock_gating;
7560         else if (IS_BROADWELL(dev_priv))
7561                 dev_priv->display.init_clock_gating = bdw_init_clock_gating;
7562         else if (IS_CHERRYVIEW(dev_priv))
7563                 dev_priv->display.init_clock_gating = chv_init_clock_gating;
7564         else if (IS_HASWELL(dev_priv))
7565                 dev_priv->display.init_clock_gating = hsw_init_clock_gating;
7566         else if (IS_IVYBRIDGE(dev_priv))
7567                 dev_priv->display.init_clock_gating = ivb_init_clock_gating;
7568         else if (IS_VALLEYVIEW(dev_priv))
7569                 dev_priv->display.init_clock_gating = vlv_init_clock_gating;
7570         else if (IS_GEN(dev_priv, 6))
7571                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7572         else if (IS_GEN(dev_priv, 5))
7573                 dev_priv->display.init_clock_gating = ilk_init_clock_gating;
7574         else if (IS_G4X(dev_priv))
7575                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7576         else if (IS_I965GM(dev_priv))
7577                 dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
7578         else if (IS_I965G(dev_priv))
7579                 dev_priv->display.init_clock_gating = i965g_init_clock_gating;
7580         else if (IS_GEN(dev_priv, 3))
7581                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7582         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7583                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7584         else if (IS_GEN(dev_priv, 2))
7585                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7586         else {
7587                 MISSING_CASE(INTEL_DEVID(dev_priv));
7588                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7589         }
7590 }
7591
7592 /* Set up chip specific power management-related functions */
7593 void intel_init_pm(struct drm_i915_private *dev_priv)
7594 {
7595         /* For cxsr */
7596         if (IS_PINEVIEW(dev_priv))
7597                 pnv_get_mem_freq(dev_priv);
7598         else if (IS_GEN(dev_priv, 5))
7599                 ilk_get_mem_freq(dev_priv);
7600
7601         if (intel_has_sagv(dev_priv))
7602                 skl_setup_sagv_block_time(dev_priv);
7603
7604         /* For FIFO watermark updates */
7605         if (INTEL_GEN(dev_priv) >= 9) {
7606                 skl_setup_wm_latency(dev_priv);
7607                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7608         } else if (HAS_PCH_SPLIT(dev_priv)) {
7609                 ilk_setup_wm_latency(dev_priv);
7610
7611                 if ((IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] &&
7612                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7613                     (!IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] &&
7614                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7615                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7616                         dev_priv->display.compute_intermediate_wm =
7617                                 ilk_compute_intermediate_wm;
7618                         dev_priv->display.initial_watermarks =
7619                                 ilk_initial_watermarks;
7620                         dev_priv->display.optimize_watermarks =
7621                                 ilk_optimize_watermarks;
7622                 } else {
7623                         drm_dbg_kms(&dev_priv->drm,
7624                                     "Failed to read display plane latency. "
7625                                     "Disable CxSR\n");
7626                 }
7627         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7628                 vlv_setup_wm_latency(dev_priv);
7629                 dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
7630                 dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
7631                 dev_priv->display.initial_watermarks = vlv_initial_watermarks;
7632                 dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
7633                 dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
7634         } else if (IS_G4X(dev_priv)) {
7635                 g4x_setup_wm_latency(dev_priv);
7636                 dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
7637                 dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
7638                 dev_priv->display.initial_watermarks = g4x_initial_watermarks;
7639                 dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
7640         } else if (IS_PINEVIEW(dev_priv)) {
7641                 if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
7642                                             dev_priv->is_ddr3,
7643                                             dev_priv->fsb_freq,
7644                                             dev_priv->mem_freq)) {
7645                         drm_info(&dev_priv->drm,
7646                                  "failed to find known CxSR latency "
7647                                  "(found ddr%s fsb freq %d, mem freq %d), "
7648                                  "disabling CxSR\n",
7649                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7650                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7651                         /* Disable CxSR and never update its watermark again */
7652                         intel_set_memory_cxsr(dev_priv, false);
7653                         dev_priv->display.update_wm = NULL;
7654                 } else
7655                         dev_priv->display.update_wm = pnv_update_wm;
7656         } else if (IS_GEN(dev_priv, 4)) {
7657                 dev_priv->display.update_wm = i965_update_wm;
7658         } else if (IS_GEN(dev_priv, 3)) {
7659                 dev_priv->display.update_wm = i9xx_update_wm;
7660                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7661         } else if (IS_GEN(dev_priv, 2)) {
7662                 if (INTEL_NUM_PIPES(dev_priv) == 1) {
7663                         dev_priv->display.update_wm = i845_update_wm;
7664                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7665                 } else {
7666                         dev_priv->display.update_wm = i9xx_update_wm;
7667                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7668                 }
7669         } else {
7670                 drm_err(&dev_priv->drm,
7671                         "unexpected fall-through in %s\n", __func__);
7672         }
7673 }
7674
7675 void intel_pm_setup(struct drm_i915_private *dev_priv)
7676 {
7677         dev_priv->runtime_pm.suspended = false;
7678         atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
7679 }
7680
7681 static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj)
7682 {
7683         struct intel_dbuf_state *dbuf_state;
7684
7685         dbuf_state = kmemdup(obj->state, sizeof(*dbuf_state), GFP_KERNEL);
7686         if (!dbuf_state)
7687                 return NULL;
7688
7689         return &dbuf_state->base;
7690 }
7691
7692 static void intel_dbuf_destroy_state(struct intel_global_obj *obj,
7693                                      struct intel_global_state *state)
7694 {
7695         kfree(state);
7696 }
7697
7698 static const struct intel_global_state_funcs intel_dbuf_funcs = {
7699         .atomic_duplicate_state = intel_dbuf_duplicate_state,
7700         .atomic_destroy_state = intel_dbuf_destroy_state,
7701 };
7702
7703 struct intel_dbuf_state *
7704 intel_atomic_get_dbuf_state(struct intel_atomic_state *state)
7705 {
7706         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7707         struct intel_global_state *dbuf_state;
7708
7709         dbuf_state = intel_atomic_get_global_obj_state(state, &dev_priv->dbuf.obj);
7710         if (IS_ERR(dbuf_state))
7711                 return ERR_CAST(dbuf_state);
7712
7713         return to_intel_dbuf_state(dbuf_state);
7714 }
7715
7716 int intel_dbuf_init(struct drm_i915_private *dev_priv)
7717 {
7718         struct intel_dbuf_state *dbuf_state;
7719
7720         dbuf_state = kzalloc(sizeof(*dbuf_state), GFP_KERNEL);
7721         if (!dbuf_state)
7722                 return -ENOMEM;
7723
7724         intel_atomic_global_obj_init(dev_priv, &dev_priv->dbuf.obj,
7725                                      &dbuf_state->base, &intel_dbuf_funcs);
7726
7727         return 0;
7728 }
7729
7730 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
7731 {
7732         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7733         const struct intel_dbuf_state *new_dbuf_state =
7734                 intel_atomic_get_new_dbuf_state(state);
7735         const struct intel_dbuf_state *old_dbuf_state =
7736                 intel_atomic_get_old_dbuf_state(state);
7737
7738         if (!new_dbuf_state ||
7739             new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
7740                 return;
7741
7742         WARN_ON(!new_dbuf_state->base.changed);
7743
7744         gen9_dbuf_slices_update(dev_priv,
7745                                 old_dbuf_state->enabled_slices |
7746                                 new_dbuf_state->enabled_slices);
7747 }
7748
7749 void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
7750 {
7751         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
7752         const struct intel_dbuf_state *new_dbuf_state =
7753                 intel_atomic_get_new_dbuf_state(state);
7754         const struct intel_dbuf_state *old_dbuf_state =
7755                 intel_atomic_get_old_dbuf_state(state);
7756
7757         if (!new_dbuf_state ||
7758             new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
7759                 return;
7760
7761         WARN_ON(!new_dbuf_state->base.changed);
7762
7763         gen9_dbuf_slices_update(dev_priv,
7764                                 new_dbuf_state->enabled_slices);
7765 }