drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34 #include <drm/drm_atomic_helper.h>
  35
  36 /**
  37  * DOC: RC6
  38  *
  39  * RC6 is a special power stage which allows the GPU to enter an very
  40  * low-voltage mode when idle, using down to 0V while at this stage.  This
  41  * stage is entered automatically when the GPU is idle when RC6 support is
  42  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  43  *
  44  * There are different RC6 modes available in Intel GPU, which differentiate
  45  * among each other with the latency required to enter and leave RC6 and
  46  * voltage consumed by the GPU in different states.
  47  *
  48  * The combination of the following flags define which states GPU is allowed
  49  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  50  * RC6pp is deepest RC6. Their support by hardware varies according to the
  51  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  52  * which brings the most power savings; deeper states save more power, but
  53  * require higher latency to switch to and wake up.
  54  */
  55 #define INTEL_RC6_ENABLE                        (1<<0)
  56 #define INTEL_RC6p_ENABLE                       (1<<1)
  57 #define INTEL_RC6pp_ENABLE                      (1<<2)
  58
  59 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
  60 {
  61         if (HAS_LLC(dev_priv)) {
  62                 /*
  63                  * WaCompressedResourceDisplayNewHashMode:skl,kbl
  64                  * Display WA#0390: skl,kbl
  65                  *
  66                  * Must match Sampler, Pixel Back End, and Media. See
  67                  * WaCompressedResourceSamplerPbeMediaNewHashMode.
  68                  */
  69                 I915_WRITE(CHICKEN_PAR1_1,
  70                            I915_READ(CHICKEN_PAR1_1) |
  71                            SKL_DE_COMPRESSED_HASH_MODE);
  72         }
  73
  74         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
  75         I915_WRITE(CHICKEN_PAR1_1,
  76                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  77
  78         I915_WRITE(GEN8_CONFIG0,
  79                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  80
  81         /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
  82         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  83                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  84
  85         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
  86         /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
  87         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  88                    DISP_FBC_WM_DIS |
  89                    DISP_FBC_MEMORY_WAKE);
  90
  91         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
  92         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  93                    ILK_DPFC_DISABLE_DUMMY0);
  94
  95         if (IS_SKYLAKE(dev_priv)) {
  96                 /* WaDisableDopClockGating */
  97                 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
  98                            & ~GEN7_DOP_CLOCK_GATE_ENABLE);
  99         }
 100 }
 101
 102 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
 103 {
 104         gen9_init_clock_gating(dev_priv);
 105
 106         /* WaDisableSDEUnitClockGating:bxt */
 107         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 108                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 109
 110         /*
 111          * FIXME:
 112          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 113          */
 114         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 115                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 116
 117         /*
 118          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 119          * to stay fully on.
 120          */
 121         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 122                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 123 }
 124
 125 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
 126 {
 127         u32 val;
 128         gen9_init_clock_gating(dev_priv);
 129
 130         /*
 131          * WaDisablePWMClockGating:glk
 132          * Backlight PWM may stop in the asserted state, causing backlight
 133          * to stay fully on.
 134          */
 135         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 136                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 137
 138         /* WaDDIIOTimeout:glk */
 139         if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) {
 140                 u32 val = I915_READ(CHICKEN_MISC_2);
 141                 val &= ~(GLK_CL0_PWR_DOWN |
 142                          GLK_CL1_PWR_DOWN |
 143                          GLK_CL2_PWR_DOWN);
 144                 I915_WRITE(CHICKEN_MISC_2, val);
 145         }
 146
 147         /* Display WA #1133: WaFbcSkipSegments:glk */
 148         val = I915_READ(ILK_DPFC_CHICKEN);
 149         val &= ~GLK_SKIP_SEG_COUNT_MASK;
 150         val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
 151         I915_WRITE(ILK_DPFC_CHICKEN, val);
 152 }
 153
 154 static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
 155 {
 156         u32 tmp;
 157
 158         tmp = I915_READ(CLKCFG);
 159
 160         switch (tmp & CLKCFG_FSB_MASK) {
 161         case CLKCFG_FSB_533:
 162                 dev_priv->fsb_freq = 533; /* 133*4 */
 163                 break;
 164         case CLKCFG_FSB_800:
 165                 dev_priv->fsb_freq = 800; /* 200*4 */
 166                 break;
 167         case CLKCFG_FSB_667:
 168                 dev_priv->fsb_freq =  667; /* 167*4 */
 169                 break;
 170         case CLKCFG_FSB_400:
 171                 dev_priv->fsb_freq = 400; /* 100*4 */
 172                 break;
 173         }
 174
 175         switch (tmp & CLKCFG_MEM_MASK) {
 176         case CLKCFG_MEM_533:
 177                 dev_priv->mem_freq = 533;
 178                 break;
 179         case CLKCFG_MEM_667:
 180                 dev_priv->mem_freq = 667;
 181                 break;
 182         case CLKCFG_MEM_800:
 183                 dev_priv->mem_freq = 800;
 184                 break;
 185         }
 186
 187         /* detect pineview DDR3 setting */
 188         tmp = I915_READ(CSHRDDR3CTL);
 189         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 190 }
 191
 192 static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
 193 {
 194         u16 ddrpll, csipll;
 195
 196         ddrpll = I915_READ16(DDRMPLL1);
 197         csipll = I915_READ16(CSIPLL0);
 198
 199         switch (ddrpll & 0xff) {
 200         case 0xc:
 201                 dev_priv->mem_freq = 800;
 202                 break;
 203         case 0x10:
 204                 dev_priv->mem_freq = 1066;
 205                 break;
 206         case 0x14:
 207                 dev_priv->mem_freq = 1333;
 208                 break;
 209         case 0x18:
 210                 dev_priv->mem_freq = 1600;
 211                 break;
 212         default:
 213                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 214                                  ddrpll & 0xff);
 215                 dev_priv->mem_freq = 0;
 216                 break;
 217         }
 218
 219         dev_priv->ips.r_t = dev_priv->mem_freq;
 220
 221         switch (csipll & 0x3ff) {
 222         case 0x00c:
 223                 dev_priv->fsb_freq = 3200;
 224                 break;
 225         case 0x00e:
 226                 dev_priv->fsb_freq = 3733;
 227                 break;
 228         case 0x010:
 229                 dev_priv->fsb_freq = 4266;
 230                 break;
 231         case 0x012:
 232                 dev_priv->fsb_freq = 4800;
 233                 break;
 234         case 0x014:
 235                 dev_priv->fsb_freq = 5333;
 236                 break;
 237         case 0x016:
 238                 dev_priv->fsb_freq = 5866;
 239                 break;
 240         case 0x018:
 241                 dev_priv->fsb_freq = 6400;
 242                 break;
 243         default:
 244                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 245                                  csipll & 0x3ff);
 246                 dev_priv->fsb_freq = 0;
 247                 break;
 248         }
 249
 250         if (dev_priv->fsb_freq == 3200) {
 251                 dev_priv->ips.c_m = 0;
 252         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 253                 dev_priv->ips.c_m = 1;
 254         } else {
 255                 dev_priv->ips.c_m = 2;
 256         }
 257 }
 258
 259 static const struct cxsr_latency cxsr_latency_table[] = {
 260         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 261         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 262         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 263         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 264         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 265
 266         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 267         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 268         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 269         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 270         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 271
 272         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 273         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 274         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 275         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 276         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 277
 278         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 279         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 280         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 281         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 282         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 283
 284         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 285         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 286         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 287         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 288         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 289
 290         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 291         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 292         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 293         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 294         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 295 };
 296
 297 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 298                                                          bool is_ddr3,
 299                                                          int fsb,
 300                                                          int mem)
 301 {
 302         const struct cxsr_latency *latency;
 303         int i;
 304
 305         if (fsb == 0 || mem == 0)
 306                 return NULL;
 307
 308         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 309                 latency = &cxsr_latency_table[i];
 310                 if (is_desktop == latency->is_desktop &&
 311                     is_ddr3 == latency->is_ddr3 &&
 312                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 313                         return latency;
 314         }
 315
 316         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 317
 318         return NULL;
 319 }
 320
 321 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 322 {
 323         u32 val;
 324
 325         mutex_lock(&dev_priv->pcu_lock);
 326
 327         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 328         if (enable)
 329                 val &= ~FORCE_DDR_HIGH_FREQ;
 330         else
 331                 val |= FORCE_DDR_HIGH_FREQ;
 332         val &= ~FORCE_DDR_LOW_FREQ;
 333         val |= FORCE_DDR_FREQ_REQ_ACK;
 334         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 335
 336         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 337                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 338                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 339
 340         mutex_unlock(&dev_priv->pcu_lock);
 341 }
 342
 343 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 344 {
 345         u32 val;
 346
 347         mutex_lock(&dev_priv->pcu_lock);
 348
 349         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 350         if (enable)
 351                 val |= DSP_MAXFIFO_PM5_ENABLE;
 352         else
 353                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 354         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 355
 356         mutex_unlock(&dev_priv->pcu_lock);
 357 }
 358
 359 #define FW_WM(value, plane) \
 360         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 361
 362 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 363 {
 364         bool was_enabled;
 365         u32 val;
 366
 367         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 368                 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 369                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 370                 POSTING_READ(FW_BLC_SELF_VLV);
 371         } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
 372                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 373                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 374                 POSTING_READ(FW_BLC_SELF);
 375         } else if (IS_PINEVIEW(dev_priv)) {
 376                 val = I915_READ(DSPFW3);
 377                 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
 378                 if (enable)
 379                         val |= PINEVIEW_SELF_REFRESH_EN;
 380                 else
 381                         val &= ~PINEVIEW_SELF_REFRESH_EN;
 382                 I915_WRITE(DSPFW3, val);
 383                 POSTING_READ(DSPFW3);
 384         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 385                 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
 386                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 387                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 388                 I915_WRITE(FW_BLC_SELF, val);
 389                 POSTING_READ(FW_BLC_SELF);
 390         } else if (IS_I915GM(dev_priv)) {
 391                 /*
 392                  * FIXME can't find a bit like this for 915G, and
 393                  * and yet it does have the related watermark in
 394                  * FW_BLC_SELF. What's going on?
 395                  */
 396                 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
 397                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 398                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 399                 I915_WRITE(INSTPM, val);
 400                 POSTING_READ(INSTPM);
 401         } else {
 402                 return false;
 403         }
 404
 405         trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
 406
 407         DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
 408                       enableddisabled(enable),
 409                       enableddisabled(was_enabled));
 410
 411         return was_enabled;
 412 }
 413
 414 /**
 415  * intel_set_memory_cxsr - Configure CxSR state
 416  * @dev_priv: i915 device
 417  * @enable: Allow vs. disallow CxSR
 418  *
 419  * Allow or disallow the system to enter a special CxSR
 420  * (C-state self refresh) state. What typically happens in CxSR mode
 421  * is that several display FIFOs may get combined into a single larger
 422  * FIFO for a particular plane (so called max FIFO mode) to allow the
 423  * system to defer memory fetches longer, and the memory will enter
 424  * self refresh.
 425  *
 426  * Note that enabling CxSR does not guarantee that the system enter
 427  * this special mode, nor does it guarantee that the system stays
 428  * in that mode once entered. So this just allows/disallows the system
 429  * to autonomously utilize the CxSR mode. Other factors such as core
 430  * C-states will affect when/if the system actually enters/exits the
 431  * CxSR mode.
 432  *
 433  * Note that on VLV/CHV this actually only controls the max FIFO mode,
 434  * and the system is free to enter/exit memory self refresh at any time
 435  * even when the use of CxSR has been disallowed.
 436  *
 437  * While the system is actually in the CxSR/max FIFO mode, some plane
 438  * control registers will not get latched on vblank. Thus in order to
 439  * guarantee the system will respond to changes in the plane registers
 440  * we must always disallow CxSR prior to making changes to those registers.
 441  * Unfortunately the system will re-evaluate the CxSR conditions at
 442  * frame start which happens after vblank start (which is when the plane
 443  * registers would get latched), so we can't proceed with the plane update
 444  * during the same frame where we disallowed CxSR.
 445  *
 446  * Certain platforms also have a deeper HPLL SR mode. Fortunately the
 447  * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
 448  * the hardware w.r.t. HPLL SR when writing to plane registers.
 449  * Disallowing just CxSR is sufficient.
 450  */
 451 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 452 {
 453         bool ret;
 454
 455         mutex_lock(&dev_priv->wm.wm_mutex);
 456         ret = _intel_set_memory_cxsr(dev_priv, enable);
 457         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 458                 dev_priv->wm.vlv.cxsr = enable;
 459         else if (IS_G4X(dev_priv))
 460                 dev_priv->wm.g4x.cxsr = enable;
 461         mutex_unlock(&dev_priv->wm.wm_mutex);
 462
 463         return ret;
 464 }
 465
 466 /*
 467  * Latency for FIFO fetches is dependent on several factors:
 468  *   - memory configuration (speed, channels)
 469  *   - chipset
 470  *   - current MCH state
 471  * It can be fairly high in some situations, so here we assume a fairly
 472  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 473  * set this value too high, the FIFO will fetch frequently to stay full)
 474  * and power consumption (set it too low to save power and we might see
 475  * FIFO underruns and display "flicker").
 476  *
 477  * A value of 5us seems to be a good balance; safe for very low end
 478  * platforms but not overly aggressive on lower latency configs.
 479  */
 480 static const int pessimal_latency_ns = 5000;
 481
 482 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 483         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 484
 485 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 486 {
 487         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 488         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 489         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
 490         enum pipe pipe = crtc->pipe;
 491         int sprite0_start, sprite1_start;
 492
 493         switch (pipe) {
 494                 uint32_t dsparb, dsparb2, dsparb3;
 495         case PIPE_A:
 496                 dsparb = I915_READ(DSPARB);
 497                 dsparb2 = I915_READ(DSPARB2);
 498                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 499                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 500                 break;
 501         case PIPE_B:
 502                 dsparb = I915_READ(DSPARB);
 503                 dsparb2 = I915_READ(DSPARB2);
 504                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 505                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 506                 break;
 507         case PIPE_C:
 508                 dsparb2 = I915_READ(DSPARB2);
 509                 dsparb3 = I915_READ(DSPARB3);
 510                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 511                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 512                 break;
 513         default:
 514                 MISSING_CASE(pipe);
 515                 return;
 516         }
 517
 518         fifo_state->plane[PLANE_PRIMARY] = sprite0_start;
 519         fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start;
 520         fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start;
 521         fifo_state->plane[PLANE_CURSOR] = 63;
 522 }
 523
 524 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 525 {
 526         uint32_t dsparb = I915_READ(DSPARB);
 527         int size;
 528
 529         size = dsparb & 0x7f;
 530         if (plane)
 531                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 532
 533         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 534                       plane ? "B" : "A", size);
 535
 536         return size;
 537 }
 538
 539 static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 540 {
 541         uint32_t dsparb = I915_READ(DSPARB);
 542         int size;
 543
 544         size = dsparb & 0x1ff;
 545         if (plane)
 546                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 547         size >>= 1; /* Convert to cachelines */
 548
 549         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 550                       plane ? "B" : "A", size);
 551
 552         return size;
 553 }
 554
 555 static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
 556 {
 557         uint32_t dsparb = I915_READ(DSPARB);
 558         int size;
 559
 560         size = dsparb & 0x7f;
 561         size >>= 2; /* Convert to cachelines */
 562
 563         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 564                       plane ? "B" : "A",
 565                       size);
 566
 567         return size;
 568 }
 569
 570 /* Pineview has different values for various configs */
 571 static const struct intel_watermark_params pineview_display_wm = {
 572         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 573         .max_wm = PINEVIEW_MAX_WM,
 574         .default_wm = PINEVIEW_DFT_WM,
 575         .guard_size = PINEVIEW_GUARD_WM,
 576         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 577 };
 578 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 579         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 580         .max_wm = PINEVIEW_MAX_WM,
 581         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 582         .guard_size = PINEVIEW_GUARD_WM,
 583         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 584 };
 585 static const struct intel_watermark_params pineview_cursor_wm = {
 586         .fifo_size = PINEVIEW_CURSOR_FIFO,
 587         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 588         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 589         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 590         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 591 };
 592 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 593         .fifo_size = PINEVIEW_CURSOR_FIFO,
 594         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 595         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 596         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 597         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 598 };
 599 static const struct intel_watermark_params i965_cursor_wm_info = {
 600         .fifo_size = I965_CURSOR_FIFO,
 601         .max_wm = I965_CURSOR_MAX_WM,
 602         .default_wm = I965_CURSOR_DFT_WM,
 603         .guard_size = 2,
 604         .cacheline_size = I915_FIFO_LINE_SIZE,
 605 };
 606 static const struct intel_watermark_params i945_wm_info = {
 607         .fifo_size = I945_FIFO_SIZE,
 608         .max_wm = I915_MAX_WM,
 609         .default_wm = 1,
 610         .guard_size = 2,
 611         .cacheline_size = I915_FIFO_LINE_SIZE,
 612 };
 613 static const struct intel_watermark_params i915_wm_info = {
 614         .fifo_size = I915_FIFO_SIZE,
 615         .max_wm = I915_MAX_WM,
 616         .default_wm = 1,
 617         .guard_size = 2,
 618         .cacheline_size = I915_FIFO_LINE_SIZE,
 619 };
 620 static const struct intel_watermark_params i830_a_wm_info = {
 621         .fifo_size = I855GM_FIFO_SIZE,
 622         .max_wm = I915_MAX_WM,
 623         .default_wm = 1,
 624         .guard_size = 2,
 625         .cacheline_size = I830_FIFO_LINE_SIZE,
 626 };
 627 static const struct intel_watermark_params i830_bc_wm_info = {
 628         .fifo_size = I855GM_FIFO_SIZE,
 629         .max_wm = I915_MAX_WM/2,
 630         .default_wm = 1,
 631         .guard_size = 2,
 632         .cacheline_size = I830_FIFO_LINE_SIZE,
 633 };
 634 static const struct intel_watermark_params i845_wm_info = {
 635         .fifo_size = I830_FIFO_SIZE,
 636         .max_wm = I915_MAX_WM,
 637         .default_wm = 1,
 638         .guard_size = 2,
 639         .cacheline_size = I830_FIFO_LINE_SIZE,
 640 };
 641
 642 /**
 643  * intel_wm_method1 - Method 1 / "small buffer" watermark formula
 644  * @pixel_rate: Pipe pixel rate in kHz
 645  * @cpp: Plane bytes per pixel
 646  * @latency: Memory wakeup latency in 0.1us units
 647  *
 648  * Compute the watermark using the method 1 or "small buffer"
 649  * formula. The caller may additonally add extra cachelines
 650  * to account for TLB misses and clock crossings.
 651  *
 652  * This method is concerned with the short term drain rate
 653  * of the FIFO, ie. it does not account for blanking periods
 654  * which would effectively reduce the average drain rate across
 655  * a longer period. The name "small" refers to the fact the
 656  * FIFO is relatively small compared to the amount of data
 657  * fetched.
 658  *
 659  * The FIFO level vs. time graph might look something like:
 660  *
 661  *   |\   |\
 662  *   | \  | \
 663  * __---__---__ (- plane active, _ blanking)
 664  * -> time
 665  *
 666  * or perhaps like this:
 667  *
 668  *   |\|\  |\|\
 669  * __----__----__ (- plane active, _ blanking)
 670  * -> time
 671  *
 672  * Returns:
 673  * The watermark in bytes
 674  */
 675 static unsigned int intel_wm_method1(unsigned int pixel_rate,
 676                                      unsigned int cpp,
 677                                      unsigned int latency)
 678 {
 679         uint64_t ret;
 680
 681         ret = (uint64_t) pixel_rate * cpp * latency;
 682         ret = DIV_ROUND_UP_ULL(ret, 10000);
 683
 684         return ret;
 685 }
 686
 687 /**
 688  * intel_wm_method2 - Method 2 / "large buffer" watermark formula
 689  * @pixel_rate: Pipe pixel rate in kHz
 690  * @htotal: Pipe horizontal total
 691  * @width: Plane width in pixels
 692  * @cpp: Plane bytes per pixel
 693  * @latency: Memory wakeup latency in 0.1us units
 694  *
 695  * Compute the watermark using the method 2 or "large buffer"
 696  * formula. The caller may additonally add extra cachelines
 697  * to account for TLB misses and clock crossings.
 698  *
 699  * This method is concerned with the long term drain rate
 700  * of the FIFO, ie. it does account for blanking periods
 701  * which effectively reduce the average drain rate across
 702  * a longer period. The name "large" refers to the fact the
 703  * FIFO is relatively large compared to the amount of data
 704  * fetched.
 705  *
 706  * The FIFO level vs. time graph might look something like:
 707  *
 708  *    |\___       |\___
 709  *    |    \___   |    \___
 710  *    |        \  |        \
 711  * __ --__--__--__--__--__--__ (- plane active, _ blanking)
 712  * -> time
 713  *
 714  * Returns:
 715  * The watermark in bytes
 716  */
 717 static unsigned int intel_wm_method2(unsigned int pixel_rate,
 718                                      unsigned int htotal,
 719                                      unsigned int width,
 720                                      unsigned int cpp,
 721                                      unsigned int latency)
 722 {
 723         unsigned int ret;
 724
 725         /*
 726          * FIXME remove once all users are computing
 727          * watermarks in the correct place.
 728          */
 729         if (WARN_ON_ONCE(htotal == 0))
 730                 htotal = 1;
 731
 732         ret = (latency * pixel_rate) / (htotal * 10000);
 733         ret = (ret + 1) * width * cpp;
 734
 735         return ret;
 736 }
 737
 738 /**
 739  * intel_calculate_wm - calculate watermark level
 740  * @pixel_rate: pixel clock
 741  * @wm: chip FIFO params
 742  * @cpp: bytes per pixel
 743  * @latency_ns: memory latency for the platform
 744  *
 745  * Calculate the watermark level (the level at which the display plane will
 746  * start fetching from memory again).  Each chip has a different display
 747  * FIFO size and allocation, so the caller needs to figure that out and pass
 748  * in the correct intel_watermark_params structure.
 749  *
 750  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 751  * on the pixel size.  When it reaches the watermark level, it'll start
 752  * fetching FIFO line sized based chunks from memory until the FIFO fills
 753  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 754  * will occur, and a display engine hang could result.
 755  */
 756 static unsigned int intel_calculate_wm(int pixel_rate,
 757                                        const struct intel_watermark_params *wm,
 758                                        int fifo_size, int cpp,
 759                                        unsigned int latency_ns)
 760 {
 761         int entries, wm_size;
 762
 763         /*
 764          * Note: we need to make sure we don't overflow for various clock &
 765          * latency values.
 766          * clocks go from a few thousand to several hundred thousand.
 767          * latency is usually a few thousand
 768          */
 769         entries = intel_wm_method1(pixel_rate, cpp,
 770                                    latency_ns / 100);
 771         entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
 772                 wm->guard_size;
 773         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries);
 774
 775         wm_size = fifo_size - entries;
 776         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
 777
 778         /* Don't promote wm_size to unsigned... */
 779         if (wm_size > wm->max_wm)
 780                 wm_size = wm->max_wm;
 781         if (wm_size <= 0)
 782                 wm_size = wm->default_wm;
 783
 784         /*
 785          * Bspec seems to indicate that the value shouldn't be lower than
 786          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 787          * Lets go for 8 which is the burst size since certain platforms
 788          * already use a hardcoded 8 (which is what the spec says should be
 789          * done).
 790          */
 791         if (wm_size <= 8)
 792                 wm_size = 8;
 793
 794         return wm_size;
 795 }
 796
 797 static bool is_disabling(int old, int new, int threshold)
 798 {
 799         return old >= threshold && new < threshold;
 800 }
 801
 802 static bool is_enabling(int old, int new, int threshold)
 803 {
 804         return old < threshold && new >= threshold;
 805 }
 806
 807 static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
 808 {
 809         return dev_priv->wm.max_level + 1;
 810 }
 811
 812 static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
 813                                    const struct intel_plane_state *plane_state)
 814 {
 815         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 816
 817         /* FIXME check the 'enable' instead */
 818         if (!crtc_state->base.active)
 819                 return false;
 820
 821         /*
 822          * Treat cursor with fb as always visible since cursor updates
 823          * can happen faster than the vrefresh rate, and the current
 824          * watermark code doesn't handle that correctly. Cursor updates
 825          * which set/clear the fb or change the cursor size are going
 826          * to get throttled by intel_legacy_cursor_update() to work
 827          * around this problem with the watermark code.
 828          */
 829         if (plane->id == PLANE_CURSOR)
 830                 return plane_state->base.fb != NULL;
 831         else
 832                 return plane_state->base.visible;
 833 }
 834
 835 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 836 {
 837         struct intel_crtc *crtc, *enabled = NULL;
 838
 839         for_each_intel_crtc(&dev_priv->drm, crtc) {
 840                 if (intel_crtc_active(crtc)) {
 841                         if (enabled)
 842                                 return NULL;
 843                         enabled = crtc;
 844                 }
 845         }
 846
 847         return enabled;
 848 }
 849
 850 static void pineview_update_wm(struct intel_crtc *unused_crtc)
 851 {
 852         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 853         struct intel_crtc *crtc;
 854         const struct cxsr_latency *latency;
 855         u32 reg;
 856         unsigned int wm;
 857
 858         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
 859                                          dev_priv->is_ddr3,
 860                                          dev_priv->fsb_freq,
 861                                          dev_priv->mem_freq);
 862         if (!latency) {
 863                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 864                 intel_set_memory_cxsr(dev_priv, false);
 865                 return;
 866         }
 867
 868         crtc = single_enabled_crtc(dev_priv);
 869         if (crtc) {
 870                 const struct drm_display_mode *adjusted_mode =
 871                         &crtc->config->base.adjusted_mode;
 872                 const struct drm_framebuffer *fb =
 873                         crtc->base.primary->state->fb;
 874                 int cpp = fb->format->cpp[0];
 875                 int clock = adjusted_mode->crtc_clock;
 876
 877                 /* Display SR */
 878                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 879                                         pineview_display_wm.fifo_size,
 880                                         cpp, latency->display_sr);
 881                 reg = I915_READ(DSPFW1);
 882                 reg &= ~DSPFW_SR_MASK;
 883                 reg |= FW_WM(wm, SR);
 884                 I915_WRITE(DSPFW1, reg);
 885                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 886
 887                 /* cursor SR */
 888                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 889                                         pineview_display_wm.fifo_size,
 890                                         4, latency->cursor_sr);
 891                 reg = I915_READ(DSPFW3);
 892                 reg &= ~DSPFW_CURSOR_SR_MASK;
 893                 reg |= FW_WM(wm, CURSOR_SR);
 894                 I915_WRITE(DSPFW3, reg);
 895
 896                 /* Display HPLL off SR */
 897                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 898                                         pineview_display_hplloff_wm.fifo_size,
 899                                         cpp, latency->display_hpll_disable);
 900                 reg = I915_READ(DSPFW3);
 901                 reg &= ~DSPFW_HPLL_SR_MASK;
 902                 reg |= FW_WM(wm, HPLL_SR);
 903                 I915_WRITE(DSPFW3, reg);
 904
 905                 /* cursor HPLL off SR */
 906                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 907                                         pineview_display_hplloff_wm.fifo_size,
 908                                         4, latency->cursor_hpll_disable);
 909                 reg = I915_READ(DSPFW3);
 910                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 911                 reg |= FW_WM(wm, HPLL_CURSOR);
 912                 I915_WRITE(DSPFW3, reg);
 913                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 914
 915                 intel_set_memory_cxsr(dev_priv, true);
 916         } else {
 917                 intel_set_memory_cxsr(dev_priv, false);
 918         }
 919 }
 920
 921 /*
 922  * Documentation says:
 923  * "If the line size is small, the TLB fetches can get in the way of the
 924  *  data fetches, causing some lag in the pixel data return which is not
 925  *  accounted for in the above formulas. The following adjustment only
 926  *  needs to be applied if eight whole lines fit in the buffer at once.
 927  *  The WM is adjusted upwards by the difference between the FIFO size
 928  *  and the size of 8 whole lines. This adjustment is always performed
 929  *  in the actual pixel depth regardless of whether FBC is enabled or not."
 930  */
 931 static int g4x_tlb_miss_wa(int fifo_size, int width, int cpp)
 932 {
 933         int tlb_miss = fifo_size * 64 - width * cpp * 8;
 934
 935         return max(0, tlb_miss);
 936 }
 937
 938 static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
 939                                 const struct g4x_wm_values *wm)
 940 {
 941         enum pipe pipe;
 942
 943         for_each_pipe(dev_priv, pipe)
 944                 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
 945
 946         I915_WRITE(DSPFW1,
 947                    FW_WM(wm->sr.plane, SR) |
 948                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 949                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 950                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
 951         I915_WRITE(DSPFW2,
 952                    (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
 953                    FW_WM(wm->sr.fbc, FBC_SR) |
 954                    FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
 955                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
 956                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 957                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
 958         I915_WRITE(DSPFW3,
 959                    (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
 960                    FW_WM(wm->sr.cursor, CURSOR_SR) |
 961                    FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
 962                    FW_WM(wm->hpll.plane, HPLL_SR));
 963
 964         POSTING_READ(DSPFW1);
 965 }
 966
 967 #define FW_WM_VLV(value, plane) \
 968         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 969
 970 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
 971                                 const struct vlv_wm_values *wm)
 972 {
 973         enum pipe pipe;
 974
 975         for_each_pipe(dev_priv, pipe) {
 976                 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
 977
 978                 I915_WRITE(VLV_DDL(pipe),
 979                            (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
 980                            (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
 981                            (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
 982                            (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
 983         }
 984
 985         /*
 986          * Zero the (unused) WM1 watermarks, and also clear all the
 987          * high order bits so that there are no out of bounds values
 988          * present in the registers during the reprogramming.
 989          */
 990         I915_WRITE(DSPHOWM, 0);
 991         I915_WRITE(DSPHOWM1, 0);
 992         I915_WRITE(DSPFW4, 0);
 993         I915_WRITE(DSPFW5, 0);
 994         I915_WRITE(DSPFW6, 0);
 995
 996         I915_WRITE(DSPFW1,
 997                    FW_WM(wm->sr.plane, SR) |
 998                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 999                    FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
1000                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
1001         I915_WRITE(DSPFW2,
1002                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
1003                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
1004                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
1005         I915_WRITE(DSPFW3,
1006                    FW_WM(wm->sr.cursor, CURSOR_SR));
1007
1008         if (IS_CHERRYVIEW(dev_priv)) {
1009                 I915_WRITE(DSPFW7_CHV,
1010                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1011                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1012                 I915_WRITE(DSPFW8_CHV,
1013                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
1014                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
1015                 I915_WRITE(DSPFW9_CHV,
1016                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
1017                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
1018                 I915_WRITE(DSPHOWM,
1019                            FW_WM(wm->sr.plane >> 9, SR_HI) |
1020                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
1021                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
1022                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
1023                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1024                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1025                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1026                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1027                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1028                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1029         } else {
1030                 I915_WRITE(DSPFW7,
1031                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1032                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1033                 I915_WRITE(DSPHOWM,
1034                            FW_WM(wm->sr.plane >> 9, SR_HI) |
1035                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1036                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1037                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1038                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1039                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1040                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1041         }
1042
1043         POSTING_READ(DSPFW1);
1044 }
1045
1046 #undef FW_WM_VLV
1047
1048 static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
1049 {
1050         /* all latencies in usec */
1051         dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
1052         dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
1053         dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
1054
1055         dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
1056 }
1057
1058 static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
1059 {
1060         /*
1061          * DSPCNTR[13] supposedly controls whether the
1062          * primary plane can use the FIFO space otherwise
1063          * reserved for the sprite plane. It's not 100% clear
1064          * what the actual FIFO size is, but it looks like we
1065          * can happily set both primary and sprite watermarks
1066          * up to 127 cachelines. So that would seem to mean
1067          * that either DSPCNTR[13] doesn't do anything, or that
1068          * the total FIFO is >= 256 cachelines in size. Either
1069          * way, we don't seem to have to worry about this
1070          * repartitioning as the maximum watermark value the
1071          * register can hold for each plane is lower than the
1072          * minimum FIFO size.
1073          */
1074         switch (plane_id) {
1075         case PLANE_CURSOR:
1076                 return 63;
1077         case PLANE_PRIMARY:
1078                 return level == G4X_WM_LEVEL_NORMAL ? 127 : 511;
1079         case PLANE_SPRITE0:
1080                 return level == G4X_WM_LEVEL_NORMAL ? 127 : 0;
1081         default:
1082                 MISSING_CASE(plane_id);
1083                 return 0;
1084         }
1085 }
1086
1087 static int g4x_fbc_fifo_size(int level)
1088 {
1089         switch (level) {
1090         case G4X_WM_LEVEL_SR:
1091                 return 7;
1092         case G4X_WM_LEVEL_HPLL:
1093                 return 15;
1094         default:
1095                 MISSING_CASE(level);
1096                 return 0;
1097         }
1098 }
1099
1100 static uint16_t g4x_compute_wm(const struct intel_crtc_state *crtc_state,
1101                                const struct intel_plane_state *plane_state,
1102                                int level)
1103 {
1104         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1105         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1106         const struct drm_display_mode *adjusted_mode =
1107                 &crtc_state->base.adjusted_mode;
1108         int clock, htotal, cpp, width, wm;
1109         int latency = dev_priv->wm.pri_latency[level] * 10;
1110
1111         if (latency == 0)
1112                 return USHRT_MAX;
1113
1114         if (!intel_wm_plane_visible(crtc_state, plane_state))
1115                 return 0;
1116
1117         /*
1118          * Not 100% sure which way ELK should go here as the
1119          * spec only says CL/CTG should assume 32bpp and BW
1120          * doesn't need to. But as these things followed the
1121          * mobile vs. desktop lines on gen3 as well, let's
1122          * assume ELK doesn't need this.
1123          *
1124          * The spec also fails to list such a restriction for
1125          * the HPLL watermark, which seems a little strange.
1126          * Let's use 32bpp for the HPLL watermark as well.
1127          */
1128         if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY &&
1129             level != G4X_WM_LEVEL_NORMAL)
1130                 cpp = 4;
1131         else
1132                 cpp = plane_state->base.fb->format->cpp[0];
1133
1134         clock = adjusted_mode->crtc_clock;
1135         htotal = adjusted_mode->crtc_htotal;
1136
1137         if (plane->id == PLANE_CURSOR)
1138                 width = plane_state->base.crtc_w;
1139         else
1140                 width = drm_rect_width(&plane_state->base.dst);
1141
1142         if (plane->id == PLANE_CURSOR) {
1143                 wm = intel_wm_method2(clock, htotal, width, cpp, latency);
1144         } else if (plane->id == PLANE_PRIMARY &&
1145                    level == G4X_WM_LEVEL_NORMAL) {
1146                 wm = intel_wm_method1(clock, cpp, latency);
1147         } else {
1148                 int small, large;
1149
1150                 small = intel_wm_method1(clock, cpp, latency);
1151                 large = intel_wm_method2(clock, htotal, width, cpp, latency);
1152
1153                 wm = min(small, large);
1154         }
1155
1156         wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level),
1157                               width, cpp);
1158
1159         wm = DIV_ROUND_UP(wm, 64) + 2;
1160
1161         return min_t(int, wm, USHRT_MAX);
1162 }
1163
1164 static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1165                                  int level, enum plane_id plane_id, u16 value)
1166 {
1167         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1168         bool dirty = false;
1169
1170         for (; level < intel_wm_num_levels(dev_priv); level++) {
1171                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1172
1173                 dirty |= raw->plane[plane_id] != value;
1174                 raw->plane[plane_id] = value;
1175         }
1176
1177         return dirty;
1178 }
1179
1180 static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
1181                                int level, u16 value)
1182 {
1183         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1184         bool dirty = false;
1185
1186         /* NORMAL level doesn't have an FBC watermark */
1187         level = max(level, G4X_WM_LEVEL_SR);
1188
1189         for (; level < intel_wm_num_levels(dev_priv); level++) {
1190                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1191
1192                 dirty |= raw->fbc != value;
1193                 raw->fbc = value;
1194         }
1195
1196         return dirty;
1197 }
1198
1199 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1200                                    const struct intel_plane_state *pstate,
1201                                    uint32_t pri_val);
1202
1203 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1204                                      const struct intel_plane_state *plane_state)
1205 {
1206         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1207         int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1208         enum plane_id plane_id = plane->id;
1209         bool dirty = false;
1210         int level;
1211
1212         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1213                 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1214                 if (plane_id == PLANE_PRIMARY)
1215                         dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0);
1216                 goto out;
1217         }
1218
1219         for (level = 0; level < num_levels; level++) {
1220                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1221                 int wm, max_wm;
1222
1223                 wm = g4x_compute_wm(crtc_state, plane_state, level);
1224                 max_wm = g4x_plane_fifo_size(plane_id, level);
1225
1226                 if (wm > max_wm)
1227                         break;
1228
1229                 dirty |= raw->plane[plane_id] != wm;
1230                 raw->plane[plane_id] = wm;
1231
1232                 if (plane_id != PLANE_PRIMARY ||
1233                     level == G4X_WM_LEVEL_NORMAL)
1234                         continue;
1235
1236                 wm = ilk_compute_fbc_wm(crtc_state, plane_state,
1237                                         raw->plane[plane_id]);
1238                 max_wm = g4x_fbc_fifo_size(level);
1239
1240                 /*
1241                  * FBC wm is not mandatory as we
1242                  * can always just disable its use.
1243                  */
1244                 if (wm > max_wm)
1245                         wm = USHRT_MAX;
1246
1247                 dirty |= raw->fbc != wm;
1248                 raw->fbc = wm;
1249         }
1250
1251         /* mark watermarks as invalid */
1252         dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1253
1254         if (plane_id == PLANE_PRIMARY)
1255                 dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
1256
1257  out:
1258         if (dirty) {
1259                 DRM_DEBUG_KMS("%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1260                               plane->base.name,
1261                               crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
1262                               crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
1263                               crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
1264
1265                 if (plane_id == PLANE_PRIMARY)
1266                         DRM_DEBUG_KMS("FBC watermarks: SR=%d, HPLL=%d\n",
1267                                       crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
1268                                       crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
1269         }
1270
1271         return dirty;
1272 }
1273
1274 static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1275                                       enum plane_id plane_id, int level)
1276 {
1277         const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1278
1279         return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);
1280 }
1281
1282 static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
1283                                      int level)
1284 {
1285         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1286
1287         if (level > dev_priv->wm.max_level)
1288                 return false;
1289
1290         return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1291                 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1292                 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1293 }
1294
1295 /* mark all levels starting from 'level' as invalid */
1296 static void g4x_invalidate_wms(struct intel_crtc *crtc,
1297                                struct g4x_wm_state *wm_state, int level)
1298 {
1299         if (level <= G4X_WM_LEVEL_NORMAL) {
1300                 enum plane_id plane_id;
1301
1302                 for_each_plane_id_on_crtc(crtc, plane_id)
1303                         wm_state->wm.plane[plane_id] = USHRT_MAX;
1304         }
1305
1306         if (level <= G4X_WM_LEVEL_SR) {
1307                 wm_state->cxsr = false;
1308                 wm_state->sr.cursor = USHRT_MAX;
1309                 wm_state->sr.plane = USHRT_MAX;
1310                 wm_state->sr.fbc = USHRT_MAX;
1311         }
1312
1313         if (level <= G4X_WM_LEVEL_HPLL) {
1314                 wm_state->hpll_en = false;
1315                 wm_state->hpll.cursor = USHRT_MAX;
1316                 wm_state->hpll.plane = USHRT_MAX;
1317                 wm_state->hpll.fbc = USHRT_MAX;
1318         }
1319 }
1320
1321 static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1322 {
1323         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1324         struct intel_atomic_state *state =
1325                 to_intel_atomic_state(crtc_state->base.state);
1326         struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
1327         int num_active_planes = hweight32(crtc_state->active_planes &
1328                                           ~BIT(PLANE_CURSOR));
1329         const struct g4x_pipe_wm *raw;
1330         const struct intel_plane_state *old_plane_state;
1331         const struct intel_plane_state *new_plane_state;
1332         struct intel_plane *plane;
1333         enum plane_id plane_id;
1334         int i, level;
1335         unsigned int dirty = 0;
1336
1337         for_each_oldnew_intel_plane_in_state(state, plane,
1338                                              old_plane_state,
1339                                              new_plane_state, i) {
1340                 if (new_plane_state->base.crtc != &crtc->base &&
1341                     old_plane_state->base.crtc != &crtc->base)
1342                         continue;
1343
1344                 if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
1345                         dirty |= BIT(plane->id);
1346         }
1347
1348         if (!dirty)
1349                 return 0;
1350
1351         level = G4X_WM_LEVEL_NORMAL;
1352         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1353                 goto out;
1354
1355         raw = &crtc_state->wm.g4x.raw[level];
1356         for_each_plane_id_on_crtc(crtc, plane_id)
1357                 wm_state->wm.plane[plane_id] = raw->plane[plane_id];
1358
1359         level = G4X_WM_LEVEL_SR;
1360
1361         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1362                 goto out;
1363
1364         raw = &crtc_state->wm.g4x.raw[level];
1365         wm_state->sr.plane = raw->plane[PLANE_PRIMARY];
1366         wm_state->sr.cursor = raw->plane[PLANE_CURSOR];
1367         wm_state->sr.fbc = raw->fbc;
1368
1369         wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);
1370
1371         level = G4X_WM_LEVEL_HPLL;
1372
1373         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1374                 goto out;
1375
1376         raw = &crtc_state->wm.g4x.raw[level];
1377         wm_state->hpll.plane = raw->plane[PLANE_PRIMARY];
1378         wm_state->hpll.cursor = raw->plane[PLANE_CURSOR];
1379         wm_state->hpll.fbc = raw->fbc;
1380
1381         wm_state->hpll_en = wm_state->cxsr;
1382
1383         level++;
1384
1385  out:
1386         if (level == G4X_WM_LEVEL_NORMAL)
1387                 return -EINVAL;
1388
1389         /* invalidate the higher levels */
1390         g4x_invalidate_wms(crtc, wm_state, level);
1391
1392         /*
1393          * Determine if the FBC watermark(s) can be used. IF
1394          * this isn't the case we prefer to disable the FBC
1395          ( watermark(s) rather than disable the SR/HPLL
1396          * level(s) entirely.
1397          */
1398         wm_state->fbc_en = level > G4X_WM_LEVEL_NORMAL;
1399
1400         if (level >= G4X_WM_LEVEL_SR &&
1401             wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
1402                 wm_state->fbc_en = false;
1403         else if (level >= G4X_WM_LEVEL_HPLL &&
1404                  wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
1405                 wm_state->fbc_en = false;
1406
1407         return 0;
1408 }
1409
1410 static int g4x_compute_intermediate_wm(struct drm_device *dev,
1411                                        struct intel_crtc *crtc,
1412                                        struct intel_crtc_state *crtc_state)
1413 {
1414         struct g4x_wm_state *intermediate = &crtc_state->wm.g4x.intermediate;
1415         const struct g4x_wm_state *optimal = &crtc_state->wm.g4x.optimal;
1416         const struct g4x_wm_state *active = &crtc->wm.active.g4x;
1417         enum plane_id plane_id;
1418
1419         intermediate->cxsr = optimal->cxsr && active->cxsr &&
1420                 !crtc_state->disable_cxsr;
1421         intermediate->hpll_en = optimal->hpll_en && active->hpll_en &&
1422                 !crtc_state->disable_cxsr;
1423         intermediate->fbc_en = optimal->fbc_en && active->fbc_en;
1424
1425         for_each_plane_id_on_crtc(crtc, plane_id) {
1426                 intermediate->wm.plane[plane_id] =
1427                         max(optimal->wm.plane[plane_id],
1428                             active->wm.plane[plane_id]);
1429
1430                 WARN_ON(intermediate->wm.plane[plane_id] >
1431                         g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
1432         }
1433
1434         intermediate->sr.plane = max(optimal->sr.plane,
1435                                      active->sr.plane);
1436         intermediate->sr.cursor = max(optimal->sr.cursor,
1437                                       active->sr.cursor);
1438         intermediate->sr.fbc = max(optimal->sr.fbc,
1439                                    active->sr.fbc);
1440
1441         intermediate->hpll.plane = max(optimal->hpll.plane,
1442                                        active->hpll.plane);
1443         intermediate->hpll.cursor = max(optimal->hpll.cursor,
1444                                         active->hpll.cursor);
1445         intermediate->hpll.fbc = max(optimal->hpll.fbc,
1446                                      active->hpll.fbc);
1447
1448         WARN_ON((intermediate->sr.plane >
1449                  g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||
1450                  intermediate->sr.cursor >
1451                  g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&
1452                 intermediate->cxsr);
1453         WARN_ON((intermediate->sr.plane >
1454                  g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
1455                  intermediate->sr.cursor >
1456                  g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
1457                 intermediate->hpll_en);
1458
1459         WARN_ON(intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
1460                 intermediate->fbc_en && intermediate->cxsr);
1461         WARN_ON(intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
1462                 intermediate->fbc_en && intermediate->hpll_en);
1463
1464         /*
1465          * If our intermediate WM are identical to the final WM, then we can
1466          * omit the post-vblank programming; only update if it's different.
1467          */
1468         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
1469                 crtc_state->wm.need_postvbl_update = true;
1470
1471         return 0;
1472 }
1473
1474 static void g4x_merge_wm(struct drm_i915_private *dev_priv,
1475                          struct g4x_wm_values *wm)
1476 {
1477         struct intel_crtc *crtc;
1478         int num_active_crtcs = 0;
1479
1480         wm->cxsr = true;
1481         wm->hpll_en = true;
1482         wm->fbc_en = true;
1483
1484         for_each_intel_crtc(&dev_priv->drm, crtc) {
1485                 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1486
1487                 if (!crtc->active)
1488                         continue;
1489
1490                 if (!wm_state->cxsr)
1491                         wm->cxsr = false;
1492                 if (!wm_state->hpll_en)
1493                         wm->hpll_en = false;
1494                 if (!wm_state->fbc_en)
1495                         wm->fbc_en = false;
1496
1497                 num_active_crtcs++;
1498         }
1499
1500         if (num_active_crtcs != 1) {
1501                 wm->cxsr = false;
1502                 wm->hpll_en = false;
1503                 wm->fbc_en = false;
1504         }
1505
1506         for_each_intel_crtc(&dev_priv->drm, crtc) {
1507                 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1508                 enum pipe pipe = crtc->pipe;
1509
1510                 wm->pipe[pipe] = wm_state->wm;
1511                 if (crtc->active && wm->cxsr)
1512                         wm->sr = wm_state->sr;
1513                 if (crtc->active && wm->hpll_en)
1514                         wm->hpll = wm_state->hpll;
1515         }
1516 }
1517
1518 static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
1519 {
1520         struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
1521         struct g4x_wm_values new_wm = {};
1522
1523         g4x_merge_wm(dev_priv, &new_wm);
1524
1525         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
1526                 return;
1527
1528         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1529                 _intel_set_memory_cxsr(dev_priv, false);
1530
1531         g4x_write_wm_values(dev_priv, &new_wm);
1532
1533         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1534                 _intel_set_memory_cxsr(dev_priv, true);
1535
1536         *old_wm = new_wm;
1537 }
1538
1539 static void g4x_initial_watermarks(struct intel_atomic_state *state,
1540                                    struct intel_crtc_state *crtc_state)
1541 {
1542         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1543         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1544
1545         mutex_lock(&dev_priv->wm.wm_mutex);
1546         crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
1547         g4x_program_watermarks(dev_priv);
1548         mutex_unlock(&dev_priv->wm.wm_mutex);
1549 }
1550
1551 static void g4x_optimize_watermarks(struct intel_atomic_state *state,
1552                                     struct intel_crtc_state *crtc_state)
1553 {
1554         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1556
1557         if (!crtc_state->wm.need_postvbl_update)
1558                 return;
1559
1560         mutex_lock(&dev_priv->wm.wm_mutex);
1561         intel_crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
1562         g4x_program_watermarks(dev_priv);
1563         mutex_unlock(&dev_priv->wm.wm_mutex);
1564 }
1565
1566 /* latency must be in 0.1us units. */
1567 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
1568                                    unsigned int htotal,
1569                                    unsigned int width,
1570                                    unsigned int cpp,
1571                                    unsigned int latency)
1572 {
1573         unsigned int ret;
1574
1575         ret = intel_wm_method2(pixel_rate, htotal,
1576                                width, cpp, latency);
1577         ret = DIV_ROUND_UP(ret, 64);
1578
1579         return ret;
1580 }
1581
1582 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
1583 {
1584         /* all latencies in usec */
1585         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
1586
1587         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
1588
1589         if (IS_CHERRYVIEW(dev_priv)) {
1590                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
1591                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1592
1593                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
1594         }
1595 }
1596
1597 static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
1598                                      const struct intel_plane_state *plane_state,
1599                                      int level)
1600 {
1601         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1602         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1603         const struct drm_display_mode *adjusted_mode =
1604                 &crtc_state->base.adjusted_mode;
1605         int clock, htotal, cpp, width, wm;
1606
1607         if (dev_priv->wm.pri_latency[level] == 0)
1608                 return USHRT_MAX;
1609
1610         if (!intel_wm_plane_visible(crtc_state, plane_state))
1611                 return 0;
1612
1613         cpp = plane_state->base.fb->format->cpp[0];
1614         clock = adjusted_mode->crtc_clock;
1615         htotal = adjusted_mode->crtc_htotal;
1616         width = crtc_state->pipe_src_w;
1617
1618         if (plane->id == PLANE_CURSOR) {
1619                 /*
1620                  * FIXME the formula gives values that are
1621                  * too big for the cursor FIFO, and hence we
1622                  * would never be able to use cursors. For
1623                  * now just hardcode the watermark.
1624                  */
1625                 wm = 63;
1626         } else {
1627                 wm = vlv_wm_method2(clock, htotal, width, cpp,
1628                                     dev_priv->wm.pri_latency[level] * 10);
1629         }
1630
1631         return min_t(int, wm, USHRT_MAX);
1632 }
1633
1634 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
1635 {
1636         return (active_planes & (BIT(PLANE_SPRITE0) |
1637                                  BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1);
1638 }
1639
1640 static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
1641 {
1642         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1643         const struct g4x_pipe_wm *raw =
1644                 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
1645         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1646         unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1647         int num_active_planes = hweight32(active_planes);
1648         const int fifo_size = 511;
1649         int fifo_extra, fifo_left = fifo_size;
1650         int sprite0_fifo_extra = 0;
1651         unsigned int total_rate;
1652         enum plane_id plane_id;
1653
1654         /*
1655          * When enabling sprite0 after sprite1 has already been enabled
1656          * we tend to get an underrun unless sprite0 already has some
1657          * FIFO space allcoated. Hence we always allocate at least one
1658          * cacheline for sprite0 whenever sprite1 is enabled.
1659          *
1660          * All other plane enable sequences appear immune to this problem.
1661          */
1662         if (vlv_need_sprite0_fifo_workaround(active_planes))
1663                 sprite0_fifo_extra = 1;
1664
1665         total_rate = raw->plane[PLANE_PRIMARY] +
1666                 raw->plane[PLANE_SPRITE0] +
1667                 raw->plane[PLANE_SPRITE1] +
1668                 sprite0_fifo_extra;
1669
1670         if (total_rate > fifo_size)
1671                 return -EINVAL;
1672
1673         if (total_rate == 0)
1674                 total_rate = 1;
1675
1676         for_each_plane_id_on_crtc(crtc, plane_id) {
1677                 unsigned int rate;
1678
1679                 if ((active_planes & BIT(plane_id)) == 0) {
1680                         fifo_state->plane[plane_id] = 0;
1681                         continue;
1682                 }
1683
1684                 rate = raw->plane[plane_id];
1685                 fifo_state->plane[plane_id] = fifo_size * rate / total_rate;
1686                 fifo_left -= fifo_state->plane[plane_id];
1687         }
1688
1689         fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra;
1690         fifo_left -= sprite0_fifo_extra;
1691
1692         fifo_state->plane[PLANE_CURSOR] = 63;
1693
1694         fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1);
1695
1696         /* spread the remainder evenly */
1697         for_each_plane_id_on_crtc(crtc, plane_id) {
1698                 int plane_extra;
1699
1700                 if (fifo_left == 0)
1701                         break;
1702
1703                 if ((active_planes & BIT(plane_id)) == 0)
1704                         continue;
1705
1706                 plane_extra = min(fifo_extra, fifo_left);
1707                 fifo_state->plane[plane_id] += plane_extra;
1708                 fifo_left -= plane_extra;
1709         }
1710
1711         WARN_ON(active_planes != 0 && fifo_left != 0);
1712
1713         /* give it all to the first plane if none are active */
1714         if (active_planes == 0) {
1715                 WARN_ON(fifo_left != fifo_size);
1716                 fifo_state->plane[PLANE_PRIMARY] = fifo_left;
1717         }
1718
1719         return 0;
1720 }
1721
1722 /* mark all levels starting from 'level' as invalid */
1723 static void vlv_invalidate_wms(struct intel_crtc *crtc,
1724                                struct vlv_wm_state *wm_state, int level)
1725 {
1726         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1727
1728         for (; level < intel_wm_num_levels(dev_priv); level++) {
1729                 enum plane_id plane_id;
1730
1731                 for_each_plane_id_on_crtc(crtc, plane_id)
1732                         wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1733
1734                 wm_state->sr[level].cursor = USHRT_MAX;
1735                 wm_state->sr[level].plane = USHRT_MAX;
1736         }
1737 }
1738
1739 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1740 {
1741         if (wm > fifo_size)
1742                 return USHRT_MAX;
1743         else
1744                 return fifo_size - wm;
1745 }
1746
1747 /*
1748  * Starting from 'level' set all higher
1749  * levels to 'value' in the "raw" watermarks.
1750  */
1751 static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1752                                  int level, enum plane_id plane_id, u16 value)
1753 {
1754         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
1755         int num_levels = intel_wm_num_levels(dev_priv);
1756         bool dirty = false;
1757
1758         for (; level < num_levels; level++) {
1759                 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1760
1761                 dirty |= raw->plane[plane_id] != value;
1762                 raw->plane[plane_id] = value;
1763         }
1764
1765         return dirty;
1766 }
1767
1768 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1769                                      const struct intel_plane_state *plane_state)
1770 {
1771         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1772         enum plane_id plane_id = plane->id;
1773         int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1774         int level;
1775         bool dirty = false;
1776
1777         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1778                 dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1779                 goto out;
1780         }
1781
1782         for (level = 0; level < num_levels; level++) {
1783                 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1784                 int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
1785                 int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
1786
1787                 if (wm > max_wm)
1788                         break;
1789
1790                 dirty |= raw->plane[plane_id] != wm;
1791                 raw->plane[plane_id] = wm;
1792         }
1793
1794         /* mark all higher levels as invalid */
1795         dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1796
1797 out:
1798         if (dirty)
1799                 DRM_DEBUG_KMS("%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
1800                               plane->base.name,
1801                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1802                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1803                               crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
1804
1805         return dirty;
1806 }
1807
1808 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1809                                       enum plane_id plane_id, int level)
1810 {
1811         const struct g4x_pipe_wm *raw =
1812                 &crtc_state->wm.vlv.raw[level];
1813         const struct vlv_fifo_state *fifo_state =
1814                 &crtc_state->wm.vlv.fifo_state;
1815
1816         return raw->plane[plane_id] <= fifo_state->plane[plane_id];
1817 }
1818
1819 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)
1820 {
1821         return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1822                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1823                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) &&
1824                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1825 }
1826
1827 static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1828 {
1829         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1830         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1831         struct intel_atomic_state *state =
1832                 to_intel_atomic_state(crtc_state->base.state);
1833         struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1834         const struct vlv_fifo_state *fifo_state =
1835                 &crtc_state->wm.vlv.fifo_state;
1836         int num_active_planes = hweight32(crtc_state->active_planes &
1837                                           ~BIT(PLANE_CURSOR));
1838         bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base);
1839         const struct intel_plane_state *old_plane_state;
1840         const struct intel_plane_state *new_plane_state;
1841         struct intel_plane *plane;
1842         enum plane_id plane_id;
1843         int level, ret, i;
1844         unsigned int dirty = 0;
1845
1846         for_each_oldnew_intel_plane_in_state(state, plane,
1847                                              old_plane_state,
1848                                              new_plane_state, i) {
1849                 if (new_plane_state->base.crtc != &crtc->base &&
1850                     old_plane_state->base.crtc != &crtc->base)
1851                         continue;
1852
1853                 if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
1854                         dirty |= BIT(plane->id);
1855         }
1856
1857         /*
1858          * DSPARB registers may have been reset due to the
1859          * power well being turned off. Make sure we restore
1860          * them to a consistent state even if no primary/sprite
1861          * planes are initially active.
1862          */
1863         if (needs_modeset)
1864                 crtc_state->fifo_changed = true;
1865
1866         if (!dirty)
1867                 return 0;
1868
1869         /* cursor changes don't warrant a FIFO recompute */
1870         if (dirty & ~BIT(PLANE_CURSOR)) {
1871                 const struct intel_crtc_state *old_crtc_state =
1872                         intel_atomic_get_old_crtc_state(state, crtc);
1873                 const struct vlv_fifo_state *old_fifo_state =
1874                         &old_crtc_state->wm.vlv.fifo_state;
1875
1876                 ret = vlv_compute_fifo(crtc_state);
1877                 if (ret)
1878                         return ret;
1879
1880                 if (needs_modeset ||
1881                     memcmp(old_fifo_state, fifo_state,
1882                            sizeof(*fifo_state)) != 0)
1883                         crtc_state->fifo_changed = true;
1884         }
1885
1886         /* initially allow all levels */
1887         wm_state->num_levels = intel_wm_num_levels(dev_priv);
1888         /*
1889          * Note that enabling cxsr with no primary/sprite planes
1890          * enabled can wedge the pipe. Hence we only allow cxsr
1891          * with exactly one enabled primary/sprite plane.
1892          */
1893         wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
1894
1895         for (level = 0; level < wm_state->num_levels; level++) {
1896                 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1897                 const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1898
1899                 if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
1900                         break;
1901
1902                 for_each_plane_id_on_crtc(crtc, plane_id) {
1903                         wm_state->wm[level].plane[plane_id] =
1904                                 vlv_invert_wm_value(raw->plane[plane_id],
1905                                                     fifo_state->plane[plane_id]);
1906                 }
1907
1908                 wm_state->sr[level].plane =
1909                         vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY],
1910                                                  raw->plane[PLANE_SPRITE0],
1911                                                  raw->plane[PLANE_SPRITE1]),
1912                                             sr_fifo_size);
1913
1914                 wm_state->sr[level].cursor =
1915                         vlv_invert_wm_value(raw->plane[PLANE_CURSOR],
1916                                             63);
1917         }
1918
1919         if (level == 0)
1920                 return -EINVAL;
1921
1922         /* limit to only levels we can actually handle */
1923         wm_state->num_levels = level;
1924
1925         /* invalidate the higher levels */
1926         vlv_invalidate_wms(crtc, wm_state, level);
1927
1928         return 0;
1929 }
1930
1931 #define VLV_FIFO(plane, value) \
1932         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1933
1934 static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
1935                                    struct intel_crtc_state *crtc_state)
1936 {
1937         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1938         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1939         const struct vlv_fifo_state *fifo_state =
1940                 &crtc_state->wm.vlv.fifo_state;
1941         int sprite0_start, sprite1_start, fifo_size;
1942
1943         if (!crtc_state->fifo_changed)
1944                 return;
1945
1946         sprite0_start = fifo_state->plane[PLANE_PRIMARY];
1947         sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;
1948         fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;
1949
1950         WARN_ON(fifo_state->plane[PLANE_CURSOR] != 63);
1951         WARN_ON(fifo_size != 511);
1952
1953         trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
1954
1955         /*
1956          * uncore.lock serves a double purpose here. It allows us to
1957          * use the less expensive I915_{READ,WRITE}_FW() functions, and
1958          * it protects the DSPARB registers from getting clobbered by
1959          * parallel updates from multiple pipes.
1960          *
1961          * intel_pipe_update_start() has already disabled interrupts
1962          * for us, so a plain spin_lock() is sufficient here.
1963          */
1964         spin_lock(&dev_priv->uncore.lock);
1965
1966         switch (crtc->pipe) {
1967                 uint32_t dsparb, dsparb2, dsparb3;
1968         case PIPE_A:
1969                 dsparb = I915_READ_FW(DSPARB);
1970                 dsparb2 = I915_READ_FW(DSPARB2);
1971
1972                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1973                             VLV_FIFO(SPRITEB, 0xff));
1974                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1975                            VLV_FIFO(SPRITEB, sprite1_start));
1976
1977                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1978                              VLV_FIFO(SPRITEB_HI, 0x1));
1979                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1980                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1981
1982                 I915_WRITE_FW(DSPARB, dsparb);
1983                 I915_WRITE_FW(DSPARB2, dsparb2);
1984                 break;
1985         case PIPE_B:
1986                 dsparb = I915_READ_FW(DSPARB);
1987                 dsparb2 = I915_READ_FW(DSPARB2);
1988
1989                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1990                             VLV_FIFO(SPRITED, 0xff));
1991                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1992                            VLV_FIFO(SPRITED, sprite1_start));
1993
1994                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1995                              VLV_FIFO(SPRITED_HI, 0xff));
1996                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1997                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1998
1999                 I915_WRITE_FW(DSPARB, dsparb);
2000                 I915_WRITE_FW(DSPARB2, dsparb2);
2001                 break;
2002         case PIPE_C:
2003                 dsparb3 = I915_READ_FW(DSPARB3);
2004                 dsparb2 = I915_READ_FW(DSPARB2);
2005
2006                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
2007                              VLV_FIFO(SPRITEF, 0xff));
2008                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
2009                             VLV_FIFO(SPRITEF, sprite1_start));
2010
2011                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
2012                              VLV_FIFO(SPRITEF_HI, 0xff));
2013                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
2014                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
2015
2016                 I915_WRITE_FW(DSPARB3, dsparb3);
2017                 I915_WRITE_FW(DSPARB2, dsparb2);
2018                 break;
2019         default:
2020                 break;
2021         }
2022
2023         POSTING_READ_FW(DSPARB);
2024
2025         spin_unlock(&dev_priv->uncore.lock);
2026 }
2027
2028 #undef VLV_FIFO
2029
2030 static int vlv_compute_intermediate_wm(struct drm_device *dev,
2031                                        struct intel_crtc *crtc,
2032                                        struct intel_crtc_state *crtc_state)
2033 {
2034         struct vlv_wm_state *intermediate = &crtc_state->wm.vlv.intermediate;
2035         const struct vlv_wm_state *optimal = &crtc_state->wm.vlv.optimal;
2036         const struct vlv_wm_state *active = &crtc->wm.active.vlv;
2037         int level;
2038
2039         intermediate->num_levels = min(optimal->num_levels, active->num_levels);
2040         intermediate->cxsr = optimal->cxsr && active->cxsr &&
2041                 !crtc_state->disable_cxsr;
2042
2043         for (level = 0; level < intermediate->num_levels; level++) {
2044                 enum plane_id plane_id;
2045
2046                 for_each_plane_id_on_crtc(crtc, plane_id) {
2047                         intermediate->wm[level].plane[plane_id] =
2048                                 min(optimal->wm[level].plane[plane_id],
2049                                     active->wm[level].plane[plane_id]);
2050                 }
2051
2052                 intermediate->sr[level].plane = min(optimal->sr[level].plane,
2053                                                     active->sr[level].plane);
2054                 intermediate->sr[level].cursor = min(optimal->sr[level].cursor,
2055                                                      active->sr[level].cursor);
2056         }
2057
2058         vlv_invalidate_wms(crtc, intermediate, level);
2059
2060         /*
2061          * If our intermediate WM are identical to the final WM, then we can
2062          * omit the post-vblank programming; only update if it's different.
2063          */
2064         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
2065                 crtc_state->wm.need_postvbl_update = true;
2066
2067         return 0;
2068 }
2069
2070 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
2071                          struct vlv_wm_values *wm)
2072 {
2073         struct intel_crtc *crtc;
2074         int num_active_crtcs = 0;
2075
2076         wm->level = dev_priv->wm.max_level;
2077         wm->cxsr = true;
2078
2079         for_each_intel_crtc(&dev_priv->drm, crtc) {
2080                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2081
2082                 if (!crtc->active)
2083                         continue;
2084
2085                 if (!wm_state->cxsr)
2086                         wm->cxsr = false;
2087
2088                 num_active_crtcs++;
2089                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
2090         }
2091
2092         if (num_active_crtcs != 1)
2093                 wm->cxsr = false;
2094
2095         if (num_active_crtcs > 1)
2096                 wm->level = VLV_WM_LEVEL_PM2;
2097
2098         for_each_intel_crtc(&dev_priv->drm, crtc) {
2099                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2100                 enum pipe pipe = crtc->pipe;
2101
2102                 wm->pipe[pipe] = wm_state->wm[wm->level];
2103                 if (crtc->active && wm->cxsr)
2104                         wm->sr = wm_state->sr[wm->level];
2105
2106                 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
2107                 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
2108                 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
2109                 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
2110         }
2111 }
2112
2113 static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
2114 {
2115         struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
2116         struct vlv_wm_values new_wm = {};
2117
2118         vlv_merge_wm(dev_priv, &new_wm);
2119
2120         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
2121                 return;
2122
2123         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2124                 chv_set_memory_dvfs(dev_priv, false);
2125
2126         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2127                 chv_set_memory_pm5(dev_priv, false);
2128
2129         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
2130                 _intel_set_memory_cxsr(dev_priv, false);
2131
2132         vlv_write_wm_values(dev_priv, &new_wm);
2133
2134         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
2135                 _intel_set_memory_cxsr(dev_priv, true);
2136
2137         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2138                 chv_set_memory_pm5(dev_priv, true);
2139
2140         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2141                 chv_set_memory_dvfs(dev_priv, true);
2142
2143         *old_wm = new_wm;
2144 }
2145
2146 static void vlv_initial_watermarks(struct intel_atomic_state *state,
2147                                    struct intel_crtc_state *crtc_state)
2148 {
2149         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2150         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2151
2152         mutex_lock(&dev_priv->wm.wm_mutex);
2153         crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
2154         vlv_program_watermarks(dev_priv);
2155         mutex_unlock(&dev_priv->wm.wm_mutex);
2156 }
2157
2158 static void vlv_optimize_watermarks(struct intel_atomic_state *state,
2159                                     struct intel_crtc_state *crtc_state)
2160 {
2161         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2163
2164         if (!crtc_state->wm.need_postvbl_update)
2165                 return;
2166
2167         mutex_lock(&dev_priv->wm.wm_mutex);
2168         intel_crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
2169         vlv_program_watermarks(dev_priv);
2170         mutex_unlock(&dev_priv->wm.wm_mutex);
2171 }
2172
2173 static void i965_update_wm(struct intel_crtc *unused_crtc)
2174 {
2175         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2176         struct intel_crtc *crtc;
2177         int srwm = 1;
2178         int cursor_sr = 16;
2179         bool cxsr_enabled;
2180
2181         /* Calc sr entries for one plane configs */
2182         crtc = single_enabled_crtc(dev_priv);
2183         if (crtc) {
2184                 /* self-refresh has much higher latency */
2185                 static const int sr_latency_ns = 12000;
2186                 const struct drm_display_mode *adjusted_mode =
2187                         &crtc->config->base.adjusted_mode;
2188                 const struct drm_framebuffer *fb =
2189                         crtc->base.primary->state->fb;
2190                 int clock = adjusted_mode->crtc_clock;
2191                 int htotal = adjusted_mode->crtc_htotal;
2192                 int hdisplay = crtc->config->pipe_src_w;
2193                 int cpp = fb->format->cpp[0];
2194                 int entries;
2195
2196                 entries = intel_wm_method2(clock, htotal,
2197                                            hdisplay, cpp, sr_latency_ns / 100);
2198                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
2199                 srwm = I965_FIFO_SIZE - entries;
2200                 if (srwm < 0)
2201                         srwm = 1;
2202                 srwm &= 0x1ff;
2203                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
2204                               entries, srwm);
2205
2206                 entries = intel_wm_method2(clock, htotal,
2207                                            crtc->base.cursor->state->crtc_w, 4,
2208                                            sr_latency_ns / 100);
2209                 entries = DIV_ROUND_UP(entries,
2210                                        i965_cursor_wm_info.cacheline_size) +
2211                         i965_cursor_wm_info.guard_size;
2212
2213                 cursor_sr = i965_cursor_wm_info.fifo_size - entries;
2214                 if (cursor_sr > i965_cursor_wm_info.max_wm)
2215                         cursor_sr = i965_cursor_wm_info.max_wm;
2216
2217                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
2218                               "cursor %d\n", srwm, cursor_sr);
2219
2220                 cxsr_enabled = true;
2221         } else {
2222                 cxsr_enabled = false;
2223                 /* Turn off self refresh if both pipes are enabled */
2224                 intel_set_memory_cxsr(dev_priv, false);
2225         }
2226
2227         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2228                       srwm);
2229
2230         /* 965 has limitations... */
2231         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
2232                    FW_WM(8, CURSORB) |
2233                    FW_WM(8, PLANEB) |
2234                    FW_WM(8, PLANEA));
2235         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
2236                    FW_WM(8, PLANEC_OLD));
2237         /* update cursor SR watermark */
2238         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
2239
2240         if (cxsr_enabled)
2241                 intel_set_memory_cxsr(dev_priv, true);
2242 }
2243
2244 #undef FW_WM
2245
2246 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
2247 {
2248         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2249         const struct intel_watermark_params *wm_info;
2250         uint32_t fwater_lo;
2251         uint32_t fwater_hi;
2252         int cwm, srwm = 1;
2253         int fifo_size;
2254         int planea_wm, planeb_wm;
2255         struct intel_crtc *crtc, *enabled = NULL;
2256
2257         if (IS_I945GM(dev_priv))
2258                 wm_info = &i945_wm_info;
2259         else if (!IS_GEN2(dev_priv))
2260                 wm_info = &i915_wm_info;
2261         else
2262                 wm_info = &i830_a_wm_info;
2263
2264         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
2265         crtc = intel_get_crtc_for_plane(dev_priv, 0);
2266         if (intel_crtc_active(crtc)) {
2267                 const struct drm_display_mode *adjusted_mode =
2268                         &crtc->config->base.adjusted_mode;
2269                 const struct drm_framebuffer *fb =
2270                         crtc->base.primary->state->fb;
2271                 int cpp;
2272
2273                 if (IS_GEN2(dev_priv))
2274                         cpp = 4;
2275                 else
2276                         cpp = fb->format->cpp[0];
2277
2278                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2279                                                wm_info, fifo_size, cpp,
2280                                                pessimal_latency_ns);
2281                 enabled = crtc;
2282         } else {
2283                 planea_wm = fifo_size - wm_info->guard_size;
2284                 if (planea_wm > (long)wm_info->max_wm)
2285                         planea_wm = wm_info->max_wm;
2286         }
2287
2288         if (IS_GEN2(dev_priv))
2289                 wm_info = &i830_bc_wm_info;
2290
2291         fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
2292         crtc = intel_get_crtc_for_plane(dev_priv, 1);
2293         if (intel_crtc_active(crtc)) {
2294                 const struct drm_display_mode *adjusted_mode =
2295                         &crtc->config->base.adjusted_mode;
2296                 const struct drm_framebuffer *fb =
2297                         crtc->base.primary->state->fb;
2298                 int cpp;
2299
2300                 if (IS_GEN2(dev_priv))
2301                         cpp = 4;
2302                 else
2303                         cpp = fb->format->cpp[0];
2304
2305                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2306                                                wm_info, fifo_size, cpp,
2307                                                pessimal_latency_ns);
2308                 if (enabled == NULL)
2309                         enabled = crtc;
2310                 else
2311                         enabled = NULL;
2312         } else {
2313                 planeb_wm = fifo_size - wm_info->guard_size;
2314                 if (planeb_wm > (long)wm_info->max_wm)
2315                         planeb_wm = wm_info->max_wm;
2316         }
2317
2318         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2319
2320         if (IS_I915GM(dev_priv) && enabled) {
2321                 struct drm_i915_gem_object *obj;
2322
2323                 obj = intel_fb_obj(enabled->base.primary->state->fb);
2324
2325                 /* self-refresh seems busted with untiled */
2326                 if (!i915_gem_object_is_tiled(obj))
2327                         enabled = NULL;
2328         }
2329
2330         /*
2331          * Overlay gets an aggressive default since video jitter is bad.
2332          */
2333         cwm = 2;
2334
2335         /* Play safe and disable self-refresh before adjusting watermarks. */
2336         intel_set_memory_cxsr(dev_priv, false);
2337
2338         /* Calc sr entries for one plane configs */
2339         if (HAS_FW_BLC(dev_priv) && enabled) {
2340                 /* self-refresh has much higher latency */
2341                 static const int sr_latency_ns = 6000;
2342                 const struct drm_display_mode *adjusted_mode =
2343                         &enabled->config->base.adjusted_mode;
2344                 const struct drm_framebuffer *fb =
2345                         enabled->base.primary->state->fb;
2346                 int clock = adjusted_mode->crtc_clock;
2347                 int htotal = adjusted_mode->crtc_htotal;
2348                 int hdisplay = enabled->config->pipe_src_w;
2349                 int cpp;
2350                 int entries;
2351
2352                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2353                         cpp = 4;
2354                 else
2355                         cpp = fb->format->cpp[0];
2356
2357                 entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
2358                                            sr_latency_ns / 100);
2359                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
2360                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
2361                 srwm = wm_info->fifo_size - entries;
2362                 if (srwm < 0)
2363                         srwm = 1;
2364
2365                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
2366                         I915_WRITE(FW_BLC_SELF,
2367                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2368                 else
2369                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2370         }
2371
2372         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2373                       planea_wm, planeb_wm, cwm, srwm);
2374
2375         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2376         fwater_hi = (cwm & 0x1f);
2377
2378         /* Set request length to 8 cachelines per fetch */
2379         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2380         fwater_hi = fwater_hi | (1 << 8);
2381
2382         I915_WRITE(FW_BLC, fwater_lo);
2383         I915_WRITE(FW_BLC2, fwater_hi);
2384
2385         if (enabled)
2386                 intel_set_memory_cxsr(dev_priv, true);
2387 }
2388
2389 static void i845_update_wm(struct intel_crtc *unused_crtc)
2390 {
2391         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2392         struct intel_crtc *crtc;
2393         const struct drm_display_mode *adjusted_mode;
2394         uint32_t fwater_lo;
2395         int planea_wm;
2396
2397         crtc = single_enabled_crtc(dev_priv);
2398         if (crtc == NULL)
2399                 return;
2400
2401         adjusted_mode = &crtc->config->base.adjusted_mode;
2402         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
2403                                        &i845_wm_info,
2404                                        dev_priv->display.get_fifo_size(dev_priv, 0),
2405                                        4, pessimal_latency_ns);
2406         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2407         fwater_lo |= (3<<8) | planea_wm;
2408
2409         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2410
2411         I915_WRITE(FW_BLC, fwater_lo);
2412 }
2413
2414 /* latency must be in 0.1us units. */
2415 static unsigned int ilk_wm_method1(unsigned int pixel_rate,
2416                                    unsigned int cpp,
2417                                    unsigned int latency)
2418 {
2419         unsigned int ret;
2420
2421         ret = intel_wm_method1(pixel_rate, cpp, latency);
2422         ret = DIV_ROUND_UP(ret, 64) + 2;
2423
2424         return ret;
2425 }
2426
2427 /* latency must be in 0.1us units. */
2428 static unsigned int ilk_wm_method2(unsigned int pixel_rate,
2429                                    unsigned int htotal,
2430                                    unsigned int width,
2431                                    unsigned int cpp,
2432                                    unsigned int latency)
2433 {
2434         unsigned int ret;
2435
2436         ret = intel_wm_method2(pixel_rate, htotal,
2437                                width, cpp, latency);
2438         ret = DIV_ROUND_UP(ret, 64) + 2;
2439
2440         return ret;
2441 }
2442
2443 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2444                            uint8_t cpp)
2445 {
2446         /*
2447          * Neither of these should be possible since this function shouldn't be
2448          * called if the CRTC is off or the plane is invisible.  But let's be
2449          * extra paranoid to avoid a potential divide-by-zero if we screw up
2450          * elsewhere in the driver.
2451          */
2452         if (WARN_ON(!cpp))
2453                 return 0;
2454         if (WARN_ON(!horiz_pixels))
2455                 return 0;
2456
2457         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
2458 }
2459
2460 struct ilk_wm_maximums {
2461         uint16_t pri;
2462         uint16_t spr;
2463         uint16_t cur;
2464         uint16_t fbc;
2465 };
2466
2467 /*
2468  * For both WM_PIPE and WM_LP.
2469  * mem_value must be in 0.1us units.
2470  */
2471 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
2472                                    const struct intel_plane_state *pstate,
2473                                    uint32_t mem_value,
2474                                    bool is_lp)
2475 {
2476         uint32_t method1, method2;
2477         int cpp;
2478
2479         if (!intel_wm_plane_visible(cstate, pstate))
2480                 return 0;
2481
2482         cpp = pstate->base.fb->format->cpp[0];
2483
2484         method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
2485
2486         if (!is_lp)
2487                 return method1;
2488
2489         method2 = ilk_wm_method2(cstate->pixel_rate,
2490                                  cstate->base.adjusted_mode.crtc_htotal,
2491                                  drm_rect_width(&pstate->base.dst),
2492                                  cpp, mem_value);
2493
2494         return min(method1, method2);
2495 }
2496
2497 /*
2498  * For both WM_PIPE and WM_LP.
2499  * mem_value must be in 0.1us units.
2500  */
2501 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
2502                                    const struct intel_plane_state *pstate,
2503                                    uint32_t mem_value)
2504 {
2505         uint32_t method1, method2;
2506         int cpp;
2507
2508         if (!intel_wm_plane_visible(cstate, pstate))
2509                 return 0;
2510
2511         cpp = pstate->base.fb->format->cpp[0];
2512
2513         method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
2514         method2 = ilk_wm_method2(cstate->pixel_rate,
2515                                  cstate->base.adjusted_mode.crtc_htotal,
2516                                  drm_rect_width(&pstate->base.dst),
2517                                  cpp, mem_value);
2518         return min(method1, method2);
2519 }
2520
2521 /*
2522  * For both WM_PIPE and WM_LP.
2523  * mem_value must be in 0.1us units.
2524  */
2525 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
2526                                    const struct intel_plane_state *pstate,
2527                                    uint32_t mem_value)
2528 {
2529         int cpp;
2530
2531         if (!intel_wm_plane_visible(cstate, pstate))
2532                 return 0;
2533
2534         cpp = pstate->base.fb->format->cpp[0];
2535
2536         return ilk_wm_method2(cstate->pixel_rate,
2537                               cstate->base.adjusted_mode.crtc_htotal,
2538                               pstate->base.crtc_w, cpp, mem_value);
2539 }
2540
2541 /* Only for WM_LP. */
2542 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
2543                                    const struct intel_plane_state *pstate,
2544                                    uint32_t pri_val)
2545 {
2546         int cpp;
2547
2548         if (!intel_wm_plane_visible(cstate, pstate))
2549                 return 0;
2550
2551         cpp = pstate->base.fb->format->cpp[0];
2552
2553         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
2554 }
2555
2556 static unsigned int
2557 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
2558 {
2559         if (INTEL_GEN(dev_priv) >= 8)
2560                 return 3072;
2561         else if (INTEL_GEN(dev_priv) >= 7)
2562                 return 768;
2563         else
2564                 return 512;
2565 }
2566
2567 static unsigned int
2568 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
2569                      int level, bool is_sprite)
2570 {
2571         if (INTEL_GEN(dev_priv) >= 8)
2572                 /* BDW primary/sprite plane watermarks */
2573                 return level == 0 ? 255 : 2047;
2574         else if (INTEL_GEN(dev_priv) >= 7)
2575                 /* IVB/HSW primary/sprite plane watermarks */
2576                 return level == 0 ? 127 : 1023;
2577         else if (!is_sprite)
2578                 /* ILK/SNB primary plane watermarks */
2579                 return level == 0 ? 127 : 511;
2580         else
2581                 /* ILK/SNB sprite plane watermarks */
2582                 return level == 0 ? 63 : 255;
2583 }
2584
2585 static unsigned int
2586 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
2587 {
2588         if (INTEL_GEN(dev_priv) >= 7)
2589                 return level == 0 ? 63 : 255;
2590         else
2591                 return level == 0 ? 31 : 63;
2592 }
2593
2594 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
2595 {
2596         if (INTEL_GEN(dev_priv) >= 8)
2597                 return 31;
2598         else
2599                 return 15;
2600 }
2601
2602 /* Calculate the maximum primary/sprite plane watermark */
2603 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2604                                      int level,
2605                                      const struct intel_wm_config *config,
2606                                      enum intel_ddb_partitioning ddb_partitioning,
2607                                      bool is_sprite)
2608 {
2609         struct drm_i915_private *dev_priv = to_i915(dev);
2610         unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
2611
2612         /* if sprites aren't enabled, sprites get nothing */
2613         if (is_sprite && !config->sprites_enabled)
2614                 return 0;
2615
2616         /* HSW allows LP1+ watermarks even with multiple pipes */
2617         if (level == 0 || config->num_pipes_active > 1) {
2618                 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
2619
2620                 /*
2621                  * For some reason the non self refresh
2622                  * FIFO size is only half of the self
2623                  * refresh FIFO size on ILK/SNB.
2624                  */
2625                 if (INTEL_GEN(dev_priv) <= 6)
2626                         fifo_size /= 2;
2627         }
2628
2629         if (config->sprites_enabled) {
2630                 /* level 0 is always calculated with 1:1 split */
2631                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2632                         if (is_sprite)
2633                                 fifo_size *= 5;
2634                         fifo_size /= 6;
2635                 } else {
2636                         fifo_size /= 2;
2637                 }
2638         }
2639
2640         /* clamp to max that the registers can hold */
2641         return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
2642 }
2643
2644 /* Calculate the maximum cursor plane watermark */
2645 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2646                                       int level,
2647                                       const struct intel_wm_config *config)
2648 {
2649         /* HSW LP1+ watermarks w/ multiple pipes */
2650         if (level > 0 && config->num_pipes_active > 1)
2651                 return 64;
2652
2653         /* otherwise just report max that registers can hold */
2654         return ilk_cursor_wm_reg_max(to_i915(dev), level);
2655 }
2656
2657 static void ilk_compute_wm_maximums(const struct drm_device *dev,
2658                                     int level,
2659                                     const struct intel_wm_config *config,
2660                                     enum intel_ddb_partitioning ddb_partitioning,
2661                                     struct ilk_wm_maximums *max)
2662 {
2663         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2664         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2665         max->cur = ilk_cursor_wm_max(dev, level, config);
2666         max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
2667 }
2668
2669 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
2670                                         int level,
2671                                         struct ilk_wm_maximums *max)
2672 {
2673         max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
2674         max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
2675         max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
2676         max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2677 }
2678
2679 static bool ilk_validate_wm_level(int level,
2680                                   const struct ilk_wm_maximums *max,
2681                                   struct intel_wm_level *result)
2682 {
2683         bool ret;
2684
2685         /* already determined to be invalid? */
2686         if (!result->enable)
2687                 return false;
2688
2689         result->enable = result->pri_val <= max->pri &&
2690                          result->spr_val <= max->spr &&
2691                          result->cur_val <= max->cur;
2692
2693         ret = result->enable;
2694
2695         /*
2696          * HACK until we can pre-compute everything,
2697          * and thus fail gracefully if LP0 watermarks
2698          * are exceeded...
2699          */
2700         if (level == 0 && !result->enable) {
2701                 if (result->pri_val > max->pri)
2702                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2703                                       level, result->pri_val, max->pri);
2704                 if (result->spr_val > max->spr)
2705                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2706                                       level, result->spr_val, max->spr);
2707                 if (result->cur_val > max->cur)
2708                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2709                                       level, result->cur_val, max->cur);
2710
2711                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2712                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2713                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2714                 result->enable = true;
2715         }
2716
2717         return ret;
2718 }
2719
2720 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2721                                  const struct intel_crtc *intel_crtc,
2722                                  int level,
2723                                  struct intel_crtc_state *cstate,
2724                                  struct intel_plane_state *pristate,
2725                                  struct intel_plane_state *sprstate,
2726                                  struct intel_plane_state *curstate,
2727                                  struct intel_wm_level *result)
2728 {
2729         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2730         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2731         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2732
2733         /* WM1+ latency values stored in 0.5us units */
2734         if (level > 0) {
2735                 pri_latency *= 5;
2736                 spr_latency *= 5;
2737                 cur_latency *= 5;
2738         }
2739
2740         if (pristate) {
2741                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2742                                                      pri_latency, level);
2743                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2744         }
2745
2746         if (sprstate)
2747                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2748
2749         if (curstate)
2750                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2751
2752         result->enable = true;
2753 }
2754
2755 static uint32_t
2756 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2757 {
2758         const struct intel_atomic_state *intel_state =
2759                 to_intel_atomic_state(cstate->base.state);
2760         const struct drm_display_mode *adjusted_mode =
2761                 &cstate->base.adjusted_mode;
2762         u32 linetime, ips_linetime;
2763
2764         if (!cstate->base.active)
2765                 return 0;
2766         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2767                 return 0;
2768         if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))
2769                 return 0;
2770
2771         /* The WM are computed with base on how long it takes to fill a single
2772          * row at the given clock rate, multiplied by 8.
2773          * */
2774         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2775                                      adjusted_mode->crtc_clock);
2776         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2777                                          intel_state->cdclk.logical.cdclk);
2778
2779         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2780                PIPE_WM_LINETIME_TIME(linetime);
2781 }
2782
2783 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2784                                   uint16_t wm[8])
2785 {
2786         if (INTEL_GEN(dev_priv) >= 9) {
2787                 uint32_t val;
2788                 int ret, i;
2789                 int level, max_level = ilk_wm_max_level(dev_priv);
2790
2791                 /* read the first set of memory latencies[0:3] */
2792                 val = 0; /* data0 to be programmed to 0 for first set */
2793                 mutex_lock(&dev_priv->pcu_lock);
2794                 ret = sandybridge_pcode_read(dev_priv,
2795                                              GEN9_PCODE_READ_MEM_LATENCY,
2796                                              &val);
2797                 mutex_unlock(&dev_priv->pcu_lock);
2798
2799                 if (ret) {
2800                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2801                         return;
2802                 }
2803
2804                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2805                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2806                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2807                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2808                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2809                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2810                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2811
2812                 /* read the second set of memory latencies[4:7] */
2813                 val = 1; /* data0 to be programmed to 1 for second set */
2814                 mutex_lock(&dev_priv->pcu_lock);
2815                 ret = sandybridge_pcode_read(dev_priv,
2816                                              GEN9_PCODE_READ_MEM_LATENCY,
2817                                              &val);
2818                 mutex_unlock(&dev_priv->pcu_lock);
2819                 if (ret) {
2820                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2821                         return;
2822                 }
2823
2824                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2825                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2826                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2827                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2828                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2829                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2830                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2831
2832                 /*
2833                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2834                  * need to be disabled. We make sure to sanitize the values out
2835                  * of the punit to satisfy this requirement.
2836                  */
2837                 for (level = 1; level <= max_level; level++) {
2838                         if (wm[level] == 0) {
2839                                 for (i = level + 1; i <= max_level; i++)
2840                                         wm[i] = 0;
2841                                 break;
2842                         }
2843                 }
2844
2845                 /*
2846                  * WaWmMemoryReadLatency:skl+,glk
2847                  *
2848                  * punit doesn't take into account the read latency so we need
2849                  * to add 2us to the various latency levels we retrieve from the
2850                  * punit when level 0 response data us 0us.
2851                  */
2852                 if (wm[0] == 0) {
2853                         wm[0] += 2;
2854                         for (level = 1; level <= max_level; level++) {
2855                                 if (wm[level] == 0)
2856                                         break;
2857                                 wm[level] += 2;
2858                         }
2859                 }
2860
2861         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2862                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2863
2864                 wm[0] = (sskpd >> 56) & 0xFF;
2865                 if (wm[0] == 0)
2866                         wm[0] = sskpd & 0xF;
2867                 wm[1] = (sskpd >> 4) & 0xFF;
2868                 wm[2] = (sskpd >> 12) & 0xFF;
2869                 wm[3] = (sskpd >> 20) & 0x1FF;
2870                 wm[4] = (sskpd >> 32) & 0x1FF;
2871         } else if (INTEL_GEN(dev_priv) >= 6) {
2872                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2873
2874                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2875                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2876                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2877                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2878         } else if (INTEL_GEN(dev_priv) >= 5) {
2879                 uint32_t mltr = I915_READ(MLTR_ILK);
2880
2881                 /* ILK primary LP0 latency is 700 ns */
2882                 wm[0] = 7;
2883                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2884                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2885         } else {
2886                 MISSING_CASE(INTEL_DEVID(dev_priv));
2887         }
2888 }
2889
2890 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2891                                        uint16_t wm[5])
2892 {
2893         /* ILK sprite LP0 latency is 1300 ns */
2894         if (IS_GEN5(dev_priv))
2895                 wm[0] = 13;
2896 }
2897
2898 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2899                                        uint16_t wm[5])
2900 {
2901         /* ILK cursor LP0 latency is 1300 ns */
2902         if (IS_GEN5(dev_priv))
2903                 wm[0] = 13;
2904
2905         /* WaDoubleCursorLP3Latency:ivb */
2906         if (IS_IVYBRIDGE(dev_priv))
2907                 wm[3] *= 2;
2908 }
2909
2910 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2911 {
2912         /* how many WM levels are we expecting */
2913         if (INTEL_GEN(dev_priv) >= 9)
2914                 return 7;
2915         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2916                 return 4;
2917         else if (INTEL_GEN(dev_priv) >= 6)
2918                 return 3;
2919         else
2920                 return 2;
2921 }
2922
2923 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2924                                    const char *name,
2925                                    const uint16_t wm[8])
2926 {
2927         int level, max_level = ilk_wm_max_level(dev_priv);
2928
2929         for (level = 0; level <= max_level; level++) {
2930                 unsigned int latency = wm[level];
2931
2932                 if (latency == 0) {
2933                         DRM_ERROR("%s WM%d latency not provided\n",
2934                                   name, level);
2935                         continue;
2936                 }
2937
2938                 /*
2939                  * - latencies are in us on gen9.
2940                  * - before then, WM1+ latency values are in 0.5us units
2941                  */
2942                 if (INTEL_GEN(dev_priv) >= 9)
2943                         latency *= 10;
2944                 else if (level > 0)
2945                         latency *= 5;
2946
2947                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2948                               name, level, wm[level],
2949                               latency / 10, latency % 10);
2950         }
2951 }
2952
2953 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2954                                     uint16_t wm[5], uint16_t min)
2955 {
2956         int level, max_level = ilk_wm_max_level(dev_priv);
2957
2958         if (wm[0] >= min)
2959                 return false;
2960
2961         wm[0] = max(wm[0], min);
2962         for (level = 1; level <= max_level; level++)
2963                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2964
2965         return true;
2966 }
2967
2968 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
2969 {
2970         bool changed;
2971
2972         /*
2973          * The BIOS provided WM memory latency values are often
2974          * inadequate for high resolution displays. Adjust them.
2975          */
2976         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2977                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2978                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2979
2980         if (!changed)
2981                 return;
2982
2983         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2984         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2985         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2986         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
2987 }
2988
2989 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
2990 {
2991         intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
2992
2993         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2994                sizeof(dev_priv->wm.pri_latency));
2995         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2996                sizeof(dev_priv->wm.pri_latency));
2997
2998         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
2999         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
3000
3001         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3002         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3003         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3004
3005         if (IS_GEN6(dev_priv))
3006                 snb_wm_latency_quirk(dev_priv);
3007 }
3008
3009 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
3010 {
3011         intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
3012         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
3013 }
3014
3015 static bool ilk_validate_pipe_wm(struct drm_device *dev,
3016                                  struct intel_pipe_wm *pipe_wm)
3017 {
3018         /* LP0 watermark maximums depend on this pipe alone */
3019         const struct intel_wm_config config = {
3020                 .num_pipes_active = 1,
3021                 .sprites_enabled = pipe_wm->sprites_enabled,
3022                 .sprites_scaled = pipe_wm->sprites_scaled,
3023         };
3024         struct ilk_wm_maximums max;
3025
3026         /* LP0 watermarks always use 1/2 DDB partitioning */
3027         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
3028
3029         /* At least LP0 must be valid */
3030         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
3031                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
3032                 return false;
3033         }
3034
3035         return true;
3036 }
3037
3038 /* Compute new watermarks for the pipe */
3039 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
3040 {
3041         struct drm_atomic_state *state = cstate->base.state;
3042         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3043         struct intel_pipe_wm *pipe_wm;
3044         struct drm_device *dev = state->dev;
3045         const struct drm_i915_private *dev_priv = to_i915(dev);
3046         struct intel_plane *intel_plane;
3047         struct intel_plane_state *pristate = NULL;
3048         struct intel_plane_state *sprstate = NULL;
3049         struct intel_plane_state *curstate = NULL;
3050         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
3051         struct ilk_wm_maximums max;
3052
3053         pipe_wm = &cstate->wm.ilk.optimal;
3054
3055         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3056                 struct intel_plane_state *ps;
3057
3058                 ps = intel_atomic_get_existing_plane_state(state,
3059                                                            intel_plane);
3060                 if (!ps)
3061                         continue;
3062
3063                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
3064                         pristate = ps;
3065                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
3066                         sprstate = ps;
3067                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
3068                         curstate = ps;
3069         }
3070
3071         pipe_wm->pipe_enabled = cstate->base.active;
3072         if (sprstate) {
3073                 pipe_wm->sprites_enabled = sprstate->base.visible;
3074                 pipe_wm->sprites_scaled = sprstate->base.visible &&
3075                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
3076                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
3077         }
3078
3079         usable_level = max_level;
3080
3081         /* ILK/SNB: LP2+ watermarks only w/o sprites */
3082         if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
3083                 usable_level = 1;
3084
3085         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
3086         if (pipe_wm->sprites_scaled)
3087                 usable_level = 0;
3088
3089         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
3090                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
3091
3092         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
3093         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
3094
3095         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3096                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
3097
3098         if (!ilk_validate_pipe_wm(dev, pipe_wm))
3099                 return -EINVAL;
3100
3101         ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
3102
3103         for (level = 1; level <= max_level; level++) {
3104                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
3105
3106                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
3107                                      pristate, sprstate, curstate, wm);
3108
3109                 /*
3110                  * Disable any watermark level that exceeds the
3111                  * register maximums since such watermarks are
3112                  * always invalid.
3113                  */
3114                 if (level > usable_level)
3115                         continue;
3116
3117                 if (ilk_validate_wm_level(level, &max, wm))
3118                         pipe_wm->wm[level] = *wm;
3119                 else
3120                         usable_level = level;
3121         }
3122
3123         return 0;
3124 }
3125
3126 /*
3127  * Build a set of 'intermediate' watermark values that satisfy both the old
3128  * state and the new state.  These can be programmed to the hardware
3129  * immediately.
3130  */
3131 static int ilk_compute_intermediate_wm(struct drm_device *dev,
3132                                        struct intel_crtc *intel_crtc,
3133                                        struct intel_crtc_state *newstate)
3134 {
3135         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
3136         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
3137         int level, max_level = ilk_wm_max_level(to_i915(dev));
3138
3139         /*
3140          * Start with the final, target watermarks, then combine with the
3141          * currently active watermarks to get values that are safe both before
3142          * and after the vblank.
3143          */
3144         *a = newstate->wm.ilk.optimal;
3145         a->pipe_enabled |= b->pipe_enabled;
3146         a->sprites_enabled |= b->sprites_enabled;
3147         a->sprites_scaled |= b->sprites_scaled;
3148
3149         for (level = 0; level <= max_level; level++) {
3150                 struct intel_wm_level *a_wm = &a->wm[level];
3151                 const struct intel_wm_level *b_wm = &b->wm[level];
3152
3153                 a_wm->enable &= b_wm->enable;
3154                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
3155                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
3156                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
3157                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
3158         }
3159
3160         /*
3161          * We need to make sure that these merged watermark values are
3162          * actually a valid configuration themselves.  If they're not,
3163          * there's no safe way to transition from the old state to
3164          * the new state, so we need to fail the atomic transaction.
3165          */
3166         if (!ilk_validate_pipe_wm(dev, a))
3167                 return -EINVAL;
3168
3169         /*
3170          * If our intermediate WM are identical to the final WM, then we can
3171          * omit the post-vblank programming; only update if it's different.
3172          */
3173         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0)
3174                 newstate->wm.need_postvbl_update = true;
3175
3176         return 0;
3177 }
3178
3179 /*
3180  * Merge the watermarks from all active pipes for a specific level.
3181  */
3182 static void ilk_merge_wm_level(struct drm_device *dev,
3183                                int level,
3184                                struct intel_wm_level *ret_wm)
3185 {
3186         const struct intel_crtc *intel_crtc;
3187
3188         ret_wm->enable = true;
3189
3190         for_each_intel_crtc(dev, intel_crtc) {
3191                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
3192                 const struct intel_wm_level *wm = &active->wm[level];
3193
3194                 if (!active->pipe_enabled)
3195                         continue;
3196
3197                 /*
3198                  * The watermark values may have been used in the past,
3199                  * so we must maintain them in the registers for some
3200                  * time even if the level is now disabled.
3201                  */
3202                 if (!wm->enable)
3203                         ret_wm->enable = false;
3204
3205                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
3206                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
3207                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
3208                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
3209         }
3210 }
3211
3212 /*
3213  * Merge all low power watermarks for all active pipes.
3214  */
3215 static void ilk_wm_merge(struct drm_device *dev,
3216                          const struct intel_wm_config *config,
3217                          const struct ilk_wm_maximums *max,
3218                          struct intel_pipe_wm *merged)
3219 {
3220         struct drm_i915_private *dev_priv = to_i915(dev);
3221         int level, max_level = ilk_wm_max_level(dev_priv);
3222         int last_enabled_level = max_level;
3223
3224         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
3225         if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
3226             config->num_pipes_active > 1)
3227                 last_enabled_level = 0;
3228
3229         /* ILK: FBC WM must be disabled always */
3230         merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
3231
3232         /* merge each WM1+ level */
3233         for (level = 1; level <= max_level; level++) {
3234                 struct intel_wm_level *wm = &merged->wm[level];
3235
3236                 ilk_merge_wm_level(dev, level, wm);
3237
3238                 if (level > last_enabled_level)
3239                         wm->enable = false;
3240                 else if (!ilk_validate_wm_level(level, max, wm))
3241                         /* make sure all following levels get disabled */
3242                         last_enabled_level = level - 1;
3243
3244                 /*
3245                  * The spec says it is preferred to disable
3246                  * FBC WMs instead of disabling a WM level.
3247                  */
3248                 if (wm->fbc_val > max->fbc) {
3249                         if (wm->enable)
3250                                 merged->fbc_wm_enabled = false;
3251                         wm->fbc_val = 0;
3252                 }
3253         }
3254
3255         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3256         /*
3257          * FIXME this is racy. FBC might get enabled later.
3258          * What we should check here is whether FBC can be
3259          * enabled sometime later.
3260          */
3261         if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
3262             intel_fbc_is_active(dev_priv)) {
3263                 for (level = 2; level <= max_level; level++) {
3264                         struct intel_wm_level *wm = &merged->wm[level];
3265
3266                         wm->enable = false;
3267                 }
3268         }
3269 }
3270
3271 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
3272 {
3273         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
3274         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
3275 }
3276
3277 /* The value we need to program into the WM_LPx latency field */
3278 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
3279 {
3280         struct drm_i915_private *dev_priv = to_i915(dev);
3281
3282         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3283                 return 2 * level;
3284         else
3285                 return dev_priv->wm.pri_latency[level];
3286 }
3287
3288 static void ilk_compute_wm_results(struct drm_device *dev,
3289                                    const struct intel_pipe_wm *merged,
3290                                    enum intel_ddb_partitioning partitioning,
3291                                    struct ilk_wm_values *results)
3292 {
3293         struct drm_i915_private *dev_priv = to_i915(dev);
3294         struct intel_crtc *intel_crtc;
3295         int level, wm_lp;
3296
3297         results->enable_fbc_wm = merged->fbc_wm_enabled;
3298         results->partitioning = partitioning;
3299
3300         /* LP1+ register values */
3301         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3302                 const struct intel_wm_level *r;
3303
3304                 level = ilk_wm_lp_to_level(wm_lp, merged);
3305
3306                 r = &merged->wm[level];
3307
3308                 /*
3309                  * Maintain the watermark values even if the level is
3310                  * disabled. Doing otherwise could cause underruns.
3311                  */
3312                 results->wm_lp[wm_lp - 1] =
3313                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
3314                         (r->pri_val << WM1_LP_SR_SHIFT) |
3315                         r->cur_val;
3316
3317                 if (r->enable)
3318                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
3319
3320                 if (INTEL_GEN(dev_priv) >= 8)
3321                         results->wm_lp[wm_lp - 1] |=
3322                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
3323                 else
3324                         results->wm_lp[wm_lp - 1] |=
3325                                 r->fbc_val << WM1_LP_FBC_SHIFT;
3326
3327                 /*
3328                  * Always set WM1S_LP_EN when spr_val != 0, even if the
3329                  * level is disabled. Doing otherwise could cause underruns.
3330                  */
3331                 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
3332                         WARN_ON(wm_lp != 1);
3333                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
3334                 } else
3335                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
3336         }
3337
3338         /* LP0 register values */
3339         for_each_intel_crtc(dev, intel_crtc) {
3340                 enum pipe pipe = intel_crtc->pipe;
3341                 const struct intel_wm_level *r =
3342                         &intel_crtc->wm.active.ilk.wm[0];
3343
3344                 if (WARN_ON(!r->enable))
3345                         continue;
3346
3347                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
3348
3349                 results->wm_pipe[pipe] =
3350                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
3351                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
3352                         r->cur_val;
3353         }
3354 }
3355
3356 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
3357  * case both are at the same level. Prefer r1 in case they're the same. */
3358 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
3359                                                   struct intel_pipe_wm *r1,
3360                                                   struct intel_pipe_wm *r2)
3361 {
3362         int level, max_level = ilk_wm_max_level(to_i915(dev));
3363         int level1 = 0, level2 = 0;
3364
3365         for (level = 1; level <= max_level; level++) {
3366                 if (r1->wm[level].enable)
3367                         level1 = level;
3368                 if (r2->wm[level].enable)
3369                         level2 = level;
3370         }
3371
3372         if (level1 == level2) {
3373                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
3374                         return r2;
3375                 else
3376                         return r1;
3377         } else if (level1 > level2) {
3378                 return r1;
3379         } else {
3380                 return r2;
3381         }
3382 }
3383
3384 /* dirty bits used to track which watermarks need changes */
3385 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
3386 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
3387 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
3388 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
3389 #define WM_DIRTY_FBC (1 << 24)
3390 #define WM_DIRTY_DDB (1 << 25)
3391
3392 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
3393                                          const struct ilk_wm_values *old,
3394                                          const struct ilk_wm_values *new)
3395 {
3396         unsigned int dirty = 0;
3397         enum pipe pipe;
3398         int wm_lp;
3399
3400         for_each_pipe(dev_priv, pipe) {
3401                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
3402                         dirty |= WM_DIRTY_LINETIME(pipe);
3403                         /* Must disable LP1+ watermarks too */
3404                         dirty |= WM_DIRTY_LP_ALL;
3405                 }
3406
3407                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
3408                         dirty |= WM_DIRTY_PIPE(pipe);
3409                         /* Must disable LP1+ watermarks too */
3410                         dirty |= WM_DIRTY_LP_ALL;
3411                 }
3412         }
3413
3414         if (old->enable_fbc_wm != new->enable_fbc_wm) {
3415                 dirty |= WM_DIRTY_FBC;
3416                 /* Must disable LP1+ watermarks too */
3417                 dirty |= WM_DIRTY_LP_ALL;
3418         }
3419
3420         if (old->partitioning != new->partitioning) {
3421                 dirty |= WM_DIRTY_DDB;
3422                 /* Must disable LP1+ watermarks too */
3423                 dirty |= WM_DIRTY_LP_ALL;
3424         }
3425
3426         /* LP1+ watermarks already deemed dirty, no need to continue */
3427         if (dirty & WM_DIRTY_LP_ALL)
3428                 return dirty;
3429
3430         /* Find the lowest numbered LP1+ watermark in need of an update... */
3431         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3432                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
3433                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
3434                         break;
3435         }
3436
3437         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
3438         for (; wm_lp <= 3; wm_lp++)
3439                 dirty |= WM_DIRTY_LP(wm_lp);
3440
3441         return dirty;
3442 }
3443
3444 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
3445                                unsigned int dirty)
3446 {
3447         struct ilk_wm_values *previous = &dev_priv->wm.hw;
3448         bool changed = false;
3449
3450         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
3451                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
3452                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
3453                 changed = true;
3454         }
3455         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
3456                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
3457                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
3458                 changed = true;
3459         }
3460         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
3461                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
3462                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
3463                 changed = true;
3464         }
3465
3466         /*
3467          * Don't touch WM1S_LP_EN here.
3468          * Doing so could cause underruns.
3469          */
3470
3471         return changed;
3472 }
3473
3474 /*
3475  * The spec says we shouldn't write when we don't need, because every write
3476  * causes WMs to be re-evaluated, expending some power.
3477  */
3478 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
3479                                 struct ilk_wm_values *results)
3480 {
3481         struct ilk_wm_values *previous = &dev_priv->wm.hw;
3482         unsigned int dirty;
3483         uint32_t val;
3484
3485         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
3486         if (!dirty)
3487                 return;
3488
3489         _ilk_disable_lp_wm(dev_priv, dirty);
3490
3491         if (dirty & WM_DIRTY_PIPE(PIPE_A))
3492                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
3493         if (dirty & WM_DIRTY_PIPE(PIPE_B))
3494                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
3495         if (dirty & WM_DIRTY_PIPE(PIPE_C))
3496                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
3497
3498         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
3499                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
3500         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
3501                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
3502         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
3503                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
3504
3505         if (dirty & WM_DIRTY_DDB) {
3506                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3507                         val = I915_READ(WM_MISC);
3508                         if (results->partitioning == INTEL_DDB_PART_1_2)
3509                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
3510                         else
3511                                 val |= WM_MISC_DATA_PARTITION_5_6;
3512                         I915_WRITE(WM_MISC, val);
3513                 } else {
3514                         val = I915_READ(DISP_ARB_CTL2);
3515                         if (results->partitioning == INTEL_DDB_PART_1_2)
3516                                 val &= ~DISP_DATA_PARTITION_5_6;
3517                         else
3518                                 val |= DISP_DATA_PARTITION_5_6;
3519                         I915_WRITE(DISP_ARB_CTL2, val);
3520                 }
3521         }
3522
3523         if (dirty & WM_DIRTY_FBC) {
3524                 val = I915_READ(DISP_ARB_CTL);
3525                 if (results->enable_fbc_wm)
3526                         val &= ~DISP_FBC_WM_DIS;
3527                 else
3528                         val |= DISP_FBC_WM_DIS;
3529                 I915_WRITE(DISP_ARB_CTL, val);
3530         }
3531
3532         if (dirty & WM_DIRTY_LP(1) &&
3533             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
3534                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
3535
3536         if (INTEL_GEN(dev_priv) >= 7) {
3537                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
3538                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
3539                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
3540                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
3541         }
3542
3543         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
3544                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
3545         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
3546                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
3547         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
3548                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
3549
3550         dev_priv->wm.hw = *results;
3551 }
3552
3553 bool ilk_disable_lp_wm(struct drm_device *dev)
3554 {
3555         struct drm_i915_private *dev_priv = to_i915(dev);
3556
3557         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
3558 }
3559
3560 /*
3561  * FIXME: We still don't have the proper code detect if we need to apply the WA,
3562  * so assume we'll always need it in order to avoid underruns.
3563  */
3564 static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
3565 {
3566         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3567
3568         if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
3569                 return true;
3570
3571         return false;
3572 }
3573
3574 static bool
3575 intel_has_sagv(struct drm_i915_private *dev_priv)
3576 {
3577         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
3578             IS_CANNONLAKE(dev_priv))
3579                 return true;
3580
3581         if (IS_SKYLAKE(dev_priv) &&
3582             dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
3583                 return true;
3584
3585         return false;
3586 }
3587
3588 /*
3589  * SAGV dynamically adjusts the system agent voltage and clock frequencies
3590  * depending on power and performance requirements. The display engine access
3591  * to system memory is blocked during the adjustment time. Because of the
3592  * blocking time, having this enabled can cause full system hangs and/or pipe
3593  * underruns if we don't meet all of the following requirements:
3594  *
3595  *  - <= 1 pipe enabled
3596  *  - All planes can enable watermarks for latencies >= SAGV engine block time
3597  *  - We're not using an interlaced display configuration
3598  */
3599 int
3600 intel_enable_sagv(struct drm_i915_private *dev_priv)
3601 {
3602         int ret;
3603
3604         if (!intel_has_sagv(dev_priv))
3605                 return 0;
3606
3607         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
3608                 return 0;
3609
3610         DRM_DEBUG_KMS("Enabling the SAGV\n");
3611         mutex_lock(&dev_priv->pcu_lock);
3612
3613         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3614                                       GEN9_SAGV_ENABLE);
3615
3616         /* We don't need to wait for the SAGV when enabling */
3617         mutex_unlock(&dev_priv->pcu_lock);
3618
3619         /*
3620          * Some skl systems, pre-release machines in particular,
3621          * don't actually have an SAGV.
3622          */
3623         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3624                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3625                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3626                 return 0;
3627         } else if (ret < 0) {
3628                 DRM_ERROR("Failed to enable the SAGV\n");
3629                 return ret;
3630         }
3631
3632         dev_priv->sagv_status = I915_SAGV_ENABLED;
3633         return 0;
3634 }
3635
3636 int
3637 intel_disable_sagv(struct drm_i915_private *dev_priv)
3638 {
3639         int ret;
3640
3641         if (!intel_has_sagv(dev_priv))
3642                 return 0;
3643
3644         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
3645                 return 0;
3646
3647         DRM_DEBUG_KMS("Disabling the SAGV\n");
3648         mutex_lock(&dev_priv->pcu_lock);
3649
3650         /* bspec says to keep retrying for at least 1 ms */
3651         ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3652                                 GEN9_SAGV_DISABLE,
3653                                 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
3654                                 1);
3655         mutex_unlock(&dev_priv->pcu_lock);
3656
3657         /*
3658          * Some skl systems, pre-release machines in particular,
3659          * don't actually have an SAGV.
3660          */
3661         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3662                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3663                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3664                 return 0;
3665         } else if (ret < 0) {
3666                 DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
3667                 return ret;
3668         }
3669
3670         dev_priv->sagv_status = I915_SAGV_DISABLED;
3671         return 0;
3672 }
3673
3674 bool intel_can_enable_sagv(struct drm_atomic_state *state)
3675 {
3676         struct drm_device *dev = state->dev;
3677         struct drm_i915_private *dev_priv = to_i915(dev);
3678         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3679         struct intel_crtc *crtc;
3680         struct intel_plane *plane;
3681         struct intel_crtc_state *cstate;
3682         enum pipe pipe;
3683         int level, latency;
3684         int sagv_block_time_us = IS_GEN9(dev_priv) ? 30 : 20;
3685
3686         if (!intel_has_sagv(dev_priv))
3687                 return false;
3688
3689         /*
3690          * SKL+ workaround: bspec recommends we disable the SAGV when we have
3691          * more then one pipe enabled
3692          *
3693          * If there are no active CRTCs, no additional checks need be performed
3694          */
3695         if (hweight32(intel_state->active_crtcs) == 0)
3696                 return true;
3697         else if (hweight32(intel_state->active_crtcs) > 1)
3698                 return false;
3699
3700         /* Since we're now guaranteed to only have one active CRTC... */
3701         pipe = ffs(intel_state->active_crtcs) - 1;
3702         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3703         cstate = to_intel_crtc_state(crtc->base.state);
3704
3705         if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3706                 return false;
3707
3708         for_each_intel_plane_on_crtc(dev, crtc, plane) {
3709                 struct skl_plane_wm *wm =
3710                         &cstate->wm.skl.optimal.planes[plane->id];
3711
3712                 /* Skip this plane if it's not enabled */
3713                 if (!wm->wm[0].plane_en)
3714                         continue;
3715
3716                 /* Find the highest enabled wm level for this plane */
3717                 for (level = ilk_wm_max_level(dev_priv);
3718                      !wm->wm[level].plane_en; --level)
3719                      { }
3720
3721                 latency = dev_priv->wm.skl_latency[level];
3722
3723                 if (skl_needs_memory_bw_wa(intel_state) &&
3724                     plane->base.state->fb->modifier ==
3725                     I915_FORMAT_MOD_X_TILED)
3726                         latency += 15;
3727
3728                 /*
3729                  * If any of the planes on this pipe don't enable wm levels that
3730                  * incur memory latencies higher than sagv_block_time_us we
3731                  * can't enable the SAGV.
3732                  */
3733                 if (latency < sagv_block_time_us)
3734                         return false;
3735         }
3736
3737         return true;
3738 }
3739
3740 static void
3741 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3742                                    const struct intel_crtc_state *cstate,
3743                                    struct skl_ddb_entry *alloc, /* out */
3744                                    int *num_active /* out */)
3745 {
3746         struct drm_atomic_state *state = cstate->base.state;
3747         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3748         struct drm_i915_private *dev_priv = to_i915(dev);
3749         struct drm_crtc *for_crtc = cstate->base.crtc;
3750         unsigned int pipe_size, ddb_size;
3751         int nth_active_pipe;
3752
3753         if (WARN_ON(!state) || !cstate->base.active) {
3754                 alloc->start = 0;
3755                 alloc->end = 0;
3756                 *num_active = hweight32(dev_priv->active_crtcs);
3757                 return;
3758         }
3759
3760         if (intel_state->active_pipe_changes)
3761                 *num_active = hweight32(intel_state->active_crtcs);
3762         else
3763                 *num_active = hweight32(dev_priv->active_crtcs);
3764
3765         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3766         WARN_ON(ddb_size == 0);
3767
3768         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3769
3770         /*
3771          * If the state doesn't change the active CRTC's, then there's
3772          * no need to recalculate; the existing pipe allocation limits
3773          * should remain unchanged.  Note that we're safe from racing
3774          * commits since any racing commit that changes the active CRTC
3775          * list would need to grab _all_ crtc locks, including the one
3776          * we currently hold.
3777          */
3778         if (!intel_state->active_pipe_changes) {
3779                 /*
3780                  * alloc may be cleared by clear_intel_crtc_state,
3781                  * copy from old state to be sure
3782                  */
3783                 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
3784                 return;
3785         }
3786
3787         nth_active_pipe = hweight32(intel_state->active_crtcs &
3788                                     (drm_crtc_mask(for_crtc) - 1));
3789         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3790         alloc->start = nth_active_pipe * ddb_size / *num_active;
3791         alloc->end = alloc->start + pipe_size;
3792 }
3793
3794 static unsigned int skl_cursor_allocation(int num_active)
3795 {
3796         if (num_active == 1)
3797                 return 32;
3798
3799         return 8;
3800 }
3801
3802 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3803 {
3804         entry->start = reg & 0x3ff;
3805         entry->end = (reg >> 16) & 0x3ff;
3806         if (entry->end)
3807                 entry->end += 1;
3808 }
3809
3810 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3811                           struct skl_ddb_allocation *ddb /* out */)
3812 {
3813         struct intel_crtc *crtc;
3814
3815         memset(ddb, 0, sizeof(*ddb));
3816
3817         for_each_intel_crtc(&dev_priv->drm, crtc) {
3818                 enum intel_display_power_domain power_domain;
3819                 enum plane_id plane_id;
3820                 enum pipe pipe = crtc->pipe;
3821
3822                 power_domain = POWER_DOMAIN_PIPE(pipe);
3823                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3824                         continue;
3825
3826                 for_each_plane_id_on_crtc(crtc, plane_id) {
3827                         u32 val;
3828
3829                         if (plane_id != PLANE_CURSOR)
3830                                 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
3831                         else
3832                                 val = I915_READ(CUR_BUF_CFG(pipe));
3833
3834                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
3835                 }
3836
3837                 intel_display_power_put(dev_priv, power_domain);
3838         }
3839 }
3840
3841 /*
3842  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3843  * The bspec defines downscale amount as:
3844  *
3845  * """
3846  * Horizontal down scale amount = maximum[1, Horizontal source size /
3847  *                                           Horizontal destination size]
3848  * Vertical down scale amount = maximum[1, Vertical source size /
3849  *                                         Vertical destination size]
3850  * Total down scale amount = Horizontal down scale amount *
3851  *                           Vertical down scale amount
3852  * """
3853  *
3854  * Return value is provided in 16.16 fixed point form to retain fractional part.
3855  * Caller should take care of dividing & rounding off the value.
3856  */
3857 static uint_fixed_16_16_t
3858 skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
3859                            const struct intel_plane_state *pstate)
3860 {
3861         struct intel_plane *plane = to_intel_plane(pstate->base.plane);
3862         uint32_t src_w, src_h, dst_w, dst_h;
3863         uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
3864         uint_fixed_16_16_t downscale_h, downscale_w;
3865
3866         if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
3867                 return u32_to_fixed16(0);
3868
3869         /* n.b., src is 16.16 fixed point, dst is whole integer */
3870         if (plane->id == PLANE_CURSOR) {
3871                 /*
3872                  * Cursors only support 0/180 degree rotation,
3873                  * hence no need to account for rotation here.
3874                  */
3875                 src_w = pstate->base.src_w >> 16;
3876                 src_h = pstate->base.src_h >> 16;
3877                 dst_w = pstate->base.crtc_w;
3878                 dst_h = pstate->base.crtc_h;
3879         } else {
3880                 /*
3881                  * Src coordinates are already rotated by 270 degrees for
3882                  * the 90/270 degree plane rotation cases (to match the
3883                  * GTT mapping), hence no need to account for rotation here.
3884                  */
3885                 src_w = drm_rect_width(&pstate->base.src) >> 16;
3886                 src_h = drm_rect_height(&pstate->base.src) >> 16;
3887                 dst_w = drm_rect_width(&pstate->base.dst);
3888                 dst_h = drm_rect_height(&pstate->base.dst);
3889         }
3890
3891         fp_w_ratio = div_fixed16(src_w, dst_w);
3892         fp_h_ratio = div_fixed16(src_h, dst_h);
3893         downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
3894         downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
3895
3896         return mul_fixed16(downscale_w, downscale_h);
3897 }
3898
3899 static uint_fixed_16_16_t
3900 skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
3901 {
3902         uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
3903
3904         if (!crtc_state->base.enable)
3905                 return pipe_downscale;
3906
3907         if (crtc_state->pch_pfit.enabled) {
3908                 uint32_t src_w, src_h, dst_w, dst_h;
3909                 uint32_t pfit_size = crtc_state->pch_pfit.size;
3910                 uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
3911                 uint_fixed_16_16_t downscale_h, downscale_w;
3912
3913                 src_w = crtc_state->pipe_src_w;
3914                 src_h = crtc_state->pipe_src_h;
3915                 dst_w = pfit_size >> 16;
3916                 dst_h = pfit_size & 0xffff;
3917
3918                 if (!dst_w || !dst_h)
3919                         return pipe_downscale;
3920
3921                 fp_w_ratio = div_fixed16(src_w, dst_w);
3922                 fp_h_ratio = div_fixed16(src_h, dst_h);
3923                 downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
3924                 downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
3925
3926                 pipe_downscale = mul_fixed16(downscale_w, downscale_h);
3927         }
3928
3929         return pipe_downscale;
3930 }
3931
3932 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
3933                                   struct intel_crtc_state *cstate)
3934 {
3935         struct drm_crtc_state *crtc_state = &cstate->base;
3936         struct drm_atomic_state *state = crtc_state->state;
3937         struct drm_plane *plane;
3938         const struct drm_plane_state *pstate;
3939         struct intel_plane_state *intel_pstate;
3940         int crtc_clock, dotclk;
3941         uint32_t pipe_max_pixel_rate;
3942         uint_fixed_16_16_t pipe_downscale;
3943         uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
3944
3945         if (!cstate->base.enable)
3946                 return 0;
3947
3948         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
3949                 uint_fixed_16_16_t plane_downscale;
3950                 uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
3951                 int bpp;
3952
3953                 if (!intel_wm_plane_visible(cstate,
3954                                             to_intel_plane_state(pstate)))
3955                         continue;
3956
3957                 if (WARN_ON(!pstate->fb))
3958                         return -EINVAL;
3959
3960                 intel_pstate = to_intel_plane_state(pstate);
3961                 plane_downscale = skl_plane_downscale_amount(cstate,
3962                                                              intel_pstate);
3963                 bpp = pstate->fb->format->cpp[0] * 8;
3964                 if (bpp == 64)
3965                         plane_downscale = mul_fixed16(plane_downscale,
3966                                                       fp_9_div_8);
3967
3968                 max_downscale = max_fixed16(plane_downscale, max_downscale);
3969         }
3970         pipe_downscale = skl_pipe_downscale_amount(cstate);
3971
3972         pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
3973
3974         crtc_clock = crtc_state->adjusted_mode.crtc_clock;
3975         dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
3976
3977         if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
3978                 dotclk *= 2;
3979
3980         pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
3981
3982         if (pipe_max_pixel_rate < crtc_clock) {
3983                 DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n");
3984                 return -EINVAL;
3985         }
3986
3987         return 0;
3988 }
3989
3990 static unsigned int
3991 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3992                              const struct drm_plane_state *pstate,
3993                              int y)
3994 {
3995         struct intel_plane *plane = to_intel_plane(pstate->plane);
3996         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3997         uint32_t data_rate;
3998         uint32_t width = 0, height = 0;
3999         struct drm_framebuffer *fb;
4000         u32 format;
4001         uint_fixed_16_16_t down_scale_amount;
4002
4003         if (!intel_pstate->base.visible)
4004                 return 0;
4005
4006         fb = pstate->fb;
4007         format = fb->format->format;
4008
4009         if (plane->id == PLANE_CURSOR)
4010                 return 0;
4011         if (y && format != DRM_FORMAT_NV12)
4012                 return 0;
4013
4014         /*
4015          * Src coordinates are already rotated by 270 degrees for
4016          * the 90/270 degree plane rotation cases (to match the
4017          * GTT mapping), hence no need to account for rotation here.
4018          */
4019         width = drm_rect_width(&intel_pstate->base.src) >> 16;
4020         height = drm_rect_height(&intel_pstate->base.src) >> 16;
4021
4022         /* for planar format */
4023         if (format == DRM_FORMAT_NV12) {
4024                 if (y)  /* y-plane data rate */
4025                         data_rate = width * height *
4026                                 fb->format->cpp[0];
4027                 else    /* uv-plane data rate */
4028                         data_rate = (width / 2) * (height / 2) *
4029                                 fb->format->cpp[1];
4030         } else {
4031                 /* for packed formats */
4032                 data_rate = width * height * fb->format->cpp[0];
4033         }
4034
4035         down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
4036
4037         return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
4038 }
4039
4040 /*
4041  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
4042  * a 8192x4096@32bpp framebuffer:
4043  *   3 * 4096 * 8192  * 4 < 2^32
4044  */
4045 static unsigned int
4046 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
4047                                  unsigned *plane_data_rate,
4048                                  unsigned *plane_y_data_rate)
4049 {
4050         struct drm_crtc_state *cstate = &intel_cstate->base;
4051         struct drm_atomic_state *state = cstate->state;
4052         struct drm_plane *plane;
4053         const struct drm_plane_state *pstate;
4054         unsigned int total_data_rate = 0;
4055
4056         if (WARN_ON(!state))
4057                 return 0;
4058
4059         /* Calculate and cache data rate for each plane */
4060         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
4061                 enum plane_id plane_id = to_intel_plane(plane)->id;
4062                 unsigned int rate;
4063
4064                 /* packed/uv */
4065                 rate = skl_plane_relative_data_rate(intel_cstate,
4066                                                     pstate, 0);
4067                 plane_data_rate[plane_id] = rate;
4068
4069                 total_data_rate += rate;
4070
4071                 /* y-plane */
4072                 rate = skl_plane_relative_data_rate(intel_cstate,
4073                                                     pstate, 1);
4074                 plane_y_data_rate[plane_id] = rate;
4075
4076                 total_data_rate += rate;
4077         }
4078
4079         return total_data_rate;
4080 }
4081
4082 static uint16_t
4083 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
4084                   const int y)
4085 {
4086         struct drm_framebuffer *fb = pstate->fb;
4087         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
4088         uint32_t src_w, src_h;
4089         uint32_t min_scanlines = 8;
4090         uint8_t plane_bpp;
4091
4092         if (WARN_ON(!fb))
4093                 return 0;
4094
4095         /* For packed formats, no y-plane, return 0 */
4096         if (y && fb->format->format != DRM_FORMAT_NV12)
4097                 return 0;
4098
4099         /* For Non Y-tile return 8-blocks */
4100         if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
4101             fb->modifier != I915_FORMAT_MOD_Yf_TILED &&
4102             fb->modifier != I915_FORMAT_MOD_Y_TILED_CCS &&
4103             fb->modifier != I915_FORMAT_MOD_Yf_TILED_CCS)
4104                 return 8;
4105
4106         /*
4107          * Src coordinates are already rotated by 270 degrees for
4108          * the 90/270 degree plane rotation cases (to match the
4109          * GTT mapping), hence no need to account for rotation here.
4110          */
4111         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
4112         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
4113
4114         /* Halve UV plane width and height for NV12 */
4115         if (fb->format->format == DRM_FORMAT_NV12 && !y) {
4116                 src_w /= 2;
4117                 src_h /= 2;
4118         }
4119
4120         if (fb->format->format == DRM_FORMAT_NV12 && !y)
4121                 plane_bpp = fb->format->cpp[1];
4122         else
4123                 plane_bpp = fb->format->cpp[0];
4124
4125         if (drm_rotation_90_or_270(pstate->rotation)) {
4126                 switch (plane_bpp) {
4127                 case 1:
4128                         min_scanlines = 32;
4129                         break;
4130                 case 2:
4131                         min_scanlines = 16;
4132                         break;
4133                 case 4:
4134                         min_scanlines = 8;
4135                         break;
4136                 case 8:
4137                         min_scanlines = 4;
4138                         break;
4139                 default:
4140                         WARN(1, "Unsupported pixel depth %u for rotation",
4141                              plane_bpp);
4142                         min_scanlines = 32;
4143                 }
4144         }
4145
4146         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
4147 }
4148
4149 static void
4150 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
4151                  uint16_t *minimum, uint16_t *y_minimum)
4152 {
4153         const struct drm_plane_state *pstate;
4154         struct drm_plane *plane;
4155
4156         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
4157                 enum plane_id plane_id = to_intel_plane(plane)->id;
4158
4159                 if (plane_id == PLANE_CURSOR)
4160                         continue;
4161
4162                 if (!pstate->visible)
4163                         continue;
4164
4165                 minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
4166                 y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
4167         }
4168
4169         minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
4170 }
4171
4172 static int
4173 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
4174                       struct skl_ddb_allocation *ddb /* out */)
4175 {
4176         struct drm_atomic_state *state = cstate->base.state;
4177         struct drm_crtc *crtc = cstate->base.crtc;
4178         struct drm_device *dev = crtc->dev;
4179         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4180         enum pipe pipe = intel_crtc->pipe;
4181         struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
4182         uint16_t alloc_size, start;
4183         uint16_t minimum[I915_MAX_PLANES] = {};
4184         uint16_t y_minimum[I915_MAX_PLANES] = {};
4185         unsigned int total_data_rate;
4186         enum plane_id plane_id;
4187         int num_active;
4188         unsigned plane_data_rate[I915_MAX_PLANES] = {};
4189         unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
4190         uint16_t total_min_blocks = 0;
4191
4192         /* Clear the partitioning for disabled planes. */
4193         memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4194         memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
4195
4196         if (WARN_ON(!state))
4197                 return 0;
4198
4199         if (!cstate->base.active) {
4200                 alloc->start = alloc->end = 0;
4201                 return 0;
4202         }
4203
4204         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
4205         alloc_size = skl_ddb_entry_size(alloc);
4206         if (alloc_size == 0)
4207                 return 0;
4208
4209         skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
4210
4211         /*
4212          * 1. Allocate the mininum required blocks for each active plane
4213          * and allocate the cursor, it doesn't require extra allocation
4214          * proportional to the data rate.
4215          */
4216
4217         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4218                 total_min_blocks += minimum[plane_id];
4219                 total_min_blocks += y_minimum[plane_id];
4220         }
4221
4222         if (total_min_blocks > alloc_size) {
4223                 DRM_DEBUG_KMS("Requested display configuration exceeds system DDB limitations");
4224                 DRM_DEBUG_KMS("minimum required %d/%d\n", total_min_blocks,
4225                                                         alloc_size);
4226                 return -EINVAL;
4227         }
4228
4229         alloc_size -= total_min_blocks;
4230         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
4231         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
4232
4233         /*
4234          * 2. Distribute the remaining space in proportion to the amount of
4235          * data each plane needs to fetch from memory.
4236          *
4237          * FIXME: we may not allocate every single block here.
4238          */
4239         total_data_rate = skl_get_total_relative_data_rate(cstate,
4240                                                            plane_data_rate,
4241                                                            plane_y_data_rate);
4242         if (total_data_rate == 0)
4243                 return 0;
4244
4245         start = alloc->start;
4246         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4247                 unsigned int data_rate, y_data_rate;
4248                 uint16_t plane_blocks, y_plane_blocks = 0;
4249
4250                 if (plane_id == PLANE_CURSOR)
4251                         continue;
4252
4253                 data_rate = plane_data_rate[plane_id];
4254
4255                 /*
4256                  * allocation for (packed formats) or (uv-plane part of planar format):
4257                  * promote the expression to 64 bits to avoid overflowing, the
4258                  * result is < available as data_rate / total_data_rate < 1
4259                  */
4260                 plane_blocks = minimum[plane_id];
4261                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
4262                                         total_data_rate);
4263
4264                 /* Leave disabled planes at (0,0) */
4265                 if (data_rate) {
4266                         ddb->plane[pipe][plane_id].start = start;
4267                         ddb->plane[pipe][plane_id].end = start + plane_blocks;
4268                 }
4269
4270                 start += plane_blocks;
4271
4272                 /*
4273                  * allocation for y_plane part of planar format:
4274                  */
4275                 y_data_rate = plane_y_data_rate[plane_id];
4276
4277                 y_plane_blocks = y_minimum[plane_id];
4278                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
4279                                         total_data_rate);
4280
4281                 if (y_data_rate) {
4282                         ddb->y_plane[pipe][plane_id].start = start;
4283                         ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
4284                 }
4285
4286                 start += y_plane_blocks;
4287         }
4288
4289         return 0;
4290 }
4291
4292 /*
4293  * The max latency should be 257 (max the punit can code is 255 and we add 2us
4294  * for the read latency) and cpp should always be <= 8, so that
4295  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
4296  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
4297 */
4298 static uint_fixed_16_16_t
4299 skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
4300                uint8_t cpp, uint32_t latency)
4301 {
4302         uint32_t wm_intermediate_val;
4303         uint_fixed_16_16_t ret;
4304
4305         if (latency == 0)
4306                 return FP_16_16_MAX;
4307
4308         wm_intermediate_val = latency * pixel_rate * cpp;
4309         ret = div_fixed16(wm_intermediate_val, 1000 * 512);
4310
4311         if (INTEL_GEN(dev_priv) >= 10)
4312                 ret = add_fixed16_u32(ret, 1);
4313
4314         return ret;
4315 }
4316
4317 static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
4318                         uint32_t pipe_htotal,
4319                         uint32_t latency,
4320                         uint_fixed_16_16_t plane_blocks_per_line)
4321 {
4322         uint32_t wm_intermediate_val;
4323         uint_fixed_16_16_t ret;
4324
4325         if (latency == 0)
4326                 return FP_16_16_MAX;
4327
4328         wm_intermediate_val = latency * pixel_rate;
4329         wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
4330                                            pipe_htotal * 1000);
4331         ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line);
4332         return ret;
4333 }
4334
4335 static uint_fixed_16_16_t
4336 intel_get_linetime_us(struct intel_crtc_state *cstate)
4337 {
4338         uint32_t pixel_rate;
4339         uint32_t crtc_htotal;
4340         uint_fixed_16_16_t linetime_us;
4341
4342         if (!cstate->base.active)
4343                 return u32_to_fixed16(0);
4344
4345         pixel_rate = cstate->pixel_rate;
4346
4347         if (WARN_ON(pixel_rate == 0))
4348                 return u32_to_fixed16(0);
4349
4350         crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;
4351         linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
4352
4353         return linetime_us;
4354 }
4355
4356 static uint32_t
4357 skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
4358                               const struct intel_plane_state *pstate)
4359 {
4360         uint64_t adjusted_pixel_rate;
4361         uint_fixed_16_16_t downscale_amount;
4362
4363         /* Shouldn't reach here on disabled planes... */
4364         if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
4365                 return 0;
4366
4367         /*
4368          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
4369          * with additional adjustments for plane-specific scaling.
4370          */
4371         adjusted_pixel_rate = cstate->pixel_rate;
4372         downscale_amount = skl_plane_downscale_amount(cstate, pstate);
4373
4374         return mul_round_up_u32_fixed16(adjusted_pixel_rate,
4375                                             downscale_amount);
4376 }
4377
4378 static int
4379 skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
4380                             struct intel_crtc_state *cstate,
4381                             const struct intel_plane_state *intel_pstate,
4382                             struct skl_wm_params *wp)
4383 {
4384         struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
4385         const struct drm_plane_state *pstate = &intel_pstate->base;
4386         const struct drm_framebuffer *fb = pstate->fb;
4387         uint32_t interm_pbpl;
4388         struct intel_atomic_state *state =
4389                 to_intel_atomic_state(cstate->base.state);
4390         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
4391
4392         if (!intel_wm_plane_visible(cstate, intel_pstate))
4393                 return 0;
4394
4395         wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
4396                       fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
4397                       fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
4398                       fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
4399         wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
4400         wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
4401                          fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
4402
4403         if (plane->id == PLANE_CURSOR) {
4404                 wp->width = intel_pstate->base.crtc_w;
4405         } else {
4406                 /*
4407                  * Src coordinates are already rotated by 270 degrees for
4408                  * the 90/270 degree plane rotation cases (to match the
4409                  * GTT mapping), hence no need to account for rotation here.
4410                  */
4411                 wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
4412         }
4413
4414         wp->cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
4415                                                             fb->format->cpp[0];
4416         wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
4417                                                              intel_pstate);
4418
4419         if (drm_rotation_90_or_270(pstate->rotation)) {
4420
4421                 switch (wp->cpp) {
4422                 case 1:
4423                         wp->y_min_scanlines = 16;
4424                         break;
4425                 case 2:
4426                         wp->y_min_scanlines = 8;
4427                         break;
4428                 case 4:
4429                         wp->y_min_scanlines = 4;
4430                         break;
4431                 default:
4432                         MISSING_CASE(wp->cpp);
4433                         return -EINVAL;
4434                 }
4435         } else {
4436                 wp->y_min_scanlines = 4;
4437         }
4438
4439         if (apply_memory_bw_wa)
4440                 wp->y_min_scanlines *= 2;
4441
4442         wp->plane_bytes_per_line = wp->width * wp->cpp;
4443         if (wp->y_tiled) {
4444                 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
4445                                            wp->y_min_scanlines, 512);
4446
4447                 if (INTEL_GEN(dev_priv) >= 10)
4448                         interm_pbpl++;
4449
4450                 wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
4451                                                         wp->y_min_scanlines);
4452         } else if (wp->x_tiled && IS_GEN9(dev_priv)) {
4453                 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512);
4454                 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
4455         } else {
4456                 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512) + 1;
4457                 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
4458         }
4459
4460         wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines,
4461                                              wp->plane_blocks_per_line);
4462         wp->linetime_us = fixed16_to_u32_round_up(
4463                                         intel_get_linetime_us(cstate));
4464
4465         return 0;
4466 }
4467
4468 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
4469                                 struct intel_crtc_state *cstate,
4470                                 const struct intel_plane_state *intel_pstate,
4471                                 uint16_t ddb_allocation,
4472                                 int level,
4473                                 const struct skl_wm_params *wp,
4474                                 uint16_t *out_blocks, /* out */
4475                                 uint8_t *out_lines, /* out */
4476                                 bool *enabled /* out */)
4477 {
4478         const struct drm_plane_state *pstate = &intel_pstate->base;
4479         uint32_t latency = dev_priv->wm.skl_latency[level];
4480         uint_fixed_16_16_t method1, method2;
4481         uint_fixed_16_16_t selected_result;
4482         uint32_t res_blocks, res_lines;
4483         struct intel_atomic_state *state =
4484                 to_intel_atomic_state(cstate->base.state);
4485         bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
4486
4487         if (latency == 0 ||
4488             !intel_wm_plane_visible(cstate, intel_pstate)) {
4489                 *enabled = false;
4490                 return 0;
4491         }
4492
4493         /* Display WA #1141: kbl,cfl */
4494         if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
4495             IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) &&
4496             dev_priv->ipc_enabled)
4497                 latency += 4;
4498
4499         if (apply_memory_bw_wa && wp->x_tiled)
4500                 latency += 15;
4501
4502         method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
4503                                  wp->cpp, latency);
4504         method2 = skl_wm_method2(wp->plane_pixel_rate,
4505                                  cstate->base.adjusted_mode.crtc_htotal,
4506                                  latency,
4507                                  wp->plane_blocks_per_line);
4508
4509         if (wp->y_tiled) {
4510                 selected_result = max_fixed16(method2, wp->y_tile_minimum);
4511         } else {
4512                 if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /
4513                      512 < 1) && (wp->plane_bytes_per_line / 512 < 1))
4514                         selected_result = method2;
4515                 else if (ddb_allocation >=
4516                          fixed16_to_u32_round_up(wp->plane_blocks_per_line))
4517                         selected_result = min_fixed16(method1, method2);
4518                 else if (latency >= wp->linetime_us)
4519                         selected_result = min_fixed16(method1, method2);
4520                 else
4521                         selected_result = method1;
4522         }
4523
4524         res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
4525         res_lines = div_round_up_fixed16(selected_result,
4526                                          wp->plane_blocks_per_line);
4527
4528         /* Display WA #1125: skl,bxt,kbl,glk */
4529         if (level == 0 && wp->rc_surface)
4530                 res_blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
4531
4532         /* Display WA #1126: skl,bxt,kbl,glk */
4533         if (level >= 1 && level <= 7) {
4534                 if (wp->y_tiled) {
4535                         res_blocks += fixed16_to_u32_round_up(
4536                                                         wp->y_tile_minimum);
4537                         res_lines += wp->y_min_scanlines;
4538                 } else {
4539                         res_blocks++;
4540                 }
4541         }
4542
4543         if (res_blocks >= ddb_allocation || res_lines > 31) {
4544                 *enabled = false;
4545
4546                 /*
4547                  * If there are no valid level 0 watermarks, then we can't
4548                  * support this display configuration.
4549                  */
4550                 if (level) {
4551                         return 0;
4552                 } else {
4553                         struct drm_plane *plane = pstate->plane;
4554
4555                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
4556                         DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
4557                                       plane->base.id, plane->name,
4558                                       res_blocks, ddb_allocation, res_lines);
4559                         return -EINVAL;
4560                 }
4561         }
4562
4563         *out_blocks = res_blocks;
4564         *out_lines = res_lines;
4565         *enabled = true;
4566
4567         return 0;
4568 }
4569
4570 static int
4571 skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
4572                       struct skl_ddb_allocation *ddb,
4573                       struct intel_crtc_state *cstate,
4574                       const struct intel_plane_state *intel_pstate,
4575                       const struct skl_wm_params *wm_params,
4576                       struct skl_plane_wm *wm)
4577 {
4578         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4579         struct drm_plane *plane = intel_pstate->base.plane;
4580         struct intel_plane *intel_plane = to_intel_plane(plane);
4581         uint16_t ddb_blocks;
4582         enum pipe pipe = intel_crtc->pipe;
4583         int level, max_level = ilk_wm_max_level(dev_priv);
4584         int ret;
4585
4586         if (WARN_ON(!intel_pstate->base.fb))
4587                 return -EINVAL;
4588
4589         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
4590
4591         for (level = 0; level <= max_level; level++) {
4592                 struct skl_wm_level *result = &wm->wm[level];
4593
4594                 ret = skl_compute_plane_wm(dev_priv,
4595                                            cstate,
4596                                            intel_pstate,
4597                                            ddb_blocks,
4598                                            level,
4599                                            wm_params,
4600                                            &result->plane_res_b,
4601                                            &result->plane_res_l,
4602                                            &result->plane_en);
4603                 if (ret)
4604                         return ret;
4605         }
4606
4607         return 0;
4608 }
4609
4610 static uint32_t
4611 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
4612 {
4613         struct drm_atomic_state *state = cstate->base.state;
4614         struct drm_i915_private *dev_priv = to_i915(state->dev);
4615         uint_fixed_16_16_t linetime_us;
4616         uint32_t linetime_wm;
4617
4618         linetime_us = intel_get_linetime_us(cstate);
4619
4620         if (is_fixed16_zero(linetime_us))
4621                 return 0;
4622
4623         linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us));
4624
4625         /* Display WA #1135: bxt:ALL GLK:ALL */
4626         if ((IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) &&
4627             dev_priv->ipc_enabled)
4628                 linetime_wm /= 2;
4629
4630         return linetime_wm;
4631 }
4632
4633 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
4634                                       struct skl_wm_params *wp,
4635                                       struct skl_wm_level *wm_l0,
4636                                       uint16_t ddb_allocation,
4637                                       struct skl_wm_level *trans_wm /* out */)
4638 {
4639         struct drm_device *dev = cstate->base.crtc->dev;
4640         const struct drm_i915_private *dev_priv = to_i915(dev);
4641         uint16_t trans_min, trans_y_tile_min;
4642         const uint16_t trans_amount = 10; /* This is configurable amount */
4643         uint16_t trans_offset_b, res_blocks;
4644
4645         if (!cstate->base.active)
4646                 goto exit;
4647
4648         /* Transition WM are not recommended by HW team for GEN9 */
4649         if (INTEL_GEN(dev_priv) <= 9)
4650                 goto exit;
4651
4652         /* Transition WM don't make any sense if ipc is disabled */
4653         if (!dev_priv->ipc_enabled)
4654                 goto exit;
4655
4656         if (INTEL_GEN(dev_priv) >= 10)
4657                 trans_min = 4;
4658
4659         trans_offset_b = trans_min + trans_amount;
4660
4661         if (wp->y_tiled) {
4662                 trans_y_tile_min = (uint16_t) mul_round_up_u32_fixed16(2,
4663                                                         wp->y_tile_minimum);
4664                 res_blocks = max(wm_l0->plane_res_b, trans_y_tile_min) +
4665                                 trans_offset_b;
4666         } else {
4667                 res_blocks = wm_l0->plane_res_b + trans_offset_b;
4668
4669                 /* WA BUG:1938466 add one block for non y-tile planes */
4670                 if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
4671                         res_blocks += 1;
4672
4673         }
4674
4675         res_blocks += 1;
4676
4677         if (res_blocks < ddb_allocation) {
4678                 trans_wm->plane_res_b = res_blocks;
4679                 trans_wm->plane_en = true;
4680                 return;
4681         }
4682
4683 exit:
4684         trans_wm->plane_en = false;
4685 }
4686
4687 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
4688                              struct skl_ddb_allocation *ddb,
4689                              struct skl_pipe_wm *pipe_wm)
4690 {
4691         struct drm_device *dev = cstate->base.crtc->dev;
4692         struct drm_crtc_state *crtc_state = &cstate->base;
4693         const struct drm_i915_private *dev_priv = to_i915(dev);
4694         struct drm_plane *plane;
4695         const struct drm_plane_state *pstate;
4696         struct skl_plane_wm *wm;
4697         int ret;
4698
4699         /*
4700          * We'll only calculate watermarks for planes that are actually
4701          * enabled, so make sure all other planes are set as disabled.
4702          */
4703         memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
4704
4705         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
4706                 const struct intel_plane_state *intel_pstate =
4707                                                 to_intel_plane_state(pstate);
4708                 enum plane_id plane_id = to_intel_plane(plane)->id;
4709                 struct skl_wm_params wm_params;
4710                 enum pipe pipe = to_intel_crtc(cstate->base.crtc)->pipe;
4711                 uint16_t ddb_blocks;
4712
4713                 wm = &pipe_wm->planes[plane_id];
4714                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
4715                 memset(&wm_params, 0, sizeof(struct skl_wm_params));
4716
4717                 ret = skl_compute_plane_wm_params(dev_priv, cstate,
4718                                                   intel_pstate, &wm_params);
4719                 if (ret)
4720                         return ret;
4721
4722                 ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
4723                                             intel_pstate, &wm_params, wm);
4724                 if (ret)
4725                         return ret;
4726                 skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
4727                                           ddb_blocks, &wm->trans_wm);
4728         }
4729         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
4730
4731         return 0;
4732 }
4733
4734 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
4735                                 i915_reg_t reg,
4736                                 const struct skl_ddb_entry *entry)
4737 {
4738         if (entry->end)
4739                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
4740         else
4741                 I915_WRITE(reg, 0);
4742 }
4743
4744 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
4745                                i915_reg_t reg,
4746                                const struct skl_wm_level *level)
4747 {
4748         uint32_t val = 0;
4749
4750         if (level->plane_en) {
4751                 val |= PLANE_WM_EN;
4752                 val |= level->plane_res_b;
4753                 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
4754         }
4755
4756         I915_WRITE(reg, val);
4757 }
4758
4759 static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
4760                                const struct skl_plane_wm *wm,
4761                                const struct skl_ddb_allocation *ddb,
4762                                enum plane_id plane_id)
4763 {
4764         struct drm_crtc *crtc = &intel_crtc->base;
4765         struct drm_device *dev = crtc->dev;
4766         struct drm_i915_private *dev_priv = to_i915(dev);
4767         int level, max_level = ilk_wm_max_level(dev_priv);
4768         enum pipe pipe = intel_crtc->pipe;
4769
4770         for (level = 0; level <= max_level; level++) {
4771                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
4772                                    &wm->wm[level]);
4773         }
4774         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
4775                            &wm->trans_wm);
4776
4777         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
4778                             &ddb->plane[pipe][plane_id]);
4779         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
4780                             &ddb->y_plane[pipe][plane_id]);
4781 }
4782
4783 static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
4784                                 const struct skl_plane_wm *wm,
4785                                 const struct skl_ddb_allocation *ddb)
4786 {
4787         struct drm_crtc *crtc = &intel_crtc->base;
4788         struct drm_device *dev = crtc->dev;
4789         struct drm_i915_private *dev_priv = to_i915(dev);
4790         int level, max_level = ilk_wm_max_level(dev_priv);
4791         enum pipe pipe = intel_crtc->pipe;
4792
4793         for (level = 0; level <= max_level; level++) {
4794                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
4795                                    &wm->wm[level]);
4796         }
4797         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
4798
4799         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4800                             &ddb->plane[pipe][PLANE_CURSOR]);
4801 }
4802
4803 bool skl_wm_level_equals(const struct skl_wm_level *l1,
4804                          const struct skl_wm_level *l2)
4805 {
4806         if (l1->plane_en != l2->plane_en)
4807                 return false;
4808
4809         /* If both planes aren't enabled, the rest shouldn't matter */
4810         if (!l1->plane_en)
4811                 return true;
4812
4813         return (l1->plane_res_l == l2->plane_res_l &&
4814                 l1->plane_res_b == l2->plane_res_b);
4815 }
4816
4817 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
4818                                            const struct skl_ddb_entry *b)
4819 {
4820         return a->start < b->end && b->start < a->end;
4821 }
4822
4823 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
4824                                  const struct skl_ddb_entry **entries,
4825                                  const struct skl_ddb_entry *ddb,
4826                                  int ignore)
4827 {
4828         enum pipe pipe;
4829
4830         for_each_pipe(dev_priv, pipe) {
4831                 if (pipe != ignore && entries[pipe] &&
4832                     skl_ddb_entries_overlap(ddb, entries[pipe]))
4833                         return true;
4834         }
4835
4836         return false;
4837 }
4838
4839 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
4840                               const struct skl_pipe_wm *old_pipe_wm,
4841                               struct skl_pipe_wm *pipe_wm, /* out */
4842                               struct skl_ddb_allocation *ddb, /* out */
4843                               bool *changed /* out */)
4844 {
4845         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
4846         int ret;
4847
4848         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
4849         if (ret)
4850                 return ret;
4851
4852         if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
4853                 *changed = false;
4854         else
4855                 *changed = true;
4856
4857         return 0;
4858 }
4859
4860 static uint32_t
4861 pipes_modified(struct drm_atomic_state *state)
4862 {
4863         struct drm_crtc *crtc;
4864         struct drm_crtc_state *cstate;
4865         uint32_t i, ret = 0;
4866
4867         for_each_new_crtc_in_state(state, crtc, cstate, i)
4868                 ret |= drm_crtc_mask(crtc);
4869
4870         return ret;
4871 }
4872
4873 static int
4874 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
4875 {
4876         struct drm_atomic_state *state = cstate->base.state;
4877         struct drm_device *dev = state->dev;
4878         struct drm_crtc *crtc = cstate->base.crtc;
4879         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4880         struct drm_i915_private *dev_priv = to_i915(dev);
4881         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4882         struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
4883         struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
4884         struct drm_plane_state *plane_state;
4885         struct drm_plane *plane;
4886         enum pipe pipe = intel_crtc->pipe;
4887
4888         WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
4889
4890         drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
4891                 enum plane_id plane_id = to_intel_plane(plane)->id;
4892
4893                 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
4894                                         &new_ddb->plane[pipe][plane_id]) &&
4895                     skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
4896                                         &new_ddb->y_plane[pipe][plane_id]))
4897                         continue;
4898
4899                 plane_state = drm_atomic_get_plane_state(state, plane);
4900                 if (IS_ERR(plane_state))
4901                         return PTR_ERR(plane_state);
4902         }
4903
4904         return 0;
4905 }
4906
4907 static int
4908 skl_compute_ddb(struct drm_atomic_state *state)
4909 {
4910         struct drm_device *dev = state->dev;
4911         struct drm_i915_private *dev_priv = to_i915(dev);
4912         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4913         struct intel_crtc *intel_crtc;
4914         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
4915         uint32_t realloc_pipes = pipes_modified(state);
4916         int ret;
4917
4918         /*
4919          * If this is our first atomic update following hardware readout,
4920          * we can't trust the DDB that the BIOS programmed for us.  Let's
4921          * pretend that all pipes switched active status so that we'll
4922          * ensure a full DDB recompute.
4923          */
4924         if (dev_priv->wm.distrust_bios_wm) {
4925                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4926                                        state->acquire_ctx);
4927                 if (ret)
4928                         return ret;
4929
4930                 intel_state->active_pipe_changes = ~0;
4931
4932                 /*
4933                  * We usually only initialize intel_state->active_crtcs if we
4934                  * we're doing a modeset; make sure this field is always
4935                  * initialized during the sanitization process that happens
4936                  * on the first commit too.
4937                  */
4938                 if (!intel_state->modeset)
4939                         intel_state->active_crtcs = dev_priv->active_crtcs;
4940         }
4941
4942         /*
4943          * If the modeset changes which CRTC's are active, we need to
4944          * recompute the DDB allocation for *all* active pipes, even
4945          * those that weren't otherwise being modified in any way by this
4946          * atomic commit.  Due to the shrinking of the per-pipe allocations
4947          * when new active CRTC's are added, it's possible for a pipe that
4948          * we were already using and aren't changing at all here to suddenly
4949          * become invalid if its DDB needs exceeds its new allocation.
4950          *
4951          * Note that if we wind up doing a full DDB recompute, we can't let
4952          * any other display updates race with this transaction, so we need
4953          * to grab the lock on *all* CRTC's.
4954          */
4955         if (intel_state->active_pipe_changes) {
4956                 realloc_pipes = ~0;
4957                 intel_state->wm_results.dirty_pipes = ~0;
4958         }
4959
4960         /*
4961          * We're not recomputing for the pipes not included in the commit, so
4962          * make sure we start with the current state.
4963          */
4964         memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4965
4966         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4967                 struct intel_crtc_state *cstate;
4968
4969                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4970                 if (IS_ERR(cstate))
4971                         return PTR_ERR(cstate);
4972
4973                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4974                 if (ret)
4975                         return ret;
4976
4977                 ret = skl_ddb_add_affected_planes(cstate);
4978                 if (ret)
4979                         return ret;
4980         }
4981
4982         return 0;
4983 }
4984
4985 static void
4986 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4987                      struct skl_wm_values *src,
4988                      enum pipe pipe)
4989 {
4990         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4991                sizeof(dst->ddb.y_plane[pipe]));
4992         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4993                sizeof(dst->ddb.plane[pipe]));
4994 }
4995
4996 static void
4997 skl_print_wm_changes(const struct drm_atomic_state *state)
4998 {
4999         const struct drm_device *dev = state->dev;
5000         const struct drm_i915_private *dev_priv = to_i915(dev);
5001         const struct intel_atomic_state *intel_state =
5002                 to_intel_atomic_state(state);
5003         const struct drm_crtc *crtc;
5004         const struct drm_crtc_state *cstate;
5005         const struct intel_plane *intel_plane;
5006         const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
5007         const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
5008         int i;
5009
5010         for_each_new_crtc_in_state(state, crtc, cstate, i) {
5011                 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5012                 enum pipe pipe = intel_crtc->pipe;
5013
5014                 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
5015                         enum plane_id plane_id = intel_plane->id;
5016                         const struct skl_ddb_entry *old, *new;
5017
5018                         old = &old_ddb->plane[pipe][plane_id];
5019                         new = &new_ddb->plane[pipe][plane_id];
5020
5021                         if (skl_ddb_entry_equal(old, new))
5022                                 continue;
5023
5024                         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
5025                                          intel_plane->base.base.id,
5026                                          intel_plane->base.name,
5027                                          old->start, old->end,
5028                                          new->start, new->end);
5029                 }
5030         }
5031 }
5032
5033 static int
5034 skl_compute_wm(struct drm_atomic_state *state)
5035 {
5036         struct drm_crtc *crtc;
5037         struct drm_crtc_state *cstate;
5038         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5039         struct skl_wm_values *results = &intel_state->wm_results;
5040         struct drm_device *dev = state->dev;
5041         struct skl_pipe_wm *pipe_wm;
5042         bool changed = false;
5043         int ret, i;
5044
5045         /*
5046          * When we distrust bios wm we always need to recompute to set the
5047          * expected DDB allocations for each CRTC.
5048          */
5049         if (to_i915(dev)->wm.distrust_bios_wm)
5050                 changed = true;
5051
5052         /*
5053          * If this transaction isn't actually touching any CRTC's, don't
5054          * bother with watermark calculation.  Note that if we pass this
5055          * test, we're guaranteed to hold at least one CRTC state mutex,
5056          * which means we can safely use values like dev_priv->active_crtcs
5057          * since any racing commits that want to update them would need to
5058          * hold _all_ CRTC state mutexes.
5059          */
5060         for_each_new_crtc_in_state(state, crtc, cstate, i)
5061                 changed = true;
5062
5063         if (!changed)
5064                 return 0;
5065
5066         /* Clear all dirty flags */
5067         results->dirty_pipes = 0;
5068
5069         ret = skl_compute_ddb(state);
5070         if (ret)
5071                 return ret;
5072
5073         /*
5074          * Calculate WM's for all pipes that are part of this transaction.
5075          * Note that the DDB allocation above may have added more CRTC's that
5076          * weren't otherwise being modified (and set bits in dirty_pipes) if
5077          * pipe allocations had to change.
5078          *
5079          * FIXME:  Now that we're doing this in the atomic check phase, we
5080          * should allow skl_update_pipe_wm() to return failure in cases where
5081          * no suitable watermark values can be found.
5082          */
5083         for_each_new_crtc_in_state(state, crtc, cstate, i) {
5084                 struct intel_crtc_state *intel_cstate =
5085                         to_intel_crtc_state(cstate);
5086                 const struct skl_pipe_wm *old_pipe_wm =
5087                         &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
5088
5089                 pipe_wm = &intel_cstate->wm.skl.optimal;
5090                 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
5091                                          &results->ddb, &changed);
5092                 if (ret)
5093                         return ret;
5094
5095                 if (changed)
5096                         results->dirty_pipes |= drm_crtc_mask(crtc);
5097
5098                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
5099                         /* This pipe's WM's did not change */
5100                         continue;
5101
5102                 intel_cstate->update_wm_pre = true;
5103         }
5104
5105         skl_print_wm_changes(state);
5106
5107         return 0;
5108 }
5109
5110 static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
5111                                       struct intel_crtc_state *cstate)
5112 {
5113         struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
5114         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5115         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
5116         const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
5117         enum pipe pipe = crtc->pipe;
5118         enum plane_id plane_id;
5119
5120         if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
5121                 return;
5122
5123         I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
5124
5125         for_each_plane_id_on_crtc(crtc, plane_id) {
5126                 if (plane_id != PLANE_CURSOR)
5127                         skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
5128                                            ddb, plane_id);
5129                 else
5130                         skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
5131                                             ddb);
5132         }
5133 }
5134
5135 static void skl_initial_wm(struct intel_atomic_state *state,
5136                            struct intel_crtc_state *cstate)
5137 {
5138         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5139         struct drm_device *dev = intel_crtc->base.dev;
5140         struct drm_i915_private *dev_priv = to_i915(dev);
5141         struct skl_wm_values *results = &state->wm_results;
5142         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
5143         enum pipe pipe = intel_crtc->pipe;
5144
5145         if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
5146                 return;
5147
5148         mutex_lock(&dev_priv->wm.wm_mutex);
5149
5150         if (cstate->base.active_changed)
5151                 skl_atomic_update_crtc_wm(state, cstate);
5152
5153         skl_copy_wm_for_pipe(hw_vals, results, pipe);
5154
5155         mutex_unlock(&dev_priv->wm.wm_mutex);
5156 }
5157
5158 static void ilk_compute_wm_config(struct drm_device *dev,
5159                                   struct intel_wm_config *config)
5160 {
5161         struct intel_crtc *crtc;
5162
5163         /* Compute the currently _active_ config */
5164         for_each_intel_crtc(dev, crtc) {
5165                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
5166
5167                 if (!wm->pipe_enabled)
5168                         continue;
5169
5170                 config->sprites_enabled |= wm->sprites_enabled;
5171                 config->sprites_scaled |= wm->sprites_scaled;
5172                 config->num_pipes_active++;
5173         }
5174 }
5175
5176 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
5177 {
5178         struct drm_device *dev = &dev_priv->drm;
5179         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
5180         struct ilk_wm_maximums max;
5181         struct intel_wm_config config = {};
5182         struct ilk_wm_values results = {};
5183         enum intel_ddb_partitioning partitioning;
5184
5185         ilk_compute_wm_config(dev, &config);
5186
5187         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
5188         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
5189
5190         /* 5/6 split only in single pipe config on IVB+ */
5191         if (INTEL_GEN(dev_priv) >= 7 &&
5192             config.num_pipes_active == 1 && config.sprites_enabled) {
5193                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
5194                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
5195
5196                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
5197         } else {
5198                 best_lp_wm = &lp_wm_1_2;
5199         }
5200
5201         partitioning = (best_lp_wm == &lp_wm_1_2) ?
5202                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
5203
5204         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
5205
5206         ilk_write_wm_values(dev_priv, &results);
5207 }
5208
5209 static void ilk_initial_watermarks(struct intel_atomic_state *state,
5210                                    struct intel_crtc_state *cstate)
5211 {
5212         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
5213         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5214
5215         mutex_lock(&dev_priv->wm.wm_mutex);
5216         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
5217         ilk_program_watermarks(dev_priv);
5218         mutex_unlock(&dev_priv->wm.wm_mutex);
5219 }
5220
5221 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
5222                                     struct intel_crtc_state *cstate)
5223 {
5224         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
5225         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
5226
5227         mutex_lock(&dev_priv->wm.wm_mutex);
5228         if (cstate->wm.need_postvbl_update) {
5229                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
5230                 ilk_program_watermarks(dev_priv);
5231         }
5232         mutex_unlock(&dev_priv->wm.wm_mutex);
5233 }
5234
5235 static inline void skl_wm_level_from_reg_val(uint32_t val,
5236                                              struct skl_wm_level *level)
5237 {
5238         level->plane_en = val & PLANE_WM_EN;
5239         level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
5240         level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
5241                 PLANE_WM_LINES_MASK;
5242 }
5243
5244 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
5245                               struct skl_pipe_wm *out)
5246 {
5247         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5249         enum pipe pipe = intel_crtc->pipe;
5250         int level, max_level;
5251         enum plane_id plane_id;
5252         uint32_t val;
5253
5254         max_level = ilk_wm_max_level(dev_priv);
5255
5256         for_each_plane_id_on_crtc(intel_crtc, plane_id) {
5257                 struct skl_plane_wm *wm = &out->planes[plane_id];
5258
5259                 for (level = 0; level <= max_level; level++) {
5260                         if (plane_id != PLANE_CURSOR)
5261                                 val = I915_READ(PLANE_WM(pipe, plane_id, level));
5262                         else
5263                                 val = I915_READ(CUR_WM(pipe, level));
5264
5265                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
5266                 }
5267
5268                 if (plane_id != PLANE_CURSOR)
5269                         val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
5270                 else
5271                         val = I915_READ(CUR_WM_TRANS(pipe));
5272
5273                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
5274         }
5275
5276         if (!intel_crtc->active)
5277                 return;
5278
5279         out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
5280 }
5281
5282 void skl_wm_get_hw_state(struct drm_device *dev)
5283 {
5284         struct drm_i915_private *dev_priv = to_i915(dev);
5285         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
5286         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
5287         struct drm_crtc *crtc;
5288         struct intel_crtc *intel_crtc;
5289         struct intel_crtc_state *cstate;
5290
5291         skl_ddb_get_hw_state(dev_priv, ddb);
5292         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5293                 intel_crtc = to_intel_crtc(crtc);
5294                 cstate = to_intel_crtc_state(crtc->state);
5295
5296                 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
5297
5298                 if (intel_crtc->active)
5299                         hw->dirty_pipes |= drm_crtc_mask(crtc);
5300         }
5301
5302         if (dev_priv->active_crtcs) {
5303                 /* Fully recompute DDB on first atomic commit */
5304                 dev_priv->wm.distrust_bios_wm = true;
5305         } else {
5306                 /* Easy/common case; just sanitize DDB now if everything off */
5307                 memset(ddb, 0, sizeof(*ddb));
5308         }
5309 }
5310
5311 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
5312 {
5313         struct drm_device *dev = crtc->dev;
5314         struct drm_i915_private *dev_priv = to_i915(dev);
5315         struct ilk_wm_values *hw = &dev_priv->wm.hw;
5316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5317         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
5318         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
5319         enum pipe pipe = intel_crtc->pipe;
5320         static const i915_reg_t wm0_pipe_reg[] = {
5321                 [PIPE_A] = WM0_PIPEA_ILK,
5322                 [PIPE_B] = WM0_PIPEB_ILK,
5323                 [PIPE_C] = WM0_PIPEC_IVB,
5324         };
5325
5326         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
5327         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5328                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
5329
5330         memset(active, 0, sizeof(*active));
5331
5332         active->pipe_enabled = intel_crtc->active;
5333
5334         if (active->pipe_enabled) {
5335                 u32 tmp = hw->wm_pipe[pipe];
5336
5337                 /*
5338                  * For active pipes LP0 watermark is marked as
5339                  * enabled, and LP1+ watermaks as disabled since
5340                  * we can't really reverse compute them in case
5341                  * multiple pipes are active.
5342                  */
5343                 active->wm[0].enable = true;
5344                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
5345                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
5346                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
5347                 active->linetime = hw->wm_linetime[pipe];
5348         } else {
5349                 int level, max_level = ilk_wm_max_level(dev_priv);
5350
5351                 /*
5352                  * For inactive pipes, all watermark levels
5353                  * should be marked as enabled but zeroed,
5354                  * which is what we'd compute them to.
5355                  */
5356                 for (level = 0; level <= max_level; level++)
5357                         active->wm[level].enable = true;
5358         }
5359
5360         intel_crtc->wm.active.ilk = *active;
5361 }
5362
5363 #define _FW_WM(value, plane) \
5364         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
5365 #define _FW_WM_VLV(value, plane) \
5366         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
5367
5368 static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
5369                                struct g4x_wm_values *wm)
5370 {
5371         uint32_t tmp;
5372
5373         tmp = I915_READ(DSPFW1);
5374         wm->sr.plane = _FW_WM(tmp, SR);
5375         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
5376         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
5377         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
5378
5379         tmp = I915_READ(DSPFW2);
5380         wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
5381         wm->sr.fbc = _FW_WM(tmp, FBC_SR);
5382         wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
5383         wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
5384         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
5385         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
5386
5387         tmp = I915_READ(DSPFW3);
5388         wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
5389         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
5390         wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
5391         wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
5392 }
5393
5394 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
5395                                struct vlv_wm_values *wm)
5396 {
5397         enum pipe pipe;
5398         uint32_t tmp;
5399
5400         for_each_pipe(dev_priv, pipe) {
5401                 tmp = I915_READ(VLV_DDL(pipe));
5402
5403                 wm->ddl[pipe].plane[PLANE_PRIMARY] =
5404                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5405                 wm->ddl[pipe].plane[PLANE_CURSOR] =
5406                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5407                 wm->ddl[pipe].plane[PLANE_SPRITE0] =
5408                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5409                 wm->ddl[pipe].plane[PLANE_SPRITE1] =
5410                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
5411         }
5412
5413         tmp = I915_READ(DSPFW1);
5414         wm->sr.plane = _FW_WM(tmp, SR);
5415         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
5416         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
5417         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
5418
5419         tmp = I915_READ(DSPFW2);
5420         wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
5421         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
5422         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
5423
5424         tmp = I915_READ(DSPFW3);
5425         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
5426
5427         if (IS_CHERRYVIEW(dev_priv)) {
5428                 tmp = I915_READ(DSPFW7_CHV);
5429                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
5430                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
5431
5432                 tmp = I915_READ(DSPFW8_CHV);
5433                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
5434                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
5435
5436                 tmp = I915_READ(DSPFW9_CHV);
5437                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
5438                 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
5439
5440                 tmp = I915_READ(DSPHOWM);
5441                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
5442                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
5443                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
5444                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
5445                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
5446                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
5447                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
5448                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
5449                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
5450                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
5451         } else {
5452                 tmp = I915_READ(DSPFW7);
5453                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
5454                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
5455
5456                 tmp = I915_READ(DSPHOWM);
5457                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
5458                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
5459                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
5460                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
5461                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
5462                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
5463                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
5464         }
5465 }
5466
5467 #undef _FW_WM
5468 #undef _FW_WM_VLV
5469
5470 void g4x_wm_get_hw_state(struct drm_device *dev)
5471 {
5472         struct drm_i915_private *dev_priv = to_i915(dev);
5473         struct g4x_wm_values *wm = &dev_priv->wm.g4x;
5474         struct intel_crtc *crtc;
5475
5476         g4x_read_wm_values(dev_priv, wm);
5477
5478         wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
5479
5480         for_each_intel_crtc(dev, crtc) {
5481                 struct intel_crtc_state *crtc_state =
5482                         to_intel_crtc_state(crtc->base.state);
5483                 struct g4x_wm_state *active = &crtc->wm.active.g4x;
5484                 struct g4x_pipe_wm *raw;
5485                 enum pipe pipe = crtc->pipe;
5486                 enum plane_id plane_id;
5487                 int level, max_level;
5488
5489                 active->cxsr = wm->cxsr;
5490                 active->hpll_en = wm->hpll_en;
5491                 active->fbc_en = wm->fbc_en;
5492
5493                 active->sr = wm->sr;
5494                 active->hpll = wm->hpll;
5495
5496                 for_each_plane_id_on_crtc(crtc, plane_id) {
5497                         active->wm.plane[plane_id] =
5498                                 wm->pipe[pipe].plane[plane_id];
5499                 }
5500
5501                 if (wm->cxsr && wm->hpll_en)
5502                         max_level = G4X_WM_LEVEL_HPLL;
5503                 else if (wm->cxsr)
5504                         max_level = G4X_WM_LEVEL_SR;
5505                 else
5506                         max_level = G4X_WM_LEVEL_NORMAL;
5507
5508                 level = G4X_WM_LEVEL_NORMAL;
5509                 raw = &crtc_state->wm.g4x.raw[level];
5510                 for_each_plane_id_on_crtc(crtc, plane_id)
5511                         raw->plane[plane_id] = active->wm.plane[plane_id];
5512
5513                 if (++level > max_level)
5514                         goto out;
5515
5516                 raw = &crtc_state->wm.g4x.raw[level];
5517                 raw->plane[PLANE_PRIMARY] = active->sr.plane;
5518                 raw->plane[PLANE_CURSOR] = active->sr.cursor;
5519                 raw->plane[PLANE_SPRITE0] = 0;
5520                 raw->fbc = active->sr.fbc;
5521
5522                 if (++level > max_level)
5523                         goto out;
5524
5525                 raw = &crtc_state->wm.g4x.raw[level];
5526                 raw->plane[PLANE_PRIMARY] = active->hpll.plane;
5527                 raw->plane[PLANE_CURSOR] = active->hpll.cursor;
5528                 raw->plane[PLANE_SPRITE0] = 0;
5529                 raw->fbc = active->hpll.fbc;
5530
5531         out:
5532                 for_each_plane_id_on_crtc(crtc, plane_id)
5533                         g4x_raw_plane_wm_set(crtc_state, level,
5534                                              plane_id, USHRT_MAX);
5535                 g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
5536
5537                 crtc_state->wm.g4x.optimal = *active;
5538                 crtc_state->wm.g4x.intermediate = *active;
5539
5540                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
5541                               pipe_name(pipe),
5542                               wm->pipe[pipe].plane[PLANE_PRIMARY],
5543                               wm->pipe[pipe].plane[PLANE_CURSOR],
5544                               wm->pipe[pipe].plane[PLANE_SPRITE0]);
5545         }
5546
5547         DRM_DEBUG_KMS("Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
5548                       wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
5549         DRM_DEBUG_KMS("Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
5550                       wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
5551         DRM_DEBUG_KMS("Initial SR=%s HPLL=%s FBC=%s\n",
5552                       yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en));
5553 }
5554
5555 void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
5556 {
5557         struct intel_plane *plane;
5558         struct intel_crtc *crtc;
5559
5560         mutex_lock(&dev_priv->wm.wm_mutex);
5561
5562         for_each_intel_plane(&dev_priv->drm, plane) {
5563                 struct intel_crtc *crtc =
5564                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
5565                 struct intel_crtc_state *crtc_state =
5566                         to_intel_crtc_state(crtc->base.state);
5567                 struct intel_plane_state *plane_state =
5568                         to_intel_plane_state(plane->base.state);
5569                 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
5570                 enum plane_id plane_id = plane->id;
5571                 int level;
5572
5573                 if (plane_state->base.visible)
5574                         continue;
5575
5576                 for (level = 0; level < 3; level++) {
5577                         struct g4x_pipe_wm *raw =
5578                                 &crtc_state->wm.g4x.raw[level];
5579
5580                         raw->plane[plane_id] = 0;
5581                         wm_state->wm.plane[plane_id] = 0;
5582                 }
5583
5584                 if (plane_id == PLANE_PRIMARY) {
5585                         for (level = 0; level < 3; level++) {
5586                                 struct g4x_pipe_wm *raw =
5587                                         &crtc_state->wm.g4x.raw[level];
5588                                 raw->fbc = 0;
5589                         }
5590
5591                         wm_state->sr.fbc = 0;
5592                         wm_state->hpll.fbc = 0;
5593                         wm_state->fbc_en = false;
5594                 }
5595         }
5596
5597         for_each_intel_crtc(&dev_priv->drm, crtc) {
5598                 struct intel_crtc_state *crtc_state =
5599                         to_intel_crtc_state(crtc->base.state);
5600
5601                 crtc_state->wm.g4x.intermediate =
5602                         crtc_state->wm.g4x.optimal;
5603                 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
5604         }
5605
5606         g4x_program_watermarks(dev_priv);
5607
5608         mutex_unlock(&dev_priv->wm.wm_mutex);
5609 }
5610
5611 void vlv_wm_get_hw_state(struct drm_device *dev)
5612 {
5613         struct drm_i915_private *dev_priv = to_i915(dev);
5614         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
5615         struct intel_crtc *crtc;
5616         u32 val;
5617
5618         vlv_read_wm_values(dev_priv, wm);
5619
5620         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
5621         wm->level = VLV_WM_LEVEL_PM2;
5622
5623         if (IS_CHERRYVIEW(dev_priv)) {
5624                 mutex_lock(&dev_priv->pcu_lock);
5625
5626                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5627                 if (val & DSP_MAXFIFO_PM5_ENABLE)
5628                         wm->level = VLV_WM_LEVEL_PM5;
5629
5630                 /*
5631                  * If DDR DVFS is disabled in the BIOS, Punit
5632                  * will never ack the request. So if that happens
5633                  * assume we don't have to enable/disable DDR DVFS
5634                  * dynamically. To test that just set the REQ_ACK
5635                  * bit to poke the Punit, but don't change the
5636                  * HIGH/LOW bits so that we don't actually change
5637                  * the current state.
5638                  */
5639                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
5640                 val |= FORCE_DDR_FREQ_REQ_ACK;
5641                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
5642
5643                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
5644                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
5645                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
5646                                       "assuming DDR DVFS is disabled\n");
5647                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
5648                 } else {
5649                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
5650                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
5651                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
5652                 }
5653
5654                 mutex_unlock(&dev_priv->pcu_lock);
5655         }
5656
5657         for_each_intel_crtc(dev, crtc) {
5658                 struct intel_crtc_state *crtc_state =
5659                         to_intel_crtc_state(crtc->base.state);
5660                 struct vlv_wm_state *active = &crtc->wm.active.vlv;
5661                 const struct vlv_fifo_state *fifo_state =
5662                         &crtc_state->wm.vlv.fifo_state;
5663                 enum pipe pipe = crtc->pipe;
5664                 enum plane_id plane_id;
5665                 int level;
5666
5667                 vlv_get_fifo_size(crtc_state);
5668
5669                 active->num_levels = wm->level + 1;
5670                 active->cxsr = wm->cxsr;
5671
5672                 for (level = 0; level < active->num_levels; level++) {
5673                         struct g4x_pipe_wm *raw =
5674                                 &crtc_state->wm.vlv.raw[level];
5675
5676                         active->sr[level].plane = wm->sr.plane;
5677                         active->sr[level].cursor = wm->sr.cursor;
5678
5679                         for_each_plane_id_on_crtc(crtc, plane_id) {
5680                                 active->wm[level].plane[plane_id] =
5681                                         wm->pipe[pipe].plane[plane_id];
5682
5683                                 raw->plane[plane_id] =
5684                                         vlv_invert_wm_value(active->wm[level].plane[plane_id],
5685                                                             fifo_state->plane[plane_id]);
5686                         }
5687                 }
5688
5689                 for_each_plane_id_on_crtc(crtc, plane_id)
5690                         vlv_raw_plane_wm_set(crtc_state, level,
5691                                              plane_id, USHRT_MAX);
5692                 vlv_invalidate_wms(crtc, active, level);
5693
5694                 crtc_state->wm.vlv.optimal = *active;
5695                 crtc_state->wm.vlv.intermediate = *active;
5696
5697                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
5698                               pipe_name(pipe),
5699                               wm->pipe[pipe].plane[PLANE_PRIMARY],
5700                               wm->pipe[pipe].plane[PLANE_CURSOR],
5701                               wm->pipe[pipe].plane[PLANE_SPRITE0],
5702                               wm->pipe[pipe].plane[PLANE_SPRITE1]);
5703         }
5704
5705         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
5706                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
5707 }
5708
5709 void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
5710 {
5711         struct intel_plane *plane;
5712         struct intel_crtc *crtc;
5713
5714         mutex_lock(&dev_priv->wm.wm_mutex);
5715
5716         for_each_intel_plane(&dev_priv->drm, plane) {
5717                 struct intel_crtc *crtc =
5718                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
5719                 struct intel_crtc_state *crtc_state =
5720                         to_intel_crtc_state(crtc->base.state);
5721                 struct intel_plane_state *plane_state =
5722                         to_intel_plane_state(plane->base.state);
5723                 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
5724                 const struct vlv_fifo_state *fifo_state =
5725                         &crtc_state->wm.vlv.fifo_state;
5726                 enum plane_id plane_id = plane->id;
5727                 int level;
5728
5729                 if (plane_state->base.visible)
5730                         continue;
5731
5732                 for (level = 0; level < wm_state->num_levels; level++) {
5733                         struct g4x_pipe_wm *raw =
5734                                 &crtc_state->wm.vlv.raw[level];
5735
5736                         raw->plane[plane_id] = 0;
5737
5738                         wm_state->wm[level].plane[plane_id] =
5739                                 vlv_invert_wm_value(raw->plane[plane_id],
5740                                                     fifo_state->plane[plane_id]);
5741                 }
5742         }
5743
5744         for_each_intel_crtc(&dev_priv->drm, crtc) {
5745                 struct intel_crtc_state *crtc_state =
5746                         to_intel_crtc_state(crtc->base.state);
5747
5748                 crtc_state->wm.vlv.intermediate =
5749                         crtc_state->wm.vlv.optimal;
5750                 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
5751         }
5752
5753         vlv_program_watermarks(dev_priv);
5754
5755         mutex_unlock(&dev_priv->wm.wm_mutex);
5756 }
5757
5758 void ilk_wm_get_hw_state(struct drm_device *dev)
5759 {
5760         struct drm_i915_private *dev_priv = to_i915(dev);
5761         struct ilk_wm_values *hw = &dev_priv->wm.hw;
5762         struct drm_crtc *crtc;
5763
5764         for_each_crtc(dev, crtc)
5765                 ilk_pipe_wm_get_hw_state(crtc);
5766
5767         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
5768         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
5769         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
5770
5771         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
5772         if (INTEL_GEN(dev_priv) >= 7) {
5773                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
5774                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
5775         }
5776
5777         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5778                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
5779                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
5780         else if (IS_IVYBRIDGE(dev_priv))
5781                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
5782                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
5783
5784         hw->enable_fbc_wm =
5785                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
5786 }
5787
5788 /**
5789  * intel_update_watermarks - update FIFO watermark values based on current modes
5790  *
5791  * Calculate watermark values for the various WM regs based on current mode
5792  * and plane configuration.
5793  *
5794  * There are several cases to deal with here:
5795  *   - normal (i.e. non-self-refresh)
5796  *   - self-refresh (SR) mode
5797  *   - lines are large relative to FIFO size (buffer can hold up to 2)
5798  *   - lines are small relative to FIFO size (buffer can hold more than 2
5799  *     lines), so need to account for TLB latency
5800  *
5801  *   The normal calculation is:
5802  *     watermark = dotclock * bytes per pixel * latency
5803  *   where latency is platform & configuration dependent (we assume pessimal
5804  *   values here).
5805  *
5806  *   The SR calculation is:
5807  *     watermark = (trunc(latency/line time)+1) * surface width *
5808  *       bytes per pixel
5809  *   where
5810  *     line time = htotal / dotclock
5811  *     surface width = hdisplay for normal plane and 64 for cursor
5812  *   and latency is assumed to be high, as above.
5813  *
5814  * The final value programmed to the register should always be rounded up,
5815  * and include an extra 2 entries to account for clock crossings.
5816  *
5817  * We don't use the sprite, so we can ignore that.  And on Crestline we have
5818  * to set the non-SR watermarks to 8.
5819  */
5820 void intel_update_watermarks(struct intel_crtc *crtc)
5821 {
5822         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5823
5824         if (dev_priv->display.update_wm)
5825                 dev_priv->display.update_wm(crtc);
5826 }
5827
5828 void intel_enable_ipc(struct drm_i915_private *dev_priv)
5829 {
5830         u32 val;
5831
5832         /* Display WA #0477 WaDisableIPC: skl */
5833         if (IS_SKYLAKE(dev_priv)) {
5834                 dev_priv->ipc_enabled = false;
5835                 return;
5836         }
5837
5838         val = I915_READ(DISP_ARB_CTL2);
5839
5840         if (dev_priv->ipc_enabled)
5841                 val |= DISP_IPC_ENABLE;
5842         else
5843                 val &= ~DISP_IPC_ENABLE;
5844
5845         I915_WRITE(DISP_ARB_CTL2, val);
5846 }
5847
5848 void intel_init_ipc(struct drm_i915_private *dev_priv)
5849 {
5850         dev_priv->ipc_enabled = false;
5851         if (!HAS_IPC(dev_priv))
5852                 return;
5853
5854         dev_priv->ipc_enabled = true;
5855         intel_enable_ipc(dev_priv);
5856 }
5857
5858 /*
5859  * Lock protecting IPS related data structures
5860  */
5861 DEFINE_SPINLOCK(mchdev_lock);
5862
5863 /* Global for IPS driver to get at the current i915 device. Protected by
5864  * mchdev_lock. */
5865 static struct drm_i915_private *i915_mch_dev;
5866
5867 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
5868 {
5869         u16 rgvswctl;
5870
5871         lockdep_assert_held(&mchdev_lock);
5872
5873         rgvswctl = I915_READ16(MEMSWCTL);
5874         if (rgvswctl & MEMCTL_CMD_STS) {
5875                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5876                 return false; /* still busy with another command */
5877         }
5878
5879         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5880                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5881         I915_WRITE16(MEMSWCTL, rgvswctl);
5882         POSTING_READ16(MEMSWCTL);
5883
5884         rgvswctl |= MEMCTL_CMD_STS;
5885         I915_WRITE16(MEMSWCTL, rgvswctl);
5886
5887         return true;
5888 }
5889
5890 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
5891 {
5892         u32 rgvmodectl;
5893         u8 fmax, fmin, fstart, vstart;
5894
5895         spin_lock_irq(&mchdev_lock);
5896
5897         rgvmodectl = I915_READ(MEMMODECTL);
5898
5899         /* Enable temp reporting */
5900         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5901         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5902
5903         /* 100ms RC evaluation intervals */
5904         I915_WRITE(RCUPEI, 100000);
5905         I915_WRITE(RCDNEI, 100000);
5906
5907         /* Set max/min thresholds to 90ms and 80ms respectively */
5908         I915_WRITE(RCBMAXAVG, 90000);
5909         I915_WRITE(RCBMINAVG, 80000);
5910
5911         I915_WRITE(MEMIHYST, 1);
5912
5913         /* Set up min, max, and cur for interrupt handling */
5914         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5915         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5916         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5917                 MEMMODE_FSTART_SHIFT;
5918
5919         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
5920                 PXVFREQ_PX_SHIFT;
5921
5922         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
5923         dev_priv->ips.fstart = fstart;
5924
5925         dev_priv->ips.max_delay = fstart;
5926         dev_priv->ips.min_delay = fmin;
5927         dev_priv->ips.cur_delay = fstart;
5928
5929         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5930                          fmax, fmin, fstart);
5931
5932         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5933
5934         /*
5935          * Interrupts will be enabled in ironlake_irq_postinstall
5936          */
5937
5938         I915_WRITE(VIDSTART, vstart);
5939         POSTING_READ(VIDSTART);
5940
5941         rgvmodectl |= MEMMODE_SWMODE_EN;
5942         I915_WRITE(MEMMODECTL, rgvmodectl);
5943
5944         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5945                 DRM_ERROR("stuck trying to change perf mode\n");
5946         mdelay(1);
5947
5948         ironlake_set_drps(dev_priv, fstart);
5949
5950         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
5951                 I915_READ(DDREC) + I915_READ(CSIEC);
5952         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
5953         dev_priv->ips.last_count2 = I915_READ(GFXEC);
5954         dev_priv->ips.last_time2 = ktime_get_raw_ns();
5955
5956         spin_unlock_irq(&mchdev_lock);
5957 }
5958
5959 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
5960 {
5961         u16 rgvswctl;
5962
5963         spin_lock_irq(&mchdev_lock);
5964
5965         rgvswctl = I915_READ16(MEMSWCTL);
5966
5967         /* Ack interrupts, disable EFC interrupt */
5968         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5969         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5970         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5971         I915_WRITE(DEIIR, DE_PCU_EVENT);
5972         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5973
5974         /* Go back to the starting frequency */
5975         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
5976         mdelay(1);
5977         rgvswctl |= MEMCTL_CMD_STS;
5978         I915_WRITE(MEMSWCTL, rgvswctl);
5979         mdelay(1);
5980
5981         spin_unlock_irq(&mchdev_lock);
5982 }
5983
5984 /* There's a funny hw issue where the hw returns all 0 when reading from
5985  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
5986  * ourselves, instead of doing a rmw cycle (which might result in us clearing
5987  * all limits and the gpu stuck at whatever frequency it is at atm).
5988  */
5989 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
5990 {
5991         struct intel_rps *rps = &dev_priv->gt_pm.rps;
5992         u32 limits;
5993
5994         /* Only set the down limit when we've reached the lowest level to avoid
5995          * getting more interrupts, otherwise leave this clear. This prevents a
5996          * race in the hw when coming out of rc6: There's a tiny window where
5997          * the hw runs at the minimal clock before selecting the desired
5998          * frequency, if the down threshold expires in that window we will not
5999          * receive a down interrupt. */
6000         if (INTEL_GEN(dev_priv) >= 9) {
6001                 limits = (rps->max_freq_softlimit) << 23;
6002                 if (val <= rps->min_freq_softlimit)
6003                         limits |= (rps->min_freq_softlimit) << 14;
6004         } else {
6005                 limits = rps->max_freq_softlimit << 24;
6006                 if (val <= rps->min_freq_softlimit)
6007                         limits |= rps->min_freq_softlimit << 16;
6008         }
6009
6010         return limits;
6011 }
6012
6013 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
6014 {
6015         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6016         int new_power;
6017         u32 threshold_up = 0, threshold_down = 0; /* in % */
6018         u32 ei_up = 0, ei_down = 0;
6019
6020         new_power = rps->power;
6021         switch (rps->power) {
6022         case LOW_POWER:
6023                 if (val > rps->efficient_freq + 1 &&
6024                     val > rps->cur_freq)
6025                         new_power = BETWEEN;
6026                 break;
6027
6028         case BETWEEN:
6029                 if (val <= rps->efficient_freq &&
6030                     val < rps->cur_freq)
6031                         new_power = LOW_POWER;
6032                 else if (val >= rps->rp0_freq &&
6033                          val > rps->cur_freq)
6034                         new_power = HIGH_POWER;
6035                 break;
6036
6037         case HIGH_POWER:
6038                 if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 &&
6039                     val < rps->cur_freq)
6040                         new_power = BETWEEN;
6041                 break;
6042         }
6043         /* Max/min bins are special */
6044         if (val <= rps->min_freq_softlimit)
6045                 new_power = LOW_POWER;
6046         if (val >= rps->max_freq_softlimit)
6047                 new_power = HIGH_POWER;
6048         if (new_power == rps->power)
6049                 return;
6050
6051         /* Note the units here are not exactly 1us, but 1280ns. */
6052         switch (new_power) {
6053         case LOW_POWER:
6054                 /* Upclock if more than 95% busy over 16ms */
6055                 ei_up = 16000;
6056                 threshold_up = 95;
6057
6058                 /* Downclock if less than 85% busy over 32ms */
6059                 ei_down = 32000;
6060                 threshold_down = 85;
6061                 break;
6062
6063         case BETWEEN:
6064                 /* Upclock if more than 90% busy over 13ms */
6065                 ei_up = 13000;
6066                 threshold_up = 90;
6067
6068                 /* Downclock if less than 75% busy over 32ms */
6069                 ei_down = 32000;
6070                 threshold_down = 75;
6071                 break;
6072
6073         case HIGH_POWER:
6074                 /* Upclock if more than 85% busy over 10ms */
6075                 ei_up = 10000;
6076                 threshold_up = 85;
6077
6078                 /* Downclock if less than 60% busy over 32ms */
6079                 ei_down = 32000;
6080                 threshold_down = 60;
6081                 break;
6082         }
6083
6084         /* When byt can survive without system hang with dynamic
6085          * sw freq adjustments, this restriction can be lifted.
6086          */
6087         if (IS_VALLEYVIEW(dev_priv))
6088                 goto skip_hw_write;
6089
6090         I915_WRITE(GEN6_RP_UP_EI,
6091                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
6092         I915_WRITE(GEN6_RP_UP_THRESHOLD,
6093                    GT_INTERVAL_FROM_US(dev_priv,
6094                                        ei_up * threshold_up / 100));
6095
6096         I915_WRITE(GEN6_RP_DOWN_EI,
6097                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
6098         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
6099                    GT_INTERVAL_FROM_US(dev_priv,
6100                                        ei_down * threshold_down / 100));
6101
6102         I915_WRITE(GEN6_RP_CONTROL,
6103                    GEN6_RP_MEDIA_TURBO |
6104                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6105                    GEN6_RP_MEDIA_IS_GFX |
6106                    GEN6_RP_ENABLE |
6107                    GEN6_RP_UP_BUSY_AVG |
6108                    GEN6_RP_DOWN_IDLE_AVG);
6109
6110 skip_hw_write:
6111         rps->power = new_power;
6112         rps->up_threshold = threshold_up;
6113         rps->down_threshold = threshold_down;
6114         rps->last_adj = 0;
6115 }
6116
6117 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
6118 {
6119         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6120         u32 mask = 0;
6121
6122         /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
6123         if (val > rps->min_freq_softlimit)
6124                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
6125         if (val < rps->max_freq_softlimit)
6126                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
6127
6128         mask &= dev_priv->pm_rps_events;
6129
6130         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
6131 }
6132
6133 /* gen6_set_rps is called to update the frequency request, but should also be
6134  * called when the range (min_delay and max_delay) is modified so that we can
6135  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
6136 static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
6137 {
6138         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6139
6140         /* min/max delay may still have been modified so be sure to
6141          * write the limits value.
6142          */
6143         if (val != rps->cur_freq) {
6144                 gen6_set_rps_thresholds(dev_priv, val);
6145
6146                 if (INTEL_GEN(dev_priv) >= 9)
6147                         I915_WRITE(GEN6_RPNSWREQ,
6148                                    GEN9_FREQUENCY(val));
6149                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6150                         I915_WRITE(GEN6_RPNSWREQ,
6151                                    HSW_FREQUENCY(val));
6152                 else
6153                         I915_WRITE(GEN6_RPNSWREQ,
6154                                    GEN6_FREQUENCY(val) |
6155                                    GEN6_OFFSET(0) |
6156                                    GEN6_AGGRESSIVE_TURBO);
6157         }
6158
6159         /* Make sure we continue to get interrupts
6160          * until we hit the minimum or maximum frequencies.
6161          */
6162         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
6163         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
6164
6165         rps->cur_freq = val;
6166         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
6167
6168         return 0;
6169 }
6170
6171 static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
6172 {
6173         int err;
6174
6175         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
6176                       "Odd GPU freq value\n"))
6177                 val &= ~1;
6178
6179         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
6180
6181         if (val != dev_priv->gt_pm.rps.cur_freq) {
6182                 err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
6183                 if (err)
6184                         return err;
6185
6186                 gen6_set_rps_thresholds(dev_priv, val);
6187         }
6188
6189         dev_priv->gt_pm.rps.cur_freq = val;
6190         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
6191
6192         return 0;
6193 }
6194
6195 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
6196  *
6197  * * If Gfx is Idle, then
6198  * 1. Forcewake Media well.
6199  * 2. Request idle freq.
6200  * 3. Release Forcewake of Media well.
6201 */
6202 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
6203 {
6204         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6205         u32 val = rps->idle_freq;
6206         int err;
6207
6208         if (rps->cur_freq <= val)
6209                 return;
6210
6211         /* The punit delays the write of the frequency and voltage until it
6212          * determines the GPU is awake. During normal usage we don't want to
6213          * waste power changing the frequency if the GPU is sleeping (rc6).
6214          * However, the GPU and driver is now idle and we do not want to delay
6215          * switching to minimum voltage (reducing power whilst idle) as we do
6216          * not expect to be woken in the near future and so must flush the
6217          * change by waking the device.
6218          *
6219          * We choose to take the media powerwell (either would do to trick the
6220          * punit into committing the voltage change) as that takes a lot less
6221          * power than the render powerwell.
6222          */
6223         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
6224         err = valleyview_set_rps(dev_priv, val);
6225         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
6226
6227         if (err)
6228                 DRM_ERROR("Failed to set RPS for idle\n");
6229 }
6230
6231 void gen6_rps_busy(struct drm_i915_private *dev_priv)
6232 {
6233         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6234
6235         mutex_lock(&dev_priv->pcu_lock);
6236         if (rps->enabled) {
6237                 u8 freq;
6238
6239                 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
6240                         gen6_rps_reset_ei(dev_priv);
6241                 I915_WRITE(GEN6_PMINTRMSK,
6242                            gen6_rps_pm_mask(dev_priv, rps->cur_freq));
6243
6244                 gen6_enable_rps_interrupts(dev_priv);
6245
6246                 /* Use the user's desired frequency as a guide, but for better
6247                  * performance, jump directly to RPe as our starting frequency.
6248                  */
6249                 freq = max(rps->cur_freq,
6250                            rps->efficient_freq);
6251
6252                 if (intel_set_rps(dev_priv,
6253                                   clamp(freq,
6254                                         rps->min_freq_softlimit,
6255                                         rps->max_freq_softlimit)))
6256                         DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
6257         }
6258         mutex_unlock(&dev_priv->pcu_lock);
6259 }
6260
6261 void gen6_rps_idle(struct drm_i915_private *dev_priv)
6262 {
6263         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6264
6265         /* Flush our bottom-half so that it does not race with us
6266          * setting the idle frequency and so that it is bounded by
6267          * our rpm wakeref. And then disable the interrupts to stop any
6268          * futher RPS reclocking whilst we are asleep.
6269          */
6270         gen6_disable_rps_interrupts(dev_priv);
6271
6272         mutex_lock(&dev_priv->pcu_lock);
6273         if (rps->enabled) {
6274                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6275                         vlv_set_rps_idle(dev_priv);
6276                 else
6277                         gen6_set_rps(dev_priv, rps->idle_freq);
6278                 rps->last_adj = 0;
6279                 I915_WRITE(GEN6_PMINTRMSK,
6280                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
6281         }
6282         mutex_unlock(&dev_priv->pcu_lock);
6283 }
6284
6285 void gen6_rps_boost(struct drm_i915_gem_request *rq,
6286                     struct intel_rps_client *rps_client)
6287 {
6288         struct intel_rps *rps = &rq->i915->gt_pm.rps;
6289         unsigned long flags;
6290         bool boost;
6291
6292         /* This is intentionally racy! We peek at the state here, then
6293          * validate inside the RPS worker.
6294          */
6295         if (!rps->enabled)
6296                 return;
6297
6298         boost = false;
6299         spin_lock_irqsave(&rq->lock, flags);
6300         if (!rq->waitboost && !i915_gem_request_completed(rq)) {
6301                 atomic_inc(&rps->num_waiters);
6302                 rq->waitboost = true;
6303                 boost = true;
6304         }
6305         spin_unlock_irqrestore(&rq->lock, flags);
6306         if (!boost)
6307                 return;
6308
6309         if (READ_ONCE(rps->cur_freq) < rps->boost_freq)
6310                 schedule_work(&rps->work);
6311
6312         atomic_inc(rps_client ? &rps_client->boosts : &rps->boosts);
6313 }
6314
6315 int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
6316 {
6317         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6318         int err;
6319
6320         lockdep_assert_held(&dev_priv->pcu_lock);
6321         GEM_BUG_ON(val > rps->max_freq);
6322         GEM_BUG_ON(val < rps->min_freq);
6323
6324         if (!rps->enabled) {
6325                 rps->cur_freq = val;
6326                 return 0;
6327         }
6328
6329         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6330                 err = valleyview_set_rps(dev_priv, val);
6331         else
6332                 err = gen6_set_rps(dev_priv, val);
6333
6334         return err;
6335 }
6336
6337 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
6338 {
6339         I915_WRITE(GEN6_RC_CONTROL, 0);
6340         I915_WRITE(GEN9_PG_ENABLE, 0);
6341 }
6342
6343 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
6344 {
6345         I915_WRITE(GEN6_RP_CONTROL, 0);
6346 }
6347
6348 static void gen6_disable_rc6(struct drm_i915_private *dev_priv)
6349 {
6350         I915_WRITE(GEN6_RC_CONTROL, 0);
6351 }
6352
6353 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
6354 {
6355         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6356         I915_WRITE(GEN6_RP_CONTROL, 0);
6357 }
6358
6359 static void cherryview_disable_rc6(struct drm_i915_private *dev_priv)
6360 {
6361         I915_WRITE(GEN6_RC_CONTROL, 0);
6362 }
6363
6364 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
6365 {
6366         I915_WRITE(GEN6_RP_CONTROL, 0);
6367 }
6368
6369 static void valleyview_disable_rc6(struct drm_i915_private *dev_priv)
6370 {
6371         /* We're doing forcewake before Disabling RC6,
6372          * This what the BIOS expects when going into suspend */
6373         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6374
6375         I915_WRITE(GEN6_RC_CONTROL, 0);
6376
6377         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6378 }
6379
6380 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
6381 {
6382         I915_WRITE(GEN6_RP_CONTROL, 0);
6383 }
6384
6385 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
6386 {
6387         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6388                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
6389                         mode = GEN6_RC_CTL_RC6_ENABLE;
6390                 else
6391                         mode = 0;
6392         }
6393         if (HAS_RC6p(dev_priv))
6394                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
6395                                  "RC6 %s RC6p %s RC6pp %s\n",
6396                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
6397                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
6398                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
6399
6400         else
6401                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
6402                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
6403 }
6404
6405 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
6406 {
6407         struct i915_ggtt *ggtt = &dev_priv->ggtt;
6408         bool enable_rc6 = true;
6409         unsigned long rc6_ctx_base;
6410         u32 rc_ctl;
6411         int rc_sw_target;
6412
6413         rc_ctl = I915_READ(GEN6_RC_CONTROL);
6414         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
6415                        RC_SW_TARGET_STATE_SHIFT;
6416         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
6417                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
6418                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
6419                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
6420                          rc_sw_target);
6421
6422         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
6423                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
6424                 enable_rc6 = false;
6425         }
6426
6427         /*
6428          * The exact context size is not known for BXT, so assume a page size
6429          * for this check.
6430          */
6431         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
6432         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
6433               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
6434                                         ggtt->stolen_reserved_size))) {
6435                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
6436                 enable_rc6 = false;
6437         }
6438
6439         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
6440               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
6441               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
6442               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
6443                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
6444                 enable_rc6 = false;
6445         }
6446
6447         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
6448             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
6449             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
6450                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
6451                 enable_rc6 = false;
6452         }
6453
6454         if (!I915_READ(GEN6_GFXPAUSE)) {
6455                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
6456                 enable_rc6 = false;
6457         }
6458
6459         if (!I915_READ(GEN8_MISC_CTRL0)) {
6460                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
6461                 enable_rc6 = false;
6462         }
6463
6464         return enable_rc6;
6465 }
6466
6467 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
6468 {
6469         /* No RC6 before Ironlake and code is gone for ilk. */
6470         if (INTEL_INFO(dev_priv)->gen < 6)
6471                 return 0;
6472
6473         if (!enable_rc6)
6474                 return 0;
6475
6476         if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
6477                 DRM_INFO("RC6 disabled by BIOS\n");
6478                 return 0;
6479         }
6480
6481         /* Respect the kernel parameter if it is set */
6482         if (enable_rc6 >= 0) {
6483                 int mask;
6484
6485                 if (HAS_RC6p(dev_priv))
6486                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
6487                                INTEL_RC6pp_ENABLE;
6488                 else
6489                         mask = INTEL_RC6_ENABLE;
6490
6491                 if ((enable_rc6 & mask) != enable_rc6)
6492                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
6493                                          "(requested %d, valid %d)\n",
6494                                          enable_rc6 & mask, enable_rc6, mask);
6495
6496                 return enable_rc6 & mask;
6497         }
6498
6499         if (IS_IVYBRIDGE(dev_priv))
6500                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
6501
6502         return INTEL_RC6_ENABLE;
6503 }
6504
6505 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
6506 {
6507         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6508
6509         /* All of these values are in units of 50MHz */
6510
6511         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
6512         if (IS_GEN9_LP(dev_priv)) {
6513                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
6514                 rps->rp0_freq = (rp_state_cap >> 16) & 0xff;
6515                 rps->rp1_freq = (rp_state_cap >>  8) & 0xff;
6516                 rps->min_freq = (rp_state_cap >>  0) & 0xff;
6517         } else {
6518                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6519                 rps->rp0_freq = (rp_state_cap >>  0) & 0xff;
6520                 rps->rp1_freq = (rp_state_cap >>  8) & 0xff;
6521                 rps->min_freq = (rp_state_cap >> 16) & 0xff;
6522         }
6523         /* hw_max = RP0 until we check for overclocking */
6524         rps->max_freq = rps->rp0_freq;
6525
6526         rps->efficient_freq = rps->rp1_freq;
6527         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
6528             IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6529                 u32 ddcc_status = 0;
6530
6531                 if (sandybridge_pcode_read(dev_priv,
6532                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
6533                                            &ddcc_status) == 0)
6534                         rps->efficient_freq =
6535                                 clamp_t(u8,
6536                                         ((ddcc_status >> 8) & 0xff),
6537                                         rps->min_freq,
6538                                         rps->max_freq);
6539         }
6540
6541         if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6542                 /* Store the frequency values in 16.66 MHZ units, which is
6543                  * the natural hardware unit for SKL
6544                  */
6545                 rps->rp0_freq *= GEN9_FREQ_SCALER;
6546                 rps->rp1_freq *= GEN9_FREQ_SCALER;
6547                 rps->min_freq *= GEN9_FREQ_SCALER;
6548                 rps->max_freq *= GEN9_FREQ_SCALER;
6549                 rps->efficient_freq *= GEN9_FREQ_SCALER;
6550         }
6551 }
6552
6553 static void reset_rps(struct drm_i915_private *dev_priv,
6554                       int (*set)(struct drm_i915_private *, u8))
6555 {
6556         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6557         u8 freq = rps->cur_freq;
6558
6559         /* force a reset */
6560         rps->power = -1;
6561         rps->cur_freq = -1;
6562
6563         if (set(dev_priv, freq))
6564                 DRM_ERROR("Failed to reset RPS to initial values\n");
6565 }
6566
6567 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
6568 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
6569 {
6570         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6571
6572         /* Program defaults and thresholds for RPS*/
6573         I915_WRITE(GEN6_RC_VIDEO_FREQ,
6574                 GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq));
6575
6576         /* 1 second timeout*/
6577         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
6578                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
6579
6580         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
6581
6582         /* Leaning on the below call to gen6_set_rps to program/setup the
6583          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
6584          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
6585         reset_rps(dev_priv, gen6_set_rps);
6586
6587         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6588 }
6589
6590 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
6591 {
6592         struct intel_engine_cs *engine;
6593         enum intel_engine_id id;
6594         u32 rc6_mode, rc6_mask = 0;
6595
6596         /* 1a: Software RC state - RC0 */
6597         I915_WRITE(GEN6_RC_STATE, 0);
6598
6599         /* 1b: Get forcewake during program sequence. Although the driver
6600          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6601         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6602
6603         /* 2a: Disable RC states. */
6604         I915_WRITE(GEN6_RC_CONTROL, 0);
6605
6606         /* 2b: Program RC6 thresholds.*/
6607
6608         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
6609         if (IS_SKYLAKE(dev_priv))
6610                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
6611         else
6612                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
6613         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6614         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6615         for_each_engine(engine, dev_priv, id)
6616                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6617
6618         if (HAS_GUC(dev_priv))
6619                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
6620
6621         I915_WRITE(GEN6_RC_SLEEP, 0);
6622
6623         /* 2c: Program Coarse Power Gating Policies. */
6624         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
6625         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
6626
6627         /* 3a: Enable RC6 */
6628         if (intel_rc6_enabled() & INTEL_RC6_ENABLE)
6629                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
6630         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
6631         I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
6632
6633         /* WaRsUseTimeoutMode:cnl (pre-prod) */
6634         if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_C0))
6635                 rc6_mode = GEN7_RC_CTL_TO_MODE;
6636         else
6637                 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
6638
6639         I915_WRITE(GEN6_RC_CONTROL,
6640                    GEN6_RC_CTL_HW_ENABLE | rc6_mode | rc6_mask);
6641
6642         /*
6643          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
6644          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
6645          */
6646         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
6647                 I915_WRITE(GEN9_PG_ENABLE, 0);
6648         else
6649                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
6650                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
6651
6652         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6653 }
6654
6655 static void gen8_enable_rc6(struct drm_i915_private *dev_priv)
6656 {
6657         struct intel_engine_cs *engine;
6658         enum intel_engine_id id;
6659         uint32_t rc6_mask = 0;
6660
6661         /* 1a: Software RC state - RC0 */
6662         I915_WRITE(GEN6_RC_STATE, 0);
6663
6664         /* 1b: Get forcewake during program sequence. Although the driver
6665          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6666         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6667
6668         /* 2a: Disable RC states. */
6669         I915_WRITE(GEN6_RC_CONTROL, 0);
6670
6671         /* 2b: Program RC6 thresholds.*/
6672         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6673         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6674         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6675         for_each_engine(engine, dev_priv, id)
6676                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6677         I915_WRITE(GEN6_RC_SLEEP, 0);
6678         I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
6679
6680         /* 3: Enable RC6 */
6681         if (intel_rc6_enabled() & INTEL_RC6_ENABLE)
6682                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
6683         intel_print_rc6_info(dev_priv, rc6_mask);
6684
6685         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
6686                         GEN7_RC_CTL_TO_MODE |
6687                         rc6_mask);
6688
6689         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6690 }
6691
6692 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6693 {
6694         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6695
6696         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6697
6698         /* 1 Program defaults and thresholds for RPS*/
6699         I915_WRITE(GEN6_RPNSWREQ,
6700                    HSW_FREQUENCY(rps->rp1_freq));
6701         I915_WRITE(GEN6_RC_VIDEO_FREQ,
6702                    HSW_FREQUENCY(rps->rp1_freq));
6703         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
6704         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
6705
6706         /* Docs recommend 900MHz, and 300 MHz respectively */
6707         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6708                    rps->max_freq_softlimit << 24 |
6709                    rps->min_freq_softlimit << 16);
6710
6711         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
6712         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
6713         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
6714         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
6715
6716         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6717
6718         /* 2: Enable RPS */
6719         I915_WRITE(GEN6_RP_CONTROL,
6720                    GEN6_RP_MEDIA_TURBO |
6721                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6722                    GEN6_RP_MEDIA_IS_GFX |
6723                    GEN6_RP_ENABLE |
6724                    GEN6_RP_UP_BUSY_AVG |
6725                    GEN6_RP_DOWN_IDLE_AVG);
6726
6727         reset_rps(dev_priv, gen6_set_rps);
6728
6729         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6730 }
6731
6732 static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
6733 {
6734         struct intel_engine_cs *engine;
6735         enum intel_engine_id id;
6736         u32 rc6vids, rc6_mask = 0;
6737         u32 gtfifodbg;
6738         int rc6_mode;
6739         int ret;
6740
6741         I915_WRITE(GEN6_RC_STATE, 0);
6742
6743         /* Clear the DBG now so we don't confuse earlier errors */
6744         gtfifodbg = I915_READ(GTFIFODBG);
6745         if (gtfifodbg) {
6746                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
6747                 I915_WRITE(GTFIFODBG, gtfifodbg);
6748         }
6749
6750         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6751
6752         /* disable the counters and set deterministic thresholds */
6753         I915_WRITE(GEN6_RC_CONTROL, 0);
6754
6755         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6756         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6757         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6758         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6759         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6760
6761         for_each_engine(engine, dev_priv, id)
6762                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6763
6764         I915_WRITE(GEN6_RC_SLEEP, 0);
6765         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6766         if (IS_IVYBRIDGE(dev_priv))
6767                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
6768         else
6769                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6770         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
6771         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6772
6773         /* Check if we are enabling RC6 */
6774         rc6_mode = intel_rc6_enabled();
6775         if (rc6_mode & INTEL_RC6_ENABLE)
6776                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
6777
6778         /* We don't use those on Haswell */
6779         if (!IS_HASWELL(dev_priv)) {
6780                 if (rc6_mode & INTEL_RC6p_ENABLE)
6781                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
6782
6783                 if (rc6_mode & INTEL_RC6pp_ENABLE)
6784                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
6785         }
6786
6787         intel_print_rc6_info(dev_priv, rc6_mask);
6788
6789         I915_WRITE(GEN6_RC_CONTROL,
6790                    rc6_mask |
6791                    GEN6_RC_CTL_EI_MODE(1) |
6792                    GEN6_RC_CTL_HW_ENABLE);
6793
6794         rc6vids = 0;
6795         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
6796         if (IS_GEN6(dev_priv) && ret) {
6797                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
6798         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
6799                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
6800                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
6801                 rc6vids &= 0xffff00;
6802                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
6803                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
6804                 if (ret)
6805                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
6806         }
6807
6808         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6809 }
6810
6811 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
6812 {
6813         /* Here begins a magic sequence of register writes to enable
6814          * auto-downclocking.
6815          *
6816          * Perhaps there might be some value in exposing these to
6817          * userspace...
6818          */
6819         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6820
6821         /* Power down if completely idle for over 50ms */
6822         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
6823         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6824
6825         reset_rps(dev_priv, gen6_set_rps);
6826
6827         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6828 }
6829
6830 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
6831 {
6832         struct intel_rps *rps = &dev_priv->gt_pm.rps;
6833         int min_freq = 15;
6834         unsigned int gpu_freq;
6835         unsigned int max_ia_freq, min_ring_freq;
6836         unsigned int max_gpu_freq, min_gpu_freq;
6837         int scaling_factor = 180;
6838         struct cpufreq_policy *policy;
6839
6840         WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
6841
6842         policy = cpufreq_cpu_get(0);
6843         if (policy) {
6844                 max_ia_freq = policy->cpuinfo.max_freq;
6845                 cpufreq_cpu_put(policy);
6846         } else {
6847                 /*
6848                  * Default to measured freq if none found, PCU will ensure we
6849                  * don't go over
6850                  */
6851                 max_ia_freq = tsc_khz;
6852         }
6853
6854         /* Convert from kHz to MHz */
6855         max_ia_freq /= 1000;
6856
6857         min_ring_freq = I915_READ(DCLK) & 0xf;
6858         /* convert DDR frequency from units of 266.6MHz to bandwidth */
6859         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
6860
6861         if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6862                 /* Convert GT frequency to 50 HZ units */
6863                 min_gpu_freq = rps->min_freq / GEN9_FREQ_SCALER;
6864                 max_gpu_freq = rps->max_freq / GEN9_FREQ_SCALER;
6865         } else {
6866                 min_gpu_freq = rps->min_freq;
6867                 max_gpu_freq = rps->max_freq;
6868         }
6869
6870         /*
6871          * For each potential GPU frequency, load a ring frequency we'd like
6872          * to use for memory access.  We do this by specifying the IA frequency
6873          * the PCU should use as a reference to determine the ring frequency.
6874          */
6875         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
6876                 int diff = max_gpu_freq - gpu_freq;
6877                 unsigned int ia_freq = 0, ring_freq = 0;
6878
6879                 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
6880                         /*
6881                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
6882                          * No floor required for ring frequency on SKL.
6883                          */
6884                         ring_freq = gpu_freq;
6885                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
6886                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
6887                         ring_freq = max(min_ring_freq, gpu_freq);
6888                 } else if (IS_HASWELL(dev_priv)) {
6889                         ring_freq = mult_frac(gpu_freq, 5, 4);
6890                         ring_freq = max(min_ring_freq, ring_freq);
6891                         /* leave ia_freq as the default, chosen by cpufreq */
6892                 } else {
6893                         /* On older processors, there is no separate ring
6894                          * clock domain, so in order to boost the bandwidth
6895                          * of the ring, we need to upclock the CPU (ia_freq).
6896                          *
6897                          * For GPU frequencies less than 750MHz,
6898                          * just use the lowest ring freq.
6899                          */
6900                         if (gpu_freq < min_freq)
6901                                 ia_freq = 800;
6902                         else
6903                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
6904                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
6905                 }
6906
6907                 sandybridge_pcode_write(dev_priv,
6908                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
6909                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
6910                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
6911                                         gpu_freq);
6912         }
6913 }
6914
6915 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
6916 {
6917         u32 val, rp0;
6918
6919         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
6920
6921         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
6922         case 8:
6923                 /* (2 * 4) config */
6924                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
6925                 break;
6926         case 12:
6927                 /* (2 * 6) config */
6928                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
6929                 break;
6930         case 16:
6931                 /* (2 * 8) config */
6932         default:
6933                 /* Setting (2 * 8) Min RP0 for any other combination */
6934                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
6935                 break;
6936         }
6937
6938         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
6939
6940         return rp0;
6941 }
6942
6943 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
6944 {
6945         u32 val, rpe;
6946
6947         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
6948         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
6949
6950         return rpe;
6951 }
6952
6953 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
6954 {
6955         u32 val, rp1;
6956
6957         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
6958         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
6959
6960         return rp1;
6961 }
6962
6963 static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
6964 {
6965         u32 val, rpn;
6966
6967         val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
6968         rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
6969                        FB_GFX_FREQ_FUSE_MASK);
6970
6971         return rpn;
6972 }
6973
6974 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
6975 {
6976         u32 val, rp1;
6977
6978         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
6979
6980         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
6981
6982         return rp1;
6983 }
6984
6985 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
6986 {
6987         u32 val, rp0;
6988
6989         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
6990
6991         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
6992         /* Clamp to max */
6993         rp0 = min_t(u32, rp0, 0xea);
6994
6995         return rp0;
6996 }
6997
6998 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
6999 {
7000         u32 val, rpe;
7001
7002         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
7003         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
7004         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
7005         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
7006
7007         return rpe;
7008 }
7009
7010 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
7011 {
7012         u32 val;
7013
7014         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
7015         /*
7016          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
7017          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
7018          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
7019          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
7020          * to make sure it matches what Punit accepts.
7021          */
7022         return max_t(u32, val, 0xc0);
7023 }
7024
7025 /* Check that the pctx buffer wasn't move under us. */
7026 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
7027 {
7028         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
7029
7030         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
7031                              dev_priv->vlv_pctx->stolen->start);
7032 }
7033
7034
7035 /* Check that the pcbr address is not empty. */
7036 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
7037 {
7038         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
7039
7040         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
7041 }
7042
7043 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
7044 {
7045         struct i915_ggtt *ggtt = &dev_priv->ggtt;
7046         unsigned long pctx_paddr, paddr;
7047         u32 pcbr;
7048         int pctx_size = 32*1024;
7049
7050         pcbr = I915_READ(VLV_PCBR);
7051         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
7052                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
7053                 paddr = (dev_priv->mm.stolen_base +
7054                          (ggtt->stolen_size - pctx_size));
7055
7056                 pctx_paddr = (paddr & (~4095));
7057                 I915_WRITE(VLV_PCBR, pctx_paddr);
7058         }
7059
7060         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
7061 }
7062
7063 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
7064 {
7065         struct drm_i915_gem_object *pctx;
7066         unsigned long pctx_paddr;
7067         u32 pcbr;
7068         int pctx_size = 24*1024;
7069
7070         pcbr = I915_READ(VLV_PCBR);
7071         if (pcbr) {
7072                 /* BIOS set it up already, grab the pre-alloc'd space */
7073                 int pcbr_offset;
7074
7075                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
7076                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
7077                                                                       pcbr_offset,
7078                                                                       I915_GTT_OFFSET_NONE,
7079                                                                       pctx_size);
7080                 goto out;
7081         }
7082
7083         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
7084
7085         /*
7086          * From the Gunit register HAS:
7087          * The Gfx driver is expected to program this register and ensure
7088          * proper allocation within Gfx stolen memory.  For example, this
7089          * register should be programmed such than the PCBR range does not
7090          * overlap with other ranges, such as the frame buffer, protected
7091          * memory, or any other relevant ranges.
7092          */
7093         pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
7094         if (!pctx) {
7095                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
7096                 goto out;
7097         }
7098
7099         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
7100         I915_WRITE(VLV_PCBR, pctx_paddr);
7101
7102 out:
7103         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
7104         dev_priv->vlv_pctx = pctx;
7105 }
7106
7107 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
7108 {
7109         if (WARN_ON(!dev_priv->vlv_pctx))
7110                 return;
7111
7112         i915_gem_object_put(dev_priv->vlv_pctx);
7113         dev_priv->vlv_pctx = NULL;
7114 }
7115
7116 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
7117 {
7118         dev_priv->gt_pm.rps.gpll_ref_freq =
7119                 vlv_get_cck_clock(dev_priv, "GPLL ref",
7120                                   CCK_GPLL_CLOCK_CONTROL,
7121                                   dev_priv->czclk_freq);
7122
7123         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
7124                          dev_priv->gt_pm.rps.gpll_ref_freq);
7125 }
7126
7127 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
7128 {
7129         struct intel_rps *rps = &dev_priv->gt_pm.rps;
7130         u32 val;
7131
7132         valleyview_setup_pctx(dev_priv);
7133
7134         vlv_init_gpll_ref_freq(dev_priv);
7135
7136         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7137         switch ((val >> 6) & 3) {
7138         case 0:
7139         case 1:
7140                 dev_priv->mem_freq = 800;
7141                 break;
7142         case 2:
7143                 dev_priv->mem_freq = 1066;
7144                 break;
7145         case 3:
7146                 dev_priv->mem_freq = 1333;
7147                 break;
7148         }
7149         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
7150
7151         rps->max_freq = valleyview_rps_max_freq(dev_priv);
7152         rps->rp0_freq = rps->max_freq;
7153         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7154                          intel_gpu_freq(dev_priv, rps->max_freq),
7155                          rps->max_freq);
7156
7157         rps->efficient_freq = valleyview_rps_rpe_freq(dev_priv);
7158         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7159                          intel_gpu_freq(dev_priv, rps->efficient_freq),
7160                          rps->efficient_freq);
7161
7162         rps->rp1_freq = valleyview_rps_guar_freq(dev_priv);
7163         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7164                          intel_gpu_freq(dev_priv, rps->rp1_freq),
7165                          rps->rp1_freq);
7166
7167         rps->min_freq = valleyview_rps_min_freq(dev_priv);
7168         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7169                          intel_gpu_freq(dev_priv, rps->min_freq),
7170                          rps->min_freq);
7171 }
7172
7173 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
7174 {
7175         struct intel_rps *rps = &dev_priv->gt_pm.rps;
7176         u32 val;
7177
7178         cherryview_setup_pctx(dev_priv);
7179
7180         vlv_init_gpll_ref_freq(dev_priv);
7181
7182         mutex_lock(&dev_priv->sb_lock);
7183         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
7184         mutex_unlock(&dev_priv->sb_lock);
7185
7186         switch ((val >> 2) & 0x7) {
7187         case 3:
7188                 dev_priv->mem_freq = 2000;
7189                 break;
7190         default:
7191                 dev_priv->mem_freq = 1600;
7192                 break;
7193         }
7194         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
7195
7196         rps->max_freq = cherryview_rps_max_freq(dev_priv);
7197         rps->rp0_freq = rps->max_freq;
7198         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7199                          intel_gpu_freq(dev_priv, rps->max_freq),
7200                          rps->max_freq);
7201
7202         rps->efficient_freq = cherryview_rps_rpe_freq(dev_priv);
7203         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7204                          intel_gpu_freq(dev_priv, rps->efficient_freq),
7205                          rps->efficient_freq);
7206
7207         rps->rp1_freq = cherryview_rps_guar_freq(dev_priv);
7208         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7209                          intel_gpu_freq(dev_priv, rps->rp1_freq),
7210                          rps->rp1_freq);
7211
7212         rps->min_freq = cherryview_rps_min_freq(dev_priv);
7213         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7214                          intel_gpu_freq(dev_priv, rps->min_freq),
7215                          rps->min_freq);
7216
7217         WARN_ONCE((rps->max_freq | rps->efficient_freq | rps->rp1_freq |
7218                    rps->min_freq) & 1,
7219                   "Odd GPU freq values\n");
7220 }
7221
7222 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
7223 {
7224         valleyview_cleanup_pctx(dev_priv);
7225 }
7226
7227 static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
7228 {
7229         struct intel_engine_cs *engine;
7230         enum intel_engine_id id;
7231         u32 gtfifodbg, rc6_mode = 0, pcbr;
7232
7233         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
7234                                              GT_FIFO_FREE_ENTRIES_CHV);
7235         if (gtfifodbg) {
7236                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7237                                  gtfifodbg);
7238                 I915_WRITE(GTFIFODBG, gtfifodbg);
7239         }
7240
7241         cherryview_check_pctx(dev_priv);
7242
7243         /* 1a & 1b: Get forcewake during program sequence. Although the driver
7244          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
7245         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7246
7247         /*  Disable RC states. */
7248         I915_WRITE(GEN6_RC_CONTROL, 0);
7249
7250         /* 2a: Program RC6 thresholds.*/
7251         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
7252         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
7253         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
7254
7255         for_each_engine(engine, dev_priv, id)
7256                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7257         I915_WRITE(GEN6_RC_SLEEP, 0);
7258
7259         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
7260         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
7261
7262         /* Allows RC6 residency counter to work */
7263         I915_WRITE(VLV_COUNTER_CONTROL,
7264                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
7265                                       VLV_MEDIA_RC6_COUNT_EN |
7266                                       VLV_RENDER_RC6_COUNT_EN));
7267
7268         /* For now we assume BIOS is allocating and populating the PCBR  */
7269         pcbr = I915_READ(VLV_PCBR);
7270
7271         /* 3: Enable RC6 */
7272         if ((intel_rc6_enabled() & INTEL_RC6_ENABLE) &&
7273             (pcbr >> VLV_PCBR_ADDR_SHIFT))
7274                 rc6_mode = GEN7_RC_CTL_TO_MODE;
7275
7276         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
7277
7278         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7279 }
7280
7281 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
7282 {
7283         u32 val;
7284
7285         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7286
7287         /* 1: Program defaults and thresholds for RPS*/
7288         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7289         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
7290         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
7291         I915_WRITE(GEN6_RP_UP_EI, 66000);
7292         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
7293
7294         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7295
7296         /* 2: Enable RPS */
7297         I915_WRITE(GEN6_RP_CONTROL,
7298                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
7299                    GEN6_RP_MEDIA_IS_GFX |
7300                    GEN6_RP_ENABLE |
7301                    GEN6_RP_UP_BUSY_AVG |
7302                    GEN6_RP_DOWN_IDLE_AVG);
7303
7304         /* Setting Fixed Bias */
7305         val = VLV_OVERRIDE_EN |
7306                   VLV_SOC_TDP_EN |
7307                   CHV_BIAS_CPU_50_SOC_50;
7308         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
7309
7310         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7311
7312         /* RPS code assumes GPLL is used */
7313         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
7314
7315         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
7316         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
7317
7318         reset_rps(dev_priv, valleyview_set_rps);
7319
7320         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7321 }
7322
7323 static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
7324 {
7325         struct intel_engine_cs *engine;
7326         enum intel_engine_id id;
7327         u32 gtfifodbg, rc6_mode = 0;
7328
7329         valleyview_check_pctx(dev_priv);
7330
7331         gtfifodbg = I915_READ(GTFIFODBG);
7332         if (gtfifodbg) {
7333                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
7334                                  gtfifodbg);
7335                 I915_WRITE(GTFIFODBG, gtfifodbg);
7336         }
7337
7338         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7339
7340         /*  Disable RC states. */
7341         I915_WRITE(GEN6_RC_CONTROL, 0);
7342
7343         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
7344         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7345         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7346
7347         for_each_engine(engine, dev_priv, id)
7348                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
7349
7350         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
7351
7352         /* Allows RC6 residency counter to work */
7353         I915_WRITE(VLV_COUNTER_CONTROL,
7354                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
7355                                       VLV_MEDIA_RC0_COUNT_EN |
7356                                       VLV_RENDER_RC0_COUNT_EN |
7357                                       VLV_MEDIA_RC6_COUNT_EN |
7358                                       VLV_RENDER_RC6_COUNT_EN));
7359
7360         if (intel_rc6_enabled() & INTEL_RC6_ENABLE)
7361                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
7362
7363         intel_print_rc6_info(dev_priv, rc6_mode);
7364
7365         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
7366
7367         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7368 }
7369
7370 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
7371 {
7372         u32 val;
7373
7374         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7375
7376         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7377         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
7378         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
7379         I915_WRITE(GEN6_RP_UP_EI, 66000);
7380         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
7381
7382         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7383
7384         I915_WRITE(GEN6_RP_CONTROL,
7385                    GEN6_RP_MEDIA_TURBO |
7386                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
7387                    GEN6_RP_MEDIA_IS_GFX |
7388                    GEN6_RP_ENABLE |
7389                    GEN6_RP_UP_BUSY_AVG |
7390                    GEN6_RP_DOWN_IDLE_CONT);
7391
7392         /* Setting Fixed Bias */
7393         val = VLV_OVERRIDE_EN |
7394                   VLV_SOC_TDP_EN |
7395                   VLV_BIAS_CPU_125_SOC_875;
7396         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
7397
7398         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
7399
7400         /* RPS code assumes GPLL is used */
7401         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
7402
7403         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
7404         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
7405
7406         reset_rps(dev_priv, valleyview_set_rps);
7407
7408         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7409 }
7410
7411 static unsigned long intel_pxfreq(u32 vidfreq)
7412 {
7413         unsigned long freq;
7414         int div = (vidfreq & 0x3f0000) >> 16;
7415         int post = (vidfreq & 0x3000) >> 12;
7416         int pre = (vidfreq & 0x7);
7417
7418         if (!pre)
7419                 return 0;
7420
7421         freq = ((div * 133333) / ((1<<post) * pre));
7422
7423         return freq;
7424 }
7425
7426 static const struct cparams {
7427         u16 i;
7428         u16 t;
7429         u16 m;
7430         u16 c;
7431 } cparams[] = {
7432         { 1, 1333, 301, 28664 },
7433         { 1, 1066, 294, 24460 },
7434         { 1, 800, 294, 25192 },
7435         { 0, 1333, 276, 27605 },
7436         { 0, 1066, 276, 27605 },
7437         { 0, 800, 231, 23784 },
7438 };
7439
7440 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
7441 {
7442         u64 total_count, diff, ret;
7443         u32 count1, count2, count3, m = 0, c = 0;
7444         unsigned long now = jiffies_to_msecs(jiffies), diff1;
7445         int i;
7446
7447         lockdep_assert_held(&mchdev_lock);
7448
7449         diff1 = now - dev_priv->ips.last_time1;
7450
7451         /* Prevent division-by-zero if we are asking too fast.
7452          * Also, we don't get interesting results if we are polling
7453          * faster than once in 10ms, so just return the saved value
7454          * in such cases.
7455          */
7456         if (diff1 <= 10)
7457                 return dev_priv->ips.chipset_power;
7458
7459         count1 = I915_READ(DMIEC);
7460         count2 = I915_READ(DDREC);
7461         count3 = I915_READ(CSIEC);
7462
7463         total_count = count1 + count2 + count3;
7464
7465         /* FIXME: handle per-counter overflow */
7466         if (total_count < dev_priv->ips.last_count1) {
7467                 diff = ~0UL - dev_priv->ips.last_count1;
7468                 diff += total_count;
7469         } else {
7470                 diff = total_count - dev_priv->ips.last_count1;
7471         }
7472
7473         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
7474                 if (cparams[i].i == dev_priv->ips.c_m &&
7475                     cparams[i].t == dev_priv->ips.r_t) {
7476                         m = cparams[i].m;
7477                         c = cparams[i].c;
7478                         break;
7479                 }
7480         }
7481
7482         diff = div_u64(diff, diff1);
7483         ret = ((m * diff) + c);
7484         ret = div_u64(ret, 10);
7485
7486         dev_priv->ips.last_count1 = total_count;
7487         dev_priv->ips.last_time1 = now;
7488
7489         dev_priv->ips.chipset_power = ret;
7490
7491         return ret;
7492 }
7493
7494 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
7495 {
7496         unsigned long val;
7497
7498         if (INTEL_INFO(dev_priv)->gen != 5)
7499                 return 0;
7500
7501         spin_lock_irq(&mchdev_lock);
7502
7503         val = __i915_chipset_val(dev_priv);
7504
7505         spin_unlock_irq(&mchdev_lock);
7506
7507         return val;
7508 }
7509
7510 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
7511 {
7512         unsigned long m, x, b;
7513         u32 tsfs;
7514
7515         tsfs = I915_READ(TSFS);
7516
7517         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
7518         x = I915_READ8(TR1);
7519
7520         b = tsfs & TSFS_INTR_MASK;
7521
7522         return ((m * x) / 127) - b;
7523 }
7524
7525 static int _pxvid_to_vd(u8 pxvid)
7526 {
7527         if (pxvid == 0)
7528                 return 0;
7529
7530         if (pxvid >= 8 && pxvid < 31)
7531                 pxvid = 31;
7532
7533         return (pxvid + 2) * 125;
7534 }
7535
7536 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
7537 {
7538         const int vd = _pxvid_to_vd(pxvid);
7539         const int vm = vd - 1125;
7540
7541         if (INTEL_INFO(dev_priv)->is_mobile)
7542                 return vm > 0 ? vm : 0;
7543
7544         return vd;
7545 }
7546
7547 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
7548 {
7549         u64 now, diff, diffms;
7550         u32 count;
7551
7552         lockdep_assert_held(&mchdev_lock);
7553
7554         now = ktime_get_raw_ns();
7555         diffms = now - dev_priv->ips.last_time2;
7556         do_div(diffms, NSEC_PER_MSEC);
7557
7558         /* Don't divide by 0 */
7559         if (!diffms)
7560                 return;
7561
7562         count = I915_READ(GFXEC);
7563
7564         if (count < dev_priv->ips.last_count2) {
7565                 diff = ~0UL - dev_priv->ips.last_count2;
7566                 diff += count;
7567         } else {
7568                 diff = count - dev_priv->ips.last_count2;
7569         }
7570
7571         dev_priv->ips.last_count2 = count;
7572         dev_priv->ips.last_time2 = now;
7573
7574         /* More magic constants... */
7575         diff = diff * 1181;
7576         diff = div_u64(diff, diffms * 10);
7577         dev_priv->ips.gfx_power = diff;
7578 }
7579
7580 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
7581 {
7582         if (INTEL_INFO(dev_priv)->gen != 5)
7583                 return;
7584
7585         spin_lock_irq(&mchdev_lock);
7586
7587         __i915_update_gfx_val(dev_priv);
7588
7589         spin_unlock_irq(&mchdev_lock);
7590 }
7591
7592 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
7593 {
7594         unsigned long t, corr, state1, corr2, state2;
7595         u32 pxvid, ext_v;
7596
7597         lockdep_assert_held(&mchdev_lock);
7598
7599         pxvid = I915_READ(PXVFREQ(dev_priv->gt_pm.rps.cur_freq));
7600         pxvid = (pxvid >> 24) & 0x7f;
7601         ext_v = pvid_to_extvid(dev_priv, pxvid);
7602
7603         state1 = ext_v;
7604
7605         t = i915_mch_val(dev_priv);
7606
7607         /* Revel in the empirically derived constants */
7608
7609         /* Correction factor in 1/100000 units */
7610         if (t > 80)
7611                 corr = ((t * 2349) + 135940);
7612         else if (t >= 50)
7613                 corr = ((t * 964) + 29317);
7614         else /* < 50 */
7615                 corr = ((t * 301) + 1004);
7616
7617         corr = corr * ((150142 * state1) / 10000 - 78642);
7618         corr /= 100000;
7619         corr2 = (corr * dev_priv->ips.corr);
7620
7621         state2 = (corr2 * state1) / 10000;
7622         state2 /= 100; /* convert to mW */
7623
7624         __i915_update_gfx_val(dev_priv);
7625
7626         return dev_priv->ips.gfx_power + state2;
7627 }
7628
7629 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
7630 {
7631         unsigned long val;
7632
7633         if (INTEL_INFO(dev_priv)->gen != 5)
7634                 return 0;
7635
7636         spin_lock_irq(&mchdev_lock);
7637
7638         val = __i915_gfx_val(dev_priv);
7639
7640         spin_unlock_irq(&mchdev_lock);
7641
7642         return val;
7643 }
7644
7645 /**
7646  * i915_read_mch_val - return value for IPS use
7647  *
7648  * Calculate and return a value for the IPS driver to use when deciding whether
7649  * we have thermal and power headroom to increase CPU or GPU power budget.
7650  */
7651 unsigned long i915_read_mch_val(void)
7652 {
7653         struct drm_i915_private *dev_priv;
7654         unsigned long chipset_val, graphics_val, ret = 0;
7655
7656         spin_lock_irq(&mchdev_lock);
7657         if (!i915_mch_dev)
7658                 goto out_unlock;
7659         dev_priv = i915_mch_dev;
7660
7661         chipset_val = __i915_chipset_val(dev_priv);
7662         graphics_val = __i915_gfx_val(dev_priv);
7663
7664         ret = chipset_val + graphics_val;
7665
7666 out_unlock:
7667         spin_unlock_irq(&mchdev_lock);
7668
7669         return ret;
7670 }
7671 EXPORT_SYMBOL_GPL(i915_read_mch_val);
7672
7673 /**
7674  * i915_gpu_raise - raise GPU frequency limit
7675  *
7676  * Raise the limit; IPS indicates we have thermal headroom.
7677  */
7678 bool i915_gpu_raise(void)
7679 {
7680         struct drm_i915_private *dev_priv;
7681         bool ret = true;
7682
7683         spin_lock_irq(&mchdev_lock);
7684         if (!i915_mch_dev) {
7685                 ret = false;
7686                 goto out_unlock;
7687         }
7688         dev_priv = i915_mch_dev;
7689
7690         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
7691                 dev_priv->ips.max_delay--;
7692
7693 out_unlock:
7694         spin_unlock_irq(&mchdev_lock);
7695
7696         return ret;
7697 }
7698 EXPORT_SYMBOL_GPL(i915_gpu_raise);
7699
7700 /**
7701  * i915_gpu_lower - lower GPU frequency limit
7702  *
7703  * IPS indicates we're close to a thermal limit, so throttle back the GPU
7704  * frequency maximum.
7705  */
7706 bool i915_gpu_lower(void)
7707 {
7708         struct drm_i915_private *dev_priv;
7709         bool ret = true;
7710
7711         spin_lock_irq(&mchdev_lock);
7712         if (!i915_mch_dev) {
7713                 ret = false;
7714                 goto out_unlock;
7715         }
7716         dev_priv = i915_mch_dev;
7717
7718         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
7719                 dev_priv->ips.max_delay++;
7720
7721 out_unlock:
7722         spin_unlock_irq(&mchdev_lock);
7723
7724         return ret;
7725 }
7726 EXPORT_SYMBOL_GPL(i915_gpu_lower);
7727
7728 /**
7729  * i915_gpu_busy - indicate GPU business to IPS
7730  *
7731  * Tell the IPS driver whether or not the GPU is busy.
7732  */
7733 bool i915_gpu_busy(void)
7734 {
7735         bool ret = false;
7736
7737         spin_lock_irq(&mchdev_lock);
7738         if (i915_mch_dev)
7739                 ret = i915_mch_dev->gt.awake;
7740         spin_unlock_irq(&mchdev_lock);
7741
7742         return ret;
7743 }
7744 EXPORT_SYMBOL_GPL(i915_gpu_busy);
7745
7746 /**
7747  * i915_gpu_turbo_disable - disable graphics turbo
7748  *
7749  * Disable graphics turbo by resetting the max frequency and setting the
7750  * current frequency to the default.
7751  */
7752 bool i915_gpu_turbo_disable(void)
7753 {
7754         struct drm_i915_private *dev_priv;
7755         bool ret = true;
7756
7757         spin_lock_irq(&mchdev_lock);
7758         if (!i915_mch_dev) {
7759                 ret = false;
7760                 goto out_unlock;
7761         }
7762         dev_priv = i915_mch_dev;
7763
7764         dev_priv->ips.max_delay = dev_priv->ips.fstart;
7765
7766         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
7767                 ret = false;
7768
7769 out_unlock:
7770         spin_unlock_irq(&mchdev_lock);
7771
7772         return ret;
7773 }
7774 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
7775
7776 /**
7777  * Tells the intel_ips driver that the i915 driver is now loaded, if
7778  * IPS got loaded first.
7779  *
7780  * This awkward dance is so that neither module has to depend on the
7781  * other in order for IPS to do the appropriate communication of
7782  * GPU turbo limits to i915.
7783  */
7784 static void
7785 ips_ping_for_i915_load(void)
7786 {
7787         void (*link)(void);
7788
7789         link = symbol_get(ips_link_to_i915_driver);
7790         if (link) {
7791                 link();
7792                 symbol_put(ips_link_to_i915_driver);
7793         }
7794 }
7795
7796 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
7797 {
7798         /* We only register the i915 ips part with intel-ips once everything is
7799          * set up, to avoid intel-ips sneaking in and reading bogus values. */
7800         spin_lock_irq(&mchdev_lock);
7801         i915_mch_dev = dev_priv;
7802         spin_unlock_irq(&mchdev_lock);
7803
7804         ips_ping_for_i915_load();
7805 }
7806
7807 void intel_gpu_ips_teardown(void)
7808 {
7809         spin_lock_irq(&mchdev_lock);
7810         i915_mch_dev = NULL;
7811         spin_unlock_irq(&mchdev_lock);
7812 }
7813
7814 static void intel_init_emon(struct drm_i915_private *dev_priv)
7815 {
7816         u32 lcfuse;
7817         u8 pxw[16];
7818         int i;
7819
7820         /* Disable to program */
7821         I915_WRITE(ECR, 0);
7822         POSTING_READ(ECR);
7823
7824         /* Program energy weights for various events */
7825         I915_WRITE(SDEW, 0x15040d00);
7826         I915_WRITE(CSIEW0, 0x007f0000);
7827         I915_WRITE(CSIEW1, 0x1e220004);
7828         I915_WRITE(CSIEW2, 0x04000004);
7829
7830         for (i = 0; i < 5; i++)
7831                 I915_WRITE(PEW(i), 0);
7832         for (i = 0; i < 3; i++)
7833                 I915_WRITE(DEW(i), 0);
7834
7835         /* Program P-state weights to account for frequency power adjustment */
7836         for (i = 0; i < 16; i++) {
7837                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
7838                 unsigned long freq = intel_pxfreq(pxvidfreq);
7839                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7840                         PXVFREQ_PX_SHIFT;
7841                 unsigned long val;
7842
7843                 val = vid * vid;
7844                 val *= (freq / 1000);
7845                 val *= 255;
7846                 val /= (127*127*900);
7847                 if (val > 0xff)
7848                         DRM_ERROR("bad pxval: %ld\n", val);
7849                 pxw[i] = val;
7850         }
7851         /* Render standby states get 0 weight */
7852         pxw[14] = 0;
7853         pxw[15] = 0;
7854
7855         for (i = 0; i < 4; i++) {
7856                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7857                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7858                 I915_WRITE(PXW(i), val);
7859         }
7860
7861         /* Adjust magic regs to magic values (more experimental results) */
7862         I915_WRITE(OGW0, 0);
7863         I915_WRITE(OGW1, 0);
7864         I915_WRITE(EG0, 0x00007f00);
7865         I915_WRITE(EG1, 0x0000000e);
7866         I915_WRITE(EG2, 0x000e0000);
7867         I915_WRITE(EG3, 0x68000300);
7868         I915_WRITE(EG4, 0x42000000);
7869         I915_WRITE(EG5, 0x00140031);
7870         I915_WRITE(EG6, 0);
7871         I915_WRITE(EG7, 0);
7872
7873         for (i = 0; i < 8; i++)
7874                 I915_WRITE(PXWL(i), 0);
7875
7876         /* Enable PMON + select events */
7877         I915_WRITE(ECR, 0x80000019);
7878
7879         lcfuse = I915_READ(LCFUSE02);
7880
7881         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
7882 }
7883
7884 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
7885 {
7886         struct intel_rps *rps = &dev_priv->gt_pm.rps;
7887
7888         /*
7889          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7890          * requirement.
7891          */
7892         if (!i915_modparams.enable_rc6) {
7893                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7894                 intel_runtime_pm_get(dev_priv);
7895         }
7896
7897         mutex_lock(&dev_priv->drm.struct_mutex);
7898         mutex_lock(&dev_priv->pcu_lock);
7899
7900         /* Initialize RPS limits (for userspace) */
7901         if (IS_CHERRYVIEW(dev_priv))
7902                 cherryview_init_gt_powersave(dev_priv);
7903         else if (IS_VALLEYVIEW(dev_priv))
7904                 valleyview_init_gt_powersave(dev_priv);
7905         else if (INTEL_GEN(dev_priv) >= 6)
7906                 gen6_init_rps_frequencies(dev_priv);
7907
7908         /* Derive initial user preferences/limits from the hardware limits */
7909         rps->idle_freq = rps->min_freq;
7910         rps->cur_freq = rps->idle_freq;
7911
7912         rps->max_freq_softlimit = rps->max_freq;
7913         rps->min_freq_softlimit = rps->min_freq;
7914
7915         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
7916                 rps->min_freq_softlimit =
7917                         max_t(int,
7918                               rps->efficient_freq,
7919                               intel_freq_opcode(dev_priv, 450));
7920
7921         /* After setting max-softlimit, find the overclock max freq */
7922         if (IS_GEN6(dev_priv) ||
7923             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
7924                 u32 params = 0;
7925
7926                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
7927                 if (params & BIT(31)) { /* OC supported */
7928                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
7929                                          (rps->max_freq & 0xff) * 50,
7930                                          (params & 0xff) * 50);
7931                         rps->max_freq = params & 0xff;
7932                 }
7933         }
7934
7935         /* Finally allow us to boost to max by default */
7936         rps->boost_freq = rps->max_freq;
7937
7938         mutex_unlock(&dev_priv->pcu_lock);
7939         mutex_unlock(&dev_priv->drm.struct_mutex);
7940
7941         intel_autoenable_gt_powersave(dev_priv);
7942 }
7943
7944 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
7945 {
7946         if (IS_VALLEYVIEW(dev_priv))
7947                 valleyview_cleanup_gt_powersave(dev_priv);
7948
7949         if (!i915_modparams.enable_rc6)
7950                 intel_runtime_pm_put(dev_priv);
7951 }
7952
7953 /**
7954  * intel_suspend_gt_powersave - suspend PM work and helper threads
7955  * @dev_priv: i915 device
7956  *
7957  * We don't want to disable RC6 or other features here, we just want
7958  * to make sure any work we've queued has finished and won't bother
7959  * us while we're suspended.
7960  */
7961 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
7962 {
7963         if (INTEL_GEN(dev_priv) < 6)
7964                 return;
7965
7966         if (cancel_delayed_work_sync(&dev_priv->gt_pm.autoenable_work))
7967                 intel_runtime_pm_put(dev_priv);
7968
7969         /* gen6_rps_idle() will be called later to disable interrupts */
7970 }
7971
7972 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
7973 {
7974         dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
7975         dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
7976         intel_disable_gt_powersave(dev_priv);
7977
7978         gen6_reset_rps_interrupts(dev_priv);
7979 }
7980
7981 static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
7982 {
7983         lockdep_assert_held(&i915->pcu_lock);
7984
7985         if (!i915->gt_pm.llc_pstate.enabled)
7986                 return;
7987
7988         /* Currently there is no HW configuration to be done to disable. */
7989
7990         i915->gt_pm.llc_pstate.enabled = false;
7991 }
7992
7993 static void intel_disable_rc6(struct drm_i915_private *dev_priv)
7994 {
7995         lockdep_assert_held(&dev_priv->pcu_lock);
7996
7997         if (!dev_priv->gt_pm.rc6.enabled)
7998                 return;
7999
8000         if (INTEL_GEN(dev_priv) >= 9)
8001                 gen9_disable_rc6(dev_priv);
8002         else if (IS_CHERRYVIEW(dev_priv))
8003                 cherryview_disable_rc6(dev_priv);
8004         else if (IS_VALLEYVIEW(dev_priv))
8005                 valleyview_disable_rc6(dev_priv);
8006         else if (INTEL_GEN(dev_priv) >= 6)
8007                 gen6_disable_rc6(dev_priv);
8008
8009         dev_priv->gt_pm.rc6.enabled = false;
8010 }
8011
8012 static void intel_disable_rps(struct drm_i915_private *dev_priv)
8013 {
8014         lockdep_assert_held(&dev_priv->pcu_lock);
8015
8016         if (!dev_priv->gt_pm.rps.enabled)
8017                 return;
8018
8019         if (INTEL_GEN(dev_priv) >= 9)
8020                 gen9_disable_rps(dev_priv);
8021         else if (IS_CHERRYVIEW(dev_priv))
8022                 cherryview_disable_rps(dev_priv);
8023         else if (IS_VALLEYVIEW(dev_priv))
8024                 valleyview_disable_rps(dev_priv);
8025         else if (INTEL_GEN(dev_priv) >= 6)
8026                 gen6_disable_rps(dev_priv);
8027         else if (IS_IRONLAKE_M(dev_priv))
8028                 ironlake_disable_drps(dev_priv);
8029
8030         dev_priv->gt_pm.rps.enabled = false;
8031 }
8032
8033 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8034 {
8035         mutex_lock(&dev_priv->pcu_lock);
8036
8037         intel_disable_rc6(dev_priv);
8038         intel_disable_rps(dev_priv);
8039         if (HAS_LLC(dev_priv))
8040                 intel_disable_llc_pstate(dev_priv);
8041
8042         mutex_unlock(&dev_priv->pcu_lock);
8043 }
8044
8045 static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
8046 {
8047         lockdep_assert_held(&i915->pcu_lock);
8048
8049         if (i915->gt_pm.llc_pstate.enabled)
8050                 return;
8051
8052         gen6_update_ring_freq(i915);
8053
8054         i915->gt_pm.llc_pstate.enabled = true;
8055 }
8056
8057 static void intel_enable_rc6(struct drm_i915_private *dev_priv)
8058 {
8059         lockdep_assert_held(&dev_priv->pcu_lock);
8060
8061         if (dev_priv->gt_pm.rc6.enabled)
8062                 return;
8063
8064         if (IS_CHERRYVIEW(dev_priv))
8065                 cherryview_enable_rc6(dev_priv);
8066         else if (IS_VALLEYVIEW(dev_priv))
8067                 valleyview_enable_rc6(dev_priv);
8068         else if (INTEL_GEN(dev_priv) >= 9)
8069                 gen9_enable_rc6(dev_priv);
8070         else if (IS_BROADWELL(dev_priv))
8071                 gen8_enable_rc6(dev_priv);
8072         else if (INTEL_GEN(dev_priv) >= 6)
8073                 gen6_enable_rc6(dev_priv);
8074
8075         dev_priv->gt_pm.rc6.enabled = true;
8076 }
8077
8078 static void intel_enable_rps(struct drm_i915_private *dev_priv)
8079 {
8080         struct intel_rps *rps = &dev_priv->gt_pm.rps;
8081
8082         lockdep_assert_held(&dev_priv->pcu_lock);
8083
8084         if (rps->enabled)
8085                 return;
8086
8087         if (IS_CHERRYVIEW(dev_priv)) {
8088                 cherryview_enable_rps(dev_priv);
8089         } else if (IS_VALLEYVIEW(dev_priv)) {
8090                 valleyview_enable_rps(dev_priv);
8091         } else if (INTEL_GEN(dev_priv) >= 9) {
8092                 gen9_enable_rps(dev_priv);
8093         } else if (IS_BROADWELL(dev_priv)) {
8094                 gen8_enable_rps(dev_priv);
8095         } else if (INTEL_GEN(dev_priv) >= 6) {
8096                 gen6_enable_rps(dev_priv);
8097         } else if (IS_IRONLAKE_M(dev_priv)) {
8098                 ironlake_enable_drps(dev_priv);
8099                 intel_init_emon(dev_priv);
8100         }
8101
8102         WARN_ON(rps->max_freq < rps->min_freq);
8103         WARN_ON(rps->idle_freq > rps->max_freq);
8104
8105         WARN_ON(rps->efficient_freq < rps->min_freq);
8106         WARN_ON(rps->efficient_freq > rps->max_freq);
8107
8108         rps->enabled = true;
8109 }
8110
8111 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
8112 {
8113         /* Powersaving is controlled by the host when inside a VM */
8114         if (intel_vgpu_active(dev_priv))
8115                 return;
8116
8117         mutex_lock(&dev_priv->pcu_lock);
8118
8119         intel_enable_rc6(dev_priv);
8120         intel_enable_rps(dev_priv);
8121         if (HAS_LLC(dev_priv))
8122                 intel_enable_llc_pstate(dev_priv);
8123
8124         mutex_unlock(&dev_priv->pcu_lock);
8125 }
8126
8127 static void __intel_autoenable_gt_powersave(struct work_struct *work)
8128 {
8129         struct drm_i915_private *dev_priv =
8130                 container_of(work,
8131                              typeof(*dev_priv),
8132                              gt_pm.autoenable_work.work);
8133         struct intel_engine_cs *rcs;
8134         struct drm_i915_gem_request *req;
8135
8136         rcs = dev_priv->engine[RCS];
8137         if (rcs->last_retired_context)
8138                 goto out;
8139
8140         if (!rcs->init_context)
8141                 goto out;
8142
8143         mutex_lock(&dev_priv->drm.struct_mutex);
8144
8145         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
8146         if (IS_ERR(req))
8147                 goto unlock;
8148
8149         if (!i915_modparams.enable_execlists && i915_switch_context(req) == 0)
8150                 rcs->init_context(req);
8151
8152         /* Mark the device busy, calling intel_enable_gt_powersave() */
8153         i915_add_request(req);
8154
8155 unlock:
8156         mutex_unlock(&dev_priv->drm.struct_mutex);
8157 out:
8158         intel_runtime_pm_put(dev_priv);
8159 }
8160
8161 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
8162 {
8163         if (IS_IRONLAKE_M(dev_priv)) {
8164                 ironlake_enable_drps(dev_priv);
8165                 intel_init_emon(dev_priv);
8166         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
8167                 /*
8168                  * PCU communication is slow and this doesn't need to be
8169                  * done at any specific time, so do this out of our fast path
8170                  * to make resume and init faster.
8171                  *
8172                  * We depend on the HW RC6 power context save/restore
8173                  * mechanism when entering D3 through runtime PM suspend. So
8174                  * disable RPM until RPS/RC6 is properly setup. We can only
8175                  * get here via the driver load/system resume/runtime resume
8176                  * paths, so the _noresume version is enough (and in case of
8177                  * runtime resume it's necessary).
8178                  */
8179                 if (queue_delayed_work(dev_priv->wq,
8180                                        &dev_priv->gt_pm.autoenable_work,
8181                                        round_jiffies_up_relative(HZ)))
8182                         intel_runtime_pm_get_noresume(dev_priv);
8183         }
8184 }
8185
8186 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
8187 {
8188         /*
8189          * On Ibex Peak and Cougar Point, we need to disable clock
8190          * gating for the panel power sequencer or it will fail to
8191          * start up when no ports are active.
8192          */
8193         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8194 }
8195
8196 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
8197 {
8198         enum pipe pipe;
8199
8200         for_each_pipe(dev_priv, pipe) {
8201                 I915_WRITE(DSPCNTR(pipe),
8202                            I915_READ(DSPCNTR(pipe)) |
8203                            DISPPLANE_TRICKLE_FEED_DISABLE);
8204
8205                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
8206                 POSTING_READ(DSPSURF(pipe));
8207         }
8208 }
8209
8210 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
8211 {
8212         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
8213         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
8214         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
8215
8216         /*
8217          * Don't touch WM1S_LP_EN here.
8218          * Doing so could cause underruns.
8219          */
8220 }
8221
8222 static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
8223 {
8224         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
8225
8226         /*
8227          * Required for FBC
8228          * WaFbcDisableDpfcClockGating:ilk
8229          */
8230         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
8231                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
8232                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
8233
8234         I915_WRITE(PCH_3DCGDIS0,
8235                    MARIUNIT_CLOCK_GATE_DISABLE |
8236                    SVSMUNIT_CLOCK_GATE_DISABLE);
8237         I915_WRITE(PCH_3DCGDIS1,
8238                    VFMUNIT_CLOCK_GATE_DISABLE);
8239
8240         /*
8241          * According to the spec the following bits should be set in
8242          * order to enable memory self-refresh
8243          * The bit 22/21 of 0x42004
8244          * The bit 5 of 0x42020
8245          * The bit 15 of 0x45000
8246          */
8247         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8248                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
8249                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8250         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
8251         I915_WRITE(DISP_ARB_CTL,
8252                    (I915_READ(DISP_ARB_CTL) |
8253                     DISP_FBC_WM_DIS));
8254
8255         ilk_init_lp_watermarks(dev_priv);
8256
8257         /*
8258          * Based on the document from hardware guys the following bits
8259          * should be set unconditionally in order to enable FBC.
8260          * The bit 22 of 0x42000
8261          * The bit 22 of 0x42004
8262          * The bit 7,8,9 of 0x42020.
8263          */
8264         if (IS_IRONLAKE_M(dev_priv)) {
8265                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
8266                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8267                            I915_READ(ILK_DISPLAY_CHICKEN1) |
8268                            ILK_FBCQ_DIS);
8269                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8270                            I915_READ(ILK_DISPLAY_CHICKEN2) |
8271                            ILK_DPARB_GATE);
8272         }
8273
8274         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
8275
8276         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8277                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8278                    ILK_ELPIN_409_SELECT);
8279         I915_WRITE(_3D_CHICKEN2,
8280                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8281                    _3D_CHICKEN2_WM_READ_PIPELINED);
8282
8283         /* WaDisableRenderCachePipelinedFlush:ilk */
8284         I915_WRITE(CACHE_MODE_0,
8285                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
8286
8287         /* WaDisable_RenderCache_OperationalFlush:ilk */
8288         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8289
8290         g4x_disable_trickle_feed(dev_priv);
8291
8292         ibx_init_clock_gating(dev_priv);
8293 }
8294
8295 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
8296 {
8297         int pipe;
8298         uint32_t val;
8299
8300         /*
8301          * On Ibex Peak and Cougar Point, we need to disable clock
8302          * gating for the panel power sequencer or it will fail to
8303          * start up when no ports are active.
8304          */
8305         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
8306                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
8307                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
8308         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8309                    DPLS_EDP_PPS_FIX_DIS);
8310         /* The below fixes the weird display corruption, a few pixels shifted
8311          * downward, on (only) LVDS of some HP laptops with IVY.
8312          */
8313         for_each_pipe(dev_priv, pipe) {
8314                 val = I915_READ(TRANS_CHICKEN2(pipe));
8315                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
8316                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
8317                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
8318                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
8319                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
8320                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
8321                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
8322                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
8323         }
8324         /* WADP0ClockGatingDisable */
8325         for_each_pipe(dev_priv, pipe) {
8326                 I915_WRITE(TRANS_CHICKEN1(pipe),
8327                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
8328         }
8329 }
8330
8331 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
8332 {
8333         uint32_t tmp;
8334
8335         tmp = I915_READ(MCH_SSKPD);
8336         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
8337                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
8338                               tmp);
8339 }
8340
8341 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
8342 {
8343         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
8344
8345         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
8346
8347         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8348                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8349                    ILK_ELPIN_409_SELECT);
8350
8351         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
8352         I915_WRITE(_3D_CHICKEN,
8353                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
8354
8355         /* WaDisable_RenderCache_OperationalFlush:snb */
8356         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8357
8358         /*
8359          * BSpec recoomends 8x4 when MSAA is used,
8360          * however in practice 16x4 seems fastest.
8361          *
8362          * Note that PS/WM thread counts depend on the WIZ hashing
8363          * disable bit, which we don't touch here, but it's good
8364          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8365          */
8366         I915_WRITE(GEN6_GT_MODE,
8367                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8368
8369         ilk_init_lp_watermarks(dev_priv);
8370
8371         I915_WRITE(CACHE_MODE_0,
8372                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
8373
8374         I915_WRITE(GEN6_UCGCTL1,
8375                    I915_READ(GEN6_UCGCTL1) |
8376                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
8377                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
8378
8379         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8380          * gating disable must be set.  Failure to set it results in
8381          * flickering pixels due to Z write ordering failures after
8382          * some amount of runtime in the Mesa "fire" demo, and Unigine
8383          * Sanctuary and Tropics, and apparently anything else with
8384          * alpha test or pixel discard.
8385          *
8386          * According to the spec, bit 11 (RCCUNIT) must also be set,
8387          * but we didn't debug actual testcases to find it out.
8388          *
8389          * WaDisableRCCUnitClockGating:snb
8390          * WaDisableRCPBUnitClockGating:snb
8391          */
8392         I915_WRITE(GEN6_UCGCTL2,
8393                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8394                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8395
8396         /* WaStripsFansDisableFastClipPerformanceFix:snb */
8397         I915_WRITE(_3D_CHICKEN3,
8398                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
8399
8400         /*
8401          * Bspec says:
8402          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
8403          * 3DSTATE_SF number of SF output attributes is more than 16."
8404          */
8405         I915_WRITE(_3D_CHICKEN3,
8406                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
8407
8408         /*
8409          * According to the spec the following bits should be
8410          * set in order to enable memory self-refresh and fbc:
8411          * The bit21 and bit22 of 0x42000
8412          * The bit21 and bit22 of 0x42004
8413          * The bit5 and bit7 of 0x42020
8414          * The bit14 of 0x70180
8415          * The bit14 of 0x71180
8416          *
8417          * WaFbcAsynchFlipDisableFbcQueue:snb
8418          */
8419         I915_WRITE(ILK_DISPLAY_CHICKEN1,
8420                    I915_READ(ILK_DISPLAY_CHICKEN1) |
8421                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8422         I915_WRITE(ILK_DISPLAY_CHICKEN2,
8423                    I915_READ(ILK_DISPLAY_CHICKEN2) |
8424                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8425         I915_WRITE(ILK_DSPCLK_GATE_D,
8426                    I915_READ(ILK_DSPCLK_GATE_D) |
8427                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
8428                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
8429
8430         g4x_disable_trickle_feed(dev_priv);
8431
8432         cpt_init_clock_gating(dev_priv);
8433
8434         gen6_check_mch_setup(dev_priv);
8435 }
8436
8437 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
8438 {
8439         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
8440
8441         /*
8442          * WaVSThreadDispatchOverride:ivb,vlv
8443          *
8444          * This actually overrides the dispatch
8445          * mode for all thread types.
8446          */
8447         reg &= ~GEN7_FF_SCHED_MASK;
8448         reg |= GEN7_FF_TS_SCHED_HW;
8449         reg |= GEN7_FF_VS_SCHED_HW;
8450         reg |= GEN7_FF_DS_SCHED_HW;
8451
8452         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
8453 }
8454
8455 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
8456 {
8457         /*
8458          * TODO: this bit should only be enabled when really needed, then
8459          * disabled when not needed anymore in order to save power.
8460          */
8461         if (HAS_PCH_LPT_LP(dev_priv))
8462                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
8463                            I915_READ(SOUTH_DSPCLK_GATE_D) |
8464                            PCH_LP_PARTITION_LEVEL_DISABLE);
8465
8466         /* WADPOClockGatingDisable:hsw */
8467         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
8468                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
8469                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
8470 }
8471
8472 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
8473 {
8474         if (HAS_PCH_LPT_LP(dev_priv)) {
8475                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
8476
8477                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8478                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8479         }
8480 }
8481
8482 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
8483                                    int general_prio_credits,
8484                                    int high_prio_credits)
8485 {
8486         u32 misccpctl;
8487
8488         /* WaTempDisableDOPClkGating:bdw */
8489         misccpctl = I915_READ(GEN7_MISCCPCTL);
8490         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
8491
8492         I915_WRITE(GEN8_L3SQCREG1,
8493                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
8494                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
8495
8496         /*
8497          * Wait at least 100 clocks before re-enabling clock gating.
8498          * See the definition of L3SQCREG1 in BSpec.
8499          */
8500         POSTING_READ(GEN8_L3SQCREG1);
8501         udelay(1);
8502         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
8503 }
8504
8505 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
8506 {
8507         if (!HAS_PCH_CNP(dev_priv))
8508                 return;
8509
8510         /* Wa #1181 */
8511         I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
8512                    CNP_PWM_CGE_GATING_DISABLE);
8513 }
8514
8515 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
8516 {
8517         u32 val;
8518         cnp_init_clock_gating(dev_priv);
8519
8520         /* This is not an Wa. Enable for better image quality */
8521         I915_WRITE(_3D_CHICKEN3,
8522                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
8523
8524         /* WaEnableChickenDCPR:cnl */
8525         I915_WRITE(GEN8_CHICKEN_DCPR_1,
8526                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
8527
8528         /* WaFbcWakeMemOn:cnl */
8529         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
8530                    DISP_FBC_MEMORY_WAKE);
8531
8532         /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
8533         if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
8534                 I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
8535                            I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
8536                            SARBUNIT_CLKGATE_DIS);
8537
8538         /* Display WA #1133: WaFbcSkipSegments:cnl */
8539         val = I915_READ(ILK_DPFC_CHICKEN);
8540         val &= ~GLK_SKIP_SEG_COUNT_MASK;
8541         val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
8542         I915_WRITE(ILK_DPFC_CHICKEN, val);
8543 }
8544
8545 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
8546 {
8547         cnp_init_clock_gating(dev_priv);
8548         gen9_init_clock_gating(dev_priv);
8549
8550         /* WaFbcNukeOnHostModify:cfl */
8551         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8552                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8553 }
8554
8555 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
8556 {
8557         gen9_init_clock_gating(dev_priv);
8558
8559         /* WaDisableSDEUnitClockGating:kbl */
8560         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
8561                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8562                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8563
8564         /* WaDisableGamClockGating:kbl */
8565         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
8566                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
8567                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
8568
8569         /* WaFbcNukeOnHostModify:kbl */
8570         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8571                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8572 }
8573
8574 static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
8575 {
8576         gen9_init_clock_gating(dev_priv);
8577
8578         /* WAC6entrylatency:skl */
8579         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
8580                    FBC_LLC_FULLY_OPEN);
8581
8582         /* WaFbcNukeOnHostModify:skl */
8583         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
8584                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
8585 }
8586
8587 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
8588 {
8589         /* The GTT cache must be disabled if the system is using 2M pages. */
8590         bool can_use_gtt_cache = !HAS_PAGE_SIZES(dev_priv,
8591                                                  I915_GTT_PAGE_SIZE_2M);
8592         enum pipe pipe;
8593
8594         ilk_init_lp_watermarks(dev_priv);
8595
8596         /* WaSwitchSolVfFArbitrationPriority:bdw */
8597         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
8598
8599         /* WaPsrDPAMaskVBlankInSRD:bdw */
8600         I915_WRITE(CHICKEN_PAR1_1,
8601                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
8602
8603         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
8604         for_each_pipe(dev_priv, pipe) {
8605                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
8606                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
8607                            BDW_DPRS_MASK_VBLANK_SRD);
8608         }
8609
8610         /* WaVSRefCountFullforceMissDisable:bdw */
8611         /* WaDSRefCountFullforceMissDisable:bdw */
8612         I915_WRITE(GEN7_FF_THREAD_MODE,
8613                    I915_READ(GEN7_FF_THREAD_MODE) &
8614                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
8615
8616         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
8617                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
8618
8619         /* WaDisableSDEUnitClockGating:bdw */
8620         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8621                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8622
8623         /* WaProgramL3SqcReg1Default:bdw */
8624         gen8_set_l3sqc_credits(dev_priv, 30, 2);
8625
8626         /* WaGttCachingOffByDefault:bdw */
8627         I915_WRITE(HSW_GTT_CACHE_EN, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0);
8628
8629         /* WaKVMNotificationOnConfigChange:bdw */
8630         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
8631                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
8632
8633         lpt_init_clock_gating(dev_priv);
8634
8635         /* WaDisableDopClockGating:bdw
8636          *
8637          * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
8638          * clock gating.
8639          */
8640         I915_WRITE(GEN6_UCGCTL1,
8641                    I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
8642 }
8643
8644 static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
8645 {
8646         ilk_init_lp_watermarks(dev_priv);
8647
8648         /* L3 caching of data atomics doesn't work -- disable it. */
8649         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
8650         I915_WRITE(HSW_ROW_CHICKEN3,
8651                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
8652
8653         /* This is required by WaCatErrorRejectionIssue:hsw */
8654         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8655                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8656                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8657
8658         /* WaVSRefCountFullforceMissDisable:hsw */
8659         I915_WRITE(GEN7_FF_THREAD_MODE,
8660                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
8661
8662         /* WaDisable_RenderCache_OperationalFlush:hsw */
8663         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8664
8665         /* enable HiZ Raw Stall Optimization */
8666         I915_WRITE(CACHE_MODE_0_GEN7,
8667                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
8668
8669         /* WaDisable4x2SubspanOptimization:hsw */
8670         I915_WRITE(CACHE_MODE_1,
8671                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8672
8673         /*
8674          * BSpec recommends 8x4 when MSAA is used,
8675          * however in practice 16x4 seems fastest.
8676          *
8677          * Note that PS/WM thread counts depend on the WIZ hashing
8678          * disable bit, which we don't touch here, but it's good
8679          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8680          */
8681         I915_WRITE(GEN7_GT_MODE,
8682                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8683
8684         /* WaSampleCChickenBitEnable:hsw */
8685         I915_WRITE(HALF_SLICE_CHICKEN3,
8686                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
8687
8688         /* WaSwitchSolVfFArbitrationPriority:hsw */
8689         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
8690
8691         /* WaRsPkgCStateDisplayPMReq:hsw */
8692         I915_WRITE(CHICKEN_PAR1_1,
8693                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
8694
8695         lpt_init_clock_gating(dev_priv);
8696 }
8697
8698 static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
8699 {
8700         uint32_t snpcr;
8701
8702         ilk_init_lp_watermarks(dev_priv);
8703
8704         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
8705
8706         /* WaDisableEarlyCull:ivb */
8707         I915_WRITE(_3D_CHICKEN3,
8708                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
8709
8710         /* WaDisableBackToBackFlipFix:ivb */
8711         I915_WRITE(IVB_CHICKEN3,
8712                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8713                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8714
8715         /* WaDisablePSDDualDispatchEnable:ivb */
8716         if (IS_IVB_GT1(dev_priv))
8717                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
8718                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
8719
8720         /* WaDisable_RenderCache_OperationalFlush:ivb */
8721         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8722
8723         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
8724         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8725                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8726
8727         /* WaApplyL3ControlAndL3ChickenMode:ivb */
8728         I915_WRITE(GEN7_L3CNTLREG1,
8729                         GEN7_WA_FOR_GEN7_L3_CONTROL);
8730         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8731                    GEN7_WA_L3_CHICKEN_MODE);
8732         if (IS_IVB_GT1(dev_priv))
8733                 I915_WRITE(GEN7_ROW_CHICKEN2,
8734                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8735         else {
8736                 /* must write both registers */
8737                 I915_WRITE(GEN7_ROW_CHICKEN2,
8738                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8739                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
8740                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8741         }
8742
8743         /* WaForceL3Serialization:ivb */
8744         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
8745                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
8746
8747         /*
8748          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8749          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
8750          */
8751         I915_WRITE(GEN6_UCGCTL2,
8752                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8753
8754         /* This is required by WaCatErrorRejectionIssue:ivb */
8755         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8756                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8757                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8758
8759         g4x_disable_trickle_feed(dev_priv);
8760
8761         gen7_setup_fixed_func_scheduler(dev_priv);
8762
8763         if (0) { /* causes HiZ corruption on ivb:gt1 */
8764                 /* enable HiZ Raw Stall Optimization */
8765                 I915_WRITE(CACHE_MODE_0_GEN7,
8766                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
8767         }
8768
8769         /* WaDisable4x2SubspanOptimization:ivb */
8770         I915_WRITE(CACHE_MODE_1,
8771                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8772
8773         /*
8774          * BSpec recommends 8x4 when MSAA is used,
8775          * however in practice 16x4 seems fastest.
8776          *
8777          * Note that PS/WM thread counts depend on the WIZ hashing
8778          * disable bit, which we don't touch here, but it's good
8779          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8780          */
8781         I915_WRITE(GEN7_GT_MODE,
8782                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8783
8784         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
8785         snpcr &= ~GEN6_MBC_SNPCR_MASK;
8786         snpcr |= GEN6_MBC_SNPCR_MED;
8787         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
8788
8789         if (!HAS_PCH_NOP(dev_priv))
8790                 cpt_init_clock_gating(dev_priv);
8791
8792         gen6_check_mch_setup(dev_priv);
8793 }
8794
8795 static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
8796 {
8797         /* WaDisableEarlyCull:vlv */
8798         I915_WRITE(_3D_CHICKEN3,
8799                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
8800
8801         /* WaDisableBackToBackFlipFix:vlv */
8802         I915_WRITE(IVB_CHICKEN3,
8803                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8804                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
8805
8806         /* WaPsdDispatchEnable:vlv */
8807         /* WaDisablePSDDualDispatchEnable:vlv */
8808         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
8809                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
8810                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
8811
8812         /* WaDisable_RenderCache_OperationalFlush:vlv */
8813         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8814
8815         /* WaForceL3Serialization:vlv */
8816         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
8817                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
8818
8819         /* WaDisableDopClockGating:vlv */
8820         I915_WRITE(GEN7_ROW_CHICKEN2,
8821                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8822
8823         /* This is required by WaCatErrorRejectionIssue:vlv */
8824         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8825                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8826                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8827
8828         gen7_setup_fixed_func_scheduler(dev_priv);
8829
8830         /*
8831          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8832          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
8833          */
8834         I915_WRITE(GEN6_UCGCTL2,
8835                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8836
8837         /* WaDisableL3Bank2xClockGate:vlv
8838          * Disabling L3 clock gating- MMIO 940c[25] = 1
8839          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
8840         I915_WRITE(GEN7_UCGCTL4,
8841                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
8842
8843         /*
8844          * BSpec says this must be set, even though
8845          * WaDisable4x2SubspanOptimization isn't listed for VLV.
8846          */
8847         I915_WRITE(CACHE_MODE_1,
8848                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
8849
8850         /*
8851          * BSpec recommends 8x4 when MSAA is used,
8852          * however in practice 16x4 seems fastest.
8853          *
8854          * Note that PS/WM thread counts depend on the WIZ hashing
8855          * disable bit, which we don't touch here, but it's good
8856          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8857          */
8858         I915_WRITE(GEN7_GT_MODE,
8859                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8860
8861         /*
8862          * WaIncreaseL3CreditsForVLVB0:vlv
8863          * This is the hardware default actually.
8864          */
8865         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
8866
8867         /*
8868          * WaDisableVLVClockGating_VBIIssue:vlv
8869          * Disable clock gating on th GCFG unit to prevent a delay
8870          * in the reporting of vblank events.
8871          */
8872         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
8873 }
8874
8875 static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
8876 {
8877         /* WaVSRefCountFullforceMissDisable:chv */
8878         /* WaDSRefCountFullforceMissDisable:chv */
8879         I915_WRITE(GEN7_FF_THREAD_MODE,
8880                    I915_READ(GEN7_FF_THREAD_MODE) &
8881                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
8882
8883         /* WaDisableSemaphoreAndSyncFlipWait:chv */
8884         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
8885                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
8886
8887         /* WaDisableCSUnitClockGating:chv */
8888         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
8889                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
8890
8891         /* WaDisableSDEUnitClockGating:chv */
8892         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
8893                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8894
8895         /*
8896          * WaProgramL3SqcReg1Default:chv
8897          * See gfxspecs/Related Documents/Performance Guide/
8898          * LSQC Setting Recommendations.
8899          */
8900         gen8_set_l3sqc_credits(dev_priv, 38, 2);
8901
8902         /*
8903          * GTT cache may not work with big pages, so if those
8904          * are ever enabled GTT cache may need to be disabled.
8905          */
8906         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
8907 }
8908
8909 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
8910 {
8911         uint32_t dspclk_gate;
8912
8913         I915_WRITE(RENCLK_GATE_D1, 0);
8914         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8915                    GS_UNIT_CLOCK_GATE_DISABLE |
8916                    CL_UNIT_CLOCK_GATE_DISABLE);
8917         I915_WRITE(RAMCLK_GATE_D, 0);
8918         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8919                 OVRUNIT_CLOCK_GATE_DISABLE |
8920                 OVCUNIT_CLOCK_GATE_DISABLE;
8921         if (IS_GM45(dev_priv))
8922                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8923         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8924
8925         /* WaDisableRenderCachePipelinedFlush */
8926         I915_WRITE(CACHE_MODE_0,
8927                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
8928
8929         /* WaDisable_RenderCache_OperationalFlush:g4x */
8930         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8931
8932         g4x_disable_trickle_feed(dev_priv);
8933 }
8934
8935 static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
8936 {
8937         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8938         I915_WRITE(RENCLK_GATE_D2, 0);
8939         I915_WRITE(DSPCLK_GATE_D, 0);
8940         I915_WRITE(RAMCLK_GATE_D, 0);
8941         I915_WRITE16(DEUC, 0);
8942         I915_WRITE(MI_ARB_STATE,
8943                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
8944
8945         /* WaDisable_RenderCache_OperationalFlush:gen4 */
8946         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8947 }
8948
8949 static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
8950 {
8951         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8952                    I965_RCC_CLOCK_GATE_DISABLE |
8953                    I965_RCPB_CLOCK_GATE_DISABLE |
8954                    I965_ISC_CLOCK_GATE_DISABLE |
8955                    I965_FBC_CLOCK_GATE_DISABLE);
8956         I915_WRITE(RENCLK_GATE_D2, 0);
8957         I915_WRITE(MI_ARB_STATE,
8958                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
8959
8960         /* WaDisable_RenderCache_OperationalFlush:gen4 */
8961         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
8962 }
8963
8964 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
8965 {
8966         u32 dstate = I915_READ(D_STATE);
8967
8968         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8969                 DSTATE_DOT_CLOCK_GATING;
8970         I915_WRITE(D_STATE, dstate);
8971
8972         if (IS_PINEVIEW(dev_priv))
8973                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
8974
8975         /* IIR "flip pending" means done if this bit is set */
8976         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
8977
8978         /* interrupts should cause a wake up from C3 */
8979         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
8980
8981         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
8982         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
8983
8984         I915_WRITE(MI_ARB_STATE,
8985                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
8986 }
8987
8988 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
8989 {
8990         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8991
8992         /* interrupts should cause a wake up from C3 */
8993         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
8994                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
8995
8996         I915_WRITE(MEM_MODE,
8997                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
8998 }
8999
9000 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
9001 {
9002         I915_WRITE(MEM_MODE,
9003                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
9004                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
9005 }
9006
9007 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
9008 {
9009         dev_priv->display.init_clock_gating(dev_priv);
9010 }
9011
9012 void intel_suspend_hw(struct drm_i915_private *dev_priv)
9013 {
9014         if (HAS_PCH_LPT(dev_priv))
9015                 lpt_suspend_hw(dev_priv);
9016 }
9017
9018 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
9019 {
9020         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
9021 }
9022
9023 /**
9024  * intel_init_clock_gating_hooks - setup the clock gating hooks
9025  * @dev_priv: device private
9026  *
9027  * Setup the hooks that configure which clocks of a given platform can be
9028  * gated and also apply various GT and display specific workarounds for these
9029  * platforms. Note that some GT specific workarounds are applied separately
9030  * when GPU contexts or batchbuffers start their execution.
9031  */
9032 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
9033 {
9034         if (IS_CANNONLAKE(dev_priv))
9035                 dev_priv->display.init_clock_gating = cnl_init_clock_gating;
9036         else if (IS_COFFEELAKE(dev_priv))
9037                 dev_priv->display.init_clock_gating = cfl_init_clock_gating;
9038         else if (IS_SKYLAKE(dev_priv))
9039                 dev_priv->display.init_clock_gating = skl_init_clock_gating;
9040         else if (IS_KABYLAKE(dev_priv))
9041                 dev_priv->display.init_clock_gating = kbl_init_clock_gating;
9042         else if (IS_BROXTON(dev_priv))
9043                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
9044         else if (IS_GEMINILAKE(dev_priv))
9045                 dev_priv->display.init_clock_gating = glk_init_clock_gating;
9046         else if (IS_BROADWELL(dev_priv))
9047                 dev_priv->display.init_clock_gating = bdw_init_clock_gating;
9048         else if (IS_CHERRYVIEW(dev_priv))
9049                 dev_priv->display.init_clock_gating = chv_init_clock_gating;
9050         else if (IS_HASWELL(dev_priv))
9051                 dev_priv->display.init_clock_gating = hsw_init_clock_gating;
9052         else if (IS_IVYBRIDGE(dev_priv))
9053                 dev_priv->display.init_clock_gating = ivb_init_clock_gating;
9054         else if (IS_VALLEYVIEW(dev_priv))
9055                 dev_priv->display.init_clock_gating = vlv_init_clock_gating;
9056         else if (IS_GEN6(dev_priv))
9057                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
9058         else if (IS_GEN5(dev_priv))
9059                 dev_priv->display.init_clock_gating = ilk_init_clock_gating;
9060         else if (IS_G4X(dev_priv))
9061                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
9062         else if (IS_I965GM(dev_priv))
9063                 dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
9064         else if (IS_I965G(dev_priv))
9065                 dev_priv->display.init_clock_gating = i965g_init_clock_gating;
9066         else if (IS_GEN3(dev_priv))
9067                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
9068         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
9069                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
9070         else if (IS_GEN2(dev_priv))
9071                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
9072         else {
9073                 MISSING_CASE(INTEL_DEVID(dev_priv));
9074                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
9075         }
9076 }
9077
9078 /* Set up chip specific power management-related functions */
9079 void intel_init_pm(struct drm_i915_private *dev_priv)
9080 {
9081         intel_fbc_init(dev_priv);
9082
9083         /* For cxsr */
9084         if (IS_PINEVIEW(dev_priv))
9085                 i915_pineview_get_mem_freq(dev_priv);
9086         else if (IS_GEN5(dev_priv))
9087                 i915_ironlake_get_mem_freq(dev_priv);
9088
9089         /* For FIFO watermark updates */
9090         if (INTEL_GEN(dev_priv) >= 9) {
9091                 skl_setup_wm_latency(dev_priv);
9092                 dev_priv->display.initial_watermarks = skl_initial_wm;
9093                 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
9094                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
9095         } else if (HAS_PCH_SPLIT(dev_priv)) {
9096                 ilk_setup_wm_latency(dev_priv);
9097
9098                 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
9099                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
9100                     (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
9101                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
9102                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
9103                         dev_priv->display.compute_intermediate_wm =
9104                                 ilk_compute_intermediate_wm;
9105                         dev_priv->display.initial_watermarks =
9106                                 ilk_initial_watermarks;
9107                         dev_priv->display.optimize_watermarks =
9108                                 ilk_optimize_watermarks;
9109                 } else {
9110                         DRM_DEBUG_KMS("Failed to read display plane latency. "
9111                                       "Disable CxSR\n");
9112                 }
9113         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
9114                 vlv_setup_wm_latency(dev_priv);
9115                 dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
9116                 dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
9117                 dev_priv->display.initial_watermarks = vlv_initial_watermarks;
9118                 dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
9119                 dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
9120         } else if (IS_G4X(dev_priv)) {
9121                 g4x_setup_wm_latency(dev_priv);
9122                 dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
9123                 dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
9124                 dev_priv->display.initial_watermarks = g4x_initial_watermarks;
9125                 dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
9126         } else if (IS_PINEVIEW(dev_priv)) {
9127                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
9128                                             dev_priv->is_ddr3,
9129                                             dev_priv->fsb_freq,
9130                                             dev_priv->mem_freq)) {
9131                         DRM_INFO("failed to find known CxSR latency "
9132                                  "(found ddr%s fsb freq %d, mem freq %d), "
9133                                  "disabling CxSR\n",
9134                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
9135                                  dev_priv->fsb_freq, dev_priv->mem_freq);
9136                         /* Disable CxSR and never update its watermark again */
9137                         intel_set_memory_cxsr(dev_priv, false);
9138                         dev_priv->display.update_wm = NULL;
9139                 } else
9140                         dev_priv->display.update_wm = pineview_update_wm;
9141         } else if (IS_GEN4(dev_priv)) {
9142                 dev_priv->display.update_wm = i965_update_wm;
9143         } else if (IS_GEN3(dev_priv)) {
9144                 dev_priv->display.update_wm = i9xx_update_wm;
9145                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
9146         } else if (IS_GEN2(dev_priv)) {
9147                 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
9148                         dev_priv->display.update_wm = i845_update_wm;
9149                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
9150                 } else {
9151                         dev_priv->display.update_wm = i9xx_update_wm;
9152                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
9153                 }
9154         } else {
9155                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
9156         }
9157 }
9158
9159 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
9160 {
9161         uint32_t flags =
9162                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
9163
9164         switch (flags) {
9165         case GEN6_PCODE_SUCCESS:
9166                 return 0;
9167         case GEN6_PCODE_UNIMPLEMENTED_CMD:
9168                 return -ENODEV;
9169         case GEN6_PCODE_ILLEGAL_CMD:
9170                 return -ENXIO;
9171         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
9172         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
9173                 return -EOVERFLOW;
9174         case GEN6_PCODE_TIMEOUT:
9175                 return -ETIMEDOUT;
9176         default:
9177                 MISSING_CASE(flags);
9178                 return 0;
9179         }
9180 }
9181
9182 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
9183 {
9184         uint32_t flags =
9185                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
9186
9187         switch (flags) {
9188         case GEN6_PCODE_SUCCESS:
9189                 return 0;
9190         case GEN6_PCODE_ILLEGAL_CMD:
9191                 return -ENXIO;
9192         case GEN7_PCODE_TIMEOUT:
9193                 return -ETIMEDOUT;
9194         case GEN7_PCODE_ILLEGAL_DATA:
9195                 return -EINVAL;
9196         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
9197                 return -EOVERFLOW;
9198         default:
9199                 MISSING_CASE(flags);
9200                 return 0;
9201         }
9202 }
9203
9204 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
9205 {
9206         int status;
9207
9208         WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
9209
9210         /* GEN6_PCODE_* are outside of the forcewake domain, we can
9211          * use te fw I915_READ variants to reduce the amount of work
9212          * required when reading/writing.
9213          */
9214
9215         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
9216                 DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps\n",
9217                                  mbox, __builtin_return_address(0));
9218                 return -EAGAIN;
9219         }
9220
9221         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
9222         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
9223         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
9224
9225         if (__intel_wait_for_register_fw(dev_priv,
9226                                          GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
9227                                          500, 0, NULL)) {
9228                 DRM_ERROR("timeout waiting for pcode read (from mbox %x) to finish for %ps\n",
9229                           mbox, __builtin_return_address(0));
9230                 return -ETIMEDOUT;
9231         }
9232
9233         *val = I915_READ_FW(GEN6_PCODE_DATA);
9234         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
9235
9236         if (INTEL_GEN(dev_priv) > 6)
9237                 status = gen7_check_mailbox_status(dev_priv);
9238         else
9239                 status = gen6_check_mailbox_status(dev_priv);
9240
9241         if (status) {
9242                 DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
9243                                  mbox, __builtin_return_address(0), status);
9244                 return status;
9245         }
9246
9247         return 0;
9248 }
9249
9250 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
9251                             u32 mbox, u32 val)
9252 {
9253         int status;
9254
9255         WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
9256
9257         /* GEN6_PCODE_* are outside of the forcewake domain, we can
9258          * use te fw I915_READ variants to reduce the amount of work
9259          * required when reading/writing.
9260          */
9261
9262         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
9263                 DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps\n",
9264                                  val, mbox, __builtin_return_address(0));
9265                 return -EAGAIN;
9266         }
9267
9268         I915_WRITE_FW(GEN6_PCODE_DATA, val);
9269         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
9270         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
9271
9272         if (__intel_wait_for_register_fw(dev_priv,
9273                                          GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
9274                                          500, 0, NULL)) {
9275                 DRM_ERROR("timeout waiting for pcode write of 0x%08x to mbox %x to finish for %ps\n",
9276                           val, mbox, __builtin_return_address(0));
9277                 return -ETIMEDOUT;
9278         }
9279
9280         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
9281
9282         if (INTEL_GEN(dev_priv) > 6)
9283                 status = gen7_check_mailbox_status(dev_priv);
9284         else
9285                 status = gen6_check_mailbox_status(dev_priv);
9286
9287         if (status) {
9288                 DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
9289                                  val, mbox, __builtin_return_address(0), status);
9290                 return status;
9291         }
9292
9293         return 0;
9294 }
9295
9296 static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
9297                                   u32 request, u32 reply_mask, u32 reply,
9298                                   u32 *status)
9299 {
9300         u32 val = request;
9301
9302         *status = sandybridge_pcode_read(dev_priv, mbox, &val);
9303
9304         return *status || ((val & reply_mask) == reply);
9305 }
9306
9307 /**
9308  * skl_pcode_request - send PCODE request until acknowledgment
9309  * @dev_priv: device private
9310  * @mbox: PCODE mailbox ID the request is targeted for
9311  * @request: request ID
9312  * @reply_mask: mask used to check for request acknowledgment
9313  * @reply: value used to check for request acknowledgment
9314  * @timeout_base_ms: timeout for polling with preemption enabled
9315  *
9316  * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
9317  * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
9318  * The request is acknowledged once the PCODE reply dword equals @reply after
9319  * applying @reply_mask. Polling is first attempted with preemption enabled
9320  * for @timeout_base_ms and if this times out for another 50 ms with
9321  * preemption disabled.
9322  *
9323  * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
9324  * other error as reported by PCODE.
9325  */
9326 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
9327                       u32 reply_mask, u32 reply, int timeout_base_ms)
9328 {
9329         u32 status;
9330         int ret;
9331
9332         WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
9333
9334 #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
9335                                    &status)
9336
9337         /*
9338          * Prime the PCODE by doing a request first. Normally it guarantees
9339          * that a subsequent request, at most @timeout_base_ms later, succeeds.
9340          * _wait_for() doesn't guarantee when its passed condition is evaluated
9341          * first, so send the first request explicitly.
9342          */
9343         if (COND) {
9344                 ret = 0;
9345                 goto out;
9346         }
9347         ret = _wait_for(COND, timeout_base_ms * 1000, 10);
9348         if (!ret)
9349                 goto out;
9350
9351         /*
9352          * The above can time out if the number of requests was low (2 in the
9353          * worst case) _and_ PCODE was busy for some reason even after a
9354          * (queued) request and @timeout_base_ms delay. As a workaround retry
9355          * the poll with preemption disabled to maximize the number of
9356          * requests. Increase the timeout from @timeout_base_ms to 50ms to
9357          * account for interrupts that could reduce the number of these
9358          * requests, and for any quirks of the PCODE firmware that delays
9359          * the request completion.
9360          */
9361         DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
9362         WARN_ON_ONCE(timeout_base_ms > 3);
9363         preempt_disable();
9364         ret = wait_for_atomic(COND, 50);
9365         preempt_enable();
9366
9367 out:
9368         return ret ? ret : status;
9369 #undef COND
9370 }
9371
9372 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
9373 {
9374         struct intel_rps *rps = &dev_priv->gt_pm.rps;
9375
9376         /*
9377          * N = val - 0xb7
9378          * Slow = Fast = GPLL ref * N
9379          */
9380         return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000);
9381 }
9382
9383 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
9384 {
9385         struct intel_rps *rps = &dev_priv->gt_pm.rps;
9386
9387         return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7;
9388 }
9389
9390 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
9391 {
9392         struct intel_rps *rps = &dev_priv->gt_pm.rps;
9393
9394         /*
9395          * N = val / 2
9396          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
9397          */
9398         return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000);
9399 }
9400
9401 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
9402 {
9403         struct intel_rps *rps = &dev_priv->gt_pm.rps;
9404
9405         /* CHV needs even values */
9406         return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2;
9407 }
9408
9409 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
9410 {
9411         if (INTEL_GEN(dev_priv) >= 9)
9412                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
9413                                          GEN9_FREQ_SCALER);
9414         else if (IS_CHERRYVIEW(dev_priv))
9415                 return chv_gpu_freq(dev_priv, val);
9416         else if (IS_VALLEYVIEW(dev_priv))
9417                 return byt_gpu_freq(dev_priv, val);
9418         else
9419                 return val * GT_FREQUENCY_MULTIPLIER;
9420 }
9421
9422 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
9423 {
9424         if (INTEL_GEN(dev_priv) >= 9)
9425                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
9426                                          GT_FREQUENCY_MULTIPLIER);
9427         else if (IS_CHERRYVIEW(dev_priv))
9428                 return chv_freq_opcode(dev_priv, val);
9429         else if (IS_VALLEYVIEW(dev_priv))
9430                 return byt_freq_opcode(dev_priv, val);
9431         else
9432                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
9433 }
9434
9435 void intel_pm_setup(struct drm_i915_private *dev_priv)
9436 {
9437         mutex_init(&dev_priv->pcu_lock);
9438
9439         INIT_DELAYED_WORK(&dev_priv->gt_pm.autoenable_work,
9440                           __intel_autoenable_gt_powersave);
9441         atomic_set(&dev_priv->gt_pm.rps.num_waiters, 0);
9442
9443         dev_priv->runtime_pm.suspended = false;
9444         atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
9445 }
9446
9447 static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
9448                              const i915_reg_t reg)
9449 {
9450         u32 lower, upper, tmp;
9451         int loop = 2;
9452
9453         /* The register accessed do not need forcewake. We borrow
9454          * uncore lock to prevent concurrent access to range reg.
9455          */
9456         spin_lock_irq(&dev_priv->uncore.lock);
9457
9458         /* vlv and chv residency counters are 40 bits in width.
9459          * With a control bit, we can choose between upper or lower
9460          * 32bit window into this counter.
9461          *
9462          * Although we always use the counter in high-range mode elsewhere,
9463          * userspace may attempt to read the value before rc6 is initialised,
9464          * before we have set the default VLV_COUNTER_CONTROL value. So always
9465          * set the high bit to be safe.
9466          */
9467         I915_WRITE_FW(VLV_COUNTER_CONTROL,
9468                       _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
9469         upper = I915_READ_FW(reg);
9470         do {
9471                 tmp = upper;
9472
9473                 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9474                               _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
9475                 lower = I915_READ_FW(reg);
9476
9477                 I915_WRITE_FW(VLV_COUNTER_CONTROL,
9478                               _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
9479                 upper = I915_READ_FW(reg);
9480         } while (upper != tmp && --loop);
9481
9482         /* Everywhere else we always use VLV_COUNTER_CONTROL with the
9483          * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
9484          * now.
9485          */
9486
9487         spin_unlock_irq(&dev_priv->uncore.lock);
9488
9489         return lower | (u64)upper << 8;
9490 }
9491
9492 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
9493                            const i915_reg_t reg)
9494 {
9495         u64 time_hw, units, div;
9496
9497         if (!intel_rc6_enabled())
9498                 return 0;
9499
9500         intel_runtime_pm_get(dev_priv);
9501
9502         /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
9503         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
9504                 units = 1000;
9505                 div = dev_priv->czclk_freq;
9506
9507                 time_hw = vlv_residency_raw(dev_priv, reg);
9508         } else if (IS_GEN9_LP(dev_priv)) {
9509                 units = 1000;
9510                 div = 1200;             /* 833.33ns */
9511
9512                 time_hw = I915_READ(reg);
9513         } else {
9514                 units = 128000; /* 1.28us */
9515                 div = 100000;
9516
9517                 time_hw = I915_READ(reg);
9518         }
9519
9520         intel_runtime_pm_put(dev_priv);
9521         return DIV_ROUND_UP_ULL(time_hw * units, div);
9522 }