2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * Author: Damien Lespiau <damien.lespiau@intel.com>
27 #include <linux/seq_file.h>
28 #include <linux/circ_buf.h>
29 #include <linux/ctype.h>
30 #include <linux/debugfs.h>
31 #include "intel_drv.h"
33 struct pipe_crc_info {
35 struct drm_i915_private *dev_priv;
39 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
41 struct pipe_crc_info *info = inode->i_private;
42 struct drm_i915_private *dev_priv = info->dev_priv;
43 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
45 if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
48 spin_lock_irq(&pipe_crc->lock);
50 if (pipe_crc->opened) {
51 spin_unlock_irq(&pipe_crc->lock);
52 return -EBUSY; /* already open */
55 pipe_crc->opened = true;
56 filep->private_data = inode->i_private;
58 spin_unlock_irq(&pipe_crc->lock);
63 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
65 struct pipe_crc_info *info = inode->i_private;
66 struct drm_i915_private *dev_priv = info->dev_priv;
67 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
69 spin_lock_irq(&pipe_crc->lock);
70 pipe_crc->opened = false;
71 spin_unlock_irq(&pipe_crc->lock);
76 /* (6 fields, 8 chars each, space separated (5) + '\n') */
77 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
78 /* account for \'0' */
79 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
81 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
83 lockdep_assert_held(&pipe_crc->lock);
84 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
85 INTEL_PIPE_CRC_ENTRIES_NR);
89 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
92 struct pipe_crc_info *info = filep->private_data;
93 struct drm_i915_private *dev_priv = info->dev_priv;
94 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
95 char buf[PIPE_CRC_BUFFER_LEN];
100 * Don't allow user space to provide buffers not big enough to hold
103 if (count < PIPE_CRC_LINE_LEN)
106 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
109 /* nothing to read */
110 spin_lock_irq(&pipe_crc->lock);
111 while (pipe_crc_data_count(pipe_crc) == 0) {
114 if (filep->f_flags & O_NONBLOCK) {
115 spin_unlock_irq(&pipe_crc->lock);
119 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
120 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
122 spin_unlock_irq(&pipe_crc->lock);
127 /* We now have one or more entries to read */
128 n_entries = count / PIPE_CRC_LINE_LEN;
131 while (n_entries > 0) {
132 struct intel_pipe_crc_entry *entry =
133 &pipe_crc->entries[pipe_crc->tail];
135 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
136 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
139 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
140 pipe_crc->tail = (pipe_crc->tail + 1) &
141 (INTEL_PIPE_CRC_ENTRIES_NR - 1);
143 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
144 "%8u %8x %8x %8x %8x %8x\n",
145 entry->frame, entry->crc[0],
146 entry->crc[1], entry->crc[2],
147 entry->crc[3], entry->crc[4]);
149 spin_unlock_irq(&pipe_crc->lock);
151 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
154 user_buf += PIPE_CRC_LINE_LEN;
157 spin_lock_irq(&pipe_crc->lock);
160 spin_unlock_irq(&pipe_crc->lock);
165 static const struct file_operations i915_pipe_crc_fops = {
166 .owner = THIS_MODULE,
167 .open = i915_pipe_crc_open,
168 .read = i915_pipe_crc_read,
169 .release = i915_pipe_crc_release,
172 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
174 .name = "i915_pipe_A_crc",
178 .name = "i915_pipe_B_crc",
182 .name = "i915_pipe_C_crc",
187 static const char * const pipe_crc_sources[] = {
200 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
202 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
203 return pipe_crc_sources[source];
206 static int display_crc_ctl_show(struct seq_file *m, void *data)
208 struct drm_i915_private *dev_priv = m->private;
211 for_each_pipe(dev_priv, pipe)
212 seq_printf(m, "%c %s\n", pipe_name(pipe),
213 pipe_crc_source_name(dev_priv->pipe_crc[pipe].source));
218 static int display_crc_ctl_open(struct inode *inode, struct file *file)
220 return single_open(file, display_crc_ctl_show, inode->i_private);
223 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
226 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
227 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
230 case INTEL_PIPE_CRC_SOURCE_PIPE:
231 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
233 case INTEL_PIPE_CRC_SOURCE_NONE:
243 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
245 enum intel_pipe_crc_source *source)
247 struct drm_device *dev = &dev_priv->drm;
248 struct intel_encoder *encoder;
249 struct intel_crtc *crtc;
250 struct intel_digital_port *dig_port;
253 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
255 drm_modeset_lock_all(dev);
256 for_each_intel_encoder(dev, encoder) {
257 if (!encoder->base.crtc)
260 crtc = to_intel_crtc(encoder->base.crtc);
262 if (crtc->pipe != pipe)
265 switch (encoder->type) {
266 case INTEL_OUTPUT_TVOUT:
267 *source = INTEL_PIPE_CRC_SOURCE_TV;
269 case INTEL_OUTPUT_DP:
270 case INTEL_OUTPUT_EDP:
271 dig_port = enc_to_dig_port(&encoder->base);
272 switch (dig_port->port) {
274 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
277 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
280 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
283 WARN(1, "nonexisting DP port %c\n",
284 port_name(dig_port->port));
292 drm_modeset_unlock_all(dev);
297 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
299 enum intel_pipe_crc_source *source,
302 bool need_stable_symbols = false;
304 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
305 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
311 case INTEL_PIPE_CRC_SOURCE_PIPE:
312 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
314 case INTEL_PIPE_CRC_SOURCE_DP_B:
315 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
316 need_stable_symbols = true;
318 case INTEL_PIPE_CRC_SOURCE_DP_C:
319 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
320 need_stable_symbols = true;
322 case INTEL_PIPE_CRC_SOURCE_DP_D:
323 if (!IS_CHERRYVIEW(dev_priv))
325 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
326 need_stable_symbols = true;
328 case INTEL_PIPE_CRC_SOURCE_NONE:
336 * When the pipe CRC tap point is after the transcoders we need
337 * to tweak symbol-level features to produce a deterministic series of
338 * symbols for a given frame. We need to reset those features only once
339 * a frame (instead of every nth symbol):
340 * - DC-balance: used to ensure a better clock recovery from the data
342 * - DisplayPort scrambling: used for EMI reduction
344 if (need_stable_symbols) {
345 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
347 tmp |= DC_BALANCE_RESET_VLV;
350 tmp |= PIPE_A_SCRAMBLE_RESET;
353 tmp |= PIPE_B_SCRAMBLE_RESET;
356 tmp |= PIPE_C_SCRAMBLE_RESET;
361 I915_WRITE(PORT_DFT2_G4X, tmp);
367 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
369 enum intel_pipe_crc_source *source,
372 bool need_stable_symbols = false;
374 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
375 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
381 case INTEL_PIPE_CRC_SOURCE_PIPE:
382 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
384 case INTEL_PIPE_CRC_SOURCE_TV:
385 if (!SUPPORTS_TV(dev_priv))
387 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
389 case INTEL_PIPE_CRC_SOURCE_DP_B:
390 if (!IS_G4X(dev_priv))
392 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
393 need_stable_symbols = true;
395 case INTEL_PIPE_CRC_SOURCE_DP_C:
396 if (!IS_G4X(dev_priv))
398 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
399 need_stable_symbols = true;
401 case INTEL_PIPE_CRC_SOURCE_DP_D:
402 if (!IS_G4X(dev_priv))
404 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
405 need_stable_symbols = true;
407 case INTEL_PIPE_CRC_SOURCE_NONE:
415 * When the pipe CRC tap point is after the transcoders we need
416 * to tweak symbol-level features to produce a deterministic series of
417 * symbols for a given frame. We need to reset those features only once
418 * a frame (instead of every nth symbol):
419 * - DC-balance: used to ensure a better clock recovery from the data
421 * - DisplayPort scrambling: used for EMI reduction
423 if (need_stable_symbols) {
424 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
426 WARN_ON(!IS_G4X(dev_priv));
428 I915_WRITE(PORT_DFT_I9XX,
429 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
432 tmp |= PIPE_A_SCRAMBLE_RESET;
434 tmp |= PIPE_B_SCRAMBLE_RESET;
436 I915_WRITE(PORT_DFT2_G4X, tmp);
442 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
445 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
449 tmp &= ~PIPE_A_SCRAMBLE_RESET;
452 tmp &= ~PIPE_B_SCRAMBLE_RESET;
455 tmp &= ~PIPE_C_SCRAMBLE_RESET;
460 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
461 tmp &= ~DC_BALANCE_RESET_VLV;
462 I915_WRITE(PORT_DFT2_G4X, tmp);
466 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
469 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
472 tmp &= ~PIPE_A_SCRAMBLE_RESET;
474 tmp &= ~PIPE_B_SCRAMBLE_RESET;
475 I915_WRITE(PORT_DFT2_G4X, tmp);
477 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
478 I915_WRITE(PORT_DFT_I9XX,
479 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
483 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
486 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
487 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
490 case INTEL_PIPE_CRC_SOURCE_PLANE1:
491 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
493 case INTEL_PIPE_CRC_SOURCE_PLANE2:
494 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
496 case INTEL_PIPE_CRC_SOURCE_PIPE:
497 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
499 case INTEL_PIPE_CRC_SOURCE_NONE:
509 static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
512 struct drm_device *dev = &dev_priv->drm;
513 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
514 struct intel_crtc_state *pipe_config;
515 struct drm_atomic_state *state;
516 struct drm_modeset_acquire_ctx ctx;
519 drm_modeset_acquire_init(&ctx, 0);
521 state = drm_atomic_state_alloc(dev);
527 state->acquire_ctx = &ctx;
530 pipe_config = intel_atomic_get_crtc_state(state, crtc);
531 if (IS_ERR(pipe_config)) {
532 ret = PTR_ERR(pipe_config);
536 if (HAS_IPS(dev_priv)) {
538 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
539 * enabled and disabled dynamically based on package C states,
540 * user space can't make reliable use of the CRCs, so let's just
541 * completely disable it.
543 pipe_config->ips_force_disable = enable;
544 if (pipe_config->ips_enabled == enable)
545 pipe_config->base.connectors_changed = true;
548 if (IS_HASWELL(dev_priv)) {
549 pipe_config->pch_pfit.force_thru = enable;
550 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
551 pipe_config->pch_pfit.enabled != enable)
552 pipe_config->base.connectors_changed = true;
555 ret = drm_atomic_commit(state);
558 if (ret == -EDEADLK) {
559 drm_atomic_state_clear(state);
560 drm_modeset_backoff(&ctx);
564 drm_atomic_state_put(state);
566 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
567 drm_modeset_drop_locks(&ctx);
568 drm_modeset_acquire_fini(&ctx);
571 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
573 enum intel_pipe_crc_source *source,
576 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
577 *source = INTEL_PIPE_CRC_SOURCE_PF;
580 case INTEL_PIPE_CRC_SOURCE_PLANE1:
581 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
583 case INTEL_PIPE_CRC_SOURCE_PLANE2:
584 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
586 case INTEL_PIPE_CRC_SOURCE_PF:
587 if ((IS_HASWELL(dev_priv) ||
588 IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
589 hsw_pipe_A_crc_wa(dev_priv, true);
591 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
593 case INTEL_PIPE_CRC_SOURCE_NONE:
603 static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
605 enum intel_pipe_crc_source *source, u32 *val)
607 if (IS_GEN2(dev_priv))
608 return i8xx_pipe_crc_ctl_reg(source, val);
609 else if (INTEL_GEN(dev_priv) < 5)
610 return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
611 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
612 return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
613 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
614 return ilk_pipe_crc_ctl_reg(source, val);
616 return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
619 static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
621 enum intel_pipe_crc_source source)
623 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
624 enum intel_display_power_domain power_domain;
625 u32 val = 0; /* shut up gcc */
628 if (pipe_crc->source == source)
631 /* forbid changing the source without going back to 'none' */
632 if (pipe_crc->source && source)
635 power_domain = POWER_DOMAIN_PIPE(pipe);
636 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
637 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
641 ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val);
645 /* none -> real source transition */
647 struct intel_pipe_crc_entry *entries;
649 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
650 pipe_name(pipe), pipe_crc_source_name(source));
652 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
653 sizeof(pipe_crc->entries[0]),
660 spin_lock_irq(&pipe_crc->lock);
661 kfree(pipe_crc->entries);
662 pipe_crc->entries = entries;
665 spin_unlock_irq(&pipe_crc->lock);
668 pipe_crc->source = source;
670 I915_WRITE(PIPE_CRC_CTL(pipe), val);
671 POSTING_READ(PIPE_CRC_CTL(pipe));
673 /* real source -> none transition */
675 struct intel_pipe_crc_entry *entries;
676 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
679 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
682 drm_modeset_lock(&crtc->base.mutex, NULL);
683 if (crtc->base.state->active)
684 intel_wait_for_vblank(dev_priv, pipe);
685 drm_modeset_unlock(&crtc->base.mutex);
687 spin_lock_irq(&pipe_crc->lock);
688 entries = pipe_crc->entries;
689 pipe_crc->entries = NULL;
692 spin_unlock_irq(&pipe_crc->lock);
696 if (IS_G4X(dev_priv))
697 g4x_undo_pipe_scramble_reset(dev_priv, pipe);
698 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
699 vlv_undo_pipe_scramble_reset(dev_priv, pipe);
700 else if ((IS_HASWELL(dev_priv) ||
701 IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
702 hsw_pipe_A_crc_wa(dev_priv, false);
708 intel_display_power_put(dev_priv, power_domain);
714 * Parse pipe CRC command strings:
715 * command: wsp* object wsp+ name wsp+ source wsp*
718 * source: (none | plane1 | plane2 | pf)
719 * wsp: (#0x20 | #0x9 | #0xA)+
722 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
723 * "pipe A none" -> Stop CRC
725 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
732 /* skip leading white space */
733 buf = skip_spaces(buf);
735 break; /* end of buffer */
737 /* find end of word */
738 for (end = buf; *end && !isspace(*end); end++)
741 if (n_words == max_words) {
742 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
744 return -EINVAL; /* ran out of words[] before bytes */
749 words[n_words++] = buf;
756 enum intel_pipe_crc_object {
757 PIPE_CRC_OBJECT_PIPE,
760 static const char * const pipe_crc_objects[] = {
765 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
769 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
770 if (!strcmp(buf, pipe_crc_objects[i])) {
778 static int display_crc_ctl_parse_pipe(struct drm_i915_private *dev_priv,
779 const char *buf, enum pipe *pipe)
781 const char name = buf[0];
783 if (name < 'A' || name >= pipe_name(INTEL_INFO(dev_priv)->num_pipes))
792 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
797 *s = INTEL_PIPE_CRC_SOURCE_NONE;
801 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
802 if (!strcmp(buf, pipe_crc_sources[i])) {
810 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
811 char *buf, size_t len)
815 char *words[N_WORDS];
817 enum intel_pipe_crc_object object;
818 enum intel_pipe_crc_source source;
820 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
821 if (n_words != N_WORDS) {
822 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
827 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
828 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
832 if (display_crc_ctl_parse_pipe(dev_priv, words[1], &pipe) < 0) {
833 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
837 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
838 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
842 return pipe_crc_set_source(dev_priv, pipe, source);
845 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
846 size_t len, loff_t *offp)
848 struct seq_file *m = file->private_data;
849 struct drm_i915_private *dev_priv = m->private;
856 if (len > PAGE_SIZE - 1) {
857 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
862 tmpbuf = memdup_user_nul(ubuf, len);
864 return PTR_ERR(tmpbuf);
866 ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
876 const struct file_operations i915_display_crc_ctl_fops = {
877 .owner = THIS_MODULE,
878 .open = display_crc_ctl_open,
881 .release = single_release,
882 .write = display_crc_ctl_write
885 void intel_display_crc_init(struct drm_i915_private *dev_priv)
889 for_each_pipe(dev_priv, pipe) {
890 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
892 pipe_crc->opened = false;
893 spin_lock_init(&pipe_crc->lock);
894 init_waitqueue_head(&pipe_crc->wq);
898 int intel_pipe_crc_create(struct drm_minor *minor)
900 struct drm_i915_private *dev_priv = to_i915(minor->dev);
904 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
905 struct pipe_crc_info *info = &i915_pipe_crc_data[i];
907 info->dev_priv = dev_priv;
908 ent = debugfs_create_file(info->name, S_IRUGO,
909 minor->debugfs_root, info,
910 &i915_pipe_crc_fops);
918 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
921 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
922 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
923 enum intel_display_power_domain power_domain;
924 enum intel_pipe_crc_source source;
925 u32 val = 0; /* shut up gcc */
928 if (display_crc_ctl_parse_source(source_name, &source) < 0) {
929 DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
933 power_domain = POWER_DOMAIN_PIPE(crtc->index);
934 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
935 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
939 ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val);
943 I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
944 POSTING_READ(PIPE_CRC_CTL(crtc->index));
947 if (IS_G4X(dev_priv))
948 g4x_undo_pipe_scramble_reset(dev_priv, crtc->index);
949 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
950 vlv_undo_pipe_scramble_reset(dev_priv, crtc->index);
951 else if ((IS_HASWELL(dev_priv) ||
952 IS_BROADWELL(dev_priv)) && crtc->index == PIPE_A)
953 hsw_pipe_A_crc_wa(dev_priv, false);
956 pipe_crc->skipped = 0;
960 intel_display_power_put(dev_priv, power_domain);