2 * Copyright (c) 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions: *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "intel_mocs.h"
24 #include "intel_lrc.h"
25 #include "intel_ringbuffer.h"
27 /* structures required */
28 struct drm_i915_mocs_entry {
33 struct drm_i915_mocs_table {
35 const struct drm_i915_mocs_entry *table;
38 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
39 #define LE_CACHEABILITY(value) ((value) << 0)
40 #define LE_TGT_CACHE(value) ((value) << 2)
41 #define LE_LRUM(value) ((value) << 4)
42 #define LE_AOM(value) ((value) << 6)
43 #define LE_RSC(value) ((value) << 7)
44 #define LE_SCC(value) ((value) << 8)
45 #define LE_PFM(value) ((value) << 11)
46 #define LE_SCF(value) ((value) << 14)
48 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
49 #define L3_ESC(value) ((value) << 0)
50 #define L3_SCC(value) ((value) << 1)
51 #define L3_CACHEABILITY(value) ((value) << 4)
54 #define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
56 /* (e)LLC caching options */
57 #define LE_PAGETABLE 0
62 /* L3 caching options */
76 * These are the MOCS tables that are programmed across all the rings.
77 * The control value is programmed to all the rings that support the
78 * MOCS registers. While the l3cc_values are only programmed to the
79 * LNCFCMOCS0 - LNCFCMOCS32 registers.
81 * These tables are intended to be kept reasonably consistent across
82 * platforms. However some of the fields are not applicable to all of
85 * Entries not part of the following tables are undefined as far as
86 * userspace is concerned and shouldn't be relied upon. For the time
87 * being they will be implicitly initialized to the strictest caching
88 * configuration (uncached) to guarantee forwards compatibility with
89 * userspace programs written against more recent kernels providing
90 * additional MOCS entries.
92 * NOTE: These tables MUST start with being uncached and the length
93 * MUST be less than 63 as the last two registers are reserved
94 * by the hardware. These tables are part of the kernel ABI and
95 * may only be updated incrementally by adding entries at the
98 static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
99 /* { 0x00000009, 0x0010 } */
100 { (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(0) |
101 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
102 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) },
103 /* { 0x00000038, 0x0030 } */
104 { (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
105 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
106 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) },
107 /* { 0x0000003b, 0x0030 } */
108 { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
109 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
110 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }
113 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
114 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
115 /* { 0x00000009, 0x0010 } */
116 { (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(0) |
117 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
118 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) },
119 /* { 0x00000038, 0x0030 } */
120 { (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
121 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
122 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) },
123 /* { 0x0000003b, 0x0030 } */
124 { (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
125 LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
126 (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }
130 * get_mocs_settings()
132 * @table: Output table that will be made to point at appropriate
133 * MOCS values for the device.
135 * This function will return the values of the MOCS table that needs to
136 * be programmed for the platform. It will return the values that need
137 * to be programmed and if they need to be programmed.
139 * Return: true if there are applicable MOCS settings for the device.
141 static bool get_mocs_settings(struct drm_device *dev,
142 struct drm_i915_mocs_table *table)
146 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
147 table->size = ARRAY_SIZE(skylake_mocs_table);
148 table->table = skylake_mocs_table;
150 } else if (IS_BROXTON(dev)) {
151 table->size = ARRAY_SIZE(broxton_mocs_table);
152 table->table = broxton_mocs_table;
155 WARN_ONCE(INTEL_INFO(dev)->gen >= 9,
156 "Platform that should have a MOCS table does not.\n");
162 static i915_reg_t mocs_register(enum intel_ring_id ring, int index)
166 return GEN9_GFX_MOCS(index);
168 return GEN9_MFX0_MOCS(index);
170 return GEN9_BLT_MOCS(index);
172 return GEN9_VEBOX_MOCS(index);
174 return GEN9_MFX1_MOCS(index);
177 return INVALID_MMIO_REG;
182 * emit_mocs_control_table() - emit the mocs control table
183 * @req: Request to set up the MOCS table for.
184 * @table: The values to program into the control regs.
185 * @ring: The engine for whom to emit the registers.
187 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
188 * given table starting at the given address.
190 * Return: 0 on success, otherwise the error status.
192 static int emit_mocs_control_table(struct drm_i915_gem_request *req,
193 const struct drm_i915_mocs_table *table,
194 enum intel_ring_id ring)
196 struct intel_ringbuffer *ringbuf = req->ringbuf;
200 if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
203 ret = intel_logical_ring_begin(req, 2 + 2 * GEN9_NUM_MOCS_ENTRIES);
205 DRM_DEBUG("intel_logical_ring_begin failed %d\n", ret);
209 intel_logical_ring_emit(ringbuf,
210 MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
212 for (index = 0; index < table->size; index++) {
213 intel_logical_ring_emit_reg(ringbuf, mocs_register(ring, index));
214 intel_logical_ring_emit(ringbuf,
215 table->table[index].control_value);
219 * Ok, now set the unused entries to uncached. These entries
220 * are officially undefined and no contract for the contents
221 * and settings is given for these entries.
223 * Entry 0 in the table is uncached - so we are just writing
224 * that value to all the used entries.
226 for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
227 intel_logical_ring_emit_reg(ringbuf, mocs_register(ring, index));
228 intel_logical_ring_emit(ringbuf, table->table[0].control_value);
231 intel_logical_ring_emit(ringbuf, MI_NOOP);
232 intel_logical_ring_advance(ringbuf);
238 * emit_mocs_l3cc_table() - emit the mocs control table
239 * @req: Request to set up the MOCS table for.
240 * @table: The values to program into the control regs.
242 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
243 * given table starting at the given address. This register set is
244 * programmed in pairs.
246 * Return: 0 on success, otherwise the error status.
248 static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
249 const struct drm_i915_mocs_table *table)
251 struct intel_ringbuffer *ringbuf = req->ringbuf;
255 u32 filler = (table->table[0].l3cc_value & 0xffff) |
256 ((table->table[0].l3cc_value & 0xffff) << 16);
259 if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
262 ret = intel_logical_ring_begin(req, 2 + GEN9_NUM_MOCS_ENTRIES);
264 DRM_DEBUG("intel_logical_ring_begin failed %d\n", ret);
268 intel_logical_ring_emit(ringbuf,
269 MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2));
271 for (i = 0, count = 0; i < table->size / 2; i++, count += 2) {
272 value = (table->table[count].l3cc_value & 0xffff) |
273 ((table->table[count + 1].l3cc_value & 0xffff) << 16);
275 intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
276 intel_logical_ring_emit(ringbuf, value);
279 if (table->size & 0x01) {
280 /* Odd table size - 1 left over */
281 value = (table->table[count].l3cc_value & 0xffff) |
282 ((table->table[0].l3cc_value & 0xffff) << 16);
287 * Now set the rest of the table to uncached - use entry 0 as
288 * this will be uncached. Leave the last pair uninitialised as
289 * they are reserved by the hardware.
291 for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
292 intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
293 intel_logical_ring_emit(ringbuf, value);
298 intel_logical_ring_emit(ringbuf, MI_NOOP);
299 intel_logical_ring_advance(ringbuf);
305 * intel_rcs_context_init_mocs() - program the MOCS register.
306 * @req: Request to set up the MOCS tables for.
308 * This function will emit a batch buffer with the values required for
309 * programming the MOCS register values for all the currently supported
312 * These registers are partially stored in the RCS context, so they are
313 * emitted at the same time so that when a context is created these registers
314 * are set up. These registers have to be emitted into the start of the
315 * context as setting the ELSP will re-init some of these registers back
318 * Return: 0 on success, otherwise the error status.
320 int intel_rcs_context_init_mocs(struct drm_i915_gem_request *req)
322 struct drm_i915_mocs_table t;
325 if (get_mocs_settings(req->ring->dev, &t)) {
326 struct drm_i915_private *dev_priv = req->i915;
327 struct intel_engine_cs *ring;
328 enum intel_ring_id ring_id;
330 /* Program the control registers */
331 for_each_ring(ring, dev_priv, ring_id) {
332 ret = emit_mocs_control_table(req, &t, ring_id);
337 /* Now program the l3cc registers */
338 ret = emit_mocs_l3cc_table(req, &t);