2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "i915_gem_render_state.h"
140 #include "i915_vgpu.h"
141 #include "intel_lrc_reg.h"
142 #include "intel_mocs.h"
143 #include "intel_workarounds.h"
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define GEN8_CTX_STATUS_COMPLETED_MASK \
160 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
162 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
163 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
164 #define WA_TAIL_DWORDS 2
165 #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
167 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
168 struct intel_engine_cs *engine,
169 struct intel_context *ce);
170 static void execlists_init_reg_state(u32 *reg_state,
171 struct i915_gem_context *ctx,
172 struct intel_engine_cs *engine,
173 struct intel_ring *ring);
175 static inline struct i915_priolist *to_priolist(struct rb_node *rb)
177 return rb_entry(rb, struct i915_priolist, node);
180 static inline int rq_prio(const struct i915_request *rq)
182 return rq->sched.attr.priority;
185 static inline bool need_preempt(const struct intel_engine_cs *engine,
186 const struct i915_request *last,
189 return (intel_engine_has_preemption(engine) &&
190 __execlists_need_preempt(prio, rq_prio(last)) &&
191 !i915_request_completed(last));
195 * The context descriptor encodes various attributes of a context,
196 * including its GTT address and some flags. Because it's fairly
197 * expensive to calculate, we'll just do it once and cache the result,
198 * which remains valid until the context is unpinned.
200 * This is what a descriptor looks like, from LSB to MSB::
202 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
203 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
204 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC)
205 * bits 53-54: mbz, reserved for use by hardware
206 * bits 55-63: group ID, currently unused and set to 0
208 * Starting from Gen11, the upper dword of the descriptor has a new format:
210 * bits 32-36: reserved
211 * bits 37-47: SW context ID
212 * bits 48:53: engine instance
213 * bit 54: mbz, reserved for use by hardware
214 * bits 55-60: SW counter
215 * bits 61-63: engine class
217 * engine info, SW context ID and SW counter need to form a unique number
218 * (Context ID) per lrc.
221 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
222 struct intel_engine_cs *engine,
223 struct intel_context *ce)
227 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH)));
228 BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH)));
230 desc = ctx->desc_template; /* bits 0-11 */
231 GEM_BUG_ON(desc & GENMASK_ULL(63, 12));
233 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
235 GEM_BUG_ON(desc & GENMASK_ULL(63, 32));
238 * The following 32bits are copied into the OA reports (dword 2).
239 * Consider updating oa_get_render_ctx_id in i915_perf.c when changing
242 if (INTEL_GEN(ctx->i915) >= 11) {
243 GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
244 desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
247 desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
250 /* TODO: decide what to do with SW counter (bits 55-60) */
252 desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
255 GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH));
256 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
262 static void unwind_wa_tail(struct i915_request *rq)
264 rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES);
265 assert_ring_tail_valid(rq->ring, rq->tail);
268 static void __unwind_incomplete_requests(struct intel_engine_cs *engine)
270 struct i915_request *rq, *rn, *active = NULL;
271 struct list_head *uninitialized_var(pl);
272 int prio = I915_PRIORITY_INVALID | I915_PRIORITY_NEWCLIENT;
274 lockdep_assert_held(&engine->timeline.lock);
276 list_for_each_entry_safe_reverse(rq, rn,
277 &engine->timeline.requests,
279 if (i915_request_completed(rq))
282 __i915_request_unsubmit(rq);
285 GEM_BUG_ON(rq->hw_context->active);
287 GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
288 if (rq_prio(rq) != prio) {
290 pl = i915_sched_lookup_priolist(engine, prio);
292 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
294 list_add(&rq->sched.link, pl);
300 * The active request is now effectively the start of a new client
301 * stream, so give it the equivalent small priority bump to prevent
302 * it being gazumped a second time by another peer.
304 if (!(prio & I915_PRIORITY_NEWCLIENT)) {
305 prio |= I915_PRIORITY_NEWCLIENT;
306 active->sched.attr.priority = prio;
307 list_move_tail(&active->sched.link,
308 i915_sched_lookup_priolist(engine, prio));
313 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
315 struct intel_engine_cs *engine =
316 container_of(execlists, typeof(*engine), execlists);
318 __unwind_incomplete_requests(engine);
322 execlists_context_status_change(struct i915_request *rq, unsigned long status)
325 * Only used when GVT-g is enabled now. When GVT-g is disabled,
326 * The compiler should eliminate this function as dead-code.
328 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
331 atomic_notifier_call_chain(&rq->engine->context_status_notifier,
336 execlists_user_begin(struct intel_engine_execlists *execlists,
337 const struct execlist_port *port)
339 execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER);
343 execlists_user_end(struct intel_engine_execlists *execlists)
345 execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
349 execlists_context_schedule_in(struct i915_request *rq)
351 GEM_BUG_ON(rq->hw_context->active);
353 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
354 intel_engine_context_in(rq->engine);
355 rq->hw_context->active = rq->engine;
359 execlists_context_schedule_out(struct i915_request *rq, unsigned long status)
361 rq->hw_context->active = NULL;
362 intel_engine_context_out(rq->engine);
363 execlists_context_status_change(rq, status);
364 trace_i915_request_out(rq);
368 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
370 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
371 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
372 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
373 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
376 static u64 execlists_update_context(struct i915_request *rq)
378 struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
379 struct intel_context *ce = rq->hw_context;
380 u32 *reg_state = ce->lrc_reg_state;
382 reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
385 * True 32b PPGTT with dynamic page allocation: update PDP
386 * registers and point the unallocated PDPs to scratch page.
387 * PML4 is allocated during ppgtt init, so this is not needed
390 if (!i915_vm_is_48bit(&ppgtt->vm))
391 execlists_update_context_pdps(ppgtt, reg_state);
394 * Make sure the context image is complete before we submit it to HW.
396 * Ostensibly, writes (including the WCB) should be flushed prior to
397 * an uncached write such as our mmio register access, the empirical
398 * evidence (esp. on Braswell) suggests that the WC write into memory
399 * may not be visible to the HW prior to the completion of the UC
400 * register write and that we may begin execution from the context
401 * before its image is complete leading to invalid PD chasing.
403 * Furthermore, Braswell, at least, wants a full mb to be sure that
404 * the writes are coherent in memory (visible to the GPU) prior to
405 * execution, and not just visible to other CPUs (as is the result of
412 static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)
414 if (execlists->ctrl_reg) {
415 writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
416 writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);
418 writel(upper_32_bits(desc), execlists->submit_reg);
419 writel(lower_32_bits(desc), execlists->submit_reg);
423 static void execlists_submit_ports(struct intel_engine_cs *engine)
425 struct intel_engine_execlists *execlists = &engine->execlists;
426 struct execlist_port *port = execlists->port;
430 * We can skip acquiring intel_runtime_pm_get() here as it was taken
431 * on our behalf by the request (see i915_gem_mark_busy()) and it will
432 * not be relinquished until the device is idle (see
433 * i915_gem_idle_work_handler()). As a precaution, we make sure
434 * that all ELSP are drained i.e. we have processed the CSB,
435 * before allowing ourselves to idle and calling intel_runtime_pm_put().
437 GEM_BUG_ON(!engine->i915->gt.awake);
440 * ELSQ note: the submit queue is not cleared after being submitted
441 * to the HW so we need to make sure we always clean it up. This is
442 * currently ensured by the fact that we always write the same number
443 * of elsq entries, keep this in mind before changing the loop below.
445 for (n = execlists_num_ports(execlists); n--; ) {
446 struct i915_request *rq;
450 rq = port_unpack(&port[n], &count);
452 GEM_BUG_ON(count > !n);
454 execlists_context_schedule_in(rq);
455 port_set(&port[n], port_pack(rq, count));
456 desc = execlists_update_context(rq);
457 GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
459 GEM_TRACE("%s in[%d]: ctx=%d.%d, global=%d (fence %llx:%d) (current %d), prio=%d\n",
461 port[n].context_id, count,
463 rq->fence.context, rq->fence.seqno,
464 intel_engine_get_seqno(engine),
471 write_desc(execlists, desc, n);
474 /* we need to manually load the submit queue */
475 if (execlists->ctrl_reg)
476 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
478 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
481 static bool ctx_single_port_submission(const struct intel_context *ce)
483 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
484 i915_gem_context_force_single_submission(ce->gem_context));
487 static bool can_merge_ctx(const struct intel_context *prev,
488 const struct intel_context *next)
493 if (ctx_single_port_submission(prev))
499 static void port_assign(struct execlist_port *port, struct i915_request *rq)
501 GEM_BUG_ON(rq == port_request(port));
503 if (port_isset(port))
504 i915_request_put(port_request(port));
506 port_set(port, port_pack(i915_request_get(rq), port_count(port)));
509 static void inject_preempt_context(struct intel_engine_cs *engine)
511 struct intel_engine_execlists *execlists = &engine->execlists;
512 struct intel_context *ce =
513 to_intel_context(engine->i915->preempt_context, engine);
516 GEM_BUG_ON(execlists->preempt_complete_status !=
517 upper_32_bits(ce->lrc_desc));
520 * Switch to our empty preempt context so
521 * the state of the GPU is known (idle).
523 GEM_TRACE("%s\n", engine->name);
524 for (n = execlists_num_ports(execlists); --n; )
525 write_desc(execlists, 0, n);
527 write_desc(execlists, ce->lrc_desc, n);
529 /* we need to manually load the submit queue */
530 if (execlists->ctrl_reg)
531 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
533 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
534 execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT);
537 static void complete_preempt_context(struct intel_engine_execlists *execlists)
539 GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT));
541 if (inject_preempt_hang(execlists))
544 execlists_cancel_port_requests(execlists);
545 __unwind_incomplete_requests(container_of(execlists,
546 struct intel_engine_cs,
550 static void execlists_dequeue(struct intel_engine_cs *engine)
552 struct intel_engine_execlists * const execlists = &engine->execlists;
553 struct execlist_port *port = execlists->port;
554 const struct execlist_port * const last_port =
555 &execlists->port[execlists->port_mask];
556 struct i915_request *last = port_request(port);
561 * Hardware submission is through 2 ports. Conceptually each port
562 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
563 * static for a context, and unique to each, so we only execute
564 * requests belonging to a single context from each ring. RING_HEAD
565 * is maintained by the CS in the context image, it marks the place
566 * where it got up to last time, and through RING_TAIL we tell the CS
567 * where we want to execute up to this time.
569 * In this list the requests are in order of execution. Consecutive
570 * requests from the same context are adjacent in the ringbuffer. We
571 * can combine these requests into a single RING_TAIL update:
573 * RING_HEAD...req1...req2
575 * since to execute req2 the CS must first execute req1.
577 * Our goal then is to point each port to the end of a consecutive
578 * sequence of requests as being the most optimal (fewest wake ups
579 * and context switches) submission.
584 * Don't resubmit or switch until all outstanding
585 * preemptions (lite-restore) are seen. Then we
586 * know the next preemption status we see corresponds
587 * to this ELSP update.
589 GEM_BUG_ON(!execlists_is_active(execlists,
590 EXECLISTS_ACTIVE_USER));
591 GEM_BUG_ON(!port_count(&port[0]));
594 * If we write to ELSP a second time before the HW has had
595 * a chance to respond to the previous write, we can confuse
596 * the HW and hit "undefined behaviour". After writing to ELSP,
597 * we must then wait until we see a context-switch event from
598 * the HW to indicate that it has had a chance to respond.
600 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
603 if (need_preempt(engine, last, execlists->queue_priority)) {
604 inject_preempt_context(engine);
609 * In theory, we could coalesce more requests onto
610 * the second port (the first port is active, with
611 * no preemptions pending). However, that means we
612 * then have to deal with the possible lite-restore
613 * of the second port (as we submit the ELSP, there
614 * may be a context-switch) but also we may complete
615 * the resubmission before the context-switch. Ergo,
616 * coalescing onto the second port will cause a
617 * preemption event, but we cannot predict whether
618 * that will affect port[0] or port[1].
620 * If the second port is already active, we can wait
621 * until the next context-switch before contemplating
622 * new requests. The GPU will be busy and we should be
623 * able to resubmit the new ELSP before it idles,
624 * avoiding pipeline bubbles (momentary pauses where
625 * the driver is unable to keep up the supply of new
626 * work). However, we have to double check that the
627 * priorities of the ports haven't been switch.
629 if (port_count(&port[1]))
633 * WaIdleLiteRestore:bdw,skl
634 * Apply the wa NOOPs to prevent
635 * ring:HEAD == rq:TAIL as we resubmit the
636 * request. See gen8_emit_breadcrumb() for
637 * where we prepare the padding after the
638 * end of the request.
640 last->tail = last->wa_tail;
643 while ((rb = rb_first_cached(&execlists->queue))) {
644 struct i915_priolist *p = to_priolist(rb);
645 struct i915_request *rq, *rn;
648 priolist_for_each_request_consume(rq, rn, p, i) {
650 need_preempt(engine, last, rq_prio(rq)));
653 * Can we combine this request with the current port?
654 * It has to be the same context/ringbuffer and not
655 * have any exceptions (e.g. GVT saying never to
658 * If we can combine the requests, we can execute both
659 * by updating the RING_TAIL to point to the end of the
660 * second request, and so we never need to tell the
661 * hardware about the first.
664 !can_merge_ctx(rq->hw_context, last->hw_context)) {
666 * If we are on the second port and cannot
667 * combine this request with the last, then we
670 if (port == last_port)
674 * If GVT overrides us we only ever submit
675 * port[0], leaving port[1] empty. Note that we
676 * also have to be careful that we don't queue
677 * the same context (even though a different
678 * request) to the second port.
680 if (ctx_single_port_submission(last->hw_context) ||
681 ctx_single_port_submission(rq->hw_context))
684 GEM_BUG_ON(last->hw_context == rq->hw_context);
687 port_assign(port, last);
690 GEM_BUG_ON(port_isset(port));
693 list_del_init(&rq->sched.link);
695 __i915_request_submit(rq);
696 trace_i915_request_in(rq, port_index(port, execlists));
702 rb_erase_cached(&p->node, &execlists->queue);
703 if (p->priority != I915_PRIORITY_NORMAL)
704 kmem_cache_free(engine->i915->priorities, p);
709 * Here be a bit of magic! Or sleight-of-hand, whichever you prefer.
711 * We choose queue_priority such that if we add a request of greater
712 * priority than this, we kick the submission tasklet to decide on
713 * the right order of submitting the requests to hardware. We must
714 * also be prepared to reorder requests as they are in-flight on the
715 * HW. We derive the queue_priority then as the first "hole" in
716 * the HW submission ports and if there are no available slots,
717 * the priority of the lowest executing request, i.e. last.
719 * When we do receive a higher priority request ready to run from the
720 * user, see queue_request(), the queue_priority is bumped to that
721 * request triggering preemption on the next dequeue (or subsequent
722 * interrupt for secondary ports).
724 execlists->queue_priority =
725 port != execlists->port ? rq_prio(last) : INT_MIN;
728 port_assign(port, last);
729 execlists_submit_ports(engine);
732 /* We must always keep the beast fed if we have work piled up */
733 GEM_BUG_ON(rb_first_cached(&execlists->queue) &&
734 !port_isset(execlists->port));
736 /* Re-evaluate the executing context setup after each preemptive kick */
738 execlists_user_begin(execlists, execlists->port);
740 /* If the engine is now idle, so should be the flag; and vice versa. */
741 GEM_BUG_ON(execlists_is_active(&engine->execlists,
742 EXECLISTS_ACTIVE_USER) ==
743 !port_isset(engine->execlists.port));
747 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
749 struct execlist_port *port = execlists->port;
750 unsigned int num_ports = execlists_num_ports(execlists);
752 while (num_ports-- && port_isset(port)) {
753 struct i915_request *rq = port_request(port);
755 GEM_TRACE("%s:port%u global=%d (fence %llx:%d), (current %d)\n",
757 (unsigned int)(port - execlists->port),
759 rq->fence.context, rq->fence.seqno,
760 intel_engine_get_seqno(rq->engine));
762 GEM_BUG_ON(!execlists->active);
763 execlists_context_schedule_out(rq,
764 i915_request_completed(rq) ?
765 INTEL_CONTEXT_SCHEDULE_OUT :
766 INTEL_CONTEXT_SCHEDULE_PREEMPTED);
768 i915_request_put(rq);
770 memset(port, 0, sizeof(*port));
774 execlists_clear_all_active(execlists);
777 static void reset_csb_pointers(struct intel_engine_execlists *execlists)
779 const unsigned int reset_value = GEN8_CSB_ENTRIES - 1;
782 * After a reset, the HW starts writing into CSB entry [0]. We
783 * therefore have to set our HEAD pointer back one entry so that
784 * the *first* entry we check is entry 0. To complicate this further,
785 * as we don't wait for the first interrupt after reset, we have to
786 * fake the HW write to point back to the last entry so that our
787 * inline comparison of our cached head position against the last HW
788 * write works even before the first interrupt.
790 execlists->csb_head = reset_value;
791 WRITE_ONCE(*execlists->csb_write, reset_value);
794 static void nop_submission_tasklet(unsigned long data)
796 /* The driver is wedged; don't process any more events. */
799 static void execlists_cancel_requests(struct intel_engine_cs *engine)
801 struct intel_engine_execlists * const execlists = &engine->execlists;
802 struct i915_request *rq, *rn;
806 GEM_TRACE("%s current %d\n",
807 engine->name, intel_engine_get_seqno(engine));
810 * Before we call engine->cancel_requests(), we should have exclusive
811 * access to the submission state. This is arranged for us by the
812 * caller disabling the interrupt generation, the tasklet and other
813 * threads that may then access the same state, giving us a free hand
814 * to reset state. However, we still need to let lockdep be aware that
815 * we know this state may be accessed in hardirq context, so we
816 * disable the irq around this manipulation and we want to keep
817 * the spinlock focused on its duties and not accidentally conflate
818 * coverage to the submission's irq state. (Similarly, although we
819 * shouldn't need to disable irq around the manipulation of the
820 * submission's irq state, we also wish to remind ourselves that
823 spin_lock_irqsave(&engine->timeline.lock, flags);
825 /* Cancel the requests on the HW and clear the ELSP tracker. */
826 execlists_cancel_port_requests(execlists);
827 execlists_user_end(execlists);
829 /* Mark all executing requests as skipped. */
830 list_for_each_entry(rq, &engine->timeline.requests, link) {
831 GEM_BUG_ON(!rq->global_seqno);
833 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
836 dma_fence_set_error(&rq->fence, -EIO);
839 /* Flush the queued requests to the timeline list (for retiring). */
840 while ((rb = rb_first_cached(&execlists->queue))) {
841 struct i915_priolist *p = to_priolist(rb);
844 priolist_for_each_request_consume(rq, rn, p, i) {
845 list_del_init(&rq->sched.link);
847 dma_fence_set_error(&rq->fence, -EIO);
848 __i915_request_submit(rq);
851 rb_erase_cached(&p->node, &execlists->queue);
852 if (p->priority != I915_PRIORITY_NORMAL)
853 kmem_cache_free(engine->i915->priorities, p);
856 intel_write_status_page(engine,
858 intel_engine_last_submit(engine));
860 /* Remaining _unready_ requests will be nop'ed when submitted */
862 execlists->queue_priority = INT_MIN;
863 execlists->queue = RB_ROOT_CACHED;
864 GEM_BUG_ON(port_isset(execlists->port));
866 GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet));
867 execlists->tasklet.func = nop_submission_tasklet;
869 spin_unlock_irqrestore(&engine->timeline.lock, flags);
873 reset_in_progress(const struct intel_engine_execlists *execlists)
875 return unlikely(!__tasklet_is_enabled(&execlists->tasklet));
878 static void process_csb(struct intel_engine_cs *engine)
880 struct intel_engine_execlists * const execlists = &engine->execlists;
881 struct execlist_port *port = execlists->port;
882 const u32 * const buf = execlists->csb_status;
886 * Note that csb_write, csb_status may be either in HWSP or mmio.
887 * When reading from the csb_write mmio register, we have to be
888 * careful to only use the GEN8_CSB_WRITE_PTR portion, which is
889 * the low 4bits. As it happens we know the next 4bits are always
890 * zero and so we can simply masked off the low u8 of the register
891 * and treat it identically to reading from the HWSP (without having
892 * to use explicit shifting and masking, and probably bifurcating
893 * the code to handle the legacy mmio read).
895 head = execlists->csb_head;
896 tail = READ_ONCE(*execlists->csb_write);
897 GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail);
898 if (unlikely(head == tail))
902 * Hopefully paired with a wmb() in HW!
904 * We must complete the read of the write pointer before any reads
905 * from the CSB, so that we do not see stale values. Without an rmb
906 * (lfence) the HW may speculatively perform the CSB[] reads *before*
907 * we perform the READ_ONCE(*csb_write).
912 struct i915_request *rq;
916 if (++head == GEN8_CSB_ENTRIES)
920 * We are flying near dragons again.
922 * We hold a reference to the request in execlist_port[]
923 * but no more than that. We are operating in softirq
924 * context and so cannot hold any mutex or sleep. That
925 * prevents us stopping the requests we are processing
926 * in port[] from being retired simultaneously (the
927 * breadcrumb will be complete before we see the
928 * context-switch). As we only hold the reference to the
929 * request, any pointer chasing underneath the request
930 * is subject to a potential use-after-free. Thus we
931 * store all of the bookkeeping within port[] as
932 * required, and avoid using unguarded pointers beneath
933 * request itself. The same applies to the atomic
937 GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n",
939 buf[2 * head + 0], buf[2 * head + 1],
942 status = buf[2 * head];
943 if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE |
944 GEN8_CTX_STATUS_PREEMPTED))
945 execlists_set_active(execlists,
946 EXECLISTS_ACTIVE_HWACK);
947 if (status & GEN8_CTX_STATUS_ACTIVE_IDLE)
948 execlists_clear_active(execlists,
949 EXECLISTS_ACTIVE_HWACK);
951 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
954 /* We should never get a COMPLETED | IDLE_ACTIVE! */
955 GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE);
957 if (status & GEN8_CTX_STATUS_COMPLETE &&
958 buf[2*head + 1] == execlists->preempt_complete_status) {
959 GEM_TRACE("%s preempt-idle\n", engine->name);
960 complete_preempt_context(execlists);
964 if (status & GEN8_CTX_STATUS_PREEMPTED &&
965 execlists_is_active(execlists,
966 EXECLISTS_ACTIVE_PREEMPT))
969 GEM_BUG_ON(!execlists_is_active(execlists,
970 EXECLISTS_ACTIVE_USER));
972 rq = port_unpack(port, &count);
973 GEM_TRACE("%s out[0]: ctx=%d.%d, global=%d (fence %llx:%d) (current %d), prio=%d\n",
975 port->context_id, count,
976 rq ? rq->global_seqno : 0,
977 rq ? rq->fence.context : 0,
978 rq ? rq->fence.seqno : 0,
979 intel_engine_get_seqno(engine),
980 rq ? rq_prio(rq) : 0);
982 /* Check the context/desc id for this event matches */
983 GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id);
985 GEM_BUG_ON(count == 0);
988 * On the final event corresponding to the
989 * submission of this context, we expect either
990 * an element-switch event or a completion
991 * event (and on completion, the active-idle
992 * marker). No more preemptions, lite-restore
995 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
996 GEM_BUG_ON(port_isset(&port[1]) &&
997 !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH));
998 GEM_BUG_ON(!port_isset(&port[1]) &&
999 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
1002 * We rely on the hardware being strongly
1003 * ordered, that the breadcrumb write is
1004 * coherent (visible from the CPU) before the
1005 * user interrupt and CSB is processed.
1007 GEM_BUG_ON(!i915_request_completed(rq));
1009 execlists_context_schedule_out(rq,
1010 INTEL_CONTEXT_SCHEDULE_OUT);
1011 i915_request_put(rq);
1013 GEM_TRACE("%s completed ctx=%d\n",
1014 engine->name, port->context_id);
1016 port = execlists_port_complete(execlists, port);
1017 if (port_isset(port))
1018 execlists_user_begin(execlists, port);
1020 execlists_user_end(execlists);
1022 port_set(port, port_pack(rq, count));
1024 } while (head != tail);
1026 execlists->csb_head = head;
1029 static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
1031 lockdep_assert_held(&engine->timeline.lock);
1033 process_csb(engine);
1034 if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT))
1035 execlists_dequeue(engine);
1039 * Check the unread Context Status Buffers and manage the submission of new
1040 * contexts to the ELSP accordingly.
1042 static void execlists_submission_tasklet(unsigned long data)
1044 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
1045 unsigned long flags;
1047 GEM_TRACE("%s awake?=%d, active=%x\n",
1049 engine->i915->gt.awake,
1050 engine->execlists.active);
1052 spin_lock_irqsave(&engine->timeline.lock, flags);
1053 __execlists_submission_tasklet(engine);
1054 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1057 static void queue_request(struct intel_engine_cs *engine,
1058 struct i915_sched_node *node,
1061 list_add_tail(&node->link, i915_sched_lookup_priolist(engine, prio));
1064 static void __submit_queue_imm(struct intel_engine_cs *engine)
1066 struct intel_engine_execlists * const execlists = &engine->execlists;
1068 if (reset_in_progress(execlists))
1069 return; /* defer until we restart the engine following reset */
1071 if (execlists->tasklet.func == execlists_submission_tasklet)
1072 __execlists_submission_tasklet(engine);
1074 tasklet_hi_schedule(&execlists->tasklet);
1077 static void submit_queue(struct intel_engine_cs *engine, int prio)
1079 if (prio > engine->execlists.queue_priority) {
1080 engine->execlists.queue_priority = prio;
1081 __submit_queue_imm(engine);
1085 static void execlists_submit_request(struct i915_request *request)
1087 struct intel_engine_cs *engine = request->engine;
1088 unsigned long flags;
1090 /* Will be called from irq-context when using foreign fences. */
1091 spin_lock_irqsave(&engine->timeline.lock, flags);
1093 queue_request(engine, &request->sched, rq_prio(request));
1095 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
1096 GEM_BUG_ON(list_empty(&request->sched.link));
1098 submit_queue(engine, rq_prio(request));
1100 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1103 static void execlists_context_destroy(struct intel_context *ce)
1105 GEM_BUG_ON(ce->pin_count);
1110 intel_ring_free(ce->ring);
1112 GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj));
1113 i915_gem_object_put(ce->state->obj);
1116 static void execlists_context_unpin(struct intel_context *ce)
1118 struct intel_engine_cs *engine;
1121 * The tasklet may still be using a pointer to our state, via an
1122 * old request. However, since we know we only unpin the context
1123 * on retirement of the following request, we know that the last
1124 * request referencing us will have had a completion CS interrupt.
1125 * If we see that it is still active, it means that the tasklet hasn't
1126 * had the chance to run yet; let it run before we teardown the
1127 * reference it may use.
1129 engine = READ_ONCE(ce->active);
1130 if (unlikely(engine)) {
1131 unsigned long flags;
1133 spin_lock_irqsave(&engine->timeline.lock, flags);
1134 process_csb(engine);
1135 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1137 GEM_BUG_ON(READ_ONCE(ce->active));
1140 i915_gem_context_unpin_hw_id(ce->gem_context);
1142 intel_ring_unpin(ce->ring);
1144 ce->state->obj->pin_global--;
1145 i915_gem_object_unpin_map(ce->state->obj);
1146 i915_vma_unpin(ce->state);
1148 i915_gem_context_put(ce->gem_context);
1151 static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
1157 * Clear this page out of any CPU caches for coherent swap-in/out.
1158 * We only want to do this on the first bind so that we do not stall
1159 * on an active context (which by nature is already on the GPU).
1161 if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1162 err = i915_gem_object_set_to_wc_domain(vma->obj, true);
1167 flags = PIN_GLOBAL | PIN_HIGH;
1168 flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
1170 return i915_vma_pin(vma, 0, 0, flags);
1173 static struct intel_context *
1174 __execlists_context_pin(struct intel_engine_cs *engine,
1175 struct i915_gem_context *ctx,
1176 struct intel_context *ce)
1181 ret = execlists_context_deferred_alloc(ctx, engine, ce);
1184 GEM_BUG_ON(!ce->state);
1186 ret = __context_pin(ctx, ce->state);
1190 vaddr = i915_gem_object_pin_map(ce->state->obj,
1191 i915_coherent_map_type(ctx->i915) |
1193 if (IS_ERR(vaddr)) {
1194 ret = PTR_ERR(vaddr);
1198 ret = intel_ring_pin(ce->ring);
1202 ret = i915_gem_context_pin_hw_id(ctx);
1206 intel_lr_context_descriptor_update(ctx, engine, ce);
1208 GEM_BUG_ON(!intel_ring_offset_valid(ce->ring, ce->ring->head));
1210 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
1211 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1212 i915_ggtt_offset(ce->ring->vma);
1213 ce->lrc_reg_state[CTX_RING_HEAD + 1] = ce->ring->head;
1214 ce->lrc_reg_state[CTX_RING_TAIL + 1] = ce->ring->tail;
1216 ce->state->obj->pin_global++;
1217 i915_gem_context_get(ctx);
1221 intel_ring_unpin(ce->ring);
1223 i915_gem_object_unpin_map(ce->state->obj);
1225 __i915_vma_unpin(ce->state);
1228 return ERR_PTR(ret);
1231 static const struct intel_context_ops execlists_context_ops = {
1232 .unpin = execlists_context_unpin,
1233 .destroy = execlists_context_destroy,
1236 static struct intel_context *
1237 execlists_context_pin(struct intel_engine_cs *engine,
1238 struct i915_gem_context *ctx)
1240 struct intel_context *ce = to_intel_context(ctx, engine);
1242 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1243 GEM_BUG_ON(!ctx->ppgtt);
1245 if (likely(ce->pin_count++))
1247 GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
1249 ce->ops = &execlists_context_ops;
1251 return __execlists_context_pin(engine, ctx, ce);
1254 static int execlists_request_alloc(struct i915_request *request)
1258 GEM_BUG_ON(!request->hw_context->pin_count);
1260 /* Flush enough space to reduce the likelihood of waiting after
1261 * we start building the request - in which case we will just
1262 * have to repeat work.
1264 request->reserved_space += EXECLISTS_REQUEST_SIZE;
1266 ret = intel_ring_wait_for_space(request->ring, request->reserved_space);
1270 /* Note that after this point, we have committed to using
1271 * this request as it is being used to both track the
1272 * state of engine initialisation and liveness of the
1273 * golden renderstate above. Think twice before you try
1274 * to cancel/unwind this request now.
1277 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
1282 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1283 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1284 * but there is a slight complication as this is applied in WA batch where the
1285 * values are only initialized once so we cannot take register value at the
1286 * beginning and reuse it further; hence we save its value to memory, upload a
1287 * constant value with bit21 set and then we restore it back with the saved value.
1288 * To simplify the WA, a constant value is formed by using the default value
1289 * of this register. This shouldn't be a problem because we are only modifying
1290 * it for a short period and this batch in non-premptible. We can ofcourse
1291 * use additional instructions that read the actual value of the register
1292 * at that time and set our bit of interest but it makes the WA complicated.
1294 * This WA is also required for Gen9 so extracting as a function avoids
1298 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
1300 /* NB no one else is allowed to scribble over scratch + 256! */
1301 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1302 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1303 *batch++ = i915_scratch_offset(engine->i915) + 256;
1306 *batch++ = MI_LOAD_REGISTER_IMM(1);
1307 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1308 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
1310 batch = gen8_emit_pipe_control(batch,
1311 PIPE_CONTROL_CS_STALL |
1312 PIPE_CONTROL_DC_FLUSH_ENABLE,
1315 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1316 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1317 *batch++ = i915_scratch_offset(engine->i915) + 256;
1324 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1325 * initialized at the beginning and shared across all contexts but this field
1326 * helps us to have multiple batches at different offsets and select them based
1327 * on a criteria. At the moment this batch always start at the beginning of the page
1328 * and at this point we don't have multiple wa_ctx batch buffers.
1330 * The number of WA applied are not known at the beginning; we use this field
1331 * to return the no of DWORDS written.
1333 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1334 * so it adds NOOPs as padding to make it cacheline aligned.
1335 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1336 * makes a complete batch buffer.
1338 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1340 /* WaDisableCtxRestoreArbitration:bdw,chv */
1341 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1343 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1344 if (IS_BROADWELL(engine->i915))
1345 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1347 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1348 /* Actual scratch location is at 128 bytes offset */
1349 batch = gen8_emit_pipe_control(batch,
1350 PIPE_CONTROL_FLUSH_L3 |
1351 PIPE_CONTROL_GLOBAL_GTT_IVB |
1352 PIPE_CONTROL_CS_STALL |
1353 PIPE_CONTROL_QW_WRITE,
1354 i915_scratch_offset(engine->i915) +
1355 2 * CACHELINE_BYTES);
1357 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1359 /* Pad to end of cacheline */
1360 while ((unsigned long)batch % CACHELINE_BYTES)
1364 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1365 * execution depends on the length specified in terms of cache lines
1366 * in the register CTX_RCS_INDIRECT_CTX
1377 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count)
1379 GEM_BUG_ON(!count || count > 63);
1381 *batch++ = MI_LOAD_REGISTER_IMM(count);
1383 *batch++ = i915_mmio_reg_offset(lri->reg);
1384 *batch++ = lri->value;
1385 } while (lri++, --count);
1391 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1393 static const struct lri lri[] = {
1394 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1396 COMMON_SLICE_CHICKEN2,
1397 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE,
1404 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX,
1405 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX),
1411 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX,
1412 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX),
1416 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1418 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1419 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1421 batch = emit_lri(batch, lri, ARRAY_SIZE(lri));
1423 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1424 if (HAS_POOLED_EU(engine->i915)) {
1426 * EU pool configuration is setup along with golden context
1427 * during context initialization. This value depends on
1428 * device type (2x6 or 3x6) and needs to be updated based
1429 * on which subslice is disabled especially for 2x6
1430 * devices, however it is safe to load default
1431 * configuration of 3x6 device instead of masking off
1432 * corresponding bits because HW ignores bits of a disabled
1433 * subslice and drops down to appropriate config. Please
1434 * see render_state_setup() in i915_gem_render_state.c for
1435 * possible configurations, to avoid duplication they are
1436 * not shown here again.
1438 *batch++ = GEN9_MEDIA_POOL_STATE;
1439 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1440 *batch++ = 0x00777000;
1446 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1448 /* Pad to end of cacheline */
1449 while ((unsigned long)batch % CACHELINE_BYTES)
1456 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1461 * WaPipeControlBefore3DStateSamplePattern: cnl
1463 * Ensure the engine is idle prior to programming a
1464 * 3DSTATE_SAMPLE_PATTERN during a context restore.
1466 batch = gen8_emit_pipe_control(batch,
1467 PIPE_CONTROL_CS_STALL,
1470 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for
1471 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in
1472 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is
1473 * confusing. Since gen8_emit_pipe_control() already advances the
1474 * batch by 6 dwords, we advance the other 10 here, completing a
1475 * cacheline. It's not clear if the workaround requires this padding
1476 * before other commands, or if it's just the regular padding we would
1477 * already have for the workaround bb, so leave it here for now.
1479 for (i = 0; i < 10; i++)
1482 /* Pad to end of cacheline */
1483 while ((unsigned long)batch % CACHELINE_BYTES)
1489 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1491 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
1493 struct drm_i915_gem_object *obj;
1494 struct i915_vma *vma;
1497 obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE);
1499 return PTR_ERR(obj);
1501 vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
1507 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
1511 engine->wa_ctx.vma = vma;
1515 i915_gem_object_put(obj);
1519 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
1521 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
1524 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1526 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1528 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1529 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
1531 wa_bb_func_t wa_bb_fn[2];
1533 void *batch, *batch_ptr;
1537 if (GEM_DEBUG_WARN_ON(engine->id != RCS))
1540 switch (INTEL_GEN(engine->i915)) {
1544 wa_bb_fn[0] = gen10_init_indirectctx_bb;
1548 wa_bb_fn[0] = gen9_init_indirectctx_bb;
1552 wa_bb_fn[0] = gen8_init_indirectctx_bb;
1556 MISSING_CASE(INTEL_GEN(engine->i915));
1560 ret = lrc_setup_wa_ctx(engine);
1562 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1566 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1567 batch = batch_ptr = kmap_atomic(page);
1570 * Emit the two workaround batch buffers, recording the offset from the
1571 * start of the workaround batch buffer object for each and their
1574 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
1575 wa_bb[i]->offset = batch_ptr - batch;
1576 if (GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset,
1577 CACHELINE_BYTES))) {
1582 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
1583 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
1586 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
1588 kunmap_atomic(batch);
1590 lrc_destroy_wa_ctx(engine);
1595 static void enable_execlists(struct intel_engine_cs *engine)
1597 struct drm_i915_private *dev_priv = engine->i915;
1599 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1602 * Make sure we're not enabling the new 12-deep CSB
1603 * FIFO as that requires a slightly updated handling
1604 * in the ctx switch irq. Since we're currently only
1605 * using only 2 elements of the enhanced execlists the
1606 * deeper FIFO it's not needed and it's not worth adding
1607 * more statements to the irq handler to support it.
1609 if (INTEL_GEN(dev_priv) >= 11)
1610 I915_WRITE(RING_MODE_GEN7(engine),
1611 _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
1613 I915_WRITE(RING_MODE_GEN7(engine),
1614 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1616 I915_WRITE(RING_MI_MODE(engine->mmio_base),
1617 _MASKED_BIT_DISABLE(STOP_RING));
1619 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1620 engine->status_page.ggtt_offset);
1621 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1624 static bool unexpected_starting_state(struct intel_engine_cs *engine)
1626 struct drm_i915_private *dev_priv = engine->i915;
1627 bool unexpected = false;
1629 if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) {
1630 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
1637 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1639 intel_engine_apply_workarounds(engine);
1641 intel_mocs_init_engine(engine);
1643 intel_engine_reset_breadcrumbs(engine);
1645 if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) {
1646 struct drm_printer p = drm_debug_printer(__func__);
1648 intel_engine_dump(engine, &p, NULL);
1651 enable_execlists(engine);
1656 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1658 struct drm_i915_private *dev_priv = engine->i915;
1661 ret = gen8_init_common_ring(engine);
1665 intel_engine_apply_whitelist(engine);
1667 /* We need to disable the AsyncFlip performance optimisations in order
1668 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1669 * programmed to '1' on all products.
1671 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1673 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1675 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1680 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1684 ret = gen8_init_common_ring(engine);
1688 intel_engine_apply_whitelist(engine);
1693 static struct i915_request *
1694 execlists_reset_prepare(struct intel_engine_cs *engine)
1696 struct intel_engine_execlists * const execlists = &engine->execlists;
1697 struct i915_request *request, *active;
1698 unsigned long flags;
1700 GEM_TRACE("%s: depth<-%d\n", engine->name,
1701 atomic_read(&execlists->tasklet.count));
1704 * Prevent request submission to the hardware until we have
1705 * completed the reset in i915_gem_reset_finish(). If a request
1706 * is completed by one engine, it may then queue a request
1707 * to a second via its execlists->tasklet *just* as we are
1708 * calling engine->init_hw() and also writing the ELSP.
1709 * Turning off the execlists->tasklet until the reset is over
1710 * prevents the race.
1712 __tasklet_disable_sync_once(&execlists->tasklet);
1714 spin_lock_irqsave(&engine->timeline.lock, flags);
1717 * We want to flush the pending context switches, having disabled
1718 * the tasklet above, we can assume exclusive access to the execlists.
1719 * For this allows us to catch up with an inflight preemption event,
1720 * and avoid blaming an innocent request if the stall was due to the
1721 * preemption itself.
1723 process_csb(engine);
1726 * The last active request can then be no later than the last request
1727 * now in ELSP[0]. So search backwards from there, so that if the GPU
1728 * has advanced beyond the last CSB update, it will be pardoned.
1731 request = port_request(execlists->port);
1734 * Prevent the breadcrumb from advancing before we decide
1735 * which request is currently active.
1737 intel_engine_stop_cs(engine);
1739 list_for_each_entry_from_reverse(request,
1740 &engine->timeline.requests,
1742 if (__i915_request_completed(request,
1743 request->global_seqno))
1750 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1755 static void execlists_reset(struct intel_engine_cs *engine,
1756 struct i915_request *request)
1758 struct intel_engine_execlists * const execlists = &engine->execlists;
1759 unsigned long flags;
1762 GEM_TRACE("%s request global=%d, current=%d\n",
1763 engine->name, request ? request->global_seqno : 0,
1764 intel_engine_get_seqno(engine));
1766 spin_lock_irqsave(&engine->timeline.lock, flags);
1769 * Catch up with any missed context-switch interrupts.
1771 * Ideally we would just read the remaining CSB entries now that we
1772 * know the gpu is idle. However, the CSB registers are sometimes^W
1773 * often trashed across a GPU reset! Instead we have to rely on
1774 * guessing the missed context-switch events by looking at what
1775 * requests were completed.
1777 execlists_cancel_port_requests(execlists);
1779 /* Push back any incomplete requests for replay after the reset. */
1780 __unwind_incomplete_requests(engine);
1782 /* Following the reset, we need to reload the CSB read/write pointers */
1783 reset_csb_pointers(&engine->execlists);
1785 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1788 * If the request was innocent, we leave the request in the ELSP
1789 * and will try to replay it on restarting. The context image may
1790 * have been corrupted by the reset, in which case we may have
1791 * to service a new GPU hang, but more likely we can continue on
1794 * If the request was guilty, we presume the context is corrupt
1795 * and have to at least restore the RING register in the context
1796 * image back to the expected values to skip over the guilty request.
1798 if (!request || request->fence.error != -EIO)
1802 * We want a simple context + ring to execute the breadcrumb update.
1803 * We cannot rely on the context being intact across the GPU hang,
1804 * so clear it and rebuild just what we need for the breadcrumb.
1805 * All pending requests for this context will be zapped, and any
1806 * future request will be after userspace has had the opportunity
1807 * to recreate its own state.
1809 regs = request->hw_context->lrc_reg_state;
1810 if (engine->pinned_default_state) {
1811 memcpy(regs, /* skip restoring the vanilla PPHWSP */
1812 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
1813 engine->context_size - PAGE_SIZE);
1815 execlists_init_reg_state(regs,
1816 request->gem_context, engine, request->ring);
1818 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1819 regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(request->ring->vma);
1821 request->ring->head = intel_ring_wrap(request->ring, request->postfix);
1822 regs[CTX_RING_HEAD + 1] = request->ring->head;
1824 intel_ring_update_space(request->ring);
1826 /* Reset WaIdleLiteRestore:bdw,skl as well */
1827 unwind_wa_tail(request);
1830 static void execlists_reset_finish(struct intel_engine_cs *engine)
1832 struct intel_engine_execlists * const execlists = &engine->execlists;
1835 * After a GPU reset, we may have requests to replay. Do so now while
1836 * we still have the forcewake to be sure that the GPU is not allowed
1837 * to sleep before we restart and reload a context.
1840 if (!RB_EMPTY_ROOT(&execlists->queue.rb_root))
1841 execlists->tasklet.func(execlists->tasklet.data);
1843 tasklet_enable(&execlists->tasklet);
1844 GEM_TRACE("%s: depth->%d\n", engine->name,
1845 atomic_read(&execlists->tasklet.count));
1848 static int intel_logical_ring_emit_pdps(struct i915_request *rq)
1850 struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
1851 struct intel_engine_cs *engine = rq->engine;
1852 const int num_lri_cmds = GEN8_3LVL_PDPES * 2;
1856 cs = intel_ring_begin(rq, num_lri_cmds * 2 + 2);
1860 *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds);
1861 for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) {
1862 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1864 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
1865 *cs++ = upper_32_bits(pd_daddr);
1866 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
1867 *cs++ = lower_32_bits(pd_daddr);
1871 intel_ring_advance(rq, cs);
1876 static int gen8_emit_bb_start(struct i915_request *rq,
1877 u64 offset, u32 len,
1878 const unsigned int flags)
1883 /* Don't rely in hw updating PDPs, specially in lite-restore.
1884 * Ideally, we should set Force PD Restore in ctx descriptor,
1885 * but we can't. Force Restore would be a second option, but
1886 * it is unsafe in case of lite-restore (because the ctx is
1887 * not idle). PML4 is allocated during ppgtt init so this is
1888 * not needed in 48-bit.*/
1889 if ((intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
1890 !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
1891 !intel_vgpu_active(rq->i915)) {
1892 ret = intel_logical_ring_emit_pdps(rq);
1896 rq->gem_context->ppgtt->pd_dirty_rings &= ~intel_engine_flag(rq->engine);
1899 cs = intel_ring_begin(rq, 6);
1904 * WaDisableCtxRestoreArbitration:bdw,chv
1906 * We don't need to perform MI_ARB_ENABLE as often as we do (in
1907 * particular all the gen that do not need the w/a at all!), if we
1908 * took care to make sure that on every switch into this context
1909 * (both ordinary and for preemption) that arbitrartion was enabled
1910 * we would be fine. However, there doesn't seem to be a downside to
1911 * being paranoid and making sure it is set before each batch and
1912 * every context-switch.
1914 * Note that if we fail to enable arbitration before the request
1915 * is complete, then we do not see the context-switch interrupt and
1916 * the engine hangs (with RING_HEAD == RING_TAIL).
1918 * That satisfies both the GPGPU w/a and our heavy-handed paranoia.
1920 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1922 /* FIXME(BDW): Address space and security selectors. */
1923 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
1924 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
1925 *cs++ = lower_32_bits(offset);
1926 *cs++ = upper_32_bits(offset);
1928 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1930 intel_ring_advance(rq, cs);
1935 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
1937 struct drm_i915_private *dev_priv = engine->i915;
1938 I915_WRITE_IMR(engine,
1939 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1940 POSTING_READ_FW(RING_IMR(engine->mmio_base));
1943 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
1945 struct drm_i915_private *dev_priv = engine->i915;
1946 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1949 static int gen8_emit_flush(struct i915_request *request, u32 mode)
1953 cs = intel_ring_begin(request, 4);
1957 cmd = MI_FLUSH_DW + 1;
1959 /* We always require a command barrier so that subsequent
1960 * commands, such as breadcrumb interrupts, are strictly ordered
1961 * wrt the contents of the write cache being flushed to memory
1962 * (and thus being coherent from the CPU).
1964 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1966 if (mode & EMIT_INVALIDATE) {
1967 cmd |= MI_INVALIDATE_TLB;
1968 if (request->engine->class == VIDEO_DECODE_CLASS)
1969 cmd |= MI_INVALIDATE_BSD;
1973 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1974 *cs++ = 0; /* upper addr */
1975 *cs++ = 0; /* value */
1976 intel_ring_advance(request, cs);
1981 static int gen8_emit_flush_render(struct i915_request *request,
1984 struct intel_engine_cs *engine = request->engine;
1986 i915_scratch_offset(engine->i915) + 2 * CACHELINE_BYTES;
1987 bool vf_flush_wa = false, dc_flush_wa = false;
1991 flags |= PIPE_CONTROL_CS_STALL;
1993 if (mode & EMIT_FLUSH) {
1994 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1995 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1996 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1997 flags |= PIPE_CONTROL_FLUSH_ENABLE;
2000 if (mode & EMIT_INVALIDATE) {
2001 flags |= PIPE_CONTROL_TLB_INVALIDATE;
2002 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
2003 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
2004 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
2005 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
2006 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
2007 flags |= PIPE_CONTROL_QW_WRITE;
2008 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
2011 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
2014 if (IS_GEN9(request->i915))
2017 /* WaForGAMHang:kbl */
2018 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
2030 cs = intel_ring_begin(request, len);
2035 cs = gen8_emit_pipe_control(cs, 0, 0);
2038 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
2041 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
2044 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
2046 intel_ring_advance(request, cs);
2052 * Reserve space for 2 NOOPs at the end of each request to be
2053 * used as a workaround for not being allowed to do lite
2054 * restore with HEAD==TAIL (WaIdleLiteRestore).
2056 static void gen8_emit_wa_tail(struct i915_request *request, u32 *cs)
2058 /* Ensure there's always at least one preemption point per-request. */
2059 *cs++ = MI_ARB_CHECK;
2061 request->wa_tail = intel_ring_offset(request, cs);
2064 static void gen8_emit_breadcrumb(struct i915_request *request, u32 *cs)
2066 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
2067 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
2069 cs = gen8_emit_ggtt_write(cs, request->global_seqno,
2070 intel_hws_seqno_address(request->engine));
2071 *cs++ = MI_USER_INTERRUPT;
2072 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2073 request->tail = intel_ring_offset(request, cs);
2074 assert_ring_tail_valid(request->ring, request->tail);
2076 gen8_emit_wa_tail(request, cs);
2078 static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
2080 static void gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs)
2082 /* We're using qword write, seqno should be aligned to 8 bytes. */
2083 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
2085 cs = gen8_emit_ggtt_write_rcs(cs, request->global_seqno,
2086 intel_hws_seqno_address(request->engine));
2087 *cs++ = MI_USER_INTERRUPT;
2088 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2089 request->tail = intel_ring_offset(request, cs);
2090 assert_ring_tail_valid(request->ring, request->tail);
2092 gen8_emit_wa_tail(request, cs);
2094 static const int gen8_emit_breadcrumb_rcs_sz = 8 + WA_TAIL_DWORDS;
2096 static int gen8_init_rcs_context(struct i915_request *rq)
2100 ret = intel_engine_emit_ctx_wa(rq);
2104 ret = intel_rcs_context_init_mocs(rq);
2106 * Failing to program the MOCS is non-fatal.The system will not
2107 * run at peak performance. So generate an error and carry on.
2110 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
2112 return i915_gem_render_state_emit(rq);
2116 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
2117 * @engine: Engine Command Streamer.
2119 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
2121 struct drm_i915_private *dev_priv;
2124 * Tasklet cannot be active at this point due intel_mark_active/idle
2125 * so this is just for documentation.
2127 if (WARN_ON(test_bit(TASKLET_STATE_SCHED,
2128 &engine->execlists.tasklet.state)))
2129 tasklet_kill(&engine->execlists.tasklet);
2131 dev_priv = engine->i915;
2133 if (engine->buffer) {
2134 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
2137 if (engine->cleanup)
2138 engine->cleanup(engine);
2140 intel_engine_cleanup_common(engine);
2142 lrc_destroy_wa_ctx(engine);
2144 engine->i915 = NULL;
2145 dev_priv->engine[engine->id] = NULL;
2149 void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
2151 engine->submit_request = execlists_submit_request;
2152 engine->cancel_requests = execlists_cancel_requests;
2153 engine->schedule = i915_schedule;
2154 engine->execlists.tasklet.func = execlists_submission_tasklet;
2156 engine->reset.prepare = execlists_reset_prepare;
2158 engine->park = NULL;
2159 engine->unpark = NULL;
2161 engine->flags |= I915_ENGINE_SUPPORTS_STATS;
2162 if (engine->i915->preempt_context)
2163 engine->flags |= I915_ENGINE_HAS_PREEMPTION;
2165 engine->i915->caps.scheduler =
2166 I915_SCHEDULER_CAP_ENABLED |
2167 I915_SCHEDULER_CAP_PRIORITY;
2168 if (intel_engine_has_preemption(engine))
2169 engine->i915->caps.scheduler |= I915_SCHEDULER_CAP_PREEMPTION;
2173 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
2175 /* Default vfuncs which can be overriden by each engine. */
2176 engine->init_hw = gen8_init_common_ring;
2178 engine->reset.prepare = execlists_reset_prepare;
2179 engine->reset.reset = execlists_reset;
2180 engine->reset.finish = execlists_reset_finish;
2182 engine->context_pin = execlists_context_pin;
2183 engine->request_alloc = execlists_request_alloc;
2185 engine->emit_flush = gen8_emit_flush;
2186 engine->emit_breadcrumb = gen8_emit_breadcrumb;
2187 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
2189 engine->set_default_submission = intel_execlists_set_default_submission;
2191 if (INTEL_GEN(engine->i915) < 11) {
2192 engine->irq_enable = gen8_logical_ring_enable_irq;
2193 engine->irq_disable = gen8_logical_ring_disable_irq;
2196 * TODO: On Gen11 interrupt masks need to be clear
2197 * to allow C6 entry. Keep interrupts enabled at
2198 * and take the hit of generating extra interrupts
2199 * until a more refined solution exists.
2202 engine->emit_bb_start = gen8_emit_bb_start;
2206 logical_ring_default_irqs(struct intel_engine_cs *engine)
2208 unsigned int shift = 0;
2210 if (INTEL_GEN(engine->i915) < 11) {
2211 const u8 irq_shifts[] = {
2212 [RCS] = GEN8_RCS_IRQ_SHIFT,
2213 [BCS] = GEN8_BCS_IRQ_SHIFT,
2214 [VCS] = GEN8_VCS1_IRQ_SHIFT,
2215 [VCS2] = GEN8_VCS2_IRQ_SHIFT,
2216 [VECS] = GEN8_VECS_IRQ_SHIFT,
2219 shift = irq_shifts[engine->id];
2222 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
2223 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
2227 logical_ring_setup(struct intel_engine_cs *engine)
2229 intel_engine_setup_common(engine);
2231 /* Intentionally left blank. */
2232 engine->buffer = NULL;
2234 tasklet_init(&engine->execlists.tasklet,
2235 execlists_submission_tasklet, (unsigned long)engine);
2237 logical_ring_default_vfuncs(engine);
2238 logical_ring_default_irqs(engine);
2241 static int logical_ring_init(struct intel_engine_cs *engine)
2243 struct drm_i915_private *i915 = engine->i915;
2244 struct intel_engine_execlists * const execlists = &engine->execlists;
2247 ret = intel_engine_init_common(engine);
2251 intel_engine_init_workarounds(engine);
2253 if (HAS_LOGICAL_RING_ELSQ(i915)) {
2254 execlists->submit_reg = i915->regs +
2255 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine));
2256 execlists->ctrl_reg = i915->regs +
2257 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine));
2259 execlists->submit_reg = i915->regs +
2260 i915_mmio_reg_offset(RING_ELSP(engine));
2263 execlists->preempt_complete_status = ~0u;
2264 if (i915->preempt_context) {
2265 struct intel_context *ce =
2266 to_intel_context(i915->preempt_context, engine);
2268 execlists->preempt_complete_status =
2269 upper_32_bits(ce->lrc_desc);
2272 execlists->csb_status =
2273 &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
2275 execlists->csb_write =
2276 &engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
2278 reset_csb_pointers(execlists);
2283 int logical_render_ring_init(struct intel_engine_cs *engine)
2285 struct drm_i915_private *dev_priv = engine->i915;
2288 logical_ring_setup(engine);
2290 if (HAS_L3_DPF(dev_priv))
2291 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2293 /* Override some for render ring. */
2294 if (INTEL_GEN(dev_priv) >= 9)
2295 engine->init_hw = gen9_init_render_ring;
2297 engine->init_hw = gen8_init_render_ring;
2298 engine->init_context = gen8_init_rcs_context;
2299 engine->emit_flush = gen8_emit_flush_render;
2300 engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;
2301 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz;
2303 ret = logical_ring_init(engine);
2307 ret = intel_init_workaround_bb(engine);
2310 * We continue even if we fail to initialize WA batch
2311 * because we only expect rare glitches but nothing
2312 * critical to prevent us from using GPU
2314 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2318 intel_engine_init_whitelist(engine);
2323 int logical_xcs_ring_init(struct intel_engine_cs *engine)
2325 logical_ring_setup(engine);
2327 return logical_ring_init(engine);
2331 make_rpcs(struct drm_i915_private *dev_priv)
2333 bool subslice_pg = INTEL_INFO(dev_priv)->sseu.has_subslice_pg;
2334 u8 slices = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
2335 u8 subslices = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]);
2339 * No explicit RPCS request is needed to ensure full
2340 * slice/subslice/EU enablement prior to Gen9.
2342 if (INTEL_GEN(dev_priv) < 9)
2346 * Since the SScount bitfield in GEN8_R_PWR_CLK_STATE is only three bits
2347 * wide and Icelake has up to eight subslices, specfial programming is
2348 * needed in order to correctly enable all subslices.
2350 * According to documentation software must consider the configuration
2351 * as 2x4x8 and hardware will translate this to 1x8x8.
2353 * Furthemore, even though SScount is three bits, maximum documented
2354 * value for it is four. From this some rules/restrictions follow:
2357 * If enabled subslice count is greater than four, two whole slices must
2358 * be enabled instead.
2361 * When more than one slice is enabled, hardware ignores the subslice
2364 * From these restrictions it follows that it is not possible to enable
2365 * a count of subslices between the SScount maximum of four restriction,
2366 * and the maximum available number on a particular SKU. Either all
2367 * subslices are enabled, or a count between one and four on the first
2370 if (IS_GEN11(dev_priv) && slices == 1 && subslices >= 4) {
2371 GEM_BUG_ON(subslices & 1);
2373 subslice_pg = false;
2378 * Starting in Gen9, render power gating can leave
2379 * slice/subslice/EU in a partially enabled state. We
2380 * must make an explicit request through RPCS for full
2383 if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
2384 u32 mask, val = slices;
2386 if (INTEL_GEN(dev_priv) >= 11) {
2387 mask = GEN11_RPCS_S_CNT_MASK;
2388 val <<= GEN11_RPCS_S_CNT_SHIFT;
2390 mask = GEN8_RPCS_S_CNT_MASK;
2391 val <<= GEN8_RPCS_S_CNT_SHIFT;
2394 GEM_BUG_ON(val & ~mask);
2397 rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_S_CNT_ENABLE | val;
2401 u32 val = subslices;
2403 val <<= GEN8_RPCS_SS_CNT_SHIFT;
2405 GEM_BUG_ON(val & ~GEN8_RPCS_SS_CNT_MASK);
2406 val &= GEN8_RPCS_SS_CNT_MASK;
2408 rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val;
2411 if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
2414 val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2415 GEN8_RPCS_EU_MIN_SHIFT;
2416 GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK);
2417 val &= GEN8_RPCS_EU_MIN_MASK;
2421 val = INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2422 GEN8_RPCS_EU_MAX_SHIFT;
2423 GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK);
2424 val &= GEN8_RPCS_EU_MAX_MASK;
2428 rpcs |= GEN8_RPCS_ENABLE;
2434 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2436 u32 indirect_ctx_offset;
2438 switch (INTEL_GEN(engine->i915)) {
2440 MISSING_CASE(INTEL_GEN(engine->i915));
2443 indirect_ctx_offset =
2444 GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2447 indirect_ctx_offset =
2448 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2451 indirect_ctx_offset =
2452 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2455 indirect_ctx_offset =
2456 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2460 return indirect_ctx_offset;
2463 static void execlists_init_reg_state(u32 *regs,
2464 struct i915_gem_context *ctx,
2465 struct intel_engine_cs *engine,
2466 struct intel_ring *ring)
2468 struct drm_i915_private *dev_priv = engine->i915;
2469 u32 base = engine->mmio_base;
2470 bool rcs = engine->class == RENDER_CLASS;
2472 /* A context is actually a big batch buffer with several
2473 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
2474 * values we are setting here are only for the first context restore:
2475 * on a subsequent save, the GPU will recreate this batchbuffer with new
2476 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
2477 * we are not initializing here).
2479 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
2480 MI_LRI_FORCE_POSTED;
2482 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
2483 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
2484 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));
2485 if (INTEL_GEN(dev_priv) < 11) {
2486 regs[CTX_CONTEXT_CONTROL + 1] |=
2487 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
2488 CTX_CTRL_RS_CTX_ENABLE);
2490 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
2491 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
2492 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
2493 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
2494 RING_CTL_SIZE(ring->size) | RING_VALID);
2495 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
2496 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
2497 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
2498 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
2499 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
2500 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
2502 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2504 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
2505 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
2506 RING_INDIRECT_CTX_OFFSET(base), 0);
2507 if (wa_ctx->indirect_ctx.size) {
2508 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2510 regs[CTX_RCS_INDIRECT_CTX + 1] =
2511 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
2512 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
2514 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
2515 intel_lr_indirect_ctx_offset(engine) << 6;
2518 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
2519 if (wa_ctx->per_ctx.size) {
2520 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2522 regs[CTX_BB_PER_CTX_PTR + 1] =
2523 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
2527 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2529 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
2530 /* PDP values well be assigned later if needed */
2531 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
2532 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
2533 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
2534 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
2535 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
2536 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
2537 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
2538 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
2540 if (i915_vm_is_48bit(&ctx->ppgtt->vm)) {
2541 /* 64b PPGTT (48bit canonical)
2542 * PDP0_DESCRIPTOR contains the base address to PML4 and
2543 * other PDP Descriptors are ignored.
2545 ASSIGN_CTX_PML4(ctx->ppgtt, regs);
2549 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2550 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2551 make_rpcs(dev_priv));
2553 i915_oa_init_reg_state(engine, ctx, regs);
2556 regs[CTX_END] = MI_BATCH_BUFFER_END;
2557 if (INTEL_GEN(dev_priv) >= 10)
2558 regs[CTX_END] |= BIT(0);
2562 populate_lr_context(struct i915_gem_context *ctx,
2563 struct drm_i915_gem_object *ctx_obj,
2564 struct intel_engine_cs *engine,
2565 struct intel_ring *ring)
2571 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2573 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2577 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
2578 if (IS_ERR(vaddr)) {
2579 ret = PTR_ERR(vaddr);
2580 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2583 ctx_obj->mm.dirty = true;
2585 if (engine->default_state) {
2587 * We only want to copy over the template context state;
2588 * skipping over the headers reserved for GuC communication,
2589 * leaving those as zero.
2591 const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE;
2594 defaults = i915_gem_object_pin_map(engine->default_state,
2596 if (IS_ERR(defaults)) {
2597 ret = PTR_ERR(defaults);
2601 memcpy(vaddr + start, defaults + start, engine->context_size);
2602 i915_gem_object_unpin_map(engine->default_state);
2605 /* The second page of the context object contains some fields which must
2606 * be set up prior to the first execution. */
2607 regs = vaddr + LRC_STATE_PN * PAGE_SIZE;
2608 execlists_init_reg_state(regs, ctx, engine, ring);
2609 if (!engine->default_state)
2610 regs[CTX_CONTEXT_CONTROL + 1] |=
2611 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
2612 if (ctx == ctx->i915->preempt_context && INTEL_GEN(engine->i915) < 11)
2613 regs[CTX_CONTEXT_CONTROL + 1] |=
2614 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2615 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);
2618 i915_gem_object_unpin_map(ctx_obj);
2622 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
2623 struct intel_engine_cs *engine,
2624 struct intel_context *ce)
2626 struct drm_i915_gem_object *ctx_obj;
2627 struct i915_vma *vma;
2628 uint32_t context_size;
2629 struct intel_ring *ring;
2630 struct i915_timeline *timeline;
2636 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
2639 * Before the actual start of the context image, we insert a few pages
2640 * for our own use and for sharing with the GuC.
2642 context_size += LRC_HEADER_PAGES * PAGE_SIZE;
2644 ctx_obj = i915_gem_object_create(ctx->i915, context_size);
2645 if (IS_ERR(ctx_obj))
2646 return PTR_ERR(ctx_obj);
2648 vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.vm, NULL);
2651 goto error_deref_obj;
2654 timeline = i915_timeline_create(ctx->i915, ctx->name);
2655 if (IS_ERR(timeline)) {
2656 ret = PTR_ERR(timeline);
2657 goto error_deref_obj;
2660 ring = intel_engine_create_ring(engine, timeline, ctx->ring_size);
2661 i915_timeline_put(timeline);
2663 ret = PTR_ERR(ring);
2664 goto error_deref_obj;
2667 ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2669 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2670 goto error_ring_free;
2679 intel_ring_free(ring);
2681 i915_gem_object_put(ctx_obj);
2685 void intel_lr_context_resume(struct drm_i915_private *i915)
2687 struct intel_engine_cs *engine;
2688 struct i915_gem_context *ctx;
2689 enum intel_engine_id id;
2692 * Because we emit WA_TAIL_DWORDS there may be a disparity
2693 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2694 * that stored in context. As we only write new commands from
2695 * ce->ring->tail onwards, everything before that is junk. If the GPU
2696 * starts reading from its RING_HEAD from the context, it may try to
2697 * execute that junk and die.
2699 * So to avoid that we reset the context images upon resume. For
2700 * simplicity, we just zero everything out.
2702 list_for_each_entry(ctx, &i915->contexts.list, link) {
2703 for_each_engine(engine, i915, id) {
2704 struct intel_context *ce =
2705 to_intel_context(ctx, engine);
2710 intel_ring_reset(ce->ring, 0);
2712 if (ce->pin_count) { /* otherwise done in context_pin */
2713 u32 *regs = ce->lrc_reg_state;
2715 regs[CTX_RING_HEAD + 1] = ce->ring->head;
2716 regs[CTX_RING_TAIL + 1] = ce->ring->tail;
2722 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2723 #include "selftests/intel_lrc.c"