2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
135 #include <drm/drmP.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
139 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
143 #define RING_EXECLIST_QFULL (1 << 0x2)
144 #define RING_EXECLIST1_VALID (1 << 0x3)
145 #define RING_EXECLIST0_VALID (1 << 0x4)
146 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
147 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
148 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
150 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
151 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
153 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
154 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
155 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
157 #define CTX_LRI_HEADER_0 0x01
158 #define CTX_CONTEXT_CONTROL 0x02
159 #define CTX_RING_HEAD 0x04
160 #define CTX_RING_TAIL 0x06
161 #define CTX_RING_BUFFER_START 0x08
162 #define CTX_RING_BUFFER_CONTROL 0x0a
163 #define CTX_BB_HEAD_U 0x0c
164 #define CTX_BB_HEAD_L 0x0e
165 #define CTX_BB_STATE 0x10
166 #define CTX_SECOND_BB_HEAD_U 0x12
167 #define CTX_SECOND_BB_HEAD_L 0x14
168 #define CTX_SECOND_BB_STATE 0x16
169 #define CTX_BB_PER_CTX_PTR 0x18
170 #define CTX_RCS_INDIRECT_CTX 0x1a
171 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
172 #define CTX_LRI_HEADER_1 0x21
173 #define CTX_CTX_TIMESTAMP 0x22
174 #define CTX_PDP3_UDW 0x24
175 #define CTX_PDP3_LDW 0x26
176 #define CTX_PDP2_UDW 0x28
177 #define CTX_PDP2_LDW 0x2a
178 #define CTX_PDP1_UDW 0x2c
179 #define CTX_PDP1_LDW 0x2e
180 #define CTX_PDP0_UDW 0x30
181 #define CTX_PDP0_LDW 0x32
182 #define CTX_LRI_HEADER_2 0x41
183 #define CTX_R_PWR_CLK_STATE 0x42
184 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
186 #define GEN8_CTX_VALID (1<<0)
187 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
188 #define GEN8_CTX_FORCE_RESTORE (1<<2)
189 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
190 #define GEN8_CTX_PRIVILEGE (1<<8)
192 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
193 const u64 _addr = test_bit(n, ppgtt->pdp.used_pdpes) ? \
194 ppgtt->pdp.page_directory[n]->daddr : \
195 ppgtt->scratch_pd->daddr; \
196 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
197 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
201 ADVANCED_CONTEXT = 0,
206 #define GEN8_CTX_MODE_SHIFT 3
209 FAULT_AND_HALT, /* Debug only */
211 FAULT_AND_CONTINUE /* Unsupported */
213 #define GEN8_CTX_ID_SHIFT 32
215 static int intel_lr_context_pin(struct intel_engine_cs *ring,
216 struct intel_context *ctx);
219 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
221 * @enable_execlists: value of i915.enable_execlists module parameter.
223 * Only certain platforms support Execlists (the prerequisites being
224 * support for Logical Ring Contexts and Aliasing PPGTT or better).
226 * Return: 1 if Execlists is supported and has to be enabled.
228 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
230 WARN_ON(i915.enable_ppgtt == -1);
232 if (INTEL_INFO(dev)->gen >= 9)
235 if (enable_execlists == 0)
238 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) &&
239 i915.use_mmio_flip >= 0)
246 * intel_execlists_ctx_id() - get the Execlists Context ID
247 * @ctx_obj: Logical Ring Context backing object.
249 * Do not confuse with ctx->id! Unfortunately we have a name overload
250 * here: the old context ID we pass to userspace as a handler so that
251 * they can refer to a context, and the new context ID we pass to the
252 * ELSP so that the GPU can inform us of the context status via
255 * Return: 20-bits globally unique context ID.
257 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
259 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj);
261 /* LRCA is required to be 4K aligned so the more significant 20 bits
262 * are globally unique */
266 static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
267 struct drm_i915_gem_object *ctx_obj)
269 struct drm_device *dev = ring->dev;
271 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
273 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
275 desc = GEN8_CTX_VALID;
276 desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT;
277 if (IS_GEN8(ctx_obj->base.dev))
278 desc |= GEN8_CTX_L3LLC_COHERENT;
279 desc |= GEN8_CTX_PRIVILEGE;
281 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT;
283 /* TODO: WaDisableLiteRestore when we start using semaphore
284 * signalling between Command Streamers */
285 /* desc |= GEN8_CTX_FORCE_RESTORE; */
287 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
289 INTEL_REVID(dev) <= SKL_REVID_B0 &&
290 (ring->id == BCS || ring->id == VCS ||
291 ring->id == VECS || ring->id == VCS2))
292 desc |= GEN8_CTX_FORCE_RESTORE;
297 static void execlists_elsp_write(struct intel_engine_cs *ring,
298 struct drm_i915_gem_object *ctx_obj0,
299 struct drm_i915_gem_object *ctx_obj1)
301 struct drm_device *dev = ring->dev;
302 struct drm_i915_private *dev_priv = dev->dev_private;
306 /* XXX: You must always write both descriptors in the order below. */
308 temp = execlists_ctx_descriptor(ring, ctx_obj1);
311 desc[1] = (u32)(temp >> 32);
314 temp = execlists_ctx_descriptor(ring, ctx_obj0);
315 desc[3] = (u32)(temp >> 32);
318 spin_lock(&dev_priv->uncore.lock);
319 intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
320 I915_WRITE_FW(RING_ELSP(ring), desc[1]);
321 I915_WRITE_FW(RING_ELSP(ring), desc[0]);
322 I915_WRITE_FW(RING_ELSP(ring), desc[3]);
324 /* The context is automatically loaded after the following */
325 I915_WRITE_FW(RING_ELSP(ring), desc[2]);
327 /* ELSP is a wo register, so use another nearby reg for posting instead */
328 POSTING_READ_FW(RING_EXECLIST_STATUS(ring));
329 intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
330 spin_unlock(&dev_priv->uncore.lock);
333 static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
334 struct drm_i915_gem_object *ring_obj,
335 struct i915_hw_ppgtt *ppgtt,
341 page = i915_gem_object_get_page(ctx_obj, 1);
342 reg_state = kmap_atomic(page);
344 reg_state[CTX_RING_TAIL+1] = tail;
345 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj);
347 /* True PPGTT with dynamic page allocation: update PDP registers and
348 * point the unallocated PDPs to the scratch page
351 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
352 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
353 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
354 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
357 kunmap_atomic(reg_state);
362 static void execlists_submit_contexts(struct intel_engine_cs *ring,
363 struct intel_context *to0, u32 tail0,
364 struct intel_context *to1, u32 tail1)
366 struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state;
367 struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf;
368 struct drm_i915_gem_object *ctx_obj1 = NULL;
369 struct intel_ringbuffer *ringbuf1 = NULL;
372 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0));
373 WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj));
375 execlists_update_context(ctx_obj0, ringbuf0->obj, to0->ppgtt, tail0);
378 ringbuf1 = to1->engine[ring->id].ringbuf;
379 ctx_obj1 = to1->engine[ring->id].state;
381 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1));
382 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj));
384 execlists_update_context(ctx_obj1, ringbuf1->obj, to1->ppgtt, tail1);
387 execlists_elsp_write(ring, ctx_obj0, ctx_obj1);
390 static void execlists_context_unqueue(struct intel_engine_cs *ring)
392 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
393 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
395 assert_spin_locked(&ring->execlist_lock);
398 * If irqs are not active generate a warning as batches that finish
399 * without the irqs may get lost and a GPU Hang may occur.
401 WARN_ON(!intel_irqs_enabled(ring->dev->dev_private));
403 if (list_empty(&ring->execlist_queue))
406 /* Try to read in pairs */
407 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
411 } else if (req0->ctx == cursor->ctx) {
412 /* Same ctx: ignore first request, as second request
413 * will update tail past first request's workload */
414 cursor->elsp_submitted = req0->elsp_submitted;
415 list_del(&req0->execlist_link);
416 list_add_tail(&req0->execlist_link,
417 &ring->execlist_retired_req_list);
425 if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
427 * WaIdleLiteRestore: make sure we never cause a lite
428 * restore with HEAD==TAIL
430 if (req0->elsp_submitted) {
432 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
433 * as we resubmit the request. See gen8_emit_request()
434 * for where we prepare the padding after the end of the
437 struct intel_ringbuffer *ringbuf;
439 ringbuf = req0->ctx->engine[ring->id].ringbuf;
441 req0->tail &= ringbuf->size - 1;
445 WARN_ON(req1 && req1->elsp_submitted);
447 execlists_submit_contexts(ring, req0->ctx, req0->tail,
448 req1 ? req1->ctx : NULL,
449 req1 ? req1->tail : 0);
451 req0->elsp_submitted++;
453 req1->elsp_submitted++;
456 static bool execlists_check_remove_request(struct intel_engine_cs *ring,
459 struct drm_i915_gem_request *head_req;
461 assert_spin_locked(&ring->execlist_lock);
463 head_req = list_first_entry_or_null(&ring->execlist_queue,
464 struct drm_i915_gem_request,
467 if (head_req != NULL) {
468 struct drm_i915_gem_object *ctx_obj =
469 head_req->ctx->engine[ring->id].state;
470 if (intel_execlists_ctx_id(ctx_obj) == request_id) {
471 WARN(head_req->elsp_submitted == 0,
472 "Never submitted head request\n");
474 if (--head_req->elsp_submitted <= 0) {
475 list_del(&head_req->execlist_link);
476 list_add_tail(&head_req->execlist_link,
477 &ring->execlist_retired_req_list);
487 * intel_lrc_irq_handler() - handle Context Switch interrupts
488 * @ring: Engine Command Streamer to handle.
490 * Check the unread Context Status Buffers and manage the submission of new
491 * contexts to the ELSP accordingly.
493 void intel_lrc_irq_handler(struct intel_engine_cs *ring)
495 struct drm_i915_private *dev_priv = ring->dev->dev_private;
501 u32 submit_contexts = 0;
503 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
505 read_pointer = ring->next_context_status_buffer;
506 write_pointer = status_pointer & 0x07;
507 if (read_pointer > write_pointer)
510 spin_lock(&ring->execlist_lock);
512 while (read_pointer < write_pointer) {
514 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
515 (read_pointer % 6) * 8);
516 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
517 (read_pointer % 6) * 8 + 4);
519 if (status & GEN8_CTX_STATUS_PREEMPTED) {
520 if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
521 if (execlists_check_remove_request(ring, status_id))
522 WARN(1, "Lite Restored request removed from queue\n");
524 WARN(1, "Preemption without Lite Restore\n");
527 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) ||
528 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) {
529 if (execlists_check_remove_request(ring, status_id))
534 if (submit_contexts != 0)
535 execlists_context_unqueue(ring);
537 spin_unlock(&ring->execlist_lock);
539 WARN(submit_contexts > 2, "More than two context complete events?\n");
540 ring->next_context_status_buffer = write_pointer % 6;
542 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring),
543 ((u32)ring->next_context_status_buffer & 0x07) << 8);
546 static int execlists_context_queue(struct intel_engine_cs *ring,
547 struct intel_context *to,
549 struct drm_i915_gem_request *request)
551 struct drm_i915_gem_request *cursor;
552 int num_elements = 0;
554 if (to != ring->default_context)
555 intel_lr_context_pin(ring, to);
559 * If there isn't a request associated with this submission,
560 * create one as a temporary holder.
562 request = kzalloc(sizeof(*request), GFP_KERNEL);
565 request->ring = ring;
567 kref_init(&request->ref);
568 i915_gem_context_reference(request->ctx);
570 i915_gem_request_reference(request);
571 WARN_ON(to != request->ctx);
573 request->tail = tail;
575 spin_lock_irq(&ring->execlist_lock);
577 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
578 if (++num_elements > 2)
581 if (num_elements > 2) {
582 struct drm_i915_gem_request *tail_req;
584 tail_req = list_last_entry(&ring->execlist_queue,
585 struct drm_i915_gem_request,
588 if (to == tail_req->ctx) {
589 WARN(tail_req->elsp_submitted != 0,
590 "More than 2 already-submitted reqs queued\n");
591 list_del(&tail_req->execlist_link);
592 list_add_tail(&tail_req->execlist_link,
593 &ring->execlist_retired_req_list);
597 list_add_tail(&request->execlist_link, &ring->execlist_queue);
598 if (num_elements == 0)
599 execlists_context_unqueue(ring);
601 spin_unlock_irq(&ring->execlist_lock);
606 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf,
607 struct intel_context *ctx)
609 struct intel_engine_cs *ring = ringbuf->ring;
610 uint32_t flush_domains;
614 if (ring->gpu_caches_dirty)
615 flush_domains = I915_GEM_GPU_DOMAINS;
617 ret = ring->emit_flush(ringbuf, ctx,
618 I915_GEM_GPU_DOMAINS, flush_domains);
622 ring->gpu_caches_dirty = false;
626 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
627 struct intel_context *ctx,
628 struct list_head *vmas)
630 struct intel_engine_cs *ring = ringbuf->ring;
631 const unsigned other_rings = ~intel_ring_flag(ring);
632 struct i915_vma *vma;
633 uint32_t flush_domains = 0;
634 bool flush_chipset = false;
637 list_for_each_entry(vma, vmas, exec_list) {
638 struct drm_i915_gem_object *obj = vma->obj;
640 if (obj->active & other_rings) {
641 ret = i915_gem_object_sync(obj, ring);
646 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
647 flush_chipset |= i915_gem_clflush_object(obj, false);
649 flush_domains |= obj->base.write_domain;
652 if (flush_domains & I915_GEM_DOMAIN_GTT)
655 /* Unconditionally invalidate gpu caches and ensure that we do flush
656 * any residual writes from the previous batch.
658 return logical_ring_invalidate_all_caches(ringbuf, ctx);
661 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request,
662 struct intel_context *ctx)
666 if (ctx != request->ring->default_context) {
667 ret = intel_lr_context_pin(request->ring, ctx);
672 request->ringbuf = ctx->engine[request->ring->id].ringbuf;
674 i915_gem_context_reference(request->ctx);
679 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
680 struct intel_context *ctx,
683 struct intel_engine_cs *ring = ringbuf->ring;
684 struct drm_i915_gem_request *request;
688 if (intel_ring_space(ringbuf) >= bytes)
691 list_for_each_entry(request, &ring->request_list, list) {
693 * The request queue is per-engine, so can contain requests
694 * from multiple ringbuffers. Here, we must ignore any that
695 * aren't from the ringbuffer we're considering.
697 if (request->ringbuf != ringbuf)
700 /* Would completion of this request free enough space? */
701 space = __intel_ring_space(request->postfix, ringbuf->tail,
707 if (WARN_ON(&request->list == &ring->request_list))
710 ret = i915_wait_request(request);
714 ringbuf->space = space;
719 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
720 * @ringbuf: Logical Ringbuffer to advance.
722 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
723 * really happens during submission is that the context and current tail will be placed
724 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
725 * point, the tail *inside* the context is updated and the ELSP written to.
728 intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf,
729 struct intel_context *ctx,
730 struct drm_i915_gem_request *request)
732 struct intel_engine_cs *ring = ringbuf->ring;
734 intel_logical_ring_advance(ringbuf);
736 if (intel_ring_stopped(ring))
739 execlists_context_queue(ring, ctx, ringbuf->tail, request);
742 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf,
743 struct intel_context *ctx)
745 uint32_t __iomem *virt;
746 int rem = ringbuf->size - ringbuf->tail;
748 if (ringbuf->space < rem) {
749 int ret = logical_ring_wait_for_space(ringbuf, ctx, rem);
755 virt = ringbuf->virtual_start + ringbuf->tail;
758 iowrite32(MI_NOOP, virt++);
761 intel_ring_update_space(ringbuf);
766 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf,
767 struct intel_context *ctx, int bytes)
771 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
772 ret = logical_ring_wrap_buffer(ringbuf, ctx);
777 if (unlikely(ringbuf->space < bytes)) {
778 ret = logical_ring_wait_for_space(ringbuf, ctx, bytes);
787 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
789 * @ringbuf: Logical ringbuffer.
790 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
792 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
793 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
794 * and also preallocates a request (every workload submission is still mediated through
795 * requests, same as it did with legacy ringbuffer submission).
797 * Return: non-zero if the ringbuffer is not ready to be written to.
799 static int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
800 struct intel_context *ctx, int num_dwords)
802 struct intel_engine_cs *ring = ringbuf->ring;
803 struct drm_device *dev = ring->dev;
804 struct drm_i915_private *dev_priv = dev->dev_private;
807 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
808 dev_priv->mm.interruptible);
812 ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t));
816 /* Preallocate the olr before touching the ring */
817 ret = i915_gem_request_alloc(ring, ctx);
821 ringbuf->space -= num_dwords * sizeof(uint32_t);
826 * execlists_submission() - submit a batchbuffer for execution, Execlists style
829 * @ring: Engine Command Streamer to submit to.
830 * @ctx: Context to employ for this submission.
831 * @args: execbuffer call arguments.
832 * @vmas: list of vmas.
833 * @batch_obj: the batchbuffer to submit.
834 * @exec_start: batchbuffer start virtual address pointer.
835 * @dispatch_flags: translated execbuffer call flags.
837 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
838 * away the submission details of the execbuffer ioctl call.
840 * Return: non-zero if the submission fails.
842 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
843 struct intel_engine_cs *ring,
844 struct intel_context *ctx,
845 struct drm_i915_gem_execbuffer2 *args,
846 struct list_head *vmas,
847 struct drm_i915_gem_object *batch_obj,
848 u64 exec_start, u32 dispatch_flags)
850 struct drm_i915_private *dev_priv = dev->dev_private;
851 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
856 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
857 instp_mask = I915_EXEC_CONSTANTS_MASK;
858 switch (instp_mode) {
859 case I915_EXEC_CONSTANTS_REL_GENERAL:
860 case I915_EXEC_CONSTANTS_ABSOLUTE:
861 case I915_EXEC_CONSTANTS_REL_SURFACE:
862 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
863 DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
867 if (instp_mode != dev_priv->relative_constants_mode) {
868 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
869 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
873 /* The HW changed the meaning on this bit on gen6 */
874 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
878 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
882 if (args->num_cliprects != 0) {
883 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
886 if (args->DR4 == 0xffffffff) {
887 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
891 if (args->DR1 || args->DR4 || args->cliprects_ptr) {
892 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n");
897 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
898 DRM_DEBUG("sol reset is gen7 only\n");
902 ret = execlists_move_to_gpu(ringbuf, ctx, vmas);
906 if (ring == &dev_priv->ring[RCS] &&
907 instp_mode != dev_priv->relative_constants_mode) {
908 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
912 intel_logical_ring_emit(ringbuf, MI_NOOP);
913 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
914 intel_logical_ring_emit(ringbuf, INSTPM);
915 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
916 intel_logical_ring_advance(ringbuf);
918 dev_priv->relative_constants_mode = instp_mode;
921 ret = ring->emit_bb_start(ringbuf, ctx, exec_start, dispatch_flags);
925 trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), dispatch_flags);
927 i915_gem_execbuffer_move_to_active(vmas, ring);
928 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
933 void intel_execlists_retire_requests(struct intel_engine_cs *ring)
935 struct drm_i915_gem_request *req, *tmp;
936 struct list_head retired_list;
938 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
939 if (list_empty(&ring->execlist_retired_req_list))
942 INIT_LIST_HEAD(&retired_list);
943 spin_lock_irq(&ring->execlist_lock);
944 list_replace_init(&ring->execlist_retired_req_list, &retired_list);
945 spin_unlock_irq(&ring->execlist_lock);
947 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) {
948 struct intel_context *ctx = req->ctx;
949 struct drm_i915_gem_object *ctx_obj =
950 ctx->engine[ring->id].state;
952 if (ctx_obj && (ctx != ring->default_context))
953 intel_lr_context_unpin(ring, ctx);
954 list_del(&req->execlist_link);
955 i915_gem_request_unreference(req);
959 void intel_logical_ring_stop(struct intel_engine_cs *ring)
961 struct drm_i915_private *dev_priv = ring->dev->dev_private;
964 if (!intel_ring_initialized(ring))
967 ret = intel_ring_idle(ring);
968 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
969 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
972 /* TODO: Is this correct with Execlists enabled? */
973 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
974 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
975 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
978 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
981 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf,
982 struct intel_context *ctx)
984 struct intel_engine_cs *ring = ringbuf->ring;
987 if (!ring->gpu_caches_dirty)
990 ret = ring->emit_flush(ringbuf, ctx, 0, I915_GEM_GPU_DOMAINS);
994 ring->gpu_caches_dirty = false;
998 static int intel_lr_context_pin(struct intel_engine_cs *ring,
999 struct intel_context *ctx)
1001 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
1002 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1005 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1006 if (ctx->engine[ring->id].pin_count++ == 0) {
1007 ret = i915_gem_obj_ggtt_pin(ctx_obj,
1008 GEN8_LR_CONTEXT_ALIGN, 0);
1010 goto reset_pin_count;
1012 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
1020 i915_gem_object_ggtt_unpin(ctx_obj);
1022 ctx->engine[ring->id].pin_count = 0;
1027 void intel_lr_context_unpin(struct intel_engine_cs *ring,
1028 struct intel_context *ctx)
1030 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
1031 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1034 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1035 if (--ctx->engine[ring->id].pin_count == 0) {
1036 intel_unpin_ringbuffer_obj(ringbuf);
1037 i915_gem_object_ggtt_unpin(ctx_obj);
1042 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
1043 struct intel_context *ctx)
1046 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1047 struct drm_device *dev = ring->dev;
1048 struct drm_i915_private *dev_priv = dev->dev_private;
1049 struct i915_workarounds *w = &dev_priv->workarounds;
1051 if (WARN_ON_ONCE(w->count == 0))
1054 ring->gpu_caches_dirty = true;
1055 ret = logical_ring_flush_all_caches(ringbuf, ctx);
1059 ret = intel_logical_ring_begin(ringbuf, ctx, w->count * 2 + 2);
1063 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
1064 for (i = 0; i < w->count; i++) {
1065 intel_logical_ring_emit(ringbuf, w->reg[i].addr);
1066 intel_logical_ring_emit(ringbuf, w->reg[i].value);
1068 intel_logical_ring_emit(ringbuf, MI_NOOP);
1070 intel_logical_ring_advance(ringbuf);
1072 ring->gpu_caches_dirty = true;
1073 ret = logical_ring_flush_all_caches(ringbuf, ctx);
1080 static int gen8_init_common_ring(struct intel_engine_cs *ring)
1082 struct drm_device *dev = ring->dev;
1083 struct drm_i915_private *dev_priv = dev->dev_private;
1085 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1086 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff);
1088 if (ring->status_page.obj) {
1089 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1090 (u32)ring->status_page.gfx_addr);
1091 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1094 I915_WRITE(RING_MODE_GEN7(ring),
1095 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1096 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1097 POSTING_READ(RING_MODE_GEN7(ring));
1098 ring->next_context_status_buffer = 0;
1099 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
1101 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
1106 static int gen8_init_render_ring(struct intel_engine_cs *ring)
1108 struct drm_device *dev = ring->dev;
1109 struct drm_i915_private *dev_priv = dev->dev_private;
1112 ret = gen8_init_common_ring(ring);
1116 /* We need to disable the AsyncFlip performance optimisations in order
1117 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1118 * programmed to '1' on all products.
1120 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1122 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1124 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1126 return init_workarounds_ring(ring);
1129 static int gen9_init_render_ring(struct intel_engine_cs *ring)
1133 ret = gen8_init_common_ring(ring);
1137 return init_workarounds_ring(ring);
1140 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1141 struct intel_context *ctx,
1142 u64 offset, unsigned dispatch_flags)
1144 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1147 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1151 /* FIXME(BDW): Address space and security selectors. */
1152 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1153 intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
1154 intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
1155 intel_logical_ring_emit(ringbuf, MI_NOOP);
1156 intel_logical_ring_advance(ringbuf);
1161 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring)
1163 struct drm_device *dev = ring->dev;
1164 struct drm_i915_private *dev_priv = dev->dev_private;
1165 unsigned long flags;
1167 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1170 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1171 if (ring->irq_refcount++ == 0) {
1172 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask));
1173 POSTING_READ(RING_IMR(ring->mmio_base));
1175 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1180 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1182 struct drm_device *dev = ring->dev;
1183 struct drm_i915_private *dev_priv = dev->dev_private;
1184 unsigned long flags;
1186 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1187 if (--ring->irq_refcount == 0) {
1188 I915_WRITE_IMR(ring, ~ring->irq_keep_mask);
1189 POSTING_READ(RING_IMR(ring->mmio_base));
1191 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1194 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1195 struct intel_context *ctx,
1196 u32 invalidate_domains,
1199 struct intel_engine_cs *ring = ringbuf->ring;
1200 struct drm_device *dev = ring->dev;
1201 struct drm_i915_private *dev_priv = dev->dev_private;
1205 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1209 cmd = MI_FLUSH_DW + 1;
1211 /* We always require a command barrier so that subsequent
1212 * commands, such as breadcrumb interrupts, are strictly ordered
1213 * wrt the contents of the write cache being flushed to memory
1214 * (and thus being coherent from the CPU).
1216 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1218 if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
1219 cmd |= MI_INVALIDATE_TLB;
1220 if (ring == &dev_priv->ring[VCS])
1221 cmd |= MI_INVALIDATE_BSD;
1224 intel_logical_ring_emit(ringbuf, cmd);
1225 intel_logical_ring_emit(ringbuf,
1226 I915_GEM_HWS_SCRATCH_ADDR |
1227 MI_FLUSH_DW_USE_GTT);
1228 intel_logical_ring_emit(ringbuf, 0); /* upper addr */
1229 intel_logical_ring_emit(ringbuf, 0); /* value */
1230 intel_logical_ring_advance(ringbuf);
1235 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1236 struct intel_context *ctx,
1237 u32 invalidate_domains,
1240 struct intel_engine_cs *ring = ringbuf->ring;
1241 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1246 flags |= PIPE_CONTROL_CS_STALL;
1248 if (flush_domains) {
1249 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1250 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1253 if (invalidate_domains) {
1254 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1255 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1256 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1257 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1258 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1259 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1260 flags |= PIPE_CONTROL_QW_WRITE;
1261 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1265 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
1268 vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
1269 flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
1271 ret = intel_logical_ring_begin(ringbuf, ctx, vf_flush_wa ? 12 : 6);
1276 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1277 intel_logical_ring_emit(ringbuf, 0);
1278 intel_logical_ring_emit(ringbuf, 0);
1279 intel_logical_ring_emit(ringbuf, 0);
1280 intel_logical_ring_emit(ringbuf, 0);
1281 intel_logical_ring_emit(ringbuf, 0);
1284 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1285 intel_logical_ring_emit(ringbuf, flags);
1286 intel_logical_ring_emit(ringbuf, scratch_addr);
1287 intel_logical_ring_emit(ringbuf, 0);
1288 intel_logical_ring_emit(ringbuf, 0);
1289 intel_logical_ring_emit(ringbuf, 0);
1290 intel_logical_ring_advance(ringbuf);
1295 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1297 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1300 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1302 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1305 static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
1306 struct drm_i915_gem_request *request)
1308 struct intel_engine_cs *ring = ringbuf->ring;
1313 * Reserve space for 2 NOOPs at the end of each request to be
1314 * used as a workaround for not being allowed to do lite
1315 * restore with HEAD==TAIL (WaIdleLiteRestore).
1317 ret = intel_logical_ring_begin(ringbuf, request->ctx, 8);
1321 cmd = MI_STORE_DWORD_IMM_GEN4;
1322 cmd |= MI_GLOBAL_GTT;
1324 intel_logical_ring_emit(ringbuf, cmd);
1325 intel_logical_ring_emit(ringbuf,
1326 (ring->status_page.gfx_addr +
1327 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
1328 intel_logical_ring_emit(ringbuf, 0);
1329 intel_logical_ring_emit(ringbuf,
1330 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1331 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1332 intel_logical_ring_emit(ringbuf, MI_NOOP);
1333 intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request);
1336 * Here we add two extra NOOPs as padding to avoid
1337 * lite restore of a context with HEAD==TAIL.
1339 intel_logical_ring_emit(ringbuf, MI_NOOP);
1340 intel_logical_ring_emit(ringbuf, MI_NOOP);
1341 intel_logical_ring_advance(ringbuf);
1346 static int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1347 struct intel_context *ctx)
1349 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1350 struct render_state so;
1351 struct drm_i915_file_private *file_priv = ctx->file_priv;
1352 struct drm_file *file = file_priv ? file_priv->file : NULL;
1355 ret = i915_gem_render_state_prepare(ring, &so);
1359 if (so.rodata == NULL)
1362 ret = ring->emit_bb_start(ringbuf,
1365 I915_DISPATCH_SECURE);
1369 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
1371 ret = __i915_add_request(ring, file, so.obj);
1372 /* intel_logical_ring_add_request moves object to inactive if it
1375 i915_gem_render_state_fini(&so);
1379 static int gen8_init_rcs_context(struct intel_engine_cs *ring,
1380 struct intel_context *ctx)
1384 ret = intel_logical_ring_workarounds_emit(ring, ctx);
1388 return intel_lr_context_render_state_init(ring, ctx);
1392 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1394 * @ring: Engine Command Streamer.
1397 void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1399 struct drm_i915_private *dev_priv;
1401 if (!intel_ring_initialized(ring))
1404 dev_priv = ring->dev->dev_private;
1406 intel_logical_ring_stop(ring);
1407 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1408 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
1411 ring->cleanup(ring);
1413 i915_cmd_parser_fini_ring(ring);
1414 i915_gem_batch_pool_fini(&ring->batch_pool);
1416 if (ring->status_page.obj) {
1417 kunmap(sg_page(ring->status_page.obj->pages->sgl));
1418 ring->status_page.obj = NULL;
1422 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1426 /* Intentionally left blank. */
1427 ring->buffer = NULL;
1430 INIT_LIST_HEAD(&ring->active_list);
1431 INIT_LIST_HEAD(&ring->request_list);
1432 i915_gem_batch_pool_init(dev, &ring->batch_pool);
1433 init_waitqueue_head(&ring->irq_queue);
1435 INIT_LIST_HEAD(&ring->execlist_queue);
1436 INIT_LIST_HEAD(&ring->execlist_retired_req_list);
1437 spin_lock_init(&ring->execlist_lock);
1439 ret = i915_cmd_parser_init_ring(ring);
1443 ret = intel_lr_context_deferred_create(ring->default_context, ring);
1448 static int logical_render_ring_init(struct drm_device *dev)
1450 struct drm_i915_private *dev_priv = dev->dev_private;
1451 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
1454 ring->name = "render ring";
1456 ring->mmio_base = RENDER_RING_BASE;
1457 ring->irq_enable_mask =
1458 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1459 ring->irq_keep_mask =
1460 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT;
1461 if (HAS_L3_DPF(dev))
1462 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1464 if (INTEL_INFO(dev)->gen >= 9)
1465 ring->init_hw = gen9_init_render_ring;
1467 ring->init_hw = gen8_init_render_ring;
1468 ring->init_context = gen8_init_rcs_context;
1469 ring->cleanup = intel_fini_pipe_control;
1470 ring->get_seqno = gen8_get_seqno;
1471 ring->set_seqno = gen8_set_seqno;
1472 ring->emit_request = gen8_emit_request;
1473 ring->emit_flush = gen8_emit_flush_render;
1474 ring->irq_get = gen8_logical_ring_get_irq;
1475 ring->irq_put = gen8_logical_ring_put_irq;
1476 ring->emit_bb_start = gen8_emit_bb_start;
1479 ret = logical_ring_init(dev, ring);
1483 return intel_init_pipe_control(ring);
1486 static int logical_bsd_ring_init(struct drm_device *dev)
1488 struct drm_i915_private *dev_priv = dev->dev_private;
1489 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
1491 ring->name = "bsd ring";
1493 ring->mmio_base = GEN6_BSD_RING_BASE;
1494 ring->irq_enable_mask =
1495 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1496 ring->irq_keep_mask =
1497 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
1499 ring->init_hw = gen8_init_common_ring;
1500 ring->get_seqno = gen8_get_seqno;
1501 ring->set_seqno = gen8_set_seqno;
1502 ring->emit_request = gen8_emit_request;
1503 ring->emit_flush = gen8_emit_flush;
1504 ring->irq_get = gen8_logical_ring_get_irq;
1505 ring->irq_put = gen8_logical_ring_put_irq;
1506 ring->emit_bb_start = gen8_emit_bb_start;
1508 return logical_ring_init(dev, ring);
1511 static int logical_bsd2_ring_init(struct drm_device *dev)
1513 struct drm_i915_private *dev_priv = dev->dev_private;
1514 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
1516 ring->name = "bds2 ring";
1518 ring->mmio_base = GEN8_BSD2_RING_BASE;
1519 ring->irq_enable_mask =
1520 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1521 ring->irq_keep_mask =
1522 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
1524 ring->init_hw = gen8_init_common_ring;
1525 ring->get_seqno = gen8_get_seqno;
1526 ring->set_seqno = gen8_set_seqno;
1527 ring->emit_request = gen8_emit_request;
1528 ring->emit_flush = gen8_emit_flush;
1529 ring->irq_get = gen8_logical_ring_get_irq;
1530 ring->irq_put = gen8_logical_ring_put_irq;
1531 ring->emit_bb_start = gen8_emit_bb_start;
1533 return logical_ring_init(dev, ring);
1536 static int logical_blt_ring_init(struct drm_device *dev)
1538 struct drm_i915_private *dev_priv = dev->dev_private;
1539 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
1541 ring->name = "blitter ring";
1543 ring->mmio_base = BLT_RING_BASE;
1544 ring->irq_enable_mask =
1545 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1546 ring->irq_keep_mask =
1547 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
1549 ring->init_hw = gen8_init_common_ring;
1550 ring->get_seqno = gen8_get_seqno;
1551 ring->set_seqno = gen8_set_seqno;
1552 ring->emit_request = gen8_emit_request;
1553 ring->emit_flush = gen8_emit_flush;
1554 ring->irq_get = gen8_logical_ring_get_irq;
1555 ring->irq_put = gen8_logical_ring_put_irq;
1556 ring->emit_bb_start = gen8_emit_bb_start;
1558 return logical_ring_init(dev, ring);
1561 static int logical_vebox_ring_init(struct drm_device *dev)
1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
1566 ring->name = "video enhancement ring";
1568 ring->mmio_base = VEBOX_RING_BASE;
1569 ring->irq_enable_mask =
1570 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1571 ring->irq_keep_mask =
1572 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
1574 ring->init_hw = gen8_init_common_ring;
1575 ring->get_seqno = gen8_get_seqno;
1576 ring->set_seqno = gen8_set_seqno;
1577 ring->emit_request = gen8_emit_request;
1578 ring->emit_flush = gen8_emit_flush;
1579 ring->irq_get = gen8_logical_ring_get_irq;
1580 ring->irq_put = gen8_logical_ring_put_irq;
1581 ring->emit_bb_start = gen8_emit_bb_start;
1583 return logical_ring_init(dev, ring);
1587 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers
1590 * This function inits the engines for an Execlists submission style (the equivalent in the
1591 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for
1592 * those engines that are present in the hardware.
1594 * Return: non-zero if the initialization failed.
1596 int intel_logical_rings_init(struct drm_device *dev)
1598 struct drm_i915_private *dev_priv = dev->dev_private;
1601 ret = logical_render_ring_init(dev);
1606 ret = logical_bsd_ring_init(dev);
1608 goto cleanup_render_ring;
1612 ret = logical_blt_ring_init(dev);
1614 goto cleanup_bsd_ring;
1617 if (HAS_VEBOX(dev)) {
1618 ret = logical_vebox_ring_init(dev);
1620 goto cleanup_blt_ring;
1623 if (HAS_BSD2(dev)) {
1624 ret = logical_bsd2_ring_init(dev);
1626 goto cleanup_vebox_ring;
1629 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
1631 goto cleanup_bsd2_ring;
1636 intel_logical_ring_cleanup(&dev_priv->ring[VCS2]);
1638 intel_logical_ring_cleanup(&dev_priv->ring[VECS]);
1640 intel_logical_ring_cleanup(&dev_priv->ring[BCS]);
1642 intel_logical_ring_cleanup(&dev_priv->ring[VCS]);
1643 cleanup_render_ring:
1644 intel_logical_ring_cleanup(&dev_priv->ring[RCS]);
1650 make_rpcs(struct drm_device *dev)
1655 * No explicit RPCS request is needed to ensure full
1656 * slice/subslice/EU enablement prior to Gen9.
1658 if (INTEL_INFO(dev)->gen < 9)
1662 * Starting in Gen9, render power gating can leave
1663 * slice/subslice/EU in a partially enabled state. We
1664 * must make an explicit request through RPCS for full
1667 if (INTEL_INFO(dev)->has_slice_pg) {
1668 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1669 rpcs |= INTEL_INFO(dev)->slice_total <<
1670 GEN8_RPCS_S_CNT_SHIFT;
1671 rpcs |= GEN8_RPCS_ENABLE;
1674 if (INTEL_INFO(dev)->has_subslice_pg) {
1675 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1676 rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
1677 GEN8_RPCS_SS_CNT_SHIFT;
1678 rpcs |= GEN8_RPCS_ENABLE;
1681 if (INTEL_INFO(dev)->has_eu_pg) {
1682 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
1683 GEN8_RPCS_EU_MIN_SHIFT;
1684 rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
1685 GEN8_RPCS_EU_MAX_SHIFT;
1686 rpcs |= GEN8_RPCS_ENABLE;
1693 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1694 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1696 struct drm_device *dev = ring->dev;
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1700 uint32_t *reg_state;
1704 ppgtt = dev_priv->mm.aliasing_ppgtt;
1706 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1708 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1712 ret = i915_gem_object_get_pages(ctx_obj);
1714 DRM_DEBUG_DRIVER("Could not get object pages\n");
1718 i915_gem_object_pin_pages(ctx_obj);
1720 /* The second page of the context object contains some fields which must
1721 * be set up prior to the first execution. */
1722 page = i915_gem_object_get_page(ctx_obj, 1);
1723 reg_state = kmap_atomic(page);
1725 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1726 * commands followed by (reg, value) pairs. The values we are setting here are
1727 * only for the first context restore: on a subsequent save, the GPU will
1728 * recreate this batchbuffer with new values (including all the missing
1729 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1730 if (ring->id == RCS)
1731 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14);
1733 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11);
1734 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
1735 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
1736 reg_state[CTX_CONTEXT_CONTROL+1] =
1737 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
1738 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
1739 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
1740 reg_state[CTX_RING_HEAD+1] = 0;
1741 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
1742 reg_state[CTX_RING_TAIL+1] = 0;
1743 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base);
1744 /* Ring buffer start address is not known until the buffer is pinned.
1745 * It is written to the context image in execlists_update_context()
1747 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base);
1748 reg_state[CTX_RING_BUFFER_CONTROL+1] =
1749 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID;
1750 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168;
1751 reg_state[CTX_BB_HEAD_U+1] = 0;
1752 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140;
1753 reg_state[CTX_BB_HEAD_L+1] = 0;
1754 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110;
1755 reg_state[CTX_BB_STATE+1] = (1<<5);
1756 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c;
1757 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0;
1758 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114;
1759 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0;
1760 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118;
1761 reg_state[CTX_SECOND_BB_STATE+1] = 0;
1762 if (ring->id == RCS) {
1763 /* TODO: according to BSpec, the register state context
1764 * for CHV does not have these. OTOH, these registers do
1765 * exist in CHV. I'm waiting for a clarification */
1766 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0;
1767 reg_state[CTX_BB_PER_CTX_PTR+1] = 0;
1768 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4;
1769 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0;
1770 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8;
1771 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0;
1773 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9);
1774 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED;
1775 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8;
1776 reg_state[CTX_CTX_TIMESTAMP+1] = 0;
1777 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3);
1778 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3);
1779 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2);
1780 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2);
1781 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1);
1782 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
1783 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
1784 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
1786 /* With dynamic page allocation, PDPs may not be allocated at this point,
1787 * Point the unallocated PDPs to the scratch page
1789 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
1790 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
1791 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
1792 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
1793 if (ring->id == RCS) {
1794 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1795 reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
1796 reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
1799 kunmap_atomic(reg_state);
1802 set_page_dirty(page);
1803 i915_gem_object_unpin_pages(ctx_obj);
1809 * intel_lr_context_free() - free the LRC specific bits of a context
1810 * @ctx: the LR context to free.
1812 * The real context freeing is done in i915_gem_context_free: this only
1813 * takes care of the bits that are LRC related: the per-engine backing
1814 * objects and the logical ringbuffer.
1816 void intel_lr_context_free(struct intel_context *ctx)
1820 for (i = 0; i < I915_NUM_RINGS; i++) {
1821 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1824 struct intel_ringbuffer *ringbuf =
1825 ctx->engine[i].ringbuf;
1826 struct intel_engine_cs *ring = ringbuf->ring;
1828 if (ctx == ring->default_context) {
1829 intel_unpin_ringbuffer_obj(ringbuf);
1830 i915_gem_object_ggtt_unpin(ctx_obj);
1832 WARN_ON(ctx->engine[ring->id].pin_count);
1833 intel_destroy_ringbuffer_obj(ringbuf);
1835 drm_gem_object_unreference(&ctx_obj->base);
1840 static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
1844 WARN_ON(INTEL_INFO(ring->dev)->gen < 8);
1848 if (INTEL_INFO(ring->dev)->gen >= 9)
1849 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
1851 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
1857 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
1864 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
1865 struct drm_i915_gem_object *default_ctx_obj)
1867 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1869 /* The status page is offset 0 from the default context object
1871 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj);
1872 ring->status_page.page_addr =
1873 kmap(sg_page(default_ctx_obj->pages->sgl));
1874 ring->status_page.obj = default_ctx_obj;
1876 I915_WRITE(RING_HWS_PGA(ring->mmio_base),
1877 (u32)ring->status_page.gfx_addr);
1878 POSTING_READ(RING_HWS_PGA(ring->mmio_base));
1882 * intel_lr_context_deferred_create() - create the LRC specific bits of a context
1883 * @ctx: LR context to create.
1884 * @ring: engine to be used with the context.
1886 * This function can be called more than once, with different engines, if we plan
1887 * to use the context with them. The context backing objects and the ringbuffers
1888 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
1889 * the creation is a deferred call: it's better to make sure first that we need to use
1890 * a given ring with the context.
1892 * Return: non-zero on error.
1894 int intel_lr_context_deferred_create(struct intel_context *ctx,
1895 struct intel_engine_cs *ring)
1897 const bool is_global_default_ctx = (ctx == ring->default_context);
1898 struct drm_device *dev = ring->dev;
1899 struct drm_i915_gem_object *ctx_obj;
1900 uint32_t context_size;
1901 struct intel_ringbuffer *ringbuf;
1904 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
1905 WARN_ON(ctx->engine[ring->id].state);
1907 context_size = round_up(get_lr_context_size(ring), 4096);
1909 ctx_obj = i915_gem_alloc_object(dev, context_size);
1911 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
1915 if (is_global_default_ctx) {
1916 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
1918 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n",
1920 drm_gem_object_unreference(&ctx_obj->base);
1925 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1927 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
1930 goto error_unpin_ctx;
1933 ringbuf->ring = ring;
1935 ringbuf->size = 32 * PAGE_SIZE;
1936 ringbuf->effective_size = ringbuf->size;
1939 ringbuf->last_retired_head = -1;
1940 intel_ring_update_space(ringbuf);
1942 if (ringbuf->obj == NULL) {
1943 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1946 "Failed to allocate ringbuffer obj %s: %d\n",
1948 goto error_free_rbuf;
1951 if (is_global_default_ctx) {
1952 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1955 "Failed to pin and map ringbuffer %s: %d\n",
1957 goto error_destroy_rbuf;
1963 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
1965 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
1969 ctx->engine[ring->id].ringbuf = ringbuf;
1970 ctx->engine[ring->id].state = ctx_obj;
1972 if (ctx == ring->default_context)
1973 lrc_setup_hardware_status_page(ring, ctx_obj);
1974 else if (ring->id == RCS && !ctx->rcs_initialized) {
1975 if (ring->init_context) {
1976 ret = ring->init_context(ring, ctx);
1978 DRM_ERROR("ring init context: %d\n", ret);
1979 ctx->engine[ring->id].ringbuf = NULL;
1980 ctx->engine[ring->id].state = NULL;
1985 ctx->rcs_initialized = true;
1991 if (is_global_default_ctx)
1992 intel_unpin_ringbuffer_obj(ringbuf);
1994 intel_destroy_ringbuffer_obj(ringbuf);
1998 if (is_global_default_ctx)
1999 i915_gem_object_ggtt_unpin(ctx_obj);
2000 drm_gem_object_unreference(&ctx_obj->base);
2004 void intel_lr_context_reset(struct drm_device *dev,
2005 struct intel_context *ctx)
2007 struct drm_i915_private *dev_priv = dev->dev_private;
2008 struct intel_engine_cs *ring;
2011 for_each_ring(ring, dev_priv, i) {
2012 struct drm_i915_gem_object *ctx_obj =
2013 ctx->engine[ring->id].state;
2014 struct intel_ringbuffer *ringbuf =
2015 ctx->engine[ring->id].ringbuf;
2016 uint32_t *reg_state;
2022 if (i915_gem_object_get_pages(ctx_obj)) {
2023 WARN(1, "Failed get_pages for context obj\n");
2026 page = i915_gem_object_get_page(ctx_obj, 1);
2027 reg_state = kmap_atomic(page);
2029 reg_state[CTX_RING_HEAD+1] = 0;
2030 reg_state[CTX_RING_TAIL+1] = 0;
2032 kunmap_atomic(reg_state);