2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "i915_gem_render_state.h"
140 #include "intel_lrc_reg.h"
141 #include "intel_mocs.h"
143 #define RING_EXECLIST_QFULL (1 << 0x2)
144 #define RING_EXECLIST1_VALID (1 << 0x3)
145 #define RING_EXECLIST0_VALID (1 << 0x4)
146 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
147 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
148 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
150 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
151 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
152 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
153 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
154 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
155 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
157 #define GEN8_CTX_STATUS_COMPLETED_MASK \
158 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
160 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
161 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
162 #define WA_TAIL_DWORDS 2
163 #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
165 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
166 struct intel_engine_cs *engine);
167 static void execlists_init_reg_state(u32 *reg_state,
168 struct i915_gem_context *ctx,
169 struct intel_engine_cs *engine,
170 struct intel_ring *ring);
173 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
174 * descriptor for a pinned context
175 * @ctx: Context to work on
176 * @engine: Engine the descriptor will be used with
178 * The context descriptor encodes various attributes of a context,
179 * including its GTT address and some flags. Because it's fairly
180 * expensive to calculate, we'll just do it once and cache the result,
181 * which remains valid until the context is unpinned.
183 * This is what a descriptor looks like, from LSB to MSB::
185 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
186 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
187 * bits 32-52: ctx ID, a globally unique tag
188 * bits 53-54: mbz, reserved for use by hardware
189 * bits 55-63: group ID, currently unused and set to 0
192 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
193 struct intel_engine_cs *engine)
195 struct intel_context *ce = &ctx->engine[engine->id];
198 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
200 desc = ctx->desc_template; /* bits 0-11 */
201 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
203 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
208 static struct i915_priolist *
209 lookup_priolist(struct intel_engine_cs *engine,
210 struct i915_priotree *pt,
213 struct intel_engine_execlists * const execlists = &engine->execlists;
214 struct i915_priolist *p;
215 struct rb_node **parent, *rb;
218 if (unlikely(execlists->no_priolist))
219 prio = I915_PRIORITY_NORMAL;
222 /* most positive priority is scheduled first, equal priorities fifo */
224 parent = &execlists->queue.rb_node;
227 p = rb_entry(rb, typeof(*p), node);
228 if (prio > p->priority) {
229 parent = &rb->rb_left;
230 } else if (prio < p->priority) {
231 parent = &rb->rb_right;
238 if (prio == I915_PRIORITY_NORMAL) {
239 p = &execlists->default_priolist;
241 p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
242 /* Convert an allocation failure to a priority bump */
244 prio = I915_PRIORITY_NORMAL; /* recurses just once */
246 /* To maintain ordering with all rendering, after an
247 * allocation failure we have to disable all scheduling.
248 * Requests will then be executed in fifo, and schedule
249 * will ensure that dependencies are emitted in fifo.
250 * There will be still some reordering with existing
251 * requests, so if userspace lied about their
252 * dependencies that reordering may be visible.
254 execlists->no_priolist = true;
260 INIT_LIST_HEAD(&p->requests);
261 rb_link_node(&p->node, rb, parent);
262 rb_insert_color(&p->node, &execlists->queue);
265 execlists->first = &p->node;
267 return ptr_pack_bits(p, first, 1);
270 static void unwind_wa_tail(struct drm_i915_gem_request *rq)
272 rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES);
273 assert_ring_tail_valid(rq->ring, rq->tail);
276 static void __unwind_incomplete_requests(struct intel_engine_cs *engine)
278 struct drm_i915_gem_request *rq, *rn;
279 struct i915_priolist *uninitialized_var(p);
280 int last_prio = I915_PRIORITY_INVALID;
282 lockdep_assert_held(&engine->timeline->lock);
284 list_for_each_entry_safe_reverse(rq, rn,
285 &engine->timeline->requests,
287 if (i915_gem_request_completed(rq))
290 __i915_gem_request_unsubmit(rq);
293 GEM_BUG_ON(rq->priotree.priority == I915_PRIORITY_INVALID);
294 if (rq->priotree.priority != last_prio) {
295 p = lookup_priolist(engine,
297 rq->priotree.priority);
298 p = ptr_mask_bits(p, 1);
300 last_prio = rq->priotree.priority;
303 list_add(&rq->priotree.link, &p->requests);
308 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
310 struct intel_engine_cs *engine =
311 container_of(execlists, typeof(*engine), execlists);
313 spin_lock_irq(&engine->timeline->lock);
314 __unwind_incomplete_requests(engine);
315 spin_unlock_irq(&engine->timeline->lock);
319 execlists_context_status_change(struct drm_i915_gem_request *rq,
320 unsigned long status)
323 * Only used when GVT-g is enabled now. When GVT-g is disabled,
324 * The compiler should eliminate this function as dead-code.
326 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
329 atomic_notifier_call_chain(&rq->engine->context_status_notifier,
334 execlists_context_schedule_in(struct drm_i915_gem_request *rq)
336 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
337 intel_engine_context_in(rq->engine);
341 execlists_context_schedule_out(struct drm_i915_gem_request *rq)
343 intel_engine_context_out(rq->engine);
344 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
348 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
350 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
351 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
352 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
353 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
356 static u64 execlists_update_context(struct drm_i915_gem_request *rq)
358 struct intel_context *ce = &rq->ctx->engine[rq->engine->id];
359 struct i915_hw_ppgtt *ppgtt =
360 rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
361 u32 *reg_state = ce->lrc_reg_state;
363 reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
365 /* True 32b PPGTT with dynamic page allocation: update PDP
366 * registers and point the unallocated PDPs to scratch page.
367 * PML4 is allocated during ppgtt init, so this is not needed
370 if (ppgtt && !i915_vm_is_48bit(&ppgtt->base))
371 execlists_update_context_pdps(ppgtt, reg_state);
376 static inline void elsp_write(u64 desc, u32 __iomem *elsp)
378 writel(upper_32_bits(desc), elsp);
379 writel(lower_32_bits(desc), elsp);
382 static void execlists_submit_ports(struct intel_engine_cs *engine)
384 struct execlist_port *port = engine->execlists.port;
387 for (n = execlists_num_ports(&engine->execlists); n--; ) {
388 struct drm_i915_gem_request *rq;
392 rq = port_unpack(&port[n], &count);
394 GEM_BUG_ON(count > !n);
396 execlists_context_schedule_in(rq);
397 port_set(&port[n], port_pack(rq, count));
398 desc = execlists_update_context(rq);
399 GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
401 GEM_TRACE("%s in[%d]: ctx=%d.%d, seqno=%x\n",
403 port[n].context_id, count,
410 elsp_write(desc, engine->execlists.elsp);
412 execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK);
415 static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
417 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
418 i915_gem_context_force_single_submission(ctx));
421 static bool can_merge_ctx(const struct i915_gem_context *prev,
422 const struct i915_gem_context *next)
427 if (ctx_single_port_submission(prev))
433 static void port_assign(struct execlist_port *port,
434 struct drm_i915_gem_request *rq)
436 GEM_BUG_ON(rq == port_request(port));
438 if (port_isset(port))
439 i915_gem_request_put(port_request(port));
441 port_set(port, port_pack(i915_gem_request_get(rq), port_count(port)));
444 static void inject_preempt_context(struct intel_engine_cs *engine)
446 struct intel_context *ce =
447 &engine->i915->preempt_context->engine[engine->id];
450 GEM_BUG_ON(engine->execlists.preempt_complete_status !=
451 upper_32_bits(ce->lrc_desc));
452 GEM_BUG_ON(!IS_ALIGNED(ce->ring->size, WA_TAIL_BYTES));
454 memset(ce->ring->vaddr + ce->ring->tail, 0, WA_TAIL_BYTES);
455 ce->ring->tail += WA_TAIL_BYTES;
456 ce->ring->tail &= (ce->ring->size - 1);
457 ce->lrc_reg_state[CTX_RING_TAIL+1] = ce->ring->tail;
459 GEM_BUG_ON((ce->lrc_reg_state[CTX_CONTEXT_CONTROL + 1] &
460 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
461 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT)) !=
462 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
463 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT));
465 GEM_TRACE("%s\n", engine->name);
466 for (n = execlists_num_ports(&engine->execlists); --n; )
467 elsp_write(0, engine->execlists.elsp);
469 elsp_write(ce->lrc_desc, engine->execlists.elsp);
470 execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK);
473 static void execlists_dequeue(struct intel_engine_cs *engine)
475 struct intel_engine_execlists * const execlists = &engine->execlists;
476 struct execlist_port *port = execlists->port;
477 const struct execlist_port * const last_port =
478 &execlists->port[execlists->port_mask];
479 struct drm_i915_gem_request *last = port_request(port);
483 /* Hardware submission is through 2 ports. Conceptually each port
484 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
485 * static for a context, and unique to each, so we only execute
486 * requests belonging to a single context from each ring. RING_HEAD
487 * is maintained by the CS in the context image, it marks the place
488 * where it got up to last time, and through RING_TAIL we tell the CS
489 * where we want to execute up to this time.
491 * In this list the requests are in order of execution. Consecutive
492 * requests from the same context are adjacent in the ringbuffer. We
493 * can combine these requests into a single RING_TAIL update:
495 * RING_HEAD...req1...req2
497 * since to execute req2 the CS must first execute req1.
499 * Our goal then is to point each port to the end of a consecutive
500 * sequence of requests as being the most optimal (fewest wake ups
501 * and context switches) submission.
504 spin_lock_irq(&engine->timeline->lock);
505 rb = execlists->first;
506 GEM_BUG_ON(rb_first(&execlists->queue) != rb);
512 * Don't resubmit or switch until all outstanding
513 * preemptions (lite-restore) are seen. Then we
514 * know the next preemption status we see corresponds
515 * to this ELSP update.
517 GEM_BUG_ON(!port_count(&port[0]));
518 if (port_count(&port[0]) > 1)
522 * If we write to ELSP a second time before the HW has had
523 * a chance to respond to the previous write, we can confuse
524 * the HW and hit "undefined behaviour". After writing to ELSP,
525 * we must then wait until we see a context-switch event from
526 * the HW to indicate that it has had a chance to respond.
528 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
531 if (engine->i915->preempt_context &&
532 rb_entry(rb, struct i915_priolist, node)->priority >
533 max(last->priotree.priority, 0)) {
535 * Switch to our empty preempt context so
536 * the state of the GPU is known (idle).
538 inject_preempt_context(engine);
539 execlists_set_active(execlists,
540 EXECLISTS_ACTIVE_PREEMPT);
544 * In theory, we could coalesce more requests onto
545 * the second port (the first port is active, with
546 * no preemptions pending). However, that means we
547 * then have to deal with the possible lite-restore
548 * of the second port (as we submit the ELSP, there
549 * may be a context-switch) but also we may complete
550 * the resubmission before the context-switch. Ergo,
551 * coalescing onto the second port will cause a
552 * preemption event, but we cannot predict whether
553 * that will affect port[0] or port[1].
555 * If the second port is already active, we can wait
556 * until the next context-switch before contemplating
557 * new requests. The GPU will be busy and we should be
558 * able to resubmit the new ELSP before it idles,
559 * avoiding pipeline bubbles (momentary pauses where
560 * the driver is unable to keep up the supply of new
563 if (port_count(&port[1]))
566 /* WaIdleLiteRestore:bdw,skl
567 * Apply the wa NOOPs to prevent
568 * ring:HEAD == req:TAIL as we resubmit the
569 * request. See gen8_emit_breadcrumb() for
570 * where we prepare the padding after the
571 * end of the request.
573 last->tail = last->wa_tail;
578 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
579 struct drm_i915_gem_request *rq, *rn;
581 list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
583 * Can we combine this request with the current port?
584 * It has to be the same context/ringbuffer and not
585 * have any exceptions (e.g. GVT saying never to
588 * If we can combine the requests, we can execute both
589 * by updating the RING_TAIL to point to the end of the
590 * second request, and so we never need to tell the
591 * hardware about the first.
593 if (last && !can_merge_ctx(rq->ctx, last->ctx)) {
595 * If we are on the second port and cannot
596 * combine this request with the last, then we
599 if (port == last_port) {
600 __list_del_many(&p->requests,
606 * If GVT overrides us we only ever submit
607 * port[0], leaving port[1] empty. Note that we
608 * also have to be careful that we don't queue
609 * the same context (even though a different
610 * request) to the second port.
612 if (ctx_single_port_submission(last->ctx) ||
613 ctx_single_port_submission(rq->ctx)) {
614 __list_del_many(&p->requests,
619 GEM_BUG_ON(last->ctx == rq->ctx);
622 port_assign(port, last);
625 GEM_BUG_ON(port_isset(port));
628 INIT_LIST_HEAD(&rq->priotree.link);
629 __i915_gem_request_submit(rq);
630 trace_i915_gem_request_in(rq, port_index(port, execlists));
636 rb_erase(&p->node, &execlists->queue);
637 INIT_LIST_HEAD(&p->requests);
638 if (p->priority != I915_PRIORITY_NORMAL)
639 kmem_cache_free(engine->i915->priorities, p);
642 execlists->first = rb;
644 port_assign(port, last);
646 /* We must always keep the beast fed if we have work piled up */
647 GEM_BUG_ON(port_isset(execlists->port) &&
648 !execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
649 GEM_BUG_ON(execlists->first && !port_isset(execlists->port));
652 spin_unlock_irq(&engine->timeline->lock);
655 execlists_set_active(execlists, EXECLISTS_ACTIVE_USER);
656 execlists_submit_ports(engine);
661 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
663 struct execlist_port *port = execlists->port;
664 unsigned int num_ports = execlists_num_ports(execlists);
666 while (num_ports-- && port_isset(port)) {
667 struct drm_i915_gem_request *rq = port_request(port);
669 GEM_BUG_ON(!execlists->active);
670 intel_engine_context_out(rq->engine);
671 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_PREEMPTED);
672 i915_gem_request_put(rq);
674 memset(port, 0, sizeof(*port));
679 static void execlists_cancel_requests(struct intel_engine_cs *engine)
681 struct intel_engine_execlists * const execlists = &engine->execlists;
682 struct drm_i915_gem_request *rq, *rn;
686 spin_lock_irqsave(&engine->timeline->lock, flags);
688 /* Cancel the requests on the HW and clear the ELSP tracker. */
689 execlists_cancel_port_requests(execlists);
691 /* Mark all executing requests as skipped. */
692 list_for_each_entry(rq, &engine->timeline->requests, link) {
693 GEM_BUG_ON(!rq->global_seqno);
694 if (!i915_gem_request_completed(rq))
695 dma_fence_set_error(&rq->fence, -EIO);
698 /* Flush the queued requests to the timeline list (for retiring). */
699 rb = execlists->first;
701 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
703 list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
704 INIT_LIST_HEAD(&rq->priotree.link);
706 dma_fence_set_error(&rq->fence, -EIO);
707 __i915_gem_request_submit(rq);
711 rb_erase(&p->node, &execlists->queue);
712 INIT_LIST_HEAD(&p->requests);
713 if (p->priority != I915_PRIORITY_NORMAL)
714 kmem_cache_free(engine->i915->priorities, p);
717 /* Remaining _unready_ requests will be nop'ed when submitted */
720 execlists->queue = RB_ROOT;
721 execlists->first = NULL;
722 GEM_BUG_ON(port_isset(execlists->port));
725 * The port is checked prior to scheduling a tasklet, but
726 * just in case we have suspended the tasklet to do the
727 * wedging make sure that when it wakes, it decides there
728 * is no work to do by clearing the irq_posted bit.
730 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
732 spin_unlock_irqrestore(&engine->timeline->lock, flags);
736 * Check the unread Context Status Buffers and manage the submission of new
737 * contexts to the ELSP accordingly.
739 static void execlists_submission_tasklet(unsigned long data)
741 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
742 struct intel_engine_execlists * const execlists = &engine->execlists;
743 struct execlist_port * const port = execlists->port;
744 struct drm_i915_private *dev_priv = engine->i915;
747 /* We can skip acquiring intel_runtime_pm_get() here as it was taken
748 * on our behalf by the request (see i915_gem_mark_busy()) and it will
749 * not be relinquished until the device is idle (see
750 * i915_gem_idle_work_handler()). As a precaution, we make sure
751 * that all ELSP are drained i.e. we have processed the CSB,
752 * before allowing ourselves to idle and calling intel_runtime_pm_put().
754 GEM_BUG_ON(!dev_priv->gt.awake);
756 /* Prefer doing test_and_clear_bit() as a two stage operation to avoid
757 * imposing the cost of a locked atomic transaction when submitting a
758 * new request (outside of the context-switch interrupt).
760 while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {
761 /* The HWSP contains a (cacheable) mirror of the CSB */
763 &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
764 unsigned int head, tail;
766 if (unlikely(execlists->csb_use_mmio)) {
767 buf = (u32 * __force)
768 (dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
769 execlists->csb_head = -1; /* force mmio read of CSB ptrs */
772 /* The write will be ordered by the uncached read (itself
773 * a memory barrier), so we do not need another in the form
774 * of a locked instruction. The race between the interrupt
775 * handler and the split test/clear is harmless as we order
776 * our clear before the CSB read. If the interrupt arrived
777 * first between the test and the clear, we read the updated
778 * CSB and clear the bit. If the interrupt arrives as we read
779 * the CSB or later (i.e. after we had cleared the bit) the bit
780 * is set and we do a new loop.
782 __clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
783 if (unlikely(execlists->csb_head == -1)) { /* following a reset */
785 intel_uncore_forcewake_get(dev_priv,
786 execlists->fw_domains);
790 head = readl(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
791 tail = GEN8_CSB_WRITE_PTR(head);
792 head = GEN8_CSB_READ_PTR(head);
793 execlists->csb_head = head;
795 const int write_idx =
796 intel_hws_csb_write_index(dev_priv) -
797 I915_HWS_CSB_BUF0_INDEX;
799 head = execlists->csb_head;
800 tail = READ_ONCE(buf[write_idx]);
802 GEM_TRACE("%s cs-irq head=%d [%d%s], tail=%d [%d%s]\n",
804 head, GEN8_CSB_READ_PTR(readl(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)))), fw ? "" : "?",
805 tail, GEN8_CSB_WRITE_PTR(readl(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)))), fw ? "" : "?");
807 while (head != tail) {
808 struct drm_i915_gem_request *rq;
812 if (++head == GEN8_CSB_ENTRIES)
815 /* We are flying near dragons again.
817 * We hold a reference to the request in execlist_port[]
818 * but no more than that. We are operating in softirq
819 * context and so cannot hold any mutex or sleep. That
820 * prevents us stopping the requests we are processing
821 * in port[] from being retired simultaneously (the
822 * breadcrumb will be complete before we see the
823 * context-switch). As we only hold the reference to the
824 * request, any pointer chasing underneath the request
825 * is subject to a potential use-after-free. Thus we
826 * store all of the bookkeeping within port[] as
827 * required, and avoid using unguarded pointers beneath
828 * request itself. The same applies to the atomic
832 status = READ_ONCE(buf[2 * head]); /* maybe mmio! */
833 GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n",
835 status, buf[2*head + 1],
838 if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE |
839 GEN8_CTX_STATUS_PREEMPTED))
840 execlists_set_active(execlists,
841 EXECLISTS_ACTIVE_HWACK);
842 if (status & GEN8_CTX_STATUS_ACTIVE_IDLE)
843 execlists_clear_active(execlists,
844 EXECLISTS_ACTIVE_HWACK);
846 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
849 /* We should never get a COMPLETED | IDLE_ACTIVE! */
850 GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE);
852 if (status & GEN8_CTX_STATUS_COMPLETE &&
853 buf[2*head + 1] == execlists->preempt_complete_status) {
854 GEM_TRACE("%s preempt-idle\n", engine->name);
856 execlists_cancel_port_requests(execlists);
857 execlists_unwind_incomplete_requests(execlists);
859 GEM_BUG_ON(!execlists_is_active(execlists,
860 EXECLISTS_ACTIVE_PREEMPT));
861 execlists_clear_active(execlists,
862 EXECLISTS_ACTIVE_PREEMPT);
866 if (status & GEN8_CTX_STATUS_PREEMPTED &&
867 execlists_is_active(execlists,
868 EXECLISTS_ACTIVE_PREEMPT))
871 GEM_BUG_ON(!execlists_is_active(execlists,
872 EXECLISTS_ACTIVE_USER));
874 /* Check the context/desc id for this event matches */
875 GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id);
877 rq = port_unpack(port, &count);
878 GEM_TRACE("%s out[0]: ctx=%d.%d, seqno=%x\n",
880 port->context_id, count,
881 rq ? rq->global_seqno : 0);
882 GEM_BUG_ON(count == 0);
884 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
885 GEM_BUG_ON(port_isset(&port[1]) &&
886 !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH));
887 GEM_BUG_ON(!i915_gem_request_completed(rq));
888 execlists_context_schedule_out(rq);
889 trace_i915_gem_request_out(rq);
890 i915_gem_request_put(rq);
892 execlists_port_complete(execlists, port);
894 port_set(port, port_pack(rq, count));
897 /* After the final element, the hw should be idle */
898 GEM_BUG_ON(port_count(port) == 0 &&
899 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
900 if (port_count(port) == 0)
901 execlists_clear_active(execlists,
902 EXECLISTS_ACTIVE_USER);
905 if (head != execlists->csb_head) {
906 execlists->csb_head = head;
907 writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
908 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
912 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT))
913 execlists_dequeue(engine);
916 intel_uncore_forcewake_put(dev_priv, execlists->fw_domains);
919 static void insert_request(struct intel_engine_cs *engine,
920 struct i915_priotree *pt,
923 struct i915_priolist *p = lookup_priolist(engine, pt, prio);
925 list_add_tail(&pt->link, &ptr_mask_bits(p, 1)->requests);
926 if (ptr_unmask_bits(p, 1))
927 tasklet_hi_schedule(&engine->execlists.tasklet);
930 static void execlists_submit_request(struct drm_i915_gem_request *request)
932 struct intel_engine_cs *engine = request->engine;
935 /* Will be called from irq-context when using foreign fences. */
936 spin_lock_irqsave(&engine->timeline->lock, flags);
938 insert_request(engine, &request->priotree, request->priotree.priority);
940 GEM_BUG_ON(!engine->execlists.first);
941 GEM_BUG_ON(list_empty(&request->priotree.link));
943 spin_unlock_irqrestore(&engine->timeline->lock, flags);
946 static struct drm_i915_gem_request *pt_to_request(struct i915_priotree *pt)
948 return container_of(pt, struct drm_i915_gem_request, priotree);
951 static struct intel_engine_cs *
952 pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked)
954 struct intel_engine_cs *engine = pt_to_request(pt)->engine;
958 if (engine != locked) {
959 spin_unlock(&locked->timeline->lock);
960 spin_lock(&engine->timeline->lock);
966 static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
968 struct intel_engine_cs *engine;
969 struct i915_dependency *dep, *p;
970 struct i915_dependency stack;
973 GEM_BUG_ON(prio == I915_PRIORITY_INVALID);
975 if (i915_gem_request_completed(request))
978 if (prio <= READ_ONCE(request->priotree.priority))
981 /* Need BKL in order to use the temporary link inside i915_dependency */
982 lockdep_assert_held(&request->i915->drm.struct_mutex);
984 stack.signaler = &request->priotree;
985 list_add(&stack.dfs_link, &dfs);
988 * Recursively bump all dependent priorities to match the new request.
990 * A naive approach would be to use recursion:
991 * static void update_priorities(struct i915_priotree *pt, prio) {
992 * list_for_each_entry(dep, &pt->signalers_list, signal_link)
993 * update_priorities(dep->signal, prio)
994 * insert_request(pt);
996 * but that may have unlimited recursion depth and so runs a very
997 * real risk of overunning the kernel stack. Instead, we build
998 * a flat list of all dependencies starting with the current request.
999 * As we walk the list of dependencies, we add all of its dependencies
1000 * to the end of the list (this may include an already visited
1001 * request) and continue to walk onwards onto the new dependencies. The
1002 * end result is a topological list of requests in reverse order, the
1003 * last element in the list is the request we must execute first.
1005 list_for_each_entry(dep, &dfs, dfs_link) {
1006 struct i915_priotree *pt = dep->signaler;
1009 * Within an engine, there can be no cycle, but we may
1010 * refer to the same dependency chain multiple times
1011 * (redundant dependencies are not eliminated) and across
1014 list_for_each_entry(p, &pt->signalers_list, signal_link) {
1015 GEM_BUG_ON(p == dep); /* no cycles! */
1017 if (i915_priotree_signaled(p->signaler))
1020 GEM_BUG_ON(p->signaler->priority < pt->priority);
1021 if (prio > READ_ONCE(p->signaler->priority))
1022 list_move_tail(&p->dfs_link, &dfs);
1027 * If we didn't need to bump any existing priorities, and we haven't
1028 * yet submitted this request (i.e. there is no potential race with
1029 * execlists_submit_request()), we can set our own priority and skip
1030 * acquiring the engine locks.
1032 if (request->priotree.priority == I915_PRIORITY_INVALID) {
1033 GEM_BUG_ON(!list_empty(&request->priotree.link));
1034 request->priotree.priority = prio;
1035 if (stack.dfs_link.next == stack.dfs_link.prev)
1037 __list_del_entry(&stack.dfs_link);
1040 engine = request->engine;
1041 spin_lock_irq(&engine->timeline->lock);
1043 /* Fifo and depth-first replacement ensure our deps execute before us */
1044 list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
1045 struct i915_priotree *pt = dep->signaler;
1047 INIT_LIST_HEAD(&dep->dfs_link);
1049 engine = pt_lock_engine(pt, engine);
1051 if (prio <= pt->priority)
1054 pt->priority = prio;
1055 if (!list_empty(&pt->link)) {
1056 __list_del_entry(&pt->link);
1057 insert_request(engine, pt, prio);
1061 spin_unlock_irq(&engine->timeline->lock);
1064 static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
1070 * Clear this page out of any CPU caches for coherent swap-in/out.
1071 * We only want to do this on the first bind so that we do not stall
1072 * on an active context (which by nature is already on the GPU).
1074 if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1075 err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1080 flags = PIN_GLOBAL | PIN_HIGH;
1081 if (ctx->ggtt_offset_bias)
1082 flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
1084 return i915_vma_pin(vma, 0, GEN8_LR_CONTEXT_ALIGN, flags);
1087 static struct intel_ring *
1088 execlists_context_pin(struct intel_engine_cs *engine,
1089 struct i915_gem_context *ctx)
1091 struct intel_context *ce = &ctx->engine[engine->id];
1095 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1097 if (likely(ce->pin_count++))
1099 GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
1101 ret = execlists_context_deferred_alloc(ctx, engine);
1104 GEM_BUG_ON(!ce->state);
1106 ret = __context_pin(ctx, ce->state);
1110 vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
1111 if (IS_ERR(vaddr)) {
1112 ret = PTR_ERR(vaddr);
1116 ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias);
1120 intel_lr_context_descriptor_update(ctx, engine);
1122 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
1123 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1124 i915_ggtt_offset(ce->ring->vma);
1126 ce->state->obj->pin_global++;
1127 i915_gem_context_get(ctx);
1132 i915_gem_object_unpin_map(ce->state->obj);
1134 __i915_vma_unpin(ce->state);
1137 return ERR_PTR(ret);
1140 static void execlists_context_unpin(struct intel_engine_cs *engine,
1141 struct i915_gem_context *ctx)
1143 struct intel_context *ce = &ctx->engine[engine->id];
1145 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1146 GEM_BUG_ON(ce->pin_count == 0);
1148 if (--ce->pin_count)
1151 intel_ring_unpin(ce->ring);
1153 ce->state->obj->pin_global--;
1154 i915_gem_object_unpin_map(ce->state->obj);
1155 i915_vma_unpin(ce->state);
1157 i915_gem_context_put(ctx);
1160 static int execlists_request_alloc(struct drm_i915_gem_request *request)
1162 struct intel_engine_cs *engine = request->engine;
1163 struct intel_context *ce = &request->ctx->engine[engine->id];
1166 GEM_BUG_ON(!ce->pin_count);
1168 /* Flush enough space to reduce the likelihood of waiting after
1169 * we start building the request - in which case we will just
1170 * have to repeat work.
1172 request->reserved_space += EXECLISTS_REQUEST_SIZE;
1174 ret = intel_ring_wait_for_space(request->ring, request->reserved_space);
1178 /* Note that after this point, we have committed to using
1179 * this request as it is being used to both track the
1180 * state of engine initialisation and liveness of the
1181 * golden renderstate above. Think twice before you try
1182 * to cancel/unwind this request now.
1185 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
1190 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1191 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1192 * but there is a slight complication as this is applied in WA batch where the
1193 * values are only initialized once so we cannot take register value at the
1194 * beginning and reuse it further; hence we save its value to memory, upload a
1195 * constant value with bit21 set and then we restore it back with the saved value.
1196 * To simplify the WA, a constant value is formed by using the default value
1197 * of this register. This shouldn't be a problem because we are only modifying
1198 * it for a short period and this batch in non-premptible. We can ofcourse
1199 * use additional instructions that read the actual value of the register
1200 * at that time and set our bit of interest but it makes the WA complicated.
1202 * This WA is also required for Gen9 so extracting as a function avoids
1206 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
1208 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1209 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1210 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1213 *batch++ = MI_LOAD_REGISTER_IMM(1);
1214 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1215 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
1217 batch = gen8_emit_pipe_control(batch,
1218 PIPE_CONTROL_CS_STALL |
1219 PIPE_CONTROL_DC_FLUSH_ENABLE,
1222 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1223 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1224 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1231 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1232 * initialized at the beginning and shared across all contexts but this field
1233 * helps us to have multiple batches at different offsets and select them based
1234 * on a criteria. At the moment this batch always start at the beginning of the page
1235 * and at this point we don't have multiple wa_ctx batch buffers.
1237 * The number of WA applied are not known at the beginning; we use this field
1238 * to return the no of DWORDS written.
1240 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1241 * so it adds NOOPs as padding to make it cacheline aligned.
1242 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1243 * makes a complete batch buffer.
1245 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1247 /* WaDisableCtxRestoreArbitration:bdw,chv */
1248 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1250 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1251 if (IS_BROADWELL(engine->i915))
1252 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1254 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1255 /* Actual scratch location is at 128 bytes offset */
1256 batch = gen8_emit_pipe_control(batch,
1257 PIPE_CONTROL_FLUSH_L3 |
1258 PIPE_CONTROL_GLOBAL_GTT_IVB |
1259 PIPE_CONTROL_CS_STALL |
1260 PIPE_CONTROL_QW_WRITE,
1261 i915_ggtt_offset(engine->scratch) +
1262 2 * CACHELINE_BYTES);
1264 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1266 /* Pad to end of cacheline */
1267 while ((unsigned long)batch % CACHELINE_BYTES)
1271 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1272 * execution depends on the length specified in terms of cache lines
1273 * in the register CTX_RCS_INDIRECT_CTX
1279 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1281 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1283 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1284 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1286 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1287 *batch++ = MI_LOAD_REGISTER_IMM(1);
1288 *batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2);
1289 *batch++ = _MASKED_BIT_DISABLE(
1290 GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE);
1293 /* WaClearSlmSpaceAtContextSwitch:kbl */
1294 /* Actual scratch location is at 128 bytes offset */
1295 if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
1296 batch = gen8_emit_pipe_control(batch,
1297 PIPE_CONTROL_FLUSH_L3 |
1298 PIPE_CONTROL_GLOBAL_GTT_IVB |
1299 PIPE_CONTROL_CS_STALL |
1300 PIPE_CONTROL_QW_WRITE,
1301 i915_ggtt_offset(engine->scratch)
1302 + 2 * CACHELINE_BYTES);
1305 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1306 if (HAS_POOLED_EU(engine->i915)) {
1308 * EU pool configuration is setup along with golden context
1309 * during context initialization. This value depends on
1310 * device type (2x6 or 3x6) and needs to be updated based
1311 * on which subslice is disabled especially for 2x6
1312 * devices, however it is safe to load default
1313 * configuration of 3x6 device instead of masking off
1314 * corresponding bits because HW ignores bits of a disabled
1315 * subslice and drops down to appropriate config. Please
1316 * see render_state_setup() in i915_gem_render_state.c for
1317 * possible configurations, to avoid duplication they are
1318 * not shown here again.
1320 *batch++ = GEN9_MEDIA_POOL_STATE;
1321 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1322 *batch++ = 0x00777000;
1328 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1330 /* Pad to end of cacheline */
1331 while ((unsigned long)batch % CACHELINE_BYTES)
1338 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1343 * WaPipeControlBefore3DStateSamplePattern: cnl
1345 * Ensure the engine is idle prior to programming a
1346 * 3DSTATE_SAMPLE_PATTERN during a context restore.
1348 batch = gen8_emit_pipe_control(batch,
1349 PIPE_CONTROL_CS_STALL,
1352 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for
1353 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in
1354 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is
1355 * confusing. Since gen8_emit_pipe_control() already advances the
1356 * batch by 6 dwords, we advance the other 10 here, completing a
1357 * cacheline. It's not clear if the workaround requires this padding
1358 * before other commands, or if it's just the regular padding we would
1359 * already have for the workaround bb, so leave it here for now.
1361 for (i = 0; i < 10; i++)
1364 /* Pad to end of cacheline */
1365 while ((unsigned long)batch % CACHELINE_BYTES)
1371 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1373 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
1375 struct drm_i915_gem_object *obj;
1376 struct i915_vma *vma;
1379 obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE);
1381 return PTR_ERR(obj);
1383 vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
1389 err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
1393 engine->wa_ctx.vma = vma;
1397 i915_gem_object_put(obj);
1401 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
1403 i915_vma_unpin_and_release(&engine->wa_ctx.vma);
1406 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1408 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1410 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1411 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
1413 wa_bb_func_t wa_bb_fn[2];
1415 void *batch, *batch_ptr;
1419 if (GEM_WARN_ON(engine->id != RCS))
1422 switch (INTEL_GEN(engine->i915)) {
1424 wa_bb_fn[0] = gen10_init_indirectctx_bb;
1428 wa_bb_fn[0] = gen9_init_indirectctx_bb;
1432 wa_bb_fn[0] = gen8_init_indirectctx_bb;
1436 MISSING_CASE(INTEL_GEN(engine->i915));
1440 ret = lrc_setup_wa_ctx(engine);
1442 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1446 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1447 batch = batch_ptr = kmap_atomic(page);
1450 * Emit the two workaround batch buffers, recording the offset from the
1451 * start of the workaround batch buffer object for each and their
1454 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
1455 wa_bb[i]->offset = batch_ptr - batch;
1456 if (GEM_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset,
1457 CACHELINE_BYTES))) {
1462 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
1463 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
1466 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
1468 kunmap_atomic(batch);
1470 lrc_destroy_wa_ctx(engine);
1475 static u8 gtiir[] = {
1483 static void enable_execlists(struct intel_engine_cs *engine)
1485 struct drm_i915_private *dev_priv = engine->i915;
1487 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1490 * Make sure we're not enabling the new 12-deep CSB
1491 * FIFO as that requires a slightly updated handling
1492 * in the ctx switch irq. Since we're currently only
1493 * using only 2 elements of the enhanced execlists the
1494 * deeper FIFO it's not needed and it's not worth adding
1495 * more statements to the irq handler to support it.
1497 if (INTEL_GEN(dev_priv) >= 11)
1498 I915_WRITE(RING_MODE_GEN7(engine),
1499 _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
1501 I915_WRITE(RING_MODE_GEN7(engine),
1502 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1504 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1505 engine->status_page.ggtt_offset);
1506 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1508 /* Following the reset, we need to reload the CSB read/write pointers */
1509 engine->execlists.csb_head = -1;
1512 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1514 struct intel_engine_execlists * const execlists = &engine->execlists;
1517 ret = intel_mocs_init_engine(engine);
1521 intel_engine_reset_breadcrumbs(engine);
1522 intel_engine_init_hangcheck(engine);
1524 enable_execlists(engine);
1526 /* After a GPU reset, we may have requests to replay */
1527 if (execlists->first)
1528 tasklet_schedule(&execlists->tasklet);
1533 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1535 struct drm_i915_private *dev_priv = engine->i915;
1538 ret = gen8_init_common_ring(engine);
1542 /* We need to disable the AsyncFlip performance optimisations in order
1543 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1544 * programmed to '1' on all products.
1546 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1548 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1550 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1552 return init_workarounds_ring(engine);
1555 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1559 ret = gen8_init_common_ring(engine);
1563 return init_workarounds_ring(engine);
1566 static void reset_irq(struct intel_engine_cs *engine)
1568 struct drm_i915_private *dev_priv = engine->i915;
1571 GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
1574 * Clear any pending interrupt state.
1576 * We do it twice out of paranoia that some of the IIR are double
1577 * buffered, and if we only reset it once there may still be
1578 * an interrupt pending.
1580 for (i = 0; i < 2; i++) {
1581 I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
1582 GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift);
1583 POSTING_READ(GEN8_GT_IIR(gtiir[engine->id]));
1585 GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) &
1586 (GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift));
1588 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
1591 static void reset_common_ring(struct intel_engine_cs *engine,
1592 struct drm_i915_gem_request *request)
1594 struct intel_engine_execlists * const execlists = &engine->execlists;
1595 struct intel_context *ce;
1596 unsigned long flags;
1598 GEM_TRACE("%s seqno=%x\n",
1599 engine->name, request ? request->global_seqno : 0);
1603 spin_lock_irqsave(&engine->timeline->lock, flags);
1606 * Catch up with any missed context-switch interrupts.
1608 * Ideally we would just read the remaining CSB entries now that we
1609 * know the gpu is idle. However, the CSB registers are sometimes^W
1610 * often trashed across a GPU reset! Instead we have to rely on
1611 * guessing the missed context-switch events by looking at what
1612 * requests were completed.
1614 execlists_cancel_port_requests(execlists);
1616 /* Push back any incomplete requests for replay after the reset. */
1617 __unwind_incomplete_requests(engine);
1619 spin_unlock_irqrestore(&engine->timeline->lock, flags);
1621 /* Mark all CS interrupts as complete */
1622 execlists->active = 0;
1624 /* If the request was innocent, we leave the request in the ELSP
1625 * and will try to replay it on restarting. The context image may
1626 * have been corrupted by the reset, in which case we may have
1627 * to service a new GPU hang, but more likely we can continue on
1630 * If the request was guilty, we presume the context is corrupt
1631 * and have to at least restore the RING register in the context
1632 * image back to the expected values to skip over the guilty request.
1634 if (!request || request->fence.error != -EIO)
1637 /* We want a simple context + ring to execute the breadcrumb update.
1638 * We cannot rely on the context being intact across the GPU hang,
1639 * so clear it and rebuild just what we need for the breadcrumb.
1640 * All pending requests for this context will be zapped, and any
1641 * future request will be after userspace has had the opportunity
1642 * to recreate its own state.
1644 ce = &request->ctx->engine[engine->id];
1645 execlists_init_reg_state(ce->lrc_reg_state,
1646 request->ctx, engine, ce->ring);
1648 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1649 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1650 i915_ggtt_offset(ce->ring->vma);
1651 ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix;
1653 request->ring->head = request->postfix;
1654 intel_ring_update_space(request->ring);
1656 /* Reset WaIdleLiteRestore:bdw,skl as well */
1657 unwind_wa_tail(request);
1660 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1662 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1663 struct intel_engine_cs *engine = req->engine;
1664 const int num_lri_cmds = GEN8_3LVL_PDPES * 2;
1668 cs = intel_ring_begin(req, num_lri_cmds * 2 + 2);
1672 *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds);
1673 for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) {
1674 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1676 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
1677 *cs++ = upper_32_bits(pd_daddr);
1678 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
1679 *cs++ = lower_32_bits(pd_daddr);
1683 intel_ring_advance(req, cs);
1688 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1689 u64 offset, u32 len,
1690 const unsigned int flags)
1695 /* Don't rely in hw updating PDPs, specially in lite-restore.
1696 * Ideally, we should set Force PD Restore in ctx descriptor,
1697 * but we can't. Force Restore would be a second option, but
1698 * it is unsafe in case of lite-restore (because the ctx is
1699 * not idle). PML4 is allocated during ppgtt init so this is
1700 * not needed in 48-bit.*/
1701 if (req->ctx->ppgtt &&
1702 (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings) &&
1703 !i915_vm_is_48bit(&req->ctx->ppgtt->base) &&
1704 !intel_vgpu_active(req->i915)) {
1705 ret = intel_logical_ring_emit_pdps(req);
1709 req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1712 cs = intel_ring_begin(req, 4);
1717 * WaDisableCtxRestoreArbitration:bdw,chv
1719 * We don't need to perform MI_ARB_ENABLE as often as we do (in
1720 * particular all the gen that do not need the w/a at all!), if we
1721 * took care to make sure that on every switch into this context
1722 * (both ordinary and for preemption) that arbitrartion was enabled
1723 * we would be fine. However, there doesn't seem to be a downside to
1724 * being paranoid and making sure it is set before each batch and
1725 * every context-switch.
1727 * Note that if we fail to enable arbitration before the request
1728 * is complete, then we do not see the context-switch interrupt and
1729 * the engine hangs (with RING_HEAD == RING_TAIL).
1731 * That satisfies both the GPGPU w/a and our heavy-handed paranoia.
1733 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1735 /* FIXME(BDW): Address space and security selectors. */
1736 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
1737 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) |
1738 (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
1739 *cs++ = lower_32_bits(offset);
1740 *cs++ = upper_32_bits(offset);
1741 intel_ring_advance(req, cs);
1746 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
1748 struct drm_i915_private *dev_priv = engine->i915;
1749 I915_WRITE_IMR(engine,
1750 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1751 POSTING_READ_FW(RING_IMR(engine->mmio_base));
1754 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
1756 struct drm_i915_private *dev_priv = engine->i915;
1757 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1760 static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode)
1764 cs = intel_ring_begin(request, 4);
1768 cmd = MI_FLUSH_DW + 1;
1770 /* We always require a command barrier so that subsequent
1771 * commands, such as breadcrumb interrupts, are strictly ordered
1772 * wrt the contents of the write cache being flushed to memory
1773 * (and thus being coherent from the CPU).
1775 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1777 if (mode & EMIT_INVALIDATE) {
1778 cmd |= MI_INVALIDATE_TLB;
1779 if (request->engine->id == VCS)
1780 cmd |= MI_INVALIDATE_BSD;
1784 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1785 *cs++ = 0; /* upper addr */
1786 *cs++ = 0; /* value */
1787 intel_ring_advance(request, cs);
1792 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1795 struct intel_engine_cs *engine = request->engine;
1797 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1798 bool vf_flush_wa = false, dc_flush_wa = false;
1802 flags |= PIPE_CONTROL_CS_STALL;
1804 if (mode & EMIT_FLUSH) {
1805 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1806 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1807 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1808 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1811 if (mode & EMIT_INVALIDATE) {
1812 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1813 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1814 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1815 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1816 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1817 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1818 flags |= PIPE_CONTROL_QW_WRITE;
1819 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1822 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1825 if (IS_GEN9(request->i915))
1828 /* WaForGAMHang:kbl */
1829 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
1841 cs = intel_ring_begin(request, len);
1846 cs = gen8_emit_pipe_control(cs, 0, 0);
1849 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
1852 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
1855 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
1857 intel_ring_advance(request, cs);
1863 * Reserve space for 2 NOOPs at the end of each request to be
1864 * used as a workaround for not being allowed to do lite
1865 * restore with HEAD==TAIL (WaIdleLiteRestore).
1867 static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *cs)
1869 /* Ensure there's always at least one preemption point per-request. */
1870 *cs++ = MI_ARB_CHECK;
1872 request->wa_tail = intel_ring_offset(request, cs);
1875 static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs)
1877 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1878 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1880 cs = gen8_emit_ggtt_write(cs, request->global_seqno,
1881 intel_hws_seqno_address(request->engine));
1882 *cs++ = MI_USER_INTERRUPT;
1884 request->tail = intel_ring_offset(request, cs);
1885 assert_ring_tail_valid(request->ring, request->tail);
1887 gen8_emit_wa_tail(request, cs);
1889 static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
1891 static void gen8_emit_breadcrumb_rcs(struct drm_i915_gem_request *request,
1894 /* We're using qword write, seqno should be aligned to 8 bytes. */
1895 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
1897 cs = gen8_emit_ggtt_write_rcs(cs, request->global_seqno,
1898 intel_hws_seqno_address(request->engine));
1899 *cs++ = MI_USER_INTERRUPT;
1901 request->tail = intel_ring_offset(request, cs);
1902 assert_ring_tail_valid(request->ring, request->tail);
1904 gen8_emit_wa_tail(request, cs);
1906 static const int gen8_emit_breadcrumb_rcs_sz = 8 + WA_TAIL_DWORDS;
1908 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1912 ret = intel_ring_workarounds_emit(req);
1916 ret = intel_rcs_context_init_mocs(req);
1918 * Failing to program the MOCS is non-fatal.The system will not
1919 * run at peak performance. So generate an error and carry on.
1922 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1924 return i915_gem_render_state_emit(req);
1928 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1929 * @engine: Engine Command Streamer.
1931 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
1933 struct drm_i915_private *dev_priv;
1936 * Tasklet cannot be active at this point due intel_mark_active/idle
1937 * so this is just for documentation.
1939 if (WARN_ON(test_bit(TASKLET_STATE_SCHED,
1940 &engine->execlists.tasklet.state)))
1941 tasklet_kill(&engine->execlists.tasklet);
1943 dev_priv = engine->i915;
1945 if (engine->buffer) {
1946 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
1949 if (engine->cleanup)
1950 engine->cleanup(engine);
1952 intel_engine_cleanup_common(engine);
1954 lrc_destroy_wa_ctx(engine);
1956 engine->i915 = NULL;
1957 dev_priv->engine[engine->id] = NULL;
1961 static void execlists_set_default_submission(struct intel_engine_cs *engine)
1963 engine->submit_request = execlists_submit_request;
1964 engine->cancel_requests = execlists_cancel_requests;
1965 engine->schedule = execlists_schedule;
1966 engine->execlists.tasklet.func = execlists_submission_tasklet;
1968 engine->park = NULL;
1969 engine->unpark = NULL;
1971 engine->flags |= I915_ENGINE_SUPPORTS_STATS;
1973 engine->i915->caps.scheduler =
1974 I915_SCHEDULER_CAP_ENABLED |
1975 I915_SCHEDULER_CAP_PRIORITY;
1976 if (engine->i915->preempt_context)
1977 engine->i915->caps.scheduler |= I915_SCHEDULER_CAP_PREEMPTION;
1981 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
1983 /* Default vfuncs which can be overriden by each engine. */
1984 engine->init_hw = gen8_init_common_ring;
1985 engine->reset_hw = reset_common_ring;
1987 engine->context_pin = execlists_context_pin;
1988 engine->context_unpin = execlists_context_unpin;
1990 engine->request_alloc = execlists_request_alloc;
1992 engine->emit_flush = gen8_emit_flush;
1993 engine->emit_breadcrumb = gen8_emit_breadcrumb;
1994 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
1996 engine->set_default_submission = execlists_set_default_submission;
1998 engine->irq_enable = gen8_logical_ring_enable_irq;
1999 engine->irq_disable = gen8_logical_ring_disable_irq;
2000 engine->emit_bb_start = gen8_emit_bb_start;
2004 logical_ring_default_irqs(struct intel_engine_cs *engine)
2006 unsigned shift = engine->irq_shift;
2007 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
2008 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
2012 logical_ring_setup(struct intel_engine_cs *engine)
2014 struct drm_i915_private *dev_priv = engine->i915;
2015 enum forcewake_domains fw_domains;
2017 intel_engine_setup_common(engine);
2019 /* Intentionally left blank. */
2020 engine->buffer = NULL;
2022 fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
2026 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
2027 RING_CONTEXT_STATUS_PTR(engine),
2028 FW_REG_READ | FW_REG_WRITE);
2030 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
2031 RING_CONTEXT_STATUS_BUF_BASE(engine),
2034 engine->execlists.fw_domains = fw_domains;
2036 tasklet_init(&engine->execlists.tasklet,
2037 execlists_submission_tasklet, (unsigned long)engine);
2039 logical_ring_default_vfuncs(engine);
2040 logical_ring_default_irqs(engine);
2043 static int logical_ring_init(struct intel_engine_cs *engine)
2047 ret = intel_engine_init_common(engine);
2051 engine->execlists.elsp =
2052 engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
2054 engine->execlists.preempt_complete_status = ~0u;
2055 if (engine->i915->preempt_context)
2056 engine->execlists.preempt_complete_status =
2057 upper_32_bits(engine->i915->preempt_context->engine[engine->id].lrc_desc);
2062 intel_logical_ring_cleanup(engine);
2066 int logical_render_ring_init(struct intel_engine_cs *engine)
2068 struct drm_i915_private *dev_priv = engine->i915;
2071 logical_ring_setup(engine);
2073 if (HAS_L3_DPF(dev_priv))
2074 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2076 /* Override some for render ring. */
2077 if (INTEL_GEN(dev_priv) >= 9)
2078 engine->init_hw = gen9_init_render_ring;
2080 engine->init_hw = gen8_init_render_ring;
2081 engine->init_context = gen8_init_rcs_context;
2082 engine->emit_flush = gen8_emit_flush_render;
2083 engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;
2084 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz;
2086 ret = intel_engine_create_scratch(engine, PAGE_SIZE);
2090 ret = intel_init_workaround_bb(engine);
2093 * We continue even if we fail to initialize WA batch
2094 * because we only expect rare glitches but nothing
2095 * critical to prevent us from using GPU
2097 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2101 return logical_ring_init(engine);
2104 int logical_xcs_ring_init(struct intel_engine_cs *engine)
2106 logical_ring_setup(engine);
2108 return logical_ring_init(engine);
2112 make_rpcs(struct drm_i915_private *dev_priv)
2117 * No explicit RPCS request is needed to ensure full
2118 * slice/subslice/EU enablement prior to Gen9.
2120 if (INTEL_GEN(dev_priv) < 9)
2124 * Starting in Gen9, render power gating can leave
2125 * slice/subslice/EU in a partially enabled state. We
2126 * must make an explicit request through RPCS for full
2129 if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
2130 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2131 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
2132 GEN8_RPCS_S_CNT_SHIFT;
2133 rpcs |= GEN8_RPCS_ENABLE;
2136 if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
2137 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2138 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) <<
2139 GEN8_RPCS_SS_CNT_SHIFT;
2140 rpcs |= GEN8_RPCS_ENABLE;
2143 if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
2144 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2145 GEN8_RPCS_EU_MIN_SHIFT;
2146 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2147 GEN8_RPCS_EU_MAX_SHIFT;
2148 rpcs |= GEN8_RPCS_ENABLE;
2154 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2156 u32 indirect_ctx_offset;
2158 switch (INTEL_GEN(engine->i915)) {
2160 MISSING_CASE(INTEL_GEN(engine->i915));
2163 indirect_ctx_offset =
2164 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2167 indirect_ctx_offset =
2168 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2171 indirect_ctx_offset =
2172 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2176 return indirect_ctx_offset;
2179 static void execlists_init_reg_state(u32 *regs,
2180 struct i915_gem_context *ctx,
2181 struct intel_engine_cs *engine,
2182 struct intel_ring *ring)
2184 struct drm_i915_private *dev_priv = engine->i915;
2185 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
2186 u32 base = engine->mmio_base;
2187 bool rcs = engine->id == RCS;
2189 /* A context is actually a big batch buffer with several
2190 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
2191 * values we are setting here are only for the first context restore:
2192 * on a subsequent save, the GPU will recreate this batchbuffer with new
2193 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
2194 * we are not initializing here).
2196 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
2197 MI_LRI_FORCE_POSTED;
2199 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
2200 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2201 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT) |
2202 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2203 (HAS_RESOURCE_STREAMER(dev_priv) ?
2204 CTX_CTRL_RS_CTX_ENABLE : 0)));
2205 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
2206 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
2207 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
2208 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
2209 RING_CTL_SIZE(ring->size) | RING_VALID);
2210 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
2211 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
2212 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
2213 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
2214 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
2215 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
2217 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2219 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
2220 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
2221 RING_INDIRECT_CTX_OFFSET(base), 0);
2222 if (wa_ctx->indirect_ctx.size) {
2223 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2225 regs[CTX_RCS_INDIRECT_CTX + 1] =
2226 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
2227 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
2229 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
2230 intel_lr_indirect_ctx_offset(engine) << 6;
2233 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
2234 if (wa_ctx->per_ctx.size) {
2235 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2237 regs[CTX_BB_PER_CTX_PTR + 1] =
2238 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
2242 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2244 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
2245 /* PDP values well be assigned later if needed */
2246 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
2247 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
2248 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
2249 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
2250 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
2251 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
2252 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
2253 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
2255 if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) {
2256 /* 64b PPGTT (48bit canonical)
2257 * PDP0_DESCRIPTOR contains the base address to PML4 and
2258 * other PDP Descriptors are ignored.
2260 ASSIGN_CTX_PML4(ppgtt, regs);
2264 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2265 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2266 make_rpcs(dev_priv));
2268 i915_oa_init_reg_state(engine, ctx, regs);
2273 populate_lr_context(struct i915_gem_context *ctx,
2274 struct drm_i915_gem_object *ctx_obj,
2275 struct intel_engine_cs *engine,
2276 struct intel_ring *ring)
2282 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2284 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2288 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
2289 if (IS_ERR(vaddr)) {
2290 ret = PTR_ERR(vaddr);
2291 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2294 ctx_obj->mm.dirty = true;
2296 if (engine->default_state) {
2298 * We only want to copy over the template context state;
2299 * skipping over the headers reserved for GuC communication,
2300 * leaving those as zero.
2302 const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE;
2305 defaults = i915_gem_object_pin_map(engine->default_state,
2307 if (IS_ERR(defaults))
2308 return PTR_ERR(defaults);
2310 memcpy(vaddr + start, defaults + start, engine->context_size);
2311 i915_gem_object_unpin_map(engine->default_state);
2314 /* The second page of the context object contains some fields which must
2315 * be set up prior to the first execution. */
2316 regs = vaddr + LRC_STATE_PN * PAGE_SIZE;
2317 execlists_init_reg_state(regs, ctx, engine, ring);
2318 if (!engine->default_state)
2319 regs[CTX_CONTEXT_CONTROL + 1] |=
2320 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
2321 if (ctx == ctx->i915->preempt_context)
2322 regs[CTX_CONTEXT_CONTROL + 1] |=
2323 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2324 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);
2326 i915_gem_object_unpin_map(ctx_obj);
2331 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
2332 struct intel_engine_cs *engine)
2334 struct drm_i915_gem_object *ctx_obj;
2335 struct intel_context *ce = &ctx->engine[engine->id];
2336 struct i915_vma *vma;
2337 uint32_t context_size;
2338 struct intel_ring *ring;
2344 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
2347 * Before the actual start of the context image, we insert a few pages
2348 * for our own use and for sharing with the GuC.
2350 context_size += LRC_HEADER_PAGES * PAGE_SIZE;
2352 ctx_obj = i915_gem_object_create(ctx->i915, context_size);
2353 if (IS_ERR(ctx_obj)) {
2354 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2355 return PTR_ERR(ctx_obj);
2358 vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.base, NULL);
2361 goto error_deref_obj;
2364 ring = intel_engine_create_ring(engine, ctx->ring_size);
2366 ret = PTR_ERR(ring);
2367 goto error_deref_obj;
2370 ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2372 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2373 goto error_ring_free;
2382 intel_ring_free(ring);
2384 i915_gem_object_put(ctx_obj);
2388 void intel_lr_context_resume(struct drm_i915_private *dev_priv)
2390 struct intel_engine_cs *engine;
2391 struct i915_gem_context *ctx;
2392 enum intel_engine_id id;
2394 /* Because we emit WA_TAIL_DWORDS there may be a disparity
2395 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2396 * that stored in context. As we only write new commands from
2397 * ce->ring->tail onwards, everything before that is junk. If the GPU
2398 * starts reading from its RING_HEAD from the context, it may try to
2399 * execute that junk and die.
2401 * So to avoid that we reset the context images upon resume. For
2402 * simplicity, we just zero everything out.
2404 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
2405 for_each_engine(engine, dev_priv, id) {
2406 struct intel_context *ce = &ctx->engine[engine->id];
2412 reg = i915_gem_object_pin_map(ce->state->obj,
2414 if (WARN_ON(IS_ERR(reg)))
2417 reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg);
2418 reg[CTX_RING_HEAD+1] = 0;
2419 reg[CTX_RING_TAIL+1] = 0;
2421 ce->state->obj->mm.dirty = true;
2422 i915_gem_object_unpin_map(ce->state->obj);
2424 intel_ring_reset(ce->ring, 0);