2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/i915_drm.h>
137 #include "i915_drv.h"
138 #include "i915_gem_render_state.h"
139 #include "i915_reset.h"
140 #include "i915_vgpu.h"
141 #include "intel_lrc_reg.h"
142 #include "intel_mocs.h"
143 #include "intel_workarounds.h"
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define GEN8_CTX_STATUS_COMPLETED_MASK \
160 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
162 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
163 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
164 #define WA_TAIL_DWORDS 2
165 #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
167 #define ACTIVE_PRIORITY (I915_PRIORITY_NEWCLIENT | I915_PRIORITY_NOSEMAPHORE)
169 static int execlists_context_deferred_alloc(struct intel_context *ce,
170 struct intel_engine_cs *engine);
171 static void execlists_init_reg_state(u32 *reg_state,
172 struct intel_context *ce,
173 struct intel_engine_cs *engine,
174 struct intel_ring *ring);
176 static inline struct i915_priolist *to_priolist(struct rb_node *rb)
178 return rb_entry(rb, struct i915_priolist, node);
181 static inline int rq_prio(const struct i915_request *rq)
183 return rq->sched.attr.priority;
186 static int effective_prio(const struct i915_request *rq)
188 int prio = rq_prio(rq);
191 * On unwinding the active request, we give it a priority bump
192 * equivalent to a freshly submitted request. This protects it from
193 * being gazumped again, but it would be preferable if we didn't
194 * let it be gazumped in the first place!
196 * See __unwind_incomplete_requests()
198 if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(rq)) {
200 * After preemption, we insert the active request at the
201 * end of the new priority level. This means that we will be
202 * _lower_ priority than the preemptee all things equal (and
203 * so the preemption is valid), so adjust our comparison
206 prio |= ACTIVE_PRIORITY;
210 /* Restrict mere WAIT boosts from triggering preemption */
211 return prio | __NO_PREEMPTION;
214 static int queue_prio(const struct intel_engine_execlists *execlists)
216 struct i915_priolist *p;
219 rb = rb_first_cached(&execlists->queue);
224 * As the priolist[] are inverted, with the highest priority in [0],
225 * we have to flip the index value to become priority.
228 return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used);
231 static inline bool need_preempt(const struct intel_engine_cs *engine,
232 const struct i915_request *rq)
236 if (!intel_engine_has_preemption(engine))
239 if (i915_request_completed(rq))
243 * Check if the current priority hint merits a preemption attempt.
245 * We record the highest value priority we saw during rescheduling
246 * prior to this dequeue, therefore we know that if it is strictly
247 * less than the current tail of ESLP[0], we do not need to force
248 * a preempt-to-idle cycle.
250 * However, the priority hint is a mere hint that we may need to
251 * preempt. If that hint is stale or we may be trying to preempt
252 * ourselves, ignore the request.
254 last_prio = effective_prio(rq);
255 if (!__execlists_need_preempt(engine->execlists.queue_priority_hint,
260 * Check against the first request in ELSP[1], it will, thanks to the
261 * power of PI, be the highest priority of that context.
263 if (!list_is_last(&rq->link, &engine->timeline.requests) &&
264 rq_prio(list_next_entry(rq, link)) > last_prio)
268 * If the inflight context did not trigger the preemption, then maybe
269 * it was the set of queued requests? Pick the highest priority in
270 * the queue (the first active priolist) and see if it deserves to be
271 * running instead of ELSP[0].
273 * The highest priority request in the queue can not be either
274 * ELSP[0] or ELSP[1] as, thanks again to PI, if it was the same
275 * context, it's priority would not exceed ELSP[0] aka last_prio.
277 return queue_prio(&engine->execlists) > last_prio;
280 __maybe_unused static inline bool
281 assert_priority_queue(const struct i915_request *prev,
282 const struct i915_request *next)
284 const struct intel_engine_execlists *execlists =
285 &prev->engine->execlists;
288 * Without preemption, the prev may refer to the still active element
289 * which we refuse to let go.
291 * Even with preemption, there are times when we think it is better not
292 * to preempt and leave an ostensibly lower priority request in flight.
294 if (port_request(execlists->port) == prev)
297 return rq_prio(prev) >= rq_prio(next);
301 * The context descriptor encodes various attributes of a context,
302 * including its GTT address and some flags. Because it's fairly
303 * expensive to calculate, we'll just do it once and cache the result,
304 * which remains valid until the context is unpinned.
306 * This is what a descriptor looks like, from LSB to MSB::
308 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
309 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
310 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC)
311 * bits 53-54: mbz, reserved for use by hardware
312 * bits 55-63: group ID, currently unused and set to 0
314 * Starting from Gen11, the upper dword of the descriptor has a new format:
316 * bits 32-36: reserved
317 * bits 37-47: SW context ID
318 * bits 48:53: engine instance
319 * bit 54: mbz, reserved for use by hardware
320 * bits 55-60: SW counter
321 * bits 61-63: engine class
323 * engine info, SW context ID and SW counter need to form a unique number
324 * (Context ID) per lrc.
327 lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine)
329 struct i915_gem_context *ctx = ce->gem_context;
332 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH)));
333 BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH)));
335 desc = ctx->desc_template; /* bits 0-11 */
336 GEM_BUG_ON(desc & GENMASK_ULL(63, 12));
338 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
340 GEM_BUG_ON(desc & GENMASK_ULL(63, 32));
343 * The following 32bits are copied into the OA reports (dword 2).
344 * Consider updating oa_get_render_ctx_id in i915_perf.c when changing
347 if (INTEL_GEN(engine->i915) >= 11) {
348 GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
349 desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
352 desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
355 /* TODO: decide what to do with SW counter (bits 55-60) */
357 desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
360 GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH));
361 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
367 static void unwind_wa_tail(struct i915_request *rq)
369 rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES);
370 assert_ring_tail_valid(rq->ring, rq->tail);
373 static struct i915_request *
374 __unwind_incomplete_requests(struct intel_engine_cs *engine)
376 struct i915_request *rq, *rn, *active = NULL;
377 struct list_head *uninitialized_var(pl);
378 int prio = I915_PRIORITY_INVALID | ACTIVE_PRIORITY;
380 lockdep_assert_held(&engine->timeline.lock);
382 list_for_each_entry_safe_reverse(rq, rn,
383 &engine->timeline.requests,
385 if (i915_request_completed(rq))
388 __i915_request_unsubmit(rq);
391 GEM_BUG_ON(rq->hw_context->active);
393 GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
394 if (rq_prio(rq) != prio) {
396 pl = i915_sched_lookup_priolist(engine, prio);
398 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
400 list_add(&rq->sched.link, pl);
406 * The active request is now effectively the start of a new client
407 * stream, so give it the equivalent small priority bump to prevent
408 * it being gazumped a second time by another peer.
410 * Note we have to be careful not to apply a priority boost to a request
411 * still spinning on its semaphores. If the request hasn't started, that
412 * means it is still waiting for its dependencies to be signaled, and
413 * if we apply a priority boost to this request, we will boost it past
414 * its signalers and so break PI.
416 * One consequence of this preemption boost is that we may jump
417 * over lesser priorities (such as I915_PRIORITY_WAIT), effectively
418 * making those priorities non-preemptible. They will be moved forward
419 * in the priority queue, but they will not gain immediate access to
422 if (~prio & ACTIVE_PRIORITY && __i915_request_has_started(active)) {
423 prio |= ACTIVE_PRIORITY;
424 active->sched.attr.priority = prio;
425 list_move_tail(&active->sched.link,
426 i915_sched_lookup_priolist(engine, prio));
433 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
435 struct intel_engine_cs *engine =
436 container_of(execlists, typeof(*engine), execlists);
438 __unwind_incomplete_requests(engine);
442 execlists_context_status_change(struct i915_request *rq, unsigned long status)
445 * Only used when GVT-g is enabled now. When GVT-g is disabled,
446 * The compiler should eliminate this function as dead-code.
448 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
451 atomic_notifier_call_chain(&rq->engine->context_status_notifier,
456 execlists_user_begin(struct intel_engine_execlists *execlists,
457 const struct execlist_port *port)
459 execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER);
463 execlists_user_end(struct intel_engine_execlists *execlists)
465 execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
469 execlists_context_schedule_in(struct i915_request *rq)
471 GEM_BUG_ON(rq->hw_context->active);
473 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
474 intel_engine_context_in(rq->engine);
475 rq->hw_context->active = rq->engine;
479 execlists_context_schedule_out(struct i915_request *rq, unsigned long status)
481 rq->hw_context->active = NULL;
482 intel_engine_context_out(rq->engine);
483 execlists_context_status_change(rq, status);
484 trace_i915_request_out(rq);
487 static u64 execlists_update_context(struct i915_request *rq)
489 struct intel_context *ce = rq->hw_context;
491 ce->lrc_reg_state[CTX_RING_TAIL + 1] =
492 intel_ring_set_tail(rq->ring, rq->tail);
495 * Make sure the context image is complete before we submit it to HW.
497 * Ostensibly, writes (including the WCB) should be flushed prior to
498 * an uncached write such as our mmio register access, the empirical
499 * evidence (esp. on Braswell) suggests that the WC write into memory
500 * may not be visible to the HW prior to the completion of the UC
501 * register write and that we may begin execution from the context
502 * before its image is complete leading to invalid PD chasing.
504 * Furthermore, Braswell, at least, wants a full mb to be sure that
505 * the writes are coherent in memory (visible to the GPU) prior to
506 * execution, and not just visible to other CPUs (as is the result of
513 static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)
515 if (execlists->ctrl_reg) {
516 writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
517 writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);
519 writel(upper_32_bits(desc), execlists->submit_reg);
520 writel(lower_32_bits(desc), execlists->submit_reg);
524 static void execlists_submit_ports(struct intel_engine_cs *engine)
526 struct intel_engine_execlists *execlists = &engine->execlists;
527 struct execlist_port *port = execlists->port;
531 * We can skip acquiring intel_runtime_pm_get() here as it was taken
532 * on our behalf by the request (see i915_gem_mark_busy()) and it will
533 * not be relinquished until the device is idle (see
534 * i915_gem_idle_work_handler()). As a precaution, we make sure
535 * that all ELSP are drained i.e. we have processed the CSB,
536 * before allowing ourselves to idle and calling intel_runtime_pm_put().
538 GEM_BUG_ON(!engine->i915->gt.awake);
541 * ELSQ note: the submit queue is not cleared after being submitted
542 * to the HW so we need to make sure we always clean it up. This is
543 * currently ensured by the fact that we always write the same number
544 * of elsq entries, keep this in mind before changing the loop below.
546 for (n = execlists_num_ports(execlists); n--; ) {
547 struct i915_request *rq;
551 rq = port_unpack(&port[n], &count);
553 GEM_BUG_ON(count > !n);
555 execlists_context_schedule_in(rq);
556 port_set(&port[n], port_pack(rq, count));
557 desc = execlists_update_context(rq);
558 GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
560 GEM_TRACE("%s in[%d]: ctx=%d.%d, fence %llx:%lld (current %d), prio=%d\n",
562 port[n].context_id, count,
563 rq->fence.context, rq->fence.seqno,
571 write_desc(execlists, desc, n);
574 /* we need to manually load the submit queue */
575 if (execlists->ctrl_reg)
576 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
578 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
581 static bool ctx_single_port_submission(const struct intel_context *ce)
583 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
584 i915_gem_context_force_single_submission(ce->gem_context));
587 static bool can_merge_ctx(const struct intel_context *prev,
588 const struct intel_context *next)
593 if (ctx_single_port_submission(prev))
599 static bool can_merge_rq(const struct i915_request *prev,
600 const struct i915_request *next)
602 GEM_BUG_ON(!assert_priority_queue(prev, next));
604 if (!can_merge_ctx(prev->hw_context, next->hw_context))
610 static void port_assign(struct execlist_port *port, struct i915_request *rq)
612 GEM_BUG_ON(rq == port_request(port));
614 if (port_isset(port))
615 i915_request_put(port_request(port));
617 port_set(port, port_pack(i915_request_get(rq), port_count(port)));
620 static void inject_preempt_context(struct intel_engine_cs *engine)
622 struct intel_engine_execlists *execlists = &engine->execlists;
623 struct intel_context *ce = engine->preempt_context;
626 GEM_BUG_ON(execlists->preempt_complete_status !=
627 upper_32_bits(ce->lrc_desc));
630 * Switch to our empty preempt context so
631 * the state of the GPU is known (idle).
633 GEM_TRACE("%s\n", engine->name);
634 for (n = execlists_num_ports(execlists); --n; )
635 write_desc(execlists, 0, n);
637 write_desc(execlists, ce->lrc_desc, n);
639 /* we need to manually load the submit queue */
640 if (execlists->ctrl_reg)
641 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
643 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
644 execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT);
646 (void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);
649 static void complete_preempt_context(struct intel_engine_execlists *execlists)
651 GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT));
653 if (inject_preempt_hang(execlists))
656 execlists_cancel_port_requests(execlists);
657 __unwind_incomplete_requests(container_of(execlists,
658 struct intel_engine_cs,
662 static void execlists_dequeue(struct intel_engine_cs *engine)
664 struct intel_engine_execlists * const execlists = &engine->execlists;
665 struct execlist_port *port = execlists->port;
666 const struct execlist_port * const last_port =
667 &execlists->port[execlists->port_mask];
668 struct i915_request *last = port_request(port);
673 * Hardware submission is through 2 ports. Conceptually each port
674 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
675 * static for a context, and unique to each, so we only execute
676 * requests belonging to a single context from each ring. RING_HEAD
677 * is maintained by the CS in the context image, it marks the place
678 * where it got up to last time, and through RING_TAIL we tell the CS
679 * where we want to execute up to this time.
681 * In this list the requests are in order of execution. Consecutive
682 * requests from the same context are adjacent in the ringbuffer. We
683 * can combine these requests into a single RING_TAIL update:
685 * RING_HEAD...req1...req2
687 * since to execute req2 the CS must first execute req1.
689 * Our goal then is to point each port to the end of a consecutive
690 * sequence of requests as being the most optimal (fewest wake ups
691 * and context switches) submission.
696 * Don't resubmit or switch until all outstanding
697 * preemptions (lite-restore) are seen. Then we
698 * know the next preemption status we see corresponds
699 * to this ELSP update.
701 GEM_BUG_ON(!execlists_is_active(execlists,
702 EXECLISTS_ACTIVE_USER));
703 GEM_BUG_ON(!port_count(&port[0]));
706 * If we write to ELSP a second time before the HW has had
707 * a chance to respond to the previous write, we can confuse
708 * the HW and hit "undefined behaviour". After writing to ELSP,
709 * we must then wait until we see a context-switch event from
710 * the HW to indicate that it has had a chance to respond.
712 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
715 if (need_preempt(engine, last)) {
716 inject_preempt_context(engine);
721 * In theory, we could coalesce more requests onto
722 * the second port (the first port is active, with
723 * no preemptions pending). However, that means we
724 * then have to deal with the possible lite-restore
725 * of the second port (as we submit the ELSP, there
726 * may be a context-switch) but also we may complete
727 * the resubmission before the context-switch. Ergo,
728 * coalescing onto the second port will cause a
729 * preemption event, but we cannot predict whether
730 * that will affect port[0] or port[1].
732 * If the second port is already active, we can wait
733 * until the next context-switch before contemplating
734 * new requests. The GPU will be busy and we should be
735 * able to resubmit the new ELSP before it idles,
736 * avoiding pipeline bubbles (momentary pauses where
737 * the driver is unable to keep up the supply of new
738 * work). However, we have to double check that the
739 * priorities of the ports haven't been switch.
741 if (port_count(&port[1]))
745 * WaIdleLiteRestore:bdw,skl
746 * Apply the wa NOOPs to prevent
747 * ring:HEAD == rq:TAIL as we resubmit the
748 * request. See gen8_emit_fini_breadcrumb() for
749 * where we prepare the padding after the
750 * end of the request.
752 last->tail = last->wa_tail;
755 while ((rb = rb_first_cached(&execlists->queue))) {
756 struct i915_priolist *p = to_priolist(rb);
757 struct i915_request *rq, *rn;
760 priolist_for_each_request_consume(rq, rn, p, i) {
762 * Can we combine this request with the current port?
763 * It has to be the same context/ringbuffer and not
764 * have any exceptions (e.g. GVT saying never to
767 * If we can combine the requests, we can execute both
768 * by updating the RING_TAIL to point to the end of the
769 * second request, and so we never need to tell the
770 * hardware about the first.
772 if (last && !can_merge_rq(last, rq)) {
774 * If we are on the second port and cannot
775 * combine this request with the last, then we
778 if (port == last_port)
782 * We must not populate both ELSP[] with the
783 * same LRCA, i.e. we must submit 2 different
784 * contexts if we submit 2 ELSP.
786 if (last->hw_context == rq->hw_context)
790 * If GVT overrides us we only ever submit
791 * port[0], leaving port[1] empty. Note that we
792 * also have to be careful that we don't queue
793 * the same context (even though a different
794 * request) to the second port.
796 if (ctx_single_port_submission(last->hw_context) ||
797 ctx_single_port_submission(rq->hw_context))
802 port_assign(port, last);
805 GEM_BUG_ON(port_isset(port));
808 list_del_init(&rq->sched.link);
810 __i915_request_submit(rq);
811 trace_i915_request_in(rq, port_index(port, execlists));
817 rb_erase_cached(&p->node, &execlists->queue);
818 i915_priolist_free(p);
823 * Here be a bit of magic! Or sleight-of-hand, whichever you prefer.
825 * We choose the priority hint such that if we add a request of greater
826 * priority than this, we kick the submission tasklet to decide on
827 * the right order of submitting the requests to hardware. We must
828 * also be prepared to reorder requests as they are in-flight on the
829 * HW. We derive the priority hint then as the first "hole" in
830 * the HW submission ports and if there are no available slots,
831 * the priority of the lowest executing request, i.e. last.
833 * When we do receive a higher priority request ready to run from the
834 * user, see queue_request(), the priority hint is bumped to that
835 * request triggering preemption on the next dequeue (or subsequent
836 * interrupt for secondary ports).
838 execlists->queue_priority_hint = queue_prio(execlists);
841 port_assign(port, last);
842 execlists_submit_ports(engine);
845 /* We must always keep the beast fed if we have work piled up */
846 GEM_BUG_ON(rb_first_cached(&execlists->queue) &&
847 !port_isset(execlists->port));
849 /* Re-evaluate the executing context setup after each preemptive kick */
851 execlists_user_begin(execlists, execlists->port);
853 /* If the engine is now idle, so should be the flag; and vice versa. */
854 GEM_BUG_ON(execlists_is_active(&engine->execlists,
855 EXECLISTS_ACTIVE_USER) ==
856 !port_isset(engine->execlists.port));
860 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
862 struct execlist_port *port = execlists->port;
863 unsigned int num_ports = execlists_num_ports(execlists);
865 while (num_ports-- && port_isset(port)) {
866 struct i915_request *rq = port_request(port);
868 GEM_TRACE("%s:port%u fence %llx:%lld, (current %d)\n",
870 (unsigned int)(port - execlists->port),
871 rq->fence.context, rq->fence.seqno,
874 GEM_BUG_ON(!execlists->active);
875 execlists_context_schedule_out(rq,
876 i915_request_completed(rq) ?
877 INTEL_CONTEXT_SCHEDULE_OUT :
878 INTEL_CONTEXT_SCHEDULE_PREEMPTED);
880 i915_request_put(rq);
882 memset(port, 0, sizeof(*port));
886 execlists_clear_all_active(execlists);
890 invalidate_csb_entries(const u32 *first, const u32 *last)
892 clflush((void *)first);
893 clflush((void *)last);
896 static void reset_csb_pointers(struct intel_engine_execlists *execlists)
898 const unsigned int reset_value = GEN8_CSB_ENTRIES - 1;
901 * After a reset, the HW starts writing into CSB entry [0]. We
902 * therefore have to set our HEAD pointer back one entry so that
903 * the *first* entry we check is entry 0. To complicate this further,
904 * as we don't wait for the first interrupt after reset, we have to
905 * fake the HW write to point back to the last entry so that our
906 * inline comparison of our cached head position against the last HW
907 * write works even before the first interrupt.
909 execlists->csb_head = reset_value;
910 WRITE_ONCE(*execlists->csb_write, reset_value);
912 invalidate_csb_entries(&execlists->csb_status[0],
913 &execlists->csb_status[GEN8_CSB_ENTRIES - 1]);
916 static void nop_submission_tasklet(unsigned long data)
918 /* The driver is wedged; don't process any more events. */
921 static void execlists_cancel_requests(struct intel_engine_cs *engine)
923 struct intel_engine_execlists * const execlists = &engine->execlists;
924 struct i915_request *rq, *rn;
928 GEM_TRACE("%s\n", engine->name);
931 * Before we call engine->cancel_requests(), we should have exclusive
932 * access to the submission state. This is arranged for us by the
933 * caller disabling the interrupt generation, the tasklet and other
934 * threads that may then access the same state, giving us a free hand
935 * to reset state. However, we still need to let lockdep be aware that
936 * we know this state may be accessed in hardirq context, so we
937 * disable the irq around this manipulation and we want to keep
938 * the spinlock focused on its duties and not accidentally conflate
939 * coverage to the submission's irq state. (Similarly, although we
940 * shouldn't need to disable irq around the manipulation of the
941 * submission's irq state, we also wish to remind ourselves that
944 spin_lock_irqsave(&engine->timeline.lock, flags);
946 /* Cancel the requests on the HW and clear the ELSP tracker. */
947 execlists_cancel_port_requests(execlists);
948 execlists_user_end(execlists);
950 /* Mark all executing requests as skipped. */
951 list_for_each_entry(rq, &engine->timeline.requests, link) {
952 if (!i915_request_signaled(rq))
953 dma_fence_set_error(&rq->fence, -EIO);
955 i915_request_mark_complete(rq);
958 /* Flush the queued requests to the timeline list (for retiring). */
959 while ((rb = rb_first_cached(&execlists->queue))) {
960 struct i915_priolist *p = to_priolist(rb);
963 priolist_for_each_request_consume(rq, rn, p, i) {
964 list_del_init(&rq->sched.link);
965 __i915_request_submit(rq);
966 dma_fence_set_error(&rq->fence, -EIO);
967 i915_request_mark_complete(rq);
970 rb_erase_cached(&p->node, &execlists->queue);
971 i915_priolist_free(p);
974 /* Remaining _unready_ requests will be nop'ed when submitted */
976 execlists->queue_priority_hint = INT_MIN;
977 execlists->queue = RB_ROOT_CACHED;
978 GEM_BUG_ON(port_isset(execlists->port));
980 GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet));
981 execlists->tasklet.func = nop_submission_tasklet;
983 spin_unlock_irqrestore(&engine->timeline.lock, flags);
987 reset_in_progress(const struct intel_engine_execlists *execlists)
989 return unlikely(!__tasklet_is_enabled(&execlists->tasklet));
992 static void process_csb(struct intel_engine_cs *engine)
994 struct intel_engine_execlists * const execlists = &engine->execlists;
995 struct execlist_port *port = execlists->port;
996 const u32 * const buf = execlists->csb_status;
999 lockdep_assert_held(&engine->timeline.lock);
1002 * Note that csb_write, csb_status may be either in HWSP or mmio.
1003 * When reading from the csb_write mmio register, we have to be
1004 * careful to only use the GEN8_CSB_WRITE_PTR portion, which is
1005 * the low 4bits. As it happens we know the next 4bits are always
1006 * zero and so we can simply masked off the low u8 of the register
1007 * and treat it identically to reading from the HWSP (without having
1008 * to use explicit shifting and masking, and probably bifurcating
1009 * the code to handle the legacy mmio read).
1011 head = execlists->csb_head;
1012 tail = READ_ONCE(*execlists->csb_write);
1013 GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail);
1014 if (unlikely(head == tail))
1018 * Hopefully paired with a wmb() in HW!
1020 * We must complete the read of the write pointer before any reads
1021 * from the CSB, so that we do not see stale values. Without an rmb
1022 * (lfence) the HW may speculatively perform the CSB[] reads *before*
1023 * we perform the READ_ONCE(*csb_write).
1028 struct i915_request *rq;
1029 unsigned int status;
1032 if (++head == GEN8_CSB_ENTRIES)
1036 * We are flying near dragons again.
1038 * We hold a reference to the request in execlist_port[]
1039 * but no more than that. We are operating in softirq
1040 * context and so cannot hold any mutex or sleep. That
1041 * prevents us stopping the requests we are processing
1042 * in port[] from being retired simultaneously (the
1043 * breadcrumb will be complete before we see the
1044 * context-switch). As we only hold the reference to the
1045 * request, any pointer chasing underneath the request
1046 * is subject to a potential use-after-free. Thus we
1047 * store all of the bookkeeping within port[] as
1048 * required, and avoid using unguarded pointers beneath
1049 * request itself. The same applies to the atomic
1053 GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n",
1055 buf[2 * head + 0], buf[2 * head + 1],
1058 status = buf[2 * head];
1059 if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE |
1060 GEN8_CTX_STATUS_PREEMPTED))
1061 execlists_set_active(execlists,
1062 EXECLISTS_ACTIVE_HWACK);
1063 if (status & GEN8_CTX_STATUS_ACTIVE_IDLE)
1064 execlists_clear_active(execlists,
1065 EXECLISTS_ACTIVE_HWACK);
1067 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
1070 /* We should never get a COMPLETED | IDLE_ACTIVE! */
1071 GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE);
1073 if (status & GEN8_CTX_STATUS_COMPLETE &&
1074 buf[2*head + 1] == execlists->preempt_complete_status) {
1075 GEM_TRACE("%s preempt-idle\n", engine->name);
1076 complete_preempt_context(execlists);
1080 if (status & GEN8_CTX_STATUS_PREEMPTED &&
1081 execlists_is_active(execlists,
1082 EXECLISTS_ACTIVE_PREEMPT))
1085 GEM_BUG_ON(!execlists_is_active(execlists,
1086 EXECLISTS_ACTIVE_USER));
1088 rq = port_unpack(port, &count);
1089 GEM_TRACE("%s out[0]: ctx=%d.%d, fence %llx:%lld (current %d), prio=%d\n",
1091 port->context_id, count,
1092 rq ? rq->fence.context : 0,
1093 rq ? rq->fence.seqno : 0,
1094 rq ? hwsp_seqno(rq) : 0,
1095 rq ? rq_prio(rq) : 0);
1097 /* Check the context/desc id for this event matches */
1098 GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id);
1100 GEM_BUG_ON(count == 0);
1103 * On the final event corresponding to the
1104 * submission of this context, we expect either
1105 * an element-switch event or a completion
1106 * event (and on completion, the active-idle
1107 * marker). No more preemptions, lite-restore
1110 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
1111 GEM_BUG_ON(port_isset(&port[1]) &&
1112 !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH));
1113 GEM_BUG_ON(!port_isset(&port[1]) &&
1114 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
1117 * We rely on the hardware being strongly
1118 * ordered, that the breadcrumb write is
1119 * coherent (visible from the CPU) before the
1120 * user interrupt and CSB is processed.
1122 GEM_BUG_ON(!i915_request_completed(rq));
1124 execlists_context_schedule_out(rq,
1125 INTEL_CONTEXT_SCHEDULE_OUT);
1126 i915_request_put(rq);
1128 GEM_TRACE("%s completed ctx=%d\n",
1129 engine->name, port->context_id);
1131 port = execlists_port_complete(execlists, port);
1132 if (port_isset(port))
1133 execlists_user_begin(execlists, port);
1135 execlists_user_end(execlists);
1137 port_set(port, port_pack(rq, count));
1139 } while (head != tail);
1141 execlists->csb_head = head;
1144 * Gen11 has proven to fail wrt global observation point between
1145 * entry and tail update, failing on the ordering and thus
1146 * we see an old entry in the context status buffer.
1148 * Forcibly evict out entries for the next gpu csb update,
1149 * to increase the odds that we get a fresh entries with non
1150 * working hardware. The cost for doing so comes out mostly with
1151 * the wash as hardware, working or not, will need to do the
1152 * invalidation before.
1154 invalidate_csb_entries(&buf[0], &buf[GEN8_CSB_ENTRIES - 1]);
1157 static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
1159 lockdep_assert_held(&engine->timeline.lock);
1161 process_csb(engine);
1162 if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT))
1163 execlists_dequeue(engine);
1167 * Check the unread Context Status Buffers and manage the submission of new
1168 * contexts to the ELSP accordingly.
1170 static void execlists_submission_tasklet(unsigned long data)
1172 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
1173 unsigned long flags;
1175 GEM_TRACE("%s awake?=%d, active=%x\n",
1177 !!engine->i915->gt.awake,
1178 engine->execlists.active);
1180 spin_lock_irqsave(&engine->timeline.lock, flags);
1181 __execlists_submission_tasklet(engine);
1182 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1185 static void queue_request(struct intel_engine_cs *engine,
1186 struct i915_sched_node *node,
1189 list_add_tail(&node->link, i915_sched_lookup_priolist(engine, prio));
1192 static void __submit_queue_imm(struct intel_engine_cs *engine)
1194 struct intel_engine_execlists * const execlists = &engine->execlists;
1196 if (reset_in_progress(execlists))
1197 return; /* defer until we restart the engine following reset */
1199 if (execlists->tasklet.func == execlists_submission_tasklet)
1200 __execlists_submission_tasklet(engine);
1202 tasklet_hi_schedule(&execlists->tasklet);
1205 static void submit_queue(struct intel_engine_cs *engine, int prio)
1207 if (prio > engine->execlists.queue_priority_hint) {
1208 engine->execlists.queue_priority_hint = prio;
1209 __submit_queue_imm(engine);
1213 static void execlists_submit_request(struct i915_request *request)
1215 struct intel_engine_cs *engine = request->engine;
1216 unsigned long flags;
1218 /* Will be called from irq-context when using foreign fences. */
1219 spin_lock_irqsave(&engine->timeline.lock, flags);
1221 queue_request(engine, &request->sched, rq_prio(request));
1223 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
1224 GEM_BUG_ON(list_empty(&request->sched.link));
1226 submit_queue(engine, rq_prio(request));
1228 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1231 static void __execlists_context_fini(struct intel_context *ce)
1233 intel_ring_put(ce->ring);
1235 GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj));
1236 i915_gem_object_put(ce->state->obj);
1239 static void execlists_context_destroy(struct kref *kref)
1241 struct intel_context *ce = container_of(kref, typeof(*ce), ref);
1243 GEM_BUG_ON(intel_context_is_pinned(ce));
1246 __execlists_context_fini(ce);
1248 intel_context_free(ce);
1251 static int __context_pin(struct i915_vma *vma)
1256 flags = PIN_GLOBAL | PIN_HIGH;
1257 flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
1259 err = i915_vma_pin(vma, 0, 0, flags);
1263 vma->obj->pin_global++;
1264 vma->obj->mm.dirty = true;
1269 static void __context_unpin(struct i915_vma *vma)
1271 vma->obj->pin_global--;
1272 __i915_vma_unpin(vma);
1275 static void execlists_context_unpin(struct intel_context *ce)
1277 struct intel_engine_cs *engine;
1280 * The tasklet may still be using a pointer to our state, via an
1281 * old request. However, since we know we only unpin the context
1282 * on retirement of the following request, we know that the last
1283 * request referencing us will have had a completion CS interrupt.
1284 * If we see that it is still active, it means that the tasklet hasn't
1285 * had the chance to run yet; let it run before we teardown the
1286 * reference it may use.
1288 engine = READ_ONCE(ce->active);
1289 if (unlikely(engine)) {
1290 unsigned long flags;
1292 spin_lock_irqsave(&engine->timeline.lock, flags);
1293 process_csb(engine);
1294 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1296 GEM_BUG_ON(READ_ONCE(ce->active));
1299 i915_gem_context_unpin_hw_id(ce->gem_context);
1301 intel_ring_unpin(ce->ring);
1303 i915_gem_object_unpin_map(ce->state->obj);
1304 __context_unpin(ce->state);
1308 __execlists_update_reg_state(struct intel_context *ce,
1309 struct intel_engine_cs *engine)
1311 struct intel_ring *ring = ce->ring;
1312 u32 *regs = ce->lrc_reg_state;
1314 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
1315 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
1317 regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(ring->vma);
1318 regs[CTX_RING_HEAD + 1] = ring->head;
1319 regs[CTX_RING_TAIL + 1] = ring->tail;
1322 if (engine->class == RENDER_CLASS)
1323 regs[CTX_R_PWR_CLK_STATE + 1] =
1324 gen8_make_rpcs(engine->i915, &ce->sseu);
1328 __execlists_context_pin(struct intel_context *ce,
1329 struct intel_engine_cs *engine)
1334 GEM_BUG_ON(!ce->gem_context->ppgtt);
1336 ret = execlists_context_deferred_alloc(ce, engine);
1339 GEM_BUG_ON(!ce->state);
1341 ret = __context_pin(ce->state);
1345 vaddr = i915_gem_object_pin_map(ce->state->obj,
1346 i915_coherent_map_type(engine->i915) |
1348 if (IS_ERR(vaddr)) {
1349 ret = PTR_ERR(vaddr);
1353 ret = intel_ring_pin(ce->ring);
1357 ret = i915_gem_context_pin_hw_id(ce->gem_context);
1361 ce->lrc_desc = lrc_descriptor(ce, engine);
1362 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
1363 __execlists_update_reg_state(ce, engine);
1368 intel_ring_unpin(ce->ring);
1370 i915_gem_object_unpin_map(ce->state->obj);
1372 __context_unpin(ce->state);
1377 static int execlists_context_pin(struct intel_context *ce)
1379 return __execlists_context_pin(ce, ce->engine);
1382 static const struct intel_context_ops execlists_context_ops = {
1383 .pin = execlists_context_pin,
1384 .unpin = execlists_context_unpin,
1385 .destroy = execlists_context_destroy,
1388 static int gen8_emit_init_breadcrumb(struct i915_request *rq)
1392 GEM_BUG_ON(!rq->timeline->has_initial_breadcrumb);
1394 cs = intel_ring_begin(rq, 6);
1399 * Check if we have been preempted before we even get started.
1401 * After this point i915_request_started() reports true, even if
1402 * we get preempted and so are no longer running.
1404 *cs++ = MI_ARB_CHECK;
1407 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
1408 *cs++ = rq->timeline->hwsp_offset;
1410 *cs++ = rq->fence.seqno - 1;
1412 intel_ring_advance(rq, cs);
1414 /* Record the updated position of the request's payload */
1415 rq->infix = intel_ring_offset(rq, cs);
1420 static int emit_pdps(struct i915_request *rq)
1422 const struct intel_engine_cs * const engine = rq->engine;
1423 struct i915_hw_ppgtt * const ppgtt = rq->gem_context->ppgtt;
1427 GEM_BUG_ON(intel_vgpu_active(rq->i915));
1430 * Beware ye of the dragons, this sequence is magic!
1432 * Small changes to this sequence can cause anything from
1433 * GPU hangs to forcewake errors and machine lockups!
1436 /* Flush any residual operations from the context load */
1437 err = engine->emit_flush(rq, EMIT_FLUSH);
1441 /* Magic required to prevent forcewake errors! */
1442 err = engine->emit_flush(rq, EMIT_INVALIDATE);
1446 cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2);
1450 /* Ensure the LRI have landed before we invalidate & continue */
1451 *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED;
1452 for (i = GEN8_3LVL_PDPES; i--; ) {
1453 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1455 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
1456 *cs++ = upper_32_bits(pd_daddr);
1457 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
1458 *cs++ = lower_32_bits(pd_daddr);
1462 intel_ring_advance(rq, cs);
1464 /* Be doubly sure the LRI have landed before proceeding */
1465 err = engine->emit_flush(rq, EMIT_FLUSH);
1469 /* Re-invalidate the TLB for luck */
1470 return engine->emit_flush(rq, EMIT_INVALIDATE);
1473 static int execlists_request_alloc(struct i915_request *request)
1477 GEM_BUG_ON(!intel_context_is_pinned(request->hw_context));
1480 * Flush enough space to reduce the likelihood of waiting after
1481 * we start building the request - in which case we will just
1482 * have to repeat work.
1484 request->reserved_space += EXECLISTS_REQUEST_SIZE;
1487 * Note that after this point, we have committed to using
1488 * this request as it is being used to both track the
1489 * state of engine initialisation and liveness of the
1490 * golden renderstate above. Think twice before you try
1491 * to cancel/unwind this request now.
1494 /* Unconditionally invalidate GPU caches and TLBs. */
1495 if (i915_vm_is_4lvl(&request->gem_context->ppgtt->vm))
1496 ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
1498 ret = emit_pdps(request);
1502 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
1507 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1508 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1509 * but there is a slight complication as this is applied in WA batch where the
1510 * values are only initialized once so we cannot take register value at the
1511 * beginning and reuse it further; hence we save its value to memory, upload a
1512 * constant value with bit21 set and then we restore it back with the saved value.
1513 * To simplify the WA, a constant value is formed by using the default value
1514 * of this register. This shouldn't be a problem because we are only modifying
1515 * it for a short period and this batch in non-premptible. We can ofcourse
1516 * use additional instructions that read the actual value of the register
1517 * at that time and set our bit of interest but it makes the WA complicated.
1519 * This WA is also required for Gen9 so extracting as a function avoids
1523 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
1525 /* NB no one else is allowed to scribble over scratch + 256! */
1526 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1527 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1528 *batch++ = i915_scratch_offset(engine->i915) + 256;
1531 *batch++ = MI_LOAD_REGISTER_IMM(1);
1532 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1533 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
1535 batch = gen8_emit_pipe_control(batch,
1536 PIPE_CONTROL_CS_STALL |
1537 PIPE_CONTROL_DC_FLUSH_ENABLE,
1540 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1541 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1542 *batch++ = i915_scratch_offset(engine->i915) + 256;
1549 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1550 * initialized at the beginning and shared across all contexts but this field
1551 * helps us to have multiple batches at different offsets and select them based
1552 * on a criteria. At the moment this batch always start at the beginning of the page
1553 * and at this point we don't have multiple wa_ctx batch buffers.
1555 * The number of WA applied are not known at the beginning; we use this field
1556 * to return the no of DWORDS written.
1558 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1559 * so it adds NOOPs as padding to make it cacheline aligned.
1560 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1561 * makes a complete batch buffer.
1563 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1565 /* WaDisableCtxRestoreArbitration:bdw,chv */
1566 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1568 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1569 if (IS_BROADWELL(engine->i915))
1570 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1572 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1573 /* Actual scratch location is at 128 bytes offset */
1574 batch = gen8_emit_pipe_control(batch,
1575 PIPE_CONTROL_FLUSH_L3 |
1576 PIPE_CONTROL_GLOBAL_GTT_IVB |
1577 PIPE_CONTROL_CS_STALL |
1578 PIPE_CONTROL_QW_WRITE,
1579 i915_scratch_offset(engine->i915) +
1580 2 * CACHELINE_BYTES);
1582 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1584 /* Pad to end of cacheline */
1585 while ((unsigned long)batch % CACHELINE_BYTES)
1589 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1590 * execution depends on the length specified in terms of cache lines
1591 * in the register CTX_RCS_INDIRECT_CTX
1602 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count)
1604 GEM_BUG_ON(!count || count > 63);
1606 *batch++ = MI_LOAD_REGISTER_IMM(count);
1608 *batch++ = i915_mmio_reg_offset(lri->reg);
1609 *batch++ = lri->value;
1610 } while (lri++, --count);
1616 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1618 static const struct lri lri[] = {
1619 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1621 COMMON_SLICE_CHICKEN2,
1622 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE,
1629 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX,
1630 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX),
1636 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX,
1637 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX),
1641 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1643 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1644 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1646 batch = emit_lri(batch, lri, ARRAY_SIZE(lri));
1648 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1649 if (HAS_POOLED_EU(engine->i915)) {
1651 * EU pool configuration is setup along with golden context
1652 * during context initialization. This value depends on
1653 * device type (2x6 or 3x6) and needs to be updated based
1654 * on which subslice is disabled especially for 2x6
1655 * devices, however it is safe to load default
1656 * configuration of 3x6 device instead of masking off
1657 * corresponding bits because HW ignores bits of a disabled
1658 * subslice and drops down to appropriate config. Please
1659 * see render_state_setup() in i915_gem_render_state.c for
1660 * possible configurations, to avoid duplication they are
1661 * not shown here again.
1663 *batch++ = GEN9_MEDIA_POOL_STATE;
1664 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1665 *batch++ = 0x00777000;
1671 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1673 /* Pad to end of cacheline */
1674 while ((unsigned long)batch % CACHELINE_BYTES)
1681 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1686 * WaPipeControlBefore3DStateSamplePattern: cnl
1688 * Ensure the engine is idle prior to programming a
1689 * 3DSTATE_SAMPLE_PATTERN during a context restore.
1691 batch = gen8_emit_pipe_control(batch,
1692 PIPE_CONTROL_CS_STALL,
1695 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for
1696 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in
1697 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is
1698 * confusing. Since gen8_emit_pipe_control() already advances the
1699 * batch by 6 dwords, we advance the other 10 here, completing a
1700 * cacheline. It's not clear if the workaround requires this padding
1701 * before other commands, or if it's just the regular padding we would
1702 * already have for the workaround bb, so leave it here for now.
1704 for (i = 0; i < 10; i++)
1707 /* Pad to end of cacheline */
1708 while ((unsigned long)batch % CACHELINE_BYTES)
1714 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1716 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
1718 struct drm_i915_gem_object *obj;
1719 struct i915_vma *vma;
1722 obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE);
1724 return PTR_ERR(obj);
1726 vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
1732 err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
1736 engine->wa_ctx.vma = vma;
1740 i915_gem_object_put(obj);
1744 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
1746 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
1749 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1751 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1753 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1754 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
1756 wa_bb_func_t wa_bb_fn[2];
1758 void *batch, *batch_ptr;
1762 if (GEM_DEBUG_WARN_ON(engine->id != RCS0))
1765 switch (INTEL_GEN(engine->i915)) {
1769 wa_bb_fn[0] = gen10_init_indirectctx_bb;
1773 wa_bb_fn[0] = gen9_init_indirectctx_bb;
1777 wa_bb_fn[0] = gen8_init_indirectctx_bb;
1781 MISSING_CASE(INTEL_GEN(engine->i915));
1785 ret = lrc_setup_wa_ctx(engine);
1787 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1791 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1792 batch = batch_ptr = kmap_atomic(page);
1795 * Emit the two workaround batch buffers, recording the offset from the
1796 * start of the workaround batch buffer object for each and their
1799 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
1800 wa_bb[i]->offset = batch_ptr - batch;
1801 if (GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset,
1802 CACHELINE_BYTES))) {
1807 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
1808 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
1811 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
1813 kunmap_atomic(batch);
1815 lrc_destroy_wa_ctx(engine);
1820 static void enable_execlists(struct intel_engine_cs *engine)
1822 struct drm_i915_private *dev_priv = engine->i915;
1824 intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
1827 * Make sure we're not enabling the new 12-deep CSB
1828 * FIFO as that requires a slightly updated handling
1829 * in the ctx switch irq. Since we're currently only
1830 * using only 2 elements of the enhanced execlists the
1831 * deeper FIFO it's not needed and it's not worth adding
1832 * more statements to the irq handler to support it.
1834 if (INTEL_GEN(dev_priv) >= 11)
1835 I915_WRITE(RING_MODE_GEN7(engine),
1836 _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
1838 I915_WRITE(RING_MODE_GEN7(engine),
1839 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1841 I915_WRITE(RING_MI_MODE(engine->mmio_base),
1842 _MASKED_BIT_DISABLE(STOP_RING));
1844 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1845 i915_ggtt_offset(engine->status_page.vma));
1846 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1849 static bool unexpected_starting_state(struct intel_engine_cs *engine)
1851 struct drm_i915_private *dev_priv = engine->i915;
1852 bool unexpected = false;
1854 if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) {
1855 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
1862 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1864 intel_engine_apply_workarounds(engine);
1865 intel_engine_apply_whitelist(engine);
1867 intel_mocs_init_engine(engine);
1869 intel_engine_reset_breadcrumbs(engine);
1871 if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) {
1872 struct drm_printer p = drm_debug_printer(__func__);
1874 intel_engine_dump(engine, &p, NULL);
1877 enable_execlists(engine);
1882 static void execlists_reset_prepare(struct intel_engine_cs *engine)
1884 struct intel_engine_execlists * const execlists = &engine->execlists;
1885 unsigned long flags;
1887 GEM_TRACE("%s: depth<-%d\n", engine->name,
1888 atomic_read(&execlists->tasklet.count));
1891 * Prevent request submission to the hardware until we have
1892 * completed the reset in i915_gem_reset_finish(). If a request
1893 * is completed by one engine, it may then queue a request
1894 * to a second via its execlists->tasklet *just* as we are
1895 * calling engine->init_hw() and also writing the ELSP.
1896 * Turning off the execlists->tasklet until the reset is over
1897 * prevents the race.
1899 __tasklet_disable_sync_once(&execlists->tasklet);
1900 GEM_BUG_ON(!reset_in_progress(execlists));
1902 intel_engine_stop_cs(engine);
1904 /* And flush any current direct submission. */
1905 spin_lock_irqsave(&engine->timeline.lock, flags);
1906 process_csb(engine); /* drain preemption events */
1907 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1910 static bool lrc_regs_ok(const struct i915_request *rq)
1912 const struct intel_ring *ring = rq->ring;
1913 const u32 *regs = rq->hw_context->lrc_reg_state;
1915 /* Quick spot check for the common signs of context corruption */
1917 if (regs[CTX_RING_BUFFER_CONTROL + 1] !=
1918 (RING_CTL_SIZE(ring->size) | RING_VALID))
1921 if (regs[CTX_RING_BUFFER_START + 1] != i915_ggtt_offset(ring->vma))
1927 static void execlists_reset(struct intel_engine_cs *engine, bool stalled)
1929 struct intel_engine_execlists * const execlists = &engine->execlists;
1930 struct i915_request *rq;
1931 unsigned long flags;
1934 spin_lock_irqsave(&engine->timeline.lock, flags);
1937 * Catch up with any missed context-switch interrupts.
1939 * Ideally we would just read the remaining CSB entries now that we
1940 * know the gpu is idle. However, the CSB registers are sometimes^W
1941 * often trashed across a GPU reset! Instead we have to rely on
1942 * guessing the missed context-switch events by looking at what
1943 * requests were completed.
1945 execlists_cancel_port_requests(execlists);
1947 /* Push back any incomplete requests for replay after the reset. */
1948 rq = __unwind_incomplete_requests(engine);
1950 /* Following the reset, we need to reload the CSB read/write pointers */
1951 reset_csb_pointers(&engine->execlists);
1957 * If this request hasn't started yet, e.g. it is waiting on a
1958 * semaphore, we need to avoid skipping the request or else we
1959 * break the signaling chain. However, if the context is corrupt
1960 * the request will not restart and we will be stuck with a wedged
1961 * device. It is quite often the case that if we issue a reset
1962 * while the GPU is loading the context image, that the context
1963 * image becomes corrupt.
1965 * Otherwise, if we have not started yet, the request should replay
1966 * perfectly and we do not need to flag the result as being erroneous.
1968 if (!i915_request_started(rq) && lrc_regs_ok(rq))
1972 * If the request was innocent, we leave the request in the ELSP
1973 * and will try to replay it on restarting. The context image may
1974 * have been corrupted by the reset, in which case we may have
1975 * to service a new GPU hang, but more likely we can continue on
1978 * If the request was guilty, we presume the context is corrupt
1979 * and have to at least restore the RING register in the context
1980 * image back to the expected values to skip over the guilty request.
1982 i915_reset_request(rq, stalled);
1983 if (!stalled && lrc_regs_ok(rq))
1987 * We want a simple context + ring to execute the breadcrumb update.
1988 * We cannot rely on the context being intact across the GPU hang,
1989 * so clear it and rebuild just what we need for the breadcrumb.
1990 * All pending requests for this context will be zapped, and any
1991 * future request will be after userspace has had the opportunity
1992 * to recreate its own state.
1994 regs = rq->hw_context->lrc_reg_state;
1995 if (engine->pinned_default_state) {
1996 memcpy(regs, /* skip restoring the vanilla PPHWSP */
1997 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
1998 engine->context_size - PAGE_SIZE);
2001 /* Rerun the request; its payload has been neutered (if guilty). */
2002 rq->ring->head = intel_ring_wrap(rq->ring, rq->head);
2003 intel_ring_update_space(rq->ring);
2005 execlists_init_reg_state(regs, rq->hw_context, engine, rq->ring);
2006 __execlists_update_reg_state(rq->hw_context, engine);
2009 spin_unlock_irqrestore(&engine->timeline.lock, flags);
2012 static void execlists_reset_finish(struct intel_engine_cs *engine)
2014 struct intel_engine_execlists * const execlists = &engine->execlists;
2017 * After a GPU reset, we may have requests to replay. Do so now while
2018 * we still have the forcewake to be sure that the GPU is not allowed
2019 * to sleep before we restart and reload a context.
2021 GEM_BUG_ON(!reset_in_progress(execlists));
2022 if (!RB_EMPTY_ROOT(&execlists->queue.rb_root))
2023 execlists->tasklet.func(execlists->tasklet.data);
2025 if (__tasklet_enable(&execlists->tasklet))
2026 /* And kick in case we missed a new request submission. */
2027 tasklet_hi_schedule(&execlists->tasklet);
2028 GEM_TRACE("%s: depth->%d\n", engine->name,
2029 atomic_read(&execlists->tasklet.count));
2032 static int gen8_emit_bb_start(struct i915_request *rq,
2033 u64 offset, u32 len,
2034 const unsigned int flags)
2038 cs = intel_ring_begin(rq, 6);
2043 * WaDisableCtxRestoreArbitration:bdw,chv
2045 * We don't need to perform MI_ARB_ENABLE as often as we do (in
2046 * particular all the gen that do not need the w/a at all!), if we
2047 * took care to make sure that on every switch into this context
2048 * (both ordinary and for preemption) that arbitrartion was enabled
2049 * we would be fine. However, there doesn't seem to be a downside to
2050 * being paranoid and making sure it is set before each batch and
2051 * every context-switch.
2053 * Note that if we fail to enable arbitration before the request
2054 * is complete, then we do not see the context-switch interrupt and
2055 * the engine hangs (with RING_HEAD == RING_TAIL).
2057 * That satisfies both the GPGPU w/a and our heavy-handed paranoia.
2059 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2061 /* FIXME(BDW): Address space and security selectors. */
2062 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
2063 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8));
2064 *cs++ = lower_32_bits(offset);
2065 *cs++ = upper_32_bits(offset);
2067 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
2070 intel_ring_advance(rq, cs);
2075 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
2077 struct drm_i915_private *dev_priv = engine->i915;
2078 I915_WRITE_IMR(engine,
2079 ~(engine->irq_enable_mask | engine->irq_keep_mask));
2080 POSTING_READ_FW(RING_IMR(engine->mmio_base));
2083 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
2085 struct drm_i915_private *dev_priv = engine->i915;
2086 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
2089 static int gen8_emit_flush(struct i915_request *request, u32 mode)
2093 cs = intel_ring_begin(request, 4);
2097 cmd = MI_FLUSH_DW + 1;
2099 /* We always require a command barrier so that subsequent
2100 * commands, such as breadcrumb interrupts, are strictly ordered
2101 * wrt the contents of the write cache being flushed to memory
2102 * (and thus being coherent from the CPU).
2104 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2106 if (mode & EMIT_INVALIDATE) {
2107 cmd |= MI_INVALIDATE_TLB;
2108 if (request->engine->class == VIDEO_DECODE_CLASS)
2109 cmd |= MI_INVALIDATE_BSD;
2113 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
2114 *cs++ = 0; /* upper addr */
2115 *cs++ = 0; /* value */
2116 intel_ring_advance(request, cs);
2121 static int gen8_emit_flush_render(struct i915_request *request,
2124 struct intel_engine_cs *engine = request->engine;
2126 i915_scratch_offset(engine->i915) + 2 * CACHELINE_BYTES;
2127 bool vf_flush_wa = false, dc_flush_wa = false;
2131 flags |= PIPE_CONTROL_CS_STALL;
2133 if (mode & EMIT_FLUSH) {
2134 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
2135 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
2136 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
2137 flags |= PIPE_CONTROL_FLUSH_ENABLE;
2140 if (mode & EMIT_INVALIDATE) {
2141 flags |= PIPE_CONTROL_TLB_INVALIDATE;
2142 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
2143 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
2144 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
2145 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
2146 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
2147 flags |= PIPE_CONTROL_QW_WRITE;
2148 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
2151 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
2154 if (IS_GEN(request->i915, 9))
2157 /* WaForGAMHang:kbl */
2158 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
2170 cs = intel_ring_begin(request, len);
2175 cs = gen8_emit_pipe_control(cs, 0, 0);
2178 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
2181 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
2184 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
2186 intel_ring_advance(request, cs);
2192 * Reserve space for 2 NOOPs at the end of each request to be
2193 * used as a workaround for not being allowed to do lite
2194 * restore with HEAD==TAIL (WaIdleLiteRestore).
2196 static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs)
2198 /* Ensure there's always at least one preemption point per-request. */
2199 *cs++ = MI_ARB_CHECK;
2201 request->wa_tail = intel_ring_offset(request, cs);
2206 static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
2208 cs = gen8_emit_ggtt_write(cs,
2209 request->fence.seqno,
2210 request->timeline->hwsp_offset,
2213 cs = gen8_emit_ggtt_write(cs,
2214 intel_engine_next_hangcheck_seqno(request->engine),
2215 I915_GEM_HWS_HANGCHECK_ADDR,
2216 MI_FLUSH_DW_STORE_INDEX);
2219 *cs++ = MI_USER_INTERRUPT;
2220 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2222 request->tail = intel_ring_offset(request, cs);
2223 assert_ring_tail_valid(request->ring, request->tail);
2225 return gen8_emit_wa_tail(request, cs);
2228 static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
2230 cs = gen8_emit_ggtt_write_rcs(cs,
2231 request->fence.seqno,
2232 request->timeline->hwsp_offset,
2233 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
2234 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
2235 PIPE_CONTROL_DC_FLUSH_ENABLE |
2236 PIPE_CONTROL_FLUSH_ENABLE |
2237 PIPE_CONTROL_CS_STALL);
2239 cs = gen8_emit_ggtt_write_rcs(cs,
2240 intel_engine_next_hangcheck_seqno(request->engine),
2241 I915_GEM_HWS_HANGCHECK_ADDR,
2242 PIPE_CONTROL_STORE_DATA_INDEX);
2244 *cs++ = MI_USER_INTERRUPT;
2245 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2247 request->tail = intel_ring_offset(request, cs);
2248 assert_ring_tail_valid(request->ring, request->tail);
2250 return gen8_emit_wa_tail(request, cs);
2253 static int gen8_init_rcs_context(struct i915_request *rq)
2257 ret = intel_engine_emit_ctx_wa(rq);
2261 ret = intel_rcs_context_init_mocs(rq);
2263 * Failing to program the MOCS is non-fatal.The system will not
2264 * run at peak performance. So generate an error and carry on.
2267 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
2269 return i915_gem_render_state_emit(rq);
2273 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
2274 * @engine: Engine Command Streamer.
2276 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
2278 struct drm_i915_private *dev_priv;
2281 * Tasklet cannot be active at this point due intel_mark_active/idle
2282 * so this is just for documentation.
2284 if (WARN_ON(test_bit(TASKLET_STATE_SCHED,
2285 &engine->execlists.tasklet.state)))
2286 tasklet_kill(&engine->execlists.tasklet);
2288 dev_priv = engine->i915;
2290 if (engine->buffer) {
2291 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
2294 if (engine->cleanup)
2295 engine->cleanup(engine);
2297 intel_engine_cleanup_common(engine);
2299 lrc_destroy_wa_ctx(engine);
2301 engine->i915 = NULL;
2302 dev_priv->engine[engine->id] = NULL;
2306 void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
2308 engine->submit_request = execlists_submit_request;
2309 engine->cancel_requests = execlists_cancel_requests;
2310 engine->schedule = i915_schedule;
2311 engine->execlists.tasklet.func = execlists_submission_tasklet;
2313 engine->reset.prepare = execlists_reset_prepare;
2315 engine->park = NULL;
2316 engine->unpark = NULL;
2318 engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
2319 engine->flags |= I915_ENGINE_SUPPORTS_STATS;
2320 if (engine->preempt_context)
2321 engine->flags |= I915_ENGINE_HAS_PREEMPTION;
2325 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
2327 /* Default vfuncs which can be overriden by each engine. */
2328 engine->init_hw = gen8_init_common_ring;
2330 engine->reset.prepare = execlists_reset_prepare;
2331 engine->reset.reset = execlists_reset;
2332 engine->reset.finish = execlists_reset_finish;
2334 engine->cops = &execlists_context_ops;
2335 engine->request_alloc = execlists_request_alloc;
2337 engine->emit_flush = gen8_emit_flush;
2338 engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
2339 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb;
2341 engine->set_default_submission = intel_execlists_set_default_submission;
2343 if (INTEL_GEN(engine->i915) < 11) {
2344 engine->irq_enable = gen8_logical_ring_enable_irq;
2345 engine->irq_disable = gen8_logical_ring_disable_irq;
2348 * TODO: On Gen11 interrupt masks need to be clear
2349 * to allow C6 entry. Keep interrupts enabled at
2350 * and take the hit of generating extra interrupts
2351 * until a more refined solution exists.
2354 engine->emit_bb_start = gen8_emit_bb_start;
2358 logical_ring_default_irqs(struct intel_engine_cs *engine)
2360 unsigned int shift = 0;
2362 if (INTEL_GEN(engine->i915) < 11) {
2363 const u8 irq_shifts[] = {
2364 [RCS0] = GEN8_RCS_IRQ_SHIFT,
2365 [BCS0] = GEN8_BCS_IRQ_SHIFT,
2366 [VCS0] = GEN8_VCS0_IRQ_SHIFT,
2367 [VCS1] = GEN8_VCS1_IRQ_SHIFT,
2368 [VECS0] = GEN8_VECS_IRQ_SHIFT,
2371 shift = irq_shifts[engine->id];
2374 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
2375 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
2379 logical_ring_setup(struct intel_engine_cs *engine)
2383 err = intel_engine_setup_common(engine);
2387 /* Intentionally left blank. */
2388 engine->buffer = NULL;
2390 tasklet_init(&engine->execlists.tasklet,
2391 execlists_submission_tasklet, (unsigned long)engine);
2393 logical_ring_default_vfuncs(engine);
2394 logical_ring_default_irqs(engine);
2399 static int logical_ring_init(struct intel_engine_cs *engine)
2401 struct drm_i915_private *i915 = engine->i915;
2402 struct intel_engine_execlists * const execlists = &engine->execlists;
2405 ret = intel_engine_init_common(engine);
2409 intel_engine_init_workarounds(engine);
2411 if (HAS_LOGICAL_RING_ELSQ(i915)) {
2412 execlists->submit_reg = i915->uncore.regs +
2413 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine));
2414 execlists->ctrl_reg = i915->uncore.regs +
2415 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine));
2417 execlists->submit_reg = i915->uncore.regs +
2418 i915_mmio_reg_offset(RING_ELSP(engine));
2421 execlists->preempt_complete_status = ~0u;
2422 if (engine->preempt_context)
2423 execlists->preempt_complete_status =
2424 upper_32_bits(engine->preempt_context->lrc_desc);
2426 execlists->csb_status =
2427 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
2429 execlists->csb_write =
2430 &engine->status_page.addr[intel_hws_csb_write_index(i915)];
2432 reset_csb_pointers(execlists);
2437 int logical_render_ring_init(struct intel_engine_cs *engine)
2441 ret = logical_ring_setup(engine);
2445 /* Override some for render ring. */
2446 engine->init_context = gen8_init_rcs_context;
2447 engine->emit_flush = gen8_emit_flush_render;
2448 engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
2450 ret = logical_ring_init(engine);
2454 ret = intel_init_workaround_bb(engine);
2457 * We continue even if we fail to initialize WA batch
2458 * because we only expect rare glitches but nothing
2459 * critical to prevent us from using GPU
2461 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2465 intel_engine_init_whitelist(engine);
2470 int logical_xcs_ring_init(struct intel_engine_cs *engine)
2474 err = logical_ring_setup(engine);
2478 return logical_ring_init(engine);
2481 u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *req_sseu)
2483 const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
2484 bool subslice_pg = sseu->has_subslice_pg;
2485 struct intel_sseu ctx_sseu;
2486 u8 slices, subslices;
2490 * No explicit RPCS request is needed to ensure full
2491 * slice/subslice/EU enablement prior to Gen9.
2493 if (INTEL_GEN(i915) < 9)
2497 * If i915/perf is active, we want a stable powergating configuration
2500 * We could choose full enablement, but on ICL we know there are use
2501 * cases which disable slices for functional, apart for performance
2502 * reasons. So in this case we select a known stable subset.
2504 if (!i915->perf.oa.exclusive_stream) {
2505 ctx_sseu = *req_sseu;
2507 ctx_sseu = intel_device_default_sseu(i915);
2509 if (IS_GEN(i915, 11)) {
2511 * We only need subslice count so it doesn't matter
2512 * which ones we select - just turn off low bits in the
2513 * amount of half of all available subslices per slice.
2515 ctx_sseu.subslice_mask =
2516 ~(~0 << (hweight8(ctx_sseu.subslice_mask) / 2));
2517 ctx_sseu.slice_mask = 0x1;
2521 slices = hweight8(ctx_sseu.slice_mask);
2522 subslices = hweight8(ctx_sseu.subslice_mask);
2525 * Since the SScount bitfield in GEN8_R_PWR_CLK_STATE is only three bits
2526 * wide and Icelake has up to eight subslices, specfial programming is
2527 * needed in order to correctly enable all subslices.
2529 * According to documentation software must consider the configuration
2530 * as 2x4x8 and hardware will translate this to 1x8x8.
2532 * Furthemore, even though SScount is three bits, maximum documented
2533 * value for it is four. From this some rules/restrictions follow:
2536 * If enabled subslice count is greater than four, two whole slices must
2537 * be enabled instead.
2540 * When more than one slice is enabled, hardware ignores the subslice
2543 * From these restrictions it follows that it is not possible to enable
2544 * a count of subslices between the SScount maximum of four restriction,
2545 * and the maximum available number on a particular SKU. Either all
2546 * subslices are enabled, or a count between one and four on the first
2549 if (IS_GEN(i915, 11) &&
2551 subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
2552 GEM_BUG_ON(subslices & 1);
2554 subslice_pg = false;
2559 * Starting in Gen9, render power gating can leave
2560 * slice/subslice/EU in a partially enabled state. We
2561 * must make an explicit request through RPCS for full
2564 if (sseu->has_slice_pg) {
2565 u32 mask, val = slices;
2567 if (INTEL_GEN(i915) >= 11) {
2568 mask = GEN11_RPCS_S_CNT_MASK;
2569 val <<= GEN11_RPCS_S_CNT_SHIFT;
2571 mask = GEN8_RPCS_S_CNT_MASK;
2572 val <<= GEN8_RPCS_S_CNT_SHIFT;
2575 GEM_BUG_ON(val & ~mask);
2578 rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_S_CNT_ENABLE | val;
2582 u32 val = subslices;
2584 val <<= GEN8_RPCS_SS_CNT_SHIFT;
2586 GEM_BUG_ON(val & ~GEN8_RPCS_SS_CNT_MASK);
2587 val &= GEN8_RPCS_SS_CNT_MASK;
2589 rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val;
2592 if (sseu->has_eu_pg) {
2595 val = ctx_sseu.min_eus_per_subslice << GEN8_RPCS_EU_MIN_SHIFT;
2596 GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK);
2597 val &= GEN8_RPCS_EU_MIN_MASK;
2601 val = ctx_sseu.max_eus_per_subslice << GEN8_RPCS_EU_MAX_SHIFT;
2602 GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK);
2603 val &= GEN8_RPCS_EU_MAX_MASK;
2607 rpcs |= GEN8_RPCS_ENABLE;
2613 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2615 u32 indirect_ctx_offset;
2617 switch (INTEL_GEN(engine->i915)) {
2619 MISSING_CASE(INTEL_GEN(engine->i915));
2622 indirect_ctx_offset =
2623 GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2626 indirect_ctx_offset =
2627 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2630 indirect_ctx_offset =
2631 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2634 indirect_ctx_offset =
2635 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2639 return indirect_ctx_offset;
2642 static void execlists_init_reg_state(u32 *regs,
2643 struct intel_context *ce,
2644 struct intel_engine_cs *engine,
2645 struct intel_ring *ring)
2647 struct i915_hw_ppgtt *ppgtt = ce->gem_context->ppgtt;
2648 bool rcs = engine->class == RENDER_CLASS;
2649 u32 base = engine->mmio_base;
2651 /* A context is actually a big batch buffer with several
2652 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
2653 * values we are setting here are only for the first context restore:
2654 * on a subsequent save, the GPU will recreate this batchbuffer with new
2655 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
2656 * we are not initializing here).
2658 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
2659 MI_LRI_FORCE_POSTED;
2661 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
2662 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
2663 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));
2664 if (INTEL_GEN(engine->i915) < 11) {
2665 regs[CTX_CONTEXT_CONTROL + 1] |=
2666 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
2667 CTX_CTRL_RS_CTX_ENABLE);
2669 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
2670 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
2671 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
2672 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
2673 RING_CTL_SIZE(ring->size) | RING_VALID);
2674 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
2675 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
2676 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
2677 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
2678 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
2679 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
2681 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2683 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
2684 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
2685 RING_INDIRECT_CTX_OFFSET(base), 0);
2686 if (wa_ctx->indirect_ctx.size) {
2687 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2689 regs[CTX_RCS_INDIRECT_CTX + 1] =
2690 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
2691 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
2693 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
2694 intel_lr_indirect_ctx_offset(engine) << 6;
2697 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
2698 if (wa_ctx->per_ctx.size) {
2699 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2701 regs[CTX_BB_PER_CTX_PTR + 1] =
2702 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
2706 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2708 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
2709 /* PDP values well be assigned later if needed */
2710 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
2711 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
2712 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
2713 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
2714 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
2715 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
2716 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
2717 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
2719 if (i915_vm_is_4lvl(&ppgtt->vm)) {
2720 /* 64b PPGTT (48bit canonical)
2721 * PDP0_DESCRIPTOR contains the base address to PML4 and
2722 * other PDP Descriptors are ignored.
2724 ASSIGN_CTX_PML4(ppgtt, regs);
2726 ASSIGN_CTX_PDP(ppgtt, regs, 3);
2727 ASSIGN_CTX_PDP(ppgtt, regs, 2);
2728 ASSIGN_CTX_PDP(ppgtt, regs, 1);
2729 ASSIGN_CTX_PDP(ppgtt, regs, 0);
2733 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2734 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0);
2736 i915_oa_init_reg_state(engine, ce, regs);
2739 regs[CTX_END] = MI_BATCH_BUFFER_END;
2740 if (INTEL_GEN(engine->i915) >= 10)
2741 regs[CTX_END] |= BIT(0);
2745 populate_lr_context(struct intel_context *ce,
2746 struct drm_i915_gem_object *ctx_obj,
2747 struct intel_engine_cs *engine,
2748 struct intel_ring *ring)
2754 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
2755 if (IS_ERR(vaddr)) {
2756 ret = PTR_ERR(vaddr);
2757 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2761 if (engine->default_state) {
2763 * We only want to copy over the template context state;
2764 * skipping over the headers reserved for GuC communication,
2765 * leaving those as zero.
2767 const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE;
2770 defaults = i915_gem_object_pin_map(engine->default_state,
2772 if (IS_ERR(defaults)) {
2773 ret = PTR_ERR(defaults);
2777 memcpy(vaddr + start, defaults + start, engine->context_size);
2778 i915_gem_object_unpin_map(engine->default_state);
2781 /* The second page of the context object contains some fields which must
2782 * be set up prior to the first execution. */
2783 regs = vaddr + LRC_STATE_PN * PAGE_SIZE;
2784 execlists_init_reg_state(regs, ce, engine, ring);
2785 if (!engine->default_state)
2786 regs[CTX_CONTEXT_CONTROL + 1] |=
2787 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
2788 if (ce->gem_context == engine->i915->preempt_context &&
2789 INTEL_GEN(engine->i915) < 11)
2790 regs[CTX_CONTEXT_CONTROL + 1] |=
2791 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2792 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);
2796 __i915_gem_object_flush_map(ctx_obj,
2797 LRC_HEADER_PAGES * PAGE_SIZE,
2798 engine->context_size);
2799 i915_gem_object_unpin_map(ctx_obj);
2803 static struct i915_timeline *get_timeline(struct i915_gem_context *ctx)
2806 return i915_timeline_get(ctx->timeline);
2808 return i915_timeline_create(ctx->i915, NULL);
2811 static int execlists_context_deferred_alloc(struct intel_context *ce,
2812 struct intel_engine_cs *engine)
2814 struct drm_i915_gem_object *ctx_obj;
2815 struct i915_vma *vma;
2817 struct intel_ring *ring;
2818 struct i915_timeline *timeline;
2824 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
2827 * Before the actual start of the context image, we insert a few pages
2828 * for our own use and for sharing with the GuC.
2830 context_size += LRC_HEADER_PAGES * PAGE_SIZE;
2832 ctx_obj = i915_gem_object_create(engine->i915, context_size);
2833 if (IS_ERR(ctx_obj))
2834 return PTR_ERR(ctx_obj);
2836 vma = i915_vma_instance(ctx_obj, &engine->i915->ggtt.vm, NULL);
2839 goto error_deref_obj;
2842 timeline = get_timeline(ce->gem_context);
2843 if (IS_ERR(timeline)) {
2844 ret = PTR_ERR(timeline);
2845 goto error_deref_obj;
2848 ring = intel_engine_create_ring(engine,
2850 ce->gem_context->ring_size);
2851 i915_timeline_put(timeline);
2853 ret = PTR_ERR(ring);
2854 goto error_deref_obj;
2857 ret = populate_lr_context(ce, ctx_obj, engine, ring);
2859 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2860 goto error_ring_free;
2869 intel_ring_put(ring);
2871 i915_gem_object_put(ctx_obj);
2875 void intel_lr_context_resume(struct drm_i915_private *i915)
2877 struct i915_gem_context *ctx;
2878 struct intel_context *ce;
2881 * Because we emit WA_TAIL_DWORDS there may be a disparity
2882 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2883 * that stored in context. As we only write new commands from
2884 * ce->ring->tail onwards, everything before that is junk. If the GPU
2885 * starts reading from its RING_HEAD from the context, it may try to
2886 * execute that junk and die.
2888 * So to avoid that we reset the context images upon resume. For
2889 * simplicity, we just zero everything out.
2891 list_for_each_entry(ctx, &i915->contexts.list, link) {
2892 list_for_each_entry(ce, &ctx->active_engines, active_link) {
2893 GEM_BUG_ON(!ce->ring);
2894 intel_ring_reset(ce->ring, 0);
2895 __execlists_update_reg_state(ce, ce->engine);
2900 void intel_execlists_show_requests(struct intel_engine_cs *engine,
2901 struct drm_printer *m,
2902 void (*show_request)(struct drm_printer *m,
2903 struct i915_request *rq,
2904 const char *prefix),
2907 const struct intel_engine_execlists *execlists = &engine->execlists;
2908 struct i915_request *rq, *last;
2909 unsigned long flags;
2913 spin_lock_irqsave(&engine->timeline.lock, flags);
2917 list_for_each_entry(rq, &engine->timeline.requests, link) {
2918 if (count++ < max - 1)
2919 show_request(m, rq, "\t\tE ");
2926 "\t\t...skipping %d executing requests...\n",
2929 show_request(m, last, "\t\tE ");
2934 if (execlists->queue_priority_hint != INT_MIN)
2935 drm_printf(m, "\t\tQueue priority hint: %d\n",
2936 execlists->queue_priority_hint);
2937 for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) {
2938 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
2941 priolist_for_each_request(rq, p, i) {
2942 if (count++ < max - 1)
2943 show_request(m, rq, "\t\tQ ");
2951 "\t\t...skipping %d queued requests...\n",
2954 show_request(m, last, "\t\tQ ");
2957 spin_unlock_irqrestore(&engine->timeline.lock, flags);
2960 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2961 #include "selftests/intel_lrc.c"