2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31 #include <linux/export.h>
33 #include "intel_drv.h"
34 #include <drm/i915_drm.h>
47 static const struct gmbus_port gmbus_ports[] = {
56 /* Intel GPIO access functions */
58 #define I2C_RISEFALL_TIME 10
60 static inline struct intel_gmbus *
61 to_intel_gmbus(struct i2c_adapter *i2c)
63 return container_of(i2c, struct intel_gmbus, adapter);
66 static int get_disp_clk_div(struct drm_i915_private *dev_priv,
72 reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO);
76 ((reg_val & CDCLK_FREQ_MASK) >> CDCLK_FREQ_SHIFT) + 1;
78 clk_ratio = (reg_val & CZCLK_FREQ_MASK) + 1;
83 static void gmbus_set_freq(struct drm_i915_private *dev_priv)
85 int vco, gmbus_freq = 0, cdclk_div;
87 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
89 vco = valleyview_get_vco(dev_priv);
91 /* Get the CDCLK divide ratio */
92 cdclk_div = get_disp_clk_div(dev_priv, CDCLK);
95 * Program the gmbus_freq based on the cdclk frequency.
96 * BSpec erroneously claims we should aim for 4MHz, but
97 * in fact 1MHz is the correct frequency.
100 gmbus_freq = (vco << 1) / cdclk_div;
102 if (WARN_ON(gmbus_freq == 0))
105 I915_WRITE(GMBUSFREQ_VLV, gmbus_freq);
109 intel_i2c_reset(struct drm_device *dev)
111 struct drm_i915_private *dev_priv = dev->dev_private;
114 * In BIOS-less system, program the correct gmbus frequency
115 * before reading edid.
117 if (IS_VALLEYVIEW(dev))
118 gmbus_set_freq(dev_priv);
120 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
121 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
124 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
128 /* When using bit bashing for I2C, this bit needs to be set to 1 */
129 if (!IS_PINEVIEW(dev_priv->dev))
132 val = I915_READ(DSPCLK_GATE_D);
134 val |= DPCUNIT_CLOCK_GATE_DISABLE;
136 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
137 I915_WRITE(DSPCLK_GATE_D, val);
140 static u32 get_reserved(struct intel_gmbus *bus)
142 struct drm_i915_private *dev_priv = bus->dev_priv;
143 struct drm_device *dev = dev_priv->dev;
146 /* On most chips, these bits must be preserved in software. */
147 if (!IS_I830(dev) && !IS_845G(dev))
148 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
149 (GPIO_DATA_PULLUP_DISABLE |
150 GPIO_CLOCK_PULLUP_DISABLE);
155 static int get_clock(void *data)
157 struct intel_gmbus *bus = data;
158 struct drm_i915_private *dev_priv = bus->dev_priv;
159 u32 reserved = get_reserved(bus);
160 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
161 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
162 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
165 static int get_data(void *data)
167 struct intel_gmbus *bus = data;
168 struct drm_i915_private *dev_priv = bus->dev_priv;
169 u32 reserved = get_reserved(bus);
170 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
171 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
172 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
175 static void set_clock(void *data, int state_high)
177 struct intel_gmbus *bus = data;
178 struct drm_i915_private *dev_priv = bus->dev_priv;
179 u32 reserved = get_reserved(bus);
183 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
185 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
188 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
189 POSTING_READ(bus->gpio_reg);
192 static void set_data(void *data, int state_high)
194 struct intel_gmbus *bus = data;
195 struct drm_i915_private *dev_priv = bus->dev_priv;
196 u32 reserved = get_reserved(bus);
200 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
202 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
205 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
206 POSTING_READ(bus->gpio_reg);
210 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
212 struct intel_gmbus *bus = container_of(adapter,
215 struct drm_i915_private *dev_priv = bus->dev_priv;
217 intel_i2c_reset(dev_priv->dev);
218 intel_i2c_quirk_set(dev_priv, true);
221 udelay(I2C_RISEFALL_TIME);
226 intel_gpio_post_xfer(struct i2c_adapter *adapter)
228 struct intel_gmbus *bus = container_of(adapter,
231 struct drm_i915_private *dev_priv = bus->dev_priv;
235 intel_i2c_quirk_set(dev_priv, false);
239 intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
241 struct drm_i915_private *dev_priv = bus->dev_priv;
242 struct i2c_algo_bit_data *algo;
244 algo = &bus->bit_algo;
246 /* -1 to map pin pair to gmbus index */
247 bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
249 bus->adapter.algo_data = algo;
250 algo->setsda = set_data;
251 algo->setscl = set_clock;
252 algo->getsda = get_data;
253 algo->getscl = get_clock;
254 algo->pre_xfer = intel_gpio_pre_xfer;
255 algo->post_xfer = intel_gpio_post_xfer;
256 algo->udelay = I2C_RISEFALL_TIME;
257 algo->timeout = usecs_to_jiffies(2200);
262 * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI
263 * mode. This results in spurious interrupt warnings if the legacy irq no. is
264 * shared with another device. The kernel then disables that interrupt source
265 * and so prevents the other device from working properly.
267 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
269 gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
274 int reg_offset = dev_priv->gpio_mmio_base;
278 if (!HAS_GMBUS_IRQ(dev_priv->dev))
281 /* Important: The hw handles only the first bit, so set only one! Since
282 * we also need to check for NAKs besides the hw ready/idle signal, we
283 * need to wake up periodically and check that ourselves. */
284 I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
286 for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
287 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
288 TASK_UNINTERRUPTIBLE);
290 gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
291 if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
296 finish_wait(&dev_priv->gmbus_wait_queue, &wait);
298 I915_WRITE(GMBUS4 + reg_offset, 0);
300 if (gmbus2 & GMBUS_SATOER)
302 if (gmbus2 & gmbus2_status)
308 gmbus_wait_idle(struct drm_i915_private *dev_priv)
311 int reg_offset = dev_priv->gpio_mmio_base;
313 #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
315 if (!HAS_GMBUS_IRQ(dev_priv->dev))
316 return wait_for(C, 10);
318 /* Important: The hw handles only the first bit, so set only one! */
319 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
321 ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
322 msecs_to_jiffies_timeout(10));
324 I915_WRITE(GMBUS4 + reg_offset, 0);
334 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
337 int reg_offset = dev_priv->gpio_mmio_base;
341 I915_WRITE(GMBUS1 + reg_offset,
344 (len << GMBUS_BYTE_COUNT_SHIFT) |
345 (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
346 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
351 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
356 val = I915_READ(GMBUS3 + reg_offset);
360 } while (--len && ++loop < 4);
367 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
369 int reg_offset = dev_priv->gpio_mmio_base;
375 while (len && loop < 4) {
376 val |= *buf++ << (8 * loop++);
380 I915_WRITE(GMBUS3 + reg_offset, val);
381 I915_WRITE(GMBUS1 + reg_offset,
383 (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
384 (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
385 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
391 val |= *buf++ << (8 * loop);
392 } while (--len && ++loop < 4);
394 I915_WRITE(GMBUS3 + reg_offset, val);
396 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
405 * The gmbus controller can combine a 1 or 2 byte write with a read that
406 * immediately follows it by using an "INDEX" cycle.
409 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
411 return (i + 1 < num &&
412 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
413 (msgs[i + 1].flags & I2C_M_RD));
417 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
419 int reg_offset = dev_priv->gpio_mmio_base;
420 u32 gmbus1_index = 0;
424 if (msgs[0].len == 2)
425 gmbus5 = GMBUS_2BYTE_INDEX_EN |
426 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
427 if (msgs[0].len == 1)
428 gmbus1_index = GMBUS_CYCLE_INDEX |
429 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
431 /* GMBUS5 holds 16-bit index */
433 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
435 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
437 /* Clear GMBUS5 after each index transfer */
439 I915_WRITE(GMBUS5 + reg_offset, 0);
445 gmbus_xfer(struct i2c_adapter *adapter,
446 struct i2c_msg *msgs,
449 struct intel_gmbus *bus = container_of(adapter,
452 struct drm_i915_private *dev_priv = bus->dev_priv;
456 intel_aux_display_runtime_get(dev_priv);
457 mutex_lock(&dev_priv->gmbus_mutex);
459 if (bus->force_bit) {
460 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
464 reg_offset = dev_priv->gpio_mmio_base;
466 I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
468 for (i = 0; i < num; i++) {
469 if (gmbus_is_index_read(msgs, i, num)) {
470 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
471 i += 1; /* set i to the index of the read xfer */
472 } else if (msgs[i].flags & I2C_M_RD) {
473 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
475 ret = gmbus_xfer_write(dev_priv, &msgs[i]);
478 if (ret == -ETIMEDOUT)
483 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
491 /* Generate a STOP condition on the bus. Note that gmbus can't generata
492 * a STOP on the very first cycle. To simplify the code we
493 * unconditionally generate the STOP condition with an additional gmbus
495 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
497 /* Mark the GMBUS interface as disabled after waiting for idle.
498 * We will re-enable it at the start of the next xfer,
499 * till then let it sleep.
501 if (gmbus_wait_idle(dev_priv)) {
502 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
506 I915_WRITE(GMBUS0 + reg_offset, 0);
512 * Wait for bus to IDLE before clearing NAK.
513 * If we clear the NAK while bus is still active, then it will stay
514 * active and the next transaction may fail.
516 * If no ACK is received during the address phase of a transaction, the
517 * adapter must report -ENXIO. It is not clear what to return if no ACK
518 * is received at other times. But we have to be careful to not return
519 * spurious -ENXIO because that will prevent i2c and drm edid functions
520 * from retrying. So return -ENXIO only when gmbus properly quiescents -
521 * timing out seems to happen when there _is_ a ddc chip present, but
522 * it's slow responding and only answers on the 2nd retry.
525 if (gmbus_wait_idle(dev_priv)) {
526 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
531 /* Toggle the Software Clear Interrupt bit. This has the effect
532 * of resetting the GMBUS controller and so clearing the
533 * BUS_ERROR raised by the slave's NAK.
535 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
536 I915_WRITE(GMBUS1 + reg_offset, 0);
537 I915_WRITE(GMBUS0 + reg_offset, 0);
539 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
540 adapter->name, msgs[i].addr,
541 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
546 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
547 bus->adapter.name, bus->reg0 & 0xff);
548 I915_WRITE(GMBUS0 + reg_offset, 0);
550 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
552 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
555 mutex_unlock(&dev_priv->gmbus_mutex);
556 intel_aux_display_runtime_put(dev_priv);
560 static u32 gmbus_func(struct i2c_adapter *adapter)
562 return i2c_bit_algo.functionality(adapter) &
563 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
564 /* I2C_FUNC_10BIT_ADDR | */
565 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
566 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
569 static const struct i2c_algorithm gmbus_algorithm = {
570 .master_xfer = gmbus_xfer,
571 .functionality = gmbus_func
575 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
578 int intel_setup_gmbus(struct drm_device *dev)
580 struct drm_i915_private *dev_priv = dev->dev_private;
583 if (HAS_PCH_NOP(dev))
585 else if (HAS_PCH_SPLIT(dev))
586 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
587 else if (IS_VALLEYVIEW(dev))
588 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
590 dev_priv->gpio_mmio_base = 0;
592 mutex_init(&dev_priv->gmbus_mutex);
593 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
595 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
596 struct intel_gmbus *bus = &dev_priv->gmbus[i];
597 u32 port = i + 1; /* +1 to map gmbus index to pin pair */
599 bus->adapter.owner = THIS_MODULE;
600 bus->adapter.class = I2C_CLASS_DDC;
601 snprintf(bus->adapter.name,
602 sizeof(bus->adapter.name),
604 gmbus_ports[i].name);
606 bus->adapter.dev.parent = &dev->pdev->dev;
607 bus->dev_priv = dev_priv;
609 bus->adapter.algo = &gmbus_algorithm;
611 /* By default use a conservative clock rate */
612 bus->reg0 = port | GMBUS_RATE_100KHZ;
614 /* gmbus seems to be broken on i830 */
618 intel_gpio_setup(bus, port);
620 ret = i2c_add_adapter(&bus->adapter);
625 intel_i2c_reset(dev_priv->dev);
631 struct intel_gmbus *bus = &dev_priv->gmbus[i];
632 i2c_del_adapter(&bus->adapter);
637 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
640 WARN_ON(!intel_gmbus_is_port_valid(port));
641 /* -1 to map pin pair to gmbus index */
642 return (intel_gmbus_is_port_valid(port)) ?
643 &dev_priv->gmbus[port - 1].adapter : NULL;
646 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
648 struct intel_gmbus *bus = to_intel_gmbus(adapter);
650 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
653 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
655 struct intel_gmbus *bus = to_intel_gmbus(adapter);
657 bus->force_bit += force_bit ? 1 : -1;
658 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
659 force_bit ? "en" : "dis", adapter->name,
663 void intel_teardown_gmbus(struct drm_device *dev)
665 struct drm_i915_private *dev_priv = dev->dev_private;
668 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
669 struct intel_gmbus *bus = &dev_priv->gmbus[i];
670 i2c_del_adapter(&bus->adapter);