2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31 #include <linux/export.h>
32 #include <drm/drm_hdcp.h>
33 #include "intel_drv.h"
34 #include <drm/i915_drm.h>
42 /* Map gmbus pin pairs to names and registers. */
43 static const struct gmbus_pin gmbus_pins[] = {
44 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
45 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
46 [GMBUS_PIN_PANEL] = { "panel", GPIOC },
47 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
48 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
49 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
52 static const struct gmbus_pin gmbus_pins_bdw[] = {
53 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
54 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
55 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
56 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
59 static const struct gmbus_pin gmbus_pins_skl[] = {
60 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
61 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
62 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
65 static const struct gmbus_pin gmbus_pins_bxt[] = {
66 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
67 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
68 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
71 static const struct gmbus_pin gmbus_pins_cnp[] = {
72 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
73 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
74 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
75 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
78 static const struct gmbus_pin gmbus_pins_icp[] = {
79 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
80 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
81 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
82 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
83 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
84 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
87 /* pin is expected to be valid */
88 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
91 if (HAS_PCH_ICP(dev_priv))
92 return &gmbus_pins_icp[pin];
93 else if (HAS_PCH_CNP(dev_priv))
94 return &gmbus_pins_cnp[pin];
95 else if (IS_GEN9_LP(dev_priv))
96 return &gmbus_pins_bxt[pin];
97 else if (IS_GEN9_BC(dev_priv))
98 return &gmbus_pins_skl[pin];
99 else if (IS_BROADWELL(dev_priv))
100 return &gmbus_pins_bdw[pin];
102 return &gmbus_pins[pin];
105 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
110 if (HAS_PCH_ICP(dev_priv))
111 size = ARRAY_SIZE(gmbus_pins_icp);
112 else if (HAS_PCH_CNP(dev_priv))
113 size = ARRAY_SIZE(gmbus_pins_cnp);
114 else if (IS_GEN9_LP(dev_priv))
115 size = ARRAY_SIZE(gmbus_pins_bxt);
116 else if (IS_GEN9_BC(dev_priv))
117 size = ARRAY_SIZE(gmbus_pins_skl);
118 else if (IS_BROADWELL(dev_priv))
119 size = ARRAY_SIZE(gmbus_pins_bdw);
121 size = ARRAY_SIZE(gmbus_pins);
123 return pin < size && get_gmbus_pin(dev_priv, pin)->name;
126 /* Intel GPIO access functions */
128 #define I2C_RISEFALL_TIME 10
130 static inline struct intel_gmbus *
131 to_intel_gmbus(struct i2c_adapter *i2c)
133 return container_of(i2c, struct intel_gmbus, adapter);
137 intel_i2c_reset(struct drm_i915_private *dev_priv)
139 I915_WRITE(GMBUS0, 0);
140 I915_WRITE(GMBUS4, 0);
143 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
148 /* When using bit bashing for I2C, this bit needs to be set to 1 */
149 val = I915_READ(DSPCLK_GATE_D);
151 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
153 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
154 I915_WRITE(DSPCLK_GATE_D, val);
157 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
162 val = I915_READ(SOUTH_DSPCLK_GATE_D);
164 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
166 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
167 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
170 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
175 val = I915_READ(GEN9_CLKGATE_DIS_4);
177 val |= BXT_GMBUS_GATING_DIS;
179 val &= ~BXT_GMBUS_GATING_DIS;
180 I915_WRITE(GEN9_CLKGATE_DIS_4, val);
183 static u32 get_reserved(struct intel_gmbus *bus)
185 struct drm_i915_private *dev_priv = bus->dev_priv;
188 /* On most chips, these bits must be preserved in software. */
189 if (!IS_I830(dev_priv) && !IS_I845G(dev_priv))
190 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
191 (GPIO_DATA_PULLUP_DISABLE |
192 GPIO_CLOCK_PULLUP_DISABLE);
197 static int get_clock(void *data)
199 struct intel_gmbus *bus = data;
200 struct drm_i915_private *dev_priv = bus->dev_priv;
201 u32 reserved = get_reserved(bus);
202 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
203 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
204 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
207 static int get_data(void *data)
209 struct intel_gmbus *bus = data;
210 struct drm_i915_private *dev_priv = bus->dev_priv;
211 u32 reserved = get_reserved(bus);
212 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
213 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
214 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
217 static void set_clock(void *data, int state_high)
219 struct intel_gmbus *bus = data;
220 struct drm_i915_private *dev_priv = bus->dev_priv;
221 u32 reserved = get_reserved(bus);
225 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
227 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
230 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
231 POSTING_READ(bus->gpio_reg);
234 static void set_data(void *data, int state_high)
236 struct intel_gmbus *bus = data;
237 struct drm_i915_private *dev_priv = bus->dev_priv;
238 u32 reserved = get_reserved(bus);
242 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
244 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
247 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
248 POSTING_READ(bus->gpio_reg);
252 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
254 struct intel_gmbus *bus = container_of(adapter,
257 struct drm_i915_private *dev_priv = bus->dev_priv;
259 intel_i2c_reset(dev_priv);
261 if (IS_PINEVIEW(dev_priv))
262 pnv_gmbus_clock_gating(dev_priv, false);
266 udelay(I2C_RISEFALL_TIME);
271 intel_gpio_post_xfer(struct i2c_adapter *adapter)
273 struct intel_gmbus *bus = container_of(adapter,
276 struct drm_i915_private *dev_priv = bus->dev_priv;
281 if (IS_PINEVIEW(dev_priv))
282 pnv_gmbus_clock_gating(dev_priv, true);
286 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
288 struct drm_i915_private *dev_priv = bus->dev_priv;
289 struct i2c_algo_bit_data *algo;
291 algo = &bus->bit_algo;
293 bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
294 bus->adapter.algo_data = algo;
295 algo->setsda = set_data;
296 algo->setscl = set_clock;
297 algo->getsda = get_data;
298 algo->getscl = get_clock;
299 algo->pre_xfer = intel_gpio_pre_xfer;
300 algo->post_xfer = intel_gpio_post_xfer;
301 algo->udelay = I2C_RISEFALL_TIME;
302 algo->timeout = usecs_to_jiffies(2200);
306 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
312 /* Important: The hw handles only the first bit, so set only one! Since
313 * we also need to check for NAKs besides the hw ready/idle signal, we
314 * need to wake up periodically and check that ourselves.
316 if (!HAS_GMBUS_IRQ(dev_priv))
319 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
320 I915_WRITE_FW(GMBUS4, irq_en);
322 status |= GMBUS_SATOER;
323 ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2);
325 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50);
327 I915_WRITE_FW(GMBUS4, 0);
328 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
330 if (gmbus2 & GMBUS_SATOER)
337 gmbus_wait_idle(struct drm_i915_private *dev_priv)
343 /* Important: The hw handles only the first bit, so set only one! */
345 if (HAS_GMBUS_IRQ(dev_priv))
346 irq_enable = GMBUS_IDLE_EN;
348 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
349 I915_WRITE_FW(GMBUS4, irq_enable);
351 ret = intel_wait_for_register_fw(dev_priv,
352 GMBUS2, GMBUS_ACTIVE, 0,
355 I915_WRITE_FW(GMBUS4, 0);
356 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
362 unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
364 return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
365 GMBUS_BYTE_COUNT_MAX;
369 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
370 unsigned short addr, u8 *buf, unsigned int len,
371 u32 gmbus0_reg, u32 gmbus1_index)
373 unsigned int size = len;
374 bool burst_read = len > gmbus_max_xfer_size(dev_priv);
375 bool extra_byte_added = false;
379 * As per HW Spec, for 512Bytes need to read extra Byte and
380 * Ignore the extra byte read.
383 extra_byte_added = true;
386 size = len % 256 + 256;
387 I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
390 I915_WRITE_FW(GMBUS1,
393 (size << GMBUS_BYTE_COUNT_SHIFT) |
394 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
395 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
400 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
404 val = I915_READ_FW(GMBUS3);
406 if (extra_byte_added && len == 1)
411 } while (--len && ++loop < 4);
413 if (burst_read && len == size - 4)
414 /* Reset the override bit */
415 I915_WRITE_FW(GMBUS0, gmbus0_reg);
422 * HW spec says that 512Bytes in Burst read need special treatment.
423 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
424 * an I2C slave, which supports such a lengthy burst read too for experiments.
426 * So until things get clarified on HW support, to avoid the burst read length
427 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
429 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
432 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
433 u32 gmbus0_reg, u32 gmbus1_index)
436 unsigned int rx_size = msg->len;
441 if (HAS_GMBUS_BURST_READ(dev_priv))
442 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
444 len = min(rx_size, gmbus_max_xfer_size(dev_priv));
446 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
447 gmbus0_reg, gmbus1_index);
453 } while (rx_size != 0);
459 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
460 unsigned short addr, u8 *buf, unsigned int len,
463 unsigned int chunk_size = len;
467 while (len && loop < 4) {
468 val |= *buf++ << (8 * loop++);
472 I915_WRITE_FW(GMBUS3, val);
473 I915_WRITE_FW(GMBUS1,
474 gmbus1_index | GMBUS_CYCLE_WAIT |
475 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
476 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
477 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
483 val |= *buf++ << (8 * loop);
484 } while (--len && ++loop < 4);
486 I915_WRITE_FW(GMBUS3, val);
488 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
497 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
501 unsigned int tx_size = msg->len;
506 len = min(tx_size, gmbus_max_xfer_size(dev_priv));
508 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
515 } while (tx_size != 0);
521 * The gmbus controller can combine a 1 or 2 byte write with another read/write
522 * that immediately follows it by using an "INDEX" cycle.
525 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
527 return (i + 1 < num &&
528 msgs[i].addr == msgs[i + 1].addr &&
529 !(msgs[i].flags & I2C_M_RD) &&
530 (msgs[i].len == 1 || msgs[i].len == 2) &&
531 msgs[i + 1].len > 0);
535 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
538 u32 gmbus1_index = 0;
542 if (msgs[0].len == 2)
543 gmbus5 = GMBUS_2BYTE_INDEX_EN |
544 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
545 if (msgs[0].len == 1)
546 gmbus1_index = GMBUS_CYCLE_INDEX |
547 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
549 /* GMBUS5 holds 16-bit index */
551 I915_WRITE_FW(GMBUS5, gmbus5);
553 if (msgs[1].flags & I2C_M_RD)
554 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
557 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
559 /* Clear GMBUS5 after each index transfer */
561 I915_WRITE_FW(GMBUS5, 0);
567 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
570 struct intel_gmbus *bus = container_of(adapter,
573 struct drm_i915_private *dev_priv = bus->dev_priv;
574 int i = 0, inc, try = 0;
577 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
578 if (IS_GEN9_LP(dev_priv))
579 bxt_gmbus_clock_gating(dev_priv, false);
580 else if (HAS_PCH_SPT(dev_priv) ||
581 HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
582 pch_gmbus_clock_gating(dev_priv, false);
585 I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0);
587 for (; i < num; i += inc) {
589 if (gmbus_is_index_xfer(msgs, i, num)) {
590 ret = gmbus_index_xfer(dev_priv, &msgs[i],
591 gmbus0_source | bus->reg0);
592 inc = 2; /* an index transmission is two msgs */
593 } else if (msgs[i].flags & I2C_M_RD) {
594 ret = gmbus_xfer_read(dev_priv, &msgs[i],
595 gmbus0_source | bus->reg0, 0);
597 ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
601 ret = gmbus_wait(dev_priv,
602 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
603 if (ret == -ETIMEDOUT)
609 /* Generate a STOP condition on the bus. Note that gmbus can't generata
610 * a STOP on the very first cycle. To simplify the code we
611 * unconditionally generate the STOP condition with an additional gmbus
613 I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
615 /* Mark the GMBUS interface as disabled after waiting for idle.
616 * We will re-enable it at the start of the next xfer,
617 * till then let it sleep.
619 if (gmbus_wait_idle(dev_priv)) {
620 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
624 I915_WRITE_FW(GMBUS0, 0);
630 * Wait for bus to IDLE before clearing NAK.
631 * If we clear the NAK while bus is still active, then it will stay
632 * active and the next transaction may fail.
634 * If no ACK is received during the address phase of a transaction, the
635 * adapter must report -ENXIO. It is not clear what to return if no ACK
636 * is received at other times. But we have to be careful to not return
637 * spurious -ENXIO because that will prevent i2c and drm edid functions
638 * from retrying. So return -ENXIO only when gmbus properly quiescents -
639 * timing out seems to happen when there _is_ a ddc chip present, but
640 * it's slow responding and only answers on the 2nd retry.
643 if (gmbus_wait_idle(dev_priv)) {
644 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
649 /* Toggle the Software Clear Interrupt bit. This has the effect
650 * of resetting the GMBUS controller and so clearing the
651 * BUS_ERROR raised by the slave's NAK.
653 I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT);
654 I915_WRITE_FW(GMBUS1, 0);
655 I915_WRITE_FW(GMBUS0, 0);
657 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
658 adapter->name, msgs[i].addr,
659 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
662 * Passive adapters sometimes NAK the first probe. Retry the first
663 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
664 * has retries internally. See also the retry loop in
665 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
667 if (ret == -ENXIO && i == 0 && try++ == 0) {
668 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
676 DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
677 bus->adapter.name, bus->reg0 & 0xff);
678 I915_WRITE_FW(GMBUS0, 0);
681 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
682 * instead. Use EAGAIN to have i2c core retry.
687 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
688 if (IS_GEN9_LP(dev_priv))
689 bxt_gmbus_clock_gating(dev_priv, true);
690 else if (HAS_PCH_SPT(dev_priv) ||
691 HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
692 pch_gmbus_clock_gating(dev_priv, true);
698 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
700 struct intel_gmbus *bus =
701 container_of(adapter, struct intel_gmbus, adapter);
702 struct drm_i915_private *dev_priv = bus->dev_priv;
703 intel_wakeref_t wakeref;
706 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
708 if (bus->force_bit) {
709 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
711 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
713 ret = do_gmbus_xfer(adapter, msgs, num, 0);
715 bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
718 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
723 int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
725 struct intel_gmbus *bus =
726 container_of(adapter, struct intel_gmbus, adapter);
727 struct drm_i915_private *dev_priv = bus->dev_priv;
728 u8 cmd = DRM_HDCP_DDC_AKSV;
729 u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
730 struct i2c_msg msgs[] = {
732 .addr = DRM_HDCP_DDC_ADDR,
738 .addr = DRM_HDCP_DDC_ADDR,
744 intel_wakeref_t wakeref;
747 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
748 mutex_lock(&dev_priv->gmbus_mutex);
751 * In order to output Aksv to the receiver, use an indexed write to
752 * pass the i2c command, and tell GMBUS to use the HW-provided value
753 * instead of sourcing GMBUS3 for the data.
755 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
757 mutex_unlock(&dev_priv->gmbus_mutex);
758 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
763 static u32 gmbus_func(struct i2c_adapter *adapter)
765 return i2c_bit_algo.functionality(adapter) &
766 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
767 /* I2C_FUNC_10BIT_ADDR | */
768 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
769 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
772 static const struct i2c_algorithm gmbus_algorithm = {
773 .master_xfer = gmbus_xfer,
774 .functionality = gmbus_func
777 static void gmbus_lock_bus(struct i2c_adapter *adapter,
780 struct intel_gmbus *bus = to_intel_gmbus(adapter);
781 struct drm_i915_private *dev_priv = bus->dev_priv;
783 mutex_lock(&dev_priv->gmbus_mutex);
786 static int gmbus_trylock_bus(struct i2c_adapter *adapter,
789 struct intel_gmbus *bus = to_intel_gmbus(adapter);
790 struct drm_i915_private *dev_priv = bus->dev_priv;
792 return mutex_trylock(&dev_priv->gmbus_mutex);
795 static void gmbus_unlock_bus(struct i2c_adapter *adapter,
798 struct intel_gmbus *bus = to_intel_gmbus(adapter);
799 struct drm_i915_private *dev_priv = bus->dev_priv;
801 mutex_unlock(&dev_priv->gmbus_mutex);
804 static const struct i2c_lock_operations gmbus_lock_ops = {
805 .lock_bus = gmbus_lock_bus,
806 .trylock_bus = gmbus_trylock_bus,
807 .unlock_bus = gmbus_unlock_bus,
811 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
812 * @dev_priv: i915 device private
814 int intel_setup_gmbus(struct drm_i915_private *dev_priv)
816 struct pci_dev *pdev = dev_priv->drm.pdev;
817 struct intel_gmbus *bus;
821 if (!HAS_DISPLAY(dev_priv))
824 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
825 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
826 else if (!HAS_GMCH(dev_priv))
828 * Broxton uses the same PCH offsets for South Display Engine,
829 * even though it doesn't have a PCH.
831 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
833 mutex_init(&dev_priv->gmbus_mutex);
834 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
836 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
837 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
840 bus = &dev_priv->gmbus[pin];
842 bus->adapter.owner = THIS_MODULE;
843 bus->adapter.class = I2C_CLASS_DDC;
844 snprintf(bus->adapter.name,
845 sizeof(bus->adapter.name),
847 get_gmbus_pin(dev_priv, pin)->name);
849 bus->adapter.dev.parent = &pdev->dev;
850 bus->dev_priv = dev_priv;
852 bus->adapter.algo = &gmbus_algorithm;
853 bus->adapter.lock_ops = &gmbus_lock_ops;
856 * We wish to retry with bit banging
857 * after a timed out GMBUS attempt.
859 bus->adapter.retries = 1;
861 /* By default use a conservative clock rate */
862 bus->reg0 = pin | GMBUS_RATE_100KHZ;
864 /* gmbus seems to be broken on i830 */
865 if (IS_I830(dev_priv))
868 intel_gpio_setup(bus, pin);
870 ret = i2c_add_adapter(&bus->adapter);
875 intel_i2c_reset(dev_priv);
881 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
884 bus = &dev_priv->gmbus[pin];
885 i2c_del_adapter(&bus->adapter);
890 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
893 if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
896 return &dev_priv->gmbus[pin].adapter;
899 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
901 struct intel_gmbus *bus = to_intel_gmbus(adapter);
903 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
906 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
908 struct intel_gmbus *bus = to_intel_gmbus(adapter);
909 struct drm_i915_private *dev_priv = bus->dev_priv;
911 mutex_lock(&dev_priv->gmbus_mutex);
913 bus->force_bit += force_bit ? 1 : -1;
914 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
915 force_bit ? "en" : "dis", adapter->name,
918 mutex_unlock(&dev_priv->gmbus_mutex);
921 void intel_teardown_gmbus(struct drm_i915_private *dev_priv)
923 struct intel_gmbus *bus;
926 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
927 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
930 bus = &dev_priv->gmbus[pin];
931 i2c_del_adapter(&bus->adapter);