2 * SPDX-License-Identifier: MIT
4 * Copyright © 2014-2018 Intel Corporation
7 #include "intel_huc_fw.h"
14 * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
15 * Efficiency Video Coding) operations. Userspace can use the firmware
16 * capabilities by adding HuC specific commands to batch buffers.
19 * The same firmware loader is used as the GuC. However, the actual
20 * loading to HW is deferred until GEM initialization is done.
22 * Note that HuC firmware loading must be done before GuC loading.
25 #define BXT_HUC_FW_MAJOR 01
26 #define BXT_HUC_FW_MINOR 8
27 #define BXT_BLD_NUM 2893
29 #define SKL_HUC_FW_MAJOR 01
30 #define SKL_HUC_FW_MINOR 07
31 #define SKL_BLD_NUM 1398
33 #define KBL_HUC_FW_MAJOR 02
34 #define KBL_HUC_FW_MINOR 00
35 #define KBL_BLD_NUM 1810
37 #define HUC_FW_PATH(platform, major, minor, bld_num) \
38 "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
39 __stringify(minor) "_" __stringify(bld_num) ".bin"
41 #define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
42 SKL_HUC_FW_MINOR, SKL_BLD_NUM)
43 MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
45 #define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
46 BXT_HUC_FW_MINOR, BXT_BLD_NUM)
47 MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
49 #define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
50 KBL_HUC_FW_MINOR, KBL_BLD_NUM)
51 MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
53 static void huc_fw_select(struct intel_uc_fw *huc_fw)
55 struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
56 struct drm_i915_private *dev_priv = huc_to_i915(huc);
58 GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
60 if (!HAS_HUC(dev_priv))
63 if (i915_modparams.huc_firmware_path) {
64 huc_fw->path = i915_modparams.huc_firmware_path;
65 huc_fw->major_ver_wanted = 0;
66 huc_fw->minor_ver_wanted = 0;
67 } else if (IS_SKYLAKE(dev_priv)) {
68 huc_fw->path = I915_SKL_HUC_UCODE;
69 huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
70 huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
71 } else if (IS_BROXTON(dev_priv)) {
72 huc_fw->path = I915_BXT_HUC_UCODE;
73 huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
74 huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
75 } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
76 huc_fw->path = I915_KBL_HUC_UCODE;
77 huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
78 huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
83 * intel_huc_fw_init_early() - initializes HuC firmware struct
84 * @huc: intel_huc struct
86 * On platforms with HuC selects firmware for uploading
88 void intel_huc_fw_init_early(struct intel_huc *huc)
90 struct intel_uc_fw *huc_fw = &huc->fw;
92 intel_uc_fw_init(huc_fw, INTEL_UC_FW_TYPE_HUC);
93 huc_fw_select(huc_fw);
97 * huc_fw_xfer() - DMA's the firmware
98 * @huc_fw: the firmware descriptor
99 * @vma: the firmware image (bound into the GGTT)
101 * Transfer the firmware image to RAM for execution by the microcontroller.
103 * Return: 0 on success, non-zero on failure
105 static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
107 struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
108 struct drm_i915_private *dev_priv = huc_to_i915(huc);
109 unsigned long offset = 0;
113 GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
115 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
117 /* Set the source address for the uCode */
118 offset = intel_guc_ggtt_offset(&dev_priv->guc, vma) +
119 huc_fw->header_offset;
120 I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
121 I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
123 /* Hardware doesn't look at destination address for HuC. Set it to 0,
124 * but still program the correct address space.
126 I915_WRITE(DMA_ADDR_1_LOW, 0);
127 I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
129 size = huc_fw->header_size + huc_fw->ucode_size;
130 I915_WRITE(DMA_COPY_SIZE, size);
133 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
135 /* Wait for DMA to finish */
136 ret = intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0, 100);
138 DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
140 /* Disable the bits once DMA is over */
141 I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
143 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
149 * intel_huc_fw_upload() - load HuC uCode to device
150 * @huc: intel_huc structure
152 * Called from intel_uc_init_hw() during driver load, resume from sleep and
153 * after a GPU reset. Note that HuC must be loaded before GuC.
155 * The firmware image should have already been fetched into memory, so only
156 * check that fetch succeeded, and then transfer the image to the h/w.
158 * Return: non-zero code on error
160 int intel_huc_fw_upload(struct intel_huc *huc)
162 return intel_uc_fw_upload(&huc->fw, huc_fw_xfer);