drivers/gpu/drm/i915/intel_huc_fw.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2014-2018 Intel Corporation
   5  */
   6
   7 #include "intel_huc_fw.h"
   8 #include "i915_drv.h"
   9
  10 /**
  11  * DOC: HuC Firmware
  12  *
  13  * Motivation:
  14  * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
  15  * Efficiency Video Coding) operations. Userspace can use the firmware
  16  * capabilities by adding HuC specific commands to batch buffers.
  17  *
  18  * Implementation:
  19  * The same firmware loader is used as the GuC. However, the actual
  20  * loading to HW is deferred until GEM initialization is done.
  21  *
  22  * Note that HuC firmware loading must be done before GuC loading.
  23  */
  24
  25 #define BXT_HUC_FW_MAJOR 01
  26 #define BXT_HUC_FW_MINOR 8
  27 #define BXT_BLD_NUM 2893
  28
  29 #define SKL_HUC_FW_MAJOR 01
  30 #define SKL_HUC_FW_MINOR 07
  31 #define SKL_BLD_NUM 1398
  32
  33 #define KBL_HUC_FW_MAJOR 02
  34 #define KBL_HUC_FW_MINOR 00
  35 #define KBL_BLD_NUM 1810
  36
  37 #define GLK_HUC_FW_MAJOR 03
  38 #define GLK_HUC_FW_MINOR 01
  39 #define GLK_BLD_NUM 2893
  40
  41 #define ICL_HUC_FW_MAJOR 8
  42 #define ICL_HUC_FW_MINOR 4
  43 #define ICL_BLD_NUM 3238
  44
  45 #define HUC_FW_PATH(platform, major, minor, bld_num) \
  46         "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
  47         __stringify(minor) "_" __stringify(bld_num) ".bin"
  48
  49 #define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
  50         SKL_HUC_FW_MINOR, SKL_BLD_NUM)
  51 MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
  52
  53 #define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
  54         BXT_HUC_FW_MINOR, BXT_BLD_NUM)
  55 MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
  56
  57 #define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
  58         KBL_HUC_FW_MINOR, KBL_BLD_NUM)
  59 MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
  60
  61 #define I915_GLK_HUC_UCODE HUC_FW_PATH(glk, GLK_HUC_FW_MAJOR, \
  62         GLK_HUC_FW_MINOR, GLK_BLD_NUM)
  63 MODULE_FIRMWARE(I915_GLK_HUC_UCODE);
  64
  65 #define I915_ICL_HUC_UCODE HUC_FW_PATH(icl, ICL_HUC_FW_MAJOR, \
  66         ICL_HUC_FW_MINOR, ICL_BLD_NUM)
  67 MODULE_FIRMWARE(I915_ICL_HUC_UCODE);
  68
  69 static void huc_fw_select(struct intel_uc_fw *huc_fw)
  70 {
  71         struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
  72         struct drm_i915_private *dev_priv = huc_to_i915(huc);
  73
  74         GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
  75
  76         if (!HAS_HUC(dev_priv))
  77                 return;
  78
  79         if (i915_modparams.huc_firmware_path) {
  80                 huc_fw->path = i915_modparams.huc_firmware_path;
  81                 huc_fw->major_ver_wanted = 0;
  82                 huc_fw->minor_ver_wanted = 0;
  83         } else if (IS_SKYLAKE(dev_priv)) {
  84                 huc_fw->path = I915_SKL_HUC_UCODE;
  85                 huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
  86                 huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
  87         } else if (IS_BROXTON(dev_priv)) {
  88                 huc_fw->path = I915_BXT_HUC_UCODE;
  89                 huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
  90                 huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
  91         } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
  92                 huc_fw->path = I915_KBL_HUC_UCODE;
  93                 huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
  94                 huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
  95         } else if (IS_GEMINILAKE(dev_priv)) {
  96                 huc_fw->path = I915_GLK_HUC_UCODE;
  97                 huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
  98                 huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
  99         } else if (IS_ICELAKE(dev_priv)) {
 100                 huc_fw->path = I915_ICL_HUC_UCODE;
 101                 huc_fw->major_ver_wanted = ICL_HUC_FW_MAJOR;
 102                 huc_fw->minor_ver_wanted = ICL_HUC_FW_MINOR;
 103         }
 104 }
 105
 106 /**
 107  * intel_huc_fw_init_early() - initializes HuC firmware struct
 108  * @huc: intel_huc struct
 109  *
 110  * On platforms with HuC selects firmware for uploading
 111  */
 112 void intel_huc_fw_init_early(struct intel_huc *huc)
 113 {
 114         struct intel_uc_fw *huc_fw = &huc->fw;
 115
 116         intel_uc_fw_init_early(huc_fw, INTEL_UC_FW_TYPE_HUC);
 117         huc_fw_select(huc_fw);
 118 }
 119
 120 static void huc_xfer_rsa(struct intel_huc *huc)
 121 {
 122         struct intel_uc_fw *fw = &huc->fw;
 123         struct sg_table *pages = fw->obj->mm.pages;
 124
 125         /*
 126          * HuC firmware image is outside GuC accessible range.
 127          * Copy the RSA signature out of the image into
 128          * the perma-pinned region set aside for it
 129          */
 130         sg_pcopy_to_buffer(pages->sgl, pages->nents,
 131                            huc->rsa_data_vaddr, fw->rsa_size,
 132                            fw->rsa_offset);
 133 }
 134
 135 static int huc_xfer_ucode(struct intel_huc *huc)
 136 {
 137         struct intel_uc_fw *huc_fw = &huc->fw;
 138         struct drm_i915_private *dev_priv = huc_to_i915(huc);
 139         struct intel_uncore *uncore = &dev_priv->uncore;
 140         unsigned long offset = 0;
 141         u32 size;
 142         int ret;
 143
 144         GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
 145
 146         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 147
 148         /* Set the source address for the uCode */
 149         offset = intel_uc_fw_ggtt_offset(huc_fw) +
 150                  huc_fw->header_offset;
 151         intel_uncore_write(uncore, DMA_ADDR_0_LOW,
 152                            lower_32_bits(offset));
 153         intel_uncore_write(uncore, DMA_ADDR_0_HIGH,
 154                            upper_32_bits(offset) & 0xFFFF);
 155
 156         /*
 157          * Hardware doesn't look at destination address for HuC. Set it to 0,
 158          * but still program the correct address space.
 159          */
 160         intel_uncore_write(uncore, DMA_ADDR_1_LOW, 0);
 161         intel_uncore_write(uncore, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 162
 163         size = huc_fw->header_size + huc_fw->ucode_size;
 164         intel_uncore_write(uncore, DMA_COPY_SIZE, size);
 165
 166         /* Start the DMA */
 167         intel_uncore_write(uncore, DMA_CTRL,
 168                            _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
 169
 170         /* Wait for DMA to finish */
 171         ret = intel_wait_for_register_fw(uncore, DMA_CTRL, START_DMA, 0, 100);
 172
 173         DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
 174
 175         /* Disable the bits once DMA is over */
 176         intel_uncore_write(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
 177
 178         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 179
 180         return ret;
 181 }
 182
 183 /**
 184  * huc_fw_xfer() - DMA's the firmware
 185  * @huc_fw: the firmware descriptor
 186  *
 187  * Transfer the firmware image to RAM for execution by the microcontroller.
 188  *
 189  * Return: 0 on success, non-zero on failure
 190  */
 191 static int huc_fw_xfer(struct intel_uc_fw *huc_fw)
 192 {
 193         struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
 194
 195         huc_xfer_rsa(huc);
 196
 197         return huc_xfer_ucode(huc);
 198 }
 199
 200 /**
 201  * intel_huc_fw_upload() - load HuC uCode to device
 202  * @huc: intel_huc structure
 203  *
 204  * Called from intel_uc_init_hw() during driver load, resume from sleep and
 205  * after a GPU reset. Note that HuC must be loaded before GuC.
 206  *
 207  * The firmware image should have already been fetched into memory, so only
 208  * check that fetch succeeded, and then transfer the image to the h/w.
 209  *
 210  * Return:      non-zero code on error
 211  */
 212 int intel_huc_fw_upload(struct intel_huc *huc)
 213 {
 214         return intel_uc_fw_upload(&huc->fw, huc_fw_xfer);
 215 }