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25 #include <linux/types.h>
27 #include "intel_huc.h"
30 void intel_huc_init_early(struct intel_huc *huc)
32 struct drm_i915_private *i915 = huc_to_i915(huc);
34 intel_huc_fw_init_early(huc);
36 if (INTEL_GEN(i915) >= 11) {
37 huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
38 huc->status.mask = HUC_LOAD_SUCCESSFUL;
39 huc->status.value = HUC_LOAD_SUCCESSFUL;
41 huc->status.reg = HUC_STATUS2;
42 huc->status.mask = HUC_FW_VERIFIED;
43 huc->status.value = HUC_FW_VERIFIED;
47 int intel_huc_init_misc(struct intel_huc *huc)
49 struct drm_i915_private *i915 = huc_to_i915(huc);
51 intel_uc_fw_fetch(i915, &huc->fw);
55 static int intel_huc_rsa_data_create(struct intel_huc *huc)
57 struct drm_i915_private *i915 = huc_to_i915(huc);
58 struct intel_guc *guc = &i915->guc;
63 * HuC firmware will sit above GUC_GGTT_TOP and will not map
64 * through GTT. Unfortunately, this means GuC cannot perform
65 * the HuC auth. as the rsa offset now falls within the GuC
66 * inaccessible range. We resort to perma-pinning an additional
67 * vma within the accessible range that only contains the rsa
68 * signature. The GuC can use this extra pinning to perform
69 * the authentication since its GGTT offset will be GuC
72 vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
76 vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
78 i915_vma_unpin_and_release(&vma, 0);
79 return PTR_ERR(vaddr);
83 huc->rsa_data_vaddr = vaddr;
88 static void intel_huc_rsa_data_destroy(struct intel_huc *huc)
90 i915_vma_unpin_and_release(&huc->rsa_data, I915_VMA_RELEASE_MAP);
93 int intel_huc_init(struct intel_huc *huc)
97 err = intel_huc_rsa_data_create(huc);
101 return intel_uc_fw_init(&huc->fw);
104 void intel_huc_fini(struct intel_huc *huc)
106 intel_uc_fw_fini(&huc->fw);
107 intel_huc_rsa_data_destroy(huc);
111 * intel_huc_auth() - Authenticate HuC uCode
112 * @huc: intel_huc structure
114 * Called after HuC and GuC firmware loading during intel_uc_init_hw().
116 * This function pins HuC firmware image object into GGTT.
117 * Then it invokes GuC action to authenticate passing the offset to RSA
118 * signature through intel_guc_auth_huc(). It then waits for 50ms for
119 * firmware verification ACK and unpins the object.
121 int intel_huc_auth(struct intel_huc *huc)
123 struct drm_i915_private *i915 = huc_to_i915(huc);
124 struct intel_guc *guc = &i915->guc;
127 if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
130 ret = intel_guc_auth_huc(guc,
131 intel_guc_ggtt_offset(guc, huc->rsa_data));
133 DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
137 /* Check authentication status, it should be done by now */
138 ret = __intel_wait_for_register(&i915->uncore,
144 DRM_ERROR("HuC: Firmware not verified %d\n", ret);
151 huc->fw.load_status = INTEL_UC_FIRMWARE_FAIL;
153 DRM_ERROR("HuC: Authentication failed %d\n", ret);
158 * intel_huc_check_status() - check HuC status
159 * @huc: intel_huc structure
161 * This function reads status register to verify if HuC
162 * firmware was successfully loaded.
164 * Returns: 1 if HuC firmware is loaded and verified,
165 * 0 if HuC firmware is not loaded and -ENODEV if HuC
166 * is not present on this platform.
168 int intel_huc_check_status(struct intel_huc *huc)
170 struct drm_i915_private *dev_priv = huc_to_i915(huc);
171 intel_wakeref_t wakeref;
174 if (!HAS_HUC(dev_priv))
177 with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
178 status = (I915_READ(huc->status.reg) & huc->status.mask) ==