drivers/gpu/drm/i915/intel_huc.c

   1 /*
   2  * Copyright © 2016-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/types.h>
  26
  27 #include "intel_huc.h"
  28 #include "i915_drv.h"
  29
  30 /**
  31  * DOC: HuC Firmware
  32  *
  33  * Motivation:
  34  * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
  35  * Efficiency Video Coding) operations. Userspace can use the firmware
  36  * capabilities by adding HuC specific commands to batch buffers.
  37  *
  38  * Implementation:
  39  * The same firmware loader is used as the GuC. However, the actual
  40  * loading to HW is deferred until GEM initialization is done.
  41  *
  42  * Note that HuC firmware loading must be done before GuC loading.
  43  */
  44
  45 #define BXT_HUC_FW_MAJOR 01
  46 #define BXT_HUC_FW_MINOR 07
  47 #define BXT_BLD_NUM 1398
  48
  49 #define SKL_HUC_FW_MAJOR 01
  50 #define SKL_HUC_FW_MINOR 07
  51 #define SKL_BLD_NUM 1398
  52
  53 #define KBL_HUC_FW_MAJOR 02
  54 #define KBL_HUC_FW_MINOR 00
  55 #define KBL_BLD_NUM 1810
  56
  57 #define GLK_HUC_FW_MAJOR 02
  58 #define GLK_HUC_FW_MINOR 00
  59 #define GLK_BLD_NUM 1748
  60
  61 #define HUC_FW_PATH(platform, major, minor, bld_num) \
  62         "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
  63         __stringify(minor) "_" __stringify(bld_num) ".bin"
  64
  65 #define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
  66         SKL_HUC_FW_MINOR, SKL_BLD_NUM)
  67 MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
  68
  69 #define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
  70         BXT_HUC_FW_MINOR, BXT_BLD_NUM)
  71 MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
  72
  73 #define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
  74         KBL_HUC_FW_MINOR, KBL_BLD_NUM)
  75 MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
  76
  77 #define I915_GLK_HUC_UCODE HUC_FW_PATH(glk, GLK_HUC_FW_MAJOR, \
  78         GLK_HUC_FW_MINOR, GLK_BLD_NUM)
  79
  80 /**
  81  * intel_huc_select_fw() - selects HuC firmware for loading
  82  * @huc:        intel_huc struct
  83  */
  84 void intel_huc_select_fw(struct intel_huc *huc)
  85 {
  86         struct drm_i915_private *dev_priv = huc_to_i915(huc);
  87
  88         intel_uc_fw_init(&huc->fw, INTEL_UC_FW_TYPE_HUC);
  89
  90         if (i915_modparams.huc_firmware_path) {
  91                 huc->fw.path = i915_modparams.huc_firmware_path;
  92                 huc->fw.major_ver_wanted = 0;
  93                 huc->fw.minor_ver_wanted = 0;
  94         } else if (IS_SKYLAKE(dev_priv)) {
  95                 huc->fw.path = I915_SKL_HUC_UCODE;
  96                 huc->fw.major_ver_wanted = SKL_HUC_FW_MAJOR;
  97                 huc->fw.minor_ver_wanted = SKL_HUC_FW_MINOR;
  98         } else if (IS_BROXTON(dev_priv)) {
  99                 huc->fw.path = I915_BXT_HUC_UCODE;
 100                 huc->fw.major_ver_wanted = BXT_HUC_FW_MAJOR;
 101                 huc->fw.minor_ver_wanted = BXT_HUC_FW_MINOR;
 102         } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 103                 huc->fw.path = I915_KBL_HUC_UCODE;
 104                 huc->fw.major_ver_wanted = KBL_HUC_FW_MAJOR;
 105                 huc->fw.minor_ver_wanted = KBL_HUC_FW_MINOR;
 106         } else if (IS_GEMINILAKE(dev_priv)) {
 107                 huc->fw.path = I915_GLK_HUC_UCODE;
 108                 huc->fw.major_ver_wanted = GLK_HUC_FW_MAJOR;
 109                 huc->fw.minor_ver_wanted = GLK_HUC_FW_MINOR;
 110         } else {
 111                 DRM_ERROR("No HuC firmware known for platform with HuC!\n");
 112                 return;
 113         }
 114 }
 115
 116 /**
 117  * huc_ucode_xfer() - DMA's the firmware
 118  * @dev_priv: the drm_i915_private device
 119  *
 120  * Transfer the firmware image to RAM for execution by the microcontroller.
 121  *
 122  * Return: 0 on success, non-zero on failure
 123  */
 124 static int huc_ucode_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
 125 {
 126         struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
 127         struct drm_i915_private *dev_priv = huc_to_i915(huc);
 128         unsigned long offset = 0;
 129         u32 size;
 130         int ret;
 131
 132         GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
 133
 134         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 135
 136         /* Set the source address for the uCode */
 137         offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
 138         I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 139         I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 140
 141         /* Hardware doesn't look at destination address for HuC. Set it to 0,
 142          * but still program the correct address space.
 143          */
 144         I915_WRITE(DMA_ADDR_1_LOW, 0);
 145         I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 146
 147         size = huc_fw->header_size + huc_fw->ucode_size;
 148         I915_WRITE(DMA_COPY_SIZE, size);
 149
 150         /* Start the DMA */
 151         I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
 152
 153         /* Wait for DMA to finish */
 154         ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
 155
 156         DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
 157
 158         /* Disable the bits once DMA is over */
 159         I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
 160
 161         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 162
 163         return ret;
 164 }
 165
 166 /**
 167  * intel_huc_init_hw() - load HuC uCode to device
 168  * @huc: intel_huc structure
 169  *
 170  * Called from guc_setup() during driver loading and also after a GPU reset.
 171  * Be note that HuC loading must be done before GuC loading.
 172  *
 173  * The firmware image should have already been fetched into memory by the
 174  * earlier call to intel_huc_init(), so here we need only check that
 175  * is succeeded, and then transfer the image to the h/w.
 176  *
 177  */
 178 void intel_huc_init_hw(struct intel_huc *huc)
 179 {
 180         intel_uc_fw_upload(&huc->fw, huc_ucode_xfer);
 181 }
 182
 183 /**
 184  * intel_huc_auth() - Authenticate HuC uCode
 185  * @huc: intel_huc structure
 186  *
 187  * Called after HuC and GuC firmware loading during intel_uc_init_hw().
 188  *
 189  * This function pins HuC firmware image object into GGTT.
 190  * Then it invokes GuC action to authenticate passing the offset to RSA
 191  * signature through intel_guc_auth_huc(). It then waits for 50ms for
 192  * firmware verification ACK and unpins the object.
 193  */
 194 void intel_huc_auth(struct intel_huc *huc)
 195 {
 196         struct drm_i915_private *i915 = huc_to_i915(huc);
 197         struct intel_guc *guc = &i915->guc;
 198         struct i915_vma *vma;
 199         int ret;
 200
 201         if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 202                 return;
 203
 204         vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
 205                                 PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
 206         if (IS_ERR(vma)) {
 207                 DRM_ERROR("failed to pin huc fw object %d\n",
 208                                 (int)PTR_ERR(vma));
 209                 return;
 210         }
 211
 212         ret = intel_guc_auth_huc(guc,
 213                                  guc_ggtt_offset(vma) + huc->fw.rsa_offset);
 214         if (ret) {
 215                 DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
 216                 goto out;
 217         }
 218
 219         /* Check authentication status, it should be done by now */
 220         ret = intel_wait_for_register(i915,
 221                                       HUC_STATUS2,
 222                                       HUC_FW_VERIFIED,
 223                                       HUC_FW_VERIFIED,
 224                                       50);
 225         if (ret) {
 226                 DRM_ERROR("HuC: Authentication failed %d\n", ret);
 227                 goto out;
 228         }
 229
 230 out:
 231         i915_vma_unpin(vma);
 232 }