drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_scdc_helper.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include <drm/intel_lpe_audio.h>
  41 #include "i915_drv.h"
  42
  43 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  44 {
  45         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  46 }
  47
  48 static void
  49 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  50 {
  51         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  52         struct drm_i915_private *dev_priv = to_i915(dev);
  53         uint32_t enabled_bits;
  54
  55         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  56
  57         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  58              "HDMI port enabled, expecting disabled\n");
  59 }
  60
  61 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  62 {
  63         struct intel_digital_port *intel_dig_port =
  64                 container_of(encoder, struct intel_digital_port, base.base);
  65         return &intel_dig_port->hdmi;
  66 }
  67
  68 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  69 {
  70         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  71 }
  72
  73 static u32 g4x_infoframe_index(unsigned int type)
  74 {
  75         switch (type) {
  76         case HDMI_INFOFRAME_TYPE_AVI:
  77                 return VIDEO_DIP_SELECT_AVI;
  78         case HDMI_INFOFRAME_TYPE_SPD:
  79                 return VIDEO_DIP_SELECT_SPD;
  80         case HDMI_INFOFRAME_TYPE_VENDOR:
  81                 return VIDEO_DIP_SELECT_VENDOR;
  82         default:
  83                 MISSING_CASE(type);
  84                 return 0;
  85         }
  86 }
  87
  88 static u32 g4x_infoframe_enable(unsigned int type)
  89 {
  90         switch (type) {
  91         case HDMI_INFOFRAME_TYPE_AVI:
  92                 return VIDEO_DIP_ENABLE_AVI;
  93         case HDMI_INFOFRAME_TYPE_SPD:
  94                 return VIDEO_DIP_ENABLE_SPD;
  95         case HDMI_INFOFRAME_TYPE_VENDOR:
  96                 return VIDEO_DIP_ENABLE_VENDOR;
  97         default:
  98                 MISSING_CASE(type);
  99                 return 0;
 100         }
 101 }
 102
 103 static u32 hsw_infoframe_enable(unsigned int type)
 104 {
 105         switch (type) {
 106         case DP_SDP_VSC:
 107                 return VIDEO_DIP_ENABLE_VSC_HSW;
 108         case HDMI_INFOFRAME_TYPE_AVI:
 109                 return VIDEO_DIP_ENABLE_AVI_HSW;
 110         case HDMI_INFOFRAME_TYPE_SPD:
 111                 return VIDEO_DIP_ENABLE_SPD_HSW;
 112         case HDMI_INFOFRAME_TYPE_VENDOR:
 113                 return VIDEO_DIP_ENABLE_VS_HSW;
 114         default:
 115                 MISSING_CASE(type);
 116                 return 0;
 117         }
 118 }
 119
 120 static i915_reg_t
 121 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 122                  enum transcoder cpu_transcoder,
 123                  unsigned int type,
 124                  int i)
 125 {
 126         switch (type) {
 127         case DP_SDP_VSC:
 128                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 129         case HDMI_INFOFRAME_TYPE_AVI:
 130                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 131         case HDMI_INFOFRAME_TYPE_SPD:
 132                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 133         case HDMI_INFOFRAME_TYPE_VENDOR:
 134                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 135         default:
 136                 MISSING_CASE(type);
 137                 return INVALID_MMIO_REG;
 138         }
 139 }
 140
 141 static void g4x_write_infoframe(struct drm_encoder *encoder,
 142                                 const struct intel_crtc_state *crtc_state,
 143                                 unsigned int type,
 144                                 const void *frame, ssize_t len)
 145 {
 146         const uint32_t *data = frame;
 147         struct drm_device *dev = encoder->dev;
 148         struct drm_i915_private *dev_priv = to_i915(dev);
 149         u32 val = I915_READ(VIDEO_DIP_CTL);
 150         int i;
 151
 152         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 153
 154         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 155         val |= g4x_infoframe_index(type);
 156
 157         val &= ~g4x_infoframe_enable(type);
 158
 159         I915_WRITE(VIDEO_DIP_CTL, val);
 160
 161         mmiowb();
 162         for (i = 0; i < len; i += 4) {
 163                 I915_WRITE(VIDEO_DIP_DATA, *data);
 164                 data++;
 165         }
 166         /* Write every possible data byte to force correct ECC calculation. */
 167         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 168                 I915_WRITE(VIDEO_DIP_DATA, 0);
 169         mmiowb();
 170
 171         val |= g4x_infoframe_enable(type);
 172         val &= ~VIDEO_DIP_FREQ_MASK;
 173         val |= VIDEO_DIP_FREQ_VSYNC;
 174
 175         I915_WRITE(VIDEO_DIP_CTL, val);
 176         POSTING_READ(VIDEO_DIP_CTL);
 177 }
 178
 179 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
 180                                   const struct intel_crtc_state *pipe_config)
 181 {
 182         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 183         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 184         u32 val = I915_READ(VIDEO_DIP_CTL);
 185
 186         if ((val & VIDEO_DIP_ENABLE) == 0)
 187                 return false;
 188
 189         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
 190                 return false;
 191
 192         return val & (VIDEO_DIP_ENABLE_AVI |
 193                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 194 }
 195
 196 static void ibx_write_infoframe(struct drm_encoder *encoder,
 197                                 const struct intel_crtc_state *crtc_state,
 198                                 unsigned int type,
 199                                 const void *frame, ssize_t len)
 200 {
 201         const uint32_t *data = frame;
 202         struct drm_device *dev = encoder->dev;
 203         struct drm_i915_private *dev_priv = to_i915(dev);
 204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 205         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 206         u32 val = I915_READ(reg);
 207         int i;
 208
 209         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 210
 211         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 212         val |= g4x_infoframe_index(type);
 213
 214         val &= ~g4x_infoframe_enable(type);
 215
 216         I915_WRITE(reg, val);
 217
 218         mmiowb();
 219         for (i = 0; i < len; i += 4) {
 220                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 221                 data++;
 222         }
 223         /* Write every possible data byte to force correct ECC calculation. */
 224         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 225                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 226         mmiowb();
 227
 228         val |= g4x_infoframe_enable(type);
 229         val &= ~VIDEO_DIP_FREQ_MASK;
 230         val |= VIDEO_DIP_FREQ_VSYNC;
 231
 232         I915_WRITE(reg, val);
 233         POSTING_READ(reg);
 234 }
 235
 236 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
 237                                   const struct intel_crtc_state *pipe_config)
 238 {
 239         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 240         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 241         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 242         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 243         u32 val = I915_READ(reg);
 244
 245         if ((val & VIDEO_DIP_ENABLE) == 0)
 246                 return false;
 247
 248         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
 249                 return false;
 250
 251         return val & (VIDEO_DIP_ENABLE_AVI |
 252                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 253                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 254 }
 255
 256 static void cpt_write_infoframe(struct drm_encoder *encoder,
 257                                 const struct intel_crtc_state *crtc_state,
 258                                 unsigned int type,
 259                                 const void *frame, ssize_t len)
 260 {
 261         const uint32_t *data = frame;
 262         struct drm_device *dev = encoder->dev;
 263         struct drm_i915_private *dev_priv = to_i915(dev);
 264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 265         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 266         u32 val = I915_READ(reg);
 267         int i;
 268
 269         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 270
 271         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 272         val |= g4x_infoframe_index(type);
 273
 274         /* The DIP control register spec says that we need to update the AVI
 275          * infoframe without clearing its enable bit */
 276         if (type != HDMI_INFOFRAME_TYPE_AVI)
 277                 val &= ~g4x_infoframe_enable(type);
 278
 279         I915_WRITE(reg, val);
 280
 281         mmiowb();
 282         for (i = 0; i < len; i += 4) {
 283                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 284                 data++;
 285         }
 286         /* Write every possible data byte to force correct ECC calculation. */
 287         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 288                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 289         mmiowb();
 290
 291         val |= g4x_infoframe_enable(type);
 292         val &= ~VIDEO_DIP_FREQ_MASK;
 293         val |= VIDEO_DIP_FREQ_VSYNC;
 294
 295         I915_WRITE(reg, val);
 296         POSTING_READ(reg);
 297 }
 298
 299 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
 300                                   const struct intel_crtc_state *pipe_config)
 301 {
 302         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 303         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 304         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 305
 306         if ((val & VIDEO_DIP_ENABLE) == 0)
 307                 return false;
 308
 309         return val & (VIDEO_DIP_ENABLE_AVI |
 310                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 311                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 312 }
 313
 314 static void vlv_write_infoframe(struct drm_encoder *encoder,
 315                                 const struct intel_crtc_state *crtc_state,
 316                                 unsigned int type,
 317                                 const void *frame, ssize_t len)
 318 {
 319         const uint32_t *data = frame;
 320         struct drm_device *dev = encoder->dev;
 321         struct drm_i915_private *dev_priv = to_i915(dev);
 322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 323         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 324         u32 val = I915_READ(reg);
 325         int i;
 326
 327         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 328
 329         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 330         val |= g4x_infoframe_index(type);
 331
 332         val &= ~g4x_infoframe_enable(type);
 333
 334         I915_WRITE(reg, val);
 335
 336         mmiowb();
 337         for (i = 0; i < len; i += 4) {
 338                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 339                 data++;
 340         }
 341         /* Write every possible data byte to force correct ECC calculation. */
 342         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 343                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 344         mmiowb();
 345
 346         val |= g4x_infoframe_enable(type);
 347         val &= ~VIDEO_DIP_FREQ_MASK;
 348         val |= VIDEO_DIP_FREQ_VSYNC;
 349
 350         I915_WRITE(reg, val);
 351         POSTING_READ(reg);
 352 }
 353
 354 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
 355                                   const struct intel_crtc_state *pipe_config)
 356 {
 357         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 358         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 359         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 360         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 361
 362         if ((val & VIDEO_DIP_ENABLE) == 0)
 363                 return false;
 364
 365         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
 366                 return false;
 367
 368         return val & (VIDEO_DIP_ENABLE_AVI |
 369                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 370                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 371 }
 372
 373 static void hsw_write_infoframe(struct drm_encoder *encoder,
 374                                 const struct intel_crtc_state *crtc_state,
 375                                 unsigned int type,
 376                                 const void *frame, ssize_t len)
 377 {
 378         const uint32_t *data = frame;
 379         struct drm_device *dev = encoder->dev;
 380         struct drm_i915_private *dev_priv = to_i915(dev);
 381         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 382         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 383         i915_reg_t data_reg;
 384         int data_size = type == DP_SDP_VSC ?
 385                 VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
 386         int i;
 387         u32 val = I915_READ(ctl_reg);
 388
 389         data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
 390
 391         val &= ~hsw_infoframe_enable(type);
 392         I915_WRITE(ctl_reg, val);
 393
 394         mmiowb();
 395         for (i = 0; i < len; i += 4) {
 396                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 397                                             type, i >> 2), *data);
 398                 data++;
 399         }
 400         /* Write every possible data byte to force correct ECC calculation. */
 401         for (; i < data_size; i += 4)
 402                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 403                                             type, i >> 2), 0);
 404         mmiowb();
 405
 406         val |= hsw_infoframe_enable(type);
 407         I915_WRITE(ctl_reg, val);
 408         POSTING_READ(ctl_reg);
 409 }
 410
 411 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
 412                                   const struct intel_crtc_state *pipe_config)
 413 {
 414         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 415         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 416
 417         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 418                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 419                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 420 }
 421
 422 /*
 423  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 424  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 425  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 426  * used for both technologies.
 427  *
 428  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 429  * DW1:       DB3       | DB2 | DB1 | DB0
 430  * DW2:       DB7       | DB6 | DB5 | DB4
 431  * DW3: ...
 432  *
 433  * (HB is Header Byte, DB is Data Byte)
 434  *
 435  * The hdmi pack() functions don't know about that hardware specific hole so we
 436  * trick them by giving an offset into the buffer and moving back the header
 437  * bytes by one.
 438  */
 439 static void intel_write_infoframe(struct drm_encoder *encoder,
 440                                   const struct intel_crtc_state *crtc_state,
 441                                   union hdmi_infoframe *frame)
 442 {
 443         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 444         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 445         ssize_t len;
 446
 447         /* see comment above for the reason for this offset */
 448         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 449         if (len < 0)
 450                 return;
 451
 452         /* Insert the 'hole' (see big comment above) at position 3 */
 453         buffer[0] = buffer[1];
 454         buffer[1] = buffer[2];
 455         buffer[2] = buffer[3];
 456         buffer[3] = 0;
 457         len++;
 458
 459         intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
 460 }
 461
 462 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 463                                          const struct intel_crtc_state *crtc_state)
 464 {
 465         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 466         const struct drm_display_mode *adjusted_mode =
 467                 &crtc_state->base.adjusted_mode;
 468         struct drm_connector *connector = &intel_hdmi->attached_connector->base;
 469         bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported;
 470         union hdmi_infoframe frame;
 471         int ret;
 472
 473         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 474                                                        adjusted_mode,
 475                                                        is_hdmi2_sink);
 476         if (ret < 0) {
 477                 DRM_ERROR("couldn't fill AVI infoframe\n");
 478                 return;
 479         }
 480
 481         if (crtc_state->ycbcr420)
 482                 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
 483         else
 484                 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
 485
 486         drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
 487                                            crtc_state->limited_color_range ?
 488                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 489                                            HDMI_QUANTIZATION_RANGE_FULL,
 490                                            intel_hdmi->rgb_quant_range_selectable,
 491                                            is_hdmi2_sink);
 492
 493         /* TODO: handle pixel repetition for YCBCR420 outputs */
 494         intel_write_infoframe(encoder, crtc_state, &frame);
 495 }
 496
 497 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder,
 498                                          const struct intel_crtc_state *crtc_state)
 499 {
 500         union hdmi_infoframe frame;
 501         int ret;
 502
 503         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 504         if (ret < 0) {
 505                 DRM_ERROR("couldn't fill SPD infoframe\n");
 506                 return;
 507         }
 508
 509         frame.spd.sdi = HDMI_SPD_SDI_PC;
 510
 511         intel_write_infoframe(encoder, crtc_state, &frame);
 512 }
 513
 514 static void
 515 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 516                               const struct intel_crtc_state *crtc_state,
 517                               const struct drm_connector_state *conn_state)
 518 {
 519         union hdmi_infoframe frame;
 520         int ret;
 521
 522         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 523                                                           conn_state->connector,
 524                                                           &crtc_state->base.adjusted_mode);
 525         if (ret < 0)
 526                 return;
 527
 528         intel_write_infoframe(encoder, crtc_state, &frame);
 529 }
 530
 531 static void g4x_set_infoframes(struct drm_encoder *encoder,
 532                                bool enable,
 533                                const struct intel_crtc_state *crtc_state,
 534                                const struct drm_connector_state *conn_state)
 535 {
 536         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 537         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 538         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 539         i915_reg_t reg = VIDEO_DIP_CTL;
 540         u32 val = I915_READ(reg);
 541         u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
 542
 543         assert_hdmi_port_disabled(intel_hdmi);
 544
 545         /* If the registers were not initialized yet, they might be zeroes,
 546          * which means we're selecting the AVI DIP and we're setting its
 547          * frequency to once. This seems to really confuse the HW and make
 548          * things stop working (the register spec says the AVI always needs to
 549          * be sent every VSync). So here we avoid writing to the register more
 550          * than we need and also explicitly select the AVI DIP and explicitly
 551          * set its frequency to every VSync. Avoiding to write it twice seems to
 552          * be enough to solve the problem, but being defensive shouldn't hurt us
 553          * either. */
 554         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 555
 556         if (!enable) {
 557                 if (!(val & VIDEO_DIP_ENABLE))
 558                         return;
 559                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 560                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 561                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 562                         return;
 563                 }
 564                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 565                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 566                 I915_WRITE(reg, val);
 567                 POSTING_READ(reg);
 568                 return;
 569         }
 570
 571         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 572                 if (val & VIDEO_DIP_ENABLE) {
 573                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 574                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 575                         return;
 576                 }
 577                 val &= ~VIDEO_DIP_PORT_MASK;
 578                 val |= port;
 579         }
 580
 581         val |= VIDEO_DIP_ENABLE;
 582         val &= ~(VIDEO_DIP_ENABLE_AVI |
 583                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 584
 585         I915_WRITE(reg, val);
 586         POSTING_READ(reg);
 587
 588         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 589         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 590         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 591 }
 592
 593 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
 594 {
 595         struct drm_connector *connector = conn_state->connector;
 596
 597         /*
 598          * HDMI cloning is only supported on g4x which doesn't
 599          * support deep color or GCP infoframes anyway so no
 600          * need to worry about multiple HDMI sinks here.
 601          */
 602
 603         return connector->display_info.bpc > 8;
 604 }
 605
 606 /*
 607  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 608  *
 609  * From HDMI specification 1.4a:
 610  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 611  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 612  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 613  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 614  *   phase of 0
 615  */
 616 static bool gcp_default_phase_possible(int pipe_bpp,
 617                                        const struct drm_display_mode *mode)
 618 {
 619         unsigned int pixels_per_group;
 620
 621         switch (pipe_bpp) {
 622         case 30:
 623                 /* 4 pixels in 5 clocks */
 624                 pixels_per_group = 4;
 625                 break;
 626         case 36:
 627                 /* 2 pixels in 3 clocks */
 628                 pixels_per_group = 2;
 629                 break;
 630         case 48:
 631                 /* 1 pixel in 2 clocks */
 632                 pixels_per_group = 1;
 633                 break;
 634         default:
 635                 /* phase information not relevant for 8bpc */
 636                 return false;
 637         }
 638
 639         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 640                 mode->crtc_htotal % pixels_per_group == 0 &&
 641                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 642                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 643                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 644                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 645                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 646                  mode->crtc_htotal/2 % pixels_per_group == 0);
 647 }
 648
 649 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder,
 650                                          const struct intel_crtc_state *crtc_state,
 651                                          const struct drm_connector_state *conn_state)
 652 {
 653         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 654         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 655         i915_reg_t reg;
 656         u32 val = 0;
 657
 658         if (HAS_DDI(dev_priv))
 659                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 660         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 661                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 662         else if (HAS_PCH_SPLIT(dev_priv))
 663                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 664         else
 665                 return false;
 666
 667         /* Indicate color depth whenever the sink supports deep color */
 668         if (hdmi_sink_is_deep_color(conn_state))
 669                 val |= GCP_COLOR_INDICATION;
 670
 671         /* Enable default_phase whenever the display mode is suitably aligned */
 672         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
 673                                        &crtc_state->base.adjusted_mode))
 674                 val |= GCP_DEFAULT_PHASE_ENABLE;
 675
 676         I915_WRITE(reg, val);
 677
 678         return val != 0;
 679 }
 680
 681 static void ibx_set_infoframes(struct drm_encoder *encoder,
 682                                bool enable,
 683                                const struct intel_crtc_state *crtc_state,
 684                                const struct drm_connector_state *conn_state)
 685 {
 686         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 687         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 688         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 689         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 690         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 691         u32 val = I915_READ(reg);
 692         u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
 693
 694         assert_hdmi_port_disabled(intel_hdmi);
 695
 696         /* See the big comment in g4x_set_infoframes() */
 697         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 698
 699         if (!enable) {
 700                 if (!(val & VIDEO_DIP_ENABLE))
 701                         return;
 702                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 703                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 704                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 705                 I915_WRITE(reg, val);
 706                 POSTING_READ(reg);
 707                 return;
 708         }
 709
 710         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 711                 WARN(val & VIDEO_DIP_ENABLE,
 712                      "DIP already enabled on port %c\n",
 713                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 714                 val &= ~VIDEO_DIP_PORT_MASK;
 715                 val |= port;
 716         }
 717
 718         val |= VIDEO_DIP_ENABLE;
 719         val &= ~(VIDEO_DIP_ENABLE_AVI |
 720                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 721                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 722
 723         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 724                 val |= VIDEO_DIP_ENABLE_GCP;
 725
 726         I915_WRITE(reg, val);
 727         POSTING_READ(reg);
 728
 729         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 730         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 731         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 732 }
 733
 734 static void cpt_set_infoframes(struct drm_encoder *encoder,
 735                                bool enable,
 736                                const struct intel_crtc_state *crtc_state,
 737                                const struct drm_connector_state *conn_state)
 738 {
 739         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 741         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 742         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 743         u32 val = I915_READ(reg);
 744
 745         assert_hdmi_port_disabled(intel_hdmi);
 746
 747         /* See the big comment in g4x_set_infoframes() */
 748         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 749
 750         if (!enable) {
 751                 if (!(val & VIDEO_DIP_ENABLE))
 752                         return;
 753                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 754                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 755                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 756                 I915_WRITE(reg, val);
 757                 POSTING_READ(reg);
 758                 return;
 759         }
 760
 761         /* Set both together, unset both together: see the spec. */
 762         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 763         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 764                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 765
 766         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 767                 val |= VIDEO_DIP_ENABLE_GCP;
 768
 769         I915_WRITE(reg, val);
 770         POSTING_READ(reg);
 771
 772         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 773         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 774         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 775 }
 776
 777 static void vlv_set_infoframes(struct drm_encoder *encoder,
 778                                bool enable,
 779                                const struct intel_crtc_state *crtc_state,
 780                                const struct drm_connector_state *conn_state)
 781 {
 782         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 783         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 784         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 785         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 786         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 787         u32 val = I915_READ(reg);
 788         u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
 789
 790         assert_hdmi_port_disabled(intel_hdmi);
 791
 792         /* See the big comment in g4x_set_infoframes() */
 793         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 794
 795         if (!enable) {
 796                 if (!(val & VIDEO_DIP_ENABLE))
 797                         return;
 798                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 799                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 800                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 801                 I915_WRITE(reg, val);
 802                 POSTING_READ(reg);
 803                 return;
 804         }
 805
 806         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 807                 WARN(val & VIDEO_DIP_ENABLE,
 808                      "DIP already enabled on port %c\n",
 809                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 810                 val &= ~VIDEO_DIP_PORT_MASK;
 811                 val |= port;
 812         }
 813
 814         val |= VIDEO_DIP_ENABLE;
 815         val &= ~(VIDEO_DIP_ENABLE_AVI |
 816                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 817                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 818
 819         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 820                 val |= VIDEO_DIP_ENABLE_GCP;
 821
 822         I915_WRITE(reg, val);
 823         POSTING_READ(reg);
 824
 825         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 826         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 827         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 828 }
 829
 830 static void hsw_set_infoframes(struct drm_encoder *encoder,
 831                                bool enable,
 832                                const struct intel_crtc_state *crtc_state,
 833                                const struct drm_connector_state *conn_state)
 834 {
 835         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 836         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 837         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
 838         u32 val = I915_READ(reg);
 839
 840         assert_hdmi_port_disabled(intel_hdmi);
 841
 842         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 843                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 844                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 845
 846         if (!enable) {
 847                 I915_WRITE(reg, val);
 848                 POSTING_READ(reg);
 849                 return;
 850         }
 851
 852         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 853                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
 854
 855         I915_WRITE(reg, val);
 856         POSTING_READ(reg);
 857
 858         intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 859         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 860         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 861 }
 862
 863 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
 864 {
 865         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
 866         struct i2c_adapter *adapter =
 867                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
 868
 869         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
 870                 return;
 871
 872         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
 873                       enable ? "Enabling" : "Disabling");
 874
 875         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
 876                                          adapter, enable);
 877 }
 878
 879 static void intel_hdmi_prepare(struct intel_encoder *encoder,
 880                                const struct intel_crtc_state *crtc_state)
 881 {
 882         struct drm_device *dev = encoder->base.dev;
 883         struct drm_i915_private *dev_priv = to_i915(dev);
 884         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 885         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 886         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 887         u32 hdmi_val;
 888
 889         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
 890
 891         hdmi_val = SDVO_ENCODING_HDMI;
 892         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
 893                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
 894         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 895                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 896         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 897                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 898
 899         if (crtc_state->pipe_bpp > 24)
 900                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 901         else
 902                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 903
 904         if (crtc_state->has_hdmi_sink)
 905                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 906
 907         if (HAS_PCH_CPT(dev_priv))
 908                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 909         else if (IS_CHERRYVIEW(dev_priv))
 910                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 911         else
 912                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 913
 914         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 915         POSTING_READ(intel_hdmi->hdmi_reg);
 916 }
 917
 918 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 919                                     enum pipe *pipe)
 920 {
 921         struct drm_device *dev = encoder->base.dev;
 922         struct drm_i915_private *dev_priv = to_i915(dev);
 923         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 924         u32 tmp;
 925         bool ret;
 926
 927         if (!intel_display_power_get_if_enabled(dev_priv,
 928                                                 encoder->power_domain))
 929                 return false;
 930
 931         ret = false;
 932
 933         tmp = I915_READ(intel_hdmi->hdmi_reg);
 934
 935         if (!(tmp & SDVO_ENABLE))
 936                 goto out;
 937
 938         if (HAS_PCH_CPT(dev_priv))
 939                 *pipe = PORT_TO_PIPE_CPT(tmp);
 940         else if (IS_CHERRYVIEW(dev_priv))
 941                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 942         else
 943                 *pipe = PORT_TO_PIPE(tmp);
 944
 945         ret = true;
 946
 947 out:
 948         intel_display_power_put(dev_priv, encoder->power_domain);
 949
 950         return ret;
 951 }
 952
 953 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 954                                   struct intel_crtc_state *pipe_config)
 955 {
 956         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 957         struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
 958         struct drm_device *dev = encoder->base.dev;
 959         struct drm_i915_private *dev_priv = to_i915(dev);
 960         u32 tmp, flags = 0;
 961         int dotclock;
 962
 963         pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
 964
 965         tmp = I915_READ(intel_hdmi->hdmi_reg);
 966
 967         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 968                 flags |= DRM_MODE_FLAG_PHSYNC;
 969         else
 970                 flags |= DRM_MODE_FLAG_NHSYNC;
 971
 972         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 973                 flags |= DRM_MODE_FLAG_PVSYNC;
 974         else
 975                 flags |= DRM_MODE_FLAG_NVSYNC;
 976
 977         if (tmp & HDMI_MODE_SELECT_HDMI)
 978                 pipe_config->has_hdmi_sink = true;
 979
 980         if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
 981                 pipe_config->has_infoframe = true;
 982
 983         if (tmp & SDVO_AUDIO_ENABLE)
 984                 pipe_config->has_audio = true;
 985
 986         if (!HAS_PCH_SPLIT(dev_priv) &&
 987             tmp & HDMI_COLOR_RANGE_16_235)
 988                 pipe_config->limited_color_range = true;
 989
 990         pipe_config->base.adjusted_mode.flags |= flags;
 991
 992         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 993                 dotclock = pipe_config->port_clock * 2 / 3;
 994         else
 995                 dotclock = pipe_config->port_clock;
 996
 997         if (pipe_config->pixel_multiplier)
 998                 dotclock /= pipe_config->pixel_multiplier;
 999
1000         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1001
1002         pipe_config->lane_count = 4;
1003 }
1004
1005 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1006                                     const struct intel_crtc_state *pipe_config,
1007                                     const struct drm_connector_state *conn_state)
1008 {
1009         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1010
1011         WARN_ON(!pipe_config->has_hdmi_sink);
1012         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1013                          pipe_name(crtc->pipe));
1014         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1015 }
1016
1017 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1018                             const struct intel_crtc_state *pipe_config,
1019                             const struct drm_connector_state *conn_state)
1020 {
1021         struct drm_device *dev = encoder->base.dev;
1022         struct drm_i915_private *dev_priv = to_i915(dev);
1023         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1024         u32 temp;
1025
1026         temp = I915_READ(intel_hdmi->hdmi_reg);
1027
1028         temp |= SDVO_ENABLE;
1029         if (pipe_config->has_audio)
1030                 temp |= SDVO_AUDIO_ENABLE;
1031
1032         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1033         POSTING_READ(intel_hdmi->hdmi_reg);
1034
1035         if (pipe_config->has_audio)
1036                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1037 }
1038
1039 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1040                             const struct intel_crtc_state *pipe_config,
1041                             const struct drm_connector_state *conn_state)
1042 {
1043         struct drm_device *dev = encoder->base.dev;
1044         struct drm_i915_private *dev_priv = to_i915(dev);
1045         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1046         u32 temp;
1047
1048         temp = I915_READ(intel_hdmi->hdmi_reg);
1049
1050         temp |= SDVO_ENABLE;
1051         if (pipe_config->has_audio)
1052                 temp |= SDVO_AUDIO_ENABLE;
1053
1054         /*
1055          * HW workaround, need to write this twice for issue
1056          * that may result in first write getting masked.
1057          */
1058         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1059         POSTING_READ(intel_hdmi->hdmi_reg);
1060         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1061         POSTING_READ(intel_hdmi->hdmi_reg);
1062
1063         /*
1064          * HW workaround, need to toggle enable bit off and on
1065          * for 12bpc with pixel repeat.
1066          *
1067          * FIXME: BSpec says this should be done at the end of
1068          * of the modeset sequence, so not sure if this isn't too soon.
1069          */
1070         if (pipe_config->pipe_bpp > 24 &&
1071             pipe_config->pixel_multiplier > 1) {
1072                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1073                 POSTING_READ(intel_hdmi->hdmi_reg);
1074
1075                 /*
1076                  * HW workaround, need to write this twice for issue
1077                  * that may result in first write getting masked.
1078                  */
1079                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1080                 POSTING_READ(intel_hdmi->hdmi_reg);
1081                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1082                 POSTING_READ(intel_hdmi->hdmi_reg);
1083         }
1084
1085         if (pipe_config->has_audio)
1086                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1087 }
1088
1089 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1090                             const struct intel_crtc_state *pipe_config,
1091                             const struct drm_connector_state *conn_state)
1092 {
1093         struct drm_device *dev = encoder->base.dev;
1094         struct drm_i915_private *dev_priv = to_i915(dev);
1095         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1096         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1097         enum pipe pipe = crtc->pipe;
1098         u32 temp;
1099
1100         temp = I915_READ(intel_hdmi->hdmi_reg);
1101
1102         temp |= SDVO_ENABLE;
1103         if (pipe_config->has_audio)
1104                 temp |= SDVO_AUDIO_ENABLE;
1105
1106         /*
1107          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1108          *
1109          * The procedure for 12bpc is as follows:
1110          * 1. disable HDMI clock gating
1111          * 2. enable HDMI with 8bpc
1112          * 3. enable HDMI with 12bpc
1113          * 4. enable HDMI clock gating
1114          */
1115
1116         if (pipe_config->pipe_bpp > 24) {
1117                 I915_WRITE(TRANS_CHICKEN1(pipe),
1118                            I915_READ(TRANS_CHICKEN1(pipe)) |
1119                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1120
1121                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1122                 temp |= SDVO_COLOR_FORMAT_8bpc;
1123         }
1124
1125         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1126         POSTING_READ(intel_hdmi->hdmi_reg);
1127
1128         if (pipe_config->pipe_bpp > 24) {
1129                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1130                 temp |= HDMI_COLOR_FORMAT_12bpc;
1131
1132                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1133                 POSTING_READ(intel_hdmi->hdmi_reg);
1134
1135                 I915_WRITE(TRANS_CHICKEN1(pipe),
1136                            I915_READ(TRANS_CHICKEN1(pipe)) &
1137                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1138         }
1139
1140         if (pipe_config->has_audio)
1141                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1142 }
1143
1144 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1145                             const struct intel_crtc_state *pipe_config,
1146                             const struct drm_connector_state *conn_state)
1147 {
1148 }
1149
1150 static void intel_disable_hdmi(struct intel_encoder *encoder,
1151                                const struct intel_crtc_state *old_crtc_state,
1152                                const struct drm_connector_state *old_conn_state)
1153 {
1154         struct drm_device *dev = encoder->base.dev;
1155         struct drm_i915_private *dev_priv = to_i915(dev);
1156         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1157         struct intel_digital_port *intel_dig_port =
1158                 hdmi_to_dig_port(intel_hdmi);
1159         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1160         u32 temp;
1161
1162         temp = I915_READ(intel_hdmi->hdmi_reg);
1163
1164         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1165         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1166         POSTING_READ(intel_hdmi->hdmi_reg);
1167
1168         /*
1169          * HW workaround for IBX, we need to move the port
1170          * to transcoder A after disabling it to allow the
1171          * matching DP port to be enabled on transcoder A.
1172          */
1173         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1174                 /*
1175                  * We get CPU/PCH FIFO underruns on the other pipe when
1176                  * doing the workaround. Sweep them under the rug.
1177                  */
1178                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1179                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1180
1181                 temp &= ~SDVO_PIPE_B_SELECT;
1182                 temp |= SDVO_ENABLE;
1183                 /*
1184                  * HW workaround, need to write this twice for issue
1185                  * that may result in first write getting masked.
1186                  */
1187                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1188                 POSTING_READ(intel_hdmi->hdmi_reg);
1189                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1190                 POSTING_READ(intel_hdmi->hdmi_reg);
1191
1192                 temp &= ~SDVO_ENABLE;
1193                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1194                 POSTING_READ(intel_hdmi->hdmi_reg);
1195
1196                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1197                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1198                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1199         }
1200
1201         intel_dig_port->set_infoframes(&encoder->base, false,
1202                                        old_crtc_state, old_conn_state);
1203
1204         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1205 }
1206
1207 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1208                              const struct intel_crtc_state *old_crtc_state,
1209                              const struct drm_connector_state *old_conn_state)
1210 {
1211         if (old_crtc_state->has_audio)
1212                 intel_audio_codec_disable(encoder,
1213                                           old_crtc_state, old_conn_state);
1214
1215         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1216 }
1217
1218 static void pch_disable_hdmi(struct intel_encoder *encoder,
1219                              const struct intel_crtc_state *old_crtc_state,
1220                              const struct drm_connector_state *old_conn_state)
1221 {
1222         if (old_crtc_state->has_audio)
1223                 intel_audio_codec_disable(encoder,
1224                                           old_crtc_state, old_conn_state);
1225 }
1226
1227 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1228                                   const struct intel_crtc_state *old_crtc_state,
1229                                   const struct drm_connector_state *old_conn_state)
1230 {
1231         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1232 }
1233
1234 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1235 {
1236         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1237         const struct ddi_vbt_port_info *info =
1238                 &dev_priv->vbt.ddi_port_info[encoder->port];
1239         int max_tmds_clock;
1240
1241         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1242                 max_tmds_clock = 594000;
1243         else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1244                 max_tmds_clock = 300000;
1245         else if (INTEL_GEN(dev_priv) >= 5)
1246                 max_tmds_clock = 225000;
1247         else
1248                 max_tmds_clock = 165000;
1249
1250         if (info->max_tmds_clock)
1251                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1252
1253         return max_tmds_clock;
1254 }
1255
1256 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1257                                  bool respect_downstream_limits,
1258                                  bool force_dvi)
1259 {
1260         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1261         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1262
1263         if (respect_downstream_limits) {
1264                 struct intel_connector *connector = hdmi->attached_connector;
1265                 const struct drm_display_info *info = &connector->base.display_info;
1266
1267                 if (hdmi->dp_dual_mode.max_tmds_clock)
1268                         max_tmds_clock = min(max_tmds_clock,
1269                                              hdmi->dp_dual_mode.max_tmds_clock);
1270
1271                 if (info->max_tmds_clock)
1272                         max_tmds_clock = min(max_tmds_clock,
1273                                              info->max_tmds_clock);
1274                 else if (!hdmi->has_hdmi_sink || force_dvi)
1275                         max_tmds_clock = min(max_tmds_clock, 165000);
1276         }
1277
1278         return max_tmds_clock;
1279 }
1280
1281 static enum drm_mode_status
1282 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1283                       int clock, bool respect_downstream_limits,
1284                       bool force_dvi)
1285 {
1286         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1287
1288         if (clock < 25000)
1289                 return MODE_CLOCK_LOW;
1290         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1291                 return MODE_CLOCK_HIGH;
1292
1293         /* BXT DPLL can't generate 223-240 MHz */
1294         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1295                 return MODE_CLOCK_RANGE;
1296
1297         /* CHV DPLL can't generate 216-240 MHz */
1298         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1299                 return MODE_CLOCK_RANGE;
1300
1301         return MODE_OK;
1302 }
1303
1304 static enum drm_mode_status
1305 intel_hdmi_mode_valid(struct drm_connector *connector,
1306                       struct drm_display_mode *mode)
1307 {
1308         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1309         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1310         struct drm_i915_private *dev_priv = to_i915(dev);
1311         enum drm_mode_status status;
1312         int clock;
1313         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1314         bool force_dvi =
1315                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1316
1317         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1318                 return MODE_NO_DBLESCAN;
1319
1320         clock = mode->clock;
1321
1322         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1323                 clock *= 2;
1324
1325         if (clock > max_dotclk)
1326                 return MODE_CLOCK_HIGH;
1327
1328         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1329                 clock *= 2;
1330
1331         if (drm_mode_is_420_only(&connector->display_info, mode))
1332                 clock /= 2;
1333
1334         /* check if we can do 8bpc */
1335         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1336
1337         /* if we can't do 8bpc we may still be able to do 12bpc */
1338         if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi)
1339                 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi);
1340
1341         return status;
1342 }
1343
1344 static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
1345 {
1346         struct drm_i915_private *dev_priv =
1347                 to_i915(crtc_state->base.crtc->dev);
1348         struct drm_atomic_state *state = crtc_state->base.state;
1349         struct drm_connector_state *connector_state;
1350         struct drm_connector *connector;
1351         int i;
1352
1353         if (HAS_GMCH_DISPLAY(dev_priv))
1354                 return false;
1355
1356         if (crtc_state->pipe_bpp <= 8*3)
1357                 return false;
1358
1359         if (!crtc_state->has_hdmi_sink)
1360                 return false;
1361
1362         /*
1363          * HDMI 12bpc affects the clocks, so it's only possible
1364          * when not cloning with other encoder types.
1365          */
1366         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1367                 return false;
1368
1369         for_each_new_connector_in_state(state, connector, connector_state, i) {
1370                 const struct drm_display_info *info = &connector->display_info;
1371
1372                 if (connector_state->crtc != crtc_state->base.crtc)
1373                         continue;
1374
1375                 if (crtc_state->ycbcr420) {
1376                         const struct drm_hdmi_info *hdmi = &info->hdmi;
1377
1378                         if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
1379                                 return false;
1380                 } else {
1381                         if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36))
1382                                 return false;
1383                 }
1384         }
1385
1386         /* Display WA #1139: glk */
1387         if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1388             crtc_state->base.adjusted_mode.htotal > 5460)
1389                 return false;
1390
1391         return true;
1392 }
1393
1394 static bool
1395 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1396                            struct intel_crtc_state *config,
1397                            int *clock_12bpc, int *clock_8bpc)
1398 {
1399         struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1400
1401         if (!connector->ycbcr_420_allowed) {
1402                 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1403                 return false;
1404         }
1405
1406         /* YCBCR420 TMDS rate requirement is half the pixel clock */
1407         config->port_clock /= 2;
1408         *clock_12bpc /= 2;
1409         *clock_8bpc /= 2;
1410         config->ycbcr420 = true;
1411
1412         /* YCBCR 420 output conversion needs a scaler */
1413         if (skl_update_scaler_crtc(config)) {
1414                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1415                 return false;
1416         }
1417
1418         intel_pch_panel_fitting(intel_crtc, config,
1419                                 DRM_MODE_SCALE_FULLSCREEN);
1420
1421         return true;
1422 }
1423
1424 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1425                                struct intel_crtc_state *pipe_config,
1426                                struct drm_connector_state *conn_state)
1427 {
1428         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1429         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1430         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1431         struct drm_connector *connector = conn_state->connector;
1432         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
1433         struct intel_digital_connector_state *intel_conn_state =
1434                 to_intel_digital_connector_state(conn_state);
1435         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1436         int clock_12bpc = clock_8bpc * 3 / 2;
1437         int desired_bpp;
1438         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1439
1440         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1441
1442         if (pipe_config->has_hdmi_sink)
1443                 pipe_config->has_infoframe = true;
1444
1445         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1446                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1447                 pipe_config->limited_color_range =
1448                         pipe_config->has_hdmi_sink &&
1449                         drm_default_rgb_quant_range(adjusted_mode) ==
1450                         HDMI_QUANTIZATION_RANGE_LIMITED;
1451         } else {
1452                 pipe_config->limited_color_range =
1453                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1454         }
1455
1456         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1457                 pipe_config->pixel_multiplier = 2;
1458                 clock_8bpc *= 2;
1459                 clock_12bpc *= 2;
1460         }
1461
1462         if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
1463                 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
1464                                                 &clock_12bpc, &clock_8bpc)) {
1465                         DRM_ERROR("Can't support YCBCR420 output\n");
1466                         return false;
1467                 }
1468         }
1469
1470         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1471                 pipe_config->has_pch_encoder = true;
1472
1473         if (pipe_config->has_hdmi_sink) {
1474                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1475                         pipe_config->has_audio = intel_hdmi->has_audio;
1476                 else
1477                         pipe_config->has_audio =
1478                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1479         }
1480
1481         /*
1482          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1483          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1484          * outputs. We also need to check that the higher clock still fits
1485          * within limits.
1486          */
1487         if (hdmi_12bpc_possible(pipe_config) &&
1488             hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK) {
1489                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1490                 desired_bpp = 12*3;
1491
1492                 /* Need to adjust the port link by 1.5x for 12bpc. */
1493                 pipe_config->port_clock = clock_12bpc;
1494         } else {
1495                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1496                 desired_bpp = 8*3;
1497
1498                 pipe_config->port_clock = clock_8bpc;
1499         }
1500
1501         if (!pipe_config->bw_constrained) {
1502                 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1503                 pipe_config->pipe_bpp = desired_bpp;
1504         }
1505
1506         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1507                                   false, force_dvi) != MODE_OK) {
1508                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1509                 return false;
1510         }
1511
1512         /* Set user selected PAR to incoming mode's member */
1513         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1514
1515         pipe_config->lane_count = 4;
1516
1517         if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
1518                                            IS_GEMINILAKE(dev_priv))) {
1519                 if (scdc->scrambling.low_rates)
1520                         pipe_config->hdmi_scrambling = true;
1521
1522                 if (pipe_config->port_clock > 340000) {
1523                         pipe_config->hdmi_scrambling = true;
1524                         pipe_config->hdmi_high_tmds_clock_ratio = true;
1525                 }
1526         }
1527
1528         return true;
1529 }
1530
1531 static void
1532 intel_hdmi_unset_edid(struct drm_connector *connector)
1533 {
1534         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1535
1536         intel_hdmi->has_hdmi_sink = false;
1537         intel_hdmi->has_audio = false;
1538         intel_hdmi->rgb_quant_range_selectable = false;
1539
1540         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1541         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1542
1543         kfree(to_intel_connector(connector)->detect_edid);
1544         to_intel_connector(connector)->detect_edid = NULL;
1545 }
1546
1547 static void
1548 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1549 {
1550         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1551         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1552         enum port port = hdmi_to_dig_port(hdmi)->base.port;
1553         struct i2c_adapter *adapter =
1554                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1555         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1556
1557         /*
1558          * Type 1 DVI adaptors are not required to implement any
1559          * registers, so we can't always detect their presence.
1560          * Ideally we should be able to check the state of the
1561          * CONFIG1 pin, but no such luck on our hardware.
1562          *
1563          * The only method left to us is to check the VBT to see
1564          * if the port is a dual mode capable DP port. But let's
1565          * only do that when we sucesfully read the EDID, to avoid
1566          * confusing log messages about DP dual mode adaptors when
1567          * there's nothing connected to the port.
1568          */
1569         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1570                 if (has_edid &&
1571                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1572                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1573                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1574                 } else {
1575                         type = DRM_DP_DUAL_MODE_NONE;
1576                 }
1577         }
1578
1579         if (type == DRM_DP_DUAL_MODE_NONE)
1580                 return;
1581
1582         hdmi->dp_dual_mode.type = type;
1583         hdmi->dp_dual_mode.max_tmds_clock =
1584                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1585
1586         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1587                       drm_dp_get_dual_mode_type_name(type),
1588                       hdmi->dp_dual_mode.max_tmds_clock);
1589 }
1590
1591 static bool
1592 intel_hdmi_set_edid(struct drm_connector *connector)
1593 {
1594         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1595         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1596         struct edid *edid;
1597         bool connected = false;
1598
1599         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1600
1601         edid = drm_get_edid(connector,
1602                             intel_gmbus_get_adapter(dev_priv,
1603                             intel_hdmi->ddc_bus));
1604
1605         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1606
1607         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1608
1609         to_intel_connector(connector)->detect_edid = edid;
1610         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1611                 intel_hdmi->rgb_quant_range_selectable =
1612                         drm_rgb_quant_range_selectable(edid);
1613
1614                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1615                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1616
1617                 connected = true;
1618         }
1619
1620         return connected;
1621 }
1622
1623 static enum drm_connector_status
1624 intel_hdmi_detect(struct drm_connector *connector, bool force)
1625 {
1626         enum drm_connector_status status;
1627         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1628
1629         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1630                       connector->base.id, connector->name);
1631
1632         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1633
1634         intel_hdmi_unset_edid(connector);
1635
1636         if (intel_hdmi_set_edid(connector))
1637                 status = connector_status_connected;
1638         else
1639                 status = connector_status_disconnected;
1640
1641         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1642
1643         return status;
1644 }
1645
1646 static void
1647 intel_hdmi_force(struct drm_connector *connector)
1648 {
1649         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1650                       connector->base.id, connector->name);
1651
1652         intel_hdmi_unset_edid(connector);
1653
1654         if (connector->status != connector_status_connected)
1655                 return;
1656
1657         intel_hdmi_set_edid(connector);
1658 }
1659
1660 static int intel_hdmi_get_modes(struct drm_connector *connector)
1661 {
1662         struct edid *edid;
1663
1664         edid = to_intel_connector(connector)->detect_edid;
1665         if (edid == NULL)
1666                 return 0;
1667
1668         return intel_connector_update_modes(connector, edid);
1669 }
1670
1671 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1672                                   const struct intel_crtc_state *pipe_config,
1673                                   const struct drm_connector_state *conn_state)
1674 {
1675         struct intel_digital_port *intel_dig_port =
1676                 enc_to_dig_port(&encoder->base);
1677
1678         intel_hdmi_prepare(encoder, pipe_config);
1679
1680         intel_dig_port->set_infoframes(&encoder->base,
1681                                        pipe_config->has_infoframe,
1682                                        pipe_config, conn_state);
1683 }
1684
1685 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1686                                 const struct intel_crtc_state *pipe_config,
1687                                 const struct drm_connector_state *conn_state)
1688 {
1689         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1690         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1691
1692         vlv_phy_pre_encoder_enable(encoder, pipe_config);
1693
1694         /* HDMI 1.0V-2dB */
1695         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1696                                  0x2b247878);
1697
1698         dport->set_infoframes(&encoder->base,
1699                               pipe_config->has_infoframe,
1700                               pipe_config, conn_state);
1701
1702         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1703
1704         vlv_wait_port_ready(dev_priv, dport, 0x0);
1705 }
1706
1707 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1708                                     const struct intel_crtc_state *pipe_config,
1709                                     const struct drm_connector_state *conn_state)
1710 {
1711         intel_hdmi_prepare(encoder, pipe_config);
1712
1713         vlv_phy_pre_pll_enable(encoder, pipe_config);
1714 }
1715
1716 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1717                                     const struct intel_crtc_state *pipe_config,
1718                                     const struct drm_connector_state *conn_state)
1719 {
1720         intel_hdmi_prepare(encoder, pipe_config);
1721
1722         chv_phy_pre_pll_enable(encoder, pipe_config);
1723 }
1724
1725 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
1726                                       const struct intel_crtc_state *old_crtc_state,
1727                                       const struct drm_connector_state *old_conn_state)
1728 {
1729         chv_phy_post_pll_disable(encoder, old_crtc_state);
1730 }
1731
1732 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
1733                                   const struct intel_crtc_state *old_crtc_state,
1734                                   const struct drm_connector_state *old_conn_state)
1735 {
1736         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1737         vlv_phy_reset_lanes(encoder, old_crtc_state);
1738 }
1739
1740 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
1741                                   const struct intel_crtc_state *old_crtc_state,
1742                                   const struct drm_connector_state *old_conn_state)
1743 {
1744         struct drm_device *dev = encoder->base.dev;
1745         struct drm_i915_private *dev_priv = to_i915(dev);
1746
1747         mutex_lock(&dev_priv->sb_lock);
1748
1749         /* Assert data lane reset */
1750         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
1751
1752         mutex_unlock(&dev_priv->sb_lock);
1753 }
1754
1755 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
1756                                 const struct intel_crtc_state *pipe_config,
1757                                 const struct drm_connector_state *conn_state)
1758 {
1759         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1760         struct drm_device *dev = encoder->base.dev;
1761         struct drm_i915_private *dev_priv = to_i915(dev);
1762
1763         chv_phy_pre_encoder_enable(encoder, pipe_config);
1764
1765         /* FIXME: Program the support xxx V-dB */
1766         /* Use 800mV-0dB */
1767         chv_set_phy_signal_level(encoder, 128, 102, false);
1768
1769         dport->set_infoframes(&encoder->base,
1770                               pipe_config->has_infoframe,
1771                               pipe_config, conn_state);
1772
1773         g4x_enable_hdmi(encoder, pipe_config, conn_state);
1774
1775         vlv_wait_port_ready(dev_priv, dport, 0x0);
1776
1777         /* Second common lane will stay alive on its own now */
1778         chv_phy_release_cl2_override(encoder);
1779 }
1780
1781 static void intel_hdmi_destroy(struct drm_connector *connector)
1782 {
1783         kfree(to_intel_connector(connector)->detect_edid);
1784         drm_connector_cleanup(connector);
1785         kfree(connector);
1786 }
1787
1788 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1789         .detect = intel_hdmi_detect,
1790         .force = intel_hdmi_force,
1791         .fill_modes = drm_helper_probe_single_connector_modes,
1792         .atomic_get_property = intel_digital_connector_atomic_get_property,
1793         .atomic_set_property = intel_digital_connector_atomic_set_property,
1794         .late_register = intel_connector_register,
1795         .early_unregister = intel_connector_unregister,
1796         .destroy = intel_hdmi_destroy,
1797         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1798         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1799 };
1800
1801 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1802         .get_modes = intel_hdmi_get_modes,
1803         .mode_valid = intel_hdmi_mode_valid,
1804         .atomic_check = intel_digital_connector_atomic_check,
1805 };
1806
1807 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1808         .destroy = intel_encoder_destroy,
1809 };
1810
1811 static void
1812 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1813 {
1814         intel_attach_force_audio_property(connector);
1815         intel_attach_broadcast_rgb_property(connector);
1816         intel_attach_aspect_ratio_property(connector);
1817         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1818 }
1819
1820 /*
1821  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
1822  * @encoder: intel_encoder
1823  * @connector: drm_connector
1824  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
1825  *  or reset the high tmds clock ratio for scrambling
1826  * @scrambling: bool to Indicate if the function needs to set or reset
1827  *  sink scrambling
1828  *
1829  * This function handles scrambling on HDMI 2.0 capable sinks.
1830  * If required clock rate is > 340 Mhz && scrambling is supported by sink
1831  * it enables scrambling. This should be called before enabling the HDMI
1832  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
1833  * detect a scrambled clock within 100 ms.
1834  */
1835 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1836                                        struct drm_connector *connector,
1837                                        bool high_tmds_clock_ratio,
1838                                        bool scrambling)
1839 {
1840         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1841         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1842         struct drm_scrambling *sink_scrambling =
1843                                 &connector->display_info.hdmi.scdc.scrambling;
1844         struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv,
1845                                                            intel_hdmi->ddc_bus);
1846         bool ret;
1847
1848         if (!sink_scrambling->supported)
1849                 return;
1850
1851         DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n",
1852                       encoder->base.name, connector->name);
1853
1854         /* Set TMDS bit clock ratio to 1/40 or 1/10 */
1855         ret = drm_scdc_set_high_tmds_clock_ratio(adptr, high_tmds_clock_ratio);
1856         if (!ret) {
1857                 DRM_ERROR("Set TMDS ratio failed\n");
1858                 return;
1859         }
1860
1861         /* Enable/disable sink scrambling */
1862         ret = drm_scdc_set_scrambling(adptr, scrambling);
1863         if (!ret) {
1864                 DRM_ERROR("Set sink scrambling failed\n");
1865                 return;
1866         }
1867
1868         DRM_DEBUG_KMS("sink scrambling handled\n");
1869 }
1870
1871 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
1872 {
1873         u8 ddc_pin;
1874
1875         switch (port) {
1876         case PORT_B:
1877                 ddc_pin = GMBUS_PIN_DPB;
1878                 break;
1879         case PORT_C:
1880                 ddc_pin = GMBUS_PIN_DPC;
1881                 break;
1882         case PORT_D:
1883                 ddc_pin = GMBUS_PIN_DPD_CHV;
1884                 break;
1885         default:
1886                 MISSING_CASE(port);
1887                 ddc_pin = GMBUS_PIN_DPB;
1888                 break;
1889         }
1890         return ddc_pin;
1891 }
1892
1893 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
1894 {
1895         u8 ddc_pin;
1896
1897         switch (port) {
1898         case PORT_B:
1899                 ddc_pin = GMBUS_PIN_1_BXT;
1900                 break;
1901         case PORT_C:
1902                 ddc_pin = GMBUS_PIN_2_BXT;
1903                 break;
1904         default:
1905                 MISSING_CASE(port);
1906                 ddc_pin = GMBUS_PIN_1_BXT;
1907                 break;
1908         }
1909         return ddc_pin;
1910 }
1911
1912 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
1913                               enum port port)
1914 {
1915         u8 ddc_pin;
1916
1917         switch (port) {
1918         case PORT_B:
1919                 ddc_pin = GMBUS_PIN_1_BXT;
1920                 break;
1921         case PORT_C:
1922                 ddc_pin = GMBUS_PIN_2_BXT;
1923                 break;
1924         case PORT_D:
1925                 ddc_pin = GMBUS_PIN_4_CNP;
1926                 break;
1927         default:
1928                 MISSING_CASE(port);
1929                 ddc_pin = GMBUS_PIN_1_BXT;
1930                 break;
1931         }
1932         return ddc_pin;
1933 }
1934
1935 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
1936                               enum port port)
1937 {
1938         u8 ddc_pin;
1939
1940         switch (port) {
1941         case PORT_B:
1942                 ddc_pin = GMBUS_PIN_DPB;
1943                 break;
1944         case PORT_C:
1945                 ddc_pin = GMBUS_PIN_DPC;
1946                 break;
1947         case PORT_D:
1948                 ddc_pin = GMBUS_PIN_DPD;
1949                 break;
1950         default:
1951                 MISSING_CASE(port);
1952                 ddc_pin = GMBUS_PIN_DPB;
1953                 break;
1954         }
1955         return ddc_pin;
1956 }
1957
1958 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
1959                              enum port port)
1960 {
1961         const struct ddi_vbt_port_info *info =
1962                 &dev_priv->vbt.ddi_port_info[port];
1963         u8 ddc_pin;
1964
1965         if (info->alternate_ddc_pin) {
1966                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
1967                               info->alternate_ddc_pin, port_name(port));
1968                 return info->alternate_ddc_pin;
1969         }
1970
1971         if (IS_CHERRYVIEW(dev_priv))
1972                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
1973         else if (IS_GEN9_LP(dev_priv))
1974                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
1975         else if (HAS_PCH_CNP(dev_priv))
1976                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
1977         else
1978                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
1979
1980         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
1981                       ddc_pin, port_name(port));
1982
1983         return ddc_pin;
1984 }
1985
1986 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
1987 {
1988         struct drm_i915_private *dev_priv =
1989                 to_i915(intel_dig_port->base.base.dev);
1990
1991         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1992                 intel_dig_port->write_infoframe = vlv_write_infoframe;
1993                 intel_dig_port->set_infoframes = vlv_set_infoframes;
1994                 intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
1995         } else if (IS_G4X(dev_priv)) {
1996                 intel_dig_port->write_infoframe = g4x_write_infoframe;
1997                 intel_dig_port->set_infoframes = g4x_set_infoframes;
1998                 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
1999         } else if (HAS_DDI(dev_priv)) {
2000                 intel_dig_port->write_infoframe = hsw_write_infoframe;
2001                 intel_dig_port->set_infoframes = hsw_set_infoframes;
2002                 intel_dig_port->infoframe_enabled = hsw_infoframe_enabled;
2003         } else if (HAS_PCH_IBX(dev_priv)) {
2004                 intel_dig_port->write_infoframe = ibx_write_infoframe;
2005                 intel_dig_port->set_infoframes = ibx_set_infoframes;
2006                 intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
2007         } else {
2008                 intel_dig_port->write_infoframe = cpt_write_infoframe;
2009                 intel_dig_port->set_infoframes = cpt_set_infoframes;
2010                 intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
2011         }
2012 }
2013
2014 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2015                                struct intel_connector *intel_connector)
2016 {
2017         struct drm_connector *connector = &intel_connector->base;
2018         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2019         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2020         struct drm_device *dev = intel_encoder->base.dev;
2021         struct drm_i915_private *dev_priv = to_i915(dev);
2022         enum port port = intel_encoder->port;
2023
2024         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2025                       port_name(port));
2026
2027         if (WARN(intel_dig_port->max_lanes < 4,
2028                  "Not enough lanes (%d) for HDMI on port %c\n",
2029                  intel_dig_port->max_lanes, port_name(port)))
2030                 return;
2031
2032         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2033                            DRM_MODE_CONNECTOR_HDMIA);
2034         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2035
2036         connector->interlace_allowed = 1;
2037         connector->doublescan_allowed = 0;
2038         connector->stereo_allowed = 1;
2039
2040         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2041                 connector->ycbcr_420_allowed = true;
2042
2043         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2044
2045         if (WARN_ON(port == PORT_A))
2046                 return;
2047         intel_encoder->hpd_pin = intel_hpd_pin(port);
2048
2049         if (HAS_DDI(dev_priv))
2050                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2051         else
2052                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2053
2054         intel_hdmi_add_properties(intel_hdmi, connector);
2055
2056         intel_connector_attach_encoder(intel_connector, intel_encoder);
2057         intel_hdmi->attached_connector = intel_connector;
2058
2059         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2060          * 0xd.  Failure to do so will result in spurious interrupts being
2061          * generated on the port when a cable is not attached.
2062          */
2063         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
2064                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2065                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2066         }
2067 }
2068
2069 void intel_hdmi_init(struct drm_i915_private *dev_priv,
2070                      i915_reg_t hdmi_reg, enum port port)
2071 {
2072         struct intel_digital_port *intel_dig_port;
2073         struct intel_encoder *intel_encoder;
2074         struct intel_connector *intel_connector;
2075
2076         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2077         if (!intel_dig_port)
2078                 return;
2079
2080         intel_connector = intel_connector_alloc();
2081         if (!intel_connector) {
2082                 kfree(intel_dig_port);
2083                 return;
2084         }
2085
2086         intel_encoder = &intel_dig_port->base;
2087
2088         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2089                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2090                          "HDMI %c", port_name(port));
2091
2092         intel_encoder->compute_config = intel_hdmi_compute_config;
2093         if (HAS_PCH_SPLIT(dev_priv)) {
2094                 intel_encoder->disable = pch_disable_hdmi;
2095                 intel_encoder->post_disable = pch_post_disable_hdmi;
2096         } else {
2097                 intel_encoder->disable = g4x_disable_hdmi;
2098         }
2099         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2100         intel_encoder->get_config = intel_hdmi_get_config;
2101         if (IS_CHERRYVIEW(dev_priv)) {
2102                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2103                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2104                 intel_encoder->enable = vlv_enable_hdmi;
2105                 intel_encoder->post_disable = chv_hdmi_post_disable;
2106                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2107         } else if (IS_VALLEYVIEW(dev_priv)) {
2108                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2109                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2110                 intel_encoder->enable = vlv_enable_hdmi;
2111                 intel_encoder->post_disable = vlv_hdmi_post_disable;
2112         } else {
2113                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2114                 if (HAS_PCH_CPT(dev_priv))
2115                         intel_encoder->enable = cpt_enable_hdmi;
2116                 else if (HAS_PCH_IBX(dev_priv))
2117                         intel_encoder->enable = ibx_enable_hdmi;
2118                 else
2119                         intel_encoder->enable = g4x_enable_hdmi;
2120         }
2121
2122         intel_encoder->type = INTEL_OUTPUT_HDMI;
2123         intel_encoder->power_domain = intel_port_to_power_domain(port);
2124         intel_encoder->port = port;
2125         if (IS_CHERRYVIEW(dev_priv)) {
2126                 if (port == PORT_D)
2127                         intel_encoder->crtc_mask = 1 << 2;
2128                 else
2129                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2130         } else {
2131                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2132         }
2133         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2134         /*
2135          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2136          * to work on real hardware. And since g4x can send infoframes to
2137          * only one port anyway, nothing is lost by allowing it.
2138          */
2139         if (IS_G4X(dev_priv))
2140                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2141
2142         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2143         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2144         intel_dig_port->max_lanes = 4;
2145
2146         intel_infoframe_init(intel_dig_port);
2147
2148         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2149 }