2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_hdcp.h>
37 #include <drm/drm_scdc_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
40 #include <drm/intel_lpe_audio.h>
43 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
45 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
49 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
51 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
52 struct drm_i915_private *dev_priv = to_i915(dev);
55 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
57 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
58 "HDMI port enabled, expecting disabled\n");
62 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
63 enum transcoder cpu_transcoder)
65 WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
66 TRANS_DDI_FUNC_ENABLE,
67 "HDMI transcoder function enabled, expecting disabled\n");
70 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
72 struct intel_digital_port *intel_dig_port =
73 container_of(encoder, struct intel_digital_port, base.base);
74 return &intel_dig_port->hdmi;
77 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
79 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
82 static u32 g4x_infoframe_index(unsigned int type)
85 case HDMI_INFOFRAME_TYPE_AVI:
86 return VIDEO_DIP_SELECT_AVI;
87 case HDMI_INFOFRAME_TYPE_SPD:
88 return VIDEO_DIP_SELECT_SPD;
89 case HDMI_INFOFRAME_TYPE_VENDOR:
90 return VIDEO_DIP_SELECT_VENDOR;
97 static u32 g4x_infoframe_enable(unsigned int type)
100 case HDMI_INFOFRAME_TYPE_AVI:
101 return VIDEO_DIP_ENABLE_AVI;
102 case HDMI_INFOFRAME_TYPE_SPD:
103 return VIDEO_DIP_ENABLE_SPD;
104 case HDMI_INFOFRAME_TYPE_VENDOR:
105 return VIDEO_DIP_ENABLE_VENDOR;
112 static u32 hsw_infoframe_enable(unsigned int type)
116 return VIDEO_DIP_ENABLE_VSC_HSW;
118 return VDIP_ENABLE_PPS;
119 case HDMI_INFOFRAME_TYPE_AVI:
120 return VIDEO_DIP_ENABLE_AVI_HSW;
121 case HDMI_INFOFRAME_TYPE_SPD:
122 return VIDEO_DIP_ENABLE_SPD_HSW;
123 case HDMI_INFOFRAME_TYPE_VENDOR:
124 return VIDEO_DIP_ENABLE_VS_HSW;
132 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
133 enum transcoder cpu_transcoder,
139 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
141 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
142 case HDMI_INFOFRAME_TYPE_AVI:
143 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
144 case HDMI_INFOFRAME_TYPE_SPD:
145 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
146 case HDMI_INFOFRAME_TYPE_VENDOR:
147 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
150 return INVALID_MMIO_REG;
154 static int hsw_dip_data_size(unsigned int type)
158 return VIDEO_DIP_VSC_DATA_SIZE;
160 return VIDEO_DIP_PPS_DATA_SIZE;
162 return VIDEO_DIP_DATA_SIZE;
166 static void g4x_write_infoframe(struct intel_encoder *encoder,
167 const struct intel_crtc_state *crtc_state,
169 const void *frame, ssize_t len)
171 const u32 *data = frame;
172 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
173 u32 val = I915_READ(VIDEO_DIP_CTL);
176 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
178 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
179 val |= g4x_infoframe_index(type);
181 val &= ~g4x_infoframe_enable(type);
183 I915_WRITE(VIDEO_DIP_CTL, val);
186 for (i = 0; i < len; i += 4) {
187 I915_WRITE(VIDEO_DIP_DATA, *data);
190 /* Write every possible data byte to force correct ECC calculation. */
191 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
192 I915_WRITE(VIDEO_DIP_DATA, 0);
195 val |= g4x_infoframe_enable(type);
196 val &= ~VIDEO_DIP_FREQ_MASK;
197 val |= VIDEO_DIP_FREQ_VSYNC;
199 I915_WRITE(VIDEO_DIP_CTL, val);
200 POSTING_READ(VIDEO_DIP_CTL);
203 static bool g4x_infoframe_enabled(struct intel_encoder *encoder,
204 const struct intel_crtc_state *pipe_config)
206 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
207 u32 val = I915_READ(VIDEO_DIP_CTL);
209 if ((val & VIDEO_DIP_ENABLE) == 0)
212 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
215 return val & (VIDEO_DIP_ENABLE_AVI |
216 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
219 static void ibx_write_infoframe(struct intel_encoder *encoder,
220 const struct intel_crtc_state *crtc_state,
222 const void *frame, ssize_t len)
224 const u32 *data = frame;
225 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
227 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
228 u32 val = I915_READ(reg);
231 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
233 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
234 val |= g4x_infoframe_index(type);
236 val &= ~g4x_infoframe_enable(type);
238 I915_WRITE(reg, val);
241 for (i = 0; i < len; i += 4) {
242 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
245 /* Write every possible data byte to force correct ECC calculation. */
246 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
247 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
250 val |= g4x_infoframe_enable(type);
251 val &= ~VIDEO_DIP_FREQ_MASK;
252 val |= VIDEO_DIP_FREQ_VSYNC;
254 I915_WRITE(reg, val);
258 static bool ibx_infoframe_enabled(struct intel_encoder *encoder,
259 const struct intel_crtc_state *pipe_config)
261 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
262 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
263 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
264 u32 val = I915_READ(reg);
266 if ((val & VIDEO_DIP_ENABLE) == 0)
269 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
272 return val & (VIDEO_DIP_ENABLE_AVI |
273 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
274 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
277 static void cpt_write_infoframe(struct intel_encoder *encoder,
278 const struct intel_crtc_state *crtc_state,
280 const void *frame, ssize_t len)
282 const u32 *data = frame;
283 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
285 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
286 u32 val = I915_READ(reg);
289 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
291 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
292 val |= g4x_infoframe_index(type);
294 /* The DIP control register spec says that we need to update the AVI
295 * infoframe without clearing its enable bit */
296 if (type != HDMI_INFOFRAME_TYPE_AVI)
297 val &= ~g4x_infoframe_enable(type);
299 I915_WRITE(reg, val);
302 for (i = 0; i < len; i += 4) {
303 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
306 /* Write every possible data byte to force correct ECC calculation. */
307 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
308 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
311 val |= g4x_infoframe_enable(type);
312 val &= ~VIDEO_DIP_FREQ_MASK;
313 val |= VIDEO_DIP_FREQ_VSYNC;
315 I915_WRITE(reg, val);
319 static bool cpt_infoframe_enabled(struct intel_encoder *encoder,
320 const struct intel_crtc_state *pipe_config)
322 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
323 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
324 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
326 if ((val & VIDEO_DIP_ENABLE) == 0)
329 return val & (VIDEO_DIP_ENABLE_AVI |
330 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
331 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
334 static void vlv_write_infoframe(struct intel_encoder *encoder,
335 const struct intel_crtc_state *crtc_state,
337 const void *frame, ssize_t len)
339 const u32 *data = frame;
340 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
342 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
343 u32 val = I915_READ(reg);
346 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
348 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
349 val |= g4x_infoframe_index(type);
351 val &= ~g4x_infoframe_enable(type);
353 I915_WRITE(reg, val);
356 for (i = 0; i < len; i += 4) {
357 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
360 /* Write every possible data byte to force correct ECC calculation. */
361 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
362 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
365 val |= g4x_infoframe_enable(type);
366 val &= ~VIDEO_DIP_FREQ_MASK;
367 val |= VIDEO_DIP_FREQ_VSYNC;
369 I915_WRITE(reg, val);
373 static bool vlv_infoframe_enabled(struct intel_encoder *encoder,
374 const struct intel_crtc_state *pipe_config)
376 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
377 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
378 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
380 if ((val & VIDEO_DIP_ENABLE) == 0)
383 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
386 return val & (VIDEO_DIP_ENABLE_AVI |
387 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
388 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
391 static void hsw_write_infoframe(struct intel_encoder *encoder,
392 const struct intel_crtc_state *crtc_state,
394 const void *frame, ssize_t len)
396 const u32 *data = frame;
397 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
398 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
399 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
402 u32 val = I915_READ(ctl_reg);
404 data_size = hsw_dip_data_size(type);
406 val &= ~hsw_infoframe_enable(type);
407 I915_WRITE(ctl_reg, val);
410 for (i = 0; i < len; i += 4) {
411 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
412 type, i >> 2), *data);
415 /* Write every possible data byte to force correct ECC calculation. */
416 for (; i < data_size; i += 4)
417 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
421 val |= hsw_infoframe_enable(type);
422 I915_WRITE(ctl_reg, val);
423 POSTING_READ(ctl_reg);
426 static bool hsw_infoframe_enabled(struct intel_encoder *encoder,
427 const struct intel_crtc_state *pipe_config)
429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
430 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
432 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
433 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
434 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
438 * The data we write to the DIP data buffer registers is 1 byte bigger than the
439 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
440 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
441 * used for both technologies.
443 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
444 * DW1: DB3 | DB2 | DB1 | DB0
445 * DW2: DB7 | DB6 | DB5 | DB4
448 * (HB is Header Byte, DB is Data Byte)
450 * The hdmi pack() functions don't know about that hardware specific hole so we
451 * trick them by giving an offset into the buffer and moving back the header
454 static void intel_write_infoframe(struct intel_encoder *encoder,
455 const struct intel_crtc_state *crtc_state,
456 union hdmi_infoframe *frame)
458 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
459 u8 buffer[VIDEO_DIP_DATA_SIZE];
462 /* see comment above for the reason for this offset */
463 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
467 /* Insert the 'hole' (see big comment above) at position 3 */
468 memmove(&buffer[0], &buffer[1], 3);
472 intel_dig_port->write_infoframe(encoder,
474 frame->any.type, buffer, len);
477 static void intel_hdmi_set_avi_infoframe(struct intel_encoder *encoder,
478 const struct intel_crtc_state *crtc_state,
479 const struct drm_connector_state *conn_state)
481 const struct drm_display_mode *adjusted_mode =
482 &crtc_state->base.adjusted_mode;
483 union hdmi_infoframe frame;
486 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
487 conn_state->connector,
490 DRM_ERROR("couldn't fill AVI infoframe\n");
494 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
495 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
496 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
497 frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
499 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
501 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
502 conn_state->connector,
504 crtc_state->limited_color_range ?
505 HDMI_QUANTIZATION_RANGE_LIMITED :
506 HDMI_QUANTIZATION_RANGE_FULL);
508 drm_hdmi_avi_infoframe_content_type(&frame.avi,
511 /* TODO: handle pixel repetition for YCBCR420 outputs */
512 intel_write_infoframe(encoder, crtc_state,
516 static void intel_hdmi_set_spd_infoframe(struct intel_encoder *encoder,
517 const struct intel_crtc_state *crtc_state)
519 union hdmi_infoframe frame;
522 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
524 DRM_ERROR("couldn't fill SPD infoframe\n");
528 frame.spd.sdi = HDMI_SPD_SDI_PC;
530 intel_write_infoframe(encoder, crtc_state,
535 intel_hdmi_set_hdmi_infoframe(struct intel_encoder *encoder,
536 const struct intel_crtc_state *crtc_state,
537 const struct drm_connector_state *conn_state)
539 union hdmi_infoframe frame;
542 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
543 conn_state->connector,
544 &crtc_state->base.adjusted_mode);
548 intel_write_infoframe(encoder, crtc_state,
552 static void g4x_set_infoframes(struct intel_encoder *encoder,
554 const struct intel_crtc_state *crtc_state,
555 const struct drm_connector_state *conn_state)
557 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
558 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
559 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
560 i915_reg_t reg = VIDEO_DIP_CTL;
561 u32 val = I915_READ(reg);
562 u32 port = VIDEO_DIP_PORT(encoder->port);
564 assert_hdmi_port_disabled(intel_hdmi);
566 /* If the registers were not initialized yet, they might be zeroes,
567 * which means we're selecting the AVI DIP and we're setting its
568 * frequency to once. This seems to really confuse the HW and make
569 * things stop working (the register spec says the AVI always needs to
570 * be sent every VSync). So here we avoid writing to the register more
571 * than we need and also explicitly select the AVI DIP and explicitly
572 * set its frequency to every VSync. Avoiding to write it twice seems to
573 * be enough to solve the problem, but being defensive shouldn't hurt us
575 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
578 if (!(val & VIDEO_DIP_ENABLE))
580 if (port != (val & VIDEO_DIP_PORT_MASK)) {
581 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
582 (val & VIDEO_DIP_PORT_MASK) >> 29);
585 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
586 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
587 I915_WRITE(reg, val);
592 if (port != (val & VIDEO_DIP_PORT_MASK)) {
593 if (val & VIDEO_DIP_ENABLE) {
594 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
595 (val & VIDEO_DIP_PORT_MASK) >> 29);
598 val &= ~VIDEO_DIP_PORT_MASK;
602 val |= VIDEO_DIP_ENABLE;
603 val &= ~(VIDEO_DIP_ENABLE_AVI |
604 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
606 I915_WRITE(reg, val);
609 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
610 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
611 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
614 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
616 struct drm_connector *connector = conn_state->connector;
619 * HDMI cloning is only supported on g4x which doesn't
620 * support deep color or GCP infoframes anyway so no
621 * need to worry about multiple HDMI sinks here.
624 return connector->display_info.bpc > 8;
628 * Determine if default_phase=1 can be indicated in the GCP infoframe.
630 * From HDMI specification 1.4a:
631 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
632 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
633 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
634 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
637 static bool gcp_default_phase_possible(int pipe_bpp,
638 const struct drm_display_mode *mode)
640 unsigned int pixels_per_group;
644 /* 4 pixels in 5 clocks */
645 pixels_per_group = 4;
648 /* 2 pixels in 3 clocks */
649 pixels_per_group = 2;
652 /* 1 pixel in 2 clocks */
653 pixels_per_group = 1;
656 /* phase information not relevant for 8bpc */
660 return mode->crtc_hdisplay % pixels_per_group == 0 &&
661 mode->crtc_htotal % pixels_per_group == 0 &&
662 mode->crtc_hblank_start % pixels_per_group == 0 &&
663 mode->crtc_hblank_end % pixels_per_group == 0 &&
664 mode->crtc_hsync_start % pixels_per_group == 0 &&
665 mode->crtc_hsync_end % pixels_per_group == 0 &&
666 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
667 mode->crtc_htotal/2 % pixels_per_group == 0);
670 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
671 const struct intel_crtc_state *crtc_state,
672 const struct drm_connector_state *conn_state)
674 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
675 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
679 if (HAS_DDI(dev_priv))
680 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
681 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
682 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
683 else if (HAS_PCH_SPLIT(dev_priv))
684 reg = TVIDEO_DIP_GCP(crtc->pipe);
688 /* Indicate color depth whenever the sink supports deep color */
689 if (hdmi_sink_is_deep_color(conn_state))
690 val |= GCP_COLOR_INDICATION;
692 /* Enable default_phase whenever the display mode is suitably aligned */
693 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
694 &crtc_state->base.adjusted_mode))
695 val |= GCP_DEFAULT_PHASE_ENABLE;
697 I915_WRITE(reg, val);
702 static void ibx_set_infoframes(struct intel_encoder *encoder,
704 const struct intel_crtc_state *crtc_state,
705 const struct drm_connector_state *conn_state)
707 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
709 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
710 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
711 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
712 u32 val = I915_READ(reg);
713 u32 port = VIDEO_DIP_PORT(encoder->port);
715 assert_hdmi_port_disabled(intel_hdmi);
717 /* See the big comment in g4x_set_infoframes() */
718 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
721 if (!(val & VIDEO_DIP_ENABLE))
723 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
724 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
725 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
726 I915_WRITE(reg, val);
731 if (port != (val & VIDEO_DIP_PORT_MASK)) {
732 WARN(val & VIDEO_DIP_ENABLE,
733 "DIP already enabled on port %c\n",
734 (val & VIDEO_DIP_PORT_MASK) >> 29);
735 val &= ~VIDEO_DIP_PORT_MASK;
739 val |= VIDEO_DIP_ENABLE;
740 val &= ~(VIDEO_DIP_ENABLE_AVI |
741 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
742 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
744 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
745 val |= VIDEO_DIP_ENABLE_GCP;
747 I915_WRITE(reg, val);
750 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
751 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
752 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
755 static void cpt_set_infoframes(struct intel_encoder *encoder,
757 const struct intel_crtc_state *crtc_state,
758 const struct drm_connector_state *conn_state)
760 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
762 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
763 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
764 u32 val = I915_READ(reg);
766 assert_hdmi_port_disabled(intel_hdmi);
768 /* See the big comment in g4x_set_infoframes() */
769 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
772 if (!(val & VIDEO_DIP_ENABLE))
774 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
775 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
776 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
777 I915_WRITE(reg, val);
782 /* Set both together, unset both together: see the spec. */
783 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
784 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
785 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
787 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
788 val |= VIDEO_DIP_ENABLE_GCP;
790 I915_WRITE(reg, val);
793 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
794 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
795 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
798 static void vlv_set_infoframes(struct intel_encoder *encoder,
800 const struct intel_crtc_state *crtc_state,
801 const struct drm_connector_state *conn_state)
803 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
805 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
806 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
807 u32 val = I915_READ(reg);
808 u32 port = VIDEO_DIP_PORT(encoder->port);
810 assert_hdmi_port_disabled(intel_hdmi);
812 /* See the big comment in g4x_set_infoframes() */
813 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
816 if (!(val & VIDEO_DIP_ENABLE))
818 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
819 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
820 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
821 I915_WRITE(reg, val);
826 if (port != (val & VIDEO_DIP_PORT_MASK)) {
827 WARN(val & VIDEO_DIP_ENABLE,
828 "DIP already enabled on port %c\n",
829 (val & VIDEO_DIP_PORT_MASK) >> 29);
830 val &= ~VIDEO_DIP_PORT_MASK;
834 val |= VIDEO_DIP_ENABLE;
835 val &= ~(VIDEO_DIP_ENABLE_AVI |
836 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
837 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
839 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
840 val |= VIDEO_DIP_ENABLE_GCP;
842 I915_WRITE(reg, val);
845 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
846 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
847 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
850 static void hsw_set_infoframes(struct intel_encoder *encoder,
852 const struct intel_crtc_state *crtc_state,
853 const struct drm_connector_state *conn_state)
855 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
856 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
857 u32 val = I915_READ(reg);
859 assert_hdmi_transcoder_func_disabled(dev_priv,
860 crtc_state->cpu_transcoder);
862 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
863 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
864 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
867 I915_WRITE(reg, val);
872 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
873 val |= VIDEO_DIP_ENABLE_GCP_HSW;
875 I915_WRITE(reg, val);
878 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
879 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
880 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
883 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
885 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
886 struct i2c_adapter *adapter =
887 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
889 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
892 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
893 enable ? "Enabling" : "Disabling");
895 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
899 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
900 unsigned int offset, void *buffer, size_t size)
902 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
903 struct drm_i915_private *dev_priv =
904 intel_dig_port->base.base.dev->dev_private;
905 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
908 u8 start = offset & 0xff;
909 struct i2c_msg msgs[] = {
911 .addr = DRM_HDCP_DDC_ADDR,
917 .addr = DRM_HDCP_DDC_ADDR,
923 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
924 if (ret == ARRAY_SIZE(msgs))
926 return ret >= 0 ? -EIO : ret;
929 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
930 unsigned int offset, void *buffer, size_t size)
932 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
933 struct drm_i915_private *dev_priv =
934 intel_dig_port->base.base.dev->dev_private;
935 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
941 write_buf = kzalloc(size + 1, GFP_KERNEL);
945 write_buf[0] = offset & 0xff;
946 memcpy(&write_buf[1], buffer, size);
948 msg.addr = DRM_HDCP_DDC_ADDR;
953 ret = i2c_transfer(adapter, &msg, 1);
964 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
967 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
968 struct drm_i915_private *dev_priv =
969 intel_dig_port->base.base.dev->dev_private;
970 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
974 ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
977 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
981 ret = intel_gmbus_output_aksv(adapter);
983 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
989 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
993 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
996 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
1001 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1005 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1006 bstatus, DRM_HDCP_BSTATUS_LEN);
1008 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1013 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1014 bool *repeater_present)
1019 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1021 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1024 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1029 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1033 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1034 ri_prime, DRM_HDCP_RI_LEN);
1036 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1041 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1047 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1049 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1052 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1057 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1058 int num_downstream, u8 *ksv_fifo)
1061 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1062 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1064 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1071 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1076 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1079 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1080 part, DRM_HDCP_V_PRIME_PART_LEN);
1082 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1087 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1093 usleep_range(6, 60); /* Bspec says >= 6us */
1095 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1097 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1098 enable ? "Enable" : "Disable", ret);
1105 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1107 struct drm_i915_private *dev_priv =
1108 intel_dig_port->base.base.dev->dev_private;
1109 enum port port = intel_dig_port->base.port;
1113 u8 shim[DRM_HDCP_RI_LEN];
1116 ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1120 I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
1122 /* Wait for Ri prime match */
1123 if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
1124 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1125 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1126 I915_READ(PORT_HDCP_STATUS(port)));
1132 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1133 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1134 .read_bksv = intel_hdmi_hdcp_read_bksv,
1135 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1136 .repeater_present = intel_hdmi_hdcp_repeater_present,
1137 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1138 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1139 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1140 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1141 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1142 .check_link = intel_hdmi_hdcp_check_link,
1145 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1146 const struct intel_crtc_state *crtc_state)
1148 struct drm_device *dev = encoder->base.dev;
1149 struct drm_i915_private *dev_priv = to_i915(dev);
1150 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1151 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1152 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1155 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1157 hdmi_val = SDVO_ENCODING_HDMI;
1158 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1159 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1160 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1161 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1162 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1163 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1165 if (crtc_state->pipe_bpp > 24)
1166 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1168 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1170 if (crtc_state->has_hdmi_sink)
1171 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1173 if (HAS_PCH_CPT(dev_priv))
1174 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1175 else if (IS_CHERRYVIEW(dev_priv))
1176 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1178 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1180 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1181 POSTING_READ(intel_hdmi->hdmi_reg);
1184 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1187 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1188 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1189 intel_wakeref_t wakeref;
1192 wakeref = intel_display_power_get_if_enabled(dev_priv,
1193 encoder->power_domain);
1197 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1199 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1204 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1205 struct intel_crtc_state *pipe_config)
1207 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1208 struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
1209 struct drm_device *dev = encoder->base.dev;
1210 struct drm_i915_private *dev_priv = to_i915(dev);
1214 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1216 tmp = I915_READ(intel_hdmi->hdmi_reg);
1218 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1219 flags |= DRM_MODE_FLAG_PHSYNC;
1221 flags |= DRM_MODE_FLAG_NHSYNC;
1223 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1224 flags |= DRM_MODE_FLAG_PVSYNC;
1226 flags |= DRM_MODE_FLAG_NVSYNC;
1228 if (tmp & HDMI_MODE_SELECT_HDMI)
1229 pipe_config->has_hdmi_sink = true;
1231 if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
1232 pipe_config->has_infoframe = true;
1234 if (tmp & SDVO_AUDIO_ENABLE)
1235 pipe_config->has_audio = true;
1237 if (!HAS_PCH_SPLIT(dev_priv) &&
1238 tmp & HDMI_COLOR_RANGE_16_235)
1239 pipe_config->limited_color_range = true;
1241 pipe_config->base.adjusted_mode.flags |= flags;
1243 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1244 dotclock = pipe_config->port_clock * 2 / 3;
1246 dotclock = pipe_config->port_clock;
1248 if (pipe_config->pixel_multiplier)
1249 dotclock /= pipe_config->pixel_multiplier;
1251 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1253 pipe_config->lane_count = 4;
1256 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1257 const struct intel_crtc_state *pipe_config,
1258 const struct drm_connector_state *conn_state)
1260 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1262 WARN_ON(!pipe_config->has_hdmi_sink);
1263 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1264 pipe_name(crtc->pipe));
1265 intel_audio_codec_enable(encoder, pipe_config, conn_state);
1268 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1269 const struct intel_crtc_state *pipe_config,
1270 const struct drm_connector_state *conn_state)
1272 struct drm_device *dev = encoder->base.dev;
1273 struct drm_i915_private *dev_priv = to_i915(dev);
1274 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1277 temp = I915_READ(intel_hdmi->hdmi_reg);
1279 temp |= SDVO_ENABLE;
1280 if (pipe_config->has_audio)
1281 temp |= SDVO_AUDIO_ENABLE;
1283 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1284 POSTING_READ(intel_hdmi->hdmi_reg);
1286 if (pipe_config->has_audio)
1287 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1290 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1291 const struct intel_crtc_state *pipe_config,
1292 const struct drm_connector_state *conn_state)
1294 struct drm_device *dev = encoder->base.dev;
1295 struct drm_i915_private *dev_priv = to_i915(dev);
1296 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1299 temp = I915_READ(intel_hdmi->hdmi_reg);
1301 temp |= SDVO_ENABLE;
1302 if (pipe_config->has_audio)
1303 temp |= SDVO_AUDIO_ENABLE;
1306 * HW workaround, need to write this twice for issue
1307 * that may result in first write getting masked.
1309 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1310 POSTING_READ(intel_hdmi->hdmi_reg);
1311 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1312 POSTING_READ(intel_hdmi->hdmi_reg);
1315 * HW workaround, need to toggle enable bit off and on
1316 * for 12bpc with pixel repeat.
1318 * FIXME: BSpec says this should be done at the end of
1319 * of the modeset sequence, so not sure if this isn't too soon.
1321 if (pipe_config->pipe_bpp > 24 &&
1322 pipe_config->pixel_multiplier > 1) {
1323 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1324 POSTING_READ(intel_hdmi->hdmi_reg);
1327 * HW workaround, need to write this twice for issue
1328 * that may result in first write getting masked.
1330 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1331 POSTING_READ(intel_hdmi->hdmi_reg);
1332 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1333 POSTING_READ(intel_hdmi->hdmi_reg);
1336 if (pipe_config->has_audio)
1337 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1340 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1341 const struct intel_crtc_state *pipe_config,
1342 const struct drm_connector_state *conn_state)
1344 struct drm_device *dev = encoder->base.dev;
1345 struct drm_i915_private *dev_priv = to_i915(dev);
1346 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1347 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1348 enum pipe pipe = crtc->pipe;
1351 temp = I915_READ(intel_hdmi->hdmi_reg);
1353 temp |= SDVO_ENABLE;
1354 if (pipe_config->has_audio)
1355 temp |= SDVO_AUDIO_ENABLE;
1358 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1360 * The procedure for 12bpc is as follows:
1361 * 1. disable HDMI clock gating
1362 * 2. enable HDMI with 8bpc
1363 * 3. enable HDMI with 12bpc
1364 * 4. enable HDMI clock gating
1367 if (pipe_config->pipe_bpp > 24) {
1368 I915_WRITE(TRANS_CHICKEN1(pipe),
1369 I915_READ(TRANS_CHICKEN1(pipe)) |
1370 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1372 temp &= ~SDVO_COLOR_FORMAT_MASK;
1373 temp |= SDVO_COLOR_FORMAT_8bpc;
1376 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1377 POSTING_READ(intel_hdmi->hdmi_reg);
1379 if (pipe_config->pipe_bpp > 24) {
1380 temp &= ~SDVO_COLOR_FORMAT_MASK;
1381 temp |= HDMI_COLOR_FORMAT_12bpc;
1383 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1384 POSTING_READ(intel_hdmi->hdmi_reg);
1386 I915_WRITE(TRANS_CHICKEN1(pipe),
1387 I915_READ(TRANS_CHICKEN1(pipe)) &
1388 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1391 if (pipe_config->has_audio)
1392 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1395 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1396 const struct intel_crtc_state *pipe_config,
1397 const struct drm_connector_state *conn_state)
1401 static void intel_disable_hdmi(struct intel_encoder *encoder,
1402 const struct intel_crtc_state *old_crtc_state,
1403 const struct drm_connector_state *old_conn_state)
1405 struct drm_device *dev = encoder->base.dev;
1406 struct drm_i915_private *dev_priv = to_i915(dev);
1407 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1408 struct intel_digital_port *intel_dig_port =
1409 hdmi_to_dig_port(intel_hdmi);
1410 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1413 temp = I915_READ(intel_hdmi->hdmi_reg);
1415 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1416 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1417 POSTING_READ(intel_hdmi->hdmi_reg);
1420 * HW workaround for IBX, we need to move the port
1421 * to transcoder A after disabling it to allow the
1422 * matching DP port to be enabled on transcoder A.
1424 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1426 * We get CPU/PCH FIFO underruns on the other pipe when
1427 * doing the workaround. Sweep them under the rug.
1429 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1430 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1432 temp &= ~SDVO_PIPE_SEL_MASK;
1433 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1435 * HW workaround, need to write this twice for issue
1436 * that may result in first write getting masked.
1438 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1439 POSTING_READ(intel_hdmi->hdmi_reg);
1440 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1441 POSTING_READ(intel_hdmi->hdmi_reg);
1443 temp &= ~SDVO_ENABLE;
1444 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1445 POSTING_READ(intel_hdmi->hdmi_reg);
1447 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1448 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1449 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1452 intel_dig_port->set_infoframes(encoder,
1454 old_crtc_state, old_conn_state);
1456 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1459 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1460 const struct intel_crtc_state *old_crtc_state,
1461 const struct drm_connector_state *old_conn_state)
1463 if (old_crtc_state->has_audio)
1464 intel_audio_codec_disable(encoder,
1465 old_crtc_state, old_conn_state);
1467 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1470 static void pch_disable_hdmi(struct intel_encoder *encoder,
1471 const struct intel_crtc_state *old_crtc_state,
1472 const struct drm_connector_state *old_conn_state)
1474 if (old_crtc_state->has_audio)
1475 intel_audio_codec_disable(encoder,
1476 old_crtc_state, old_conn_state);
1479 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1480 const struct intel_crtc_state *old_crtc_state,
1481 const struct drm_connector_state *old_conn_state)
1483 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1486 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1488 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1489 const struct ddi_vbt_port_info *info =
1490 &dev_priv->vbt.ddi_port_info[encoder->port];
1493 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1494 max_tmds_clock = 594000;
1495 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1496 max_tmds_clock = 300000;
1497 else if (INTEL_GEN(dev_priv) >= 5)
1498 max_tmds_clock = 225000;
1500 max_tmds_clock = 165000;
1502 if (info->max_tmds_clock)
1503 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1505 return max_tmds_clock;
1508 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1509 bool respect_downstream_limits,
1512 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1513 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1515 if (respect_downstream_limits) {
1516 struct intel_connector *connector = hdmi->attached_connector;
1517 const struct drm_display_info *info = &connector->base.display_info;
1519 if (hdmi->dp_dual_mode.max_tmds_clock)
1520 max_tmds_clock = min(max_tmds_clock,
1521 hdmi->dp_dual_mode.max_tmds_clock);
1523 if (info->max_tmds_clock)
1524 max_tmds_clock = min(max_tmds_clock,
1525 info->max_tmds_clock);
1526 else if (!hdmi->has_hdmi_sink || force_dvi)
1527 max_tmds_clock = min(max_tmds_clock, 165000);
1530 return max_tmds_clock;
1533 static enum drm_mode_status
1534 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1535 int clock, bool respect_downstream_limits,
1538 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1541 return MODE_CLOCK_LOW;
1542 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1543 return MODE_CLOCK_HIGH;
1545 /* BXT DPLL can't generate 223-240 MHz */
1546 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1547 return MODE_CLOCK_RANGE;
1549 /* CHV DPLL can't generate 216-240 MHz */
1550 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1551 return MODE_CLOCK_RANGE;
1556 static enum drm_mode_status
1557 intel_hdmi_mode_valid(struct drm_connector *connector,
1558 struct drm_display_mode *mode)
1560 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1561 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1562 struct drm_i915_private *dev_priv = to_i915(dev);
1563 enum drm_mode_status status;
1565 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1567 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1569 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1570 return MODE_NO_DBLESCAN;
1572 clock = mode->clock;
1574 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1577 if (clock > max_dotclk)
1578 return MODE_CLOCK_HIGH;
1580 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1583 if (drm_mode_is_420_only(&connector->display_info, mode))
1586 /* check if we can do 8bpc */
1587 status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1589 if (hdmi->has_hdmi_sink && !force_dvi) {
1590 /* if we can't do 8bpc we may still be able to do 12bpc */
1591 if (status != MODE_OK && !HAS_GMCH(dev_priv))
1592 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
1595 /* if we can't do 8,12bpc we may still be able to do 10bpc */
1596 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
1597 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
1604 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1607 struct drm_i915_private *dev_priv =
1608 to_i915(crtc_state->base.crtc->dev);
1609 struct drm_atomic_state *state = crtc_state->base.state;
1610 struct drm_connector_state *connector_state;
1611 struct drm_connector *connector;
1612 const struct drm_display_mode *adjusted_mode =
1613 &crtc_state->base.adjusted_mode;
1616 if (HAS_GMCH(dev_priv))
1619 if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
1622 if (crtc_state->pipe_bpp <= 8*3)
1625 if (!crtc_state->has_hdmi_sink)
1629 * HDMI deep color affects the clocks, so it's only possible
1630 * when not cloning with other encoder types.
1632 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1635 for_each_new_connector_in_state(state, connector, connector_state, i) {
1636 const struct drm_display_info *info = &connector->display_info;
1638 if (connector_state->crtc != crtc_state->base.crtc)
1641 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
1642 const struct drm_hdmi_info *hdmi = &info->hdmi;
1644 if (bpc == 12 && !(hdmi->y420_dc_modes &
1645 DRM_EDID_YCBCR420_DC_36))
1647 else if (bpc == 10 && !(hdmi->y420_dc_modes &
1648 DRM_EDID_YCBCR420_DC_30))
1651 if (bpc == 12 && !(info->edid_hdmi_dc_modes &
1652 DRM_EDID_HDMI_DC_36))
1654 else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
1655 DRM_EDID_HDMI_DC_30))
1660 /* Display WA #1139: glk */
1661 if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1662 adjusted_mode->htotal > 5460)
1665 /* Display Wa_1405510057:icl */
1666 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1667 bpc == 10 && IS_ICELAKE(dev_priv) &&
1668 (adjusted_mode->crtc_hblank_end -
1669 adjusted_mode->crtc_hblank_start) % 8 == 2)
1676 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1677 struct intel_crtc_state *config,
1678 int *clock_12bpc, int *clock_10bpc,
1681 struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1683 if (!connector->ycbcr_420_allowed) {
1684 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1688 /* YCBCR420 TMDS rate requirement is half the pixel clock */
1689 config->port_clock /= 2;
1693 config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1695 /* YCBCR 420 output conversion needs a scaler */
1696 if (skl_update_scaler_crtc(config)) {
1697 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1701 intel_pch_panel_fitting(intel_crtc, config,
1702 DRM_MODE_SCALE_FULLSCREEN);
1707 int intel_hdmi_compute_config(struct intel_encoder *encoder,
1708 struct intel_crtc_state *pipe_config,
1709 struct drm_connector_state *conn_state)
1711 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1712 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1713 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1714 struct drm_connector *connector = conn_state->connector;
1715 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
1716 struct intel_digital_connector_state *intel_conn_state =
1717 to_intel_digital_connector_state(conn_state);
1718 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1719 int clock_10bpc = clock_8bpc * 5 / 4;
1720 int clock_12bpc = clock_8bpc * 3 / 2;
1722 bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1724 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1727 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1728 pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1730 if (pipe_config->has_hdmi_sink)
1731 pipe_config->has_infoframe = true;
1733 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1734 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1735 pipe_config->limited_color_range =
1736 pipe_config->has_hdmi_sink &&
1737 drm_default_rgb_quant_range(adjusted_mode) ==
1738 HDMI_QUANTIZATION_RANGE_LIMITED;
1740 pipe_config->limited_color_range =
1741 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1744 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1745 pipe_config->pixel_multiplier = 2;
1751 if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
1752 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
1753 &clock_12bpc, &clock_10bpc,
1755 DRM_ERROR("Can't support YCBCR420 output\n");
1760 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1761 pipe_config->has_pch_encoder = true;
1763 if (pipe_config->has_hdmi_sink) {
1764 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1765 pipe_config->has_audio = intel_hdmi->has_audio;
1767 pipe_config->has_audio =
1768 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1772 * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
1773 * to check that the higher clock still fits within limits.
1775 if (hdmi_deep_color_possible(pipe_config, 12) &&
1776 hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
1777 true, force_dvi) == MODE_OK) {
1778 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1781 /* Need to adjust the port link by 1.5x for 12bpc. */
1782 pipe_config->port_clock = clock_12bpc;
1783 } else if (hdmi_deep_color_possible(pipe_config, 10) &&
1784 hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
1785 true, force_dvi) == MODE_OK) {
1786 DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
1787 desired_bpp = 10 * 3;
1789 /* Need to adjust the port link by 1.25x for 10bpc. */
1790 pipe_config->port_clock = clock_10bpc;
1792 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1795 pipe_config->port_clock = clock_8bpc;
1798 if (!pipe_config->bw_constrained) {
1799 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1800 pipe_config->pipe_bpp = desired_bpp;
1803 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1804 false, force_dvi) != MODE_OK) {
1805 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1809 /* Set user selected PAR to incoming mode's member */
1810 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1812 pipe_config->lane_count = 4;
1814 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
1815 IS_GEMINILAKE(dev_priv))) {
1816 if (scdc->scrambling.low_rates)
1817 pipe_config->hdmi_scrambling = true;
1819 if (pipe_config->port_clock > 340000) {
1820 pipe_config->hdmi_scrambling = true;
1821 pipe_config->hdmi_high_tmds_clock_ratio = true;
1829 intel_hdmi_unset_edid(struct drm_connector *connector)
1831 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1833 intel_hdmi->has_hdmi_sink = false;
1834 intel_hdmi->has_audio = false;
1836 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1837 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1839 kfree(to_intel_connector(connector)->detect_edid);
1840 to_intel_connector(connector)->detect_edid = NULL;
1844 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1846 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1847 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1848 enum port port = hdmi_to_dig_port(hdmi)->base.port;
1849 struct i2c_adapter *adapter =
1850 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1851 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1854 * Type 1 DVI adaptors are not required to implement any
1855 * registers, so we can't always detect their presence.
1856 * Ideally we should be able to check the state of the
1857 * CONFIG1 pin, but no such luck on our hardware.
1859 * The only method left to us is to check the VBT to see
1860 * if the port is a dual mode capable DP port. But let's
1861 * only do that when we sucesfully read the EDID, to avoid
1862 * confusing log messages about DP dual mode adaptors when
1863 * there's nothing connected to the port.
1865 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1866 /* An overridden EDID imply that we want this port for testing.
1867 * Make sure not to set limits for that port.
1869 if (has_edid && !connector->override_edid &&
1870 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1871 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1872 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1874 type = DRM_DP_DUAL_MODE_NONE;
1878 if (type == DRM_DP_DUAL_MODE_NONE)
1881 hdmi->dp_dual_mode.type = type;
1882 hdmi->dp_dual_mode.max_tmds_clock =
1883 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1885 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1886 drm_dp_get_dual_mode_type_name(type),
1887 hdmi->dp_dual_mode.max_tmds_clock);
1891 intel_hdmi_set_edid(struct drm_connector *connector)
1893 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1894 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1895 intel_wakeref_t wakeref;
1897 bool connected = false;
1898 struct i2c_adapter *i2c;
1900 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1902 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
1904 edid = drm_get_edid(connector, i2c);
1906 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
1907 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
1908 intel_gmbus_force_bit(i2c, true);
1909 edid = drm_get_edid(connector, i2c);
1910 intel_gmbus_force_bit(i2c, false);
1913 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1915 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
1917 to_intel_connector(connector)->detect_edid = edid;
1918 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1919 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1920 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1925 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
1930 static enum drm_connector_status
1931 intel_hdmi_detect(struct drm_connector *connector, bool force)
1933 enum drm_connector_status status = connector_status_disconnected;
1934 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1935 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1936 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
1937 intel_wakeref_t wakeref;
1939 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1940 connector->base.id, connector->name);
1942 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1944 if (IS_ICELAKE(dev_priv) &&
1945 !intel_digital_port_connected(encoder))
1948 intel_hdmi_unset_edid(connector);
1950 if (intel_hdmi_set_edid(connector))
1951 status = connector_status_connected;
1954 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
1956 if (status != connector_status_connected)
1957 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
1963 intel_hdmi_force(struct drm_connector *connector)
1965 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1966 connector->base.id, connector->name);
1968 intel_hdmi_unset_edid(connector);
1970 if (connector->status != connector_status_connected)
1973 intel_hdmi_set_edid(connector);
1976 static int intel_hdmi_get_modes(struct drm_connector *connector)
1980 edid = to_intel_connector(connector)->detect_edid;
1984 return intel_connector_update_modes(connector, edid);
1987 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1988 const struct intel_crtc_state *pipe_config,
1989 const struct drm_connector_state *conn_state)
1991 struct intel_digital_port *intel_dig_port =
1992 enc_to_dig_port(&encoder->base);
1994 intel_hdmi_prepare(encoder, pipe_config);
1996 intel_dig_port->set_infoframes(encoder,
1997 pipe_config->has_infoframe,
1998 pipe_config, conn_state);
2001 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
2002 const struct intel_crtc_state *pipe_config,
2003 const struct drm_connector_state *conn_state)
2005 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2006 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2008 vlv_phy_pre_encoder_enable(encoder, pipe_config);
2011 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2014 dport->set_infoframes(encoder,
2015 pipe_config->has_infoframe,
2016 pipe_config, conn_state);
2018 g4x_enable_hdmi(encoder, pipe_config, conn_state);
2020 vlv_wait_port_ready(dev_priv, dport, 0x0);
2023 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2024 const struct intel_crtc_state *pipe_config,
2025 const struct drm_connector_state *conn_state)
2027 intel_hdmi_prepare(encoder, pipe_config);
2029 vlv_phy_pre_pll_enable(encoder, pipe_config);
2032 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2033 const struct intel_crtc_state *pipe_config,
2034 const struct drm_connector_state *conn_state)
2036 intel_hdmi_prepare(encoder, pipe_config);
2038 chv_phy_pre_pll_enable(encoder, pipe_config);
2041 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2042 const struct intel_crtc_state *old_crtc_state,
2043 const struct drm_connector_state *old_conn_state)
2045 chv_phy_post_pll_disable(encoder, old_crtc_state);
2048 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2049 const struct intel_crtc_state *old_crtc_state,
2050 const struct drm_connector_state *old_conn_state)
2052 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2053 vlv_phy_reset_lanes(encoder, old_crtc_state);
2056 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2057 const struct intel_crtc_state *old_crtc_state,
2058 const struct drm_connector_state *old_conn_state)
2060 struct drm_device *dev = encoder->base.dev;
2061 struct drm_i915_private *dev_priv = to_i915(dev);
2063 mutex_lock(&dev_priv->sb_lock);
2065 /* Assert data lane reset */
2066 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2068 mutex_unlock(&dev_priv->sb_lock);
2071 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2072 const struct intel_crtc_state *pipe_config,
2073 const struct drm_connector_state *conn_state)
2075 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2076 struct drm_device *dev = encoder->base.dev;
2077 struct drm_i915_private *dev_priv = to_i915(dev);
2079 chv_phy_pre_encoder_enable(encoder, pipe_config);
2081 /* FIXME: Program the support xxx V-dB */
2083 chv_set_phy_signal_level(encoder, 128, 102, false);
2085 dport->set_infoframes(encoder,
2086 pipe_config->has_infoframe,
2087 pipe_config, conn_state);
2089 g4x_enable_hdmi(encoder, pipe_config, conn_state);
2091 vlv_wait_port_ready(dev_priv, dport, 0x0);
2093 /* Second common lane will stay alive on its own now */
2094 chv_phy_release_cl2_override(encoder);
2098 intel_hdmi_connector_register(struct drm_connector *connector)
2102 ret = intel_connector_register(connector);
2106 i915_debugfs_connector_add(connector);
2111 static void intel_hdmi_destroy(struct drm_connector *connector)
2113 if (intel_attached_hdmi(connector)->cec_notifier)
2114 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2116 intel_connector_destroy(connector);
2119 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2120 .detect = intel_hdmi_detect,
2121 .force = intel_hdmi_force,
2122 .fill_modes = drm_helper_probe_single_connector_modes,
2123 .atomic_get_property = intel_digital_connector_atomic_get_property,
2124 .atomic_set_property = intel_digital_connector_atomic_set_property,
2125 .late_register = intel_hdmi_connector_register,
2126 .early_unregister = intel_connector_unregister,
2127 .destroy = intel_hdmi_destroy,
2128 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2129 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2132 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2133 .get_modes = intel_hdmi_get_modes,
2134 .mode_valid = intel_hdmi_mode_valid,
2135 .atomic_check = intel_digital_connector_atomic_check,
2138 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2139 .destroy = intel_encoder_destroy,
2143 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2145 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2147 intel_attach_force_audio_property(connector);
2148 intel_attach_broadcast_rgb_property(connector);
2149 intel_attach_aspect_ratio_property(connector);
2150 drm_connector_attach_content_type_property(connector);
2151 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2153 if (!HAS_GMCH(dev_priv))
2154 drm_connector_attach_max_bpc_property(connector, 8, 12);
2158 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2159 * @encoder: intel_encoder
2160 * @connector: drm_connector
2161 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2162 * or reset the high tmds clock ratio for scrambling
2163 * @scrambling: bool to Indicate if the function needs to set or reset
2166 * This function handles scrambling on HDMI 2.0 capable sinks.
2167 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2168 * it enables scrambling. This should be called before enabling the HDMI
2169 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2170 * detect a scrambled clock within 100 ms.
2173 * True on success, false on failure.
2175 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2176 struct drm_connector *connector,
2177 bool high_tmds_clock_ratio,
2180 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2181 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2182 struct drm_scrambling *sink_scrambling =
2183 &connector->display_info.hdmi.scdc.scrambling;
2184 struct i2c_adapter *adapter =
2185 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2187 if (!sink_scrambling->supported)
2190 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2191 connector->base.id, connector->name,
2192 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2194 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2195 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2196 high_tmds_clock_ratio) &&
2197 drm_scdc_set_scrambling(adapter, scrambling);
2200 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2206 ddc_pin = GMBUS_PIN_DPB;
2209 ddc_pin = GMBUS_PIN_DPC;
2212 ddc_pin = GMBUS_PIN_DPD_CHV;
2216 ddc_pin = GMBUS_PIN_DPB;
2222 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2228 ddc_pin = GMBUS_PIN_1_BXT;
2231 ddc_pin = GMBUS_PIN_2_BXT;
2235 ddc_pin = GMBUS_PIN_1_BXT;
2241 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2248 ddc_pin = GMBUS_PIN_1_BXT;
2251 ddc_pin = GMBUS_PIN_2_BXT;
2254 ddc_pin = GMBUS_PIN_4_CNP;
2257 ddc_pin = GMBUS_PIN_3_BXT;
2261 ddc_pin = GMBUS_PIN_1_BXT;
2267 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2273 ddc_pin = GMBUS_PIN_1_BXT;
2276 ddc_pin = GMBUS_PIN_2_BXT;
2279 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2282 ddc_pin = GMBUS_PIN_10_TC2_ICP;
2285 ddc_pin = GMBUS_PIN_11_TC3_ICP;
2288 ddc_pin = GMBUS_PIN_12_TC4_ICP;
2292 ddc_pin = GMBUS_PIN_2_BXT;
2298 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2305 ddc_pin = GMBUS_PIN_DPB;
2308 ddc_pin = GMBUS_PIN_DPC;
2311 ddc_pin = GMBUS_PIN_DPD;
2315 ddc_pin = GMBUS_PIN_DPB;
2321 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2324 const struct ddi_vbt_port_info *info =
2325 &dev_priv->vbt.ddi_port_info[port];
2328 if (info->alternate_ddc_pin) {
2329 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2330 info->alternate_ddc_pin, port_name(port));
2331 return info->alternate_ddc_pin;
2334 if (IS_CHERRYVIEW(dev_priv))
2335 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2336 else if (IS_GEN9_LP(dev_priv))
2337 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2338 else if (HAS_PCH_CNP(dev_priv))
2339 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2340 else if (HAS_PCH_ICP(dev_priv))
2341 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2343 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2345 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2346 ddc_pin, port_name(port));
2351 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
2353 struct drm_i915_private *dev_priv =
2354 to_i915(intel_dig_port->base.base.dev);
2356 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2357 intel_dig_port->write_infoframe = vlv_write_infoframe;
2358 intel_dig_port->set_infoframes = vlv_set_infoframes;
2359 intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
2360 } else if (IS_G4X(dev_priv)) {
2361 intel_dig_port->write_infoframe = g4x_write_infoframe;
2362 intel_dig_port->set_infoframes = g4x_set_infoframes;
2363 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
2364 } else if (HAS_DDI(dev_priv)) {
2365 if (intel_dig_port->lspcon.active) {
2366 intel_dig_port->write_infoframe =
2367 lspcon_write_infoframe;
2368 intel_dig_port->set_infoframes = lspcon_set_infoframes;
2369 intel_dig_port->infoframe_enabled =
2370 lspcon_infoframe_enabled;
2372 intel_dig_port->set_infoframes = hsw_set_infoframes;
2373 intel_dig_port->infoframe_enabled =
2374 hsw_infoframe_enabled;
2375 intel_dig_port->write_infoframe = hsw_write_infoframe;
2377 } else if (HAS_PCH_IBX(dev_priv)) {
2378 intel_dig_port->write_infoframe = ibx_write_infoframe;
2379 intel_dig_port->set_infoframes = ibx_set_infoframes;
2380 intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
2382 intel_dig_port->write_infoframe = cpt_write_infoframe;
2383 intel_dig_port->set_infoframes = cpt_set_infoframes;
2384 intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
2388 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2389 struct intel_connector *intel_connector)
2391 struct drm_connector *connector = &intel_connector->base;
2392 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2393 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2394 struct drm_device *dev = intel_encoder->base.dev;
2395 struct drm_i915_private *dev_priv = to_i915(dev);
2396 enum port port = intel_encoder->port;
2398 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2401 if (WARN(intel_dig_port->max_lanes < 4,
2402 "Not enough lanes (%d) for HDMI on port %c\n",
2403 intel_dig_port->max_lanes, port_name(port)))
2406 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2407 DRM_MODE_CONNECTOR_HDMIA);
2408 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2410 connector->interlace_allowed = 1;
2411 connector->doublescan_allowed = 0;
2412 connector->stereo_allowed = 1;
2414 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2415 connector->ycbcr_420_allowed = true;
2417 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2419 if (WARN_ON(port == PORT_A))
2421 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
2423 if (HAS_DDI(dev_priv))
2424 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2426 intel_connector->get_hw_state = intel_connector_get_hw_state;
2428 intel_hdmi_add_properties(intel_hdmi, connector);
2430 if (is_hdcp_supported(dev_priv, port)) {
2431 int ret = intel_hdcp_init(intel_connector,
2432 &intel_hdmi_hdcp_shim);
2434 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
2437 intel_connector_attach_encoder(intel_connector, intel_encoder);
2438 intel_hdmi->attached_connector = intel_connector;
2440 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2441 * 0xd. Failure to do so will result in spurious interrupts being
2442 * generated on the port when a cable is not attached.
2444 if (IS_G45(dev_priv)) {
2445 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2446 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2449 intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
2450 port_identifier(port));
2451 if (!intel_hdmi->cec_notifier)
2452 DRM_DEBUG_KMS("CEC notifier get failed\n");
2455 void intel_hdmi_init(struct drm_i915_private *dev_priv,
2456 i915_reg_t hdmi_reg, enum port port)
2458 struct intel_digital_port *intel_dig_port;
2459 struct intel_encoder *intel_encoder;
2460 struct intel_connector *intel_connector;
2462 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2463 if (!intel_dig_port)
2466 intel_connector = intel_connector_alloc();
2467 if (!intel_connector) {
2468 kfree(intel_dig_port);
2472 intel_encoder = &intel_dig_port->base;
2474 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2475 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2476 "HDMI %c", port_name(port));
2478 intel_encoder->hotplug = intel_encoder_hotplug;
2479 intel_encoder->compute_config = intel_hdmi_compute_config;
2480 if (HAS_PCH_SPLIT(dev_priv)) {
2481 intel_encoder->disable = pch_disable_hdmi;
2482 intel_encoder->post_disable = pch_post_disable_hdmi;
2484 intel_encoder->disable = g4x_disable_hdmi;
2486 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2487 intel_encoder->get_config = intel_hdmi_get_config;
2488 if (IS_CHERRYVIEW(dev_priv)) {
2489 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2490 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2491 intel_encoder->enable = vlv_enable_hdmi;
2492 intel_encoder->post_disable = chv_hdmi_post_disable;
2493 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2494 } else if (IS_VALLEYVIEW(dev_priv)) {
2495 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2496 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2497 intel_encoder->enable = vlv_enable_hdmi;
2498 intel_encoder->post_disable = vlv_hdmi_post_disable;
2500 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2501 if (HAS_PCH_CPT(dev_priv))
2502 intel_encoder->enable = cpt_enable_hdmi;
2503 else if (HAS_PCH_IBX(dev_priv))
2504 intel_encoder->enable = ibx_enable_hdmi;
2506 intel_encoder->enable = g4x_enable_hdmi;
2509 intel_encoder->type = INTEL_OUTPUT_HDMI;
2510 intel_encoder->power_domain = intel_port_to_power_domain(port);
2511 intel_encoder->port = port;
2512 if (IS_CHERRYVIEW(dev_priv)) {
2514 intel_encoder->crtc_mask = 1 << 2;
2516 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2518 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2520 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2522 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2523 * to work on real hardware. And since g4x can send infoframes to
2524 * only one port anyway, nothing is lost by allowing it.
2526 if (IS_G4X(dev_priv))
2527 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2529 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2530 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2531 intel_dig_port->max_lanes = 4;
2533 intel_infoframe_init(intel_dig_port);
2535 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
2536 intel_hdmi_init_connector(intel_dig_port, intel_connector);