2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_hdcp.h>
38 #include <drm/drm_scdc_helper.h>
39 #include "intel_drv.h"
40 #include <drm/i915_drm.h>
41 #include <drm/intel_lpe_audio.h>
44 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
46 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
50 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
52 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
53 struct drm_i915_private *dev_priv = to_i915(dev);
56 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
58 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
59 "HDMI port enabled, expecting disabled\n");
63 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
64 enum transcoder cpu_transcoder)
66 WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
67 TRANS_DDI_FUNC_ENABLE,
68 "HDMI transcoder function enabled, expecting disabled\n");
71 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
73 struct intel_digital_port *intel_dig_port =
74 container_of(encoder, struct intel_digital_port, base.base);
75 return &intel_dig_port->hdmi;
78 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
80 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
83 static u32 g4x_infoframe_index(unsigned int type)
86 case HDMI_INFOFRAME_TYPE_AVI:
87 return VIDEO_DIP_SELECT_AVI;
88 case HDMI_INFOFRAME_TYPE_SPD:
89 return VIDEO_DIP_SELECT_SPD;
90 case HDMI_INFOFRAME_TYPE_VENDOR:
91 return VIDEO_DIP_SELECT_VENDOR;
98 static u32 g4x_infoframe_enable(unsigned int type)
101 case HDMI_INFOFRAME_TYPE_AVI:
102 return VIDEO_DIP_ENABLE_AVI;
103 case HDMI_INFOFRAME_TYPE_SPD:
104 return VIDEO_DIP_ENABLE_SPD;
105 case HDMI_INFOFRAME_TYPE_VENDOR:
106 return VIDEO_DIP_ENABLE_VENDOR;
113 static u32 hsw_infoframe_enable(unsigned int type)
117 return VIDEO_DIP_ENABLE_VSC_HSW;
119 return VDIP_ENABLE_PPS;
120 case HDMI_INFOFRAME_TYPE_AVI:
121 return VIDEO_DIP_ENABLE_AVI_HSW;
122 case HDMI_INFOFRAME_TYPE_SPD:
123 return VIDEO_DIP_ENABLE_SPD_HSW;
124 case HDMI_INFOFRAME_TYPE_VENDOR:
125 return VIDEO_DIP_ENABLE_VS_HSW;
133 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
134 enum transcoder cpu_transcoder,
140 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
142 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
143 case HDMI_INFOFRAME_TYPE_AVI:
144 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
145 case HDMI_INFOFRAME_TYPE_SPD:
146 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
147 case HDMI_INFOFRAME_TYPE_VENDOR:
148 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
151 return INVALID_MMIO_REG;
155 static int hsw_dip_data_size(unsigned int type)
159 return VIDEO_DIP_VSC_DATA_SIZE;
161 return VIDEO_DIP_PPS_DATA_SIZE;
163 return VIDEO_DIP_DATA_SIZE;
167 static void g4x_write_infoframe(struct intel_encoder *encoder,
168 const struct intel_crtc_state *crtc_state,
170 const void *frame, ssize_t len)
172 const u32 *data = frame;
173 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
174 u32 val = I915_READ(VIDEO_DIP_CTL);
177 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
179 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
180 val |= g4x_infoframe_index(type);
182 val &= ~g4x_infoframe_enable(type);
184 I915_WRITE(VIDEO_DIP_CTL, val);
187 for (i = 0; i < len; i += 4) {
188 I915_WRITE(VIDEO_DIP_DATA, *data);
191 /* Write every possible data byte to force correct ECC calculation. */
192 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
193 I915_WRITE(VIDEO_DIP_DATA, 0);
196 val |= g4x_infoframe_enable(type);
197 val &= ~VIDEO_DIP_FREQ_MASK;
198 val |= VIDEO_DIP_FREQ_VSYNC;
200 I915_WRITE(VIDEO_DIP_CTL, val);
201 POSTING_READ(VIDEO_DIP_CTL);
204 static bool g4x_infoframe_enabled(struct intel_encoder *encoder,
205 const struct intel_crtc_state *pipe_config)
207 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
208 u32 val = I915_READ(VIDEO_DIP_CTL);
210 if ((val & VIDEO_DIP_ENABLE) == 0)
213 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
216 return val & (VIDEO_DIP_ENABLE_AVI |
217 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
220 static void ibx_write_infoframe(struct intel_encoder *encoder,
221 const struct intel_crtc_state *crtc_state,
223 const void *frame, ssize_t len)
225 const u32 *data = frame;
226 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
228 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
229 u32 val = I915_READ(reg);
232 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
234 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
235 val |= g4x_infoframe_index(type);
237 val &= ~g4x_infoframe_enable(type);
239 I915_WRITE(reg, val);
242 for (i = 0; i < len; i += 4) {
243 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
246 /* Write every possible data byte to force correct ECC calculation. */
247 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
248 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
251 val |= g4x_infoframe_enable(type);
252 val &= ~VIDEO_DIP_FREQ_MASK;
253 val |= VIDEO_DIP_FREQ_VSYNC;
255 I915_WRITE(reg, val);
259 static bool ibx_infoframe_enabled(struct intel_encoder *encoder,
260 const struct intel_crtc_state *pipe_config)
262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
263 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
264 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
265 u32 val = I915_READ(reg);
267 if ((val & VIDEO_DIP_ENABLE) == 0)
270 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
273 return val & (VIDEO_DIP_ENABLE_AVI |
274 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
275 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
278 static void cpt_write_infoframe(struct intel_encoder *encoder,
279 const struct intel_crtc_state *crtc_state,
281 const void *frame, ssize_t len)
283 const u32 *data = frame;
284 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
286 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
287 u32 val = I915_READ(reg);
290 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
292 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
293 val |= g4x_infoframe_index(type);
295 /* The DIP control register spec says that we need to update the AVI
296 * infoframe without clearing its enable bit */
297 if (type != HDMI_INFOFRAME_TYPE_AVI)
298 val &= ~g4x_infoframe_enable(type);
300 I915_WRITE(reg, val);
303 for (i = 0; i < len; i += 4) {
304 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
307 /* Write every possible data byte to force correct ECC calculation. */
308 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
309 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
312 val |= g4x_infoframe_enable(type);
313 val &= ~VIDEO_DIP_FREQ_MASK;
314 val |= VIDEO_DIP_FREQ_VSYNC;
316 I915_WRITE(reg, val);
320 static bool cpt_infoframe_enabled(struct intel_encoder *encoder,
321 const struct intel_crtc_state *pipe_config)
323 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
324 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
325 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
327 if ((val & VIDEO_DIP_ENABLE) == 0)
330 return val & (VIDEO_DIP_ENABLE_AVI |
331 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
332 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
335 static void vlv_write_infoframe(struct intel_encoder *encoder,
336 const struct intel_crtc_state *crtc_state,
338 const void *frame, ssize_t len)
340 const u32 *data = frame;
341 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
343 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
344 u32 val = I915_READ(reg);
347 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
349 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
350 val |= g4x_infoframe_index(type);
352 val &= ~g4x_infoframe_enable(type);
354 I915_WRITE(reg, val);
357 for (i = 0; i < len; i += 4) {
358 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
361 /* Write every possible data byte to force correct ECC calculation. */
362 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
363 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
366 val |= g4x_infoframe_enable(type);
367 val &= ~VIDEO_DIP_FREQ_MASK;
368 val |= VIDEO_DIP_FREQ_VSYNC;
370 I915_WRITE(reg, val);
374 static bool vlv_infoframe_enabled(struct intel_encoder *encoder,
375 const struct intel_crtc_state *pipe_config)
377 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
378 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
379 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
381 if ((val & VIDEO_DIP_ENABLE) == 0)
384 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
387 return val & (VIDEO_DIP_ENABLE_AVI |
388 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
389 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
392 static void hsw_write_infoframe(struct intel_encoder *encoder,
393 const struct intel_crtc_state *crtc_state,
395 const void *frame, ssize_t len)
397 const u32 *data = frame;
398 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
399 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
400 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
403 u32 val = I915_READ(ctl_reg);
405 data_size = hsw_dip_data_size(type);
407 val &= ~hsw_infoframe_enable(type);
408 I915_WRITE(ctl_reg, val);
411 for (i = 0; i < len; i += 4) {
412 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
413 type, i >> 2), *data);
416 /* Write every possible data byte to force correct ECC calculation. */
417 for (; i < data_size; i += 4)
418 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
422 val |= hsw_infoframe_enable(type);
423 I915_WRITE(ctl_reg, val);
424 POSTING_READ(ctl_reg);
427 static bool hsw_infoframe_enabled(struct intel_encoder *encoder,
428 const struct intel_crtc_state *pipe_config)
430 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
431 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
433 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
434 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
435 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
439 * The data we write to the DIP data buffer registers is 1 byte bigger than the
440 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
441 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
442 * used for both technologies.
444 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
445 * DW1: DB3 | DB2 | DB1 | DB0
446 * DW2: DB7 | DB6 | DB5 | DB4
449 * (HB is Header Byte, DB is Data Byte)
451 * The hdmi pack() functions don't know about that hardware specific hole so we
452 * trick them by giving an offset into the buffer and moving back the header
455 static void intel_write_infoframe(struct intel_encoder *encoder,
456 const struct intel_crtc_state *crtc_state,
457 union hdmi_infoframe *frame)
459 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
460 u8 buffer[VIDEO_DIP_DATA_SIZE];
463 /* see comment above for the reason for this offset */
464 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
468 /* Insert the 'hole' (see big comment above) at position 3 */
469 memmove(&buffer[0], &buffer[1], 3);
473 intel_dig_port->write_infoframe(encoder,
475 frame->any.type, buffer, len);
478 static void intel_hdmi_set_avi_infoframe(struct intel_encoder *encoder,
479 const struct intel_crtc_state *crtc_state,
480 const struct drm_connector_state *conn_state)
482 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
483 const struct drm_display_mode *adjusted_mode =
484 &crtc_state->base.adjusted_mode;
485 struct drm_connector *connector = &intel_hdmi->attached_connector->base;
486 bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported ||
487 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
488 union hdmi_infoframe frame;
491 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
495 DRM_ERROR("couldn't fill AVI infoframe\n");
499 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
500 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
501 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
502 frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
504 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
506 drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
507 crtc_state->limited_color_range ?
508 HDMI_QUANTIZATION_RANGE_LIMITED :
509 HDMI_QUANTIZATION_RANGE_FULL,
510 intel_hdmi->rgb_quant_range_selectable,
513 drm_hdmi_avi_infoframe_content_type(&frame.avi,
516 /* TODO: handle pixel repetition for YCBCR420 outputs */
517 intel_write_infoframe(encoder, crtc_state,
521 static void intel_hdmi_set_spd_infoframe(struct intel_encoder *encoder,
522 const struct intel_crtc_state *crtc_state)
524 union hdmi_infoframe frame;
527 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
529 DRM_ERROR("couldn't fill SPD infoframe\n");
533 frame.spd.sdi = HDMI_SPD_SDI_PC;
535 intel_write_infoframe(encoder, crtc_state,
540 intel_hdmi_set_hdmi_infoframe(struct intel_encoder *encoder,
541 const struct intel_crtc_state *crtc_state,
542 const struct drm_connector_state *conn_state)
544 union hdmi_infoframe frame;
547 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
548 conn_state->connector,
549 &crtc_state->base.adjusted_mode);
553 intel_write_infoframe(encoder, crtc_state,
557 static void g4x_set_infoframes(struct intel_encoder *encoder,
559 const struct intel_crtc_state *crtc_state,
560 const struct drm_connector_state *conn_state)
562 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
563 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
564 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
565 i915_reg_t reg = VIDEO_DIP_CTL;
566 u32 val = I915_READ(reg);
567 u32 port = VIDEO_DIP_PORT(encoder->port);
569 assert_hdmi_port_disabled(intel_hdmi);
571 /* If the registers were not initialized yet, they might be zeroes,
572 * which means we're selecting the AVI DIP and we're setting its
573 * frequency to once. This seems to really confuse the HW and make
574 * things stop working (the register spec says the AVI always needs to
575 * be sent every VSync). So here we avoid writing to the register more
576 * than we need and also explicitly select the AVI DIP and explicitly
577 * set its frequency to every VSync. Avoiding to write it twice seems to
578 * be enough to solve the problem, but being defensive shouldn't hurt us
580 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
583 if (!(val & VIDEO_DIP_ENABLE))
585 if (port != (val & VIDEO_DIP_PORT_MASK)) {
586 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
587 (val & VIDEO_DIP_PORT_MASK) >> 29);
590 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
591 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
592 I915_WRITE(reg, val);
597 if (port != (val & VIDEO_DIP_PORT_MASK)) {
598 if (val & VIDEO_DIP_ENABLE) {
599 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
600 (val & VIDEO_DIP_PORT_MASK) >> 29);
603 val &= ~VIDEO_DIP_PORT_MASK;
607 val |= VIDEO_DIP_ENABLE;
608 val &= ~(VIDEO_DIP_ENABLE_AVI |
609 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
611 I915_WRITE(reg, val);
614 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
615 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
616 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
619 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
621 struct drm_connector *connector = conn_state->connector;
624 * HDMI cloning is only supported on g4x which doesn't
625 * support deep color or GCP infoframes anyway so no
626 * need to worry about multiple HDMI sinks here.
629 return connector->display_info.bpc > 8;
633 * Determine if default_phase=1 can be indicated in the GCP infoframe.
635 * From HDMI specification 1.4a:
636 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
637 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
638 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
639 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
642 static bool gcp_default_phase_possible(int pipe_bpp,
643 const struct drm_display_mode *mode)
645 unsigned int pixels_per_group;
649 /* 4 pixels in 5 clocks */
650 pixels_per_group = 4;
653 /* 2 pixels in 3 clocks */
654 pixels_per_group = 2;
657 /* 1 pixel in 2 clocks */
658 pixels_per_group = 1;
661 /* phase information not relevant for 8bpc */
665 return mode->crtc_hdisplay % pixels_per_group == 0 &&
666 mode->crtc_htotal % pixels_per_group == 0 &&
667 mode->crtc_hblank_start % pixels_per_group == 0 &&
668 mode->crtc_hblank_end % pixels_per_group == 0 &&
669 mode->crtc_hsync_start % pixels_per_group == 0 &&
670 mode->crtc_hsync_end % pixels_per_group == 0 &&
671 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
672 mode->crtc_htotal/2 % pixels_per_group == 0);
675 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
676 const struct intel_crtc_state *crtc_state,
677 const struct drm_connector_state *conn_state)
679 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
680 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
684 if (HAS_DDI(dev_priv))
685 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
686 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
687 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
688 else if (HAS_PCH_SPLIT(dev_priv))
689 reg = TVIDEO_DIP_GCP(crtc->pipe);
693 /* Indicate color depth whenever the sink supports deep color */
694 if (hdmi_sink_is_deep_color(conn_state))
695 val |= GCP_COLOR_INDICATION;
697 /* Enable default_phase whenever the display mode is suitably aligned */
698 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
699 &crtc_state->base.adjusted_mode))
700 val |= GCP_DEFAULT_PHASE_ENABLE;
702 I915_WRITE(reg, val);
707 static void ibx_set_infoframes(struct intel_encoder *encoder,
709 const struct intel_crtc_state *crtc_state,
710 const struct drm_connector_state *conn_state)
712 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
714 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
715 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
716 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
717 u32 val = I915_READ(reg);
718 u32 port = VIDEO_DIP_PORT(encoder->port);
720 assert_hdmi_port_disabled(intel_hdmi);
722 /* See the big comment in g4x_set_infoframes() */
723 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
726 if (!(val & VIDEO_DIP_ENABLE))
728 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
729 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
730 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
731 I915_WRITE(reg, val);
736 if (port != (val & VIDEO_DIP_PORT_MASK)) {
737 WARN(val & VIDEO_DIP_ENABLE,
738 "DIP already enabled on port %c\n",
739 (val & VIDEO_DIP_PORT_MASK) >> 29);
740 val &= ~VIDEO_DIP_PORT_MASK;
744 val |= VIDEO_DIP_ENABLE;
745 val &= ~(VIDEO_DIP_ENABLE_AVI |
746 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
747 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
749 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
750 val |= VIDEO_DIP_ENABLE_GCP;
752 I915_WRITE(reg, val);
755 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
756 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
757 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
760 static void cpt_set_infoframes(struct intel_encoder *encoder,
762 const struct intel_crtc_state *crtc_state,
763 const struct drm_connector_state *conn_state)
765 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
767 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
768 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
769 u32 val = I915_READ(reg);
771 assert_hdmi_port_disabled(intel_hdmi);
773 /* See the big comment in g4x_set_infoframes() */
774 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
777 if (!(val & VIDEO_DIP_ENABLE))
779 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
780 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
781 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
782 I915_WRITE(reg, val);
787 /* Set both together, unset both together: see the spec. */
788 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
789 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
790 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
792 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
793 val |= VIDEO_DIP_ENABLE_GCP;
795 I915_WRITE(reg, val);
798 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
799 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
800 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
803 static void vlv_set_infoframes(struct intel_encoder *encoder,
805 const struct intel_crtc_state *crtc_state,
806 const struct drm_connector_state *conn_state)
808 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
810 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
811 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
812 u32 val = I915_READ(reg);
813 u32 port = VIDEO_DIP_PORT(encoder->port);
815 assert_hdmi_port_disabled(intel_hdmi);
817 /* See the big comment in g4x_set_infoframes() */
818 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
821 if (!(val & VIDEO_DIP_ENABLE))
823 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
824 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
825 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
826 I915_WRITE(reg, val);
831 if (port != (val & VIDEO_DIP_PORT_MASK)) {
832 WARN(val & VIDEO_DIP_ENABLE,
833 "DIP already enabled on port %c\n",
834 (val & VIDEO_DIP_PORT_MASK) >> 29);
835 val &= ~VIDEO_DIP_PORT_MASK;
839 val |= VIDEO_DIP_ENABLE;
840 val &= ~(VIDEO_DIP_ENABLE_AVI |
841 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
842 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
844 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
845 val |= VIDEO_DIP_ENABLE_GCP;
847 I915_WRITE(reg, val);
850 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
851 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
852 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
855 static void hsw_set_infoframes(struct intel_encoder *encoder,
857 const struct intel_crtc_state *crtc_state,
858 const struct drm_connector_state *conn_state)
860 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
861 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
862 u32 val = I915_READ(reg);
864 assert_hdmi_transcoder_func_disabled(dev_priv,
865 crtc_state->cpu_transcoder);
867 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
868 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
869 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
872 I915_WRITE(reg, val);
877 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
878 val |= VIDEO_DIP_ENABLE_GCP_HSW;
880 I915_WRITE(reg, val);
883 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
884 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
885 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
888 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
890 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
891 struct i2c_adapter *adapter =
892 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
894 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
897 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
898 enable ? "Enabling" : "Disabling");
900 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
904 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
905 unsigned int offset, void *buffer, size_t size)
907 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
908 struct drm_i915_private *dev_priv =
909 intel_dig_port->base.base.dev->dev_private;
910 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
913 u8 start = offset & 0xff;
914 struct i2c_msg msgs[] = {
916 .addr = DRM_HDCP_DDC_ADDR,
922 .addr = DRM_HDCP_DDC_ADDR,
928 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
929 if (ret == ARRAY_SIZE(msgs))
931 return ret >= 0 ? -EIO : ret;
934 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
935 unsigned int offset, void *buffer, size_t size)
937 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
938 struct drm_i915_private *dev_priv =
939 intel_dig_port->base.base.dev->dev_private;
940 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
946 write_buf = kzalloc(size + 1, GFP_KERNEL);
950 write_buf[0] = offset & 0xff;
951 memcpy(&write_buf[1], buffer, size);
953 msg.addr = DRM_HDCP_DDC_ADDR;
958 ret = i2c_transfer(adapter, &msg, 1);
969 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
972 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
973 struct drm_i915_private *dev_priv =
974 intel_dig_port->base.base.dev->dev_private;
975 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
979 ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
982 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
986 ret = intel_gmbus_output_aksv(adapter);
988 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
994 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
998 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
1001 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
1006 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1010 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1011 bstatus, DRM_HDCP_BSTATUS_LEN);
1013 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1018 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1019 bool *repeater_present)
1024 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1026 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1029 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1034 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1038 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1039 ri_prime, DRM_HDCP_RI_LEN);
1041 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1046 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1052 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1054 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1057 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1062 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1063 int num_downstream, u8 *ksv_fifo)
1066 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1067 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1069 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1076 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1081 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1084 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1085 part, DRM_HDCP_V_PRIME_PART_LEN);
1087 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1092 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1098 usleep_range(6, 60); /* Bspec says >= 6us */
1100 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1102 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1103 enable ? "Enable" : "Disable", ret);
1110 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1112 struct drm_i915_private *dev_priv =
1113 intel_dig_port->base.base.dev->dev_private;
1114 enum port port = intel_dig_port->base.port;
1118 u8 shim[DRM_HDCP_RI_LEN];
1121 ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1125 I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
1127 /* Wait for Ri prime match */
1128 if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
1129 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1130 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1131 I915_READ(PORT_HDCP_STATUS(port)));
1137 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1138 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1139 .read_bksv = intel_hdmi_hdcp_read_bksv,
1140 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1141 .repeater_present = intel_hdmi_hdcp_repeater_present,
1142 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1143 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1144 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1145 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1146 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1147 .check_link = intel_hdmi_hdcp_check_link,
1150 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1151 const struct intel_crtc_state *crtc_state)
1153 struct drm_device *dev = encoder->base.dev;
1154 struct drm_i915_private *dev_priv = to_i915(dev);
1155 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1156 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1157 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1160 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1162 hdmi_val = SDVO_ENCODING_HDMI;
1163 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1164 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1165 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1166 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1167 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1168 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1170 if (crtc_state->pipe_bpp > 24)
1171 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1173 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1175 if (crtc_state->has_hdmi_sink)
1176 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1178 if (HAS_PCH_CPT(dev_priv))
1179 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1180 else if (IS_CHERRYVIEW(dev_priv))
1181 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1183 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1185 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1186 POSTING_READ(intel_hdmi->hdmi_reg);
1189 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1192 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1193 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1196 if (!intel_display_power_get_if_enabled(dev_priv,
1197 encoder->power_domain))
1200 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1202 intel_display_power_put(dev_priv, encoder->power_domain);
1207 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1208 struct intel_crtc_state *pipe_config)
1210 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1211 struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
1212 struct drm_device *dev = encoder->base.dev;
1213 struct drm_i915_private *dev_priv = to_i915(dev);
1217 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1219 tmp = I915_READ(intel_hdmi->hdmi_reg);
1221 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1222 flags |= DRM_MODE_FLAG_PHSYNC;
1224 flags |= DRM_MODE_FLAG_NHSYNC;
1226 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1227 flags |= DRM_MODE_FLAG_PVSYNC;
1229 flags |= DRM_MODE_FLAG_NVSYNC;
1231 if (tmp & HDMI_MODE_SELECT_HDMI)
1232 pipe_config->has_hdmi_sink = true;
1234 if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
1235 pipe_config->has_infoframe = true;
1237 if (tmp & SDVO_AUDIO_ENABLE)
1238 pipe_config->has_audio = true;
1240 if (!HAS_PCH_SPLIT(dev_priv) &&
1241 tmp & HDMI_COLOR_RANGE_16_235)
1242 pipe_config->limited_color_range = true;
1244 pipe_config->base.adjusted_mode.flags |= flags;
1246 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1247 dotclock = pipe_config->port_clock * 2 / 3;
1249 dotclock = pipe_config->port_clock;
1251 if (pipe_config->pixel_multiplier)
1252 dotclock /= pipe_config->pixel_multiplier;
1254 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1256 pipe_config->lane_count = 4;
1259 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1260 const struct intel_crtc_state *pipe_config,
1261 const struct drm_connector_state *conn_state)
1263 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1265 WARN_ON(!pipe_config->has_hdmi_sink);
1266 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1267 pipe_name(crtc->pipe));
1268 intel_audio_codec_enable(encoder, pipe_config, conn_state);
1271 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1272 const struct intel_crtc_state *pipe_config,
1273 const struct drm_connector_state *conn_state)
1275 struct drm_device *dev = encoder->base.dev;
1276 struct drm_i915_private *dev_priv = to_i915(dev);
1277 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1280 temp = I915_READ(intel_hdmi->hdmi_reg);
1282 temp |= SDVO_ENABLE;
1283 if (pipe_config->has_audio)
1284 temp |= SDVO_AUDIO_ENABLE;
1286 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1287 POSTING_READ(intel_hdmi->hdmi_reg);
1289 if (pipe_config->has_audio)
1290 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1293 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1294 const struct intel_crtc_state *pipe_config,
1295 const struct drm_connector_state *conn_state)
1297 struct drm_device *dev = encoder->base.dev;
1298 struct drm_i915_private *dev_priv = to_i915(dev);
1299 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1302 temp = I915_READ(intel_hdmi->hdmi_reg);
1304 temp |= SDVO_ENABLE;
1305 if (pipe_config->has_audio)
1306 temp |= SDVO_AUDIO_ENABLE;
1309 * HW workaround, need to write this twice for issue
1310 * that may result in first write getting masked.
1312 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1313 POSTING_READ(intel_hdmi->hdmi_reg);
1314 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1315 POSTING_READ(intel_hdmi->hdmi_reg);
1318 * HW workaround, need to toggle enable bit off and on
1319 * for 12bpc with pixel repeat.
1321 * FIXME: BSpec says this should be done at the end of
1322 * of the modeset sequence, so not sure if this isn't too soon.
1324 if (pipe_config->pipe_bpp > 24 &&
1325 pipe_config->pixel_multiplier > 1) {
1326 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1327 POSTING_READ(intel_hdmi->hdmi_reg);
1330 * HW workaround, need to write this twice for issue
1331 * that may result in first write getting masked.
1333 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1334 POSTING_READ(intel_hdmi->hdmi_reg);
1335 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1336 POSTING_READ(intel_hdmi->hdmi_reg);
1339 if (pipe_config->has_audio)
1340 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1343 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1344 const struct intel_crtc_state *pipe_config,
1345 const struct drm_connector_state *conn_state)
1347 struct drm_device *dev = encoder->base.dev;
1348 struct drm_i915_private *dev_priv = to_i915(dev);
1349 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1350 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1351 enum pipe pipe = crtc->pipe;
1354 temp = I915_READ(intel_hdmi->hdmi_reg);
1356 temp |= SDVO_ENABLE;
1357 if (pipe_config->has_audio)
1358 temp |= SDVO_AUDIO_ENABLE;
1361 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1363 * The procedure for 12bpc is as follows:
1364 * 1. disable HDMI clock gating
1365 * 2. enable HDMI with 8bpc
1366 * 3. enable HDMI with 12bpc
1367 * 4. enable HDMI clock gating
1370 if (pipe_config->pipe_bpp > 24) {
1371 I915_WRITE(TRANS_CHICKEN1(pipe),
1372 I915_READ(TRANS_CHICKEN1(pipe)) |
1373 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1375 temp &= ~SDVO_COLOR_FORMAT_MASK;
1376 temp |= SDVO_COLOR_FORMAT_8bpc;
1379 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1380 POSTING_READ(intel_hdmi->hdmi_reg);
1382 if (pipe_config->pipe_bpp > 24) {
1383 temp &= ~SDVO_COLOR_FORMAT_MASK;
1384 temp |= HDMI_COLOR_FORMAT_12bpc;
1386 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1387 POSTING_READ(intel_hdmi->hdmi_reg);
1389 I915_WRITE(TRANS_CHICKEN1(pipe),
1390 I915_READ(TRANS_CHICKEN1(pipe)) &
1391 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1394 if (pipe_config->has_audio)
1395 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1398 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1399 const struct intel_crtc_state *pipe_config,
1400 const struct drm_connector_state *conn_state)
1404 static void intel_disable_hdmi(struct intel_encoder *encoder,
1405 const struct intel_crtc_state *old_crtc_state,
1406 const struct drm_connector_state *old_conn_state)
1408 struct drm_device *dev = encoder->base.dev;
1409 struct drm_i915_private *dev_priv = to_i915(dev);
1410 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1411 struct intel_digital_port *intel_dig_port =
1412 hdmi_to_dig_port(intel_hdmi);
1413 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1416 temp = I915_READ(intel_hdmi->hdmi_reg);
1418 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1419 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1420 POSTING_READ(intel_hdmi->hdmi_reg);
1423 * HW workaround for IBX, we need to move the port
1424 * to transcoder A after disabling it to allow the
1425 * matching DP port to be enabled on transcoder A.
1427 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1429 * We get CPU/PCH FIFO underruns on the other pipe when
1430 * doing the workaround. Sweep them under the rug.
1432 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1433 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1435 temp &= ~SDVO_PIPE_SEL_MASK;
1436 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1438 * HW workaround, need to write this twice for issue
1439 * that may result in first write getting masked.
1441 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1442 POSTING_READ(intel_hdmi->hdmi_reg);
1443 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1444 POSTING_READ(intel_hdmi->hdmi_reg);
1446 temp &= ~SDVO_ENABLE;
1447 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1448 POSTING_READ(intel_hdmi->hdmi_reg);
1450 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1451 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1452 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1455 intel_dig_port->set_infoframes(encoder,
1457 old_crtc_state, old_conn_state);
1459 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1462 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1463 const struct intel_crtc_state *old_crtc_state,
1464 const struct drm_connector_state *old_conn_state)
1466 if (old_crtc_state->has_audio)
1467 intel_audio_codec_disable(encoder,
1468 old_crtc_state, old_conn_state);
1470 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1473 static void pch_disable_hdmi(struct intel_encoder *encoder,
1474 const struct intel_crtc_state *old_crtc_state,
1475 const struct drm_connector_state *old_conn_state)
1477 if (old_crtc_state->has_audio)
1478 intel_audio_codec_disable(encoder,
1479 old_crtc_state, old_conn_state);
1482 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1483 const struct intel_crtc_state *old_crtc_state,
1484 const struct drm_connector_state *old_conn_state)
1486 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1489 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1491 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1492 const struct ddi_vbt_port_info *info =
1493 &dev_priv->vbt.ddi_port_info[encoder->port];
1496 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1497 max_tmds_clock = 594000;
1498 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1499 max_tmds_clock = 300000;
1500 else if (INTEL_GEN(dev_priv) >= 5)
1501 max_tmds_clock = 225000;
1503 max_tmds_clock = 165000;
1505 if (info->max_tmds_clock)
1506 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1508 return max_tmds_clock;
1511 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1512 bool respect_downstream_limits,
1515 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1516 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1518 if (respect_downstream_limits) {
1519 struct intel_connector *connector = hdmi->attached_connector;
1520 const struct drm_display_info *info = &connector->base.display_info;
1522 if (hdmi->dp_dual_mode.max_tmds_clock)
1523 max_tmds_clock = min(max_tmds_clock,
1524 hdmi->dp_dual_mode.max_tmds_clock);
1526 if (info->max_tmds_clock)
1527 max_tmds_clock = min(max_tmds_clock,
1528 info->max_tmds_clock);
1529 else if (!hdmi->has_hdmi_sink || force_dvi)
1530 max_tmds_clock = min(max_tmds_clock, 165000);
1533 return max_tmds_clock;
1536 static enum drm_mode_status
1537 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1538 int clock, bool respect_downstream_limits,
1541 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1544 return MODE_CLOCK_LOW;
1545 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1546 return MODE_CLOCK_HIGH;
1548 /* BXT DPLL can't generate 223-240 MHz */
1549 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1550 return MODE_CLOCK_RANGE;
1552 /* CHV DPLL can't generate 216-240 MHz */
1553 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1554 return MODE_CLOCK_RANGE;
1559 static enum drm_mode_status
1560 intel_hdmi_mode_valid(struct drm_connector *connector,
1561 struct drm_display_mode *mode)
1563 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1564 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1565 struct drm_i915_private *dev_priv = to_i915(dev);
1566 enum drm_mode_status status;
1568 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1570 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1572 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1573 return MODE_NO_DBLESCAN;
1575 clock = mode->clock;
1577 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1580 if (clock > max_dotclk)
1581 return MODE_CLOCK_HIGH;
1583 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1586 if (drm_mode_is_420_only(&connector->display_info, mode))
1589 /* check if we can do 8bpc */
1590 status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1592 if (hdmi->has_hdmi_sink && !force_dvi) {
1593 /* if we can't do 8bpc we may still be able to do 12bpc */
1594 if (status != MODE_OK && !HAS_GMCH_DISPLAY(dev_priv))
1595 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
1598 /* if we can't do 8,12bpc we may still be able to do 10bpc */
1599 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
1600 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
1607 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1610 struct drm_i915_private *dev_priv =
1611 to_i915(crtc_state->base.crtc->dev);
1612 struct drm_atomic_state *state = crtc_state->base.state;
1613 struct drm_connector_state *connector_state;
1614 struct drm_connector *connector;
1615 const struct drm_display_mode *adjusted_mode =
1616 &crtc_state->base.adjusted_mode;
1619 if (HAS_GMCH_DISPLAY(dev_priv))
1622 if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
1625 if (crtc_state->pipe_bpp <= 8*3)
1628 if (!crtc_state->has_hdmi_sink)
1632 * HDMI deep color affects the clocks, so it's only possible
1633 * when not cloning with other encoder types.
1635 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1638 for_each_new_connector_in_state(state, connector, connector_state, i) {
1639 const struct drm_display_info *info = &connector->display_info;
1641 if (connector_state->crtc != crtc_state->base.crtc)
1644 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
1645 const struct drm_hdmi_info *hdmi = &info->hdmi;
1647 if (bpc == 12 && !(hdmi->y420_dc_modes &
1648 DRM_EDID_YCBCR420_DC_36))
1650 else if (bpc == 10 && !(hdmi->y420_dc_modes &
1651 DRM_EDID_YCBCR420_DC_30))
1654 if (bpc == 12 && !(info->edid_hdmi_dc_modes &
1655 DRM_EDID_HDMI_DC_36))
1657 else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
1658 DRM_EDID_HDMI_DC_30))
1663 /* Display WA #1139: glk */
1664 if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1665 adjusted_mode->htotal > 5460)
1668 /* Display Wa_1405510057:icl */
1669 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1670 bpc == 10 && IS_ICELAKE(dev_priv) &&
1671 (adjusted_mode->crtc_hblank_end -
1672 adjusted_mode->crtc_hblank_start) % 8 == 2)
1679 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1680 struct intel_crtc_state *config,
1681 int *clock_12bpc, int *clock_10bpc,
1684 struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1686 if (!connector->ycbcr_420_allowed) {
1687 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1691 /* YCBCR420 TMDS rate requirement is half the pixel clock */
1692 config->port_clock /= 2;
1696 config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1698 /* YCBCR 420 output conversion needs a scaler */
1699 if (skl_update_scaler_crtc(config)) {
1700 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1704 intel_pch_panel_fitting(intel_crtc, config,
1705 DRM_MODE_SCALE_FULLSCREEN);
1710 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1711 struct intel_crtc_state *pipe_config,
1712 struct drm_connector_state *conn_state)
1714 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1715 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1716 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1717 struct drm_connector *connector = conn_state->connector;
1718 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
1719 struct intel_digital_connector_state *intel_conn_state =
1720 to_intel_digital_connector_state(conn_state);
1721 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1722 int clock_10bpc = clock_8bpc * 5 / 4;
1723 int clock_12bpc = clock_8bpc * 3 / 2;
1725 bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1727 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1730 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1731 pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1733 if (pipe_config->has_hdmi_sink)
1734 pipe_config->has_infoframe = true;
1736 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1737 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1738 pipe_config->limited_color_range =
1739 pipe_config->has_hdmi_sink &&
1740 drm_default_rgb_quant_range(adjusted_mode) ==
1741 HDMI_QUANTIZATION_RANGE_LIMITED;
1743 pipe_config->limited_color_range =
1744 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1747 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1748 pipe_config->pixel_multiplier = 2;
1754 if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
1755 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
1756 &clock_12bpc, &clock_10bpc,
1758 DRM_ERROR("Can't support YCBCR420 output\n");
1763 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1764 pipe_config->has_pch_encoder = true;
1766 if (pipe_config->has_hdmi_sink) {
1767 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1768 pipe_config->has_audio = intel_hdmi->has_audio;
1770 pipe_config->has_audio =
1771 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1775 * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
1776 * to check that the higher clock still fits within limits.
1778 if (hdmi_deep_color_possible(pipe_config, 12) &&
1779 hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
1780 true, force_dvi) == MODE_OK) {
1781 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1784 /* Need to adjust the port link by 1.5x for 12bpc. */
1785 pipe_config->port_clock = clock_12bpc;
1786 } else if (hdmi_deep_color_possible(pipe_config, 10) &&
1787 hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
1788 true, force_dvi) == MODE_OK) {
1789 DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
1790 desired_bpp = 10 * 3;
1792 /* Need to adjust the port link by 1.25x for 10bpc. */
1793 pipe_config->port_clock = clock_10bpc;
1795 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1798 pipe_config->port_clock = clock_8bpc;
1801 if (!pipe_config->bw_constrained) {
1802 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1803 pipe_config->pipe_bpp = desired_bpp;
1806 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1807 false, force_dvi) != MODE_OK) {
1808 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1812 /* Set user selected PAR to incoming mode's member */
1813 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1815 pipe_config->lane_count = 4;
1817 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
1818 IS_GEMINILAKE(dev_priv))) {
1819 if (scdc->scrambling.low_rates)
1820 pipe_config->hdmi_scrambling = true;
1822 if (pipe_config->port_clock > 340000) {
1823 pipe_config->hdmi_scrambling = true;
1824 pipe_config->hdmi_high_tmds_clock_ratio = true;
1832 intel_hdmi_unset_edid(struct drm_connector *connector)
1834 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1836 intel_hdmi->has_hdmi_sink = false;
1837 intel_hdmi->has_audio = false;
1838 intel_hdmi->rgb_quant_range_selectable = false;
1840 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1841 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1843 kfree(to_intel_connector(connector)->detect_edid);
1844 to_intel_connector(connector)->detect_edid = NULL;
1848 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1850 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1851 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1852 enum port port = hdmi_to_dig_port(hdmi)->base.port;
1853 struct i2c_adapter *adapter =
1854 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1855 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1858 * Type 1 DVI adaptors are not required to implement any
1859 * registers, so we can't always detect their presence.
1860 * Ideally we should be able to check the state of the
1861 * CONFIG1 pin, but no such luck on our hardware.
1863 * The only method left to us is to check the VBT to see
1864 * if the port is a dual mode capable DP port. But let's
1865 * only do that when we sucesfully read the EDID, to avoid
1866 * confusing log messages about DP dual mode adaptors when
1867 * there's nothing connected to the port.
1869 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1870 /* An overridden EDID imply that we want this port for testing.
1871 * Make sure not to set limits for that port.
1873 if (has_edid && !connector->override_edid &&
1874 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1875 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1876 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1878 type = DRM_DP_DUAL_MODE_NONE;
1882 if (type == DRM_DP_DUAL_MODE_NONE)
1885 hdmi->dp_dual_mode.type = type;
1886 hdmi->dp_dual_mode.max_tmds_clock =
1887 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1889 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1890 drm_dp_get_dual_mode_type_name(type),
1891 hdmi->dp_dual_mode.max_tmds_clock);
1895 intel_hdmi_set_edid(struct drm_connector *connector)
1897 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1898 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1900 bool connected = false;
1901 struct i2c_adapter *i2c;
1903 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1905 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
1907 edid = drm_get_edid(connector, i2c);
1909 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
1910 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
1911 intel_gmbus_force_bit(i2c, true);
1912 edid = drm_get_edid(connector, i2c);
1913 intel_gmbus_force_bit(i2c, false);
1916 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1918 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1920 to_intel_connector(connector)->detect_edid = edid;
1921 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1922 intel_hdmi->rgb_quant_range_selectable =
1923 drm_rgb_quant_range_selectable(edid);
1925 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1926 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1931 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
1936 static enum drm_connector_status
1937 intel_hdmi_detect(struct drm_connector *connector, bool force)
1939 enum drm_connector_status status = connector_status_disconnected;
1940 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1941 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1942 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
1944 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1945 connector->base.id, connector->name);
1947 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1949 if (IS_ICELAKE(dev_priv) &&
1950 !intel_digital_port_connected(encoder))
1953 intel_hdmi_unset_edid(connector);
1955 if (intel_hdmi_set_edid(connector))
1956 status = connector_status_connected;
1959 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1961 if (status != connector_status_connected)
1962 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
1968 intel_hdmi_force(struct drm_connector *connector)
1970 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1971 connector->base.id, connector->name);
1973 intel_hdmi_unset_edid(connector);
1975 if (connector->status != connector_status_connected)
1978 intel_hdmi_set_edid(connector);
1981 static int intel_hdmi_get_modes(struct drm_connector *connector)
1985 edid = to_intel_connector(connector)->detect_edid;
1989 return intel_connector_update_modes(connector, edid);
1992 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1993 const struct intel_crtc_state *pipe_config,
1994 const struct drm_connector_state *conn_state)
1996 struct intel_digital_port *intel_dig_port =
1997 enc_to_dig_port(&encoder->base);
1999 intel_hdmi_prepare(encoder, pipe_config);
2001 intel_dig_port->set_infoframes(encoder,
2002 pipe_config->has_infoframe,
2003 pipe_config, conn_state);
2006 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
2007 const struct intel_crtc_state *pipe_config,
2008 const struct drm_connector_state *conn_state)
2010 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2011 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2013 vlv_phy_pre_encoder_enable(encoder, pipe_config);
2016 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2019 dport->set_infoframes(encoder,
2020 pipe_config->has_infoframe,
2021 pipe_config, conn_state);
2023 g4x_enable_hdmi(encoder, pipe_config, conn_state);
2025 vlv_wait_port_ready(dev_priv, dport, 0x0);
2028 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2029 const struct intel_crtc_state *pipe_config,
2030 const struct drm_connector_state *conn_state)
2032 intel_hdmi_prepare(encoder, pipe_config);
2034 vlv_phy_pre_pll_enable(encoder, pipe_config);
2037 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2038 const struct intel_crtc_state *pipe_config,
2039 const struct drm_connector_state *conn_state)
2041 intel_hdmi_prepare(encoder, pipe_config);
2043 chv_phy_pre_pll_enable(encoder, pipe_config);
2046 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2047 const struct intel_crtc_state *old_crtc_state,
2048 const struct drm_connector_state *old_conn_state)
2050 chv_phy_post_pll_disable(encoder, old_crtc_state);
2053 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2054 const struct intel_crtc_state *old_crtc_state,
2055 const struct drm_connector_state *old_conn_state)
2057 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2058 vlv_phy_reset_lanes(encoder, old_crtc_state);
2061 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2062 const struct intel_crtc_state *old_crtc_state,
2063 const struct drm_connector_state *old_conn_state)
2065 struct drm_device *dev = encoder->base.dev;
2066 struct drm_i915_private *dev_priv = to_i915(dev);
2068 mutex_lock(&dev_priv->sb_lock);
2070 /* Assert data lane reset */
2071 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2073 mutex_unlock(&dev_priv->sb_lock);
2076 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2077 const struct intel_crtc_state *pipe_config,
2078 const struct drm_connector_state *conn_state)
2080 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2081 struct drm_device *dev = encoder->base.dev;
2082 struct drm_i915_private *dev_priv = to_i915(dev);
2084 chv_phy_pre_encoder_enable(encoder, pipe_config);
2086 /* FIXME: Program the support xxx V-dB */
2088 chv_set_phy_signal_level(encoder, 128, 102, false);
2090 dport->set_infoframes(encoder,
2091 pipe_config->has_infoframe,
2092 pipe_config, conn_state);
2094 g4x_enable_hdmi(encoder, pipe_config, conn_state);
2096 vlv_wait_port_ready(dev_priv, dport, 0x0);
2098 /* Second common lane will stay alive on its own now */
2099 chv_phy_release_cl2_override(encoder);
2103 intel_hdmi_connector_register(struct drm_connector *connector)
2107 ret = intel_connector_register(connector);
2111 i915_debugfs_connector_add(connector);
2116 static void intel_hdmi_destroy(struct drm_connector *connector)
2118 if (intel_attached_hdmi(connector)->cec_notifier)
2119 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2121 intel_connector_destroy(connector);
2124 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2125 .detect = intel_hdmi_detect,
2126 .force = intel_hdmi_force,
2127 .fill_modes = drm_helper_probe_single_connector_modes,
2128 .atomic_get_property = intel_digital_connector_atomic_get_property,
2129 .atomic_set_property = intel_digital_connector_atomic_set_property,
2130 .late_register = intel_hdmi_connector_register,
2131 .early_unregister = intel_connector_unregister,
2132 .destroy = intel_hdmi_destroy,
2133 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2134 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2137 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2138 .get_modes = intel_hdmi_get_modes,
2139 .mode_valid = intel_hdmi_mode_valid,
2140 .atomic_check = intel_digital_connector_atomic_check,
2143 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2144 .destroy = intel_encoder_destroy,
2148 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2150 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2152 intel_attach_force_audio_property(connector);
2153 intel_attach_broadcast_rgb_property(connector);
2154 intel_attach_aspect_ratio_property(connector);
2155 drm_connector_attach_content_type_property(connector);
2156 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2158 if (!HAS_GMCH_DISPLAY(dev_priv))
2159 drm_connector_attach_max_bpc_property(connector, 8, 12);
2163 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2164 * @encoder: intel_encoder
2165 * @connector: drm_connector
2166 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2167 * or reset the high tmds clock ratio for scrambling
2168 * @scrambling: bool to Indicate if the function needs to set or reset
2171 * This function handles scrambling on HDMI 2.0 capable sinks.
2172 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2173 * it enables scrambling. This should be called before enabling the HDMI
2174 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2175 * detect a scrambled clock within 100 ms.
2178 * True on success, false on failure.
2180 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2181 struct drm_connector *connector,
2182 bool high_tmds_clock_ratio,
2185 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2186 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2187 struct drm_scrambling *sink_scrambling =
2188 &connector->display_info.hdmi.scdc.scrambling;
2189 struct i2c_adapter *adapter =
2190 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2192 if (!sink_scrambling->supported)
2195 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2196 connector->base.id, connector->name,
2197 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2199 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2200 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2201 high_tmds_clock_ratio) &&
2202 drm_scdc_set_scrambling(adapter, scrambling);
2205 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2211 ddc_pin = GMBUS_PIN_DPB;
2214 ddc_pin = GMBUS_PIN_DPC;
2217 ddc_pin = GMBUS_PIN_DPD_CHV;
2221 ddc_pin = GMBUS_PIN_DPB;
2227 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2233 ddc_pin = GMBUS_PIN_1_BXT;
2236 ddc_pin = GMBUS_PIN_2_BXT;
2240 ddc_pin = GMBUS_PIN_1_BXT;
2246 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2253 ddc_pin = GMBUS_PIN_1_BXT;
2256 ddc_pin = GMBUS_PIN_2_BXT;
2259 ddc_pin = GMBUS_PIN_4_CNP;
2262 ddc_pin = GMBUS_PIN_3_BXT;
2266 ddc_pin = GMBUS_PIN_1_BXT;
2272 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2278 ddc_pin = GMBUS_PIN_1_BXT;
2281 ddc_pin = GMBUS_PIN_2_BXT;
2284 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2287 ddc_pin = GMBUS_PIN_10_TC2_ICP;
2290 ddc_pin = GMBUS_PIN_11_TC3_ICP;
2293 ddc_pin = GMBUS_PIN_12_TC4_ICP;
2297 ddc_pin = GMBUS_PIN_2_BXT;
2303 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2310 ddc_pin = GMBUS_PIN_DPB;
2313 ddc_pin = GMBUS_PIN_DPC;
2316 ddc_pin = GMBUS_PIN_DPD;
2320 ddc_pin = GMBUS_PIN_DPB;
2326 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2329 const struct ddi_vbt_port_info *info =
2330 &dev_priv->vbt.ddi_port_info[port];
2333 if (info->alternate_ddc_pin) {
2334 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2335 info->alternate_ddc_pin, port_name(port));
2336 return info->alternate_ddc_pin;
2339 if (IS_CHERRYVIEW(dev_priv))
2340 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2341 else if (IS_GEN9_LP(dev_priv))
2342 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2343 else if (HAS_PCH_CNP(dev_priv))
2344 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2345 else if (HAS_PCH_ICP(dev_priv))
2346 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2348 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2350 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2351 ddc_pin, port_name(port));
2356 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
2358 struct drm_i915_private *dev_priv =
2359 to_i915(intel_dig_port->base.base.dev);
2361 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2362 intel_dig_port->write_infoframe = vlv_write_infoframe;
2363 intel_dig_port->set_infoframes = vlv_set_infoframes;
2364 intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
2365 } else if (IS_G4X(dev_priv)) {
2366 intel_dig_port->write_infoframe = g4x_write_infoframe;
2367 intel_dig_port->set_infoframes = g4x_set_infoframes;
2368 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
2369 } else if (HAS_DDI(dev_priv)) {
2370 if (intel_dig_port->lspcon.active) {
2371 intel_dig_port->write_infoframe =
2372 lspcon_write_infoframe;
2373 intel_dig_port->set_infoframes = lspcon_set_infoframes;
2374 intel_dig_port->infoframe_enabled =
2375 lspcon_infoframe_enabled;
2377 intel_dig_port->set_infoframes = hsw_set_infoframes;
2378 intel_dig_port->infoframe_enabled =
2379 hsw_infoframe_enabled;
2380 intel_dig_port->write_infoframe = hsw_write_infoframe;
2382 } else if (HAS_PCH_IBX(dev_priv)) {
2383 intel_dig_port->write_infoframe = ibx_write_infoframe;
2384 intel_dig_port->set_infoframes = ibx_set_infoframes;
2385 intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
2387 intel_dig_port->write_infoframe = cpt_write_infoframe;
2388 intel_dig_port->set_infoframes = cpt_set_infoframes;
2389 intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
2393 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2394 struct intel_connector *intel_connector)
2396 struct drm_connector *connector = &intel_connector->base;
2397 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2398 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2399 struct drm_device *dev = intel_encoder->base.dev;
2400 struct drm_i915_private *dev_priv = to_i915(dev);
2401 enum port port = intel_encoder->port;
2403 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2406 if (WARN(intel_dig_port->max_lanes < 4,
2407 "Not enough lanes (%d) for HDMI on port %c\n",
2408 intel_dig_port->max_lanes, port_name(port)))
2411 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2412 DRM_MODE_CONNECTOR_HDMIA);
2413 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2415 connector->interlace_allowed = 1;
2416 connector->doublescan_allowed = 0;
2417 connector->stereo_allowed = 1;
2419 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2420 connector->ycbcr_420_allowed = true;
2422 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2424 if (WARN_ON(port == PORT_A))
2426 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
2428 if (HAS_DDI(dev_priv))
2429 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2431 intel_connector->get_hw_state = intel_connector_get_hw_state;
2433 intel_hdmi_add_properties(intel_hdmi, connector);
2435 if (is_hdcp_supported(dev_priv, port)) {
2436 int ret = intel_hdcp_init(intel_connector,
2437 &intel_hdmi_hdcp_shim);
2439 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
2442 intel_connector_attach_encoder(intel_connector, intel_encoder);
2443 intel_hdmi->attached_connector = intel_connector;
2445 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2446 * 0xd. Failure to do so will result in spurious interrupts being
2447 * generated on the port when a cable is not attached.
2449 if (IS_G45(dev_priv)) {
2450 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2451 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2454 intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
2455 port_identifier(port));
2456 if (!intel_hdmi->cec_notifier)
2457 DRM_DEBUG_KMS("CEC notifier get failed\n");
2460 void intel_hdmi_init(struct drm_i915_private *dev_priv,
2461 i915_reg_t hdmi_reg, enum port port)
2463 struct intel_digital_port *intel_dig_port;
2464 struct intel_encoder *intel_encoder;
2465 struct intel_connector *intel_connector;
2467 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2468 if (!intel_dig_port)
2471 intel_connector = intel_connector_alloc();
2472 if (!intel_connector) {
2473 kfree(intel_dig_port);
2477 intel_encoder = &intel_dig_port->base;
2479 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2480 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2481 "HDMI %c", port_name(port));
2483 intel_encoder->hotplug = intel_encoder_hotplug;
2484 intel_encoder->compute_config = intel_hdmi_compute_config;
2485 if (HAS_PCH_SPLIT(dev_priv)) {
2486 intel_encoder->disable = pch_disable_hdmi;
2487 intel_encoder->post_disable = pch_post_disable_hdmi;
2489 intel_encoder->disable = g4x_disable_hdmi;
2491 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2492 intel_encoder->get_config = intel_hdmi_get_config;
2493 if (IS_CHERRYVIEW(dev_priv)) {
2494 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2495 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2496 intel_encoder->enable = vlv_enable_hdmi;
2497 intel_encoder->post_disable = chv_hdmi_post_disable;
2498 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2499 } else if (IS_VALLEYVIEW(dev_priv)) {
2500 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2501 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2502 intel_encoder->enable = vlv_enable_hdmi;
2503 intel_encoder->post_disable = vlv_hdmi_post_disable;
2505 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2506 if (HAS_PCH_CPT(dev_priv))
2507 intel_encoder->enable = cpt_enable_hdmi;
2508 else if (HAS_PCH_IBX(dev_priv))
2509 intel_encoder->enable = ibx_enable_hdmi;
2511 intel_encoder->enable = g4x_enable_hdmi;
2514 intel_encoder->type = INTEL_OUTPUT_HDMI;
2515 intel_encoder->power_domain = intel_port_to_power_domain(port);
2516 intel_encoder->port = port;
2517 if (IS_CHERRYVIEW(dev_priv)) {
2519 intel_encoder->crtc_mask = 1 << 2;
2521 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2523 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2525 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2527 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2528 * to work on real hardware. And since g4x can send infoframes to
2529 * only one port anyway, nothing is lost by allowing it.
2531 if (IS_G4X(dev_priv))
2532 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2534 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2535 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2536 intel_dig_port->max_lanes = 4;
2538 intel_infoframe_init(intel_dig_port);
2540 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
2541 intel_hdmi_init_connector(intel_dig_port, intel_connector);