2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_hdcp.h>
38 #include <drm/drm_scdc_helper.h>
39 #include "intel_drv.h"
40 #include <drm/i915_drm.h>
41 #include <drm/intel_lpe_audio.h>
44 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
46 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
50 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
52 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
53 struct drm_i915_private *dev_priv = to_i915(dev);
56 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
58 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
59 "HDMI port enabled, expecting disabled\n");
63 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
64 enum transcoder cpu_transcoder)
66 WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
67 TRANS_DDI_FUNC_ENABLE,
68 "HDMI transcoder function enabled, expecting disabled\n");
71 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
73 struct intel_digital_port *intel_dig_port =
74 container_of(encoder, struct intel_digital_port, base.base);
75 return &intel_dig_port->hdmi;
78 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
80 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
83 static u32 g4x_infoframe_index(unsigned int type)
86 case HDMI_INFOFRAME_TYPE_AVI:
87 return VIDEO_DIP_SELECT_AVI;
88 case HDMI_INFOFRAME_TYPE_SPD:
89 return VIDEO_DIP_SELECT_SPD;
90 case HDMI_INFOFRAME_TYPE_VENDOR:
91 return VIDEO_DIP_SELECT_VENDOR;
98 static u32 g4x_infoframe_enable(unsigned int type)
101 case HDMI_INFOFRAME_TYPE_AVI:
102 return VIDEO_DIP_ENABLE_AVI;
103 case HDMI_INFOFRAME_TYPE_SPD:
104 return VIDEO_DIP_ENABLE_SPD;
105 case HDMI_INFOFRAME_TYPE_VENDOR:
106 return VIDEO_DIP_ENABLE_VENDOR;
113 static u32 hsw_infoframe_enable(unsigned int type)
117 return VIDEO_DIP_ENABLE_VSC_HSW;
118 case HDMI_INFOFRAME_TYPE_AVI:
119 return VIDEO_DIP_ENABLE_AVI_HSW;
120 case HDMI_INFOFRAME_TYPE_SPD:
121 return VIDEO_DIP_ENABLE_SPD_HSW;
122 case HDMI_INFOFRAME_TYPE_VENDOR:
123 return VIDEO_DIP_ENABLE_VS_HSW;
131 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
132 enum transcoder cpu_transcoder,
138 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
139 case HDMI_INFOFRAME_TYPE_AVI:
140 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
141 case HDMI_INFOFRAME_TYPE_SPD:
142 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
143 case HDMI_INFOFRAME_TYPE_VENDOR:
144 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
147 return INVALID_MMIO_REG;
151 static void g4x_write_infoframe(struct drm_encoder *encoder,
152 const struct intel_crtc_state *crtc_state,
154 const void *frame, ssize_t len)
156 const u32 *data = frame;
157 struct drm_device *dev = encoder->dev;
158 struct drm_i915_private *dev_priv = to_i915(dev);
159 u32 val = I915_READ(VIDEO_DIP_CTL);
162 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
164 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
165 val |= g4x_infoframe_index(type);
167 val &= ~g4x_infoframe_enable(type);
169 I915_WRITE(VIDEO_DIP_CTL, val);
172 for (i = 0; i < len; i += 4) {
173 I915_WRITE(VIDEO_DIP_DATA, *data);
176 /* Write every possible data byte to force correct ECC calculation. */
177 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
178 I915_WRITE(VIDEO_DIP_DATA, 0);
181 val |= g4x_infoframe_enable(type);
182 val &= ~VIDEO_DIP_FREQ_MASK;
183 val |= VIDEO_DIP_FREQ_VSYNC;
185 I915_WRITE(VIDEO_DIP_CTL, val);
186 POSTING_READ(VIDEO_DIP_CTL);
189 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
190 const struct intel_crtc_state *pipe_config)
192 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
193 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
194 u32 val = I915_READ(VIDEO_DIP_CTL);
196 if ((val & VIDEO_DIP_ENABLE) == 0)
199 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
202 return val & (VIDEO_DIP_ENABLE_AVI |
203 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
206 static void ibx_write_infoframe(struct drm_encoder *encoder,
207 const struct intel_crtc_state *crtc_state,
209 const void *frame, ssize_t len)
211 const u32 *data = frame;
212 struct drm_device *dev = encoder->dev;
213 struct drm_i915_private *dev_priv = to_i915(dev);
214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
215 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
216 u32 val = I915_READ(reg);
219 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
221 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
222 val |= g4x_infoframe_index(type);
224 val &= ~g4x_infoframe_enable(type);
226 I915_WRITE(reg, val);
229 for (i = 0; i < len; i += 4) {
230 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
233 /* Write every possible data byte to force correct ECC calculation. */
234 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
235 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
238 val |= g4x_infoframe_enable(type);
239 val &= ~VIDEO_DIP_FREQ_MASK;
240 val |= VIDEO_DIP_FREQ_VSYNC;
242 I915_WRITE(reg, val);
246 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
247 const struct intel_crtc_state *pipe_config)
249 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
250 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
251 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
252 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
253 u32 val = I915_READ(reg);
255 if ((val & VIDEO_DIP_ENABLE) == 0)
258 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
261 return val & (VIDEO_DIP_ENABLE_AVI |
262 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
263 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
266 static void cpt_write_infoframe(struct drm_encoder *encoder,
267 const struct intel_crtc_state *crtc_state,
269 const void *frame, ssize_t len)
271 const u32 *data = frame;
272 struct drm_device *dev = encoder->dev;
273 struct drm_i915_private *dev_priv = to_i915(dev);
274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
275 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
276 u32 val = I915_READ(reg);
279 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
281 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
282 val |= g4x_infoframe_index(type);
284 /* The DIP control register spec says that we need to update the AVI
285 * infoframe without clearing its enable bit */
286 if (type != HDMI_INFOFRAME_TYPE_AVI)
287 val &= ~g4x_infoframe_enable(type);
289 I915_WRITE(reg, val);
292 for (i = 0; i < len; i += 4) {
293 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
296 /* Write every possible data byte to force correct ECC calculation. */
297 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
298 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
301 val |= g4x_infoframe_enable(type);
302 val &= ~VIDEO_DIP_FREQ_MASK;
303 val |= VIDEO_DIP_FREQ_VSYNC;
305 I915_WRITE(reg, val);
309 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
310 const struct intel_crtc_state *pipe_config)
312 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
313 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
314 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
316 if ((val & VIDEO_DIP_ENABLE) == 0)
319 return val & (VIDEO_DIP_ENABLE_AVI |
320 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
321 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
324 static void vlv_write_infoframe(struct drm_encoder *encoder,
325 const struct intel_crtc_state *crtc_state,
327 const void *frame, ssize_t len)
329 const u32 *data = frame;
330 struct drm_device *dev = encoder->dev;
331 struct drm_i915_private *dev_priv = to_i915(dev);
332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
333 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
334 u32 val = I915_READ(reg);
337 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
339 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
340 val |= g4x_infoframe_index(type);
342 val &= ~g4x_infoframe_enable(type);
344 I915_WRITE(reg, val);
347 for (i = 0; i < len; i += 4) {
348 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
351 /* Write every possible data byte to force correct ECC calculation. */
352 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
353 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
356 val |= g4x_infoframe_enable(type);
357 val &= ~VIDEO_DIP_FREQ_MASK;
358 val |= VIDEO_DIP_FREQ_VSYNC;
360 I915_WRITE(reg, val);
364 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
365 const struct intel_crtc_state *pipe_config)
367 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
368 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
369 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
370 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
372 if ((val & VIDEO_DIP_ENABLE) == 0)
375 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port))
378 return val & (VIDEO_DIP_ENABLE_AVI |
379 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
380 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
383 static void hsw_write_infoframe(struct drm_encoder *encoder,
384 const struct intel_crtc_state *crtc_state,
386 const void *frame, ssize_t len)
388 const u32 *data = frame;
389 struct drm_device *dev = encoder->dev;
390 struct drm_i915_private *dev_priv = to_i915(dev);
391 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
392 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
393 int data_size = type == DP_SDP_VSC ?
394 VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
396 u32 val = I915_READ(ctl_reg);
398 val &= ~hsw_infoframe_enable(type);
399 I915_WRITE(ctl_reg, val);
402 for (i = 0; i < len; i += 4) {
403 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
404 type, i >> 2), *data);
407 /* Write every possible data byte to force correct ECC calculation. */
408 for (; i < data_size; i += 4)
409 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
413 val |= hsw_infoframe_enable(type);
414 I915_WRITE(ctl_reg, val);
415 POSTING_READ(ctl_reg);
418 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
419 const struct intel_crtc_state *pipe_config)
421 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
422 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
424 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
425 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
426 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
430 * The data we write to the DIP data buffer registers is 1 byte bigger than the
431 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
432 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
433 * used for both technologies.
435 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
436 * DW1: DB3 | DB2 | DB1 | DB0
437 * DW2: DB7 | DB6 | DB5 | DB4
440 * (HB is Header Byte, DB is Data Byte)
442 * The hdmi pack() functions don't know about that hardware specific hole so we
443 * trick them by giving an offset into the buffer and moving back the header
446 static void intel_write_infoframe(struct drm_encoder *encoder,
447 const struct intel_crtc_state *crtc_state,
448 union hdmi_infoframe *frame)
450 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
451 u8 buffer[VIDEO_DIP_DATA_SIZE];
454 /* see comment above for the reason for this offset */
455 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
459 /* Insert the 'hole' (see big comment above) at position 3 */
460 buffer[0] = buffer[1];
461 buffer[1] = buffer[2];
462 buffer[2] = buffer[3];
466 intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
469 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
470 const struct intel_crtc_state *crtc_state,
471 const struct drm_connector_state *conn_state)
473 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
474 const struct drm_display_mode *adjusted_mode =
475 &crtc_state->base.adjusted_mode;
476 struct drm_connector *connector = &intel_hdmi->attached_connector->base;
477 bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported;
478 union hdmi_infoframe frame;
481 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
485 DRM_ERROR("couldn't fill AVI infoframe\n");
489 if (crtc_state->ycbcr420)
490 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
492 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
494 drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
495 crtc_state->limited_color_range ?
496 HDMI_QUANTIZATION_RANGE_LIMITED :
497 HDMI_QUANTIZATION_RANGE_FULL,
498 intel_hdmi->rgb_quant_range_selectable,
501 drm_hdmi_avi_infoframe_content_type(&frame.avi,
504 /* TODO: handle pixel repetition for YCBCR420 outputs */
505 intel_write_infoframe(encoder, crtc_state, &frame);
508 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder,
509 const struct intel_crtc_state *crtc_state)
511 union hdmi_infoframe frame;
514 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
516 DRM_ERROR("couldn't fill SPD infoframe\n");
520 frame.spd.sdi = HDMI_SPD_SDI_PC;
522 intel_write_infoframe(encoder, crtc_state, &frame);
526 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
527 const struct intel_crtc_state *crtc_state,
528 const struct drm_connector_state *conn_state)
530 union hdmi_infoframe frame;
533 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
534 conn_state->connector,
535 &crtc_state->base.adjusted_mode);
539 intel_write_infoframe(encoder, crtc_state, &frame);
542 static void g4x_set_infoframes(struct drm_encoder *encoder,
544 const struct intel_crtc_state *crtc_state,
545 const struct drm_connector_state *conn_state)
547 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
548 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
549 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
550 i915_reg_t reg = VIDEO_DIP_CTL;
551 u32 val = I915_READ(reg);
552 u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
554 assert_hdmi_port_disabled(intel_hdmi);
556 /* If the registers were not initialized yet, they might be zeroes,
557 * which means we're selecting the AVI DIP and we're setting its
558 * frequency to once. This seems to really confuse the HW and make
559 * things stop working (the register spec says the AVI always needs to
560 * be sent every VSync). So here we avoid writing to the register more
561 * than we need and also explicitly select the AVI DIP and explicitly
562 * set its frequency to every VSync. Avoiding to write it twice seems to
563 * be enough to solve the problem, but being defensive shouldn't hurt us
565 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
568 if (!(val & VIDEO_DIP_ENABLE))
570 if (port != (val & VIDEO_DIP_PORT_MASK)) {
571 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
572 (val & VIDEO_DIP_PORT_MASK) >> 29);
575 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
576 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
577 I915_WRITE(reg, val);
582 if (port != (val & VIDEO_DIP_PORT_MASK)) {
583 if (val & VIDEO_DIP_ENABLE) {
584 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
585 (val & VIDEO_DIP_PORT_MASK) >> 29);
588 val &= ~VIDEO_DIP_PORT_MASK;
592 val |= VIDEO_DIP_ENABLE;
593 val &= ~(VIDEO_DIP_ENABLE_AVI |
594 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
596 I915_WRITE(reg, val);
599 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
600 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
601 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
604 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
606 struct drm_connector *connector = conn_state->connector;
609 * HDMI cloning is only supported on g4x which doesn't
610 * support deep color or GCP infoframes anyway so no
611 * need to worry about multiple HDMI sinks here.
614 return connector->display_info.bpc > 8;
618 * Determine if default_phase=1 can be indicated in the GCP infoframe.
620 * From HDMI specification 1.4a:
621 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
622 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
623 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
624 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
627 static bool gcp_default_phase_possible(int pipe_bpp,
628 const struct drm_display_mode *mode)
630 unsigned int pixels_per_group;
634 /* 4 pixels in 5 clocks */
635 pixels_per_group = 4;
638 /* 2 pixels in 3 clocks */
639 pixels_per_group = 2;
642 /* 1 pixel in 2 clocks */
643 pixels_per_group = 1;
646 /* phase information not relevant for 8bpc */
650 return mode->crtc_hdisplay % pixels_per_group == 0 &&
651 mode->crtc_htotal % pixels_per_group == 0 &&
652 mode->crtc_hblank_start % pixels_per_group == 0 &&
653 mode->crtc_hblank_end % pixels_per_group == 0 &&
654 mode->crtc_hsync_start % pixels_per_group == 0 &&
655 mode->crtc_hsync_end % pixels_per_group == 0 &&
656 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
657 mode->crtc_htotal/2 % pixels_per_group == 0);
660 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder,
661 const struct intel_crtc_state *crtc_state,
662 const struct drm_connector_state *conn_state)
664 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
665 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
669 if (HAS_DDI(dev_priv))
670 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
671 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
672 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
673 else if (HAS_PCH_SPLIT(dev_priv))
674 reg = TVIDEO_DIP_GCP(crtc->pipe);
678 /* Indicate color depth whenever the sink supports deep color */
679 if (hdmi_sink_is_deep_color(conn_state))
680 val |= GCP_COLOR_INDICATION;
682 /* Enable default_phase whenever the display mode is suitably aligned */
683 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
684 &crtc_state->base.adjusted_mode))
685 val |= GCP_DEFAULT_PHASE_ENABLE;
687 I915_WRITE(reg, val);
692 static void ibx_set_infoframes(struct drm_encoder *encoder,
694 const struct intel_crtc_state *crtc_state,
695 const struct drm_connector_state *conn_state)
697 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
699 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
700 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
701 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
702 u32 val = I915_READ(reg);
703 u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
705 assert_hdmi_port_disabled(intel_hdmi);
707 /* See the big comment in g4x_set_infoframes() */
708 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
711 if (!(val & VIDEO_DIP_ENABLE))
713 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
714 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
715 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
716 I915_WRITE(reg, val);
721 if (port != (val & VIDEO_DIP_PORT_MASK)) {
722 WARN(val & VIDEO_DIP_ENABLE,
723 "DIP already enabled on port %c\n",
724 (val & VIDEO_DIP_PORT_MASK) >> 29);
725 val &= ~VIDEO_DIP_PORT_MASK;
729 val |= VIDEO_DIP_ENABLE;
730 val &= ~(VIDEO_DIP_ENABLE_AVI |
731 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
732 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
734 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
735 val |= VIDEO_DIP_ENABLE_GCP;
737 I915_WRITE(reg, val);
740 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
741 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
742 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
745 static void cpt_set_infoframes(struct drm_encoder *encoder,
747 const struct intel_crtc_state *crtc_state,
748 const struct drm_connector_state *conn_state)
750 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
752 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
753 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
754 u32 val = I915_READ(reg);
756 assert_hdmi_port_disabled(intel_hdmi);
758 /* See the big comment in g4x_set_infoframes() */
759 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
762 if (!(val & VIDEO_DIP_ENABLE))
764 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
765 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
766 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
767 I915_WRITE(reg, val);
772 /* Set both together, unset both together: see the spec. */
773 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
774 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
775 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
777 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
778 val |= VIDEO_DIP_ENABLE_GCP;
780 I915_WRITE(reg, val);
783 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
784 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
785 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
788 static void vlv_set_infoframes(struct drm_encoder *encoder,
790 const struct intel_crtc_state *crtc_state,
791 const struct drm_connector_state *conn_state)
793 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
794 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
796 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
797 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
798 u32 val = I915_READ(reg);
799 u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port);
801 assert_hdmi_port_disabled(intel_hdmi);
803 /* See the big comment in g4x_set_infoframes() */
804 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
807 if (!(val & VIDEO_DIP_ENABLE))
809 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
810 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
811 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
812 I915_WRITE(reg, val);
817 if (port != (val & VIDEO_DIP_PORT_MASK)) {
818 WARN(val & VIDEO_DIP_ENABLE,
819 "DIP already enabled on port %c\n",
820 (val & VIDEO_DIP_PORT_MASK) >> 29);
821 val &= ~VIDEO_DIP_PORT_MASK;
825 val |= VIDEO_DIP_ENABLE;
826 val &= ~(VIDEO_DIP_ENABLE_AVI |
827 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
828 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
830 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
831 val |= VIDEO_DIP_ENABLE_GCP;
833 I915_WRITE(reg, val);
836 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
837 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
838 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
841 static void hsw_set_infoframes(struct drm_encoder *encoder,
843 const struct intel_crtc_state *crtc_state,
844 const struct drm_connector_state *conn_state)
846 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
847 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
848 u32 val = I915_READ(reg);
850 assert_hdmi_transcoder_func_disabled(dev_priv,
851 crtc_state->cpu_transcoder);
853 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
854 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
855 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
858 I915_WRITE(reg, val);
863 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
864 val |= VIDEO_DIP_ENABLE_GCP_HSW;
866 I915_WRITE(reg, val);
869 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
870 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
871 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
874 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
876 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
877 struct i2c_adapter *adapter =
878 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
880 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
883 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
884 enable ? "Enabling" : "Disabling");
886 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
890 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
891 unsigned int offset, void *buffer, size_t size)
893 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
894 struct drm_i915_private *dev_priv =
895 intel_dig_port->base.base.dev->dev_private;
896 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
899 u8 start = offset & 0xff;
900 struct i2c_msg msgs[] = {
902 .addr = DRM_HDCP_DDC_ADDR,
908 .addr = DRM_HDCP_DDC_ADDR,
914 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
915 if (ret == ARRAY_SIZE(msgs))
917 return ret >= 0 ? -EIO : ret;
920 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
921 unsigned int offset, void *buffer, size_t size)
923 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
924 struct drm_i915_private *dev_priv =
925 intel_dig_port->base.base.dev->dev_private;
926 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
932 write_buf = kzalloc(size + 1, GFP_KERNEL);
936 write_buf[0] = offset & 0xff;
937 memcpy(&write_buf[1], buffer, size);
939 msg.addr = DRM_HDCP_DDC_ADDR;
944 ret = i2c_transfer(adapter, &msg, 1);
947 return ret >= 0 ? -EIO : ret;
951 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
954 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
955 struct drm_i915_private *dev_priv =
956 intel_dig_port->base.base.dev->dev_private;
957 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
961 ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
964 DRM_ERROR("Write An over DDC failed (%d)\n", ret);
968 ret = intel_gmbus_output_aksv(adapter);
970 DRM_ERROR("Failed to output aksv (%d)\n", ret);
976 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
980 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
983 DRM_ERROR("Read Bksv over DDC failed (%d)\n", ret);
988 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
992 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
993 bstatus, DRM_HDCP_BSTATUS_LEN);
995 DRM_ERROR("Read bstatus over DDC failed (%d)\n", ret);
1000 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1001 bool *repeater_present)
1006 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1008 DRM_ERROR("Read bcaps over DDC failed (%d)\n", ret);
1011 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1016 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1020 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1021 ri_prime, DRM_HDCP_RI_LEN);
1023 DRM_ERROR("Read Ri' over DDC failed (%d)\n", ret);
1028 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1034 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1036 DRM_ERROR("Read bcaps over DDC failed (%d)\n", ret);
1039 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1044 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1045 int num_downstream, u8 *ksv_fifo)
1048 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1049 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1051 DRM_ERROR("Read ksv fifo over DDC failed (%d)\n", ret);
1058 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1063 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1066 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1067 part, DRM_HDCP_V_PRIME_PART_LEN);
1069 DRM_ERROR("Read V'[%d] over DDC failed (%d)\n", i, ret);
1074 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1080 usleep_range(6, 60); /* Bspec says >= 6us */
1082 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1084 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1085 enable ? "Enable" : "Disable", ret);
1092 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1094 struct drm_i915_private *dev_priv =
1095 intel_dig_port->base.base.dev->dev_private;
1096 enum port port = intel_dig_port->base.port;
1100 u8 shim[DRM_HDCP_RI_LEN];
1103 ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1107 I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
1109 /* Wait for Ri prime match */
1110 if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
1111 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1112 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1113 I915_READ(PORT_HDCP_STATUS(port)));
1119 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1120 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1121 .read_bksv = intel_hdmi_hdcp_read_bksv,
1122 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1123 .repeater_present = intel_hdmi_hdcp_repeater_present,
1124 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1125 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1126 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1127 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1128 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1129 .check_link = intel_hdmi_hdcp_check_link,
1132 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1133 const struct intel_crtc_state *crtc_state)
1135 struct drm_device *dev = encoder->base.dev;
1136 struct drm_i915_private *dev_priv = to_i915(dev);
1137 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1138 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1139 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1142 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1144 hdmi_val = SDVO_ENCODING_HDMI;
1145 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1146 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1147 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1148 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1149 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1150 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1152 if (crtc_state->pipe_bpp > 24)
1153 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1155 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1157 if (crtc_state->has_hdmi_sink)
1158 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1160 if (HAS_PCH_CPT(dev_priv))
1161 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1162 else if (IS_CHERRYVIEW(dev_priv))
1163 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1165 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1167 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1168 POSTING_READ(intel_hdmi->hdmi_reg);
1171 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1174 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1175 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1178 if (!intel_display_power_get_if_enabled(dev_priv,
1179 encoder->power_domain))
1182 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1184 intel_display_power_put(dev_priv, encoder->power_domain);
1189 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1190 struct intel_crtc_state *pipe_config)
1192 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1193 struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
1194 struct drm_device *dev = encoder->base.dev;
1195 struct drm_i915_private *dev_priv = to_i915(dev);
1199 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1201 tmp = I915_READ(intel_hdmi->hdmi_reg);
1203 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1204 flags |= DRM_MODE_FLAG_PHSYNC;
1206 flags |= DRM_MODE_FLAG_NHSYNC;
1208 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1209 flags |= DRM_MODE_FLAG_PVSYNC;
1211 flags |= DRM_MODE_FLAG_NVSYNC;
1213 if (tmp & HDMI_MODE_SELECT_HDMI)
1214 pipe_config->has_hdmi_sink = true;
1216 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
1217 pipe_config->has_infoframe = true;
1219 if (tmp & SDVO_AUDIO_ENABLE)
1220 pipe_config->has_audio = true;
1222 if (!HAS_PCH_SPLIT(dev_priv) &&
1223 tmp & HDMI_COLOR_RANGE_16_235)
1224 pipe_config->limited_color_range = true;
1226 pipe_config->base.adjusted_mode.flags |= flags;
1228 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1229 dotclock = pipe_config->port_clock * 2 / 3;
1231 dotclock = pipe_config->port_clock;
1233 if (pipe_config->pixel_multiplier)
1234 dotclock /= pipe_config->pixel_multiplier;
1236 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1238 pipe_config->lane_count = 4;
1241 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1242 const struct intel_crtc_state *pipe_config,
1243 const struct drm_connector_state *conn_state)
1245 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1247 WARN_ON(!pipe_config->has_hdmi_sink);
1248 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1249 pipe_name(crtc->pipe));
1250 intel_audio_codec_enable(encoder, pipe_config, conn_state);
1253 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1254 const struct intel_crtc_state *pipe_config,
1255 const struct drm_connector_state *conn_state)
1257 struct drm_device *dev = encoder->base.dev;
1258 struct drm_i915_private *dev_priv = to_i915(dev);
1259 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1262 temp = I915_READ(intel_hdmi->hdmi_reg);
1264 temp |= SDVO_ENABLE;
1265 if (pipe_config->has_audio)
1266 temp |= SDVO_AUDIO_ENABLE;
1268 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1269 POSTING_READ(intel_hdmi->hdmi_reg);
1271 if (pipe_config->has_audio)
1272 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1275 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1276 const struct intel_crtc_state *pipe_config,
1277 const struct drm_connector_state *conn_state)
1279 struct drm_device *dev = encoder->base.dev;
1280 struct drm_i915_private *dev_priv = to_i915(dev);
1281 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1284 temp = I915_READ(intel_hdmi->hdmi_reg);
1286 temp |= SDVO_ENABLE;
1287 if (pipe_config->has_audio)
1288 temp |= SDVO_AUDIO_ENABLE;
1291 * HW workaround, need to write this twice for issue
1292 * that may result in first write getting masked.
1294 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1295 POSTING_READ(intel_hdmi->hdmi_reg);
1296 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1297 POSTING_READ(intel_hdmi->hdmi_reg);
1300 * HW workaround, need to toggle enable bit off and on
1301 * for 12bpc with pixel repeat.
1303 * FIXME: BSpec says this should be done at the end of
1304 * of the modeset sequence, so not sure if this isn't too soon.
1306 if (pipe_config->pipe_bpp > 24 &&
1307 pipe_config->pixel_multiplier > 1) {
1308 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1309 POSTING_READ(intel_hdmi->hdmi_reg);
1312 * HW workaround, need to write this twice for issue
1313 * that may result in first write getting masked.
1315 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1316 POSTING_READ(intel_hdmi->hdmi_reg);
1317 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1318 POSTING_READ(intel_hdmi->hdmi_reg);
1321 if (pipe_config->has_audio)
1322 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1325 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1326 const struct intel_crtc_state *pipe_config,
1327 const struct drm_connector_state *conn_state)
1329 struct drm_device *dev = encoder->base.dev;
1330 struct drm_i915_private *dev_priv = to_i915(dev);
1331 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1332 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1333 enum pipe pipe = crtc->pipe;
1336 temp = I915_READ(intel_hdmi->hdmi_reg);
1338 temp |= SDVO_ENABLE;
1339 if (pipe_config->has_audio)
1340 temp |= SDVO_AUDIO_ENABLE;
1343 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1345 * The procedure for 12bpc is as follows:
1346 * 1. disable HDMI clock gating
1347 * 2. enable HDMI with 8bpc
1348 * 3. enable HDMI with 12bpc
1349 * 4. enable HDMI clock gating
1352 if (pipe_config->pipe_bpp > 24) {
1353 I915_WRITE(TRANS_CHICKEN1(pipe),
1354 I915_READ(TRANS_CHICKEN1(pipe)) |
1355 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1357 temp &= ~SDVO_COLOR_FORMAT_MASK;
1358 temp |= SDVO_COLOR_FORMAT_8bpc;
1361 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1362 POSTING_READ(intel_hdmi->hdmi_reg);
1364 if (pipe_config->pipe_bpp > 24) {
1365 temp &= ~SDVO_COLOR_FORMAT_MASK;
1366 temp |= HDMI_COLOR_FORMAT_12bpc;
1368 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1369 POSTING_READ(intel_hdmi->hdmi_reg);
1371 I915_WRITE(TRANS_CHICKEN1(pipe),
1372 I915_READ(TRANS_CHICKEN1(pipe)) &
1373 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1376 if (pipe_config->has_audio)
1377 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1380 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1381 const struct intel_crtc_state *pipe_config,
1382 const struct drm_connector_state *conn_state)
1386 static void intel_disable_hdmi(struct intel_encoder *encoder,
1387 const struct intel_crtc_state *old_crtc_state,
1388 const struct drm_connector_state *old_conn_state)
1390 struct drm_device *dev = encoder->base.dev;
1391 struct drm_i915_private *dev_priv = to_i915(dev);
1392 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1393 struct intel_digital_port *intel_dig_port =
1394 hdmi_to_dig_port(intel_hdmi);
1395 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1398 temp = I915_READ(intel_hdmi->hdmi_reg);
1400 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1401 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1402 POSTING_READ(intel_hdmi->hdmi_reg);
1405 * HW workaround for IBX, we need to move the port
1406 * to transcoder A after disabling it to allow the
1407 * matching DP port to be enabled on transcoder A.
1409 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1411 * We get CPU/PCH FIFO underruns on the other pipe when
1412 * doing the workaround. Sweep them under the rug.
1414 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1415 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1417 temp &= ~SDVO_PIPE_SEL_MASK;
1418 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1420 * HW workaround, need to write this twice for issue
1421 * that may result in first write getting masked.
1423 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1424 POSTING_READ(intel_hdmi->hdmi_reg);
1425 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1426 POSTING_READ(intel_hdmi->hdmi_reg);
1428 temp &= ~SDVO_ENABLE;
1429 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1430 POSTING_READ(intel_hdmi->hdmi_reg);
1432 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1433 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1434 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1437 intel_dig_port->set_infoframes(&encoder->base, false,
1438 old_crtc_state, old_conn_state);
1440 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1443 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1444 const struct intel_crtc_state *old_crtc_state,
1445 const struct drm_connector_state *old_conn_state)
1447 if (old_crtc_state->has_audio)
1448 intel_audio_codec_disable(encoder,
1449 old_crtc_state, old_conn_state);
1451 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1454 static void pch_disable_hdmi(struct intel_encoder *encoder,
1455 const struct intel_crtc_state *old_crtc_state,
1456 const struct drm_connector_state *old_conn_state)
1458 if (old_crtc_state->has_audio)
1459 intel_audio_codec_disable(encoder,
1460 old_crtc_state, old_conn_state);
1463 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1464 const struct intel_crtc_state *old_crtc_state,
1465 const struct drm_connector_state *old_conn_state)
1467 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1470 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1472 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1473 const struct ddi_vbt_port_info *info =
1474 &dev_priv->vbt.ddi_port_info[encoder->port];
1477 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1478 max_tmds_clock = 594000;
1479 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1480 max_tmds_clock = 300000;
1481 else if (INTEL_GEN(dev_priv) >= 5)
1482 max_tmds_clock = 225000;
1484 max_tmds_clock = 165000;
1486 if (info->max_tmds_clock)
1487 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1489 return max_tmds_clock;
1492 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1493 bool respect_downstream_limits,
1496 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1497 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1499 if (respect_downstream_limits) {
1500 struct intel_connector *connector = hdmi->attached_connector;
1501 const struct drm_display_info *info = &connector->base.display_info;
1503 if (hdmi->dp_dual_mode.max_tmds_clock)
1504 max_tmds_clock = min(max_tmds_clock,
1505 hdmi->dp_dual_mode.max_tmds_clock);
1507 if (info->max_tmds_clock)
1508 max_tmds_clock = min(max_tmds_clock,
1509 info->max_tmds_clock);
1510 else if (!hdmi->has_hdmi_sink || force_dvi)
1511 max_tmds_clock = min(max_tmds_clock, 165000);
1514 return max_tmds_clock;
1517 static enum drm_mode_status
1518 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1519 int clock, bool respect_downstream_limits,
1522 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1525 return MODE_CLOCK_LOW;
1526 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1527 return MODE_CLOCK_HIGH;
1529 /* BXT DPLL can't generate 223-240 MHz */
1530 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1531 return MODE_CLOCK_RANGE;
1533 /* CHV DPLL can't generate 216-240 MHz */
1534 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1535 return MODE_CLOCK_RANGE;
1540 static enum drm_mode_status
1541 intel_hdmi_mode_valid(struct drm_connector *connector,
1542 struct drm_display_mode *mode)
1544 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1545 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1546 struct drm_i915_private *dev_priv = to_i915(dev);
1547 enum drm_mode_status status;
1549 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1551 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1553 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1554 return MODE_NO_DBLESCAN;
1556 clock = mode->clock;
1558 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1561 if (clock > max_dotclk)
1562 return MODE_CLOCK_HIGH;
1564 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1567 if (drm_mode_is_420_only(&connector->display_info, mode))
1570 /* check if we can do 8bpc */
1571 status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1573 if (hdmi->has_hdmi_sink && !force_dvi) {
1574 /* if we can't do 8bpc we may still be able to do 12bpc */
1575 if (status != MODE_OK && !HAS_GMCH_DISPLAY(dev_priv))
1576 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
1579 /* if we can't do 8,12bpc we may still be able to do 10bpc */
1580 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
1581 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
1588 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1591 struct drm_i915_private *dev_priv =
1592 to_i915(crtc_state->base.crtc->dev);
1593 struct drm_atomic_state *state = crtc_state->base.state;
1594 struct drm_connector_state *connector_state;
1595 struct drm_connector *connector;
1598 if (HAS_GMCH_DISPLAY(dev_priv))
1601 if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
1604 if (crtc_state->pipe_bpp <= 8*3)
1607 if (!crtc_state->has_hdmi_sink)
1611 * HDMI deep color affects the clocks, so it's only possible
1612 * when not cloning with other encoder types.
1614 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1617 for_each_new_connector_in_state(state, connector, connector_state, i) {
1618 const struct drm_display_info *info = &connector->display_info;
1620 if (connector_state->crtc != crtc_state->base.crtc)
1623 if (crtc_state->ycbcr420) {
1624 const struct drm_hdmi_info *hdmi = &info->hdmi;
1626 if (bpc == 12 && !(hdmi->y420_dc_modes &
1627 DRM_EDID_YCBCR420_DC_36))
1629 else if (bpc == 10 && !(hdmi->y420_dc_modes &
1630 DRM_EDID_YCBCR420_DC_30))
1633 if (bpc == 12 && !(info->edid_hdmi_dc_modes &
1634 DRM_EDID_HDMI_DC_36))
1636 else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
1637 DRM_EDID_HDMI_DC_30))
1642 /* Display WA #1139: glk */
1643 if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1644 crtc_state->base.adjusted_mode.htotal > 5460)
1651 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1652 struct intel_crtc_state *config,
1653 int *clock_12bpc, int *clock_10bpc,
1656 struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1658 if (!connector->ycbcr_420_allowed) {
1659 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1663 /* YCBCR420 TMDS rate requirement is half the pixel clock */
1664 config->port_clock /= 2;
1668 config->ycbcr420 = true;
1670 /* YCBCR 420 output conversion needs a scaler */
1671 if (skl_update_scaler_crtc(config)) {
1672 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1676 intel_pch_panel_fitting(intel_crtc, config,
1677 DRM_MODE_SCALE_FULLSCREEN);
1682 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1683 struct intel_crtc_state *pipe_config,
1684 struct drm_connector_state *conn_state)
1686 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1687 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1688 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1689 struct drm_connector *connector = conn_state->connector;
1690 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
1691 struct intel_digital_connector_state *intel_conn_state =
1692 to_intel_digital_connector_state(conn_state);
1693 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1694 int clock_10bpc = clock_8bpc * 5 / 4;
1695 int clock_12bpc = clock_8bpc * 3 / 2;
1697 bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1699 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1702 pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1704 if (pipe_config->has_hdmi_sink)
1705 pipe_config->has_infoframe = true;
1707 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1708 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1709 pipe_config->limited_color_range =
1710 pipe_config->has_hdmi_sink &&
1711 drm_default_rgb_quant_range(adjusted_mode) ==
1712 HDMI_QUANTIZATION_RANGE_LIMITED;
1714 pipe_config->limited_color_range =
1715 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1718 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1719 pipe_config->pixel_multiplier = 2;
1725 if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
1726 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
1727 &clock_12bpc, &clock_10bpc,
1729 DRM_ERROR("Can't support YCBCR420 output\n");
1734 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1735 pipe_config->has_pch_encoder = true;
1737 if (pipe_config->has_hdmi_sink) {
1738 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1739 pipe_config->has_audio = intel_hdmi->has_audio;
1741 pipe_config->has_audio =
1742 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1746 * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
1747 * to check that the higher clock still fits within limits.
1749 if (hdmi_deep_color_possible(pipe_config, 12) &&
1750 hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
1751 true, force_dvi) == MODE_OK) {
1752 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1755 /* Need to adjust the port link by 1.5x for 12bpc. */
1756 pipe_config->port_clock = clock_12bpc;
1757 } else if (hdmi_deep_color_possible(pipe_config, 10) &&
1758 hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
1759 true, force_dvi) == MODE_OK) {
1760 DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
1761 desired_bpp = 10 * 3;
1763 /* Need to adjust the port link by 1.25x for 10bpc. */
1764 pipe_config->port_clock = clock_10bpc;
1766 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1769 pipe_config->port_clock = clock_8bpc;
1772 if (!pipe_config->bw_constrained) {
1773 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1774 pipe_config->pipe_bpp = desired_bpp;
1777 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1778 false, force_dvi) != MODE_OK) {
1779 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1783 /* Set user selected PAR to incoming mode's member */
1784 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1786 pipe_config->lane_count = 4;
1788 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
1789 IS_GEMINILAKE(dev_priv))) {
1790 if (scdc->scrambling.low_rates)
1791 pipe_config->hdmi_scrambling = true;
1793 if (pipe_config->port_clock > 340000) {
1794 pipe_config->hdmi_scrambling = true;
1795 pipe_config->hdmi_high_tmds_clock_ratio = true;
1803 intel_hdmi_unset_edid(struct drm_connector *connector)
1805 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1807 intel_hdmi->has_hdmi_sink = false;
1808 intel_hdmi->has_audio = false;
1809 intel_hdmi->rgb_quant_range_selectable = false;
1811 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1812 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1814 kfree(to_intel_connector(connector)->detect_edid);
1815 to_intel_connector(connector)->detect_edid = NULL;
1819 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1821 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1822 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1823 enum port port = hdmi_to_dig_port(hdmi)->base.port;
1824 struct i2c_adapter *adapter =
1825 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1826 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1829 * Type 1 DVI adaptors are not required to implement any
1830 * registers, so we can't always detect their presence.
1831 * Ideally we should be able to check the state of the
1832 * CONFIG1 pin, but no such luck on our hardware.
1834 * The only method left to us is to check the VBT to see
1835 * if the port is a dual mode capable DP port. But let's
1836 * only do that when we sucesfully read the EDID, to avoid
1837 * confusing log messages about DP dual mode adaptors when
1838 * there's nothing connected to the port.
1840 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1841 /* An overridden EDID imply that we want this port for testing.
1842 * Make sure not to set limits for that port.
1844 if (has_edid && !connector->override_edid &&
1845 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1846 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1847 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1849 type = DRM_DP_DUAL_MODE_NONE;
1853 if (type == DRM_DP_DUAL_MODE_NONE)
1856 hdmi->dp_dual_mode.type = type;
1857 hdmi->dp_dual_mode.max_tmds_clock =
1858 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1860 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1861 drm_dp_get_dual_mode_type_name(type),
1862 hdmi->dp_dual_mode.max_tmds_clock);
1866 intel_hdmi_set_edid(struct drm_connector *connector)
1868 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1869 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1871 bool connected = false;
1872 struct i2c_adapter *i2c;
1874 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1876 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
1878 edid = drm_get_edid(connector, i2c);
1880 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
1881 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
1882 intel_gmbus_force_bit(i2c, true);
1883 edid = drm_get_edid(connector, i2c);
1884 intel_gmbus_force_bit(i2c, false);
1887 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1889 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1891 to_intel_connector(connector)->detect_edid = edid;
1892 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1893 intel_hdmi->rgb_quant_range_selectable =
1894 drm_rgb_quant_range_selectable(edid);
1896 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1897 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1905 static enum drm_connector_status
1906 intel_hdmi_detect(struct drm_connector *connector, bool force)
1908 enum drm_connector_status status;
1909 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1911 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1912 connector->base.id, connector->name);
1914 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1916 intel_hdmi_unset_edid(connector);
1918 if (intel_hdmi_set_edid(connector))
1919 status = connector_status_connected;
1921 status = connector_status_disconnected;
1923 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1929 intel_hdmi_force(struct drm_connector *connector)
1931 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1932 connector->base.id, connector->name);
1934 intel_hdmi_unset_edid(connector);
1936 if (connector->status != connector_status_connected)
1939 intel_hdmi_set_edid(connector);
1942 static int intel_hdmi_get_modes(struct drm_connector *connector)
1946 edid = to_intel_connector(connector)->detect_edid;
1950 return intel_connector_update_modes(connector, edid);
1953 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1954 const struct intel_crtc_state *pipe_config,
1955 const struct drm_connector_state *conn_state)
1957 struct intel_digital_port *intel_dig_port =
1958 enc_to_dig_port(&encoder->base);
1960 intel_hdmi_prepare(encoder, pipe_config);
1962 intel_dig_port->set_infoframes(&encoder->base,
1963 pipe_config->has_infoframe,
1964 pipe_config, conn_state);
1967 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1968 const struct intel_crtc_state *pipe_config,
1969 const struct drm_connector_state *conn_state)
1971 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1972 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1974 vlv_phy_pre_encoder_enable(encoder, pipe_config);
1977 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1980 dport->set_infoframes(&encoder->base,
1981 pipe_config->has_infoframe,
1982 pipe_config, conn_state);
1984 g4x_enable_hdmi(encoder, pipe_config, conn_state);
1986 vlv_wait_port_ready(dev_priv, dport, 0x0);
1989 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1990 const struct intel_crtc_state *pipe_config,
1991 const struct drm_connector_state *conn_state)
1993 intel_hdmi_prepare(encoder, pipe_config);
1995 vlv_phy_pre_pll_enable(encoder, pipe_config);
1998 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1999 const struct intel_crtc_state *pipe_config,
2000 const struct drm_connector_state *conn_state)
2002 intel_hdmi_prepare(encoder, pipe_config);
2004 chv_phy_pre_pll_enable(encoder, pipe_config);
2007 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2008 const struct intel_crtc_state *old_crtc_state,
2009 const struct drm_connector_state *old_conn_state)
2011 chv_phy_post_pll_disable(encoder, old_crtc_state);
2014 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2015 const struct intel_crtc_state *old_crtc_state,
2016 const struct drm_connector_state *old_conn_state)
2018 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2019 vlv_phy_reset_lanes(encoder, old_crtc_state);
2022 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2023 const struct intel_crtc_state *old_crtc_state,
2024 const struct drm_connector_state *old_conn_state)
2026 struct drm_device *dev = encoder->base.dev;
2027 struct drm_i915_private *dev_priv = to_i915(dev);
2029 mutex_lock(&dev_priv->sb_lock);
2031 /* Assert data lane reset */
2032 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2034 mutex_unlock(&dev_priv->sb_lock);
2037 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2038 const struct intel_crtc_state *pipe_config,
2039 const struct drm_connector_state *conn_state)
2041 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2042 struct drm_device *dev = encoder->base.dev;
2043 struct drm_i915_private *dev_priv = to_i915(dev);
2045 chv_phy_pre_encoder_enable(encoder, pipe_config);
2047 /* FIXME: Program the support xxx V-dB */
2049 chv_set_phy_signal_level(encoder, 128, 102, false);
2051 dport->set_infoframes(&encoder->base,
2052 pipe_config->has_infoframe,
2053 pipe_config, conn_state);
2055 g4x_enable_hdmi(encoder, pipe_config, conn_state);
2057 vlv_wait_port_ready(dev_priv, dport, 0x0);
2059 /* Second common lane will stay alive on its own now */
2060 chv_phy_release_cl2_override(encoder);
2063 static void intel_hdmi_destroy(struct drm_connector *connector)
2065 kfree(to_intel_connector(connector)->detect_edid);
2066 drm_connector_cleanup(connector);
2070 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2071 .detect = intel_hdmi_detect,
2072 .force = intel_hdmi_force,
2073 .fill_modes = drm_helper_probe_single_connector_modes,
2074 .atomic_get_property = intel_digital_connector_atomic_get_property,
2075 .atomic_set_property = intel_digital_connector_atomic_set_property,
2076 .late_register = intel_connector_register,
2077 .early_unregister = intel_connector_unregister,
2078 .destroy = intel_hdmi_destroy,
2079 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2080 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2083 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2084 .get_modes = intel_hdmi_get_modes,
2085 .mode_valid = intel_hdmi_mode_valid,
2086 .atomic_check = intel_digital_connector_atomic_check,
2089 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2090 .destroy = intel_encoder_destroy,
2094 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2096 intel_attach_force_audio_property(connector);
2097 intel_attach_broadcast_rgb_property(connector);
2098 intel_attach_aspect_ratio_property(connector);
2099 drm_connector_attach_content_type_property(connector);
2100 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2104 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2105 * @encoder: intel_encoder
2106 * @connector: drm_connector
2107 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2108 * or reset the high tmds clock ratio for scrambling
2109 * @scrambling: bool to Indicate if the function needs to set or reset
2112 * This function handles scrambling on HDMI 2.0 capable sinks.
2113 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2114 * it enables scrambling. This should be called before enabling the HDMI
2115 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2116 * detect a scrambled clock within 100 ms.
2119 * True on success, false on failure.
2121 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2122 struct drm_connector *connector,
2123 bool high_tmds_clock_ratio,
2126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2127 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2128 struct drm_scrambling *sink_scrambling =
2129 &connector->display_info.hdmi.scdc.scrambling;
2130 struct i2c_adapter *adapter =
2131 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2133 if (!sink_scrambling->supported)
2136 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2137 connector->base.id, connector->name,
2138 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2140 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2141 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2142 high_tmds_clock_ratio) &&
2143 drm_scdc_set_scrambling(adapter, scrambling);
2146 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2152 ddc_pin = GMBUS_PIN_DPB;
2155 ddc_pin = GMBUS_PIN_DPC;
2158 ddc_pin = GMBUS_PIN_DPD_CHV;
2162 ddc_pin = GMBUS_PIN_DPB;
2168 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2174 ddc_pin = GMBUS_PIN_1_BXT;
2177 ddc_pin = GMBUS_PIN_2_BXT;
2181 ddc_pin = GMBUS_PIN_1_BXT;
2187 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2194 ddc_pin = GMBUS_PIN_1_BXT;
2197 ddc_pin = GMBUS_PIN_2_BXT;
2200 ddc_pin = GMBUS_PIN_4_CNP;
2203 ddc_pin = GMBUS_PIN_3_BXT;
2207 ddc_pin = GMBUS_PIN_1_BXT;
2213 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2219 ddc_pin = GMBUS_PIN_1_BXT;
2222 ddc_pin = GMBUS_PIN_2_BXT;
2225 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2228 ddc_pin = GMBUS_PIN_10_TC2_ICP;
2231 ddc_pin = GMBUS_PIN_11_TC3_ICP;
2234 ddc_pin = GMBUS_PIN_12_TC4_ICP;
2238 ddc_pin = GMBUS_PIN_2_BXT;
2244 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2251 ddc_pin = GMBUS_PIN_DPB;
2254 ddc_pin = GMBUS_PIN_DPC;
2257 ddc_pin = GMBUS_PIN_DPD;
2261 ddc_pin = GMBUS_PIN_DPB;
2267 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2270 const struct ddi_vbt_port_info *info =
2271 &dev_priv->vbt.ddi_port_info[port];
2274 if (info->alternate_ddc_pin) {
2275 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2276 info->alternate_ddc_pin, port_name(port));
2277 return info->alternate_ddc_pin;
2280 if (IS_CHERRYVIEW(dev_priv))
2281 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2282 else if (IS_GEN9_LP(dev_priv))
2283 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2284 else if (HAS_PCH_CNP(dev_priv))
2285 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2286 else if (HAS_PCH_ICP(dev_priv))
2287 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2289 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2291 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2292 ddc_pin, port_name(port));
2297 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
2299 struct drm_i915_private *dev_priv =
2300 to_i915(intel_dig_port->base.base.dev);
2302 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2303 intel_dig_port->write_infoframe = vlv_write_infoframe;
2304 intel_dig_port->set_infoframes = vlv_set_infoframes;
2305 intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
2306 } else if (IS_G4X(dev_priv)) {
2307 intel_dig_port->write_infoframe = g4x_write_infoframe;
2308 intel_dig_port->set_infoframes = g4x_set_infoframes;
2309 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
2310 } else if (HAS_DDI(dev_priv)) {
2311 intel_dig_port->write_infoframe = hsw_write_infoframe;
2312 intel_dig_port->set_infoframes = hsw_set_infoframes;
2313 intel_dig_port->infoframe_enabled = hsw_infoframe_enabled;
2314 } else if (HAS_PCH_IBX(dev_priv)) {
2315 intel_dig_port->write_infoframe = ibx_write_infoframe;
2316 intel_dig_port->set_infoframes = ibx_set_infoframes;
2317 intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
2319 intel_dig_port->write_infoframe = cpt_write_infoframe;
2320 intel_dig_port->set_infoframes = cpt_set_infoframes;
2321 intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
2325 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2326 struct intel_connector *intel_connector)
2328 struct drm_connector *connector = &intel_connector->base;
2329 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2330 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2331 struct drm_device *dev = intel_encoder->base.dev;
2332 struct drm_i915_private *dev_priv = to_i915(dev);
2333 enum port port = intel_encoder->port;
2335 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2338 if (WARN(intel_dig_port->max_lanes < 4,
2339 "Not enough lanes (%d) for HDMI on port %c\n",
2340 intel_dig_port->max_lanes, port_name(port)))
2343 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2344 DRM_MODE_CONNECTOR_HDMIA);
2345 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2347 connector->interlace_allowed = 1;
2348 connector->doublescan_allowed = 0;
2349 connector->stereo_allowed = 1;
2351 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2352 connector->ycbcr_420_allowed = true;
2354 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2356 if (WARN_ON(port == PORT_A))
2358 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
2360 if (HAS_DDI(dev_priv))
2361 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2363 intel_connector->get_hw_state = intel_connector_get_hw_state;
2365 intel_hdmi_add_properties(intel_hdmi, connector);
2367 if (is_hdcp_supported(dev_priv, port)) {
2368 int ret = intel_hdcp_init(intel_connector,
2369 &intel_hdmi_hdcp_shim);
2371 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
2374 intel_connector_attach_encoder(intel_connector, intel_encoder);
2375 intel_hdmi->attached_connector = intel_connector;
2377 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2378 * 0xd. Failure to do so will result in spurious interrupts being
2379 * generated on the port when a cable is not attached.
2381 if (IS_G45(dev_priv)) {
2382 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2383 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2387 void intel_hdmi_init(struct drm_i915_private *dev_priv,
2388 i915_reg_t hdmi_reg, enum port port)
2390 struct intel_digital_port *intel_dig_port;
2391 struct intel_encoder *intel_encoder;
2392 struct intel_connector *intel_connector;
2394 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2395 if (!intel_dig_port)
2398 intel_connector = intel_connector_alloc();
2399 if (!intel_connector) {
2400 kfree(intel_dig_port);
2404 intel_encoder = &intel_dig_port->base;
2406 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2407 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2408 "HDMI %c", port_name(port));
2410 intel_encoder->hotplug = intel_encoder_hotplug;
2411 intel_encoder->compute_config = intel_hdmi_compute_config;
2412 if (HAS_PCH_SPLIT(dev_priv)) {
2413 intel_encoder->disable = pch_disable_hdmi;
2414 intel_encoder->post_disable = pch_post_disable_hdmi;
2416 intel_encoder->disable = g4x_disable_hdmi;
2418 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2419 intel_encoder->get_config = intel_hdmi_get_config;
2420 if (IS_CHERRYVIEW(dev_priv)) {
2421 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2422 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2423 intel_encoder->enable = vlv_enable_hdmi;
2424 intel_encoder->post_disable = chv_hdmi_post_disable;
2425 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2426 } else if (IS_VALLEYVIEW(dev_priv)) {
2427 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2428 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2429 intel_encoder->enable = vlv_enable_hdmi;
2430 intel_encoder->post_disable = vlv_hdmi_post_disable;
2432 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2433 if (HAS_PCH_CPT(dev_priv))
2434 intel_encoder->enable = cpt_enable_hdmi;
2435 else if (HAS_PCH_IBX(dev_priv))
2436 intel_encoder->enable = ibx_enable_hdmi;
2438 intel_encoder->enable = g4x_enable_hdmi;
2441 intel_encoder->type = INTEL_OUTPUT_HDMI;
2442 intel_encoder->power_domain = intel_port_to_power_domain(port);
2443 intel_encoder->port = port;
2444 if (IS_CHERRYVIEW(dev_priv)) {
2446 intel_encoder->crtc_mask = 1 << 2;
2448 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2450 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2452 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2454 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2455 * to work on real hardware. And since g4x can send infoframes to
2456 * only one port anyway, nothing is lost by allowing it.
2458 if (IS_G4X(dev_priv))
2459 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2461 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2462 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2463 intel_dig_port->max_lanes = 4;
2465 intel_infoframe_init(intel_dig_port);
2467 intel_hdmi_init_connector(intel_dig_port, intel_connector);