drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_hdcp.h>
  37 #include <drm/drm_scdc_helper.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include <drm/intel_lpe_audio.h>
  41 #include "i915_drv.h"
  42
  43 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  44 {
  45         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  46 }
  47
  48 static void
  49 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  50 {
  51         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  52         struct drm_i915_private *dev_priv = to_i915(dev);
  53         u32 enabled_bits;
  54
  55         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  56
  57         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  58              "HDMI port enabled, expecting disabled\n");
  59 }
  60
  61 static void
  62 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
  63                                      enum transcoder cpu_transcoder)
  64 {
  65         WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
  66              TRANS_DDI_FUNC_ENABLE,
  67              "HDMI transcoder function enabled, expecting disabled\n");
  68 }
  69
  70 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  71 {
  72         struct intel_digital_port *intel_dig_port =
  73                 container_of(encoder, struct intel_digital_port, base.base);
  74         return &intel_dig_port->hdmi;
  75 }
  76
  77 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  78 {
  79         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  80 }
  81
  82 static u32 g4x_infoframe_index(unsigned int type)
  83 {
  84         switch (type) {
  85         case HDMI_INFOFRAME_TYPE_AVI:
  86                 return VIDEO_DIP_SELECT_AVI;
  87         case HDMI_INFOFRAME_TYPE_SPD:
  88                 return VIDEO_DIP_SELECT_SPD;
  89         case HDMI_INFOFRAME_TYPE_VENDOR:
  90                 return VIDEO_DIP_SELECT_VENDOR;
  91         default:
  92                 MISSING_CASE(type);
  93                 return 0;
  94         }
  95 }
  96
  97 static u32 g4x_infoframe_enable(unsigned int type)
  98 {
  99         switch (type) {
 100         case HDMI_INFOFRAME_TYPE_AVI:
 101                 return VIDEO_DIP_ENABLE_AVI;
 102         case HDMI_INFOFRAME_TYPE_SPD:
 103                 return VIDEO_DIP_ENABLE_SPD;
 104         case HDMI_INFOFRAME_TYPE_VENDOR:
 105                 return VIDEO_DIP_ENABLE_VENDOR;
 106         default:
 107                 MISSING_CASE(type);
 108                 return 0;
 109         }
 110 }
 111
 112 static u32 hsw_infoframe_enable(unsigned int type)
 113 {
 114         switch (type) {
 115         case DP_SDP_VSC:
 116                 return VIDEO_DIP_ENABLE_VSC_HSW;
 117         case DP_SDP_PPS:
 118                 return VDIP_ENABLE_PPS;
 119         case HDMI_INFOFRAME_TYPE_AVI:
 120                 return VIDEO_DIP_ENABLE_AVI_HSW;
 121         case HDMI_INFOFRAME_TYPE_SPD:
 122                 return VIDEO_DIP_ENABLE_SPD_HSW;
 123         case HDMI_INFOFRAME_TYPE_VENDOR:
 124                 return VIDEO_DIP_ENABLE_VS_HSW;
 125         default:
 126                 MISSING_CASE(type);
 127                 return 0;
 128         }
 129 }
 130
 131 static i915_reg_t
 132 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 133                  enum transcoder cpu_transcoder,
 134                  unsigned int type,
 135                  int i)
 136 {
 137         switch (type) {
 138         case DP_SDP_VSC:
 139                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 140         case DP_SDP_PPS:
 141                 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
 142         case HDMI_INFOFRAME_TYPE_AVI:
 143                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 144         case HDMI_INFOFRAME_TYPE_SPD:
 145                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 146         case HDMI_INFOFRAME_TYPE_VENDOR:
 147                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 148         default:
 149                 MISSING_CASE(type);
 150                 return INVALID_MMIO_REG;
 151         }
 152 }
 153
 154 static int hsw_dip_data_size(unsigned int type)
 155 {
 156         switch (type) {
 157         case DP_SDP_VSC:
 158                 return VIDEO_DIP_VSC_DATA_SIZE;
 159         case DP_SDP_PPS:
 160                 return VIDEO_DIP_PPS_DATA_SIZE;
 161         default:
 162                 return VIDEO_DIP_DATA_SIZE;
 163         }
 164 }
 165
 166 static void g4x_write_infoframe(struct intel_encoder *encoder,
 167                                 const struct intel_crtc_state *crtc_state,
 168                                 unsigned int type,
 169                                 const void *frame, ssize_t len)
 170 {
 171         const u32 *data = frame;
 172         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 173         u32 val = I915_READ(VIDEO_DIP_CTL);
 174         int i;
 175
 176         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 177
 178         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 179         val |= g4x_infoframe_index(type);
 180
 181         val &= ~g4x_infoframe_enable(type);
 182
 183         I915_WRITE(VIDEO_DIP_CTL, val);
 184
 185         mmiowb();
 186         for (i = 0; i < len; i += 4) {
 187                 I915_WRITE(VIDEO_DIP_DATA, *data);
 188                 data++;
 189         }
 190         /* Write every possible data byte to force correct ECC calculation. */
 191         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 192                 I915_WRITE(VIDEO_DIP_DATA, 0);
 193         mmiowb();
 194
 195         val |= g4x_infoframe_enable(type);
 196         val &= ~VIDEO_DIP_FREQ_MASK;
 197         val |= VIDEO_DIP_FREQ_VSYNC;
 198
 199         I915_WRITE(VIDEO_DIP_CTL, val);
 200         POSTING_READ(VIDEO_DIP_CTL);
 201 }
 202
 203 static bool g4x_infoframe_enabled(struct intel_encoder *encoder,
 204                                   const struct intel_crtc_state *pipe_config)
 205 {
 206         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 207         u32 val = I915_READ(VIDEO_DIP_CTL);
 208
 209         if ((val & VIDEO_DIP_ENABLE) == 0)
 210                 return false;
 211
 212         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 213                 return false;
 214
 215         return val & (VIDEO_DIP_ENABLE_AVI |
 216                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 217 }
 218
 219 static void ibx_write_infoframe(struct intel_encoder *encoder,
 220                                 const struct intel_crtc_state *crtc_state,
 221                                 unsigned int type,
 222                                 const void *frame, ssize_t len)
 223 {
 224         const u32 *data = frame;
 225         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 226         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 227         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 228         u32 val = I915_READ(reg);
 229         int i;
 230
 231         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 232
 233         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 234         val |= g4x_infoframe_index(type);
 235
 236         val &= ~g4x_infoframe_enable(type);
 237
 238         I915_WRITE(reg, val);
 239
 240         mmiowb();
 241         for (i = 0; i < len; i += 4) {
 242                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 243                 data++;
 244         }
 245         /* Write every possible data byte to force correct ECC calculation. */
 246         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 247                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 248         mmiowb();
 249
 250         val |= g4x_infoframe_enable(type);
 251         val &= ~VIDEO_DIP_FREQ_MASK;
 252         val |= VIDEO_DIP_FREQ_VSYNC;
 253
 254         I915_WRITE(reg, val);
 255         POSTING_READ(reg);
 256 }
 257
 258 static bool ibx_infoframe_enabled(struct intel_encoder *encoder,
 259                                   const struct intel_crtc_state *pipe_config)
 260 {
 261         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 262         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 263         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 264         u32 val = I915_READ(reg);
 265
 266         if ((val & VIDEO_DIP_ENABLE) == 0)
 267                 return false;
 268
 269         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 270                 return false;
 271
 272         return val & (VIDEO_DIP_ENABLE_AVI |
 273                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 274                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 275 }
 276
 277 static void cpt_write_infoframe(struct intel_encoder *encoder,
 278                                 const struct intel_crtc_state *crtc_state,
 279                                 unsigned int type,
 280                                 const void *frame, ssize_t len)
 281 {
 282         const u32 *data = frame;
 283         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 285         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 286         u32 val = I915_READ(reg);
 287         int i;
 288
 289         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 290
 291         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 292         val |= g4x_infoframe_index(type);
 293
 294         /* The DIP control register spec says that we need to update the AVI
 295          * infoframe without clearing its enable bit */
 296         if (type != HDMI_INFOFRAME_TYPE_AVI)
 297                 val &= ~g4x_infoframe_enable(type);
 298
 299         I915_WRITE(reg, val);
 300
 301         mmiowb();
 302         for (i = 0; i < len; i += 4) {
 303                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 304                 data++;
 305         }
 306         /* Write every possible data byte to force correct ECC calculation. */
 307         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 308                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 309         mmiowb();
 310
 311         val |= g4x_infoframe_enable(type);
 312         val &= ~VIDEO_DIP_FREQ_MASK;
 313         val |= VIDEO_DIP_FREQ_VSYNC;
 314
 315         I915_WRITE(reg, val);
 316         POSTING_READ(reg);
 317 }
 318
 319 static bool cpt_infoframe_enabled(struct intel_encoder *encoder,
 320                                   const struct intel_crtc_state *pipe_config)
 321 {
 322         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 323         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 324         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 325
 326         if ((val & VIDEO_DIP_ENABLE) == 0)
 327                 return false;
 328
 329         return val & (VIDEO_DIP_ENABLE_AVI |
 330                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 331                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 332 }
 333
 334 static void vlv_write_infoframe(struct intel_encoder *encoder,
 335                                 const struct intel_crtc_state *crtc_state,
 336                                 unsigned int type,
 337                                 const void *frame, ssize_t len)
 338 {
 339         const u32 *data = frame;
 340         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 342         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 343         u32 val = I915_READ(reg);
 344         int i;
 345
 346         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 347
 348         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 349         val |= g4x_infoframe_index(type);
 350
 351         val &= ~g4x_infoframe_enable(type);
 352
 353         I915_WRITE(reg, val);
 354
 355         mmiowb();
 356         for (i = 0; i < len; i += 4) {
 357                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 358                 data++;
 359         }
 360         /* Write every possible data byte to force correct ECC calculation. */
 361         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 362                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 363         mmiowb();
 364
 365         val |= g4x_infoframe_enable(type);
 366         val &= ~VIDEO_DIP_FREQ_MASK;
 367         val |= VIDEO_DIP_FREQ_VSYNC;
 368
 369         I915_WRITE(reg, val);
 370         POSTING_READ(reg);
 371 }
 372
 373 static bool vlv_infoframe_enabled(struct intel_encoder *encoder,
 374                                   const struct intel_crtc_state *pipe_config)
 375 {
 376         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 377         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 378         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 379
 380         if ((val & VIDEO_DIP_ENABLE) == 0)
 381                 return false;
 382
 383         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 384                 return false;
 385
 386         return val & (VIDEO_DIP_ENABLE_AVI |
 387                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 388                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 389 }
 390
 391 static void hsw_write_infoframe(struct intel_encoder *encoder,
 392                                 const struct intel_crtc_state *crtc_state,
 393                                 unsigned int type,
 394                                 const void *frame, ssize_t len)
 395 {
 396         const u32 *data = frame;
 397         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 398         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 399         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 400         int data_size;
 401         int i;
 402         u32 val = I915_READ(ctl_reg);
 403
 404         data_size = hsw_dip_data_size(type);
 405
 406         val &= ~hsw_infoframe_enable(type);
 407         I915_WRITE(ctl_reg, val);
 408
 409         mmiowb();
 410         for (i = 0; i < len; i += 4) {
 411                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 412                                             type, i >> 2), *data);
 413                 data++;
 414         }
 415         /* Write every possible data byte to force correct ECC calculation. */
 416         for (; i < data_size; i += 4)
 417                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 418                                             type, i >> 2), 0);
 419         mmiowb();
 420
 421         val |= hsw_infoframe_enable(type);
 422         I915_WRITE(ctl_reg, val);
 423         POSTING_READ(ctl_reg);
 424 }
 425
 426 static bool hsw_infoframe_enabled(struct intel_encoder *encoder,
 427                                   const struct intel_crtc_state *pipe_config)
 428 {
 429         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 430         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 431
 432         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 433                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 434                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 435 }
 436
 437 /*
 438  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 439  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 440  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 441  * used for both technologies.
 442  *
 443  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 444  * DW1:       DB3       | DB2 | DB1 | DB0
 445  * DW2:       DB7       | DB6 | DB5 | DB4
 446  * DW3: ...
 447  *
 448  * (HB is Header Byte, DB is Data Byte)
 449  *
 450  * The hdmi pack() functions don't know about that hardware specific hole so we
 451  * trick them by giving an offset into the buffer and moving back the header
 452  * bytes by one.
 453  */
 454 static void intel_write_infoframe(struct intel_encoder *encoder,
 455                                   const struct intel_crtc_state *crtc_state,
 456                                   union hdmi_infoframe *frame)
 457 {
 458         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 459         u8 buffer[VIDEO_DIP_DATA_SIZE];
 460         ssize_t len;
 461
 462         /* see comment above for the reason for this offset */
 463         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 464         if (len < 0)
 465                 return;
 466
 467         /* Insert the 'hole' (see big comment above) at position 3 */
 468         memmove(&buffer[0], &buffer[1], 3);
 469         buffer[3] = 0;
 470         len++;
 471
 472         intel_dig_port->write_infoframe(encoder,
 473                                         crtc_state,
 474                                         frame->any.type, buffer, len);
 475 }
 476
 477 static void intel_hdmi_set_avi_infoframe(struct intel_encoder *encoder,
 478                                          const struct intel_crtc_state *crtc_state,
 479                                          const struct drm_connector_state *conn_state)
 480 {
 481         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 482         const struct drm_display_mode *adjusted_mode =
 483                 &crtc_state->base.adjusted_mode;
 484         struct drm_connector *connector = &intel_hdmi->attached_connector->base;
 485         bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported ||
 486            connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
 487         union hdmi_infoframe frame;
 488         int ret;
 489
 490         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 491                                                        adjusted_mode,
 492                                                        is_hdmi2_sink);
 493         if (ret < 0) {
 494                 DRM_ERROR("couldn't fill AVI infoframe\n");
 495                 return;
 496         }
 497
 498         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 499                 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
 500         else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 501                 frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
 502         else
 503                 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
 504
 505         drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
 506                                            crtc_state->limited_color_range ?
 507                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 508                                            HDMI_QUANTIZATION_RANGE_FULL,
 509                                            intel_hdmi->rgb_quant_range_selectable,
 510                                            is_hdmi2_sink);
 511
 512         drm_hdmi_avi_infoframe_content_type(&frame.avi,
 513                                             conn_state);
 514
 515         /* TODO: handle pixel repetition for YCBCR420 outputs */
 516         intel_write_infoframe(encoder, crtc_state,
 517                               &frame);
 518 }
 519
 520 static void intel_hdmi_set_spd_infoframe(struct intel_encoder *encoder,
 521                                          const struct intel_crtc_state *crtc_state)
 522 {
 523         union hdmi_infoframe frame;
 524         int ret;
 525
 526         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 527         if (ret < 0) {
 528                 DRM_ERROR("couldn't fill SPD infoframe\n");
 529                 return;
 530         }
 531
 532         frame.spd.sdi = HDMI_SPD_SDI_PC;
 533
 534         intel_write_infoframe(encoder, crtc_state,
 535                               &frame);
 536 }
 537
 538 static void
 539 intel_hdmi_set_hdmi_infoframe(struct intel_encoder *encoder,
 540                               const struct intel_crtc_state *crtc_state,
 541                               const struct drm_connector_state *conn_state)
 542 {
 543         union hdmi_infoframe frame;
 544         int ret;
 545
 546         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 547                                                           conn_state->connector,
 548                                                           &crtc_state->base.adjusted_mode);
 549         if (ret < 0)
 550                 return;
 551
 552         intel_write_infoframe(encoder, crtc_state,
 553                               &frame);
 554 }
 555
 556 static void g4x_set_infoframes(struct intel_encoder *encoder,
 557                                bool enable,
 558                                const struct intel_crtc_state *crtc_state,
 559                                const struct drm_connector_state *conn_state)
 560 {
 561         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 562         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 563         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 564         i915_reg_t reg = VIDEO_DIP_CTL;
 565         u32 val = I915_READ(reg);
 566         u32 port = VIDEO_DIP_PORT(encoder->port);
 567
 568         assert_hdmi_port_disabled(intel_hdmi);
 569
 570         /* If the registers were not initialized yet, they might be zeroes,
 571          * which means we're selecting the AVI DIP and we're setting its
 572          * frequency to once. This seems to really confuse the HW and make
 573          * things stop working (the register spec says the AVI always needs to
 574          * be sent every VSync). So here we avoid writing to the register more
 575          * than we need and also explicitly select the AVI DIP and explicitly
 576          * set its frequency to every VSync. Avoiding to write it twice seems to
 577          * be enough to solve the problem, but being defensive shouldn't hurt us
 578          * either. */
 579         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 580
 581         if (!enable) {
 582                 if (!(val & VIDEO_DIP_ENABLE))
 583                         return;
 584                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 585                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 586                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 587                         return;
 588                 }
 589                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 590                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 591                 I915_WRITE(reg, val);
 592                 POSTING_READ(reg);
 593                 return;
 594         }
 595
 596         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 597                 if (val & VIDEO_DIP_ENABLE) {
 598                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 599                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 600                         return;
 601                 }
 602                 val &= ~VIDEO_DIP_PORT_MASK;
 603                 val |= port;
 604         }
 605
 606         val |= VIDEO_DIP_ENABLE;
 607         val &= ~(VIDEO_DIP_ENABLE_AVI |
 608                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 609
 610         I915_WRITE(reg, val);
 611         POSTING_READ(reg);
 612
 613         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
 614         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 615         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 616 }
 617
 618 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
 619 {
 620         struct drm_connector *connector = conn_state->connector;
 621
 622         /*
 623          * HDMI cloning is only supported on g4x which doesn't
 624          * support deep color or GCP infoframes anyway so no
 625          * need to worry about multiple HDMI sinks here.
 626          */
 627
 628         return connector->display_info.bpc > 8;
 629 }
 630
 631 /*
 632  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 633  *
 634  * From HDMI specification 1.4a:
 635  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 636  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 637  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 638  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 639  *   phase of 0
 640  */
 641 static bool gcp_default_phase_possible(int pipe_bpp,
 642                                        const struct drm_display_mode *mode)
 643 {
 644         unsigned int pixels_per_group;
 645
 646         switch (pipe_bpp) {
 647         case 30:
 648                 /* 4 pixels in 5 clocks */
 649                 pixels_per_group = 4;
 650                 break;
 651         case 36:
 652                 /* 2 pixels in 3 clocks */
 653                 pixels_per_group = 2;
 654                 break;
 655         case 48:
 656                 /* 1 pixel in 2 clocks */
 657                 pixels_per_group = 1;
 658                 break;
 659         default:
 660                 /* phase information not relevant for 8bpc */
 661                 return false;
 662         }
 663
 664         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 665                 mode->crtc_htotal % pixels_per_group == 0 &&
 666                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 667                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 668                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 669                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 670                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 671                  mode->crtc_htotal/2 % pixels_per_group == 0);
 672 }
 673
 674 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 675                                          const struct intel_crtc_state *crtc_state,
 676                                          const struct drm_connector_state *conn_state)
 677 {
 678         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 679         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 680         i915_reg_t reg;
 681         u32 val = 0;
 682
 683         if (HAS_DDI(dev_priv))
 684                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 685         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 686                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 687         else if (HAS_PCH_SPLIT(dev_priv))
 688                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 689         else
 690                 return false;
 691
 692         /* Indicate color depth whenever the sink supports deep color */
 693         if (hdmi_sink_is_deep_color(conn_state))
 694                 val |= GCP_COLOR_INDICATION;
 695
 696         /* Enable default_phase whenever the display mode is suitably aligned */
 697         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
 698                                        &crtc_state->base.adjusted_mode))
 699                 val |= GCP_DEFAULT_PHASE_ENABLE;
 700
 701         I915_WRITE(reg, val);
 702
 703         return val != 0;
 704 }
 705
 706 static void ibx_set_infoframes(struct intel_encoder *encoder,
 707                                bool enable,
 708                                const struct intel_crtc_state *crtc_state,
 709                                const struct drm_connector_state *conn_state)
 710 {
 711         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 712         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 713         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 714         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 715         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 716         u32 val = I915_READ(reg);
 717         u32 port = VIDEO_DIP_PORT(encoder->port);
 718
 719         assert_hdmi_port_disabled(intel_hdmi);
 720
 721         /* See the big comment in g4x_set_infoframes() */
 722         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 723
 724         if (!enable) {
 725                 if (!(val & VIDEO_DIP_ENABLE))
 726                         return;
 727                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 728                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 729                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 730                 I915_WRITE(reg, val);
 731                 POSTING_READ(reg);
 732                 return;
 733         }
 734
 735         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 736                 WARN(val & VIDEO_DIP_ENABLE,
 737                      "DIP already enabled on port %c\n",
 738                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 739                 val &= ~VIDEO_DIP_PORT_MASK;
 740                 val |= port;
 741         }
 742
 743         val |= VIDEO_DIP_ENABLE;
 744         val &= ~(VIDEO_DIP_ENABLE_AVI |
 745                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 746                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 747
 748         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 749                 val |= VIDEO_DIP_ENABLE_GCP;
 750
 751         I915_WRITE(reg, val);
 752         POSTING_READ(reg);
 753
 754         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
 755         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 756         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 757 }
 758
 759 static void cpt_set_infoframes(struct intel_encoder *encoder,
 760                                bool enable,
 761                                const struct intel_crtc_state *crtc_state,
 762                                const struct drm_connector_state *conn_state)
 763 {
 764         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 766         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 767         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 768         u32 val = I915_READ(reg);
 769
 770         assert_hdmi_port_disabled(intel_hdmi);
 771
 772         /* See the big comment in g4x_set_infoframes() */
 773         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 774
 775         if (!enable) {
 776                 if (!(val & VIDEO_DIP_ENABLE))
 777                         return;
 778                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 779                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 780                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 781                 I915_WRITE(reg, val);
 782                 POSTING_READ(reg);
 783                 return;
 784         }
 785
 786         /* Set both together, unset both together: see the spec. */
 787         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 788         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 789                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 790
 791         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 792                 val |= VIDEO_DIP_ENABLE_GCP;
 793
 794         I915_WRITE(reg, val);
 795         POSTING_READ(reg);
 796
 797         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
 798         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 799         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 800 }
 801
 802 static void vlv_set_infoframes(struct intel_encoder *encoder,
 803                                bool enable,
 804                                const struct intel_crtc_state *crtc_state,
 805                                const struct drm_connector_state *conn_state)
 806 {
 807         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 808         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 809         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 810         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 811         u32 val = I915_READ(reg);
 812         u32 port = VIDEO_DIP_PORT(encoder->port);
 813
 814         assert_hdmi_port_disabled(intel_hdmi);
 815
 816         /* See the big comment in g4x_set_infoframes() */
 817         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 818
 819         if (!enable) {
 820                 if (!(val & VIDEO_DIP_ENABLE))
 821                         return;
 822                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 823                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 824                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 825                 I915_WRITE(reg, val);
 826                 POSTING_READ(reg);
 827                 return;
 828         }
 829
 830         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 831                 WARN(val & VIDEO_DIP_ENABLE,
 832                      "DIP already enabled on port %c\n",
 833                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 834                 val &= ~VIDEO_DIP_PORT_MASK;
 835                 val |= port;
 836         }
 837
 838         val |= VIDEO_DIP_ENABLE;
 839         val &= ~(VIDEO_DIP_ENABLE_AVI |
 840                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 841                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 842
 843         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 844                 val |= VIDEO_DIP_ENABLE_GCP;
 845
 846         I915_WRITE(reg, val);
 847         POSTING_READ(reg);
 848
 849         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
 850         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 851         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 852 }
 853
 854 static void hsw_set_infoframes(struct intel_encoder *encoder,
 855                                bool enable,
 856                                const struct intel_crtc_state *crtc_state,
 857                                const struct drm_connector_state *conn_state)
 858 {
 859         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 860         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
 861         u32 val = I915_READ(reg);
 862
 863         assert_hdmi_transcoder_func_disabled(dev_priv,
 864                                              crtc_state->cpu_transcoder);
 865
 866         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 867                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 868                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 869
 870         if (!enable) {
 871                 I915_WRITE(reg, val);
 872                 POSTING_READ(reg);
 873                 return;
 874         }
 875
 876         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
 877                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
 878
 879         I915_WRITE(reg, val);
 880         POSTING_READ(reg);
 881
 882         intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
 883         intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 884         intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
 885 }
 886
 887 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
 888 {
 889         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
 890         struct i2c_adapter *adapter =
 891                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
 892
 893         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
 894                 return;
 895
 896         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
 897                       enable ? "Enabling" : "Disabling");
 898
 899         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
 900                                          adapter, enable);
 901 }
 902
 903 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
 904                                 unsigned int offset, void *buffer, size_t size)
 905 {
 906         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
 907         struct drm_i915_private *dev_priv =
 908                 intel_dig_port->base.base.dev->dev_private;
 909         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
 910                                                               hdmi->ddc_bus);
 911         int ret;
 912         u8 start = offset & 0xff;
 913         struct i2c_msg msgs[] = {
 914                 {
 915                         .addr = DRM_HDCP_DDC_ADDR,
 916                         .flags = 0,
 917                         .len = 1,
 918                         .buf = &start,
 919                 },
 920                 {
 921                         .addr = DRM_HDCP_DDC_ADDR,
 922                         .flags = I2C_M_RD,
 923                         .len = size,
 924                         .buf = buffer
 925                 }
 926         };
 927         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
 928         if (ret == ARRAY_SIZE(msgs))
 929                 return 0;
 930         return ret >= 0 ? -EIO : ret;
 931 }
 932
 933 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
 934                                  unsigned int offset, void *buffer, size_t size)
 935 {
 936         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
 937         struct drm_i915_private *dev_priv =
 938                 intel_dig_port->base.base.dev->dev_private;
 939         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
 940                                                               hdmi->ddc_bus);
 941         int ret;
 942         u8 *write_buf;
 943         struct i2c_msg msg;
 944
 945         write_buf = kzalloc(size + 1, GFP_KERNEL);
 946         if (!write_buf)
 947                 return -ENOMEM;
 948
 949         write_buf[0] = offset & 0xff;
 950         memcpy(&write_buf[1], buffer, size);
 951
 952         msg.addr = DRM_HDCP_DDC_ADDR;
 953         msg.flags = 0,
 954         msg.len = size + 1,
 955         msg.buf = write_buf;
 956
 957         ret = i2c_transfer(adapter, &msg, 1);
 958         if (ret == 1)
 959                 ret = 0;
 960         else if (ret >= 0)
 961                 ret = -EIO;
 962
 963         kfree(write_buf);
 964         return ret;
 965 }
 966
 967 static
 968 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
 969                                   u8 *an)
 970 {
 971         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
 972         struct drm_i915_private *dev_priv =
 973                 intel_dig_port->base.base.dev->dev_private;
 974         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
 975                                                               hdmi->ddc_bus);
 976         int ret;
 977
 978         ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
 979                                     DRM_HDCP_AN_LEN);
 980         if (ret) {
 981                 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
 982                 return ret;
 983         }
 984
 985         ret = intel_gmbus_output_aksv(adapter);
 986         if (ret < 0) {
 987                 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
 988                 return ret;
 989         }
 990         return 0;
 991 }
 992
 993 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
 994                                      u8 *bksv)
 995 {
 996         int ret;
 997         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
 998                                    DRM_HDCP_KSV_LEN);
 999         if (ret)
1000                 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
1001         return ret;
1002 }
1003
1004 static
1005 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1006                                  u8 *bstatus)
1007 {
1008         int ret;
1009         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1010                                    bstatus, DRM_HDCP_BSTATUS_LEN);
1011         if (ret)
1012                 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1013         return ret;
1014 }
1015
1016 static
1017 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1018                                      bool *repeater_present)
1019 {
1020         int ret;
1021         u8 val;
1022
1023         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1024         if (ret) {
1025                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1026                 return ret;
1027         }
1028         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1029         return 0;
1030 }
1031
1032 static
1033 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1034                                   u8 *ri_prime)
1035 {
1036         int ret;
1037         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1038                                    ri_prime, DRM_HDCP_RI_LEN);
1039         if (ret)
1040                 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1041         return ret;
1042 }
1043
1044 static
1045 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1046                                    bool *ksv_ready)
1047 {
1048         int ret;
1049         u8 val;
1050
1051         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1052         if (ret) {
1053                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1054                 return ret;
1055         }
1056         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1057         return 0;
1058 }
1059
1060 static
1061 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1062                                   int num_downstream, u8 *ksv_fifo)
1063 {
1064         int ret;
1065         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1066                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1067         if (ret) {
1068                 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1069                 return ret;
1070         }
1071         return 0;
1072 }
1073
1074 static
1075 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1076                                       int i, u32 *part)
1077 {
1078         int ret;
1079
1080         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1081                 return -EINVAL;
1082
1083         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1084                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1085         if (ret)
1086                 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1087         return ret;
1088 }
1089
1090 static
1091 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1092                                       bool enable)
1093 {
1094         int ret;
1095
1096         if (!enable)
1097                 usleep_range(6, 60); /* Bspec says >= 6us */
1098
1099         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1100         if (ret) {
1101                 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1102                           enable ? "Enable" : "Disable", ret);
1103                 return ret;
1104         }
1105         return 0;
1106 }
1107
1108 static
1109 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1110 {
1111         struct drm_i915_private *dev_priv =
1112                 intel_dig_port->base.base.dev->dev_private;
1113         enum port port = intel_dig_port->base.port;
1114         int ret;
1115         union {
1116                 u32 reg;
1117                 u8 shim[DRM_HDCP_RI_LEN];
1118         } ri;
1119
1120         ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1121         if (ret)
1122                 return false;
1123
1124         I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
1125
1126         /* Wait for Ri prime match */
1127         if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
1128                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1129                 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1130                           I915_READ(PORT_HDCP_STATUS(port)));
1131                 return false;
1132         }
1133         return true;
1134 }
1135
1136 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1137         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1138         .read_bksv = intel_hdmi_hdcp_read_bksv,
1139         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1140         .repeater_present = intel_hdmi_hdcp_repeater_present,
1141         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1142         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1143         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1144         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1145         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1146         .check_link = intel_hdmi_hdcp_check_link,
1147 };
1148
1149 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1150                                const struct intel_crtc_state *crtc_state)
1151 {
1152         struct drm_device *dev = encoder->base.dev;
1153         struct drm_i915_private *dev_priv = to_i915(dev);
1154         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1155         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1156         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1157         u32 hdmi_val;
1158
1159         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1160
1161         hdmi_val = SDVO_ENCODING_HDMI;
1162         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1163                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1164         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1165                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1166         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1167                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1168
1169         if (crtc_state->pipe_bpp > 24)
1170                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1171         else
1172                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1173
1174         if (crtc_state->has_hdmi_sink)
1175                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1176
1177         if (HAS_PCH_CPT(dev_priv))
1178                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1179         else if (IS_CHERRYVIEW(dev_priv))
1180                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1181         else
1182                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1183
1184         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1185         POSTING_READ(intel_hdmi->hdmi_reg);
1186 }
1187
1188 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1189                                     enum pipe *pipe)
1190 {
1191         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1192         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1193         bool ret;
1194
1195         if (!intel_display_power_get_if_enabled(dev_priv,
1196                                                 encoder->power_domain))
1197                 return false;
1198
1199         ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1200
1201         intel_display_power_put(dev_priv, encoder->power_domain);
1202
1203         return ret;
1204 }
1205
1206 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1207                                   struct intel_crtc_state *pipe_config)
1208 {
1209         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1210         struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
1211         struct drm_device *dev = encoder->base.dev;
1212         struct drm_i915_private *dev_priv = to_i915(dev);
1213         u32 tmp, flags = 0;
1214         int dotclock;
1215
1216         pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1217
1218         tmp = I915_READ(intel_hdmi->hdmi_reg);
1219
1220         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1221                 flags |= DRM_MODE_FLAG_PHSYNC;
1222         else
1223                 flags |= DRM_MODE_FLAG_NHSYNC;
1224
1225         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1226                 flags |= DRM_MODE_FLAG_PVSYNC;
1227         else
1228                 flags |= DRM_MODE_FLAG_NVSYNC;
1229
1230         if (tmp & HDMI_MODE_SELECT_HDMI)
1231                 pipe_config->has_hdmi_sink = true;
1232
1233         if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
1234                 pipe_config->has_infoframe = true;
1235
1236         if (tmp & SDVO_AUDIO_ENABLE)
1237                 pipe_config->has_audio = true;
1238
1239         if (!HAS_PCH_SPLIT(dev_priv) &&
1240             tmp & HDMI_COLOR_RANGE_16_235)
1241                 pipe_config->limited_color_range = true;
1242
1243         pipe_config->base.adjusted_mode.flags |= flags;
1244
1245         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1246                 dotclock = pipe_config->port_clock * 2 / 3;
1247         else
1248                 dotclock = pipe_config->port_clock;
1249
1250         if (pipe_config->pixel_multiplier)
1251                 dotclock /= pipe_config->pixel_multiplier;
1252
1253         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1254
1255         pipe_config->lane_count = 4;
1256 }
1257
1258 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1259                                     const struct intel_crtc_state *pipe_config,
1260                                     const struct drm_connector_state *conn_state)
1261 {
1262         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1263
1264         WARN_ON(!pipe_config->has_hdmi_sink);
1265         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1266                          pipe_name(crtc->pipe));
1267         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1268 }
1269
1270 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1271                             const struct intel_crtc_state *pipe_config,
1272                             const struct drm_connector_state *conn_state)
1273 {
1274         struct drm_device *dev = encoder->base.dev;
1275         struct drm_i915_private *dev_priv = to_i915(dev);
1276         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1277         u32 temp;
1278
1279         temp = I915_READ(intel_hdmi->hdmi_reg);
1280
1281         temp |= SDVO_ENABLE;
1282         if (pipe_config->has_audio)
1283                 temp |= SDVO_AUDIO_ENABLE;
1284
1285         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1286         POSTING_READ(intel_hdmi->hdmi_reg);
1287
1288         if (pipe_config->has_audio)
1289                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1290 }
1291
1292 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1293                             const struct intel_crtc_state *pipe_config,
1294                             const struct drm_connector_state *conn_state)
1295 {
1296         struct drm_device *dev = encoder->base.dev;
1297         struct drm_i915_private *dev_priv = to_i915(dev);
1298         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1299         u32 temp;
1300
1301         temp = I915_READ(intel_hdmi->hdmi_reg);
1302
1303         temp |= SDVO_ENABLE;
1304         if (pipe_config->has_audio)
1305                 temp |= SDVO_AUDIO_ENABLE;
1306
1307         /*
1308          * HW workaround, need to write this twice for issue
1309          * that may result in first write getting masked.
1310          */
1311         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1312         POSTING_READ(intel_hdmi->hdmi_reg);
1313         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1314         POSTING_READ(intel_hdmi->hdmi_reg);
1315
1316         /*
1317          * HW workaround, need to toggle enable bit off and on
1318          * for 12bpc with pixel repeat.
1319          *
1320          * FIXME: BSpec says this should be done at the end of
1321          * of the modeset sequence, so not sure if this isn't too soon.
1322          */
1323         if (pipe_config->pipe_bpp > 24 &&
1324             pipe_config->pixel_multiplier > 1) {
1325                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1326                 POSTING_READ(intel_hdmi->hdmi_reg);
1327
1328                 /*
1329                  * HW workaround, need to write this twice for issue
1330                  * that may result in first write getting masked.
1331                  */
1332                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1333                 POSTING_READ(intel_hdmi->hdmi_reg);
1334                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1335                 POSTING_READ(intel_hdmi->hdmi_reg);
1336         }
1337
1338         if (pipe_config->has_audio)
1339                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1340 }
1341
1342 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1343                             const struct intel_crtc_state *pipe_config,
1344                             const struct drm_connector_state *conn_state)
1345 {
1346         struct drm_device *dev = encoder->base.dev;
1347         struct drm_i915_private *dev_priv = to_i915(dev);
1348         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1349         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1350         enum pipe pipe = crtc->pipe;
1351         u32 temp;
1352
1353         temp = I915_READ(intel_hdmi->hdmi_reg);
1354
1355         temp |= SDVO_ENABLE;
1356         if (pipe_config->has_audio)
1357                 temp |= SDVO_AUDIO_ENABLE;
1358
1359         /*
1360          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1361          *
1362          * The procedure for 12bpc is as follows:
1363          * 1. disable HDMI clock gating
1364          * 2. enable HDMI with 8bpc
1365          * 3. enable HDMI with 12bpc
1366          * 4. enable HDMI clock gating
1367          */
1368
1369         if (pipe_config->pipe_bpp > 24) {
1370                 I915_WRITE(TRANS_CHICKEN1(pipe),
1371                            I915_READ(TRANS_CHICKEN1(pipe)) |
1372                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1373
1374                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1375                 temp |= SDVO_COLOR_FORMAT_8bpc;
1376         }
1377
1378         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1379         POSTING_READ(intel_hdmi->hdmi_reg);
1380
1381         if (pipe_config->pipe_bpp > 24) {
1382                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1383                 temp |= HDMI_COLOR_FORMAT_12bpc;
1384
1385                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1386                 POSTING_READ(intel_hdmi->hdmi_reg);
1387
1388                 I915_WRITE(TRANS_CHICKEN1(pipe),
1389                            I915_READ(TRANS_CHICKEN1(pipe)) &
1390                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1391         }
1392
1393         if (pipe_config->has_audio)
1394                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1395 }
1396
1397 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1398                             const struct intel_crtc_state *pipe_config,
1399                             const struct drm_connector_state *conn_state)
1400 {
1401 }
1402
1403 static void intel_disable_hdmi(struct intel_encoder *encoder,
1404                                const struct intel_crtc_state *old_crtc_state,
1405                                const struct drm_connector_state *old_conn_state)
1406 {
1407         struct drm_device *dev = encoder->base.dev;
1408         struct drm_i915_private *dev_priv = to_i915(dev);
1409         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1410         struct intel_digital_port *intel_dig_port =
1411                 hdmi_to_dig_port(intel_hdmi);
1412         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1413         u32 temp;
1414
1415         temp = I915_READ(intel_hdmi->hdmi_reg);
1416
1417         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1418         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1419         POSTING_READ(intel_hdmi->hdmi_reg);
1420
1421         /*
1422          * HW workaround for IBX, we need to move the port
1423          * to transcoder A after disabling it to allow the
1424          * matching DP port to be enabled on transcoder A.
1425          */
1426         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1427                 /*
1428                  * We get CPU/PCH FIFO underruns on the other pipe when
1429                  * doing the workaround. Sweep them under the rug.
1430                  */
1431                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1432                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1433
1434                 temp &= ~SDVO_PIPE_SEL_MASK;
1435                 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1436                 /*
1437                  * HW workaround, need to write this twice for issue
1438                  * that may result in first write getting masked.
1439                  */
1440                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1441                 POSTING_READ(intel_hdmi->hdmi_reg);
1442                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1443                 POSTING_READ(intel_hdmi->hdmi_reg);
1444
1445                 temp &= ~SDVO_ENABLE;
1446                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1447                 POSTING_READ(intel_hdmi->hdmi_reg);
1448
1449                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1450                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1451                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1452         }
1453
1454         intel_dig_port->set_infoframes(encoder,
1455                                        false,
1456                                        old_crtc_state, old_conn_state);
1457
1458         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1459 }
1460
1461 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1462                              const struct intel_crtc_state *old_crtc_state,
1463                              const struct drm_connector_state *old_conn_state)
1464 {
1465         if (old_crtc_state->has_audio)
1466                 intel_audio_codec_disable(encoder,
1467                                           old_crtc_state, old_conn_state);
1468
1469         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1470 }
1471
1472 static void pch_disable_hdmi(struct intel_encoder *encoder,
1473                              const struct intel_crtc_state *old_crtc_state,
1474                              const struct drm_connector_state *old_conn_state)
1475 {
1476         if (old_crtc_state->has_audio)
1477                 intel_audio_codec_disable(encoder,
1478                                           old_crtc_state, old_conn_state);
1479 }
1480
1481 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1482                                   const struct intel_crtc_state *old_crtc_state,
1483                                   const struct drm_connector_state *old_conn_state)
1484 {
1485         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1486 }
1487
1488 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1489 {
1490         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1491         const struct ddi_vbt_port_info *info =
1492                 &dev_priv->vbt.ddi_port_info[encoder->port];
1493         int max_tmds_clock;
1494
1495         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
1496                 max_tmds_clock = 594000;
1497         else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1498                 max_tmds_clock = 300000;
1499         else if (INTEL_GEN(dev_priv) >= 5)
1500                 max_tmds_clock = 225000;
1501         else
1502                 max_tmds_clock = 165000;
1503
1504         if (info->max_tmds_clock)
1505                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1506
1507         return max_tmds_clock;
1508 }
1509
1510 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1511                                  bool respect_downstream_limits,
1512                                  bool force_dvi)
1513 {
1514         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1515         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1516
1517         if (respect_downstream_limits) {
1518                 struct intel_connector *connector = hdmi->attached_connector;
1519                 const struct drm_display_info *info = &connector->base.display_info;
1520
1521                 if (hdmi->dp_dual_mode.max_tmds_clock)
1522                         max_tmds_clock = min(max_tmds_clock,
1523                                              hdmi->dp_dual_mode.max_tmds_clock);
1524
1525                 if (info->max_tmds_clock)
1526                         max_tmds_clock = min(max_tmds_clock,
1527                                              info->max_tmds_clock);
1528                 else if (!hdmi->has_hdmi_sink || force_dvi)
1529                         max_tmds_clock = min(max_tmds_clock, 165000);
1530         }
1531
1532         return max_tmds_clock;
1533 }
1534
1535 static enum drm_mode_status
1536 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1537                       int clock, bool respect_downstream_limits,
1538                       bool force_dvi)
1539 {
1540         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1541
1542         if (clock < 25000)
1543                 return MODE_CLOCK_LOW;
1544         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1545                 return MODE_CLOCK_HIGH;
1546
1547         /* BXT DPLL can't generate 223-240 MHz */
1548         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1549                 return MODE_CLOCK_RANGE;
1550
1551         /* CHV DPLL can't generate 216-240 MHz */
1552         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1553                 return MODE_CLOCK_RANGE;
1554
1555         return MODE_OK;
1556 }
1557
1558 static enum drm_mode_status
1559 intel_hdmi_mode_valid(struct drm_connector *connector,
1560                       struct drm_display_mode *mode)
1561 {
1562         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1563         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1564         struct drm_i915_private *dev_priv = to_i915(dev);
1565         enum drm_mode_status status;
1566         int clock;
1567         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1568         bool force_dvi =
1569                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1570
1571         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1572                 return MODE_NO_DBLESCAN;
1573
1574         clock = mode->clock;
1575
1576         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1577                 clock *= 2;
1578
1579         if (clock > max_dotclk)
1580                 return MODE_CLOCK_HIGH;
1581
1582         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1583                 clock *= 2;
1584
1585         if (drm_mode_is_420_only(&connector->display_info, mode))
1586                 clock /= 2;
1587
1588         /* check if we can do 8bpc */
1589         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1590
1591         if (hdmi->has_hdmi_sink && !force_dvi) {
1592                 /* if we can't do 8bpc we may still be able to do 12bpc */
1593                 if (status != MODE_OK && !HAS_GMCH_DISPLAY(dev_priv))
1594                         status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
1595                                                        true, force_dvi);
1596
1597                 /* if we can't do 8,12bpc we may still be able to do 10bpc */
1598                 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
1599                         status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
1600                                                        true, force_dvi);
1601         }
1602
1603         return status;
1604 }
1605
1606 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1607                                      int bpc)
1608 {
1609         struct drm_i915_private *dev_priv =
1610                 to_i915(crtc_state->base.crtc->dev);
1611         struct drm_atomic_state *state = crtc_state->base.state;
1612         struct drm_connector_state *connector_state;
1613         struct drm_connector *connector;
1614         const struct drm_display_mode *adjusted_mode =
1615                 &crtc_state->base.adjusted_mode;
1616         int i;
1617
1618         if (HAS_GMCH_DISPLAY(dev_priv))
1619                 return false;
1620
1621         if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
1622                 return false;
1623
1624         if (crtc_state->pipe_bpp <= 8*3)
1625                 return false;
1626
1627         if (!crtc_state->has_hdmi_sink)
1628                 return false;
1629
1630         /*
1631          * HDMI deep color affects the clocks, so it's only possible
1632          * when not cloning with other encoder types.
1633          */
1634         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1635                 return false;
1636
1637         for_each_new_connector_in_state(state, connector, connector_state, i) {
1638                 const struct drm_display_info *info = &connector->display_info;
1639
1640                 if (connector_state->crtc != crtc_state->base.crtc)
1641                         continue;
1642
1643                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
1644                         const struct drm_hdmi_info *hdmi = &info->hdmi;
1645
1646                         if (bpc == 12 && !(hdmi->y420_dc_modes &
1647                                            DRM_EDID_YCBCR420_DC_36))
1648                                 return false;
1649                         else if (bpc == 10 && !(hdmi->y420_dc_modes &
1650                                                 DRM_EDID_YCBCR420_DC_30))
1651                                 return false;
1652                 } else {
1653                         if (bpc == 12 && !(info->edid_hdmi_dc_modes &
1654                                            DRM_EDID_HDMI_DC_36))
1655                                 return false;
1656                         else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
1657                                                 DRM_EDID_HDMI_DC_30))
1658                                 return false;
1659                 }
1660         }
1661
1662         /* Display WA #1139: glk */
1663         if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1664             adjusted_mode->htotal > 5460)
1665                 return false;
1666
1667         /* Display Wa_1405510057:icl */
1668         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1669             bpc == 10 && IS_ICELAKE(dev_priv) &&
1670             (adjusted_mode->crtc_hblank_end -
1671              adjusted_mode->crtc_hblank_start) % 8 == 2)
1672                 return false;
1673
1674         return true;
1675 }
1676
1677 static bool
1678 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1679                            struct intel_crtc_state *config,
1680                            int *clock_12bpc, int *clock_10bpc,
1681                            int *clock_8bpc)
1682 {
1683         struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1684
1685         if (!connector->ycbcr_420_allowed) {
1686                 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1687                 return false;
1688         }
1689
1690         /* YCBCR420 TMDS rate requirement is half the pixel clock */
1691         config->port_clock /= 2;
1692         *clock_12bpc /= 2;
1693         *clock_10bpc /= 2;
1694         *clock_8bpc /= 2;
1695         config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1696
1697         /* YCBCR 420 output conversion needs a scaler */
1698         if (skl_update_scaler_crtc(config)) {
1699                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1700                 return false;
1701         }
1702
1703         intel_pch_panel_fitting(intel_crtc, config,
1704                                 DRM_MODE_SCALE_FULLSCREEN);
1705
1706         return true;
1707 }
1708
1709 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1710                                struct intel_crtc_state *pipe_config,
1711                                struct drm_connector_state *conn_state)
1712 {
1713         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1714         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1715         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1716         struct drm_connector *connector = conn_state->connector;
1717         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
1718         struct intel_digital_connector_state *intel_conn_state =
1719                 to_intel_digital_connector_state(conn_state);
1720         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1721         int clock_10bpc = clock_8bpc * 5 / 4;
1722         int clock_12bpc = clock_8bpc * 3 / 2;
1723         int desired_bpp;
1724         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1725
1726         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1727                 return false;
1728
1729         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1730         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1731
1732         if (pipe_config->has_hdmi_sink)
1733                 pipe_config->has_infoframe = true;
1734
1735         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1736                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1737                 pipe_config->limited_color_range =
1738                         pipe_config->has_hdmi_sink &&
1739                         drm_default_rgb_quant_range(adjusted_mode) ==
1740                         HDMI_QUANTIZATION_RANGE_LIMITED;
1741         } else {
1742                 pipe_config->limited_color_range =
1743                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1744         }
1745
1746         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1747                 pipe_config->pixel_multiplier = 2;
1748                 clock_8bpc *= 2;
1749                 clock_10bpc *= 2;
1750                 clock_12bpc *= 2;
1751         }
1752
1753         if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
1754                 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
1755                                                 &clock_12bpc, &clock_10bpc,
1756                                                 &clock_8bpc)) {
1757                         DRM_ERROR("Can't support YCBCR420 output\n");
1758                         return false;
1759                 }
1760         }
1761
1762         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1763                 pipe_config->has_pch_encoder = true;
1764
1765         if (pipe_config->has_hdmi_sink) {
1766                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1767                         pipe_config->has_audio = intel_hdmi->has_audio;
1768                 else
1769                         pipe_config->has_audio =
1770                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1771         }
1772
1773         /*
1774          * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
1775          * to check that the higher clock still fits within limits.
1776          */
1777         if (hdmi_deep_color_possible(pipe_config, 12) &&
1778             hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
1779                                   true, force_dvi) == MODE_OK) {
1780                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1781                 desired_bpp = 12*3;
1782
1783                 /* Need to adjust the port link by 1.5x for 12bpc. */
1784                 pipe_config->port_clock = clock_12bpc;
1785         } else if (hdmi_deep_color_possible(pipe_config, 10) &&
1786                    hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
1787                                          true, force_dvi) == MODE_OK) {
1788                 DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
1789                 desired_bpp = 10 * 3;
1790
1791                 /* Need to adjust the port link by 1.25x for 10bpc. */
1792                 pipe_config->port_clock = clock_10bpc;
1793         } else {
1794                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1795                 desired_bpp = 8*3;
1796
1797                 pipe_config->port_clock = clock_8bpc;
1798         }
1799
1800         if (!pipe_config->bw_constrained) {
1801                 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1802                 pipe_config->pipe_bpp = desired_bpp;
1803         }
1804
1805         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1806                                   false, force_dvi) != MODE_OK) {
1807                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1808                 return false;
1809         }
1810
1811         /* Set user selected PAR to incoming mode's member */
1812         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1813
1814         pipe_config->lane_count = 4;
1815
1816         if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
1817                                            IS_GEMINILAKE(dev_priv))) {
1818                 if (scdc->scrambling.low_rates)
1819                         pipe_config->hdmi_scrambling = true;
1820
1821                 if (pipe_config->port_clock > 340000) {
1822                         pipe_config->hdmi_scrambling = true;
1823                         pipe_config->hdmi_high_tmds_clock_ratio = true;
1824                 }
1825         }
1826
1827         return true;
1828 }
1829
1830 static void
1831 intel_hdmi_unset_edid(struct drm_connector *connector)
1832 {
1833         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1834
1835         intel_hdmi->has_hdmi_sink = false;
1836         intel_hdmi->has_audio = false;
1837         intel_hdmi->rgb_quant_range_selectable = false;
1838
1839         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1840         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1841
1842         kfree(to_intel_connector(connector)->detect_edid);
1843         to_intel_connector(connector)->detect_edid = NULL;
1844 }
1845
1846 static void
1847 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1848 {
1849         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1850         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1851         enum port port = hdmi_to_dig_port(hdmi)->base.port;
1852         struct i2c_adapter *adapter =
1853                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1854         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1855
1856         /*
1857          * Type 1 DVI adaptors are not required to implement any
1858          * registers, so we can't always detect their presence.
1859          * Ideally we should be able to check the state of the
1860          * CONFIG1 pin, but no such luck on our hardware.
1861          *
1862          * The only method left to us is to check the VBT to see
1863          * if the port is a dual mode capable DP port. But let's
1864          * only do that when we sucesfully read the EDID, to avoid
1865          * confusing log messages about DP dual mode adaptors when
1866          * there's nothing connected to the port.
1867          */
1868         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1869                 /* An overridden EDID imply that we want this port for testing.
1870                  * Make sure not to set limits for that port.
1871                  */
1872                 if (has_edid && !connector->override_edid &&
1873                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1874                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1875                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1876                 } else {
1877                         type = DRM_DP_DUAL_MODE_NONE;
1878                 }
1879         }
1880
1881         if (type == DRM_DP_DUAL_MODE_NONE)
1882                 return;
1883
1884         hdmi->dp_dual_mode.type = type;
1885         hdmi->dp_dual_mode.max_tmds_clock =
1886                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1887
1888         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1889                       drm_dp_get_dual_mode_type_name(type),
1890                       hdmi->dp_dual_mode.max_tmds_clock);
1891 }
1892
1893 static bool
1894 intel_hdmi_set_edid(struct drm_connector *connector)
1895 {
1896         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1897         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1898         struct edid *edid;
1899         bool connected = false;
1900         struct i2c_adapter *i2c;
1901
1902         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1903
1904         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
1905
1906         edid = drm_get_edid(connector, i2c);
1907
1908         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
1909                 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
1910                 intel_gmbus_force_bit(i2c, true);
1911                 edid = drm_get_edid(connector, i2c);
1912                 intel_gmbus_force_bit(i2c, false);
1913         }
1914
1915         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1916
1917         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1918
1919         to_intel_connector(connector)->detect_edid = edid;
1920         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1921                 intel_hdmi->rgb_quant_range_selectable =
1922                         drm_rgb_quant_range_selectable(edid);
1923
1924                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1925                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1926
1927                 connected = true;
1928         }
1929
1930         cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
1931
1932         return connected;
1933 }
1934
1935 static enum drm_connector_status
1936 intel_hdmi_detect(struct drm_connector *connector, bool force)
1937 {
1938         enum drm_connector_status status = connector_status_disconnected;
1939         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1940         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1941         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
1942
1943         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1944                       connector->base.id, connector->name);
1945
1946         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1947
1948         if (IS_ICELAKE(dev_priv) &&
1949             !intel_digital_port_connected(encoder))
1950                 goto out;
1951
1952         intel_hdmi_unset_edid(connector);
1953
1954         if (intel_hdmi_set_edid(connector))
1955                 status = connector_status_connected;
1956
1957 out:
1958         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1959
1960         if (status != connector_status_connected)
1961                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
1962
1963         return status;
1964 }
1965
1966 static void
1967 intel_hdmi_force(struct drm_connector *connector)
1968 {
1969         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1970                       connector->base.id, connector->name);
1971
1972         intel_hdmi_unset_edid(connector);
1973
1974         if (connector->status != connector_status_connected)
1975                 return;
1976
1977         intel_hdmi_set_edid(connector);
1978 }
1979
1980 static int intel_hdmi_get_modes(struct drm_connector *connector)
1981 {
1982         struct edid *edid;
1983
1984         edid = to_intel_connector(connector)->detect_edid;
1985         if (edid == NULL)
1986                 return 0;
1987
1988         return intel_connector_update_modes(connector, edid);
1989 }
1990
1991 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1992                                   const struct intel_crtc_state *pipe_config,
1993                                   const struct drm_connector_state *conn_state)
1994 {
1995         struct intel_digital_port *intel_dig_port =
1996                 enc_to_dig_port(&encoder->base);
1997
1998         intel_hdmi_prepare(encoder, pipe_config);
1999
2000         intel_dig_port->set_infoframes(encoder,
2001                                        pipe_config->has_infoframe,
2002                                        pipe_config, conn_state);
2003 }
2004
2005 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
2006                                 const struct intel_crtc_state *pipe_config,
2007                                 const struct drm_connector_state *conn_state)
2008 {
2009         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2010         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2011
2012         vlv_phy_pre_encoder_enable(encoder, pipe_config);
2013
2014         /* HDMI 1.0V-2dB */
2015         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2016                                  0x2b247878);
2017
2018         dport->set_infoframes(encoder,
2019                               pipe_config->has_infoframe,
2020                               pipe_config, conn_state);
2021
2022         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2023
2024         vlv_wait_port_ready(dev_priv, dport, 0x0);
2025 }
2026
2027 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2028                                     const struct intel_crtc_state *pipe_config,
2029                                     const struct drm_connector_state *conn_state)
2030 {
2031         intel_hdmi_prepare(encoder, pipe_config);
2032
2033         vlv_phy_pre_pll_enable(encoder, pipe_config);
2034 }
2035
2036 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2037                                     const struct intel_crtc_state *pipe_config,
2038                                     const struct drm_connector_state *conn_state)
2039 {
2040         intel_hdmi_prepare(encoder, pipe_config);
2041
2042         chv_phy_pre_pll_enable(encoder, pipe_config);
2043 }
2044
2045 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2046                                       const struct intel_crtc_state *old_crtc_state,
2047                                       const struct drm_connector_state *old_conn_state)
2048 {
2049         chv_phy_post_pll_disable(encoder, old_crtc_state);
2050 }
2051
2052 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2053                                   const struct intel_crtc_state *old_crtc_state,
2054                                   const struct drm_connector_state *old_conn_state)
2055 {
2056         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2057         vlv_phy_reset_lanes(encoder, old_crtc_state);
2058 }
2059
2060 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2061                                   const struct intel_crtc_state *old_crtc_state,
2062                                   const struct drm_connector_state *old_conn_state)
2063 {
2064         struct drm_device *dev = encoder->base.dev;
2065         struct drm_i915_private *dev_priv = to_i915(dev);
2066
2067         mutex_lock(&dev_priv->sb_lock);
2068
2069         /* Assert data lane reset */
2070         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2071
2072         mutex_unlock(&dev_priv->sb_lock);
2073 }
2074
2075 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2076                                 const struct intel_crtc_state *pipe_config,
2077                                 const struct drm_connector_state *conn_state)
2078 {
2079         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2080         struct drm_device *dev = encoder->base.dev;
2081         struct drm_i915_private *dev_priv = to_i915(dev);
2082
2083         chv_phy_pre_encoder_enable(encoder, pipe_config);
2084
2085         /* FIXME: Program the support xxx V-dB */
2086         /* Use 800mV-0dB */
2087         chv_set_phy_signal_level(encoder, 128, 102, false);
2088
2089         dport->set_infoframes(encoder,
2090                               pipe_config->has_infoframe,
2091                               pipe_config, conn_state);
2092
2093         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2094
2095         vlv_wait_port_ready(dev_priv, dport, 0x0);
2096
2097         /* Second common lane will stay alive on its own now */
2098         chv_phy_release_cl2_override(encoder);
2099 }
2100
2101 static int
2102 intel_hdmi_connector_register(struct drm_connector *connector)
2103 {
2104         int ret;
2105
2106         ret = intel_connector_register(connector);
2107         if (ret)
2108                 return ret;
2109
2110         i915_debugfs_connector_add(connector);
2111
2112         return ret;
2113 }
2114
2115 static void intel_hdmi_destroy(struct drm_connector *connector)
2116 {
2117         if (intel_attached_hdmi(connector)->cec_notifier)
2118                 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2119
2120         intel_connector_destroy(connector);
2121 }
2122
2123 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2124         .detect = intel_hdmi_detect,
2125         .force = intel_hdmi_force,
2126         .fill_modes = drm_helper_probe_single_connector_modes,
2127         .atomic_get_property = intel_digital_connector_atomic_get_property,
2128         .atomic_set_property = intel_digital_connector_atomic_set_property,
2129         .late_register = intel_hdmi_connector_register,
2130         .early_unregister = intel_connector_unregister,
2131         .destroy = intel_hdmi_destroy,
2132         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2133         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2134 };
2135
2136 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2137         .get_modes = intel_hdmi_get_modes,
2138         .mode_valid = intel_hdmi_mode_valid,
2139         .atomic_check = intel_digital_connector_atomic_check,
2140 };
2141
2142 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2143         .destroy = intel_encoder_destroy,
2144 };
2145
2146 static void
2147 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2148 {
2149         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2150
2151         intel_attach_force_audio_property(connector);
2152         intel_attach_broadcast_rgb_property(connector);
2153         intel_attach_aspect_ratio_property(connector);
2154         drm_connector_attach_content_type_property(connector);
2155         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2156
2157         if (!HAS_GMCH_DISPLAY(dev_priv))
2158                 drm_connector_attach_max_bpc_property(connector, 8, 12);
2159 }
2160
2161 /*
2162  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2163  * @encoder: intel_encoder
2164  * @connector: drm_connector
2165  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2166  *  or reset the high tmds clock ratio for scrambling
2167  * @scrambling: bool to Indicate if the function needs to set or reset
2168  *  sink scrambling
2169  *
2170  * This function handles scrambling on HDMI 2.0 capable sinks.
2171  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2172  * it enables scrambling. This should be called before enabling the HDMI
2173  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2174  * detect a scrambled clock within 100 ms.
2175  *
2176  * Returns:
2177  * True on success, false on failure.
2178  */
2179 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2180                                        struct drm_connector *connector,
2181                                        bool high_tmds_clock_ratio,
2182                                        bool scrambling)
2183 {
2184         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2185         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2186         struct drm_scrambling *sink_scrambling =
2187                 &connector->display_info.hdmi.scdc.scrambling;
2188         struct i2c_adapter *adapter =
2189                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2190
2191         if (!sink_scrambling->supported)
2192                 return true;
2193
2194         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2195                       connector->base.id, connector->name,
2196                       yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2197
2198         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2199         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2200                                                   high_tmds_clock_ratio) &&
2201                 drm_scdc_set_scrambling(adapter, scrambling);
2202 }
2203
2204 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2205 {
2206         u8 ddc_pin;
2207
2208         switch (port) {
2209         case PORT_B:
2210                 ddc_pin = GMBUS_PIN_DPB;
2211                 break;
2212         case PORT_C:
2213                 ddc_pin = GMBUS_PIN_DPC;
2214                 break;
2215         case PORT_D:
2216                 ddc_pin = GMBUS_PIN_DPD_CHV;
2217                 break;
2218         default:
2219                 MISSING_CASE(port);
2220                 ddc_pin = GMBUS_PIN_DPB;
2221                 break;
2222         }
2223         return ddc_pin;
2224 }
2225
2226 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2227 {
2228         u8 ddc_pin;
2229
2230         switch (port) {
2231         case PORT_B:
2232                 ddc_pin = GMBUS_PIN_1_BXT;
2233                 break;
2234         case PORT_C:
2235                 ddc_pin = GMBUS_PIN_2_BXT;
2236                 break;
2237         default:
2238                 MISSING_CASE(port);
2239                 ddc_pin = GMBUS_PIN_1_BXT;
2240                 break;
2241         }
2242         return ddc_pin;
2243 }
2244
2245 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2246                               enum port port)
2247 {
2248         u8 ddc_pin;
2249
2250         switch (port) {
2251         case PORT_B:
2252                 ddc_pin = GMBUS_PIN_1_BXT;
2253                 break;
2254         case PORT_C:
2255                 ddc_pin = GMBUS_PIN_2_BXT;
2256                 break;
2257         case PORT_D:
2258                 ddc_pin = GMBUS_PIN_4_CNP;
2259                 break;
2260         case PORT_F:
2261                 ddc_pin = GMBUS_PIN_3_BXT;
2262                 break;
2263         default:
2264                 MISSING_CASE(port);
2265                 ddc_pin = GMBUS_PIN_1_BXT;
2266                 break;
2267         }
2268         return ddc_pin;
2269 }
2270
2271 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2272 {
2273         u8 ddc_pin;
2274
2275         switch (port) {
2276         case PORT_A:
2277                 ddc_pin = GMBUS_PIN_1_BXT;
2278                 break;
2279         case PORT_B:
2280                 ddc_pin = GMBUS_PIN_2_BXT;
2281                 break;
2282         case PORT_C:
2283                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2284                 break;
2285         case PORT_D:
2286                 ddc_pin = GMBUS_PIN_10_TC2_ICP;
2287                 break;
2288         case PORT_E:
2289                 ddc_pin = GMBUS_PIN_11_TC3_ICP;
2290                 break;
2291         case PORT_F:
2292                 ddc_pin = GMBUS_PIN_12_TC4_ICP;
2293                 break;
2294         default:
2295                 MISSING_CASE(port);
2296                 ddc_pin = GMBUS_PIN_2_BXT;
2297                 break;
2298         }
2299         return ddc_pin;
2300 }
2301
2302 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2303                               enum port port)
2304 {
2305         u8 ddc_pin;
2306
2307         switch (port) {
2308         case PORT_B:
2309                 ddc_pin = GMBUS_PIN_DPB;
2310                 break;
2311         case PORT_C:
2312                 ddc_pin = GMBUS_PIN_DPC;
2313                 break;
2314         case PORT_D:
2315                 ddc_pin = GMBUS_PIN_DPD;
2316                 break;
2317         default:
2318                 MISSING_CASE(port);
2319                 ddc_pin = GMBUS_PIN_DPB;
2320                 break;
2321         }
2322         return ddc_pin;
2323 }
2324
2325 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2326                              enum port port)
2327 {
2328         const struct ddi_vbt_port_info *info =
2329                 &dev_priv->vbt.ddi_port_info[port];
2330         u8 ddc_pin;
2331
2332         if (info->alternate_ddc_pin) {
2333                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2334                               info->alternate_ddc_pin, port_name(port));
2335                 return info->alternate_ddc_pin;
2336         }
2337
2338         if (IS_CHERRYVIEW(dev_priv))
2339                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2340         else if (IS_GEN9_LP(dev_priv))
2341                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2342         else if (HAS_PCH_CNP(dev_priv))
2343                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2344         else if (HAS_PCH_ICP(dev_priv))
2345                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2346         else
2347                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2348
2349         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2350                       ddc_pin, port_name(port));
2351
2352         return ddc_pin;
2353 }
2354
2355 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
2356 {
2357         struct drm_i915_private *dev_priv =
2358                 to_i915(intel_dig_port->base.base.dev);
2359
2360         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2361                 intel_dig_port->write_infoframe = vlv_write_infoframe;
2362                 intel_dig_port->set_infoframes = vlv_set_infoframes;
2363                 intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
2364         } else if (IS_G4X(dev_priv)) {
2365                 intel_dig_port->write_infoframe = g4x_write_infoframe;
2366                 intel_dig_port->set_infoframes = g4x_set_infoframes;
2367                 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
2368         } else if (HAS_DDI(dev_priv)) {
2369                 if (intel_dig_port->lspcon.active) {
2370                         intel_dig_port->write_infoframe =
2371                                         lspcon_write_infoframe;
2372                         intel_dig_port->set_infoframes = lspcon_set_infoframes;
2373                         intel_dig_port->infoframe_enabled =
2374                                                 lspcon_infoframe_enabled;
2375                 } else {
2376                         intel_dig_port->set_infoframes = hsw_set_infoframes;
2377                         intel_dig_port->infoframe_enabled =
2378                                                 hsw_infoframe_enabled;
2379                         intel_dig_port->write_infoframe = hsw_write_infoframe;
2380                 }
2381         } else if (HAS_PCH_IBX(dev_priv)) {
2382                 intel_dig_port->write_infoframe = ibx_write_infoframe;
2383                 intel_dig_port->set_infoframes = ibx_set_infoframes;
2384                 intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
2385         } else {
2386                 intel_dig_port->write_infoframe = cpt_write_infoframe;
2387                 intel_dig_port->set_infoframes = cpt_set_infoframes;
2388                 intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
2389         }
2390 }
2391
2392 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2393                                struct intel_connector *intel_connector)
2394 {
2395         struct drm_connector *connector = &intel_connector->base;
2396         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2397         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2398         struct drm_device *dev = intel_encoder->base.dev;
2399         struct drm_i915_private *dev_priv = to_i915(dev);
2400         enum port port = intel_encoder->port;
2401
2402         DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2403                       port_name(port));
2404
2405         if (WARN(intel_dig_port->max_lanes < 4,
2406                  "Not enough lanes (%d) for HDMI on port %c\n",
2407                  intel_dig_port->max_lanes, port_name(port)))
2408                 return;
2409
2410         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2411                            DRM_MODE_CONNECTOR_HDMIA);
2412         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2413
2414         connector->interlace_allowed = 1;
2415         connector->doublescan_allowed = 0;
2416         connector->stereo_allowed = 1;
2417
2418         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2419                 connector->ycbcr_420_allowed = true;
2420
2421         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2422
2423         if (WARN_ON(port == PORT_A))
2424                 return;
2425         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
2426
2427         if (HAS_DDI(dev_priv))
2428                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2429         else
2430                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2431
2432         intel_hdmi_add_properties(intel_hdmi, connector);
2433
2434         if (is_hdcp_supported(dev_priv, port)) {
2435                 int ret = intel_hdcp_init(intel_connector,
2436                                           &intel_hdmi_hdcp_shim);
2437                 if (ret)
2438                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
2439         }
2440
2441         intel_connector_attach_encoder(intel_connector, intel_encoder);
2442         intel_hdmi->attached_connector = intel_connector;
2443
2444         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2445          * 0xd.  Failure to do so will result in spurious interrupts being
2446          * generated on the port when a cable is not attached.
2447          */
2448         if (IS_G45(dev_priv)) {
2449                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2450                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2451         }
2452
2453         intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
2454                                                          port_identifier(port));
2455         if (!intel_hdmi->cec_notifier)
2456                 DRM_DEBUG_KMS("CEC notifier get failed\n");
2457 }
2458
2459 void intel_hdmi_init(struct drm_i915_private *dev_priv,
2460                      i915_reg_t hdmi_reg, enum port port)
2461 {
2462         struct intel_digital_port *intel_dig_port;
2463         struct intel_encoder *intel_encoder;
2464         struct intel_connector *intel_connector;
2465
2466         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2467         if (!intel_dig_port)
2468                 return;
2469
2470         intel_connector = intel_connector_alloc();
2471         if (!intel_connector) {
2472                 kfree(intel_dig_port);
2473                 return;
2474         }
2475
2476         intel_encoder = &intel_dig_port->base;
2477
2478         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2479                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2480                          "HDMI %c", port_name(port));
2481
2482         intel_encoder->hotplug = intel_encoder_hotplug;
2483         intel_encoder->compute_config = intel_hdmi_compute_config;
2484         if (HAS_PCH_SPLIT(dev_priv)) {
2485                 intel_encoder->disable = pch_disable_hdmi;
2486                 intel_encoder->post_disable = pch_post_disable_hdmi;
2487         } else {
2488                 intel_encoder->disable = g4x_disable_hdmi;
2489         }
2490         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2491         intel_encoder->get_config = intel_hdmi_get_config;
2492         if (IS_CHERRYVIEW(dev_priv)) {
2493                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2494                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2495                 intel_encoder->enable = vlv_enable_hdmi;
2496                 intel_encoder->post_disable = chv_hdmi_post_disable;
2497                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2498         } else if (IS_VALLEYVIEW(dev_priv)) {
2499                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2500                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2501                 intel_encoder->enable = vlv_enable_hdmi;
2502                 intel_encoder->post_disable = vlv_hdmi_post_disable;
2503         } else {
2504                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2505                 if (HAS_PCH_CPT(dev_priv))
2506                         intel_encoder->enable = cpt_enable_hdmi;
2507                 else if (HAS_PCH_IBX(dev_priv))
2508                         intel_encoder->enable = ibx_enable_hdmi;
2509                 else
2510                         intel_encoder->enable = g4x_enable_hdmi;
2511         }
2512
2513         intel_encoder->type = INTEL_OUTPUT_HDMI;
2514         intel_encoder->power_domain = intel_port_to_power_domain(port);
2515         intel_encoder->port = port;
2516         if (IS_CHERRYVIEW(dev_priv)) {
2517                 if (port == PORT_D)
2518                         intel_encoder->crtc_mask = 1 << 2;
2519                 else
2520                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2521         } else {
2522                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2523         }
2524         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2525         /*
2526          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2527          * to work on real hardware. And since g4x can send infoframes to
2528          * only one port anyway, nothing is lost by allowing it.
2529          */
2530         if (IS_G4X(dev_priv))
2531                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2532
2533         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2534         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2535         intel_dig_port->max_lanes = 4;
2536
2537         intel_infoframe_init(intel_dig_port);
2538
2539         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
2540         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2541 }