1 /* SPDX-License-Identifier: MIT */
3 * Copyright (C) 2017 Google, Inc.
6 * Sean Paul <seanpaul@chromium.org>
10 #include <drm/drm_hdcp.h>
11 #include <linux/i2c.h>
12 #include <linux/random.h>
14 #include "intel_drv.h"
17 #define KEY_LOAD_TRIES 5
20 bool intel_hdcp_is_ksv_valid(u8 *ksv)
23 /* KSV has 20 1's and 20 0's */
24 for (i = 0; i < DRM_HDCP_KSV_LEN; i++)
25 ones += hweight8(ksv[i]);
33 int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port,
34 const struct intel_hdcp_shim *shim, u8 *bksv)
36 int ret, i, tries = 2;
38 /* HDCP spec states that we must retry the bksv if it is invalid */
39 for (i = 0; i < tries; i++) {
40 ret = shim->read_bksv(intel_dig_port, bksv);
43 if (intel_hdcp_is_ksv_valid(bksv))
47 DRM_DEBUG_KMS("Bksv is invalid\n");
54 /* Is HDCP1.4 capable on Platform and Sink */
55 bool intel_hdcp_capable(struct intel_connector *connector)
57 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
58 const struct intel_hdcp_shim *shim = connector->hdcp.shim;
65 if (shim->hdcp_capable) {
66 shim->hdcp_capable(intel_dig_port, &capable);
68 if (!intel_hdcp_read_valid_bksv(intel_dig_port, shim, bksv))
75 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
76 const struct intel_hdcp_shim *shim)
81 /* Poll for ksv list ready (spec says max time allowed is 5s) */
82 ret = __wait_for(read_ret = shim->read_ksv_ready(intel_dig_port,
84 read_ret || ksv_ready, 5 * 1000 * 1000, 1000,
96 static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
98 struct i915_power_domains *power_domains = &dev_priv->power_domains;
99 struct i915_power_well *power_well;
100 enum i915_power_well_id id;
101 bool enabled = false;
104 * On HSW and BDW, Display HW loads the Key as soon as Display resumes.
105 * On all BXT+, SW can load the keys only when the PW#1 is turned on.
107 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
108 id = HSW_DISP_PW_GLOBAL;
112 mutex_lock(&power_domains->lock);
114 /* PG1 (power well #1) needs to be enabled */
115 for_each_power_well(dev_priv, power_well) {
116 if (power_well->desc->id == id) {
117 enabled = power_well->desc->ops->is_enabled(dev_priv,
122 mutex_unlock(&power_domains->lock);
125 * Another req for hdcp key loadability is enabled state of pll for
126 * cdclk. Without active crtc we wont land here. So we are assuming that
127 * cdclk is already on.
133 static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv)
135 I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
136 I915_WRITE(HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS |
137 HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE);
140 static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
145 val = I915_READ(HDCP_KEY_STATUS);
146 if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS))
150 * On HSW and BDW HW loads the HDCP1.4 Key when Display comes
151 * out of reset. So if Key is not already loaded, its an error state.
153 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
154 if (!(I915_READ(HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE))
158 * Initiate loading the HDCP key from fuses.
160 * BXT+ platforms, HDCP key needs to be loaded by SW. Only SKL and KBL
161 * differ in the key load trigger process from other platforms.
163 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
164 mutex_lock(&dev_priv->pcu_lock);
165 ret = sandybridge_pcode_write(dev_priv,
166 SKL_PCODE_LOAD_HDCP_KEYS, 1);
167 mutex_unlock(&dev_priv->pcu_lock);
169 DRM_ERROR("Failed to initiate HDCP key load (%d)\n",
174 I915_WRITE(HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER);
177 /* Wait for the keys to load (500us) */
178 ret = __intel_wait_for_register(dev_priv, HDCP_KEY_STATUS,
179 HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE,
183 else if (!(val & HDCP_KEY_LOAD_STATUS))
186 /* Send Aksv over to PCH display for use in authentication */
187 I915_WRITE(HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER);
192 /* Returns updated SHA-1 index */
193 static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text)
195 I915_WRITE(HDCP_SHA_TEXT, sha_text);
196 if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
197 HDCP_SHA1_READY, HDCP_SHA1_READY, 1)) {
198 DRM_ERROR("Timed out waiting for SHA1 ready\n");
205 u32 intel_hdcp_get_repeater_ctl(struct intel_digital_port *intel_dig_port)
207 enum port port = intel_dig_port->base.port;
210 return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0;
212 return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0;
214 return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0;
216 return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0;
218 return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0;
222 DRM_ERROR("Unknown port %d\n", port);
227 int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
228 const struct intel_hdcp_shim *shim,
229 u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)
231 struct drm_i915_private *dev_priv;
232 u32 vprime, sha_text, sha_leftovers, rep_ctl;
233 int ret, i, j, sha_idx;
235 dev_priv = intel_dig_port->base.base.dev->dev_private;
237 /* Process V' values from the receiver */
238 for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
239 ret = shim->read_v_prime_part(intel_dig_port, i, &vprime);
242 I915_WRITE(HDCP_SHA_V_PRIME(i), vprime);
246 * We need to write the concatenation of all device KSVs, BINFO (DP) ||
247 * BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte
248 * stream is written via the HDCP_SHA_TEXT register in 32-bit
249 * increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This
250 * index will keep track of our progress through the 64 bytes as well as
251 * helping us work the 40-bit KSVs through our 32-bit register.
253 * NOTE: data passed via HDCP_SHA_TEXT should be big-endian
258 rep_ctl = intel_hdcp_get_repeater_ctl(intel_dig_port);
259 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
260 for (i = 0; i < num_downstream; i++) {
261 unsigned int sha_empty;
262 u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN];
264 /* Fill up the empty slots in sha_text and write it out */
265 sha_empty = sizeof(sha_text) - sha_leftovers;
266 for (j = 0; j < sha_empty; j++)
267 sha_text |= ksv[j] << ((sizeof(sha_text) - j - 1) * 8);
269 ret = intel_write_sha_text(dev_priv, sha_text);
273 /* Programming guide writes this every 64 bytes */
274 sha_idx += sizeof(sha_text);
276 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
278 /* Store the leftover bytes from the ksv in sha_text */
279 sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty;
281 for (j = 0; j < sha_leftovers; j++)
282 sha_text |= ksv[sha_empty + j] <<
283 ((sizeof(sha_text) - j - 1) * 8);
286 * If we still have room in sha_text for more data, continue.
287 * Otherwise, write it out immediately.
289 if (sizeof(sha_text) > sha_leftovers)
292 ret = intel_write_sha_text(dev_priv, sha_text);
297 sha_idx += sizeof(sha_text);
301 * We need to write BINFO/BSTATUS, and M0 now. Depending on how many
302 * bytes are leftover from the last ksv, we might be able to fit them
303 * all in sha_text (first 2 cases), or we might need to split them up
304 * into 2 writes (last 2 cases).
306 if (sha_leftovers == 0) {
307 /* Write 16 bits of text, 16 bits of M0 */
308 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16);
309 ret = intel_write_sha_text(dev_priv,
310 bstatus[0] << 8 | bstatus[1]);
313 sha_idx += sizeof(sha_text);
315 /* Write 32 bits of M0 */
316 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0);
317 ret = intel_write_sha_text(dev_priv, 0);
320 sha_idx += sizeof(sha_text);
322 /* Write 16 bits of M0 */
323 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16);
324 ret = intel_write_sha_text(dev_priv, 0);
327 sha_idx += sizeof(sha_text);
329 } else if (sha_leftovers == 1) {
330 /* Write 24 bits of text, 8 bits of M0 */
331 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_24);
332 sha_text |= bstatus[0] << 16 | bstatus[1] << 8;
333 /* Only 24-bits of data, must be in the LSB */
334 sha_text = (sha_text & 0xffffff00) >> 8;
335 ret = intel_write_sha_text(dev_priv, sha_text);
338 sha_idx += sizeof(sha_text);
340 /* Write 32 bits of M0 */
341 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0);
342 ret = intel_write_sha_text(dev_priv, 0);
345 sha_idx += sizeof(sha_text);
347 /* Write 24 bits of M0 */
348 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_8);
349 ret = intel_write_sha_text(dev_priv, 0);
352 sha_idx += sizeof(sha_text);
354 } else if (sha_leftovers == 2) {
355 /* Write 32 bits of text */
356 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
357 sha_text |= bstatus[0] << 24 | bstatus[1] << 16;
358 ret = intel_write_sha_text(dev_priv, sha_text);
361 sha_idx += sizeof(sha_text);
363 /* Write 64 bits of M0 */
364 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0);
365 for (i = 0; i < 2; i++) {
366 ret = intel_write_sha_text(dev_priv, 0);
369 sha_idx += sizeof(sha_text);
371 } else if (sha_leftovers == 3) {
372 /* Write 32 bits of text */
373 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
374 sha_text |= bstatus[0] << 24;
375 ret = intel_write_sha_text(dev_priv, sha_text);
378 sha_idx += sizeof(sha_text);
380 /* Write 8 bits of text, 24 bits of M0 */
381 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_8);
382 ret = intel_write_sha_text(dev_priv, bstatus[1]);
385 sha_idx += sizeof(sha_text);
387 /* Write 32 bits of M0 */
388 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0);
389 ret = intel_write_sha_text(dev_priv, 0);
392 sha_idx += sizeof(sha_text);
394 /* Write 8 bits of M0 */
395 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_24);
396 ret = intel_write_sha_text(dev_priv, 0);
399 sha_idx += sizeof(sha_text);
401 DRM_DEBUG_KMS("Invalid number of leftovers %d\n",
406 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32);
407 /* Fill up to 64-4 bytes with zeros (leave the last write for length) */
408 while ((sha_idx % 64) < (64 - sizeof(sha_text))) {
409 ret = intel_write_sha_text(dev_priv, 0);
412 sha_idx += sizeof(sha_text);
416 * Last write gets the length of the concatenation in bits. That is:
417 * - 5 bytes per device
418 * - 10 bytes for BINFO/BSTATUS(2), M0(8)
420 sha_text = (num_downstream * 5 + 10) * 8;
421 ret = intel_write_sha_text(dev_priv, sha_text);
425 /* Tell the HW we're done with the hash and wait for it to ACK */
426 I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_COMPLETE_HASH);
427 if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
429 HDCP_SHA1_COMPLETE, 1)) {
430 DRM_ERROR("Timed out waiting for SHA1 complete\n");
433 if (!(I915_READ(HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {
434 DRM_DEBUG_KMS("SHA-1 mismatch, HDCP failed\n");
441 /* Implements Part 2 of the HDCP authorization procedure */
443 int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
444 const struct intel_hdcp_shim *shim)
446 u8 bstatus[2], num_downstream, *ksv_fifo;
447 int ret, i, tries = 3;
449 ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
451 DRM_DEBUG_KMS("KSV list failed to become ready (%d)\n", ret);
455 ret = shim->read_bstatus(intel_dig_port, bstatus);
459 if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
460 DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
461 DRM_DEBUG_KMS("Max Topology Limit Exceeded\n");
466 * When repeater reports 0 device count, HDCP1.4 spec allows disabling
467 * the HDCP encryption. That implies that repeater can't have its own
468 * display. As there is no consumption of encrypted content in the
469 * repeater with 0 downstream devices, we are failing the
472 num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
473 if (num_downstream == 0)
476 ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL);
480 ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
485 * When V prime mismatches, DP Spec mandates re-read of
486 * V prime atleast twice.
488 for (i = 0; i < tries; i++) {
489 ret = intel_hdcp_validate_v_prime(intel_dig_port, shim,
490 ksv_fifo, num_downstream,
497 DRM_DEBUG_KMS("V Prime validation failed.(%d)\n", ret);
501 DRM_DEBUG_KMS("HDCP is enabled (%d downstream devices)\n",
509 /* Implements Part 1 of the HDCP authorization procedure */
510 static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
511 const struct intel_hdcp_shim *shim)
513 struct drm_i915_private *dev_priv;
515 unsigned long r0_prime_gen_start;
516 int ret, i, tries = 2;
519 u8 shim[DRM_HDCP_AN_LEN];
523 u8 shim[DRM_HDCP_KSV_LEN];
527 u8 shim[DRM_HDCP_RI_LEN];
529 bool repeater_present, hdcp_capable;
531 dev_priv = intel_dig_port->base.base.dev->dev_private;
533 port = intel_dig_port->base.port;
536 * Detects whether the display is HDCP capable. Although we check for
537 * valid Bksv below, the HDCP over DP spec requires that we check
538 * whether the display supports HDCP before we write An. For HDMI
539 * displays, this is not necessary.
541 if (shim->hdcp_capable) {
542 ret = shim->hdcp_capable(intel_dig_port, &hdcp_capable);
546 DRM_DEBUG_KMS("Panel is not HDCP capable\n");
551 /* Initialize An with 2 random values and acquire it */
552 for (i = 0; i < 2; i++)
553 I915_WRITE(PORT_HDCP_ANINIT(port), get_random_u32());
554 I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_CAPTURE_AN);
556 /* Wait for An to be acquired */
557 if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port),
558 HDCP_STATUS_AN_READY,
559 HDCP_STATUS_AN_READY, 1)) {
560 DRM_ERROR("Timed out waiting for An\n");
564 an.reg[0] = I915_READ(PORT_HDCP_ANLO(port));
565 an.reg[1] = I915_READ(PORT_HDCP_ANHI(port));
566 ret = shim->write_an_aksv(intel_dig_port, an.shim);
570 r0_prime_gen_start = jiffies;
572 memset(&bksv, 0, sizeof(bksv));
574 ret = intel_hdcp_read_valid_bksv(intel_dig_port, shim, bksv.shim);
578 I915_WRITE(PORT_HDCP_BKSVLO(port), bksv.reg[0]);
579 I915_WRITE(PORT_HDCP_BKSVHI(port), bksv.reg[1]);
581 ret = shim->repeater_present(intel_dig_port, &repeater_present);
584 if (repeater_present)
585 I915_WRITE(HDCP_REP_CTL,
586 intel_hdcp_get_repeater_ctl(intel_dig_port));
588 ret = shim->toggle_signalling(intel_dig_port, true);
592 I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_AUTH_AND_ENC);
594 /* Wait for R0 ready */
595 if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
596 (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) {
597 DRM_ERROR("Timed out waiting for R0 ready\n");
602 * Wait for R0' to become available. The spec says 100ms from Aksv, but
603 * some monitors can take longer than this. We'll set the timeout at
604 * 300ms just to be sure.
606 * On DP, there's an R0_READY bit available but no such bit
607 * exists on HDMI. Since the upper-bound is the same, we'll just do
608 * the stupid thing instead of polling on one and not the other.
610 wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300);
615 * DP HDCP Spec mandates the two more reattempt to read R0, incase
618 for (i = 0; i < tries; i++) {
620 ret = shim->read_ri_prime(intel_dig_port, ri.shim);
623 I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
625 /* Wait for Ri prime match */
626 if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
627 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
632 DRM_DEBUG_KMS("Timed out waiting for Ri prime match (%x)\n",
633 I915_READ(PORT_HDCP_STATUS(port)));
637 /* Wait for encryption confirmation */
638 if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port),
639 HDCP_STATUS_ENC, HDCP_STATUS_ENC, 20)) {
640 DRM_ERROR("Timed out waiting for encryption\n");
645 * XXX: If we have MST-connected devices, we need to enable encryption
649 if (repeater_present)
650 return intel_hdcp_auth_downstream(intel_dig_port, shim);
652 DRM_DEBUG_KMS("HDCP is enabled (no repeater present)\n");
656 static int _intel_hdcp_disable(struct intel_connector *connector)
658 struct intel_hdcp *hdcp = &connector->hdcp;
659 struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
660 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
661 enum port port = intel_dig_port->base.port;
664 DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n",
665 connector->base.name, connector->base.base.id);
667 I915_WRITE(PORT_HDCP_CONF(port), 0);
668 if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port), ~0, 0,
670 DRM_ERROR("Failed to disable HDCP, timeout clearing status\n");
674 ret = hdcp->shim->toggle_signalling(intel_dig_port, false);
676 DRM_ERROR("Failed to disable HDCP signalling\n");
680 DRM_DEBUG_KMS("HDCP is disabled\n");
684 static int _intel_hdcp_enable(struct intel_connector *connector)
686 struct intel_hdcp *hdcp = &connector->hdcp;
687 struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
688 int i, ret, tries = 3;
690 DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n",
691 connector->base.name, connector->base.base.id);
693 if (!hdcp_key_loadable(dev_priv)) {
694 DRM_ERROR("HDCP key Load is not possible\n");
698 for (i = 0; i < KEY_LOAD_TRIES; i++) {
699 ret = intel_hdcp_load_keys(dev_priv);
702 intel_hdcp_clear_keys(dev_priv);
705 DRM_ERROR("Could not load HDCP keys, (%d)\n", ret);
709 /* Incase of authentication failures, HDCP spec expects reauth. */
710 for (i = 0; i < tries; i++) {
711 ret = intel_hdcp_auth(conn_to_dig_port(connector), hdcp->shim);
715 DRM_DEBUG_KMS("HDCP Auth failure (%d)\n", ret);
717 /* Ensuring HDCP encryption and signalling are stopped. */
718 _intel_hdcp_disable(connector);
721 DRM_DEBUG_KMS("HDCP authentication failed (%d tries/%d)\n", tries, ret);
726 struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp)
728 return container_of(hdcp, struct intel_connector, hdcp);
731 static void intel_hdcp_check_work(struct work_struct *work)
733 struct intel_hdcp *hdcp = container_of(to_delayed_work(work),
736 struct intel_connector *connector = intel_hdcp_to_connector(hdcp);
738 if (!intel_hdcp_check_link(connector))
739 schedule_delayed_work(&hdcp->check_work,
740 DRM_HDCP_CHECK_PERIOD_MS);
743 static void intel_hdcp_prop_work(struct work_struct *work)
745 struct intel_hdcp *hdcp = container_of(work, struct intel_hdcp,
747 struct intel_connector *connector = intel_hdcp_to_connector(hdcp);
748 struct drm_device *dev = connector->base.dev;
749 struct drm_connector_state *state;
751 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
752 mutex_lock(&hdcp->mutex);
755 * This worker is only used to flip between ENABLED/DESIRED. Either of
756 * those to UNDESIRED is handled by core. If value == UNDESIRED,
757 * we're running just after hdcp has been disabled, so just exit
759 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
760 state = connector->base.state;
761 state->content_protection = hdcp->value;
764 mutex_unlock(&hdcp->mutex);
765 drm_modeset_unlock(&dev->mode_config.connection_mutex);
768 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
770 /* PORT E doesn't have HDCP, and PORT F is disabled */
771 return ((INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
772 !IS_CHERRYVIEW(dev_priv) && port < PORT_E);
775 int intel_hdcp_init(struct intel_connector *connector,
776 const struct intel_hdcp_shim *shim)
778 struct intel_hdcp *hdcp = &connector->hdcp;
781 ret = drm_connector_attach_content_protection_property(
787 mutex_init(&hdcp->mutex);
788 INIT_DELAYED_WORK(&hdcp->check_work, intel_hdcp_check_work);
789 INIT_WORK(&hdcp->prop_work, intel_hdcp_prop_work);
793 int intel_hdcp_enable(struct intel_connector *connector)
795 struct intel_hdcp *hdcp = &connector->hdcp;
801 mutex_lock(&hdcp->mutex);
803 ret = _intel_hdcp_enable(connector);
807 hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
808 schedule_work(&hdcp->prop_work);
809 schedule_delayed_work(&hdcp->check_work,
810 DRM_HDCP_CHECK_PERIOD_MS);
812 mutex_unlock(&hdcp->mutex);
816 int intel_hdcp_disable(struct intel_connector *connector)
818 struct intel_hdcp *hdcp = &connector->hdcp;
824 mutex_lock(&hdcp->mutex);
826 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
827 hdcp->value = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
828 ret = _intel_hdcp_disable(connector);
831 mutex_unlock(&hdcp->mutex);
832 cancel_delayed_work_sync(&hdcp->check_work);
836 void intel_hdcp_atomic_check(struct drm_connector *connector,
837 struct drm_connector_state *old_state,
838 struct drm_connector_state *new_state)
840 uint64_t old_cp = old_state->content_protection;
841 uint64_t new_cp = new_state->content_protection;
842 struct drm_crtc_state *crtc_state;
844 if (!new_state->crtc) {
846 * If the connector is being disabled with CP enabled, mark it
847 * desired so it's re-enabled when the connector is brought back
849 if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)
850 new_state->content_protection =
851 DRM_MODE_CONTENT_PROTECTION_DESIRED;
856 * Nothing to do if the state didn't change, or HDCP was activated since
859 if (old_cp == new_cp ||
860 (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
861 new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED))
864 crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
866 crtc_state->mode_changed = true;
869 /* Implements Part 3 of the HDCP authorization procedure */
870 int intel_hdcp_check_link(struct intel_connector *connector)
872 struct intel_hdcp *hdcp = &connector->hdcp;
873 struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
874 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
875 enum port port = intel_dig_port->base.port;
881 mutex_lock(&hdcp->mutex);
883 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
886 if (!(I915_READ(PORT_HDCP_STATUS(port)) & HDCP_STATUS_ENC)) {
887 DRM_ERROR("%s:%d HDCP check failed: link is not encrypted,%x\n",
888 connector->base.name, connector->base.base.id,
889 I915_READ(PORT_HDCP_STATUS(port)));
891 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
892 schedule_work(&hdcp->prop_work);
896 if (hdcp->shim->check_link(intel_dig_port)) {
897 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
898 hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED;
899 schedule_work(&hdcp->prop_work);
904 DRM_DEBUG_KMS("[%s:%d] HDCP link failed, retrying authentication\n",
905 connector->base.name, connector->base.base.id);
907 ret = _intel_hdcp_disable(connector);
909 DRM_ERROR("Failed to disable hdcp (%d)\n", ret);
910 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
911 schedule_work(&hdcp->prop_work);
915 ret = _intel_hdcp_enable(connector);
917 DRM_DEBUG_KMS("Failed to enable hdcp (%d)\n", ret);
918 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
919 schedule_work(&hdcp->prop_work);
924 mutex_unlock(&hdcp->mutex);