2 * Copyright © 2014-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef _INTEL_GUC_SUBMISSION_H_
26 #define _INTEL_GUC_SUBMISSION_H_
28 #include <linux/spinlock.h>
31 #include "i915_selftest.h"
33 struct drm_i915_private;
36 * This structure primarily describes the GEM object shared with the GuC.
37 * The specs sometimes refer to this object as a "GuC context", but we use
38 * the term "client" to avoid confusion with hardware contexts. This
39 * GEM object is held for the entire lifetime of our interaction with
40 * the GuC, being allocated before the GuC is loaded with its firmware.
41 * Because there's no way to update the address used by the GuC after
42 * initialisation, the shared object must stay pinned into the GGTT as
43 * long as the GuC is in use. We also keep the first page (only) mapped
44 * into kernel address space, as it includes shared data that must be
45 * updated on every request submission.
47 * The single GEM object described here is actually made up of several
48 * separate areas, as far as the GuC is concerned. The first page (kept
49 * kmap'd) includes the "process descriptor" which holds sequence data for
50 * the doorbell, and one cacheline which actually *is* the doorbell; a
51 * write to this will "ring the doorbell" (i.e. send an interrupt to the
52 * GuC). The subsequent pages of the client object constitute the work
53 * queue (a circular array of work items), again described in the process
54 * descriptor. Work queue pages are mapped momentarily as required.
56 struct intel_guc_client {
59 struct i915_gem_context *owner;
60 struct intel_guc *guc;
62 /* bitmap of (host) engine ids */
69 unsigned long doorbell_offset;
71 /* Protects GuC client's WQ access */
73 /* Per-engine counts of GuC submissions */
74 u64 submissions[I915_NUM_ENGINES];
76 /* For testing purposes, use nop WQ items instead of real ones */
77 I915_SELFTEST_DECLARE(bool use_nop_wqi);
80 int intel_guc_submission_init(struct intel_guc *guc);
81 int intel_guc_submission_enable(struct intel_guc *guc);
82 void intel_guc_submission_disable(struct intel_guc *guc);
83 void intel_guc_submission_fini(struct intel_guc *guc);
84 int intel_guc_preempt_work_create(struct intel_guc *guc);
85 void intel_guc_preempt_work_destroy(struct intel_guc *guc);