2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Vinit Azad <vinit.azad@intel.com>
25 * Ben Widawsky <ben@bwidawsk.net>
26 * Dave Gordon <david.s.gordon@intel.com>
27 * Alex Dai <yu.dai@intel.com>
30 #include "intel_guc_fw.h"
33 #define SKL_FW_MAJOR 6
34 #define SKL_FW_MINOR 1
36 #define BXT_FW_MAJOR 8
37 #define BXT_FW_MINOR 7
39 #define KBL_FW_MAJOR 9
40 #define KBL_FW_MINOR 14
42 #define GLK_FW_MAJOR 10
43 #define GLK_FW_MINOR 56
45 #define GUC_FW_PATH(platform, major, minor) \
46 "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin"
48 #define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR)
49 MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
51 #define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR)
52 MODULE_FIRMWARE(I915_BXT_GUC_UCODE);
54 #define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR)
55 MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
57 #define I915_GLK_GUC_UCODE GUC_FW_PATH(glk, GLK_FW_MAJOR, GLK_FW_MINOR)
60 * intel_guc_fw_select() - selects GuC firmware for uploading
62 * @guc: intel_guc struct
64 * Return: zero when we know firmware, non-zero in other case
66 int intel_guc_fw_select(struct intel_guc *guc)
68 struct drm_i915_private *dev_priv = guc_to_i915(guc);
70 intel_uc_fw_init(&guc->fw, INTEL_UC_FW_TYPE_GUC);
72 if (i915_modparams.guc_firmware_path) {
73 guc->fw.path = i915_modparams.guc_firmware_path;
74 guc->fw.major_ver_wanted = 0;
75 guc->fw.minor_ver_wanted = 0;
76 } else if (IS_SKYLAKE(dev_priv)) {
77 guc->fw.path = I915_SKL_GUC_UCODE;
78 guc->fw.major_ver_wanted = SKL_FW_MAJOR;
79 guc->fw.minor_ver_wanted = SKL_FW_MINOR;
80 } else if (IS_BROXTON(dev_priv)) {
81 guc->fw.path = I915_BXT_GUC_UCODE;
82 guc->fw.major_ver_wanted = BXT_FW_MAJOR;
83 guc->fw.minor_ver_wanted = BXT_FW_MINOR;
84 } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
85 guc->fw.path = I915_KBL_GUC_UCODE;
86 guc->fw.major_ver_wanted = KBL_FW_MAJOR;
87 guc->fw.minor_ver_wanted = KBL_FW_MINOR;
88 } else if (IS_GEMINILAKE(dev_priv)) {
89 guc->fw.path = I915_GLK_GUC_UCODE;
90 guc->fw.major_ver_wanted = GLK_FW_MAJOR;
91 guc->fw.minor_ver_wanted = GLK_FW_MINOR;
93 DRM_ERROR("No GuC firmware known for platform with GuC!\n");
101 * Read the GuC status register (GUC_STATUS) and store it in the
102 * specified location; then return a boolean indicating whether
103 * the value matches either of two values representing completion
104 * of the GuC boot process.
106 * This is used for polling the GuC status in a wait_for()
109 static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
112 u32 val = I915_READ(GUC_STATUS);
113 u32 uk_val = val & GS_UKERNEL_MASK;
115 return (uk_val == GS_UKERNEL_READY ||
116 ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
120 * Transfer the firmware image to RAM for execution by the microcontroller.
122 * Architecturally, the DMA engine is bidirectional, and can potentially even
123 * transfer between GTT locations. This functionality is left out of the API
124 * for now as there is no need for it.
126 * Note that GuC needs the CSS header plus uKernel code to be copied by the
127 * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
129 static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
130 struct i915_vma *vma)
132 struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
133 unsigned long offset;
134 struct sg_table *sg = vma->pages;
135 u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
138 /* where RSA signature starts */
139 offset = guc_fw->rsa_offset;
141 /* Copy RSA signature from the fw image to HW for verification */
142 sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset);
143 for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++)
144 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
146 /* The header plus uCode will be copied to WOPCM via DMA, excluding any
147 * other components */
148 I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
150 /* Set the source address for the new blob */
151 offset = guc_ggtt_offset(vma) + guc_fw->header_offset;
152 I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
153 I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
156 * Set the DMA destination. Current uCode expects the code to be
157 * loaded at 8k; locations below this are used for the stack.
159 I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
160 I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
162 /* Finally start the DMA */
163 I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
166 * Wait for the DMA to complete & the GuC to start up.
167 * NB: Docs recommend not using the interrupt for completion.
168 * Measurements indicate this should take no more than 20ms, so a
169 * timeout here indicates that the GuC has failed and is unusable.
170 * (Higher levels of the driver will attempt to fall back to
171 * execlist mode if this happens.)
173 ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
175 DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
176 I915_READ(DMA_CTRL), status);
178 if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
179 DRM_ERROR("GuC firmware signature verification failed\n");
183 DRM_DEBUG_DRIVER("returning %d\n", ret);
189 * Load the GuC firmware blob into the MinuteIA.
191 static int guc_ucode_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
193 struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
194 struct drm_i915_private *dev_priv = guc_to_i915(guc);
197 GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
199 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
201 /* Enable MIA caching. GuC clock gating is disabled. */
202 I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
204 /* WaDisableMinuteIaClockGating:bxt */
205 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
206 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
207 ~GUC_ENABLE_MIA_CLOCK_GATING));
210 /* WaC6DisallowByGfxPause:bxt */
211 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
212 I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
214 if (IS_GEN9_LP(dev_priv))
215 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
217 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
219 if (IS_GEN9(dev_priv)) {
220 /* DOP Clock Gating Enable for GuC clocks */
221 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
222 I915_READ(GEN7_MISCCPCTL)));
224 /* allows for 5us (in 10ns units) before GT can go to RC6 */
225 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
228 ret = guc_ucode_xfer_dma(dev_priv, vma);
230 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
236 * intel_guc_fw_upload() - finish preparing the GuC for activity
237 * @guc: intel_guc structure
239 * Called during driver loading and also after a GPU reset.
241 * The main action required here it to load the GuC uCode into the device.
242 * The firmware image should have already been fetched into memory by the
243 * earlier call to intel_guc_init(), so here we need only check that
244 * worked, and then transfer the image to the h/w.
246 * Return: non-zero code on error
248 int intel_guc_fw_upload(struct intel_guc *guc)
250 return intel_uc_fw_upload(&guc->fw, guc_ucode_xfer);