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25 #include "intel_guc_ct.h"
27 #ifdef CONFIG_DRM_I915_DEBUG_GUC
28 #define CT_DEBUG_DRIVER(...) DRM_DEBUG_DRIVER(__VA_ARGS__)
30 #define CT_DEBUG_DRIVER(...) do { } while (0)
34 struct list_head link;
41 struct ct_incoming_request {
42 struct list_head link;
46 enum { CTB_SEND = 0, CTB_RECV = 1 };
48 enum { CTB_OWNER_HOST = 0 };
50 static void ct_incoming_request_worker_func(struct work_struct *w);
53 * intel_guc_ct_init_early - Initialize CT state without requiring device access
54 * @ct: pointer to CT struct
56 void intel_guc_ct_init_early(struct intel_guc_ct *ct)
58 /* we're using static channel owners */
59 ct->host_channel.owner = CTB_OWNER_HOST;
61 spin_lock_init(&ct->lock);
62 INIT_LIST_HEAD(&ct->pending_requests);
63 INIT_LIST_HEAD(&ct->incoming_requests);
64 INIT_WORK(&ct->worker, ct_incoming_request_worker_func);
67 static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
69 return container_of(ct, struct intel_guc, ct);
72 static inline const char *guc_ct_buffer_type_to_str(u32 type)
75 case INTEL_GUC_CT_BUFFER_TYPE_SEND:
77 case INTEL_GUC_CT_BUFFER_TYPE_RECV:
84 static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc,
85 u32 cmds_addr, u32 size, u32 owner)
87 CT_DEBUG_DRIVER("CT: desc %p init addr=%#x size=%u owner=%u\n",
88 desc, cmds_addr, size, owner);
89 memset(desc, 0, sizeof(*desc));
90 desc->addr = cmds_addr;
95 static void guc_ct_buffer_desc_reset(struct guc_ct_buffer_desc *desc)
97 CT_DEBUG_DRIVER("CT: desc %p reset head=%u tail=%u\n",
98 desc, desc->head, desc->tail);
101 desc->is_in_error = 0;
104 static int guc_action_register_ct_buffer(struct intel_guc *guc,
109 INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER,
111 sizeof(struct guc_ct_buffer_desc),
116 /* Can't use generic send(), CT registration must go over MMIO */
117 err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
119 DRM_ERROR("CT: register %s buffer failed; err=%d\n",
120 guc_ct_buffer_type_to_str(type), err);
124 static int guc_action_deregister_ct_buffer(struct intel_guc *guc,
129 INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER,
135 /* Can't use generic send(), CT deregistration must go over MMIO */
136 err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
138 DRM_ERROR("CT: deregister %s buffer failed; owner=%d err=%d\n",
139 guc_ct_buffer_type_to_str(type), owner, err);
143 static int ctch_init(struct intel_guc *guc,
144 struct intel_guc_ct_channel *ctch)
146 struct i915_vma *vma;
151 GEM_BUG_ON(ctch->vma);
153 /* We allocate 1 page to hold both descriptors and both buffers.
154 * ___________.....................
156 * |___________| PAGE/4
157 * :___________....................:
159 * |___________| PAGE/4
160 * :_______________________________:
163 * |_______________________________|
166 * |_______________________________|
168 * Each message can use a maximum of 32 dwords and we don't expect to
169 * have more than 1 in flight at any time, so we have enough space.
170 * Some logic further ahead will rely on the fact that there is only 1
171 * page and that it is always mapped, so if the size is changed the
172 * other code will need updating as well.
176 vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
184 blob = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
189 CT_DEBUG_DRIVER("CT: vma base=%#x\n",
190 intel_guc_ggtt_offset(guc, ctch->vma));
192 /* store pointers to desc and cmds */
193 for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
194 GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
195 ctch->ctbs[i].desc = blob + PAGE_SIZE/4 * i;
196 ctch->ctbs[i].cmds = blob + PAGE_SIZE/4 * i + PAGE_SIZE/2;
202 i915_vma_unpin_and_release(&ctch->vma, 0);
204 CT_DEBUG_DRIVER("CT: channel %d initialization failed; err=%d\n",
209 static void ctch_fini(struct intel_guc *guc,
210 struct intel_guc_ct_channel *ctch)
212 GEM_BUG_ON(ctch->enabled);
214 i915_vma_unpin_and_release(&ctch->vma, I915_VMA_RELEASE_MAP);
217 static int ctch_enable(struct intel_guc *guc,
218 struct intel_guc_ct_channel *ctch)
224 GEM_BUG_ON(!ctch->vma);
226 GEM_BUG_ON(ctch->enabled);
228 /* vma should be already allocated and map'ed */
229 base = intel_guc_ggtt_offset(guc, ctch->vma);
231 /* (re)initialize descriptors
232 * cmds buffers are in the second half of the blob page
234 for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
235 GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
236 guc_ct_buffer_desc_init(ctch->ctbs[i].desc,
237 base + PAGE_SIZE/4 * i + PAGE_SIZE/2,
242 /* register buffers, starting wirh RECV buffer
243 * descriptors are in first half of the blob
245 err = guc_action_register_ct_buffer(guc,
246 base + PAGE_SIZE/4 * CTB_RECV,
247 INTEL_GUC_CT_BUFFER_TYPE_RECV);
251 err = guc_action_register_ct_buffer(guc,
252 base + PAGE_SIZE/4 * CTB_SEND,
253 INTEL_GUC_CT_BUFFER_TYPE_SEND);
257 ctch->enabled = true;
262 guc_action_deregister_ct_buffer(guc,
264 INTEL_GUC_CT_BUFFER_TYPE_RECV);
266 DRM_ERROR("CT: can't open channel %d; err=%d\n", ctch->owner, err);
270 static void ctch_disable(struct intel_guc *guc,
271 struct intel_guc_ct_channel *ctch)
273 GEM_BUG_ON(!ctch->enabled);
275 ctch->enabled = false;
277 guc_action_deregister_ct_buffer(guc,
279 INTEL_GUC_CT_BUFFER_TYPE_SEND);
280 guc_action_deregister_ct_buffer(guc,
282 INTEL_GUC_CT_BUFFER_TYPE_RECV);
285 static u32 ctch_get_next_fence(struct intel_guc_ct_channel *ctch)
287 /* For now it's trivial */
288 return ++ctch->next_fence;
292 * DOC: CTB Host to GuC request
294 * Format of the CTB Host to GuC request message is as follows::
296 * +------------+---------+---------+---------+---------+
297 * | msg[0] | [1] | [2] | ... | [n-1] |
298 * +------------+---------+---------+---------+---------+
299 * | MESSAGE | MESSAGE PAYLOAD |
300 * + HEADER +---------+---------+---------+---------+
301 * | | 0 | 1 | ... | n |
302 * +============+=========+=========+=========+=========+
303 * | len >= 1 | FENCE | request specific data |
304 * +------+-----+---------+---------+---------+---------+
306 * ^-----------------len-------------------^
309 static int ctb_write(struct intel_guc_ct_buffer *ctb,
311 u32 len /* in dwords */,
315 struct guc_ct_buffer_desc *desc = ctb->desc;
316 u32 head = desc->head / 4; /* in dwords */
317 u32 tail = desc->tail / 4; /* in dwords */
318 u32 size = desc->size / 4; /* in dwords */
319 u32 used; /* in dwords */
321 u32 *cmds = ctb->cmds;
324 GEM_BUG_ON(desc->size % 4);
325 GEM_BUG_ON(desc->head % 4);
326 GEM_BUG_ON(desc->tail % 4);
327 GEM_BUG_ON(tail >= size);
330 * tail == head condition indicates empty. GuC FW does not support
331 * using up the entire buffer to get tail == head meaning full.
334 used = (size - head) + tail;
338 /* make sure there is a space including extra dw for the fence */
339 if (unlikely(used + len + 1 >= size))
343 * Write the message. The format is the following:
344 * DW0: header (including action code)
348 header = (len << GUC_CT_MSG_LEN_SHIFT) |
349 (GUC_CT_MSG_WRITE_FENCE_TO_DESC) |
350 (want_response ? GUC_CT_MSG_SEND_STATUS : 0) |
351 (action[0] << GUC_CT_MSG_ACTION_SHIFT);
353 CT_DEBUG_DRIVER("CT: writing %*ph %*ph %*ph\n",
354 4, &header, 4, &fence,
355 4 * (len - 1), &action[1]);
358 tail = (tail + 1) % size;
361 tail = (tail + 1) % size;
363 for (i = 1; i < len; i++) {
364 cmds[tail] = action[i];
365 tail = (tail + 1) % size;
368 /* now update desc tail (back in bytes) */
369 desc->tail = tail * 4;
370 GEM_BUG_ON(desc->tail > desc->size);
376 * wait_for_ctb_desc_update - Wait for the CT buffer descriptor update.
377 * @desc: buffer descriptor
378 * @fence: response fence
379 * @status: placeholder for status
381 * Guc will update CT buffer descriptor with new fence and status
382 * after processing the command identified by the fence. Wait for
383 * specified fence and then read from the descriptor status of the
387 * * 0 response received (status is valid)
388 * * -ETIMEDOUT no response within hardcoded timeout
389 * * -EPROTO no response, CT buffer is in error
391 static int wait_for_ctb_desc_update(struct guc_ct_buffer_desc *desc,
398 * Fast commands should complete in less than 10us, so sample quickly
399 * up to that length of time, then switch to a slower sleep-wait loop.
400 * No GuC command should ever take longer than 10ms.
402 #define done (READ_ONCE(desc->fence) == fence)
403 err = wait_for_us(done, 10);
405 err = wait_for(done, 10);
409 DRM_ERROR("CT: fence %u failed; reported fence=%u\n",
412 if (WARN_ON(desc->is_in_error)) {
413 /* Something went wrong with the messaging, try to reset
414 * the buffer and hope for the best
416 guc_ct_buffer_desc_reset(desc);
421 *status = desc->status;
426 * wait_for_ct_request_update - Wait for CT request state update.
427 * @req: pointer to pending request
428 * @status: placeholder for status
430 * For each sent request, Guc shall send bac CT response message.
431 * Our message handler will update status of tracked request once
432 * response message with given fence is received. Wait here and
433 * check for valid response status value.
436 * * 0 response received (status is valid)
437 * * -ETIMEDOUT no response within hardcoded timeout
439 static int wait_for_ct_request_update(struct ct_request *req, u32 *status)
444 * Fast commands should complete in less than 10us, so sample quickly
445 * up to that length of time, then switch to a slower sleep-wait loop.
446 * No GuC command should ever take longer than 10ms.
448 #define done INTEL_GUC_MSG_IS_RESPONSE(READ_ONCE(req->status))
449 err = wait_for_us(done, 10);
451 err = wait_for(done, 10);
455 DRM_ERROR("CT: fence %u err %d\n", req->fence, err);
457 *status = req->status;
461 static int ctch_send(struct intel_guc_ct *ct,
462 struct intel_guc_ct_channel *ctch,
466 u32 response_buf_size,
469 struct intel_guc_ct_buffer *ctb = &ctch->ctbs[CTB_SEND];
470 struct guc_ct_buffer_desc *desc = ctb->desc;
471 struct ct_request request;
476 GEM_BUG_ON(!ctch->enabled);
478 GEM_BUG_ON(len & ~GUC_CT_MSG_LEN_MASK);
479 GEM_BUG_ON(!response_buf && response_buf_size);
481 fence = ctch_get_next_fence(ctch);
482 request.fence = fence;
484 request.response_len = response_buf_size;
485 request.response_buf = response_buf;
487 spin_lock_irqsave(&ct->lock, flags);
488 list_add_tail(&request.link, &ct->pending_requests);
489 spin_unlock_irqrestore(&ct->lock, flags);
491 err = ctb_write(ctb, action, len, fence, !!response_buf);
495 intel_guc_notify(ct_to_guc(ct));
498 err = wait_for_ct_request_update(&request, status);
500 err = wait_for_ctb_desc_update(desc, fence, status);
504 if (!INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(*status)) {
510 /* There shall be no data in the status */
511 WARN_ON(INTEL_GUC_MSG_TO_DATA(request.status));
512 /* Return actual response len */
513 err = request.response_len;
515 /* There shall be no response payload */
516 WARN_ON(request.response_len);
517 /* Return data decoded from the status dword */
518 err = INTEL_GUC_MSG_TO_DATA(*status);
522 spin_lock_irqsave(&ct->lock, flags);
523 list_del(&request.link);
524 spin_unlock_irqrestore(&ct->lock, flags);
530 * Command Transport (CT) buffer based GuC send function.
532 static int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
533 u32 *response_buf, u32 response_buf_size)
535 struct intel_guc_ct *ct = &guc->ct;
536 struct intel_guc_ct_channel *ctch = &ct->host_channel;
537 u32 status = ~0; /* undefined */
540 mutex_lock(&guc->send_mutex);
542 ret = ctch_send(ct, ctch, action, len, response_buf, response_buf_size,
544 if (unlikely(ret < 0)) {
545 DRM_ERROR("CT: send action %#X failed; err=%d status=%#X\n",
546 action[0], ret, status);
547 } else if (unlikely(ret)) {
548 CT_DEBUG_DRIVER("CT: send action %#x returned %d (%#x)\n",
549 action[0], ret, ret);
552 mutex_unlock(&guc->send_mutex);
556 static inline unsigned int ct_header_get_len(u32 header)
558 return (header >> GUC_CT_MSG_LEN_SHIFT) & GUC_CT_MSG_LEN_MASK;
561 static inline unsigned int ct_header_get_action(u32 header)
563 return (header >> GUC_CT_MSG_ACTION_SHIFT) & GUC_CT_MSG_ACTION_MASK;
566 static inline bool ct_header_is_response(u32 header)
568 return !!(header & GUC_CT_MSG_IS_RESPONSE);
571 static int ctb_read(struct intel_guc_ct_buffer *ctb, u32 *data)
573 struct guc_ct_buffer_desc *desc = ctb->desc;
574 u32 head = desc->head / 4; /* in dwords */
575 u32 tail = desc->tail / 4; /* in dwords */
576 u32 size = desc->size / 4; /* in dwords */
577 u32 *cmds = ctb->cmds;
578 s32 available; /* in dwords */
582 GEM_BUG_ON(desc->size % 4);
583 GEM_BUG_ON(desc->head % 4);
584 GEM_BUG_ON(desc->tail % 4);
585 GEM_BUG_ON(tail >= size);
586 GEM_BUG_ON(head >= size);
588 /* tail == head condition indicates empty */
589 available = tail - head;
590 if (unlikely(available == 0))
593 /* beware of buffer wrap case */
594 if (unlikely(available < 0))
596 CT_DEBUG_DRIVER("CT: available %d (%u:%u)\n", available, head, tail);
597 GEM_BUG_ON(available < 0);
599 data[0] = cmds[head];
600 head = (head + 1) % size;
602 /* message len with header */
603 len = ct_header_get_len(data[0]) + 1;
604 if (unlikely(len > (u32)available)) {
605 DRM_ERROR("CT: incomplete message %*ph %*ph %*ph\n",
607 4 * (head + available - 1 > size ?
608 size - head : available - 1), &cmds[head],
609 4 * (head + available - 1 > size ?
610 available - 1 - size + head : 0), &cmds[0]);
614 for (i = 1; i < len; i++) {
615 data[i] = cmds[head];
616 head = (head + 1) % size;
618 CT_DEBUG_DRIVER("CT: received %*ph\n", 4 * len, data);
620 desc->head = head * 4;
625 * DOC: CTB GuC to Host response
627 * Format of the CTB GuC to Host response message is as follows::
629 * +------------+---------+---------+---------+---------+---------+
630 * | msg[0] | [1] | [2] | [3] | ... | [n-1] |
631 * +------------+---------+---------+---------+---------+---------+
632 * | MESSAGE | MESSAGE PAYLOAD |
633 * + HEADER +---------+---------+---------+---------+---------+
634 * | | 0 | 1 | 2 | ... | n |
635 * +============+=========+=========+=========+=========+=========+
636 * | len >= 2 | FENCE | STATUS | response specific data |
637 * +------+-----+---------+---------+---------+---------+---------+
639 * ^-----------------------len-----------------------^
642 static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
645 u32 len = ct_header_get_len(header);
646 u32 msglen = len + 1; /* total message length including header */
650 struct ct_request *req;
653 GEM_BUG_ON(!ct_header_is_response(header));
654 GEM_BUG_ON(!in_irq());
656 /* Response payload shall at least include fence and status */
657 if (unlikely(len < 2)) {
658 DRM_ERROR("CT: corrupted response %*ph\n", 4 * msglen, msg);
666 /* Format of the status follows RESPONSE message */
667 if (unlikely(!INTEL_GUC_MSG_IS_RESPONSE(status))) {
668 DRM_ERROR("CT: corrupted response %*ph\n", 4 * msglen, msg);
672 CT_DEBUG_DRIVER("CT: response fence %u status %#x\n", fence, status);
674 spin_lock(&ct->lock);
675 list_for_each_entry(req, &ct->pending_requests, link) {
676 if (unlikely(fence != req->fence)) {
677 CT_DEBUG_DRIVER("CT: request %u awaits response\n",
681 if (unlikely(datalen > req->response_len)) {
682 DRM_ERROR("CT: response %u too long %*ph\n",
683 req->fence, 4 * msglen, msg);
687 memcpy(req->response_buf, msg + 3, 4 * datalen);
688 req->response_len = datalen;
689 WRITE_ONCE(req->status, status);
693 spin_unlock(&ct->lock);
696 DRM_ERROR("CT: unsolicited response %*ph\n", 4 * msglen, msg);
700 static void ct_process_request(struct intel_guc_ct *ct,
701 u32 action, u32 len, const u32 *payload)
703 struct intel_guc *guc = ct_to_guc(ct);
706 CT_DEBUG_DRIVER("CT: request %x %*ph\n", action, 4 * len, payload);
709 case INTEL_GUC_ACTION_DEFAULT:
710 ret = intel_guc_to_host_process_recv_msg(guc, payload, len);
712 goto fail_unexpected;
717 DRM_ERROR("CT: unexpected request %x %*ph\n",
718 action, 4 * len, payload);
723 static bool ct_process_incoming_requests(struct intel_guc_ct *ct)
726 struct ct_incoming_request *request;
731 spin_lock_irqsave(&ct->lock, flags);
732 request = list_first_entry_or_null(&ct->incoming_requests,
733 struct ct_incoming_request, link);
735 list_del(&request->link);
736 done = !!list_empty(&ct->incoming_requests);
737 spin_unlock_irqrestore(&ct->lock, flags);
742 header = request->msg[0];
743 payload = &request->msg[1];
744 ct_process_request(ct,
745 ct_header_get_action(header),
746 ct_header_get_len(header),
753 static void ct_incoming_request_worker_func(struct work_struct *w)
755 struct intel_guc_ct *ct = container_of(w, struct intel_guc_ct, worker);
758 done = ct_process_incoming_requests(ct);
760 queue_work(system_unbound_wq, &ct->worker);
764 * DOC: CTB GuC to Host request
766 * Format of the CTB GuC to Host request message is as follows::
768 * +------------+---------+---------+---------+---------+---------+
769 * | msg[0] | [1] | [2] | [3] | ... | [n-1] |
770 * +------------+---------+---------+---------+---------+---------+
771 * | MESSAGE | MESSAGE PAYLOAD |
772 * + HEADER +---------+---------+---------+---------+---------+
773 * | | 0 | 1 | 2 | ... | n |
774 * +============+=========+=========+=========+=========+=========+
775 * | len | request specific data |
776 * +------+-----+---------+---------+---------+---------+---------+
778 * ^-----------------------len-----------------------^
781 static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg)
784 u32 len = ct_header_get_len(header);
785 u32 msglen = len + 1; /* total message length including header */
786 struct ct_incoming_request *request;
789 GEM_BUG_ON(ct_header_is_response(header));
791 request = kmalloc(sizeof(*request) + 4 * msglen, GFP_ATOMIC);
792 if (unlikely(!request)) {
793 DRM_ERROR("CT: dropping request %*ph\n", 4 * msglen, msg);
794 return 0; /* XXX: -ENOMEM ? */
796 memcpy(request->msg, msg, 4 * msglen);
798 spin_lock_irqsave(&ct->lock, flags);
799 list_add_tail(&request->link, &ct->incoming_requests);
800 spin_unlock_irqrestore(&ct->lock, flags);
802 queue_work(system_unbound_wq, &ct->worker);
806 static void ct_process_host_channel(struct intel_guc_ct *ct)
808 struct intel_guc_ct_channel *ctch = &ct->host_channel;
809 struct intel_guc_ct_buffer *ctb = &ctch->ctbs[CTB_RECV];
810 u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */
817 err = ctb_read(ctb, msg);
821 if (ct_header_is_response(msg[0]))
822 err = ct_handle_response(ct, msg);
824 err = ct_handle_request(ct, msg);
827 if (GEM_WARN_ON(err == -EPROTO)) {
828 DRM_ERROR("CT: corrupted message detected!\n");
829 ctb->desc->is_in_error = 1;
834 * When we're communicating with the GuC over CT, GuC uses events
835 * to notify us about new messages being posted on the RECV buffer.
837 static void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
839 struct intel_guc_ct *ct = &guc->ct;
841 ct_process_host_channel(ct);
845 * intel_guc_ct_init - Init CT communication
846 * @ct: pointer to CT struct
848 * Allocate memory required for communication via
851 * Return: 0 on success, a negative errno code on failure.
853 int intel_guc_ct_init(struct intel_guc_ct *ct)
855 struct intel_guc *guc = ct_to_guc(ct);
856 struct intel_guc_ct_channel *ctch = &ct->host_channel;
859 err = ctch_init(guc, ctch);
861 DRM_ERROR("CT: can't open channel %d; err=%d\n",
866 GEM_BUG_ON(!ctch->vma);
871 * intel_guc_ct_fini - Fini CT communication
872 * @ct: pointer to CT struct
874 * Deallocate memory required for communication via
877 void intel_guc_ct_fini(struct intel_guc_ct *ct)
879 struct intel_guc *guc = ct_to_guc(ct);
880 struct intel_guc_ct_channel *ctch = &ct->host_channel;
882 ctch_fini(guc, ctch);
886 * intel_guc_ct_enable - Enable buffer based command transport.
887 * @ct: pointer to CT struct
889 * Return: 0 on success, a negative errno code on failure.
891 int intel_guc_ct_enable(struct intel_guc_ct *ct)
893 struct intel_guc *guc = ct_to_guc(ct);
894 struct intel_guc_ct_channel *ctch = &ct->host_channel;
900 err = ctch_enable(guc, ctch);
904 /* Switch into cmd transport buffer based send() */
905 guc->send = intel_guc_send_ct;
906 guc->handler = intel_guc_to_host_event_handler_ct;
907 DRM_INFO("CT: %s\n", enableddisabled(true));
912 * intel_guc_ct_disable - Disable buffer based command transport.
913 * @ct: pointer to CT struct
915 void intel_guc_ct_disable(struct intel_guc_ct *ct)
917 struct intel_guc *guc = ct_to_guc(ct);
918 struct intel_guc_ct_channel *ctch = &ct->host_channel;
923 ctch_disable(guc, ctch);
926 guc->send = intel_guc_send_nop;
927 guc->handler = intel_guc_to_host_event_handler_nop;
928 DRM_INFO("CT: %s\n", enableddisabled(false));