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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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28 #include "intel_uncore.h"
29 #include "intel_guc_fw.h"
30 #include "intel_guc_fwif.h"
31 #include "intel_guc_ct.h"
32 #include "intel_guc_log.h"
33 #include "intel_guc_reg.h"
34 #include "intel_uc_fw.h"
35 #include "i915_utils.h"
38 struct guc_preempt_work {
39 struct work_struct work;
40 struct intel_engine_cs *engine;
44 * Top level structure of GuC. It handles firmware loading and manages client
45 * pool and doorbells. intel_guc owns a intel_guc_client to replace the legacy
46 * ExecList submission.
49 struct intel_uc_fw fw;
50 struct intel_guc_log log;
51 struct intel_guc_ct ct;
53 /* Log snapshot if GuC errors during load */
54 struct drm_i915_gem_object *load_err_log;
56 /* intel_guc_recv interrupt related state */
58 unsigned int msg_enabled_mask;
62 void (*reset)(struct drm_i915_private *i915);
63 void (*enable)(struct drm_i915_private *i915);
64 void (*disable)(struct drm_i915_private *i915);
67 struct i915_vma *ads_vma;
68 struct i915_vma *stage_desc_pool;
69 void *stage_desc_pool_vaddr;
71 struct i915_vma *shared_data;
72 void *shared_data_vaddr;
74 struct intel_guc_client *execbuf_client;
75 struct intel_guc_client *preempt_client;
77 struct guc_preempt_work preempt_work[I915_NUM_ENGINES];
78 struct workqueue_struct *preempt_wq;
80 DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
81 /* Cyclic counter mod pagesize */
84 /* GuC's FW specific registers used in MMIO send */
88 enum forcewake_domains fw_domains;
91 /* To serialize the intel_guc_send actions */
92 struct mutex send_mutex;
94 /* GuC's FW specific send function */
95 int (*send)(struct intel_guc *guc, const u32 *data, u32 len,
96 u32 *response_buf, u32 response_buf_size);
98 /* GuC's FW specific event handler function */
99 void (*handler)(struct intel_guc *guc);
101 /* GuC's FW specific notify function */
102 void (*notify)(struct intel_guc *guc);
106 inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
108 return guc->send(guc, action, len, NULL, 0);
112 intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len,
113 u32 *response_buf, u32 response_buf_size)
115 return guc->send(guc, action, len, response_buf, response_buf_size);
118 static inline void intel_guc_notify(struct intel_guc *guc)
123 static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
128 /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
129 #define GUC_GGTT_TOP 0xFEE00000
132 * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
133 * @guc: intel_guc structure.
134 * @vma: i915 graphics virtual memory area.
136 * GuC does not allow any gfx GGTT address that falls into range
137 * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
138 * Currently, in order to exclude [0, ggtt.pin_bias) address space from
139 * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
140 * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.
142 * Return: GGTT offset of the @vma.
144 static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
145 struct i915_vma *vma)
147 u32 offset = i915_ggtt_offset(vma);
149 GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
150 GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
155 void intel_guc_init_early(struct intel_guc *guc);
156 void intel_guc_init_send_regs(struct intel_guc *guc);
157 void intel_guc_init_params(struct intel_guc *guc);
158 int intel_guc_init_misc(struct intel_guc *guc);
159 int intel_guc_init(struct intel_guc *guc);
160 void intel_guc_fini(struct intel_guc *guc);
161 void intel_guc_fini_misc(struct intel_guc *guc);
162 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
163 u32 *response_buf, u32 response_buf_size);
164 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
165 u32 *response_buf, u32 response_buf_size);
166 void intel_guc_to_host_event_handler(struct intel_guc *guc);
167 void intel_guc_to_host_event_handler_nop(struct intel_guc *guc);
168 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
169 const u32 *payload, u32 len);
170 int intel_guc_sample_forcewake(struct intel_guc *guc);
171 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
172 int intel_guc_suspend(struct intel_guc *guc);
173 int intel_guc_resume(struct intel_guc *guc);
174 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
176 static inline bool intel_guc_is_loaded(struct intel_guc *guc)
178 return intel_uc_fw_is_loaded(&guc->fw);
181 static inline int intel_guc_sanitize(struct intel_guc *guc)
183 intel_uc_fw_sanitize(&guc->fw);
187 static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)
189 spin_lock_irq(&guc->irq_lock);
190 guc->msg_enabled_mask |= mask;
191 spin_unlock_irq(&guc->irq_lock);
194 static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)
196 spin_lock_irq(&guc->irq_lock);
197 guc->msg_enabled_mask &= ~mask;
198 spin_unlock_irq(&guc->irq_lock);
201 int intel_guc_reset_engine(struct intel_guc *guc,
202 struct intel_engine_cs *engine);