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11 * The above copyright notice and this permission notice (including the next
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28 #include "intel_uncore.h"
29 #include "intel_guc_fw.h"
30 #include "intel_guc_fwif.h"
31 #include "intel_guc_ct.h"
32 #include "intel_guc_log.h"
33 #include "intel_guc_reg.h"
34 #include "intel_uc_fw.h"
35 #include "i915_utils.h"
38 struct guc_preempt_work {
39 struct work_struct work;
40 struct intel_engine_cs *engine;
44 * Top level structure of GuC. It handles firmware loading and manages client
45 * pool and doorbells. intel_guc owns a intel_guc_client to replace the legacy
46 * ExecList submission.
49 struct intel_uc_fw fw;
50 struct intel_guc_log log;
51 struct intel_guc_ct ct;
53 /* Log snapshot if GuC errors during load */
54 struct drm_i915_gem_object *load_err_log;
56 /* intel_guc_recv interrupt related state */
58 bool interrupts_enabled;
59 unsigned int msg_enabled_mask;
61 struct i915_vma *ads_vma;
62 struct i915_vma *stage_desc_pool;
63 void *stage_desc_pool_vaddr;
65 struct i915_vma *shared_data;
66 void *shared_data_vaddr;
68 struct intel_guc_client *execbuf_client;
69 struct intel_guc_client *preempt_client;
71 struct guc_preempt_work preempt_work[I915_NUM_ENGINES];
72 struct workqueue_struct *preempt_wq;
74 DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
75 /* Cyclic counter mod pagesize */
78 /* GuC's FW specific registers used in MMIO send */
82 enum forcewake_domains fw_domains;
85 /* To serialize the intel_guc_send actions */
86 struct mutex send_mutex;
88 /* GuC's FW specific send function */
89 int (*send)(struct intel_guc *guc, const u32 *data, u32 len,
90 u32 *response_buf, u32 response_buf_size);
92 /* GuC's FW specific event handler function */
93 void (*handler)(struct intel_guc *guc);
95 /* GuC's FW specific notify function */
96 void (*notify)(struct intel_guc *guc);
100 inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
102 return guc->send(guc, action, len, NULL, 0);
106 intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len,
107 u32 *response_buf, u32 response_buf_size)
109 return guc->send(guc, action, len, response_buf, response_buf_size);
112 static inline void intel_guc_notify(struct intel_guc *guc)
117 static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
122 /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
123 #define GUC_GGTT_TOP 0xFEE00000
126 * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
127 * @guc: intel_guc structure.
128 * @vma: i915 graphics virtual memory area.
130 * GuC does not allow any gfx GGTT address that falls into range
131 * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
132 * Currently, in order to exclude [0, ggtt.pin_bias) address space from
133 * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
134 * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.
136 * Return: GGTT offset of the @vma.
138 static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
139 struct i915_vma *vma)
141 u32 offset = i915_ggtt_offset(vma);
143 GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
144 GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
149 void intel_guc_init_early(struct intel_guc *guc);
150 void intel_guc_init_send_regs(struct intel_guc *guc);
151 void intel_guc_init_params(struct intel_guc *guc);
152 int intel_guc_init_misc(struct intel_guc *guc);
153 int intel_guc_init(struct intel_guc *guc);
154 void intel_guc_fini(struct intel_guc *guc);
155 void intel_guc_fini_misc(struct intel_guc *guc);
156 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
157 u32 *response_buf, u32 response_buf_size);
158 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
159 u32 *response_buf, u32 response_buf_size);
160 void intel_guc_to_host_event_handler(struct intel_guc *guc);
161 void intel_guc_to_host_event_handler_nop(struct intel_guc *guc);
162 void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc);
163 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
164 const u32 *payload, u32 len);
165 int intel_guc_sample_forcewake(struct intel_guc *guc);
166 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
167 int intel_guc_suspend(struct intel_guc *guc);
168 int intel_guc_resume(struct intel_guc *guc);
169 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
170 u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
171 int intel_guc_reserve_ggtt_top(struct intel_guc *guc);
172 void intel_guc_release_ggtt_top(struct intel_guc *guc);
174 static inline bool intel_guc_is_loaded(struct intel_guc *guc)
176 return intel_uc_fw_is_loaded(&guc->fw);
179 static inline int intel_guc_sanitize(struct intel_guc *guc)
181 intel_uc_fw_sanitize(&guc->fw);
185 static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)
187 spin_lock_irq(&guc->irq_lock);
188 guc->msg_enabled_mask |= mask;
189 spin_unlock_irq(&guc->irq_lock);
192 static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)
194 spin_lock_irq(&guc->irq_lock);
195 guc->msg_enabled_mask &= ~mask;
196 spin_unlock_irq(&guc->irq_lock);
199 int intel_guc_reset_engine(struct intel_guc *guc,
200 struct intel_engine_cs *engine);