drivers/gpu/drm/i915/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include "intel_drv.h"
  42 #include "i915_drv.h"
  43
  44 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
  45 {
  46         return HAS_FBC(dev_priv);
  47 }
  48
  49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
  50 {
  51         return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8;
  52 }
  53
  54 static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
  55 {
  56         return INTEL_GEN(dev_priv) < 4;
  57 }
  58
  59 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  60 {
  61         return INTEL_GEN(dev_priv) <= 3;
  62 }
  63
  64 /*
  65  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  66  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  67  * origin so the x and y offsets can actually fit the registers. As a
  68  * consequence, the fence doesn't really start exactly at the display plane
  69  * address we program because it starts at the real start of the buffer, so we
  70  * have to take this into consideration here.
  71  */
  72 static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
  73 {
  74         return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;
  75 }
  76
  77 /*
  78  * For SKL+, the plane source size used by the hardware is based on the value we
  79  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  80  * we wrote to PIPESRC.
  81  */
  82 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
  83                                             int *width, int *height)
  84 {
  85         if (width)
  86                 *width = cache->plane.src_w;
  87         if (height)
  88                 *height = cache->plane.src_h;
  89 }
  90
  91 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
  92                                         struct intel_fbc_state_cache *cache)
  93 {
  94         int lines;
  95
  96         intel_fbc_get_plane_source_size(cache, NULL, &lines);
  97         if (INTEL_GEN(dev_priv) == 7)
  98                 lines = min(lines, 2048);
  99         else if (INTEL_GEN(dev_priv) >= 8)
 100                 lines = min(lines, 2560);
 101
 102         /* Hardware needs the full buffer stride, not just the active area. */
 103         return lines * cache->fb.stride;
 104 }
 105
 106 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
 107 {
 108         u32 fbc_ctl;
 109
 110         /* Disable compression */
 111         fbc_ctl = I915_READ(FBC_CONTROL);
 112         if ((fbc_ctl & FBC_CTL_EN) == 0)
 113                 return;
 114
 115         fbc_ctl &= ~FBC_CTL_EN;
 116         I915_WRITE(FBC_CONTROL, fbc_ctl);
 117
 118         /* Wait for compressing bit to clear */
 119         if (intel_wait_for_register(dev_priv,
 120                                     FBC_STATUS, FBC_STAT_COMPRESSING, 0,
 121                                     10)) {
 122                 DRM_DEBUG_KMS("FBC idle timed out\n");
 123                 return;
 124         }
 125 }
 126
 127 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 128 {
 129         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 130         int cfb_pitch;
 131         int i;
 132         u32 fbc_ctl;
 133
 134         /* Note: fbc.threshold == 1 for i8xx */
 135         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 136         if (params->fb.stride < cfb_pitch)
 137                 cfb_pitch = params->fb.stride;
 138
 139         /* FBC_CTL wants 32B or 64B units */
 140         if (IS_GEN2(dev_priv))
 141                 cfb_pitch = (cfb_pitch / 32) - 1;
 142         else
 143                 cfb_pitch = (cfb_pitch / 64) - 1;
 144
 145         /* Clear old tags */
 146         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 147                 I915_WRITE(FBC_TAG(i), 0);
 148
 149         if (IS_GEN4(dev_priv)) {
 150                 u32 fbc_ctl2;
 151
 152                 /* Set it up... */
 153                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 154                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane);
 155                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 156                 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
 157         }
 158
 159         /* enable it... */
 160         fbc_ctl = I915_READ(FBC_CONTROL);
 161         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 162         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 163         if (IS_I945GM(dev_priv))
 164                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 165         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 166         fbc_ctl |= params->vma->fence->id;
 167         I915_WRITE(FBC_CONTROL, fbc_ctl);
 168 }
 169
 170 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 171 {
 172         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 173 }
 174
 175 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 176 {
 177         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 178         u32 dpfc_ctl;
 179
 180         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
 181         if (params->fb.format->cpp[0] == 2)
 182                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 183         else
 184                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 185
 186         if (params->vma->fence) {
 187                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id;
 188                 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 189         } else {
 190                 I915_WRITE(DPFC_FENCE_YOFF, 0);
 191         }
 192
 193         /* enable it... */
 194         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 195 }
 196
 197 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 198 {
 199         u32 dpfc_ctl;
 200
 201         /* Disable compression */
 202         dpfc_ctl = I915_READ(DPFC_CONTROL);
 203         if (dpfc_ctl & DPFC_CTL_EN) {
 204                 dpfc_ctl &= ~DPFC_CTL_EN;
 205                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 206         }
 207 }
 208
 209 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 210 {
 211         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 212 }
 213
 214 /* This function forces a CFB recompression through the nuke operation. */
 215 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 216 {
 217         I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 218         POSTING_READ(MSG_FBC_REND_STATE);
 219 }
 220
 221 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 222 {
 223         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 224         u32 dpfc_ctl;
 225         int threshold = dev_priv->fbc.threshold;
 226
 227         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 228         if (params->fb.format->cpp[0] == 2)
 229                 threshold++;
 230
 231         switch (threshold) {
 232         case 4:
 233         case 3:
 234                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 235                 break;
 236         case 2:
 237                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 238                 break;
 239         case 1:
 240                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 241                 break;
 242         }
 243
 244         if (params->vma->fence) {
 245                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 246                 if (IS_GEN5(dev_priv))
 247                         dpfc_ctl |= params->vma->fence->id;
 248                 if (IS_GEN6(dev_priv)) {
 249                         I915_WRITE(SNB_DPFC_CTL_SA,
 250                                    SNB_CPU_FENCE_ENABLE |
 251                                    params->vma->fence->id);
 252                         I915_WRITE(DPFC_CPU_FENCE_OFFSET,
 253                                    params->crtc.fence_y_offset);
 254                 }
 255         } else {
 256                 if (IS_GEN6(dev_priv)) {
 257                         I915_WRITE(SNB_DPFC_CTL_SA, 0);
 258                         I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 259                 }
 260         }
 261
 262         I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 263         I915_WRITE(ILK_FBC_RT_BASE,
 264                    i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID);
 265         /* enable it... */
 266         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 267
 268         intel_fbc_recompress(dev_priv);
 269 }
 270
 271 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 272 {
 273         u32 dpfc_ctl;
 274
 275         /* Disable compression */
 276         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 277         if (dpfc_ctl & DPFC_CTL_EN) {
 278                 dpfc_ctl &= ~DPFC_CTL_EN;
 279                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 280         }
 281 }
 282
 283 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 284 {
 285         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 286 }
 287
 288 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 289 {
 290         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 291         u32 dpfc_ctl;
 292         int threshold = dev_priv->fbc.threshold;
 293
 294         /* Display WA #0529: skl, kbl, bxt. */
 295         if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) {
 296                 u32 val = I915_READ(CHICKEN_MISC_4);
 297
 298                 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
 299
 300                 if (i915_gem_object_get_tiling(params->vma->obj) !=
 301                     I915_TILING_X)
 302                         val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
 303
 304                 I915_WRITE(CHICKEN_MISC_4, val);
 305         }
 306
 307         dpfc_ctl = 0;
 308         if (IS_IVYBRIDGE(dev_priv))
 309                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 310
 311         if (params->fb.format->cpp[0] == 2)
 312                 threshold++;
 313
 314         switch (threshold) {
 315         case 4:
 316         case 3:
 317                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 318                 break;
 319         case 2:
 320                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 321                 break;
 322         case 1:
 323                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 324                 break;
 325         }
 326
 327         if (params->vma->fence) {
 328                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 329                 I915_WRITE(SNB_DPFC_CTL_SA,
 330                            SNB_CPU_FENCE_ENABLE |
 331                            params->vma->fence->id);
 332                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 333         } else {
 334                 I915_WRITE(SNB_DPFC_CTL_SA,0);
 335                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 336         }
 337
 338         if (dev_priv->fbc.false_color)
 339                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 340
 341         if (IS_IVYBRIDGE(dev_priv)) {
 342                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 343                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 344                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 345                            ILK_FBCQ_DIS);
 346         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 347                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 348                 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
 349                            I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
 350                            HSW_FBCQ_DIS);
 351         }
 352
 353         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 354
 355         intel_fbc_recompress(dev_priv);
 356 }
 357
 358 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 359 {
 360         if (INTEL_GEN(dev_priv) >= 5)
 361                 return ilk_fbc_is_active(dev_priv);
 362         else if (IS_GM45(dev_priv))
 363                 return g4x_fbc_is_active(dev_priv);
 364         else
 365                 return i8xx_fbc_is_active(dev_priv);
 366 }
 367
 368 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 369 {
 370         struct intel_fbc *fbc = &dev_priv->fbc;
 371
 372         fbc->active = true;
 373
 374         if (INTEL_GEN(dev_priv) >= 7)
 375                 gen7_fbc_activate(dev_priv);
 376         else if (INTEL_GEN(dev_priv) >= 5)
 377                 ilk_fbc_activate(dev_priv);
 378         else if (IS_GM45(dev_priv))
 379                 g4x_fbc_activate(dev_priv);
 380         else
 381                 i8xx_fbc_activate(dev_priv);
 382 }
 383
 384 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 385 {
 386         struct intel_fbc *fbc = &dev_priv->fbc;
 387
 388         fbc->active = false;
 389
 390         if (INTEL_GEN(dev_priv) >= 5)
 391                 ilk_fbc_deactivate(dev_priv);
 392         else if (IS_GM45(dev_priv))
 393                 g4x_fbc_deactivate(dev_priv);
 394         else
 395                 i8xx_fbc_deactivate(dev_priv);
 396 }
 397
 398 /**
 399  * intel_fbc_is_active - Is FBC active?
 400  * @dev_priv: i915 device instance
 401  *
 402  * This function is used to verify the current state of FBC.
 403  *
 404  * FIXME: This should be tracked in the plane config eventually
 405  * instead of queried at runtime for most callers.
 406  */
 407 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 408 {
 409         return dev_priv->fbc.active;
 410 }
 411
 412 static void intel_fbc_work_fn(struct work_struct *__work)
 413 {
 414         struct drm_i915_private *dev_priv =
 415                 container_of(__work, struct drm_i915_private, fbc.work.work);
 416         struct intel_fbc *fbc = &dev_priv->fbc;
 417         struct intel_fbc_work *work = &fbc->work;
 418         struct intel_crtc *crtc = fbc->crtc;
 419         struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe];
 420
 421         if (drm_crtc_vblank_get(&crtc->base)) {
 422                 /* CRTC is now off, leave FBC deactivated */
 423                 mutex_lock(&fbc->lock);
 424                 work->scheduled = false;
 425                 mutex_unlock(&fbc->lock);
 426                 return;
 427         }
 428
 429 retry:
 430         /* Delay the actual enabling to let pageflipping cease and the
 431          * display to settle before starting the compression. Note that
 432          * this delay also serves a second purpose: it allows for a
 433          * vblank to pass after disabling the FBC before we attempt
 434          * to modify the control registers.
 435          *
 436          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 437          *
 438          * It is also worth mentioning that since work->scheduled_vblank can be
 439          * updated multiple times by the other threads, hitting the timeout is
 440          * not an error condition. We'll just end up hitting the "goto retry"
 441          * case below.
 442          */
 443         wait_event_timeout(vblank->queue,
 444                 drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank,
 445                 msecs_to_jiffies(50));
 446
 447         mutex_lock(&fbc->lock);
 448
 449         /* Were we cancelled? */
 450         if (!work->scheduled)
 451                 goto out;
 452
 453         /* Were we delayed again while this function was sleeping? */
 454         if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) {
 455                 mutex_unlock(&fbc->lock);
 456                 goto retry;
 457         }
 458
 459         intel_fbc_hw_activate(dev_priv);
 460
 461         work->scheduled = false;
 462
 463 out:
 464         mutex_unlock(&fbc->lock);
 465         drm_crtc_vblank_put(&crtc->base);
 466 }
 467
 468 static void intel_fbc_schedule_activation(struct intel_crtc *crtc)
 469 {
 470         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 471         struct intel_fbc *fbc = &dev_priv->fbc;
 472         struct intel_fbc_work *work = &fbc->work;
 473
 474         WARN_ON(!mutex_is_locked(&fbc->lock));
 475         if (WARN_ON(!fbc->enabled))
 476                 return;
 477
 478         if (drm_crtc_vblank_get(&crtc->base)) {
 479                 DRM_ERROR("vblank not available for FBC on pipe %c\n",
 480                           pipe_name(crtc->pipe));
 481                 return;
 482         }
 483
 484         /* It is useless to call intel_fbc_cancel_work() or cancel_work() in
 485          * this function since we're not releasing fbc.lock, so it won't have an
 486          * opportunity to grab it to discover that it was cancelled. So we just
 487          * update the expected jiffy count. */
 488         work->scheduled = true;
 489         work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base);
 490         drm_crtc_vblank_put(&crtc->base);
 491
 492         schedule_work(&work->work);
 493 }
 494
 495 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv)
 496 {
 497         struct intel_fbc *fbc = &dev_priv->fbc;
 498
 499         WARN_ON(!mutex_is_locked(&fbc->lock));
 500
 501         /* Calling cancel_work() here won't help due to the fact that the work
 502          * function grabs fbc->lock. Just set scheduled to false so the work
 503          * function can know it was cancelled. */
 504         fbc->work.scheduled = false;
 505
 506         if (fbc->active)
 507                 intel_fbc_hw_deactivate(dev_priv);
 508 }
 509
 510 static bool multiple_pipes_ok(struct intel_crtc *crtc,
 511                               struct intel_plane_state *plane_state)
 512 {
 513         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 514         struct intel_fbc *fbc = &dev_priv->fbc;
 515         enum pipe pipe = crtc->pipe;
 516
 517         /* Don't even bother tracking anything we don't need. */
 518         if (!no_fbc_on_multiple_pipes(dev_priv))
 519                 return true;
 520
 521         if (plane_state->base.visible)
 522                 fbc->visible_pipes_mask |= (1 << pipe);
 523         else
 524                 fbc->visible_pipes_mask &= ~(1 << pipe);
 525
 526         return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
 527 }
 528
 529 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 530                                       struct drm_mm_node *node,
 531                                       int size,
 532                                       int fb_cpp)
 533 {
 534         int compression_threshold = 1;
 535         int ret;
 536         u64 end;
 537
 538         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 539          * reserved range size, so it always assumes the maximum (8mb) is used.
 540          * If we enable FBC using a CFB on that memory range we'll get FIFO
 541          * underruns, even if that range is not reserved by the BIOS. */
 542         if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
 543                 end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
 544         else
 545                 end = U64_MAX;
 546
 547         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 548          * code changes, this code needs to change as well.
 549          *
 550          * The enable_fbc code will attempt to use one of our 2 compression
 551          * thresholds, therefore, in that case, we only have 1 resort.
 552          */
 553
 554         /* Try to over-allocate to reduce reallocations and fragmentation. */
 555         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 556                                                    4096, 0, end);
 557         if (ret == 0)
 558                 return compression_threshold;
 559
 560 again:
 561         /* HW's ability to limit the CFB is 1:4 */
 562         if (compression_threshold > 4 ||
 563             (fb_cpp == 2 && compression_threshold == 2))
 564                 return 0;
 565
 566         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 567                                                    4096, 0, end);
 568         if (ret && INTEL_GEN(dev_priv) <= 4) {
 569                 return 0;
 570         } else if (ret) {
 571                 compression_threshold <<= 1;
 572                 goto again;
 573         } else {
 574                 return compression_threshold;
 575         }
 576 }
 577
 578 static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 579 {
 580         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 581         struct intel_fbc *fbc = &dev_priv->fbc;
 582         struct drm_mm_node *uninitialized_var(compressed_llb);
 583         int size, fb_cpp, ret;
 584
 585         WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
 586
 587         size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
 588         fb_cpp = fbc->state_cache.fb.format->cpp[0];
 589
 590         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 591                                          size, fb_cpp);
 592         if (!ret)
 593                 goto err_llb;
 594         else if (ret > 1) {
 595                 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 596
 597         }
 598
 599         fbc->threshold = ret;
 600
 601         if (INTEL_GEN(dev_priv) >= 5)
 602                 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
 603         else if (IS_GM45(dev_priv)) {
 604                 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
 605         } else {
 606                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 607                 if (!compressed_llb)
 608                         goto err_fb;
 609
 610                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 611                                                   4096, 4096);
 612                 if (ret)
 613                         goto err_fb;
 614
 615                 fbc->compressed_llb = compressed_llb;
 616
 617                 GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
 618                                              fbc->compressed_fb.start,
 619                                              U32_MAX));
 620                 GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
 621                                              fbc->compressed_llb->start,
 622                                              U32_MAX));
 623                 I915_WRITE(FBC_CFB_BASE,
 624                            dev_priv->dsm.start + fbc->compressed_fb.start);
 625                 I915_WRITE(FBC_LL_BASE,
 626                            dev_priv->dsm.start + compressed_llb->start);
 627         }
 628
 629         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 630                       fbc->compressed_fb.size, fbc->threshold);
 631
 632         return 0;
 633
 634 err_fb:
 635         kfree(compressed_llb);
 636         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 637 err_llb:
 638         if (drm_mm_initialized(&dev_priv->mm.stolen))
 639                 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 640         return -ENOSPC;
 641 }
 642
 643 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 644 {
 645         struct intel_fbc *fbc = &dev_priv->fbc;
 646
 647         if (drm_mm_node_allocated(&fbc->compressed_fb))
 648                 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 649
 650         if (fbc->compressed_llb) {
 651                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 652                 kfree(fbc->compressed_llb);
 653         }
 654 }
 655
 656 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 657 {
 658         struct intel_fbc *fbc = &dev_priv->fbc;
 659
 660         if (!fbc_supported(dev_priv))
 661                 return;
 662
 663         mutex_lock(&fbc->lock);
 664         __intel_fbc_cleanup_cfb(dev_priv);
 665         mutex_unlock(&fbc->lock);
 666 }
 667
 668 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 669                             unsigned int stride)
 670 {
 671         /* These should have been caught earlier. */
 672         WARN_ON(stride < 512);
 673         WARN_ON((stride & (64 - 1)) != 0);
 674
 675         /* Below are the additional FBC restrictions. */
 676
 677         if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
 678                 return stride == 4096 || stride == 8192;
 679
 680         if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
 681                 return false;
 682
 683         if (stride > 16384)
 684                 return false;
 685
 686         return true;
 687 }
 688
 689 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 690                                   uint32_t pixel_format)
 691 {
 692         switch (pixel_format) {
 693         case DRM_FORMAT_XRGB8888:
 694         case DRM_FORMAT_XBGR8888:
 695                 return true;
 696         case DRM_FORMAT_XRGB1555:
 697         case DRM_FORMAT_RGB565:
 698                 /* 16bpp not supported on gen2 */
 699                 if (IS_GEN2(dev_priv))
 700                         return false;
 701                 /* WaFbcOnly1to1Ratio:ctg */
 702                 if (IS_G4X(dev_priv))
 703                         return false;
 704                 return true;
 705         default:
 706                 return false;
 707         }
 708 }
 709
 710 /*
 711  * For some reason, the hardware tracking starts looking at whatever we
 712  * programmed as the display plane base address register. It does not look at
 713  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 714  * variables instead of just looking at the pipe/plane size.
 715  */
 716 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 717 {
 718         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 719         struct intel_fbc *fbc = &dev_priv->fbc;
 720         unsigned int effective_w, effective_h, max_w, max_h;
 721
 722         if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
 723                 max_w = 4096;
 724                 max_h = 4096;
 725         } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 726                 max_w = 4096;
 727                 max_h = 2048;
 728         } else {
 729                 max_w = 2048;
 730                 max_h = 1536;
 731         }
 732
 733         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 734                                         &effective_h);
 735         effective_w += fbc->state_cache.plane.adjusted_x;
 736         effective_h += fbc->state_cache.plane.adjusted_y;
 737
 738         return effective_w <= max_w && effective_h <= max_h;
 739 }
 740
 741 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 742                                          struct intel_crtc_state *crtc_state,
 743                                          struct intel_plane_state *plane_state)
 744 {
 745         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 746         struct intel_fbc *fbc = &dev_priv->fbc;
 747         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 748         struct drm_framebuffer *fb = plane_state->base.fb;
 749
 750         cache->vma = NULL;
 751
 752         cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
 753         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 754                 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 755
 756         cache->plane.rotation = plane_state->base.rotation;
 757         /*
 758          * Src coordinates are already rotated by 270 degrees for
 759          * the 90/270 degree plane rotation cases (to match the
 760          * GTT mapping), hence no need to account for rotation here.
 761          */
 762         cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
 763         cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
 764         cache->plane.visible = plane_state->base.visible;
 765         cache->plane.adjusted_x = plane_state->main.x;
 766         cache->plane.adjusted_y = plane_state->main.y;
 767         cache->plane.y = plane_state->base.src.y1 >> 16;
 768
 769         if (!cache->plane.visible)
 770                 return;
 771
 772         cache->fb.format = fb->format;
 773         cache->fb.stride = fb->pitches[0];
 774
 775         cache->vma = plane_state->vma;
 776 }
 777
 778 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 779 {
 780         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 781         struct intel_fbc *fbc = &dev_priv->fbc;
 782         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 783
 784         /* We don't need to use a state cache here since this information is
 785          * global for all CRTC.
 786          */
 787         if (fbc->underrun_detected) {
 788                 fbc->no_fbc_reason = "underrun detected";
 789                 return false;
 790         }
 791
 792         if (!cache->vma) {
 793                 fbc->no_fbc_reason = "primary plane not visible";
 794                 return false;
 795         }
 796
 797         if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) ||
 798             (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) {
 799                 fbc->no_fbc_reason = "incompatible mode";
 800                 return false;
 801         }
 802
 803         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 804                 fbc->no_fbc_reason = "mode too large for compression";
 805                 return false;
 806         }
 807
 808         /* The use of a CPU fence is mandatory in order to detect writes
 809          * by the CPU to the scanout and trigger updates to the FBC.
 810          *
 811          * Note that is possible for a tiled surface to be unmappable (and
 812          * so have no fence associated with it) due to aperture constaints
 813          * at the time of pinning.
 814          */
 815         if (!cache->vma->fence) {
 816                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 817                 return false;
 818         }
 819         if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
 820             cache->plane.rotation != DRM_MODE_ROTATE_0) {
 821                 fbc->no_fbc_reason = "rotation unsupported";
 822                 return false;
 823         }
 824
 825         if (!stride_is_valid(dev_priv, cache->fb.stride)) {
 826                 fbc->no_fbc_reason = "framebuffer stride not supported";
 827                 return false;
 828         }
 829
 830         if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
 831                 fbc->no_fbc_reason = "pixel format is invalid";
 832                 return false;
 833         }
 834
 835         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 836         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 837             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
 838                 fbc->no_fbc_reason = "pixel rate is too big";
 839                 return false;
 840         }
 841
 842         /* It is possible for the required CFB size change without a
 843          * crtc->disable + crtc->enable since it is possible to change the
 844          * stride without triggering a full modeset. Since we try to
 845          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 846          * if this happens, but if we exceed the current CFB size we'll have to
 847          * disable FBC. Notice that it would be possible to disable FBC, wait
 848          * for a frame, free the stolen node, then try to reenable FBC in case
 849          * we didn't get any invalidate/deactivate calls, but this would require
 850          * a lot of tracking just for a specific case. If we conclude it's an
 851          * important case, we can implement it later. */
 852         if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 853             fbc->compressed_fb.size * fbc->threshold) {
 854                 fbc->no_fbc_reason = "CFB requirements changed";
 855                 return false;
 856         }
 857
 858         return true;
 859 }
 860
 861 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
 862 {
 863         struct intel_fbc *fbc = &dev_priv->fbc;
 864
 865         if (intel_vgpu_active(dev_priv)) {
 866                 fbc->no_fbc_reason = "VGPU is active";
 867                 return false;
 868         }
 869
 870         if (!i915_modparams.enable_fbc) {
 871                 fbc->no_fbc_reason = "disabled per module param or by default";
 872                 return false;
 873         }
 874
 875         if (fbc->underrun_detected) {
 876                 fbc->no_fbc_reason = "underrun detected";
 877                 return false;
 878         }
 879
 880         return true;
 881 }
 882
 883 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 884                                      struct intel_fbc_reg_params *params)
 885 {
 886         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 887         struct intel_fbc *fbc = &dev_priv->fbc;
 888         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 889
 890         /* Since all our fields are integer types, use memset here so the
 891          * comparison function can rely on memcmp because the padding will be
 892          * zero. */
 893         memset(params, 0, sizeof(*params));
 894
 895         params->vma = cache->vma;
 896
 897         params->crtc.pipe = crtc->pipe;
 898         params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
 899         params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);
 900
 901         params->fb.format = cache->fb.format;
 902         params->fb.stride = cache->fb.stride;
 903
 904         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 905
 906         if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
 907                 params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
 908                                                 32 * fbc->threshold) * 8;
 909 }
 910
 911 static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
 912                                        struct intel_fbc_reg_params *params2)
 913 {
 914         /* We can use this since intel_fbc_get_reg_params() does a memset. */
 915         return memcmp(params1, params2, sizeof(*params1)) == 0;
 916 }
 917
 918 void intel_fbc_pre_update(struct intel_crtc *crtc,
 919                           struct intel_crtc_state *crtc_state,
 920                           struct intel_plane_state *plane_state)
 921 {
 922         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 923         struct intel_fbc *fbc = &dev_priv->fbc;
 924
 925         if (!fbc_supported(dev_priv))
 926                 return;
 927
 928         mutex_lock(&fbc->lock);
 929
 930         if (!multiple_pipes_ok(crtc, plane_state)) {
 931                 fbc->no_fbc_reason = "more than one pipe active";
 932                 goto deactivate;
 933         }
 934
 935         if (!fbc->enabled || fbc->crtc != crtc)
 936                 goto unlock;
 937
 938         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 939
 940 deactivate:
 941         intel_fbc_deactivate(dev_priv);
 942 unlock:
 943         mutex_unlock(&fbc->lock);
 944 }
 945
 946 static void __intel_fbc_post_update(struct intel_crtc *crtc)
 947 {
 948         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 949         struct intel_fbc *fbc = &dev_priv->fbc;
 950         struct intel_fbc_reg_params old_params;
 951
 952         WARN_ON(!mutex_is_locked(&fbc->lock));
 953
 954         if (!fbc->enabled || fbc->crtc != crtc)
 955                 return;
 956
 957         if (!intel_fbc_can_activate(crtc)) {
 958                 WARN_ON(fbc->active);
 959                 return;
 960         }
 961
 962         old_params = fbc->params;
 963         intel_fbc_get_reg_params(crtc, &fbc->params);
 964
 965         /* If the scanout has not changed, don't modify the FBC settings.
 966          * Note that we make the fundamental assumption that the fb->obj
 967          * cannot be unpinned (and have its GTT offset and fence revoked)
 968          * without first being decoupled from the scanout and FBC disabled.
 969          */
 970         if (fbc->active &&
 971             intel_fbc_reg_params_equal(&old_params, &fbc->params))
 972                 return;
 973
 974         intel_fbc_deactivate(dev_priv);
 975         intel_fbc_schedule_activation(crtc);
 976         fbc->no_fbc_reason = "FBC enabled (active or scheduled)";
 977 }
 978
 979 void intel_fbc_post_update(struct intel_crtc *crtc)
 980 {
 981         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 982         struct intel_fbc *fbc = &dev_priv->fbc;
 983
 984         if (!fbc_supported(dev_priv))
 985                 return;
 986
 987         mutex_lock(&fbc->lock);
 988         __intel_fbc_post_update(crtc);
 989         mutex_unlock(&fbc->lock);
 990 }
 991
 992 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
 993 {
 994         if (fbc->enabled)
 995                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
 996         else
 997                 return fbc->possible_framebuffer_bits;
 998 }
 999
1000 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1001                           unsigned int frontbuffer_bits,
1002                           enum fb_op_origin origin)
1003 {
1004         struct intel_fbc *fbc = &dev_priv->fbc;
1005
1006         if (!fbc_supported(dev_priv))
1007                 return;
1008
1009         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1010                 return;
1011
1012         mutex_lock(&fbc->lock);
1013
1014         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1015
1016         if (fbc->enabled && fbc->busy_bits)
1017                 intel_fbc_deactivate(dev_priv);
1018
1019         mutex_unlock(&fbc->lock);
1020 }
1021
1022 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1023                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
1024 {
1025         struct intel_fbc *fbc = &dev_priv->fbc;
1026
1027         if (!fbc_supported(dev_priv))
1028                 return;
1029
1030         mutex_lock(&fbc->lock);
1031
1032         fbc->busy_bits &= ~frontbuffer_bits;
1033
1034         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1035                 goto out;
1036
1037         if (!fbc->busy_bits && fbc->enabled &&
1038             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1039                 if (fbc->active)
1040                         intel_fbc_recompress(dev_priv);
1041                 else
1042                         __intel_fbc_post_update(fbc->crtc);
1043         }
1044
1045 out:
1046         mutex_unlock(&fbc->lock);
1047 }
1048
1049 /**
1050  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1051  * @dev_priv: i915 device instance
1052  * @state: the atomic state structure
1053  *
1054  * This function looks at the proposed state for CRTCs and planes, then chooses
1055  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1056  * true.
1057  *
1058  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1059  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1060  */
1061 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1062                            struct intel_atomic_state *state)
1063 {
1064         struct intel_fbc *fbc = &dev_priv->fbc;
1065         struct intel_plane *plane;
1066         struct intel_plane_state *plane_state;
1067         bool crtc_chosen = false;
1068         int i;
1069
1070         mutex_lock(&fbc->lock);
1071
1072         /* Does this atomic commit involve the CRTC currently tied to FBC? */
1073         if (fbc->crtc &&
1074             !intel_atomic_get_new_crtc_state(state, fbc->crtc))
1075                 goto out;
1076
1077         if (!intel_fbc_can_enable(dev_priv))
1078                 goto out;
1079
1080         /* Simply choose the first CRTC that is compatible and has a visible
1081          * plane. We could go for fancier schemes such as checking the plane
1082          * size, but this would just affect the few platforms that don't tie FBC
1083          * to pipe or plane A. */
1084         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1085                 struct intel_crtc_state *crtc_state;
1086                 struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
1087
1088                 if (!plane_state->base.visible)
1089                         continue;
1090
1091                 if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
1092                         continue;
1093
1094                 if (fbc_on_plane_a_only(dev_priv) && plane->i9xx_plane != PLANE_A)
1095                         continue;
1096
1097                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1098
1099                 crtc_state->enable_fbc = true;
1100                 crtc_chosen = true;
1101                 break;
1102         }
1103
1104         if (!crtc_chosen)
1105                 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1106
1107 out:
1108         mutex_unlock(&fbc->lock);
1109 }
1110
1111 /**
1112  * intel_fbc_enable: tries to enable FBC on the CRTC
1113  * @crtc: the CRTC
1114  * @crtc_state: corresponding &drm_crtc_state for @crtc
1115  * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1116  *
1117  * This function checks if the given CRTC was chosen for FBC, then enables it if
1118  * possible. Notice that it doesn't activate FBC. It is valid to call
1119  * intel_fbc_enable multiple times for the same pipe without an
1120  * intel_fbc_disable in the middle, as long as it is deactivated.
1121  */
1122 void intel_fbc_enable(struct intel_crtc *crtc,
1123                       struct intel_crtc_state *crtc_state,
1124                       struct intel_plane_state *plane_state)
1125 {
1126         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1127         struct intel_fbc *fbc = &dev_priv->fbc;
1128
1129         if (!fbc_supported(dev_priv))
1130                 return;
1131
1132         mutex_lock(&fbc->lock);
1133
1134         if (fbc->enabled) {
1135                 WARN_ON(fbc->crtc == NULL);
1136                 if (fbc->crtc == crtc) {
1137                         WARN_ON(!crtc_state->enable_fbc);
1138                         WARN_ON(fbc->active);
1139                 }
1140                 goto out;
1141         }
1142
1143         if (!crtc_state->enable_fbc)
1144                 goto out;
1145
1146         WARN_ON(fbc->active);
1147         WARN_ON(fbc->crtc != NULL);
1148
1149         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1150         if (intel_fbc_alloc_cfb(crtc)) {
1151                 fbc->no_fbc_reason = "not enough stolen memory";
1152                 goto out;
1153         }
1154
1155         DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1156         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1157
1158         fbc->enabled = true;
1159         fbc->crtc = crtc;
1160 out:
1161         mutex_unlock(&fbc->lock);
1162 }
1163
1164 /**
1165  * __intel_fbc_disable - disable FBC
1166  * @dev_priv: i915 device instance
1167  *
1168  * This is the low level function that actually disables FBC. Callers should
1169  * grab the FBC lock.
1170  */
1171 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1172 {
1173         struct intel_fbc *fbc = &dev_priv->fbc;
1174         struct intel_crtc *crtc = fbc->crtc;
1175
1176         WARN_ON(!mutex_is_locked(&fbc->lock));
1177         WARN_ON(!fbc->enabled);
1178         WARN_ON(fbc->active);
1179         WARN_ON(crtc->active);
1180
1181         DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1182
1183         __intel_fbc_cleanup_cfb(dev_priv);
1184
1185         fbc->enabled = false;
1186         fbc->crtc = NULL;
1187 }
1188
1189 /**
1190  * intel_fbc_disable - disable FBC if it's associated with crtc
1191  * @crtc: the CRTC
1192  *
1193  * This function disables FBC if it's associated with the provided CRTC.
1194  */
1195 void intel_fbc_disable(struct intel_crtc *crtc)
1196 {
1197         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1198         struct intel_fbc *fbc = &dev_priv->fbc;
1199
1200         if (!fbc_supported(dev_priv))
1201                 return;
1202
1203         mutex_lock(&fbc->lock);
1204         if (fbc->crtc == crtc)
1205                 __intel_fbc_disable(dev_priv);
1206         mutex_unlock(&fbc->lock);
1207
1208         cancel_work_sync(&fbc->work.work);
1209 }
1210
1211 /**
1212  * intel_fbc_global_disable - globally disable FBC
1213  * @dev_priv: i915 device instance
1214  *
1215  * This function disables FBC regardless of which CRTC is associated with it.
1216  */
1217 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1218 {
1219         struct intel_fbc *fbc = &dev_priv->fbc;
1220
1221         if (!fbc_supported(dev_priv))
1222                 return;
1223
1224         mutex_lock(&fbc->lock);
1225         if (fbc->enabled)
1226                 __intel_fbc_disable(dev_priv);
1227         mutex_unlock(&fbc->lock);
1228
1229         cancel_work_sync(&fbc->work.work);
1230 }
1231
1232 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1233 {
1234         struct drm_i915_private *dev_priv =
1235                 container_of(work, struct drm_i915_private, fbc.underrun_work);
1236         struct intel_fbc *fbc = &dev_priv->fbc;
1237
1238         mutex_lock(&fbc->lock);
1239
1240         /* Maybe we were scheduled twice. */
1241         if (fbc->underrun_detected || !fbc->enabled)
1242                 goto out;
1243
1244         DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
1245         fbc->underrun_detected = true;
1246
1247         intel_fbc_deactivate(dev_priv);
1248 out:
1249         mutex_unlock(&fbc->lock);
1250 }
1251
1252 /**
1253  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1254  * @dev_priv: i915 device instance
1255  *
1256  * Without FBC, most underruns are harmless and don't really cause too many
1257  * problems, except for an annoying message on dmesg. With FBC, underruns can
1258  * become black screens or even worse, especially when paired with bad
1259  * watermarks. So in order for us to be on the safe side, completely disable FBC
1260  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1261  * already suggests that watermarks may be bad, so try to be as safe as
1262  * possible.
1263  *
1264  * This function is called from the IRQ handler.
1265  */
1266 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1267 {
1268         struct intel_fbc *fbc = &dev_priv->fbc;
1269
1270         if (!fbc_supported(dev_priv))
1271                 return;
1272
1273         /* There's no guarantee that underrun_detected won't be set to true
1274          * right after this check and before the work is scheduled, but that's
1275          * not a problem since we'll check it again under the work function
1276          * while FBC is locked. This check here is just to prevent us from
1277          * unnecessarily scheduling the work, and it relies on the fact that we
1278          * never switch underrun_detect back to false after it's true. */
1279         if (READ_ONCE(fbc->underrun_detected))
1280                 return;
1281
1282         schedule_work(&fbc->underrun_work);
1283 }
1284
1285 /**
1286  * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1287  * @dev_priv: i915 device instance
1288  *
1289  * The FBC code needs to track CRTC visibility since the older platforms can't
1290  * have FBC enabled while multiple pipes are used. This function does the
1291  * initial setup at driver load to make sure FBC is matching the real hardware.
1292  */
1293 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1294 {
1295         struct intel_crtc *crtc;
1296
1297         /* Don't even bother tracking anything if we don't need. */
1298         if (!no_fbc_on_multiple_pipes(dev_priv))
1299                 return;
1300
1301         for_each_intel_crtc(&dev_priv->drm, crtc)
1302                 if (intel_crtc_active(crtc) &&
1303                     crtc->base.primary->state->visible)
1304                         dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1305 }
1306
1307 /*
1308  * The DDX driver changes its behavior depending on the value it reads from
1309  * i915.enable_fbc, so sanitize it by translating the default value into either
1310  * 0 or 1 in order to allow it to know what's going on.
1311  *
1312  * Notice that this is done at driver initialization and we still allow user
1313  * space to change the value during runtime without sanitizing it again. IGT
1314  * relies on being able to change i915.enable_fbc at runtime.
1315  */
1316 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1317 {
1318         if (i915_modparams.enable_fbc >= 0)
1319                 return !!i915_modparams.enable_fbc;
1320
1321         if (!HAS_FBC(dev_priv))
1322                 return 0;
1323
1324         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1325                 return 1;
1326
1327         return 0;
1328 }
1329
1330 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1331 {
1332         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1333         if (intel_vtd_active() &&
1334             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1335                 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1336                 return true;
1337         }
1338
1339         return false;
1340 }
1341
1342 /**
1343  * intel_fbc_init - Initialize FBC
1344  * @dev_priv: the i915 device
1345  *
1346  * This function might be called during PM init process.
1347  */
1348 void intel_fbc_init(struct drm_i915_private *dev_priv)
1349 {
1350         struct intel_fbc *fbc = &dev_priv->fbc;
1351         enum pipe pipe;
1352
1353         INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
1354         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1355         mutex_init(&fbc->lock);
1356         fbc->enabled = false;
1357         fbc->active = false;
1358         fbc->work.scheduled = false;
1359
1360         if (need_fbc_vtd_wa(dev_priv))
1361                 mkwrite_device_info(dev_priv)->has_fbc = false;
1362
1363         i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1364         DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
1365                       i915_modparams.enable_fbc);
1366
1367         if (!HAS_FBC(dev_priv)) {
1368                 fbc->no_fbc_reason = "unsupported by this chipset";
1369                 return;
1370         }
1371
1372         for_each_pipe(dev_priv, pipe) {
1373                 fbc->possible_framebuffer_bits |=
1374                                 INTEL_FRONTBUFFER_PRIMARY(pipe);
1375
1376                 if (fbc_on_pipe_a_only(dev_priv))
1377                         break;
1378         }
1379
1380         /* This value was pulled out of someone's hat */
1381         if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
1382                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1383
1384         /* We still don't have any sort of hardware state readout for FBC, so
1385          * deactivate it in case the BIOS activated it to make sure software
1386          * matches the hardware state. */
1387         if (intel_fbc_hw_is_active(dev_priv))
1388                 intel_fbc_hw_deactivate(dev_priv);
1389 }