drivers/gpu/drm/i915/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include <drm/drm_fourcc.h>
  42
  43 #include "intel_drv.h"
  44 #include "i915_drv.h"
  45
  46 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
  47 {
  48         return HAS_FBC(dev_priv);
  49 }
  50
  51 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  52 {
  53         return INTEL_GEN(dev_priv) <= 3;
  54 }
  55
  56 /*
  57  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  58  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  59  * origin so the x and y offsets can actually fit the registers. As a
  60  * consequence, the fence doesn't really start exactly at the display plane
  61  * address we program because it starts at the real start of the buffer, so we
  62  * have to take this into consideration here.
  63  */
  64 static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
  65 {
  66         return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;
  67 }
  68
  69 /*
  70  * For SKL+, the plane source size used by the hardware is based on the value we
  71  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  72  * we wrote to PIPESRC.
  73  */
  74 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
  75                                             int *width, int *height)
  76 {
  77         if (width)
  78                 *width = cache->plane.src_w;
  79         if (height)
  80                 *height = cache->plane.src_h;
  81 }
  82
  83 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
  84                                         struct intel_fbc_state_cache *cache)
  85 {
  86         int lines;
  87
  88         intel_fbc_get_plane_source_size(cache, NULL, &lines);
  89         if (IS_GEN(dev_priv, 7))
  90                 lines = min(lines, 2048);
  91         else if (INTEL_GEN(dev_priv) >= 8)
  92                 lines = min(lines, 2560);
  93
  94         /* Hardware needs the full buffer stride, not just the active area. */
  95         return lines * cache->fb.stride;
  96 }
  97
  98 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
  99 {
 100         u32 fbc_ctl;
 101
 102         /* Disable compression */
 103         fbc_ctl = I915_READ(FBC_CONTROL);
 104         if ((fbc_ctl & FBC_CTL_EN) == 0)
 105                 return;
 106
 107         fbc_ctl &= ~FBC_CTL_EN;
 108         I915_WRITE(FBC_CONTROL, fbc_ctl);
 109
 110         /* Wait for compressing bit to clear */
 111         if (intel_wait_for_register(dev_priv,
 112                                     FBC_STATUS, FBC_STAT_COMPRESSING, 0,
 113                                     10)) {
 114                 DRM_DEBUG_KMS("FBC idle timed out\n");
 115                 return;
 116         }
 117 }
 118
 119 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 120 {
 121         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 122         int cfb_pitch;
 123         int i;
 124         u32 fbc_ctl;
 125
 126         /* Note: fbc.threshold == 1 for i8xx */
 127         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 128         if (params->fb.stride < cfb_pitch)
 129                 cfb_pitch = params->fb.stride;
 130
 131         /* FBC_CTL wants 32B or 64B units */
 132         if (IS_GEN(dev_priv, 2))
 133                 cfb_pitch = (cfb_pitch / 32) - 1;
 134         else
 135                 cfb_pitch = (cfb_pitch / 64) - 1;
 136
 137         /* Clear old tags */
 138         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 139                 I915_WRITE(FBC_TAG(i), 0);
 140
 141         if (IS_GEN(dev_priv, 4)) {
 142                 u32 fbc_ctl2;
 143
 144                 /* Set it up... */
 145                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 146                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane);
 147                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 148                 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
 149         }
 150
 151         /* enable it... */
 152         fbc_ctl = I915_READ(FBC_CONTROL);
 153         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 154         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 155         if (IS_I945GM(dev_priv))
 156                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 157         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 158         fbc_ctl |= params->vma->fence->id;
 159         I915_WRITE(FBC_CONTROL, fbc_ctl);
 160 }
 161
 162 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 163 {
 164         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 165 }
 166
 167 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 168 {
 169         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 170         u32 dpfc_ctl;
 171
 172         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
 173         if (params->fb.format->cpp[0] == 2)
 174                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 175         else
 176                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 177
 178         if (params->flags & PLANE_HAS_FENCE) {
 179                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id;
 180                 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 181         } else {
 182                 I915_WRITE(DPFC_FENCE_YOFF, 0);
 183         }
 184
 185         /* enable it... */
 186         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 187 }
 188
 189 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 190 {
 191         u32 dpfc_ctl;
 192
 193         /* Disable compression */
 194         dpfc_ctl = I915_READ(DPFC_CONTROL);
 195         if (dpfc_ctl & DPFC_CTL_EN) {
 196                 dpfc_ctl &= ~DPFC_CTL_EN;
 197                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 198         }
 199 }
 200
 201 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 202 {
 203         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 204 }
 205
 206 /* This function forces a CFB recompression through the nuke operation. */
 207 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 208 {
 209         I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 210         POSTING_READ(MSG_FBC_REND_STATE);
 211 }
 212
 213 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 214 {
 215         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 216         u32 dpfc_ctl;
 217         int threshold = dev_priv->fbc.threshold;
 218
 219         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 220         if (params->fb.format->cpp[0] == 2)
 221                 threshold++;
 222
 223         switch (threshold) {
 224         case 4:
 225         case 3:
 226                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 227                 break;
 228         case 2:
 229                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 230                 break;
 231         case 1:
 232                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 233                 break;
 234         }
 235
 236         if (params->flags & PLANE_HAS_FENCE) {
 237                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 238                 if (IS_GEN(dev_priv, 5))
 239                         dpfc_ctl |= params->vma->fence->id;
 240                 if (IS_GEN(dev_priv, 6)) {
 241                         I915_WRITE(SNB_DPFC_CTL_SA,
 242                                    SNB_CPU_FENCE_ENABLE |
 243                                    params->vma->fence->id);
 244                         I915_WRITE(DPFC_CPU_FENCE_OFFSET,
 245                                    params->crtc.fence_y_offset);
 246                 }
 247         } else {
 248                 if (IS_GEN(dev_priv, 6)) {
 249                         I915_WRITE(SNB_DPFC_CTL_SA, 0);
 250                         I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 251                 }
 252         }
 253
 254         I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 255         I915_WRITE(ILK_FBC_RT_BASE,
 256                    i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID);
 257         /* enable it... */
 258         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 259
 260         intel_fbc_recompress(dev_priv);
 261 }
 262
 263 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 264 {
 265         u32 dpfc_ctl;
 266
 267         /* Disable compression */
 268         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 269         if (dpfc_ctl & DPFC_CTL_EN) {
 270                 dpfc_ctl &= ~DPFC_CTL_EN;
 271                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 272         }
 273 }
 274
 275 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 276 {
 277         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 278 }
 279
 280 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 281 {
 282         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 283         u32 dpfc_ctl;
 284         int threshold = dev_priv->fbc.threshold;
 285
 286         /* Display WA #0529: skl, kbl, bxt. */
 287         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) {
 288                 u32 val = I915_READ(CHICKEN_MISC_4);
 289
 290                 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
 291
 292                 if (i915_gem_object_get_tiling(params->vma->obj) !=
 293                     I915_TILING_X)
 294                         val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
 295
 296                 I915_WRITE(CHICKEN_MISC_4, val);
 297         }
 298
 299         dpfc_ctl = 0;
 300         if (IS_IVYBRIDGE(dev_priv))
 301                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 302
 303         if (params->fb.format->cpp[0] == 2)
 304                 threshold++;
 305
 306         switch (threshold) {
 307         case 4:
 308         case 3:
 309                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 310                 break;
 311         case 2:
 312                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 313                 break;
 314         case 1:
 315                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 316                 break;
 317         }
 318
 319         if (params->flags & PLANE_HAS_FENCE) {
 320                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 321                 I915_WRITE(SNB_DPFC_CTL_SA,
 322                            SNB_CPU_FENCE_ENABLE |
 323                            params->vma->fence->id);
 324                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 325         } else {
 326                 I915_WRITE(SNB_DPFC_CTL_SA,0);
 327                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 328         }
 329
 330         if (dev_priv->fbc.false_color)
 331                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 332
 333         if (IS_IVYBRIDGE(dev_priv)) {
 334                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 335                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 336                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 337                            ILK_FBCQ_DIS);
 338         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 339                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 340                 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
 341                            I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
 342                            HSW_FBCQ_DIS);
 343         }
 344
 345         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 346
 347         intel_fbc_recompress(dev_priv);
 348 }
 349
 350 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 351 {
 352         if (INTEL_GEN(dev_priv) >= 5)
 353                 return ilk_fbc_is_active(dev_priv);
 354         else if (IS_GM45(dev_priv))
 355                 return g4x_fbc_is_active(dev_priv);
 356         else
 357                 return i8xx_fbc_is_active(dev_priv);
 358 }
 359
 360 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 361 {
 362         struct intel_fbc *fbc = &dev_priv->fbc;
 363
 364         fbc->active = true;
 365
 366         if (INTEL_GEN(dev_priv) >= 7)
 367                 gen7_fbc_activate(dev_priv);
 368         else if (INTEL_GEN(dev_priv) >= 5)
 369                 ilk_fbc_activate(dev_priv);
 370         else if (IS_GM45(dev_priv))
 371                 g4x_fbc_activate(dev_priv);
 372         else
 373                 i8xx_fbc_activate(dev_priv);
 374 }
 375
 376 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 377 {
 378         struct intel_fbc *fbc = &dev_priv->fbc;
 379
 380         fbc->active = false;
 381
 382         if (INTEL_GEN(dev_priv) >= 5)
 383                 ilk_fbc_deactivate(dev_priv);
 384         else if (IS_GM45(dev_priv))
 385                 g4x_fbc_deactivate(dev_priv);
 386         else
 387                 i8xx_fbc_deactivate(dev_priv);
 388 }
 389
 390 /**
 391  * intel_fbc_is_active - Is FBC active?
 392  * @dev_priv: i915 device instance
 393  *
 394  * This function is used to verify the current state of FBC.
 395  *
 396  * FIXME: This should be tracked in the plane config eventually
 397  * instead of queried at runtime for most callers.
 398  */
 399 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 400 {
 401         return dev_priv->fbc.active;
 402 }
 403
 404 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
 405                                  const char *reason)
 406 {
 407         struct intel_fbc *fbc = &dev_priv->fbc;
 408
 409         WARN_ON(!mutex_is_locked(&fbc->lock));
 410
 411         if (fbc->active)
 412                 intel_fbc_hw_deactivate(dev_priv);
 413
 414         fbc->no_fbc_reason = reason;
 415 }
 416
 417 static bool multiple_pipes_ok(struct intel_crtc *crtc,
 418                               struct intel_plane_state *plane_state)
 419 {
 420         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 421         struct intel_fbc *fbc = &dev_priv->fbc;
 422         enum pipe pipe = crtc->pipe;
 423
 424         /* Don't even bother tracking anything we don't need. */
 425         if (!no_fbc_on_multiple_pipes(dev_priv))
 426                 return true;
 427
 428         if (plane_state->base.visible)
 429                 fbc->visible_pipes_mask |= (1 << pipe);
 430         else
 431                 fbc->visible_pipes_mask &= ~(1 << pipe);
 432
 433         return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
 434 }
 435
 436 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 437                                       struct drm_mm_node *node,
 438                                       int size,
 439                                       int fb_cpp)
 440 {
 441         int compression_threshold = 1;
 442         int ret;
 443         u64 end;
 444
 445         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 446          * reserved range size, so it always assumes the maximum (8mb) is used.
 447          * If we enable FBC using a CFB on that memory range we'll get FIFO
 448          * underruns, even if that range is not reserved by the BIOS. */
 449         if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
 450                 end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
 451         else
 452                 end = U64_MAX;
 453
 454         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 455          * code changes, this code needs to change as well.
 456          *
 457          * The enable_fbc code will attempt to use one of our 2 compression
 458          * thresholds, therefore, in that case, we only have 1 resort.
 459          */
 460
 461         /* Try to over-allocate to reduce reallocations and fragmentation. */
 462         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 463                                                    4096, 0, end);
 464         if (ret == 0)
 465                 return compression_threshold;
 466
 467 again:
 468         /* HW's ability to limit the CFB is 1:4 */
 469         if (compression_threshold > 4 ||
 470             (fb_cpp == 2 && compression_threshold == 2))
 471                 return 0;
 472
 473         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 474                                                    4096, 0, end);
 475         if (ret && INTEL_GEN(dev_priv) <= 4) {
 476                 return 0;
 477         } else if (ret) {
 478                 compression_threshold <<= 1;
 479                 goto again;
 480         } else {
 481                 return compression_threshold;
 482         }
 483 }
 484
 485 static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 486 {
 487         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 488         struct intel_fbc *fbc = &dev_priv->fbc;
 489         struct drm_mm_node *uninitialized_var(compressed_llb);
 490         int size, fb_cpp, ret;
 491
 492         WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
 493
 494         size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
 495         fb_cpp = fbc->state_cache.fb.format->cpp[0];
 496
 497         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 498                                          size, fb_cpp);
 499         if (!ret)
 500                 goto err_llb;
 501         else if (ret > 1) {
 502                 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 503
 504         }
 505
 506         fbc->threshold = ret;
 507
 508         if (INTEL_GEN(dev_priv) >= 5)
 509                 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
 510         else if (IS_GM45(dev_priv)) {
 511                 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
 512         } else {
 513                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 514                 if (!compressed_llb)
 515                         goto err_fb;
 516
 517                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 518                                                   4096, 4096);
 519                 if (ret)
 520                         goto err_fb;
 521
 522                 fbc->compressed_llb = compressed_llb;
 523
 524                 GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
 525                                              fbc->compressed_fb.start,
 526                                              U32_MAX));
 527                 GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
 528                                              fbc->compressed_llb->start,
 529                                              U32_MAX));
 530                 I915_WRITE(FBC_CFB_BASE,
 531                            dev_priv->dsm.start + fbc->compressed_fb.start);
 532                 I915_WRITE(FBC_LL_BASE,
 533                            dev_priv->dsm.start + compressed_llb->start);
 534         }
 535
 536         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 537                       fbc->compressed_fb.size, fbc->threshold);
 538
 539         return 0;
 540
 541 err_fb:
 542         kfree(compressed_llb);
 543         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 544 err_llb:
 545         if (drm_mm_initialized(&dev_priv->mm.stolen))
 546                 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 547         return -ENOSPC;
 548 }
 549
 550 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 551 {
 552         struct intel_fbc *fbc = &dev_priv->fbc;
 553
 554         if (drm_mm_node_allocated(&fbc->compressed_fb))
 555                 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 556
 557         if (fbc->compressed_llb) {
 558                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 559                 kfree(fbc->compressed_llb);
 560         }
 561 }
 562
 563 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 564 {
 565         struct intel_fbc *fbc = &dev_priv->fbc;
 566
 567         if (!fbc_supported(dev_priv))
 568                 return;
 569
 570         mutex_lock(&fbc->lock);
 571         __intel_fbc_cleanup_cfb(dev_priv);
 572         mutex_unlock(&fbc->lock);
 573 }
 574
 575 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 576                             unsigned int stride)
 577 {
 578         /* This should have been caught earlier. */
 579         if (WARN_ON_ONCE((stride & (64 - 1)) != 0))
 580                 return false;
 581
 582         /* Below are the additional FBC restrictions. */
 583         if (stride < 512)
 584                 return false;
 585
 586         if (IS_GEN(dev_priv, 2) || IS_GEN(dev_priv, 3))
 587                 return stride == 4096 || stride == 8192;
 588
 589         if (IS_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048)
 590                 return false;
 591
 592         if (stride > 16384)
 593                 return false;
 594
 595         return true;
 596 }
 597
 598 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 599                                   u32 pixel_format)
 600 {
 601         switch (pixel_format) {
 602         case DRM_FORMAT_XRGB8888:
 603         case DRM_FORMAT_XBGR8888:
 604                 return true;
 605         case DRM_FORMAT_XRGB1555:
 606         case DRM_FORMAT_RGB565:
 607                 /* 16bpp not supported on gen2 */
 608                 if (IS_GEN(dev_priv, 2))
 609                         return false;
 610                 /* WaFbcOnly1to1Ratio:ctg */
 611                 if (IS_G4X(dev_priv))
 612                         return false;
 613                 return true;
 614         default:
 615                 return false;
 616         }
 617 }
 618
 619 /*
 620  * For some reason, the hardware tracking starts looking at whatever we
 621  * programmed as the display plane base address register. It does not look at
 622  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 623  * variables instead of just looking at the pipe/plane size.
 624  */
 625 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 626 {
 627         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 628         struct intel_fbc *fbc = &dev_priv->fbc;
 629         unsigned int effective_w, effective_h, max_w, max_h;
 630
 631         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 632                 max_w = 5120;
 633                 max_h = 4096;
 634         } else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
 635                 max_w = 4096;
 636                 max_h = 4096;
 637         } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 638                 max_w = 4096;
 639                 max_h = 2048;
 640         } else {
 641                 max_w = 2048;
 642                 max_h = 1536;
 643         }
 644
 645         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 646                                         &effective_h);
 647         effective_w += fbc->state_cache.plane.adjusted_x;
 648         effective_h += fbc->state_cache.plane.adjusted_y;
 649
 650         return effective_w <= max_w && effective_h <= max_h;
 651 }
 652
 653 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 654                                          struct intel_crtc_state *crtc_state,
 655                                          struct intel_plane_state *plane_state)
 656 {
 657         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 658         struct intel_fbc *fbc = &dev_priv->fbc;
 659         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 660         struct drm_framebuffer *fb = plane_state->base.fb;
 661
 662         cache->vma = NULL;
 663         cache->flags = 0;
 664
 665         cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
 666         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 667                 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 668
 669         cache->plane.rotation = plane_state->base.rotation;
 670         /*
 671          * Src coordinates are already rotated by 270 degrees for
 672          * the 90/270 degree plane rotation cases (to match the
 673          * GTT mapping), hence no need to account for rotation here.
 674          */
 675         cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
 676         cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
 677         cache->plane.visible = plane_state->base.visible;
 678         cache->plane.adjusted_x = plane_state->color_plane[0].x;
 679         cache->plane.adjusted_y = plane_state->color_plane[0].y;
 680         cache->plane.y = plane_state->base.src.y1 >> 16;
 681
 682         cache->plane.pixel_blend_mode = plane_state->base.pixel_blend_mode;
 683
 684         if (!cache->plane.visible)
 685                 return;
 686
 687         cache->fb.format = fb->format;
 688         cache->fb.stride = fb->pitches[0];
 689
 690         cache->vma = plane_state->vma;
 691         cache->flags = plane_state->flags;
 692         if (WARN_ON(cache->flags & PLANE_HAS_FENCE && !cache->vma->fence))
 693                 cache->flags &= ~PLANE_HAS_FENCE;
 694 }
 695
 696 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 697 {
 698         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 699         struct intel_fbc *fbc = &dev_priv->fbc;
 700         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 701
 702         /* We don't need to use a state cache here since this information is
 703          * global for all CRTC.
 704          */
 705         if (fbc->underrun_detected) {
 706                 fbc->no_fbc_reason = "underrun detected";
 707                 return false;
 708         }
 709
 710         if (!cache->vma) {
 711                 fbc->no_fbc_reason = "primary plane not visible";
 712                 return false;
 713         }
 714
 715         if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
 716                 fbc->no_fbc_reason = "incompatible mode";
 717                 return false;
 718         }
 719
 720         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 721                 fbc->no_fbc_reason = "mode too large for compression";
 722                 return false;
 723         }
 724
 725         /* The use of a CPU fence is mandatory in order to detect writes
 726          * by the CPU to the scanout and trigger updates to the FBC.
 727          *
 728          * Note that is possible for a tiled surface to be unmappable (and
 729          * so have no fence associated with it) due to aperture constaints
 730          * at the time of pinning.
 731          *
 732          * FIXME with 90/270 degree rotation we should use the fence on
 733          * the normal GTT view (the rotated view doesn't even have a
 734          * fence). Would need changes to the FBC fence Y offset as well.
 735          * For now this will effecively disable FBC with 90/270 degree
 736          * rotation.
 737          */
 738         if (!(cache->flags & PLANE_HAS_FENCE)) {
 739                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 740                 return false;
 741         }
 742         if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
 743             cache->plane.rotation != DRM_MODE_ROTATE_0) {
 744                 fbc->no_fbc_reason = "rotation unsupported";
 745                 return false;
 746         }
 747
 748         if (!stride_is_valid(dev_priv, cache->fb.stride)) {
 749                 fbc->no_fbc_reason = "framebuffer stride not supported";
 750                 return false;
 751         }
 752
 753         if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
 754                 fbc->no_fbc_reason = "pixel format is invalid";
 755                 return false;
 756         }
 757
 758         if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
 759             cache->fb.format->has_alpha) {
 760                 fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
 761                 return false;
 762         }
 763
 764         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 765         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 766             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
 767                 fbc->no_fbc_reason = "pixel rate is too big";
 768                 return false;
 769         }
 770
 771         /* It is possible for the required CFB size change without a
 772          * crtc->disable + crtc->enable since it is possible to change the
 773          * stride without triggering a full modeset. Since we try to
 774          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 775          * if this happens, but if we exceed the current CFB size we'll have to
 776          * disable FBC. Notice that it would be possible to disable FBC, wait
 777          * for a frame, free the stolen node, then try to reenable FBC in case
 778          * we didn't get any invalidate/deactivate calls, but this would require
 779          * a lot of tracking just for a specific case. If we conclude it's an
 780          * important case, we can implement it later. */
 781         if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 782             fbc->compressed_fb.size * fbc->threshold) {
 783                 fbc->no_fbc_reason = "CFB requirements changed";
 784                 return false;
 785         }
 786
 787         /*
 788          * Work around a problem on GEN9+ HW, where enabling FBC on a plane
 789          * having a Y offset that isn't divisible by 4 causes FIFO underrun
 790          * and screen flicker.
 791          */
 792         if (IS_GEN_RANGE(dev_priv, 9, 10) &&
 793             (fbc->state_cache.plane.adjusted_y & 3)) {
 794                 fbc->no_fbc_reason = "plane Y offset is misaligned";
 795                 return false;
 796         }
 797
 798         return true;
 799 }
 800
 801 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
 802 {
 803         struct intel_fbc *fbc = &dev_priv->fbc;
 804
 805         if (intel_vgpu_active(dev_priv)) {
 806                 fbc->no_fbc_reason = "VGPU is active";
 807                 return false;
 808         }
 809
 810         if (!i915_modparams.enable_fbc) {
 811                 fbc->no_fbc_reason = "disabled per module param or by default";
 812                 return false;
 813         }
 814
 815         if (fbc->underrun_detected) {
 816                 fbc->no_fbc_reason = "underrun detected";
 817                 return false;
 818         }
 819
 820         return true;
 821 }
 822
 823 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 824                                      struct intel_fbc_reg_params *params)
 825 {
 826         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 827         struct intel_fbc *fbc = &dev_priv->fbc;
 828         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 829
 830         /* Since all our fields are integer types, use memset here so the
 831          * comparison function can rely on memcmp because the padding will be
 832          * zero. */
 833         memset(params, 0, sizeof(*params));
 834
 835         params->vma = cache->vma;
 836         params->flags = cache->flags;
 837
 838         params->crtc.pipe = crtc->pipe;
 839         params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
 840         params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);
 841
 842         params->fb.format = cache->fb.format;
 843         params->fb.stride = cache->fb.stride;
 844
 845         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 846
 847         if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))
 848                 params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
 849                                                 32 * fbc->threshold) * 8;
 850 }
 851
 852 void intel_fbc_pre_update(struct intel_crtc *crtc,
 853                           struct intel_crtc_state *crtc_state,
 854                           struct intel_plane_state *plane_state)
 855 {
 856         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 857         struct intel_fbc *fbc = &dev_priv->fbc;
 858         const char *reason = "update pending";
 859
 860         if (!fbc_supported(dev_priv))
 861                 return;
 862
 863         mutex_lock(&fbc->lock);
 864
 865         if (!multiple_pipes_ok(crtc, plane_state)) {
 866                 reason = "more than one pipe active";
 867                 goto deactivate;
 868         }
 869
 870         if (!fbc->enabled || fbc->crtc != crtc)
 871                 goto unlock;
 872
 873         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 874         fbc->flip_pending = true;
 875
 876 deactivate:
 877         intel_fbc_deactivate(dev_priv, reason);
 878 unlock:
 879         mutex_unlock(&fbc->lock);
 880 }
 881
 882 /**
 883  * __intel_fbc_disable - disable FBC
 884  * @dev_priv: i915 device instance
 885  *
 886  * This is the low level function that actually disables FBC. Callers should
 887  * grab the FBC lock.
 888  */
 889 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
 890 {
 891         struct intel_fbc *fbc = &dev_priv->fbc;
 892         struct intel_crtc *crtc = fbc->crtc;
 893
 894         WARN_ON(!mutex_is_locked(&fbc->lock));
 895         WARN_ON(!fbc->enabled);
 896         WARN_ON(fbc->active);
 897
 898         DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
 899
 900         __intel_fbc_cleanup_cfb(dev_priv);
 901
 902         fbc->enabled = false;
 903         fbc->crtc = NULL;
 904 }
 905
 906 static void __intel_fbc_post_update(struct intel_crtc *crtc)
 907 {
 908         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 909         struct intel_fbc *fbc = &dev_priv->fbc;
 910
 911         WARN_ON(!mutex_is_locked(&fbc->lock));
 912
 913         if (!fbc->enabled || fbc->crtc != crtc)
 914                 return;
 915
 916         fbc->flip_pending = false;
 917         WARN_ON(fbc->active);
 918
 919         if (!i915_modparams.enable_fbc) {
 920                 intel_fbc_deactivate(dev_priv, "disabled at runtime per module param");
 921                 __intel_fbc_disable(dev_priv);
 922
 923                 return;
 924         }
 925
 926         intel_fbc_get_reg_params(crtc, &fbc->params);
 927
 928         if (!intel_fbc_can_activate(crtc))
 929                 return;
 930
 931         if (!fbc->busy_bits) {
 932                 intel_fbc_deactivate(dev_priv, "FBC enabled (active or scheduled)");
 933                 intel_fbc_hw_activate(dev_priv);
 934         } else
 935                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
 936 }
 937
 938 void intel_fbc_post_update(struct intel_crtc *crtc)
 939 {
 940         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 941         struct intel_fbc *fbc = &dev_priv->fbc;
 942
 943         if (!fbc_supported(dev_priv))
 944                 return;
 945
 946         mutex_lock(&fbc->lock);
 947         __intel_fbc_post_update(crtc);
 948         mutex_unlock(&fbc->lock);
 949 }
 950
 951 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
 952 {
 953         if (fbc->enabled)
 954                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
 955         else
 956                 return fbc->possible_framebuffer_bits;
 957 }
 958
 959 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
 960                           unsigned int frontbuffer_bits,
 961                           enum fb_op_origin origin)
 962 {
 963         struct intel_fbc *fbc = &dev_priv->fbc;
 964
 965         if (!fbc_supported(dev_priv))
 966                 return;
 967
 968         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
 969                 return;
 970
 971         mutex_lock(&fbc->lock);
 972
 973         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
 974
 975         if (fbc->enabled && fbc->busy_bits)
 976                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
 977
 978         mutex_unlock(&fbc->lock);
 979 }
 980
 981 void intel_fbc_flush(struct drm_i915_private *dev_priv,
 982                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
 983 {
 984         struct intel_fbc *fbc = &dev_priv->fbc;
 985
 986         if (!fbc_supported(dev_priv))
 987                 return;
 988
 989         mutex_lock(&fbc->lock);
 990
 991         fbc->busy_bits &= ~frontbuffer_bits;
 992
 993         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
 994                 goto out;
 995
 996         if (!fbc->busy_bits && fbc->enabled &&
 997             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
 998                 if (fbc->active)
 999                         intel_fbc_recompress(dev_priv);
1000                 else if (!fbc->flip_pending)
1001                         __intel_fbc_post_update(fbc->crtc);
1002         }
1003
1004 out:
1005         mutex_unlock(&fbc->lock);
1006 }
1007
1008 /**
1009  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1010  * @dev_priv: i915 device instance
1011  * @state: the atomic state structure
1012  *
1013  * This function looks at the proposed state for CRTCs and planes, then chooses
1014  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1015  * true.
1016  *
1017  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1018  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1019  */
1020 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1021                            struct intel_atomic_state *state)
1022 {
1023         struct intel_fbc *fbc = &dev_priv->fbc;
1024         struct intel_plane *plane;
1025         struct intel_plane_state *plane_state;
1026         bool crtc_chosen = false;
1027         int i;
1028
1029         mutex_lock(&fbc->lock);
1030
1031         /* Does this atomic commit involve the CRTC currently tied to FBC? */
1032         if (fbc->crtc &&
1033             !intel_atomic_get_new_crtc_state(state, fbc->crtc))
1034                 goto out;
1035
1036         if (!intel_fbc_can_enable(dev_priv))
1037                 goto out;
1038
1039         /* Simply choose the first CRTC that is compatible and has a visible
1040          * plane. We could go for fancier schemes such as checking the plane
1041          * size, but this would just affect the few platforms that don't tie FBC
1042          * to pipe or plane A. */
1043         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1044                 struct intel_crtc_state *crtc_state;
1045                 struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
1046
1047                 if (!plane->has_fbc)
1048                         continue;
1049
1050                 if (!plane_state->base.visible)
1051                         continue;
1052
1053                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1054
1055                 crtc_state->enable_fbc = true;
1056                 crtc_chosen = true;
1057                 break;
1058         }
1059
1060         if (!crtc_chosen)
1061                 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1062
1063 out:
1064         mutex_unlock(&fbc->lock);
1065 }
1066
1067 /**
1068  * intel_fbc_enable: tries to enable FBC on the CRTC
1069  * @crtc: the CRTC
1070  * @crtc_state: corresponding &drm_crtc_state for @crtc
1071  * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1072  *
1073  * This function checks if the given CRTC was chosen for FBC, then enables it if
1074  * possible. Notice that it doesn't activate FBC. It is valid to call
1075  * intel_fbc_enable multiple times for the same pipe without an
1076  * intel_fbc_disable in the middle, as long as it is deactivated.
1077  */
1078 void intel_fbc_enable(struct intel_crtc *crtc,
1079                       struct intel_crtc_state *crtc_state,
1080                       struct intel_plane_state *plane_state)
1081 {
1082         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1083         struct intel_fbc *fbc = &dev_priv->fbc;
1084
1085         if (!fbc_supported(dev_priv))
1086                 return;
1087
1088         mutex_lock(&fbc->lock);
1089
1090         if (fbc->enabled) {
1091                 WARN_ON(fbc->crtc == NULL);
1092                 if (fbc->crtc == crtc) {
1093                         WARN_ON(!crtc_state->enable_fbc);
1094                         WARN_ON(fbc->active);
1095                 }
1096                 goto out;
1097         }
1098
1099         if (!crtc_state->enable_fbc)
1100                 goto out;
1101
1102         WARN_ON(fbc->active);
1103         WARN_ON(fbc->crtc != NULL);
1104
1105         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1106         if (intel_fbc_alloc_cfb(crtc)) {
1107                 fbc->no_fbc_reason = "not enough stolen memory";
1108                 goto out;
1109         }
1110
1111         DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1112         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1113
1114         fbc->enabled = true;
1115         fbc->crtc = crtc;
1116 out:
1117         mutex_unlock(&fbc->lock);
1118 }
1119
1120 /**
1121  * intel_fbc_disable - disable FBC if it's associated with crtc
1122  * @crtc: the CRTC
1123  *
1124  * This function disables FBC if it's associated with the provided CRTC.
1125  */
1126 void intel_fbc_disable(struct intel_crtc *crtc)
1127 {
1128         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1129         struct intel_fbc *fbc = &dev_priv->fbc;
1130
1131         if (!fbc_supported(dev_priv))
1132                 return;
1133
1134         mutex_lock(&fbc->lock);
1135         if (fbc->crtc == crtc)
1136                 __intel_fbc_disable(dev_priv);
1137         mutex_unlock(&fbc->lock);
1138 }
1139
1140 /**
1141  * intel_fbc_global_disable - globally disable FBC
1142  * @dev_priv: i915 device instance
1143  *
1144  * This function disables FBC regardless of which CRTC is associated with it.
1145  */
1146 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1147 {
1148         struct intel_fbc *fbc = &dev_priv->fbc;
1149
1150         if (!fbc_supported(dev_priv))
1151                 return;
1152
1153         mutex_lock(&fbc->lock);
1154         if (fbc->enabled) {
1155                 WARN_ON(fbc->crtc->active);
1156                 __intel_fbc_disable(dev_priv);
1157         }
1158         mutex_unlock(&fbc->lock);
1159 }
1160
1161 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1162 {
1163         struct drm_i915_private *dev_priv =
1164                 container_of(work, struct drm_i915_private, fbc.underrun_work);
1165         struct intel_fbc *fbc = &dev_priv->fbc;
1166
1167         mutex_lock(&fbc->lock);
1168
1169         /* Maybe we were scheduled twice. */
1170         if (fbc->underrun_detected || !fbc->enabled)
1171                 goto out;
1172
1173         DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
1174         fbc->underrun_detected = true;
1175
1176         intel_fbc_deactivate(dev_priv, "FIFO underrun");
1177 out:
1178         mutex_unlock(&fbc->lock);
1179 }
1180
1181 /*
1182  * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1183  * @dev_priv: i915 device instance
1184  *
1185  * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1186  * want to re-enable FBC after an underrun to increase test coverage.
1187  */
1188 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
1189 {
1190         int ret;
1191
1192         cancel_work_sync(&dev_priv->fbc.underrun_work);
1193
1194         ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
1195         if (ret)
1196                 return ret;
1197
1198         if (dev_priv->fbc.underrun_detected) {
1199                 DRM_DEBUG_KMS("Re-allowing FBC after fifo underrun\n");
1200                 dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
1201         }
1202
1203         dev_priv->fbc.underrun_detected = false;
1204         mutex_unlock(&dev_priv->fbc.lock);
1205
1206         return 0;
1207 }
1208
1209 /**
1210  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1211  * @dev_priv: i915 device instance
1212  *
1213  * Without FBC, most underruns are harmless and don't really cause too many
1214  * problems, except for an annoying message on dmesg. With FBC, underruns can
1215  * become black screens or even worse, especially when paired with bad
1216  * watermarks. So in order for us to be on the safe side, completely disable FBC
1217  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1218  * already suggests that watermarks may be bad, so try to be as safe as
1219  * possible.
1220  *
1221  * This function is called from the IRQ handler.
1222  */
1223 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1224 {
1225         struct intel_fbc *fbc = &dev_priv->fbc;
1226
1227         if (!fbc_supported(dev_priv))
1228                 return;
1229
1230         /* There's no guarantee that underrun_detected won't be set to true
1231          * right after this check and before the work is scheduled, but that's
1232          * not a problem since we'll check it again under the work function
1233          * while FBC is locked. This check here is just to prevent us from
1234          * unnecessarily scheduling the work, and it relies on the fact that we
1235          * never switch underrun_detect back to false after it's true. */
1236         if (READ_ONCE(fbc->underrun_detected))
1237                 return;
1238
1239         schedule_work(&fbc->underrun_work);
1240 }
1241
1242 /**
1243  * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1244  * @dev_priv: i915 device instance
1245  *
1246  * The FBC code needs to track CRTC visibility since the older platforms can't
1247  * have FBC enabled while multiple pipes are used. This function does the
1248  * initial setup at driver load to make sure FBC is matching the real hardware.
1249  */
1250 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1251 {
1252         struct intel_crtc *crtc;
1253
1254         /* Don't even bother tracking anything if we don't need. */
1255         if (!no_fbc_on_multiple_pipes(dev_priv))
1256                 return;
1257
1258         for_each_intel_crtc(&dev_priv->drm, crtc)
1259                 if (intel_crtc_active(crtc) &&
1260                     crtc->base.primary->state->visible)
1261                         dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1262 }
1263
1264 /*
1265  * The DDX driver changes its behavior depending on the value it reads from
1266  * i915.enable_fbc, so sanitize it by translating the default value into either
1267  * 0 or 1 in order to allow it to know what's going on.
1268  *
1269  * Notice that this is done at driver initialization and we still allow user
1270  * space to change the value during runtime without sanitizing it again. IGT
1271  * relies on being able to change i915.enable_fbc at runtime.
1272  */
1273 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1274 {
1275         if (i915_modparams.enable_fbc >= 0)
1276                 return !!i915_modparams.enable_fbc;
1277
1278         if (!HAS_FBC(dev_priv))
1279                 return 0;
1280
1281         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1282                 return 1;
1283
1284         return 0;
1285 }
1286
1287 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1288 {
1289         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1290         if (intel_vtd_active() &&
1291             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1292                 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1293                 return true;
1294         }
1295
1296         return false;
1297 }
1298
1299 /**
1300  * intel_fbc_init - Initialize FBC
1301  * @dev_priv: the i915 device
1302  *
1303  * This function might be called during PM init process.
1304  */
1305 void intel_fbc_init(struct drm_i915_private *dev_priv)
1306 {
1307         struct intel_fbc *fbc = &dev_priv->fbc;
1308
1309         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1310         mutex_init(&fbc->lock);
1311         fbc->enabled = false;
1312         fbc->active = false;
1313
1314         if (need_fbc_vtd_wa(dev_priv))
1315                 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1316
1317         i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1318         DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
1319                       i915_modparams.enable_fbc);
1320
1321         if (!HAS_FBC(dev_priv)) {
1322                 fbc->no_fbc_reason = "unsupported by this chipset";
1323                 return;
1324         }
1325
1326         /* This value was pulled out of someone's hat */
1327         if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
1328                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1329
1330         /* We still don't have any sort of hardware state readout for FBC, so
1331          * deactivate it in case the BIOS activated it to make sure software
1332          * matches the hardware state. */
1333         if (intel_fbc_hw_is_active(dev_priv))
1334                 intel_fbc_hw_deactivate(dev_priv);
1335 }