2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_mipi_dsi.h>
30 #include "intel_drv.h"
32 /* Dual Link support */
33 #define DSI_DUAL_LINK_NONE 0
34 #define DSI_DUAL_LINK_FRONT_BACK 1
35 #define DSI_DUAL_LINK_PIXEL_ALT 2
37 struct intel_dsi_host;
40 struct intel_encoder base;
42 struct intel_dsi_host *dsi_hosts[I915_MAX_PORTS];
44 /* GPIO Desc for CRC based Panel control */
45 struct gpio_desc *gpio_panel;
47 struct intel_connector *attached_connector;
49 /* bit mask of ports being driven */
52 /* if true, use HS mode, otherwise LP */
58 /* Video mode or command mode */
61 /* number of DSI lanes */
62 unsigned int lane_count;
65 * video mode pixel format
67 * XXX: consolidate on .format in struct mipi_dsi_device.
69 enum mipi_dsi_pixel_format pixel_format;
71 /* video mode format for MIPI_VIDEO_MODE_FORMAT register */
72 u32 video_mode_format;
74 /* eot for MIPI_EOT_DISABLE register */
81 u16 dcs_backlight_ports;
92 /* data lanes dphy timing */
93 u32 dphy_data_lane_reg;
94 u32 video_frmt_cfg_bits;
97 /* timeouts in byte clocks */
103 u16 clk_lp_to_hs_count;
104 u16 clk_hs_to_lp_count;
108 u16 burst_mode_ratio;
110 /* all delays in ms */
111 u16 backlight_off_delay;
112 u16 backlight_on_delay;
115 u16 panel_pwr_cycle_delay;
118 struct intel_dsi_host {
119 struct mipi_dsi_host base;
120 struct intel_dsi *intel_dsi;
123 /* our little hack */
124 struct mipi_dsi_device *device;
127 static inline struct intel_dsi_host *to_intel_dsi_host(struct mipi_dsi_host *h)
129 return container_of(h, struct intel_dsi_host, base);
132 #define for_each_dsi_port(__port, __ports_mask) for_each_port_masked(__port, __ports_mask)
134 static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
136 return container_of(encoder, struct intel_dsi, base.base);
139 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
141 return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
144 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
146 return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
149 static inline u16 intel_dsi_encoder_ports(struct intel_encoder *encoder)
151 return enc_to_intel_dsi(&encoder->base)->ports;
155 int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
156 int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
157 enum drm_panel_orientation
158 intel_dsi_get_panel_orientation(struct intel_connector *connector);
161 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
162 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
163 int intel_dsi_get_modes(struct drm_connector *connector);
164 enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
165 struct drm_display_mode *mode);
166 struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
167 const struct mipi_dsi_host_ops *funcs,
171 int vlv_dsi_pll_compute(struct intel_encoder *encoder,
172 struct intel_crtc_state *config);
173 void vlv_dsi_pll_enable(struct intel_encoder *encoder,
174 const struct intel_crtc_state *config);
175 void vlv_dsi_pll_disable(struct intel_encoder *encoder);
176 u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
177 struct intel_crtc_state *config);
178 void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
180 bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
181 int bxt_dsi_pll_compute(struct intel_encoder *encoder,
182 struct intel_crtc_state *config);
183 void bxt_dsi_pll_enable(struct intel_encoder *encoder,
184 const struct intel_crtc_state *config);
185 void bxt_dsi_pll_disable(struct intel_encoder *encoder);
186 u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
187 struct intel_crtc_state *config);
188 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
190 /* intel_dsi_vbt.c */
191 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
192 int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi);
193 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
194 enum mipi_seq seq_id);
195 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec);
197 #endif /* _INTEL_DSI_H */