drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/sched/clock.h>
  31 #include <linux/stackdepot.h>
  32
  33 #include <drm/drm_atomic.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_dp_dual_mode_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_encoder.h>
  38 #include <drm/drm_fb_helper.h>
  39 #include <drm/drm_probe_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_vblank.h>
  42 #include <drm/i915_drm.h>
  43 #include <drm/i915_mei_hdcp_interface.h>
  44 #include <media/cec-notifier.h>
  45
  46 #include "i915_drv.h"
  47
  48 struct drm_printer;
  49
  50 /**
  51  * __wait_for - magic wait macro
  52  *
  53  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
  54  * important that we check the condition again after having timed out, since the
  55  * timeout could be due to preemption or similar and we've never had a chance to
  56  * check the condition before the timeout.
  57  */
  58 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
  59         const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
  60         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  61         int ret__;                                                      \
  62         might_sleep();                                                  \
  63         for (;;) {                                                      \
  64                 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
  65                 OP;                                                     \
  66                 /* Guarantee COND check prior to timeout */             \
  67                 barrier();                                              \
  68                 if (COND) {                                             \
  69                         ret__ = 0;                                      \
  70                         break;                                          \
  71                 }                                                       \
  72                 if (expired__) {                                        \
  73                         ret__ = -ETIMEDOUT;                             \
  74                         break;                                          \
  75                 }                                                       \
  76                 usleep_range(wait__, wait__ * 2);                       \
  77                 if (wait__ < (Wmax))                                    \
  78                         wait__ <<= 1;                                   \
  79         }                                                               \
  80         ret__;                                                          \
  81 })
  82
  83 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
  84                                                    (Wmax))
  85 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
  86
  87 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  88 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  89 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  90 #else
  91 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  92 #endif
  93
  94 #define _wait_for_atomic(COND, US, ATOMIC) \
  95 ({ \
  96         int cpu, ret, timeout = (US) * 1000; \
  97         u64 base; \
  98         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  99         if (!(ATOMIC)) { \
 100                 preempt_disable(); \
 101                 cpu = smp_processor_id(); \
 102         } \
 103         base = local_clock(); \
 104         for (;;) { \
 105                 u64 now = local_clock(); \
 106                 if (!(ATOMIC)) \
 107                         preempt_enable(); \
 108                 /* Guarantee COND check prior to timeout */ \
 109                 barrier(); \
 110                 if (COND) { \
 111                         ret = 0; \
 112                         break; \
 113                 } \
 114                 if (now - base >= timeout) { \
 115                         ret = -ETIMEDOUT; \
 116                         break; \
 117                 } \
 118                 cpu_relax(); \
 119                 if (!(ATOMIC)) { \
 120                         preempt_disable(); \
 121                         if (unlikely(cpu != smp_processor_id())) { \
 122                                 timeout -= now - base; \
 123                                 cpu = smp_processor_id(); \
 124                                 base = local_clock(); \
 125                         } \
 126                 } \
 127         } \
 128         ret; \
 129 })
 130
 131 #define wait_for_us(COND, US) \
 132 ({ \
 133         int ret__; \
 134         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 135         if ((US) > 10) \
 136                 ret__ = _wait_for((COND), (US), 10, 10); \
 137         else \
 138                 ret__ = _wait_for_atomic((COND), (US), 0); \
 139         ret__; \
 140 })
 141
 142 #define wait_for_atomic_us(COND, US) \
 143 ({ \
 144         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 145         BUILD_BUG_ON((US) > 50000); \
 146         _wait_for_atomic((COND), (US), 1); \
 147 })
 148
 149 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 150
 151 #define KHz(x) (1000 * (x))
 152 #define MHz(x) KHz(1000 * (x))
 153
 154 #define KBps(x) (1000 * (x))
 155 #define MBps(x) KBps(1000 * (x))
 156 #define GBps(x) ((u64)1000 * MBps((x)))
 157
 158 /*
 159  * Display related stuff
 160  */
 161
 162 /* store information about an Ixxx DVO */
 163 /* The i830->i865 use multiple DVOs with multiple i2cs */
 164 /* the i915, i945 have a single sDVO i2c bus - which is different */
 165 #define MAX_OUTPUTS 6
 166 /* maximum connectors per crtcs in the mode set */
 167
 168 #define INTEL_I2C_BUS_DVO 1
 169 #define INTEL_I2C_BUS_SDVO 2
 170
 171 /* these are outputs from the chip - integrated only
 172    external chips are via DVO or SDVO output */
 173 enum intel_output_type {
 174         INTEL_OUTPUT_UNUSED = 0,
 175         INTEL_OUTPUT_ANALOG = 1,
 176         INTEL_OUTPUT_DVO = 2,
 177         INTEL_OUTPUT_SDVO = 3,
 178         INTEL_OUTPUT_LVDS = 4,
 179         INTEL_OUTPUT_TVOUT = 5,
 180         INTEL_OUTPUT_HDMI = 6,
 181         INTEL_OUTPUT_DP = 7,
 182         INTEL_OUTPUT_EDP = 8,
 183         INTEL_OUTPUT_DSI = 9,
 184         INTEL_OUTPUT_DDI = 10,
 185         INTEL_OUTPUT_DP_MST = 11,
 186 };
 187
 188 #define INTEL_DVO_CHIP_NONE 0
 189 #define INTEL_DVO_CHIP_LVDS 1
 190 #define INTEL_DVO_CHIP_TMDS 2
 191 #define INTEL_DVO_CHIP_TVOUT 4
 192
 193 #define INTEL_DSI_VIDEO_MODE    0
 194 #define INTEL_DSI_COMMAND_MODE  1
 195
 196 struct intel_framebuffer {
 197         struct drm_framebuffer base;
 198         struct intel_rotation_info rot_info;
 199
 200         /* for each plane in the normal GTT view */
 201         struct {
 202                 unsigned int x, y;
 203         } normal[2];
 204         /* for each plane in the rotated GTT view */
 205         struct {
 206                 unsigned int x, y;
 207                 unsigned int pitch; /* pixels */
 208         } rotated[2];
 209 };
 210
 211 struct intel_fbdev {
 212         struct drm_fb_helper helper;
 213         struct intel_framebuffer *fb;
 214         struct i915_vma *vma;
 215         unsigned long vma_flags;
 216         async_cookie_t cookie;
 217         int preferred_bpp;
 218
 219         /* Whether or not fbdev hpd processing is temporarily suspended */
 220         bool hpd_suspended : 1;
 221         /* Set when a hotplug was received while HPD processing was
 222          * suspended
 223          */
 224         bool hpd_waiting : 1;
 225
 226         /* Protects hpd_suspended */
 227         struct mutex hpd_lock;
 228 };
 229
 230 struct intel_encoder {
 231         struct drm_encoder base;
 232
 233         enum intel_output_type type;
 234         enum port port;
 235         unsigned int cloneable;
 236         bool (*hotplug)(struct intel_encoder *encoder,
 237                         struct intel_connector *connector);
 238         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 239                                                       struct intel_crtc_state *,
 240                                                       struct drm_connector_state *);
 241         int (*compute_config)(struct intel_encoder *,
 242                               struct intel_crtc_state *,
 243                               struct drm_connector_state *);
 244         void (*pre_pll_enable)(struct intel_encoder *,
 245                                const struct intel_crtc_state *,
 246                                const struct drm_connector_state *);
 247         void (*pre_enable)(struct intel_encoder *,
 248                            const struct intel_crtc_state *,
 249                            const struct drm_connector_state *);
 250         void (*enable)(struct intel_encoder *,
 251                        const struct intel_crtc_state *,
 252                        const struct drm_connector_state *);
 253         void (*disable)(struct intel_encoder *,
 254                         const struct intel_crtc_state *,
 255                         const struct drm_connector_state *);
 256         void (*post_disable)(struct intel_encoder *,
 257                              const struct intel_crtc_state *,
 258                              const struct drm_connector_state *);
 259         void (*post_pll_disable)(struct intel_encoder *,
 260                                  const struct intel_crtc_state *,
 261                                  const struct drm_connector_state *);
 262         void (*update_pipe)(struct intel_encoder *,
 263                             const struct intel_crtc_state *,
 264                             const struct drm_connector_state *);
 265         /* Read out the current hw state of this connector, returning true if
 266          * the encoder is active. If the encoder is enabled it also set the pipe
 267          * it is connected to in the pipe parameter. */
 268         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 269         /* Reconstructs the equivalent mode flags for the current hardware
 270          * state. This must be called _after_ display->get_pipe_config has
 271          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 272          * be set correctly before calling this function. */
 273         void (*get_config)(struct intel_encoder *,
 274                            struct intel_crtc_state *pipe_config);
 275         /*
 276          * Acquires the power domains needed for an active encoder during
 277          * hardware state readout.
 278          */
 279         void (*get_power_domains)(struct intel_encoder *encoder,
 280                                   struct intel_crtc_state *crtc_state);
 281         /*
 282          * Called during system suspend after all pending requests for the
 283          * encoder are flushed (for example for DP AUX transactions) and
 284          * device interrupts are disabled.
 285          */
 286         void (*suspend)(struct intel_encoder *);
 287         int crtc_mask;
 288         enum hpd_pin hpd_pin;
 289         enum intel_display_power_domain power_domain;
 290         /* for communication with audio component; protected by av_mutex */
 291         const struct drm_connector *audio_connector;
 292 };
 293
 294 struct intel_panel {
 295         struct drm_display_mode *fixed_mode;
 296         struct drm_display_mode *downclock_mode;
 297
 298         /* backlight */
 299         struct {
 300                 bool present;
 301                 u32 level;
 302                 u32 min;
 303                 u32 max;
 304                 bool enabled;
 305                 bool combination_mode;  /* gen 2/4 only */
 306                 bool active_low_pwm;
 307                 bool alternate_pwm_increment;   /* lpt+ */
 308
 309                 /* PWM chip */
 310                 bool util_pin_active_low;       /* bxt+ */
 311                 u8 controller;          /* bxt+ only */
 312                 struct pwm_device *pwm;
 313
 314                 struct backlight_device *device;
 315
 316                 /* Connector and platform specific backlight functions */
 317                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 318                 u32 (*get)(struct intel_connector *connector);
 319                 void (*set)(const struct drm_connector_state *conn_state, u32 level);
 320                 void (*disable)(const struct drm_connector_state *conn_state);
 321                 void (*enable)(const struct intel_crtc_state *crtc_state,
 322                                const struct drm_connector_state *conn_state);
 323                 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
 324                 void (*power)(struct intel_connector *, bool enable);
 325         } backlight;
 326 };
 327
 328 struct intel_digital_port;
 329
 330 enum check_link_response {
 331         HDCP_LINK_PROTECTED     = 0,
 332         HDCP_TOPOLOGY_CHANGE,
 333         HDCP_LINK_INTEGRITY_FAILURE,
 334         HDCP_REAUTH_REQUEST
 335 };
 336
 337 /*
 338  * This structure serves as a translation layer between the generic HDCP code
 339  * and the bus-specific code. What that means is that HDCP over HDMI differs
 340  * from HDCP over DP, so to account for these differences, we need to
 341  * communicate with the receiver through this shim.
 342  *
 343  * For completeness, the 2 buses differ in the following ways:
 344  *      - DP AUX vs. DDC
 345  *              HDCP registers on the receiver are set via DP AUX for DP, and
 346  *              they are set via DDC for HDMI.
 347  *      - Receiver register offsets
 348  *              The offsets of the registers are different for DP vs. HDMI
 349  *      - Receiver register masks/offsets
 350  *              For instance, the ready bit for the KSV fifo is in a different
 351  *              place on DP vs HDMI
 352  *      - Receiver register names
 353  *              Seriously. In the DP spec, the 16-bit register containing
 354  *              downstream information is called BINFO, on HDMI it's called
 355  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
 356  *              with a completely different definition.
 357  *      - KSV FIFO
 358  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
 359  *              be read 3 keys at a time
 360  *      - Aksv output
 361  *              Since Aksv is hidden in hardware, there's different procedures
 362  *              to send it over DP AUX vs DDC
 363  */
 364 struct intel_hdcp_shim {
 365         /* Outputs the transmitter's An and Aksv values to the receiver. */
 366         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
 367
 368         /* Reads the receiver's key selection vector */
 369         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
 370
 371         /*
 372          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
 373          * definitions are the same in the respective specs, but the names are
 374          * different. Call it BSTATUS since that's the name the HDMI spec
 375          * uses and it was there first.
 376          */
 377         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
 378                             u8 *bstatus);
 379
 380         /* Determines whether a repeater is present downstream */
 381         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
 382                                 bool *repeater_present);
 383
 384         /* Reads the receiver's Ri' value */
 385         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
 386
 387         /* Determines if the receiver's KSV FIFO is ready for consumption */
 388         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
 389                               bool *ksv_ready);
 390
 391         /* Reads the ksv fifo for num_downstream devices */
 392         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
 393                              int num_downstream, u8 *ksv_fifo);
 394
 395         /* Reads a 32-bit part of V' from the receiver */
 396         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
 397                                  int i, u32 *part);
 398
 399         /* Enables HDCP signalling on the port */
 400         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
 401                                  bool enable);
 402
 403         /* Ensures the link is still protected */
 404         bool (*check_link)(struct intel_digital_port *intel_dig_port);
 405
 406         /* Detects panel's hdcp capability. This is optional for HDMI. */
 407         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
 408                             bool *hdcp_capable);
 409
 410         /* HDCP adaptation(DP/HDMI) required on the port */
 411         enum hdcp_wired_protocol protocol;
 412
 413         /* Detects whether sink is HDCP2.2 capable */
 414         int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
 415                                 bool *capable);
 416
 417         /* Write HDCP2.2 messages */
 418         int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
 419                              void *buf, size_t size);
 420
 421         /* Read HDCP2.2 messages */
 422         int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
 423                             u8 msg_id, void *buf, size_t size);
 424
 425         /*
 426          * Implementation of DP HDCP2.2 Errata for the communication of stream
 427          * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
 428          * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
 429          */
 430         int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
 431                                   bool is_repeater, u8 type);
 432
 433         /* HDCP2.2 Link Integrity Check */
 434         int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
 435 };
 436
 437 struct intel_hdcp {
 438         const struct intel_hdcp_shim *shim;
 439         /* Mutex for hdcp state of the connector */
 440         struct mutex mutex;
 441         u64 value;
 442         struct delayed_work check_work;
 443         struct work_struct prop_work;
 444
 445         /* HDCP1.4 Encryption status */
 446         bool hdcp_encrypted;
 447
 448         /* HDCP2.2 related definitions */
 449         /* Flag indicates whether this connector supports HDCP2.2 or not. */
 450         bool hdcp2_supported;
 451
 452         /* HDCP2.2 Encryption status */
 453         bool hdcp2_encrypted;
 454
 455         /*
 456          * Content Stream Type defined by content owner. TYPE0(0x0) content can
 457          * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
 458          * content can flow only through a link protected by HDCP2.2.
 459          */
 460         u8 content_type;
 461         struct hdcp_port_data port_data;
 462
 463         bool is_paired;
 464         bool is_repeater;
 465
 466         /*
 467          * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
 468          * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
 469          * When it rolls over re-auth has to be triggered.
 470          */
 471         u32 seq_num_v;
 472
 473         /*
 474          * Count of RepeaterAuth_Stream_Manage msg propagated.
 475          * Initialized to 0 on AKE_INIT. Incremented after every successful
 476          * transmission of RepeaterAuth_Stream_Manage message. When it rolls
 477          * over re-Auth has to be triggered.
 478          */
 479         u32 seq_num_m;
 480
 481         /*
 482          * Work queue to signal the CP_IRQ. Used for the waiters to read the
 483          * available information from HDCP DP sink.
 484          */
 485         wait_queue_head_t cp_irq_queue;
 486         atomic_t cp_irq_count;
 487         int cp_irq_count_cached;
 488 };
 489
 490 struct intel_connector {
 491         struct drm_connector base;
 492         /*
 493          * The fixed encoder this connector is connected to.
 494          */
 495         struct intel_encoder *encoder;
 496
 497         /* ACPI device id for ACPI and driver cooperation */
 498         u32 acpi_device_id;
 499
 500         /* Reads out the current hw, returning true if the connector is enabled
 501          * and active (i.e. dpms ON state). */
 502         bool (*get_hw_state)(struct intel_connector *);
 503
 504         /* Panel info for eDP and LVDS */
 505         struct intel_panel panel;
 506
 507         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 508         struct edid *edid;
 509         struct edid *detect_edid;
 510
 511         /* since POLL and HPD connectors may use the same HPD line keep the native
 512            state of connector->polled in case hotplug storm detection changes it */
 513         u8 polled;
 514
 515         void *port; /* store this opaque as its illegal to dereference it */
 516
 517         struct intel_dp *mst_port;
 518
 519         /* Work struct to schedule a uevent on link train failure */
 520         struct work_struct modeset_retry_work;
 521
 522         struct intel_hdcp hdcp;
 523 };
 524
 525 struct intel_digital_connector_state {
 526         struct drm_connector_state base;
 527
 528         enum hdmi_force_audio force_audio;
 529         int broadcast_rgb;
 530 };
 531
 532 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 533
 534 struct dpll {
 535         /* given values */
 536         int n;
 537         int m1, m2;
 538         int p1, p2;
 539         /* derived values */
 540         int     dot;
 541         int     vco;
 542         int     m;
 543         int     p;
 544 };
 545
 546 struct intel_atomic_state {
 547         struct drm_atomic_state base;
 548
 549         struct {
 550                 /*
 551                  * Logical state of cdclk (used for all scaling, watermark,
 552                  * etc. calculations and checks). This is computed as if all
 553                  * enabled crtcs were active.
 554                  */
 555                 struct intel_cdclk_state logical;
 556
 557                 /*
 558                  * Actual state of cdclk, can be different from the logical
 559                  * state only when all crtc's are DPMS off.
 560                  */
 561                 struct intel_cdclk_state actual;
 562
 563                 int force_min_cdclk;
 564                 bool force_min_cdclk_changed;
 565                 /* pipe to which cd2x update is synchronized */
 566                 enum pipe pipe;
 567         } cdclk;
 568
 569         bool dpll_set, modeset;
 570
 571         /*
 572          * Does this transaction change the pipes that are active?  This mask
 573          * tracks which CRTC's have changed their active state at the end of
 574          * the transaction (not counting the temporary disable during modesets).
 575          * This mask should only be non-zero when intel_state->modeset is true,
 576          * but the converse is not necessarily true; simply changing a mode may
 577          * not flip the final active status of any CRTC's
 578          */
 579         unsigned int active_pipe_changes;
 580
 581         unsigned int active_crtcs;
 582         /* minimum acceptable cdclk for each pipe */
 583         int min_cdclk[I915_MAX_PIPES];
 584         /* minimum acceptable voltage level for each pipe */
 585         u8 min_voltage_level[I915_MAX_PIPES];
 586
 587         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 588
 589         /*
 590          * Current watermarks can't be trusted during hardware readout, so
 591          * don't bother calculating intermediate watermarks.
 592          */
 593         bool skip_intermediate_wm;
 594
 595         bool rps_interactive;
 596
 597         /* Gen9+ only */
 598         struct skl_ddb_values wm_results;
 599
 600         struct i915_sw_fence commit_ready;
 601
 602         struct llist_node freed;
 603 };
 604
 605 struct intel_plane_state {
 606         struct drm_plane_state base;
 607         struct i915_ggtt_view view;
 608         struct i915_vma *vma;
 609         unsigned long flags;
 610 #define PLANE_HAS_FENCE BIT(0)
 611
 612         struct {
 613                 u32 offset;
 614                 /*
 615                  * Plane stride in:
 616                  * bytes for 0/180 degree rotation
 617                  * pixels for 90/270 degree rotation
 618                  */
 619                 u32 stride;
 620                 int x, y;
 621         } color_plane[2];
 622
 623         /* plane control register */
 624         u32 ctl;
 625
 626         /* plane color control register */
 627         u32 color_ctl;
 628
 629         /*
 630          * scaler_id
 631          *    = -1 : not using a scaler
 632          *    >=  0 : using a scalers
 633          *
 634          * plane requiring a scaler:
 635          *   - During check_plane, its bit is set in
 636          *     crtc_state->scaler_state.scaler_users by calling helper function
 637          *     update_scaler_plane.
 638          *   - scaler_id indicates the scaler it got assigned.
 639          *
 640          * plane doesn't require a scaler:
 641          *   - this can happen when scaling is no more required or plane simply
 642          *     got disabled.
 643          *   - During check_plane, corresponding bit is reset in
 644          *     crtc_state->scaler_state.scaler_users by calling helper function
 645          *     update_scaler_plane.
 646          */
 647         int scaler_id;
 648
 649         /*
 650          * linked_plane:
 651          *
 652          * ICL planar formats require 2 planes that are updated as pairs.
 653          * This member is used to make sure the other plane is also updated
 654          * when required, and for update_slave() to find the correct
 655          * plane_state to pass as argument.
 656          */
 657         struct intel_plane *linked_plane;
 658
 659         /*
 660          * slave:
 661          * If set don't update use the linked plane's state for updating
 662          * this plane during atomic commit with the update_slave() callback.
 663          *
 664          * It's also used by the watermark code to ignore wm calculations on
 665          * this plane. They're calculated by the linked plane's wm code.
 666          */
 667         u32 slave;
 668
 669         struct drm_intel_sprite_colorkey ckey;
 670 };
 671
 672 struct intel_initial_plane_config {
 673         struct intel_framebuffer *fb;
 674         unsigned int tiling;
 675         int size;
 676         u32 base;
 677         u8 rotation;
 678 };
 679
 680 #define SKL_MIN_SRC_W 8
 681 #define SKL_MAX_SRC_W 4096
 682 #define SKL_MIN_SRC_H 8
 683 #define SKL_MAX_SRC_H 4096
 684 #define SKL_MIN_DST_W 8
 685 #define SKL_MAX_DST_W 4096
 686 #define SKL_MIN_DST_H 8
 687 #define SKL_MAX_DST_H 4096
 688 #define ICL_MAX_SRC_W 5120
 689 #define ICL_MAX_SRC_H 4096
 690 #define ICL_MAX_DST_W 5120
 691 #define ICL_MAX_DST_H 4096
 692 #define SKL_MIN_YUV_420_SRC_W 16
 693 #define SKL_MIN_YUV_420_SRC_H 16
 694
 695 struct intel_scaler {
 696         int in_use;
 697         u32 mode;
 698 };
 699
 700 struct intel_crtc_scaler_state {
 701 #define SKL_NUM_SCALERS 2
 702         struct intel_scaler scalers[SKL_NUM_SCALERS];
 703
 704         /*
 705          * scaler_users: keeps track of users requesting scalers on this crtc.
 706          *
 707          *     If a bit is set, a user is using a scaler.
 708          *     Here user can be a plane or crtc as defined below:
 709          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 710          *       bit 31    - crtc
 711          *
 712          * Instead of creating a new index to cover planes and crtc, using
 713          * existing drm_plane_index for planes which is well less than 31
 714          * planes and bit 31 for crtc. This should be fine to cover all
 715          * our platforms.
 716          *
 717          * intel_atomic_setup_scalers will setup available scalers to users
 718          * requesting scalers. It will gracefully fail if request exceeds
 719          * avilability.
 720          */
 721 #define SKL_CRTC_INDEX 31
 722         unsigned scaler_users;
 723
 724         /* scaler used by crtc for panel fitting purpose */
 725         int scaler_id;
 726 };
 727
 728 /* drm_mode->private_flags */
 729 #define I915_MODE_FLAG_INHERITED (1<<0)
 730 /* Flag to get scanline using frame time stamps */
 731 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 732 /* Flag to use the scanline counter instead of the pixel counter */
 733 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
 734
 735 struct intel_pipe_wm {
 736         struct intel_wm_level wm[5];
 737         u32 linetime;
 738         bool fbc_wm_enabled;
 739         bool pipe_enabled;
 740         bool sprites_enabled;
 741         bool sprites_scaled;
 742 };
 743
 744 struct skl_plane_wm {
 745         struct skl_wm_level wm[8];
 746         struct skl_wm_level uv_wm[8];
 747         struct skl_wm_level trans_wm;
 748         bool is_planar;
 749 };
 750
 751 struct skl_pipe_wm {
 752         struct skl_plane_wm planes[I915_MAX_PLANES];
 753         u32 linetime;
 754 };
 755
 756 enum vlv_wm_level {
 757         VLV_WM_LEVEL_PM2,
 758         VLV_WM_LEVEL_PM5,
 759         VLV_WM_LEVEL_DDR_DVFS,
 760         NUM_VLV_WM_LEVELS,
 761 };
 762
 763 struct vlv_wm_state {
 764         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 765         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 766         u8 num_levels;
 767         bool cxsr;
 768 };
 769
 770 struct vlv_fifo_state {
 771         u16 plane[I915_MAX_PLANES];
 772 };
 773
 774 enum g4x_wm_level {
 775         G4X_WM_LEVEL_NORMAL,
 776         G4X_WM_LEVEL_SR,
 777         G4X_WM_LEVEL_HPLL,
 778         NUM_G4X_WM_LEVELS,
 779 };
 780
 781 struct g4x_wm_state {
 782         struct g4x_pipe_wm wm;
 783         struct g4x_sr_wm sr;
 784         struct g4x_sr_wm hpll;
 785         bool cxsr;
 786         bool hpll_en;
 787         bool fbc_en;
 788 };
 789
 790 struct intel_crtc_wm_state {
 791         union {
 792                 struct {
 793                         /*
 794                          * Intermediate watermarks; these can be
 795                          * programmed immediately since they satisfy
 796                          * both the current configuration we're
 797                          * switching away from and the new
 798                          * configuration we're switching to.
 799                          */
 800                         struct intel_pipe_wm intermediate;
 801
 802                         /*
 803                          * Optimal watermarks, programmed post-vblank
 804                          * when this state is committed.
 805                          */
 806                         struct intel_pipe_wm optimal;
 807                 } ilk;
 808
 809                 struct {
 810                         /* gen9+ only needs 1-step wm programming */
 811                         struct skl_pipe_wm optimal;
 812                         struct skl_ddb_entry ddb;
 813                         struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
 814                         struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
 815                 } skl;
 816
 817                 struct {
 818                         /* "raw" watermarks (not inverted) */
 819                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 820                         /* intermediate watermarks (inverted) */
 821                         struct vlv_wm_state intermediate;
 822                         /* optimal watermarks (inverted) */
 823                         struct vlv_wm_state optimal;
 824                         /* display FIFO split */
 825                         struct vlv_fifo_state fifo_state;
 826                 } vlv;
 827
 828                 struct {
 829                         /* "raw" watermarks */
 830                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 831                         /* intermediate watermarks */
 832                         struct g4x_wm_state intermediate;
 833                         /* optimal watermarks */
 834                         struct g4x_wm_state optimal;
 835                 } g4x;
 836         };
 837
 838         /*
 839          * Platforms with two-step watermark programming will need to
 840          * update watermark programming post-vblank to switch from the
 841          * safe intermediate watermarks to the optimal final
 842          * watermarks.
 843          */
 844         bool need_postvbl_update;
 845 };
 846
 847 enum intel_output_format {
 848         INTEL_OUTPUT_FORMAT_INVALID,
 849         INTEL_OUTPUT_FORMAT_RGB,
 850         INTEL_OUTPUT_FORMAT_YCBCR420,
 851         INTEL_OUTPUT_FORMAT_YCBCR444,
 852 };
 853
 854 struct intel_crtc_state {
 855         struct drm_crtc_state base;
 856
 857         /**
 858          * quirks - bitfield with hw state readout quirks
 859          *
 860          * For various reasons the hw state readout code might not be able to
 861          * completely faithfully read out the current state. These cases are
 862          * tracked with quirk flags so that fastboot and state checker can act
 863          * accordingly.
 864          */
 865 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 866         unsigned long quirks;
 867
 868         unsigned fb_bits; /* framebuffers to flip */
 869         bool update_pipe; /* can a fast modeset be performed? */
 870         bool disable_cxsr;
 871         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 872         bool fb_changed; /* fb on any of the planes is changed */
 873         bool fifo_changed; /* FIFO split is changed */
 874
 875         /* Pipe source size (ie. panel fitter input size)
 876          * All planes will be positioned inside this space,
 877          * and get clipped at the edges. */
 878         int pipe_src_w, pipe_src_h;
 879
 880         /*
 881          * Pipe pixel rate, adjusted for
 882          * panel fitter/pipe scaler downscaling.
 883          */
 884         unsigned int pixel_rate;
 885
 886         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 887          * between pch encoders and cpu encoders. */
 888         bool has_pch_encoder;
 889
 890         /* Are we sending infoframes on the attached port */
 891         bool has_infoframe;
 892
 893         /* CPU Transcoder for the pipe. Currently this can only differ from the
 894          * pipe on Haswell and later (where we have a special eDP transcoder)
 895          * and Broxton (where we have special DSI transcoders). */
 896         enum transcoder cpu_transcoder;
 897
 898         /*
 899          * Use reduced/limited/broadcast rbg range, compressing from the full
 900          * range fed into the crtcs.
 901          */
 902         bool limited_color_range;
 903
 904         /* Bitmask of encoder types (enum intel_output_type)
 905          * driven by the pipe.
 906          */
 907         unsigned int output_types;
 908
 909         /* Whether we should send NULL infoframes. Required for audio. */
 910         bool has_hdmi_sink;
 911
 912         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 913          * has_dp_encoder is set. */
 914         bool has_audio;
 915
 916         /*
 917          * Enable dithering, used when the selected pipe bpp doesn't match the
 918          * plane bpp.
 919          */
 920         bool dither;
 921
 922         /*
 923          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 924          * compliance video pattern tests.
 925          * Disable dither only if it is a compliance test request for
 926          * 18bpp.
 927          */
 928         bool dither_force_disable;
 929
 930         /* Controls for the clock computation, to override various stages. */
 931         bool clock_set;
 932
 933         /* SDVO TV has a bunch of special case. To make multifunction encoders
 934          * work correctly, we need to track this at runtime.*/
 935         bool sdvo_tv_clock;
 936
 937         /*
 938          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 939          * required. This is set in the 2nd loop of calling encoder's
 940          * ->compute_config if the first pick doesn't work out.
 941          */
 942         bool bw_constrained;
 943
 944         /* Settings for the intel dpll used on pretty much everything but
 945          * haswell. */
 946         struct dpll dpll;
 947
 948         /* Selected dpll when shared or NULL. */
 949         struct intel_shared_dpll *shared_dpll;
 950
 951         /* Actual register state of the dpll, for shared dpll cross-checking. */
 952         struct intel_dpll_hw_state dpll_hw_state;
 953
 954         /* DSI PLL registers */
 955         struct {
 956                 u32 ctrl, div;
 957         } dsi_pll;
 958
 959         int pipe_bpp;
 960         struct intel_link_m_n dp_m_n;
 961
 962         /* m2_n2 for eDP downclock */
 963         struct intel_link_m_n dp_m2_n2;
 964         bool has_drrs;
 965
 966         bool has_psr;
 967         bool has_psr2;
 968
 969         /*
 970          * Frequence the dpll for the port should run at. Differs from the
 971          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 972          * already multiplied by pixel_multiplier.
 973          */
 974         int port_clock;
 975
 976         /* Used by SDVO (and if we ever fix it, HDMI). */
 977         unsigned pixel_multiplier;
 978
 979         u8 lane_count;
 980
 981         /*
 982          * Used by platforms having DP/HDMI PHY with programmable lane
 983          * latency optimization.
 984          */
 985         u8 lane_lat_optim_mask;
 986
 987         /* minimum acceptable voltage level */
 988         u8 min_voltage_level;
 989
 990         /* Panel fitter controls for gen2-gen4 + VLV */
 991         struct {
 992                 u32 control;
 993                 u32 pgm_ratios;
 994                 u32 lvds_border_bits;
 995         } gmch_pfit;
 996
 997         /* Panel fitter placement and size for Ironlake+ */
 998         struct {
 999                 u32 pos;
1000                 u32 size;
1001                 bool enabled;
1002                 bool force_thru;
1003         } pch_pfit;
1004
1005         /* FDI configuration, only valid if has_pch_encoder is set. */
1006         int fdi_lanes;
1007         struct intel_link_m_n fdi_m_n;
1008
1009         bool ips_enabled;
1010
1011         bool crc_enabled;
1012
1013         bool enable_fbc;
1014
1015         bool double_wide;
1016
1017         int pbn;
1018
1019         struct intel_crtc_scaler_state scaler_state;
1020
1021         /* w/a for waiting 2 vblanks during crtc enable */
1022         enum pipe hsw_workaround_pipe;
1023
1024         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1025         bool disable_lp_wm;
1026
1027         struct intel_crtc_wm_state wm;
1028
1029         /* Gamma mode programmed on the pipe */
1030         u32 gamma_mode;
1031
1032         union {
1033                 /* CSC mode programmed on the pipe */
1034                 u32 csc_mode;
1035
1036                 /* CHV CGM mode */
1037                 u32 cgm_mode;
1038         };
1039
1040         /* bitmask of visible planes (enum plane_id) */
1041         u8 active_planes;
1042         u8 nv12_planes;
1043         u8 c8_planes;
1044
1045         /* bitmask of planes that will be updated during the commit */
1046         u8 update_planes;
1047
1048         struct {
1049                 u32 enable;
1050                 u32 gcp;
1051                 union hdmi_infoframe avi;
1052                 union hdmi_infoframe spd;
1053                 union hdmi_infoframe hdmi;
1054         } infoframes;
1055
1056         /* HDMI scrambling status */
1057         bool hdmi_scrambling;
1058
1059         /* HDMI High TMDS char rate ratio */
1060         bool hdmi_high_tmds_clock_ratio;
1061
1062         /* Output format RGB/YCBCR etc */
1063         enum intel_output_format output_format;
1064
1065         /* Output down scaling is done in LSPCON device */
1066         bool lspcon_downsampling;
1067
1068         /* enable pipe gamma? */
1069         bool gamma_enable;
1070
1071         /* enable pipe csc? */
1072         bool csc_enable;
1073
1074         /* Display Stream compression state */
1075         struct {
1076                 bool compression_enable;
1077                 bool dsc_split;
1078                 u16 compressed_bpp;
1079                 u8 slice_count;
1080         } dsc_params;
1081         struct drm_dsc_config dp_dsc_cfg;
1082
1083         /* Forward Error correction State */
1084         bool fec_enable;
1085 };
1086
1087 struct intel_crtc {
1088         struct drm_crtc base;
1089         enum pipe pipe;
1090         /*
1091          * Whether the crtc and the connected output pipeline is active. Implies
1092          * that crtc->enabled is set, i.e. the current mode configuration has
1093          * some outputs connected to this crtc.
1094          */
1095         bool active;
1096         u8 plane_ids_mask;
1097         unsigned long long enabled_power_domains;
1098         struct intel_overlay *overlay;
1099
1100         struct intel_crtc_state *config;
1101
1102         /* Access to these should be protected by dev_priv->irq_lock. */
1103         bool cpu_fifo_underrun_disabled;
1104         bool pch_fifo_underrun_disabled;
1105
1106         /* per-pipe watermark state */
1107         struct {
1108                 /* watermarks currently being used  */
1109                 union {
1110                         struct intel_pipe_wm ilk;
1111                         struct vlv_wm_state vlv;
1112                         struct g4x_wm_state g4x;
1113                 } active;
1114         } wm;
1115
1116         int scanline_offset;
1117
1118         struct {
1119                 unsigned start_vbl_count;
1120                 ktime_t start_vbl_time;
1121                 int min_vbl, max_vbl;
1122                 int scanline_start;
1123         } debug;
1124
1125         /* scalers available on this crtc */
1126         int num_scalers;
1127 };
1128
1129 struct intel_plane {
1130         struct drm_plane base;
1131         enum i9xx_plane_id i9xx_plane;
1132         enum plane_id id;
1133         enum pipe pipe;
1134         bool has_fbc;
1135         bool has_ccs;
1136         u32 frontbuffer_bit;
1137
1138         struct {
1139                 u32 base, cntl, size;
1140         } cursor;
1141
1142         /*
1143          * NOTE: Do not place new plane state fields here (e.g., when adding
1144          * new plane properties).  New runtime state should now be placed in
1145          * the intel_plane_state structure and accessed via plane_state.
1146          */
1147
1148         unsigned int (*max_stride)(struct intel_plane *plane,
1149                                    u32 pixel_format, u64 modifier,
1150                                    unsigned int rotation);
1151         void (*update_plane)(struct intel_plane *plane,
1152                              const struct intel_crtc_state *crtc_state,
1153                              const struct intel_plane_state *plane_state);
1154         void (*update_slave)(struct intel_plane *plane,
1155                              const struct intel_crtc_state *crtc_state,
1156                              const struct intel_plane_state *plane_state);
1157         void (*disable_plane)(struct intel_plane *plane,
1158                               const struct intel_crtc_state *crtc_state);
1159         bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1160         int (*check_plane)(struct intel_crtc_state *crtc_state,
1161                            struct intel_plane_state *plane_state);
1162 };
1163
1164 struct intel_watermark_params {
1165         u16 fifo_size;
1166         u16 max_wm;
1167         u8 default_wm;
1168         u8 guard_size;
1169         u8 cacheline_size;
1170 };
1171
1172 struct cxsr_latency {
1173         bool is_desktop : 1;
1174         bool is_ddr3 : 1;
1175         u16 fsb_freq;
1176         u16 mem_freq;
1177         u16 display_sr;
1178         u16 display_hpll_disable;
1179         u16 cursor_sr;
1180         u16 cursor_hpll_disable;
1181 };
1182
1183 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1184 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1185 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1186 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1187 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1188 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1189 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1190 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1191 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1192
1193 struct intel_hdmi {
1194         i915_reg_t hdmi_reg;
1195         int ddc_bus;
1196         struct {
1197                 enum drm_dp_dual_mode_type type;
1198                 int max_tmds_clock;
1199         } dp_dual_mode;
1200         bool has_hdmi_sink;
1201         bool has_audio;
1202         struct intel_connector *attached_connector;
1203         struct cec_notifier *cec_notifier;
1204 };
1205
1206 struct intel_dp_mst_encoder;
1207 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1208
1209 /*
1210  * enum link_m_n_set:
1211  *      When platform provides two set of M_N registers for dp, we can
1212  *      program them and switch between them incase of DRRS.
1213  *      But When only one such register is provided, we have to program the
1214  *      required divider value on that registers itself based on the DRRS state.
1215  *
1216  * M1_N1        : Program dp_m_n on M1_N1 registers
1217  *                        dp_m2_n2 on M2_N2 registers (If supported)
1218  *
1219  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1220  *                        M2_N2 registers are not supported
1221  */
1222
1223 enum link_m_n_set {
1224         /* Sets the m1_n1 and m2_n2 */
1225         M1_N1 = 0,
1226         M2_N2
1227 };
1228
1229 struct intel_dp_compliance_data {
1230         unsigned long edid;
1231         u8 video_pattern;
1232         u16 hdisplay, vdisplay;
1233         u8 bpc;
1234 };
1235
1236 struct intel_dp_compliance {
1237         unsigned long test_type;
1238         struct intel_dp_compliance_data test_data;
1239         bool test_active;
1240         int test_link_rate;
1241         u8 test_lane_count;
1242 };
1243
1244 struct intel_dp {
1245         i915_reg_t output_reg;
1246         u32 DP;
1247         int link_rate;
1248         u8 lane_count;
1249         u8 sink_count;
1250         bool link_mst;
1251         bool link_trained;
1252         bool has_audio;
1253         bool reset_link_params;
1254         u8 dpcd[DP_RECEIVER_CAP_SIZE];
1255         u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1256         u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1257         u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1258         u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1259         u8 fec_capable;
1260         /* source rates */
1261         int num_source_rates;
1262         const int *source_rates;
1263         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1264         int num_sink_rates;
1265         int sink_rates[DP_MAX_SUPPORTED_RATES];
1266         bool use_rate_select;
1267         /* intersection of source and sink rates */
1268         int num_common_rates;
1269         int common_rates[DP_MAX_SUPPORTED_RATES];
1270         /* Max lane count for the current link */
1271         int max_link_lane_count;
1272         /* Max rate for the current link */
1273         int max_link_rate;
1274         /* sink or branch descriptor */
1275         struct drm_dp_desc desc;
1276         struct drm_dp_aux aux;
1277         u8 train_set[4];
1278         int panel_power_up_delay;
1279         int panel_power_down_delay;
1280         int panel_power_cycle_delay;
1281         int backlight_on_delay;
1282         int backlight_off_delay;
1283         struct delayed_work panel_vdd_work;
1284         bool want_panel_vdd;
1285         unsigned long last_power_on;
1286         unsigned long last_backlight_off;
1287         ktime_t panel_power_off_time;
1288
1289         struct notifier_block edp_notifier;
1290
1291         /*
1292          * Pipe whose power sequencer is currently locked into
1293          * this port. Only relevant on VLV/CHV.
1294          */
1295         enum pipe pps_pipe;
1296         /*
1297          * Pipe currently driving the port. Used for preventing
1298          * the use of the PPS for any pipe currentrly driving
1299          * external DP as that will mess things up on VLV.
1300          */
1301         enum pipe active_pipe;
1302         /*
1303          * Set if the sequencer may be reset due to a power transition,
1304          * requiring a reinitialization. Only relevant on BXT.
1305          */
1306         bool pps_reset;
1307         struct edp_power_seq pps_delays;
1308
1309         bool can_mst; /* this port supports mst */
1310         bool is_mst;
1311         int active_mst_links;
1312         /* connector directly attached - won't be use for modeset in mst world */
1313         struct intel_connector *attached_connector;
1314
1315         /* mst connector list */
1316         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1317         struct drm_dp_mst_topology_mgr mst_mgr;
1318
1319         u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1320         /*
1321          * This function returns the value we have to program the AUX_CTL
1322          * register with to kick off an AUX transaction.
1323          */
1324         u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1325                                 u32 aux_clock_divider);
1326
1327         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1328         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1329
1330         /* This is called before a link training is starterd */
1331         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1332
1333         /* Displayport compliance testing */
1334         struct intel_dp_compliance compliance;
1335
1336         /* Display stream compression testing */
1337         bool force_dsc_en;
1338 };
1339
1340 enum lspcon_vendor {
1341         LSPCON_VENDOR_MCA,
1342         LSPCON_VENDOR_PARADE
1343 };
1344
1345 struct intel_lspcon {
1346         bool active;
1347         enum drm_lspcon_mode mode;
1348         enum lspcon_vendor vendor;
1349 };
1350
1351 struct intel_digital_port {
1352         struct intel_encoder base;
1353         u32 saved_port_bits;
1354         struct intel_dp dp;
1355         struct intel_hdmi hdmi;
1356         struct intel_lspcon lspcon;
1357         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1358         bool release_cl2_override;
1359         u8 max_lanes;
1360         /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1361         enum aux_ch aux_ch;
1362         enum intel_display_power_domain ddi_io_power_domain;
1363         bool tc_legacy_port:1;
1364         enum tc_port_type tc_type;
1365
1366         void (*write_infoframe)(struct intel_encoder *encoder,
1367                                 const struct intel_crtc_state *crtc_state,
1368                                 unsigned int type,
1369                                 const void *frame, ssize_t len);
1370         void (*read_infoframe)(struct intel_encoder *encoder,
1371                                const struct intel_crtc_state *crtc_state,
1372                                unsigned int type,
1373                                void *frame, ssize_t len);
1374         void (*set_infoframes)(struct intel_encoder *encoder,
1375                                bool enable,
1376                                const struct intel_crtc_state *crtc_state,
1377                                const struct drm_connector_state *conn_state);
1378         u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1379                                   const struct intel_crtc_state *pipe_config);
1380 };
1381
1382 struct intel_dp_mst_encoder {
1383         struct intel_encoder base;
1384         enum pipe pipe;
1385         struct intel_digital_port *primary;
1386         struct intel_connector *connector;
1387 };
1388
1389 static inline enum dpio_channel
1390 vlv_dport_to_channel(struct intel_digital_port *dport)
1391 {
1392         switch (dport->base.port) {
1393         case PORT_B:
1394         case PORT_D:
1395                 return DPIO_CH0;
1396         case PORT_C:
1397                 return DPIO_CH1;
1398         default:
1399                 BUG();
1400         }
1401 }
1402
1403 static inline enum dpio_phy
1404 vlv_dport_to_phy(struct intel_digital_port *dport)
1405 {
1406         switch (dport->base.port) {
1407         case PORT_B:
1408         case PORT_C:
1409                 return DPIO_PHY0;
1410         case PORT_D:
1411                 return DPIO_PHY1;
1412         default:
1413                 BUG();
1414         }
1415 }
1416
1417 static inline enum dpio_channel
1418 vlv_pipe_to_channel(enum pipe pipe)
1419 {
1420         switch (pipe) {
1421         case PIPE_A:
1422         case PIPE_C:
1423                 return DPIO_CH0;
1424         case PIPE_B:
1425                 return DPIO_CH1;
1426         default:
1427                 BUG();
1428         }
1429 }
1430
1431 static inline struct intel_crtc *
1432 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1433 {
1434         return dev_priv->pipe_to_crtc_mapping[pipe];
1435 }
1436
1437 static inline struct intel_crtc *
1438 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1439 {
1440         return dev_priv->plane_to_crtc_mapping[plane];
1441 }
1442
1443 struct intel_load_detect_pipe {
1444         struct drm_atomic_state *restore_state;
1445 };
1446
1447 static inline struct intel_encoder *
1448 intel_attached_encoder(struct drm_connector *connector)
1449 {
1450         return to_intel_connector(connector)->encoder;
1451 }
1452
1453 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1454 {
1455         switch (encoder->type) {
1456         case INTEL_OUTPUT_DDI:
1457         case INTEL_OUTPUT_DP:
1458         case INTEL_OUTPUT_EDP:
1459         case INTEL_OUTPUT_HDMI:
1460                 return true;
1461         default:
1462                 return false;
1463         }
1464 }
1465
1466 static inline struct intel_digital_port *
1467 enc_to_dig_port(struct drm_encoder *encoder)
1468 {
1469         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1470
1471         if (intel_encoder_is_dig_port(intel_encoder))
1472                 return container_of(encoder, struct intel_digital_port,
1473                                     base.base);
1474         else
1475                 return NULL;
1476 }
1477
1478 static inline struct intel_digital_port *
1479 conn_to_dig_port(struct intel_connector *connector)
1480 {
1481         return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1482 }
1483
1484 static inline struct intel_dp_mst_encoder *
1485 enc_to_mst(struct drm_encoder *encoder)
1486 {
1487         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1488 }
1489
1490 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1491 {
1492         return &enc_to_dig_port(encoder)->dp;
1493 }
1494
1495 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1496 {
1497         switch (encoder->type) {
1498         case INTEL_OUTPUT_DP:
1499         case INTEL_OUTPUT_EDP:
1500                 return true;
1501         case INTEL_OUTPUT_DDI:
1502                 /* Skip pure HDMI/DVI DDI encoders */
1503                 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1504         default:
1505                 return false;
1506         }
1507 }
1508
1509 static inline struct intel_lspcon *
1510 enc_to_intel_lspcon(struct drm_encoder *encoder)
1511 {
1512         return &enc_to_dig_port(encoder)->lspcon;
1513 }
1514
1515 static inline struct intel_digital_port *
1516 dp_to_dig_port(struct intel_dp *intel_dp)
1517 {
1518         return container_of(intel_dp, struct intel_digital_port, dp);
1519 }
1520
1521 static inline struct intel_lspcon *
1522 dp_to_lspcon(struct intel_dp *intel_dp)
1523 {
1524         return &dp_to_dig_port(intel_dp)->lspcon;
1525 }
1526
1527 static inline struct drm_i915_private *
1528 dp_to_i915(struct intel_dp *intel_dp)
1529 {
1530         return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1531 }
1532
1533 static inline struct intel_digital_port *
1534 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1535 {
1536         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1537 }
1538
1539 static inline struct intel_plane_state *
1540 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1541                                  struct intel_plane *plane)
1542 {
1543         struct drm_plane_state *ret =
1544                 drm_atomic_get_plane_state(&state->base, &plane->base);
1545
1546         if (IS_ERR(ret))
1547                 return ERR_CAST(ret);
1548
1549         return to_intel_plane_state(ret);
1550 }
1551
1552 static inline struct intel_plane_state *
1553 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1554                                  struct intel_plane *plane)
1555 {
1556         return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1557                                                                    &plane->base));
1558 }
1559
1560 static inline struct intel_plane_state *
1561 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1562                                  struct intel_plane *plane)
1563 {
1564         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1565                                                                    &plane->base));
1566 }
1567
1568 static inline struct intel_crtc_state *
1569 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1570                                 struct intel_crtc *crtc)
1571 {
1572         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1573                                                                  &crtc->base));
1574 }
1575
1576 static inline struct intel_crtc_state *
1577 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1578                                 struct intel_crtc *crtc)
1579 {
1580         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1581                                                                  &crtc->base));
1582 }
1583
1584 /* intel_fifo_underrun.c */
1585 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1586                                            enum pipe pipe, bool enable);
1587 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1588                                            enum pipe pch_transcoder,
1589                                            bool enable);
1590 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1591                                          enum pipe pipe);
1592 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1593                                          enum pipe pch_transcoder);
1594 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1595 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1596
1597 /* i915_irq.c */
1598 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
1599 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
1600 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1601 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1602 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1603 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1604 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1605 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1606 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1607
1608 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1609                                             u32 mask)
1610 {
1611         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1612 }
1613
1614 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1615 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1616 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1617 {
1618         /*
1619          * We only use drm_irq_uninstall() at unload and VT switch, so
1620          * this is the only thing we need to check.
1621          */
1622         return dev_priv->runtime_pm.irqs_enabled;
1623 }
1624
1625 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1626 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1627                                      u8 pipe_mask);
1628 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1629                                      u8 pipe_mask);
1630 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1631 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1632 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1633
1634 /* intel_display.c */
1635 void intel_plane_destroy(struct drm_plane *plane);
1636 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1637 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1638 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1639 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1640 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1641                       const char *name, u32 reg, int ref_freq);
1642 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1643                            const char *name, u32 reg);
1644 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1645 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1646 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1647 unsigned int intel_fb_xy_to_linear(int x, int y,
1648                                    const struct intel_plane_state *state,
1649                                    int plane);
1650 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1651                                    int color_plane, unsigned int height);
1652 void intel_add_fb_offsets(int *x, int *y,
1653                           const struct intel_plane_state *state, int plane);
1654 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1655 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1656 void intel_mark_busy(struct drm_i915_private *dev_priv);
1657 void intel_mark_idle(struct drm_i915_private *dev_priv);
1658 int intel_display_suspend(struct drm_device *dev);
1659 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1660 void intel_encoder_destroy(struct drm_encoder *encoder);
1661 struct drm_display_mode *
1662 intel_encoder_current_mode(struct intel_encoder *encoder);
1663 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1664 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1665 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1666                               enum port port);
1667 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1668                                       struct drm_file *file_priv);
1669 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1670                                              enum pipe pipe);
1671 static inline bool
1672 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1673                     enum intel_output_type type)
1674 {
1675         return crtc_state->output_types & (1 << type);
1676 }
1677 static inline bool
1678 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1679 {
1680         return crtc_state->output_types &
1681                 ((1 << INTEL_OUTPUT_DP) |
1682                  (1 << INTEL_OUTPUT_DP_MST) |
1683                  (1 << INTEL_OUTPUT_EDP));
1684 }
1685 static inline void
1686 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1687 {
1688         drm_wait_one_vblank(&dev_priv->drm, pipe);
1689 }
1690 static inline void
1691 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1692 {
1693         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1694
1695         if (crtc->active)
1696                 intel_wait_for_vblank(dev_priv, pipe);
1697 }
1698
1699 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1700
1701 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1702 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1703                          struct intel_digital_port *dport,
1704                          unsigned int expected_mask);
1705 int intel_get_load_detect_pipe(struct drm_connector *connector,
1706                                const struct drm_display_mode *mode,
1707                                struct intel_load_detect_pipe *old,
1708                                struct drm_modeset_acquire_ctx *ctx);
1709 void intel_release_load_detect_pipe(struct drm_connector *connector,
1710                                     struct intel_load_detect_pipe *old,
1711                                     struct drm_modeset_acquire_ctx *ctx);
1712 struct i915_vma *
1713 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1714                            const struct i915_ggtt_view *view,
1715                            bool uses_fence,
1716                            unsigned long *out_flags);
1717 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1718 struct drm_framebuffer *
1719 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1720                          struct drm_mode_fb_cmd2 *mode_cmd);
1721 int intel_prepare_plane_fb(struct drm_plane *plane,
1722                            struct drm_plane_state *new_state);
1723 void intel_cleanup_plane_fb(struct drm_plane *plane,
1724                             struct drm_plane_state *old_state);
1725 int intel_plane_atomic_get_property(struct drm_plane *plane,
1726                                     const struct drm_plane_state *state,
1727                                     struct drm_property *property,
1728                                     u64 *val);
1729 int intel_plane_atomic_set_property(struct drm_plane *plane,
1730                                     struct drm_plane_state *state,
1731                                     struct drm_property *property,
1732                                     u64 val);
1733 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1734                                     struct drm_crtc_state *crtc_state,
1735                                     const struct intel_plane_state *old_plane_state,
1736                                     struct drm_plane_state *plane_state);
1737
1738 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1739                                     enum pipe pipe);
1740
1741 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1742                      const struct dpll *dpll);
1743 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1744 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1745 bool intel_fuzzy_clock_check(int clock1, int clock2);
1746
1747 /* modesetting asserts */
1748 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1749                            enum pipe pipe);
1750 void assert_pll(struct drm_i915_private *dev_priv,
1751                 enum pipe pipe, bool state);
1752 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1753 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1754 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1755 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1756 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1757 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1758                        enum pipe pipe, bool state);
1759 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1760 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1761 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1762 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1763 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1764 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1765 void intel_finish_reset(struct drm_i915_private *dev_priv);
1766 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1767 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1768 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1769 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1770 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1771 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1772 unsigned int skl_cdclk_get_vco(unsigned int freq);
1773 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1774 void intel_dp_get_m_n(struct intel_crtc *crtc,
1775                       struct intel_crtc_state *pipe_config);
1776 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1777                       enum link_m_n_set m_n);
1778 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1779 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1780                         struct dpll *best_clock);
1781 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1782
1783 bool intel_crtc_active(struct intel_crtc *crtc);
1784 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1785 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1786 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1787 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1788 enum intel_display_power_domain
1789 intel_aux_power_domain(struct intel_digital_port *dig_port);
1790 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1791                                  struct intel_crtc_state *pipe_config);
1792 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1793                                   struct intel_crtc_state *crtc_state);
1794
1795 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1796 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1797 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1798                   u32 pixel_format);
1799
1800 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1801 {
1802         return i915_ggtt_offset(state->vma);
1803 }
1804
1805 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1806                         const struct intel_plane_state *plane_state);
1807 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
1808 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1809                   const struct intel_plane_state *plane_state);
1810 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
1811 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1812                      int plane);
1813 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1814 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1815 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1816 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1817                                    u32 pixel_format, u64 modifier,
1818                                    unsigned int rotation);
1819
1820 /* intel_dp_link_training.c */
1821 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1822 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1823
1824 /* intel_vdsc.c */
1825 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
1826                                 struct intel_crtc_state *pipe_config);
1827 enum intel_display_power_domain
1828 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
1829
1830 /* intel_dp_aux_backlight.c */
1831 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1832
1833 /* intel_dp_mst.c */
1834 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1835 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1836 /* vlv_dsi.c */
1837 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1838
1839 /* icl_dsi.c */
1840 void icl_dsi_init(struct drm_i915_private *dev_priv);
1841
1842 /* intel_dsi_dcs_backlight.c */
1843 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1844
1845 /* intel_hotplug.c */
1846 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1847 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1848                            struct intel_connector *connector);
1849
1850 /* intel_overlay.c */
1851 void intel_overlay_setup(struct drm_i915_private *dev_priv);
1852 void intel_overlay_cleanup(struct drm_i915_private *dev_priv);
1853 int intel_overlay_switch_off(struct intel_overlay *overlay);
1854 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1855                                   struct drm_file *file_priv);
1856 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1857                               struct drm_file *file_priv);
1858 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1859
1860 /* intel_quirks.c */
1861 void intel_init_quirks(struct drm_i915_private *dev_priv);
1862
1863 /* intel_runtime_pm.c */
1864 void intel_runtime_pm_init_early(struct drm_i915_private *dev_priv);
1865 int intel_power_domains_init(struct drm_i915_private *);
1866 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
1867 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1868 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
1869 void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1870 void icl_display_core_uninit(struct drm_i915_private *dev_priv);
1871 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
1872 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
1873
1874 enum i915_drm_suspend_mode {
1875         I915_DRM_SUSPEND_IDLE,
1876         I915_DRM_SUSPEND_MEM,
1877         I915_DRM_SUSPEND_HIBERNATE,
1878 };
1879
1880 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
1881                                  enum i915_drm_suspend_mode);
1882 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
1883 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1884 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1885 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1886 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
1887 void intel_runtime_pm_cleanup(struct drm_i915_private *dev_priv);
1888 const char *
1889 intel_display_power_domain_str(enum intel_display_power_domain domain);
1890
1891 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1892                                     enum intel_display_power_domain domain);
1893 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1894                                       enum intel_display_power_domain domain);
1895 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
1896                                         enum intel_display_power_domain domain);
1897 intel_wakeref_t
1898 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1899                                    enum intel_display_power_domain domain);
1900 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
1901                                        enum intel_display_power_domain domain);
1902 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
1903 void intel_display_power_put(struct drm_i915_private *dev_priv,
1904                              enum intel_display_power_domain domain,
1905                              intel_wakeref_t wakeref);
1906 #else
1907 #define intel_display_power_put(i915, domain, wakeref) \
1908         intel_display_power_put_unchecked(i915, domain)
1909 #endif
1910 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
1911                             u8 req_slices);
1912
1913 static inline void
1914 assert_rpm_device_not_suspended(struct i915_runtime_pm *rpm)
1915 {
1916         WARN_ONCE(rpm->suspended,
1917                   "Device suspended during HW access\n");
1918 }
1919
1920 static inline void
1921 __assert_rpm_wakelock_held(struct i915_runtime_pm *rpm)
1922 {
1923         assert_rpm_device_not_suspended(rpm);
1924         WARN_ONCE(!atomic_read(&rpm->wakeref_count),
1925                   "RPM wakelock ref not held during HW access");
1926 }
1927
1928 static inline void
1929 assert_rpm_wakelock_held(struct drm_i915_private *i915)
1930 {
1931         __assert_rpm_wakelock_held(&i915->runtime_pm);
1932 }
1933
1934 /**
1935  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1936  * @i915: i915 device instance
1937  *
1938  * This function disable asserts that check if we hold an RPM wakelock
1939  * reference, while keeping the device-not-suspended checks still enabled.
1940  * It's meant to be used only in special circumstances where our rule about
1941  * the wakelock refcount wrt. the device power state doesn't hold. According
1942  * to this rule at any point where we access the HW or want to keep the HW in
1943  * an active state we must hold an RPM wakelock reference acquired via one of
1944  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1945  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1946  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1947  * users should avoid using this function.
1948  *
1949  * Any calls to this function must have a symmetric call to
1950  * enable_rpm_wakeref_asserts().
1951  */
1952 static inline void
1953 disable_rpm_wakeref_asserts(struct drm_i915_private *i915)
1954 {
1955         atomic_inc(&i915->runtime_pm.wakeref_count);
1956 }
1957
1958 /**
1959  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1960  * @i915: i915 device instance
1961  *
1962  * This function re-enables the RPM assert checks after disabling them with
1963  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1964  * circumstances otherwise its use should be avoided.
1965  *
1966  * Any calls to this function must have a symmetric call to
1967  * disable_rpm_wakeref_asserts().
1968  */
1969 static inline void
1970 enable_rpm_wakeref_asserts(struct drm_i915_private *i915)
1971 {
1972         atomic_dec(&i915->runtime_pm.wakeref_count);
1973 }
1974
1975 intel_wakeref_t intel_runtime_pm_get(struct drm_i915_private *i915);
1976 intel_wakeref_t intel_runtime_pm_get_if_in_use(struct drm_i915_private *i915);
1977 intel_wakeref_t intel_runtime_pm_get_noresume(struct drm_i915_private *i915);
1978
1979 #define with_intel_runtime_pm(i915, wf) \
1980         for ((wf) = intel_runtime_pm_get(i915); (wf); \
1981              intel_runtime_pm_put((i915), (wf)), (wf) = 0)
1982
1983 #define with_intel_runtime_pm_if_in_use(i915, wf) \
1984         for ((wf) = intel_runtime_pm_get_if_in_use(i915); (wf); \
1985              intel_runtime_pm_put((i915), (wf)), (wf) = 0)
1986
1987 void intel_runtime_pm_put_unchecked(struct drm_i915_private *i915);
1988 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
1989 void intel_runtime_pm_put(struct drm_i915_private *i915, intel_wakeref_t wref);
1990 #else
1991 #define intel_runtime_pm_put(i915, wref) intel_runtime_pm_put_unchecked(i915)
1992 #endif
1993
1994 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
1995 void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
1996                                     struct drm_printer *p);
1997 #else
1998 static inline void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
1999                                                   struct drm_printer *p)
2000 {
2001 }
2002 #endif
2003
2004 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2005                              bool override, unsigned int mask);
2006 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2007                           enum dpio_channel ch, bool override);
2008
2009 /* intel_atomic.c */
2010 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2011                                                 const struct drm_connector_state *state,
2012                                                 struct drm_property *property,
2013                                                 u64 *val);
2014 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2015                                                 struct drm_connector_state *state,
2016                                                 struct drm_property *property,
2017                                                 u64 val);
2018 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2019                                          struct drm_connector_state *new_state);
2020 struct drm_connector_state *
2021 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2022
2023 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2024 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2025                                struct drm_crtc_state *state);
2026 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2027 void intel_atomic_state_clear(struct drm_atomic_state *);
2028
2029 static inline struct intel_crtc_state *
2030 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2031                             struct intel_crtc *crtc)
2032 {
2033         struct drm_crtc_state *crtc_state;
2034         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2035         if (IS_ERR(crtc_state))
2036                 return ERR_CAST(crtc_state);
2037
2038         return to_intel_crtc_state(crtc_state);
2039 }
2040
2041 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2042                                struct intel_crtc *intel_crtc,
2043                                struct intel_crtc_state *crtc_state);
2044
2045 #endif /* __INTEL_DRV_H__ */