2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <linux/stackdepot.h>
33 #include <drm/i915_drm.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_probe_helper.h>
41 #include <drm/drm_rect.h>
42 #include <drm/drm_vblank.h>
43 #include <drm/drm_atomic.h>
44 #include <media/cec-notifier.h>
49 * __wait_for - magic wait macro
51 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
52 * important that we check the condition again after having timed out, since the
53 * timeout could be due to preemption or similar and we've never had a chance to
54 * check the condition before the timeout.
56 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
57 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
58 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
62 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
64 /* Guarantee COND check prior to timeout */ \
74 usleep_range(wait__, wait__ * 2); \
75 if (wait__ < (Wmax)) \
81 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
83 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
85 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
86 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
87 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
89 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
92 #define _wait_for_atomic(COND, US, ATOMIC) \
94 int cpu, ret, timeout = (US) * 1000; \
96 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
99 cpu = smp_processor_id(); \
101 base = local_clock(); \
103 u64 now = local_clock(); \
106 /* Guarantee COND check prior to timeout */ \
112 if (now - base >= timeout) { \
119 if (unlikely(cpu != smp_processor_id())) { \
120 timeout -= now - base; \
121 cpu = smp_processor_id(); \
122 base = local_clock(); \
129 #define wait_for_us(COND, US) \
132 BUILD_BUG_ON(!__builtin_constant_p(US)); \
134 ret__ = _wait_for((COND), (US), 10, 10); \
136 ret__ = _wait_for_atomic((COND), (US), 0); \
140 #define wait_for_atomic_us(COND, US) \
142 BUILD_BUG_ON(!__builtin_constant_p(US)); \
143 BUILD_BUG_ON((US) > 50000); \
144 _wait_for_atomic((COND), (US), 1); \
147 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
149 #define KHz(x) (1000 * (x))
150 #define MHz(x) KHz(1000 * (x))
152 #define KBps(x) (1000 * (x))
153 #define MBps(x) KBps(1000 * (x))
154 #define GBps(x) ((u64)1000 * MBps((x)))
157 * Display related stuff
160 /* store information about an Ixxx DVO */
161 /* The i830->i865 use multiple DVOs with multiple i2cs */
162 /* the i915, i945 have a single sDVO i2c bus - which is different */
163 #define MAX_OUTPUTS 6
164 /* maximum connectors per crtcs in the mode set */
166 #define INTEL_I2C_BUS_DVO 1
167 #define INTEL_I2C_BUS_SDVO 2
169 /* these are outputs from the chip - integrated only
170 external chips are via DVO or SDVO output */
171 enum intel_output_type {
172 INTEL_OUTPUT_UNUSED = 0,
173 INTEL_OUTPUT_ANALOG = 1,
174 INTEL_OUTPUT_DVO = 2,
175 INTEL_OUTPUT_SDVO = 3,
176 INTEL_OUTPUT_LVDS = 4,
177 INTEL_OUTPUT_TVOUT = 5,
178 INTEL_OUTPUT_HDMI = 6,
180 INTEL_OUTPUT_EDP = 8,
181 INTEL_OUTPUT_DSI = 9,
182 INTEL_OUTPUT_DDI = 10,
183 INTEL_OUTPUT_DP_MST = 11,
186 #define INTEL_DVO_CHIP_NONE 0
187 #define INTEL_DVO_CHIP_LVDS 1
188 #define INTEL_DVO_CHIP_TMDS 2
189 #define INTEL_DVO_CHIP_TVOUT 4
191 #define INTEL_DSI_VIDEO_MODE 0
192 #define INTEL_DSI_COMMAND_MODE 1
194 struct intel_framebuffer {
195 struct drm_framebuffer base;
196 struct intel_rotation_info rot_info;
198 /* for each plane in the normal GTT view */
202 /* for each plane in the rotated GTT view */
205 unsigned int pitch; /* pixels */
210 struct drm_fb_helper helper;
211 struct intel_framebuffer *fb;
212 struct i915_vma *vma;
213 unsigned long vma_flags;
214 async_cookie_t cookie;
217 /* Whether or not fbdev hpd processing is temporarily suspended */
218 bool hpd_suspended : 1;
219 /* Set when a hotplug was received while HPD processing was
222 bool hpd_waiting : 1;
224 /* Protects hpd_suspended */
225 struct mutex hpd_lock;
228 struct intel_encoder {
229 struct drm_encoder base;
231 enum intel_output_type type;
233 unsigned int cloneable;
234 bool (*hotplug)(struct intel_encoder *encoder,
235 struct intel_connector *connector);
236 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
237 struct intel_crtc_state *,
238 struct drm_connector_state *);
239 int (*compute_config)(struct intel_encoder *,
240 struct intel_crtc_state *,
241 struct drm_connector_state *);
242 void (*pre_pll_enable)(struct intel_encoder *,
243 const struct intel_crtc_state *,
244 const struct drm_connector_state *);
245 void (*pre_enable)(struct intel_encoder *,
246 const struct intel_crtc_state *,
247 const struct drm_connector_state *);
248 void (*enable)(struct intel_encoder *,
249 const struct intel_crtc_state *,
250 const struct drm_connector_state *);
251 void (*disable)(struct intel_encoder *,
252 const struct intel_crtc_state *,
253 const struct drm_connector_state *);
254 void (*post_disable)(struct intel_encoder *,
255 const struct intel_crtc_state *,
256 const struct drm_connector_state *);
257 void (*post_pll_disable)(struct intel_encoder *,
258 const struct intel_crtc_state *,
259 const struct drm_connector_state *);
260 void (*update_pipe)(struct intel_encoder *,
261 const struct intel_crtc_state *,
262 const struct drm_connector_state *);
263 /* Read out the current hw state of this connector, returning true if
264 * the encoder is active. If the encoder is enabled it also set the pipe
265 * it is connected to in the pipe parameter. */
266 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
267 /* Reconstructs the equivalent mode flags for the current hardware
268 * state. This must be called _after_ display->get_pipe_config has
269 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
270 * be set correctly before calling this function. */
271 void (*get_config)(struct intel_encoder *,
272 struct intel_crtc_state *pipe_config);
273 /* Returns a mask of power domains that need to be referenced as part
274 * of the hardware state readout code. */
275 u64 (*get_power_domains)(struct intel_encoder *encoder,
276 struct intel_crtc_state *crtc_state);
278 * Called during system suspend after all pending requests for the
279 * encoder are flushed (for example for DP AUX transactions) and
280 * device interrupts are disabled.
282 void (*suspend)(struct intel_encoder *);
284 enum hpd_pin hpd_pin;
285 enum intel_display_power_domain power_domain;
286 /* for communication with audio component; protected by av_mutex */
287 const struct drm_connector *audio_connector;
291 struct drm_display_mode *fixed_mode;
292 struct drm_display_mode *downclock_mode;
301 bool combination_mode; /* gen 2/4 only */
303 bool alternate_pwm_increment; /* lpt+ */
306 bool util_pin_active_low; /* bxt+ */
307 u8 controller; /* bxt+ only */
308 struct pwm_device *pwm;
310 struct backlight_device *device;
312 /* Connector and platform specific backlight functions */
313 int (*setup)(struct intel_connector *connector, enum pipe pipe);
314 u32 (*get)(struct intel_connector *connector);
315 void (*set)(const struct drm_connector_state *conn_state, u32 level);
316 void (*disable)(const struct drm_connector_state *conn_state);
317 void (*enable)(const struct intel_crtc_state *crtc_state,
318 const struct drm_connector_state *conn_state);
319 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
320 void (*power)(struct intel_connector *, bool enable);
324 struct intel_digital_port;
327 * This structure serves as a translation layer between the generic HDCP code
328 * and the bus-specific code. What that means is that HDCP over HDMI differs
329 * from HDCP over DP, so to account for these differences, we need to
330 * communicate with the receiver through this shim.
332 * For completeness, the 2 buses differ in the following ways:
334 * HDCP registers on the receiver are set via DP AUX for DP, and
335 * they are set via DDC for HDMI.
336 * - Receiver register offsets
337 * The offsets of the registers are different for DP vs. HDMI
338 * - Receiver register masks/offsets
339 * For instance, the ready bit for the KSV fifo is in a different
340 * place on DP vs HDMI
341 * - Receiver register names
342 * Seriously. In the DP spec, the 16-bit register containing
343 * downstream information is called BINFO, on HDMI it's called
344 * BSTATUS. To confuse matters further, DP has a BSTATUS register
345 * with a completely different definition.
347 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
348 * be read 3 keys at a time
350 * Since Aksv is hidden in hardware, there's different procedures
351 * to send it over DP AUX vs DDC
353 struct intel_hdcp_shim {
354 /* Outputs the transmitter's An and Aksv values to the receiver. */
355 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
357 /* Reads the receiver's key selection vector */
358 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
361 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
362 * definitions are the same in the respective specs, but the names are
363 * different. Call it BSTATUS since that's the name the HDMI spec
364 * uses and it was there first.
366 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
369 /* Determines whether a repeater is present downstream */
370 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
371 bool *repeater_present);
373 /* Reads the receiver's Ri' value */
374 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
376 /* Determines if the receiver's KSV FIFO is ready for consumption */
377 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
380 /* Reads the ksv fifo for num_downstream devices */
381 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
382 int num_downstream, u8 *ksv_fifo);
384 /* Reads a 32-bit part of V' from the receiver */
385 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
388 /* Enables HDCP signalling on the port */
389 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
392 /* Ensures the link is still protected */
393 bool (*check_link)(struct intel_digital_port *intel_dig_port);
395 /* Detects panel's hdcp capability. This is optional for HDMI. */
396 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
401 const struct intel_hdcp_shim *shim;
402 /* Mutex for hdcp state of the connector */
405 struct delayed_work check_work;
406 struct work_struct prop_work;
409 struct intel_connector {
410 struct drm_connector base;
412 * The fixed encoder this connector is connected to.
414 struct intel_encoder *encoder;
416 /* ACPI device id for ACPI and driver cooperation */
419 /* Reads out the current hw, returning true if the connector is enabled
420 * and active (i.e. dpms ON state). */
421 bool (*get_hw_state)(struct intel_connector *);
423 /* Panel info for eDP and LVDS */
424 struct intel_panel panel;
426 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
428 struct edid *detect_edid;
430 /* since POLL and HPD connectors may use the same HPD line keep the native
431 state of connector->polled in case hotplug storm detection changes it */
434 void *port; /* store this opaque as its illegal to dereference it */
436 struct intel_dp *mst_port;
438 /* Work struct to schedule a uevent on link train failure */
439 struct work_struct modeset_retry_work;
441 struct intel_hdcp hdcp;
444 struct intel_digital_connector_state {
445 struct drm_connector_state base;
447 enum hdmi_force_audio force_audio;
451 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
465 struct intel_atomic_state {
466 struct drm_atomic_state base;
470 * Logical state of cdclk (used for all scaling, watermark,
471 * etc. calculations and checks). This is computed as if all
472 * enabled crtcs were active.
474 struct intel_cdclk_state logical;
477 * Actual state of cdclk, can be different from the logical
478 * state only when all crtc's are DPMS off.
480 struct intel_cdclk_state actual;
483 bool dpll_set, modeset;
486 * Does this transaction change the pipes that are active? This mask
487 * tracks which CRTC's have changed their active state at the end of
488 * the transaction (not counting the temporary disable during modesets).
489 * This mask should only be non-zero when intel_state->modeset is true,
490 * but the converse is not necessarily true; simply changing a mode may
491 * not flip the final active status of any CRTC's
493 unsigned int active_pipe_changes;
495 unsigned int active_crtcs;
496 /* minimum acceptable cdclk for each pipe */
497 int min_cdclk[I915_MAX_PIPES];
498 /* minimum acceptable voltage level for each pipe */
499 u8 min_voltage_level[I915_MAX_PIPES];
501 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
504 * Current watermarks can't be trusted during hardware readout, so
505 * don't bother calculating intermediate watermarks.
507 bool skip_intermediate_wm;
509 bool rps_interactive;
512 struct skl_ddb_values wm_results;
514 struct i915_sw_fence commit_ready;
516 struct llist_node freed;
519 struct intel_plane_state {
520 struct drm_plane_state base;
521 struct i915_ggtt_view view;
522 struct i915_vma *vma;
524 #define PLANE_HAS_FENCE BIT(0)
530 * bytes for 0/180 degree rotation
531 * pixels for 90/270 degree rotation
537 /* plane control register */
540 /* plane color control register */
545 * = -1 : not using a scaler
546 * >= 0 : using a scalers
548 * plane requiring a scaler:
549 * - During check_plane, its bit is set in
550 * crtc_state->scaler_state.scaler_users by calling helper function
551 * update_scaler_plane.
552 * - scaler_id indicates the scaler it got assigned.
554 * plane doesn't require a scaler:
555 * - this can happen when scaling is no more required or plane simply
557 * - During check_plane, corresponding bit is reset in
558 * crtc_state->scaler_state.scaler_users by calling helper function
559 * update_scaler_plane.
566 * ICL planar formats require 2 planes that are updated as pairs.
567 * This member is used to make sure the other plane is also updated
568 * when required, and for update_slave() to find the correct
569 * plane_state to pass as argument.
571 struct intel_plane *linked_plane;
575 * If set don't update use the linked plane's state for updating
576 * this plane during atomic commit with the update_slave() callback.
578 * It's also used by the watermark code to ignore wm calculations on
579 * this plane. They're calculated by the linked plane's wm code.
583 struct drm_intel_sprite_colorkey ckey;
586 struct intel_initial_plane_config {
587 struct intel_framebuffer *fb;
594 #define SKL_MIN_SRC_W 8
595 #define SKL_MAX_SRC_W 4096
596 #define SKL_MIN_SRC_H 8
597 #define SKL_MAX_SRC_H 4096
598 #define SKL_MIN_DST_W 8
599 #define SKL_MAX_DST_W 4096
600 #define SKL_MIN_DST_H 8
601 #define SKL_MAX_DST_H 4096
602 #define ICL_MAX_SRC_W 5120
603 #define ICL_MAX_SRC_H 4096
604 #define ICL_MAX_DST_W 5120
605 #define ICL_MAX_DST_H 4096
606 #define SKL_MIN_YUV_420_SRC_W 16
607 #define SKL_MIN_YUV_420_SRC_H 16
609 struct intel_scaler {
614 struct intel_crtc_scaler_state {
615 #define SKL_NUM_SCALERS 2
616 struct intel_scaler scalers[SKL_NUM_SCALERS];
619 * scaler_users: keeps track of users requesting scalers on this crtc.
621 * If a bit is set, a user is using a scaler.
622 * Here user can be a plane or crtc as defined below:
623 * bits 0-30 - plane (bit position is index from drm_plane_index)
626 * Instead of creating a new index to cover planes and crtc, using
627 * existing drm_plane_index for planes which is well less than 31
628 * planes and bit 31 for crtc. This should be fine to cover all
631 * intel_atomic_setup_scalers will setup available scalers to users
632 * requesting scalers. It will gracefully fail if request exceeds
635 #define SKL_CRTC_INDEX 31
636 unsigned scaler_users;
638 /* scaler used by crtc for panel fitting purpose */
642 /* drm_mode->private_flags */
643 #define I915_MODE_FLAG_INHERITED (1<<0)
644 /* Flag to get scanline using frame time stamps */
645 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
646 /* Flag to use the scanline counter instead of the pixel counter */
647 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
649 struct intel_pipe_wm {
650 struct intel_wm_level wm[5];
654 bool sprites_enabled;
658 struct skl_plane_wm {
659 struct skl_wm_level wm[8];
660 struct skl_wm_level uv_wm[8];
661 struct skl_wm_level trans_wm;
666 struct skl_plane_wm planes[I915_MAX_PLANES];
673 VLV_WM_LEVEL_DDR_DVFS,
677 struct vlv_wm_state {
678 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
679 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
684 struct vlv_fifo_state {
685 u16 plane[I915_MAX_PLANES];
695 struct g4x_wm_state {
696 struct g4x_pipe_wm wm;
698 struct g4x_sr_wm hpll;
704 struct intel_crtc_wm_state {
708 * Intermediate watermarks; these can be
709 * programmed immediately since they satisfy
710 * both the current configuration we're
711 * switching away from and the new
712 * configuration we're switching to.
714 struct intel_pipe_wm intermediate;
717 * Optimal watermarks, programmed post-vblank
718 * when this state is committed.
720 struct intel_pipe_wm optimal;
724 /* gen9+ only needs 1-step wm programming */
725 struct skl_pipe_wm optimal;
726 struct skl_ddb_entry ddb;
727 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
728 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
732 /* "raw" watermarks (not inverted) */
733 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
734 /* intermediate watermarks (inverted) */
735 struct vlv_wm_state intermediate;
736 /* optimal watermarks (inverted) */
737 struct vlv_wm_state optimal;
738 /* display FIFO split */
739 struct vlv_fifo_state fifo_state;
743 /* "raw" watermarks */
744 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
745 /* intermediate watermarks */
746 struct g4x_wm_state intermediate;
747 /* optimal watermarks */
748 struct g4x_wm_state optimal;
753 * Platforms with two-step watermark programming will need to
754 * update watermark programming post-vblank to switch from the
755 * safe intermediate watermarks to the optimal final
758 bool need_postvbl_update;
761 enum intel_output_format {
762 INTEL_OUTPUT_FORMAT_INVALID,
763 INTEL_OUTPUT_FORMAT_RGB,
764 INTEL_OUTPUT_FORMAT_YCBCR420,
765 INTEL_OUTPUT_FORMAT_YCBCR444,
768 struct intel_crtc_state {
769 struct drm_crtc_state base;
772 * quirks - bitfield with hw state readout quirks
774 * For various reasons the hw state readout code might not be able to
775 * completely faithfully read out the current state. These cases are
776 * tracked with quirk flags so that fastboot and state checker can act
779 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
780 unsigned long quirks;
782 unsigned fb_bits; /* framebuffers to flip */
783 bool update_pipe; /* can a fast modeset be performed? */
785 bool update_wm_pre, update_wm_post; /* watermarks are updated */
786 bool fb_changed; /* fb on any of the planes is changed */
787 bool fifo_changed; /* FIFO split is changed */
789 /* Pipe source size (ie. panel fitter input size)
790 * All planes will be positioned inside this space,
791 * and get clipped at the edges. */
792 int pipe_src_w, pipe_src_h;
795 * Pipe pixel rate, adjusted for
796 * panel fitter/pipe scaler downscaling.
798 unsigned int pixel_rate;
800 /* Whether to set up the PCH/FDI. Note that we never allow sharing
801 * between pch encoders and cpu encoders. */
802 bool has_pch_encoder;
804 /* Are we sending infoframes on the attached port */
807 /* CPU Transcoder for the pipe. Currently this can only differ from the
808 * pipe on Haswell and later (where we have a special eDP transcoder)
809 * and Broxton (where we have special DSI transcoders). */
810 enum transcoder cpu_transcoder;
813 * Use reduced/limited/broadcast rbg range, compressing from the full
814 * range fed into the crtcs.
816 bool limited_color_range;
818 /* Bitmask of encoder types (enum intel_output_type)
819 * driven by the pipe.
821 unsigned int output_types;
823 /* Whether we should send NULL infoframes. Required for audio. */
826 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
827 * has_dp_encoder is set. */
831 * Enable dithering, used when the selected pipe bpp doesn't match the
837 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
838 * compliance video pattern tests.
839 * Disable dither only if it is a compliance test request for
842 bool dither_force_disable;
844 /* Controls for the clock computation, to override various stages. */
847 /* SDVO TV has a bunch of special case. To make multifunction encoders
848 * work correctly, we need to track this at runtime.*/
852 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
853 * required. This is set in the 2nd loop of calling encoder's
854 * ->compute_config if the first pick doesn't work out.
858 /* Settings for the intel dpll used on pretty much everything but
862 /* Selected dpll when shared or NULL. */
863 struct intel_shared_dpll *shared_dpll;
865 /* Actual register state of the dpll, for shared dpll cross-checking. */
866 struct intel_dpll_hw_state dpll_hw_state;
868 /* DSI PLL registers */
874 struct intel_link_m_n dp_m_n;
876 /* m2_n2 for eDP downclock */
877 struct intel_link_m_n dp_m2_n2;
884 * Frequence the dpll for the port should run at. Differs from the
885 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
886 * already multiplied by pixel_multiplier.
890 /* Used by SDVO (and if we ever fix it, HDMI). */
891 unsigned pixel_multiplier;
896 * Used by platforms having DP/HDMI PHY with programmable lane
897 * latency optimization.
899 u8 lane_lat_optim_mask;
901 /* minimum acceptable voltage level */
902 u8 min_voltage_level;
904 /* Panel fitter controls for gen2-gen4 + VLV */
908 u32 lvds_border_bits;
911 /* Panel fitter placement and size for Ironlake+ */
919 /* FDI configuration, only valid if has_pch_encoder is set. */
921 struct intel_link_m_n fdi_m_n;
924 bool ips_force_disable;
932 struct intel_crtc_scaler_state scaler_state;
934 /* w/a for waiting 2 vblanks during crtc enable */
935 enum pipe hsw_workaround_pipe;
937 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
940 struct intel_crtc_wm_state wm;
942 /* Gamma mode programmed on the pipe */
945 /* bitmask of visible planes (enum plane_id) */
949 /* bitmask of planes that will be updated during the commit */
952 /* HDMI scrambling status */
953 bool hdmi_scrambling;
955 /* HDMI High TMDS char rate ratio */
956 bool hdmi_high_tmds_clock_ratio;
958 /* Output format RGB/YCBCR etc */
959 enum intel_output_format output_format;
961 /* Output down scaling is done in LSPCON device */
962 bool lspcon_downsampling;
964 /* Display Stream compression state */
966 bool compression_enable;
971 struct drm_dsc_config dp_dsc_cfg;
973 /* Forward Error correction State */
978 struct drm_crtc base;
981 * Whether the crtc and the connected output pipeline is active. Implies
982 * that crtc->enabled is set, i.e. the current mode configuration has
983 * some outputs connected to this crtc.
987 unsigned long long enabled_power_domains;
988 struct intel_overlay *overlay;
990 struct intel_crtc_state *config;
992 /* global reset count when the last flip was submitted */
993 unsigned int reset_count;
995 /* Access to these should be protected by dev_priv->irq_lock. */
996 bool cpu_fifo_underrun_disabled;
997 bool pch_fifo_underrun_disabled;
999 /* per-pipe watermark state */
1001 /* watermarks currently being used */
1003 struct intel_pipe_wm ilk;
1004 struct vlv_wm_state vlv;
1005 struct g4x_wm_state g4x;
1009 int scanline_offset;
1012 unsigned start_vbl_count;
1013 ktime_t start_vbl_time;
1014 int min_vbl, max_vbl;
1018 /* scalers available on this crtc */
1022 struct intel_plane {
1023 struct drm_plane base;
1024 enum i9xx_plane_id i9xx_plane;
1029 u32 frontbuffer_bit;
1032 u32 base, cntl, size;
1036 * NOTE: Do not place new plane state fields here (e.g., when adding
1037 * new plane properties). New runtime state should now be placed in
1038 * the intel_plane_state structure and accessed via plane_state.
1041 unsigned int (*max_stride)(struct intel_plane *plane,
1042 u32 pixel_format, u64 modifier,
1043 unsigned int rotation);
1044 void (*update_plane)(struct intel_plane *plane,
1045 const struct intel_crtc_state *crtc_state,
1046 const struct intel_plane_state *plane_state);
1047 void (*update_slave)(struct intel_plane *plane,
1048 const struct intel_crtc_state *crtc_state,
1049 const struct intel_plane_state *plane_state);
1050 void (*disable_plane)(struct intel_plane *plane,
1051 const struct intel_crtc_state *crtc_state);
1052 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1053 int (*check_plane)(struct intel_crtc_state *crtc_state,
1054 struct intel_plane_state *plane_state);
1057 struct intel_watermark_params {
1065 struct cxsr_latency {
1066 bool is_desktop : 1;
1071 u16 display_hpll_disable;
1073 u16 cursor_hpll_disable;
1076 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1077 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1078 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1079 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1080 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1081 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1082 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1083 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1084 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1087 i915_reg_t hdmi_reg;
1090 enum drm_dp_dual_mode_type type;
1095 struct intel_connector *attached_connector;
1096 struct cec_notifier *cec_notifier;
1099 struct intel_dp_mst_encoder;
1100 #define DP_MAX_DOWNSTREAM_PORTS 0x10
1103 * enum link_m_n_set:
1104 * When platform provides two set of M_N registers for dp, we can
1105 * program them and switch between them incase of DRRS.
1106 * But When only one such register is provided, we have to program the
1107 * required divider value on that registers itself based on the DRRS state.
1109 * M1_N1 : Program dp_m_n on M1_N1 registers
1110 * dp_m2_n2 on M2_N2 registers (If supported)
1112 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1113 * M2_N2 registers are not supported
1117 /* Sets the m1_n1 and m2_n2 */
1122 struct intel_dp_compliance_data {
1125 u16 hdisplay, vdisplay;
1129 struct intel_dp_compliance {
1130 unsigned long test_type;
1131 struct intel_dp_compliance_data test_data;
1138 i915_reg_t output_reg;
1146 bool reset_link_params;
1147 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1148 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1149 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1150 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1151 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1154 int num_source_rates;
1155 const int *source_rates;
1156 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1158 int sink_rates[DP_MAX_SUPPORTED_RATES];
1159 bool use_rate_select;
1160 /* intersection of source and sink rates */
1161 int num_common_rates;
1162 int common_rates[DP_MAX_SUPPORTED_RATES];
1163 /* Max lane count for the current link */
1164 int max_link_lane_count;
1165 /* Max rate for the current link */
1167 /* sink or branch descriptor */
1168 struct drm_dp_desc desc;
1169 struct drm_dp_aux aux;
1171 int panel_power_up_delay;
1172 int panel_power_down_delay;
1173 int panel_power_cycle_delay;
1174 int backlight_on_delay;
1175 int backlight_off_delay;
1176 struct delayed_work panel_vdd_work;
1177 bool want_panel_vdd;
1178 unsigned long last_power_on;
1179 unsigned long last_backlight_off;
1180 ktime_t panel_power_off_time;
1182 struct notifier_block edp_notifier;
1185 * Pipe whose power sequencer is currently locked into
1186 * this port. Only relevant on VLV/CHV.
1190 * Pipe currently driving the port. Used for preventing
1191 * the use of the PPS for any pipe currentrly driving
1192 * external DP as that will mess things up on VLV.
1194 enum pipe active_pipe;
1196 * Set if the sequencer may be reset due to a power transition,
1197 * requiring a reinitialization. Only relevant on BXT.
1200 struct edp_power_seq pps_delays;
1202 bool can_mst; /* this port supports mst */
1204 int active_mst_links;
1205 /* connector directly attached - won't be use for modeset in mst world */
1206 struct intel_connector *attached_connector;
1208 /* mst connector list */
1209 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1210 struct drm_dp_mst_topology_mgr mst_mgr;
1212 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1214 * This function returns the value we have to program the AUX_CTL
1215 * register with to kick off an AUX transaction.
1217 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1218 u32 aux_clock_divider);
1220 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1221 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1223 /* This is called before a link training is starterd */
1224 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1226 /* Displayport compliance testing */
1227 struct intel_dp_compliance compliance;
1229 /* Display stream compression testing */
1233 enum lspcon_vendor {
1235 LSPCON_VENDOR_PARADE
1238 struct intel_lspcon {
1240 enum drm_lspcon_mode mode;
1241 enum lspcon_vendor vendor;
1244 struct intel_digital_port {
1245 struct intel_encoder base;
1246 u32 saved_port_bits;
1248 struct intel_hdmi hdmi;
1249 struct intel_lspcon lspcon;
1250 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1251 bool release_cl2_override;
1253 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1255 enum intel_display_power_domain ddi_io_power_domain;
1256 bool tc_legacy_port:1;
1257 enum tc_port_type tc_type;
1259 void (*write_infoframe)(struct intel_encoder *encoder,
1260 const struct intel_crtc_state *crtc_state,
1262 const void *frame, ssize_t len);
1263 void (*set_infoframes)(struct intel_encoder *encoder,
1265 const struct intel_crtc_state *crtc_state,
1266 const struct drm_connector_state *conn_state);
1267 bool (*infoframe_enabled)(struct intel_encoder *encoder,
1268 const struct intel_crtc_state *pipe_config);
1271 struct intel_dp_mst_encoder {
1272 struct intel_encoder base;
1274 struct intel_digital_port *primary;
1275 struct intel_connector *connector;
1278 static inline enum dpio_channel
1279 vlv_dport_to_channel(struct intel_digital_port *dport)
1281 switch (dport->base.port) {
1292 static inline enum dpio_phy
1293 vlv_dport_to_phy(struct intel_digital_port *dport)
1295 switch (dport->base.port) {
1306 static inline enum dpio_channel
1307 vlv_pipe_to_channel(enum pipe pipe)
1320 static inline struct intel_crtc *
1321 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1323 return dev_priv->pipe_to_crtc_mapping[pipe];
1326 static inline struct intel_crtc *
1327 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1329 return dev_priv->plane_to_crtc_mapping[plane];
1332 struct intel_load_detect_pipe {
1333 struct drm_atomic_state *restore_state;
1336 static inline struct intel_encoder *
1337 intel_attached_encoder(struct drm_connector *connector)
1339 return to_intel_connector(connector)->encoder;
1342 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1344 switch (encoder->type) {
1345 case INTEL_OUTPUT_DDI:
1346 case INTEL_OUTPUT_DP:
1347 case INTEL_OUTPUT_EDP:
1348 case INTEL_OUTPUT_HDMI:
1355 static inline struct intel_digital_port *
1356 enc_to_dig_port(struct drm_encoder *encoder)
1358 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1360 if (intel_encoder_is_dig_port(intel_encoder))
1361 return container_of(encoder, struct intel_digital_port,
1367 static inline struct intel_digital_port *
1368 conn_to_dig_port(struct intel_connector *connector)
1370 return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1373 static inline struct intel_dp_mst_encoder *
1374 enc_to_mst(struct drm_encoder *encoder)
1376 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1379 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1381 return &enc_to_dig_port(encoder)->dp;
1384 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1386 switch (encoder->type) {
1387 case INTEL_OUTPUT_DP:
1388 case INTEL_OUTPUT_EDP:
1390 case INTEL_OUTPUT_DDI:
1391 /* Skip pure HDMI/DVI DDI encoders */
1392 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1398 static inline struct intel_lspcon *
1399 enc_to_intel_lspcon(struct drm_encoder *encoder)
1401 return &enc_to_dig_port(encoder)->lspcon;
1404 static inline struct intel_digital_port *
1405 dp_to_dig_port(struct intel_dp *intel_dp)
1407 return container_of(intel_dp, struct intel_digital_port, dp);
1410 static inline struct intel_lspcon *
1411 dp_to_lspcon(struct intel_dp *intel_dp)
1413 return &dp_to_dig_port(intel_dp)->lspcon;
1416 static inline struct drm_i915_private *
1417 dp_to_i915(struct intel_dp *intel_dp)
1419 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1422 static inline struct intel_digital_port *
1423 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1425 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1428 static inline struct intel_plane_state *
1429 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1430 struct intel_plane *plane)
1432 struct drm_plane_state *ret =
1433 drm_atomic_get_plane_state(&state->base, &plane->base);
1436 return ERR_CAST(ret);
1438 return to_intel_plane_state(ret);
1441 static inline struct intel_plane_state *
1442 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1443 struct intel_plane *plane)
1445 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1449 static inline struct intel_plane_state *
1450 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1451 struct intel_plane *plane)
1453 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1457 static inline struct intel_crtc_state *
1458 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1459 struct intel_crtc *crtc)
1461 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1465 static inline struct intel_crtc_state *
1466 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1467 struct intel_crtc *crtc)
1469 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1473 /* intel_fifo_underrun.c */
1474 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1475 enum pipe pipe, bool enable);
1476 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1477 enum pipe pch_transcoder,
1479 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1481 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1482 enum pipe pch_transcoder);
1483 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1484 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1487 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
1488 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
1489 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1490 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1491 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1492 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1493 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1494 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1496 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1499 return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1502 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1503 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1504 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1507 * We only use drm_irq_uninstall() at unload and VT switch, so
1508 * this is the only thing we need to check.
1510 return dev_priv->runtime_pm.irqs_enabled;
1513 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1514 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1516 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1518 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1519 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1520 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1523 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1524 i915_reg_t adpa_reg, enum pipe *pipe);
1525 void intel_crt_init(struct drm_i915_private *dev_priv);
1526 void intel_crt_reset(struct drm_encoder *encoder);
1529 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1530 const struct intel_crtc_state *old_crtc_state,
1531 const struct drm_connector_state *old_conn_state);
1532 void hsw_fdi_link_train(struct intel_crtc *crtc,
1533 const struct intel_crtc_state *crtc_state);
1534 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1535 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1536 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1537 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1538 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1539 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
1540 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1541 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1542 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1543 void intel_ddi_get_config(struct intel_encoder *encoder,
1544 struct intel_crtc_state *pipe_config);
1546 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1548 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1549 struct intel_crtc_state *crtc_state);
1550 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1551 u32 ddi_signal_levels(struct intel_dp *intel_dp);
1552 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1553 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1555 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1557 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
1558 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1559 enum intel_dpll_id pll_id);
1561 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1562 int color_plane, unsigned int height);
1565 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1566 void intel_audio_codec_enable(struct intel_encoder *encoder,
1567 const struct intel_crtc_state *crtc_state,
1568 const struct drm_connector_state *conn_state);
1569 void intel_audio_codec_disable(struct intel_encoder *encoder,
1570 const struct intel_crtc_state *old_crtc_state,
1571 const struct drm_connector_state *old_conn_state);
1572 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1573 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1574 void intel_audio_init(struct drm_i915_private *dev_priv);
1575 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1578 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1579 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1580 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1581 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1582 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1583 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1584 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1585 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1586 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1587 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1588 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1589 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1590 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1591 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1592 const struct intel_cdclk_state *b);
1593 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1594 const struct intel_cdclk_state *b);
1595 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1596 const struct intel_cdclk_state *cdclk_state);
1597 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1598 const char *context);
1600 /* intel_display.c */
1601 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1602 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1603 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1604 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1605 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1606 const char *name, u32 reg, int ref_freq);
1607 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1608 const char *name, u32 reg);
1609 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1610 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1611 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1612 unsigned int intel_fb_xy_to_linear(int x, int y,
1613 const struct intel_plane_state *state,
1615 void intel_add_fb_offsets(int *x, int *y,
1616 const struct intel_plane_state *state, int plane);
1617 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1618 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1619 void intel_mark_busy(struct drm_i915_private *dev_priv);
1620 void intel_mark_idle(struct drm_i915_private *dev_priv);
1621 int intel_display_suspend(struct drm_device *dev);
1622 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1623 void intel_encoder_destroy(struct drm_encoder *encoder);
1624 struct drm_display_mode *
1625 intel_encoder_current_mode(struct intel_encoder *encoder);
1626 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1627 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1628 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1630 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1631 struct drm_file *file_priv);
1632 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1635 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1636 enum intel_output_type type)
1638 return crtc_state->output_types & (1 << type);
1641 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1643 return crtc_state->output_types &
1644 ((1 << INTEL_OUTPUT_DP) |
1645 (1 << INTEL_OUTPUT_DP_MST) |
1646 (1 << INTEL_OUTPUT_EDP));
1649 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1651 drm_wait_one_vblank(&dev_priv->drm, pipe);
1654 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1656 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1659 intel_wait_for_vblank(dev_priv, pipe);
1662 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1664 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1665 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1666 struct intel_digital_port *dport,
1667 unsigned int expected_mask);
1668 int intel_get_load_detect_pipe(struct drm_connector *connector,
1669 const struct drm_display_mode *mode,
1670 struct intel_load_detect_pipe *old,
1671 struct drm_modeset_acquire_ctx *ctx);
1672 void intel_release_load_detect_pipe(struct drm_connector *connector,
1673 struct intel_load_detect_pipe *old,
1674 struct drm_modeset_acquire_ctx *ctx);
1676 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1677 const struct i915_ggtt_view *view,
1679 unsigned long *out_flags);
1680 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1681 struct drm_framebuffer *
1682 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1683 struct drm_mode_fb_cmd2 *mode_cmd);
1684 int intel_prepare_plane_fb(struct drm_plane *plane,
1685 struct drm_plane_state *new_state);
1686 void intel_cleanup_plane_fb(struct drm_plane *plane,
1687 struct drm_plane_state *old_state);
1688 int intel_plane_atomic_get_property(struct drm_plane *plane,
1689 const struct drm_plane_state *state,
1690 struct drm_property *property,
1692 int intel_plane_atomic_set_property(struct drm_plane *plane,
1693 struct drm_plane_state *state,
1694 struct drm_property *property,
1696 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1697 struct drm_crtc_state *crtc_state,
1698 const struct intel_plane_state *old_plane_state,
1699 struct drm_plane_state *plane_state);
1701 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1704 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1705 const struct dpll *dpll);
1706 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1707 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1709 /* modesetting asserts */
1710 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1712 void assert_pll(struct drm_i915_private *dev_priv,
1713 enum pipe pipe, bool state);
1714 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1715 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1716 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1717 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1718 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1719 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1720 enum pipe pipe, bool state);
1721 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1722 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1723 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1724 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1725 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1726 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1727 void intel_finish_reset(struct drm_i915_private *dev_priv);
1728 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1729 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1730 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1731 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1732 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1733 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1734 unsigned int skl_cdclk_get_vco(unsigned int freq);
1735 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1736 void intel_dp_get_m_n(struct intel_crtc *crtc,
1737 struct intel_crtc_state *pipe_config);
1738 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1739 enum link_m_n_set m_n);
1740 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1741 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1742 struct dpll *best_clock);
1743 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1745 bool intel_crtc_active(struct intel_crtc *crtc);
1746 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1747 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1748 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1749 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1750 enum intel_display_power_domain
1751 intel_aux_power_domain(struct intel_digital_port *dig_port);
1752 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1753 struct intel_crtc_state *pipe_config);
1754 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1755 struct intel_crtc_state *crtc_state);
1757 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1758 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1759 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1762 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1764 return i915_ggtt_offset(state->vma);
1767 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1768 const struct intel_plane_state *plane_state);
1769 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
1770 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1771 const struct intel_plane_state *plane_state);
1772 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
1773 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1775 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1776 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1777 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1778 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1779 u32 pixel_format, u64 modifier,
1780 unsigned int rotation);
1782 /* intel_connector.c */
1783 int intel_connector_init(struct intel_connector *connector);
1784 struct intel_connector *intel_connector_alloc(void);
1785 void intel_connector_free(struct intel_connector *connector);
1786 void intel_connector_destroy(struct drm_connector *connector);
1787 int intel_connector_register(struct drm_connector *connector);
1788 void intel_connector_unregister(struct drm_connector *connector);
1789 void intel_connector_attach_encoder(struct intel_connector *connector,
1790 struct intel_encoder *encoder);
1791 bool intel_connector_get_hw_state(struct intel_connector *connector);
1792 enum pipe intel_connector_get_pipe(struct intel_connector *connector);
1793 int intel_connector_update_modes(struct drm_connector *connector,
1795 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1796 void intel_attach_force_audio_property(struct drm_connector *connector);
1797 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1798 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1801 void intel_csr_ucode_init(struct drm_i915_private *);
1802 void intel_csr_load_program(struct drm_i915_private *);
1803 void intel_csr_ucode_fini(struct drm_i915_private *);
1804 void intel_csr_ucode_suspend(struct drm_i915_private *);
1805 void intel_csr_ucode_resume(struct drm_i915_private *);
1808 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1809 i915_reg_t dp_reg, enum port port,
1811 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1813 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1814 struct intel_connector *intel_connector);
1815 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1816 int link_rate, u8 lane_count,
1818 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1819 int link_rate, u8 lane_count);
1820 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1821 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1822 int intel_dp_retrain_link(struct intel_encoder *encoder,
1823 struct drm_modeset_acquire_ctx *ctx);
1824 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1825 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
1826 const struct intel_crtc_state *crtc_state,
1828 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1829 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1830 void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
1831 int intel_dp_compute_config(struct intel_encoder *encoder,
1832 struct intel_crtc_state *pipe_config,
1833 struct drm_connector_state *conn_state);
1834 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1835 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1836 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1838 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1839 const struct drm_connector_state *conn_state);
1840 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1841 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1842 void intel_edp_panel_on(struct intel_dp *intel_dp);
1843 void intel_edp_panel_off(struct intel_dp *intel_dp);
1844 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1845 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1846 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1847 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1848 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1849 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1850 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1851 u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
1852 void intel_plane_destroy(struct drm_plane *plane);
1853 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1854 const struct intel_crtc_state *crtc_state);
1855 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1856 const struct intel_crtc_state *crtc_state);
1857 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1858 unsigned int frontbuffer_bits);
1859 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1860 unsigned int frontbuffer_bits);
1863 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1866 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1867 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1869 intel_dp_voltage_max(struct intel_dp *intel_dp);
1871 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing);
1872 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1873 u8 *link_bw, u8 *rate_select);
1874 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1875 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1877 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE]);
1878 u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
1879 int mode_clock, int mode_hdisplay);
1880 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
1884 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
1885 struct intel_crtc_state *pipe_config);
1886 enum intel_display_power_domain
1887 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
1889 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1891 return ~((1 << lane_count) - 1) & 0xf;
1894 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1895 int intel_dp_link_required(int pixel_clock, int bpp);
1896 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1897 bool intel_digital_port_connected(struct intel_encoder *encoder);
1898 void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
1899 struct intel_digital_port *dig_port);
1901 /* intel_dp_aux_backlight.c */
1902 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1904 /* intel_dp_mst.c */
1905 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1906 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1908 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1911 void icl_dsi_init(struct drm_i915_private *dev_priv);
1913 /* intel_dsi_dcs_backlight.c */
1914 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1917 void intel_dvo_init(struct drm_i915_private *dev_priv);
1918 /* intel_hotplug.c */
1919 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1920 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1921 struct intel_connector *connector);
1923 /* legacy fbdev emulation in intel_fbdev.c */
1924 #ifdef CONFIG_DRM_FBDEV_EMULATION
1925 extern int intel_fbdev_init(struct drm_device *dev);
1926 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1927 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1928 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1929 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1930 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1931 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1933 static inline int intel_fbdev_init(struct drm_device *dev)
1938 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1942 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1946 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1950 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1954 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1958 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1964 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1965 struct intel_atomic_state *state);
1966 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1967 void intel_fbc_pre_update(struct intel_crtc *crtc,
1968 struct intel_crtc_state *crtc_state,
1969 struct intel_plane_state *plane_state);
1970 void intel_fbc_post_update(struct intel_crtc *crtc);
1971 void intel_fbc_init(struct drm_i915_private *dev_priv);
1972 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1973 void intel_fbc_enable(struct intel_crtc *crtc,
1974 struct intel_crtc_state *crtc_state,
1975 struct intel_plane_state *plane_state);
1976 void intel_fbc_disable(struct intel_crtc *crtc);
1977 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1978 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1979 unsigned int frontbuffer_bits,
1980 enum fb_op_origin origin);
1981 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1982 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1983 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1984 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1985 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1988 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1990 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1991 struct intel_connector *intel_connector);
1992 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1993 int intel_hdmi_compute_config(struct intel_encoder *encoder,
1994 struct intel_crtc_state *pipe_config,
1995 struct drm_connector_state *conn_state);
1996 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1997 struct drm_connector *connector,
1998 bool high_tmds_clock_ratio,
2000 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
2001 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
2004 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
2005 i915_reg_t lvds_reg, enum pipe *pipe);
2006 void intel_lvds_init(struct drm_i915_private *dev_priv);
2007 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
2008 bool intel_is_dual_link_lvds(struct drm_device *dev);
2010 /* intel_overlay.c */
2011 void intel_overlay_setup(struct drm_i915_private *dev_priv);
2012 void intel_overlay_cleanup(struct drm_i915_private *dev_priv);
2013 int intel_overlay_switch_off(struct intel_overlay *overlay);
2014 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
2015 struct drm_file *file_priv);
2016 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
2017 struct drm_file *file_priv);
2018 void intel_overlay_reset(struct drm_i915_private *dev_priv);
2022 int intel_panel_init(struct intel_panel *panel,
2023 struct drm_display_mode *fixed_mode,
2024 struct drm_display_mode *downclock_mode);
2025 void intel_panel_fini(struct intel_panel *panel);
2026 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
2027 struct drm_display_mode *adjusted_mode);
2028 void intel_pch_panel_fitting(struct intel_crtc *crtc,
2029 struct intel_crtc_state *pipe_config,
2031 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
2032 struct intel_crtc_state *pipe_config,
2034 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
2035 u32 level, u32 max);
2036 int intel_panel_setup_backlight(struct drm_connector *connector,
2038 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
2039 const struct drm_connector_state *conn_state);
2040 void intel_panel_update_backlight(struct intel_encoder *encoder,
2041 const struct intel_crtc_state *crtc_state,
2042 const struct drm_connector_state *conn_state);
2043 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
2044 extern struct drm_display_mode *intel_find_panel_downclock(
2045 struct drm_i915_private *dev_priv,
2046 struct drm_display_mode *fixed_mode,
2047 struct drm_connector *connector);
2049 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
2050 int intel_backlight_device_register(struct intel_connector *connector);
2051 void intel_backlight_device_unregister(struct intel_connector *connector);
2052 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2053 static inline int intel_backlight_device_register(struct intel_connector *connector)
2057 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
2060 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2063 void intel_hdcp_atomic_check(struct drm_connector *connector,
2064 struct drm_connector_state *old_state,
2065 struct drm_connector_state *new_state);
2066 int intel_hdcp_init(struct intel_connector *connector,
2067 const struct intel_hdcp_shim *hdcp_shim);
2068 int intel_hdcp_enable(struct intel_connector *connector);
2069 int intel_hdcp_disable(struct intel_connector *connector);
2070 int intel_hdcp_check_link(struct intel_connector *connector);
2071 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
2072 bool intel_hdcp_capable(struct intel_connector *connector);
2075 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
2076 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
2077 void intel_psr_enable(struct intel_dp *intel_dp,
2078 const struct intel_crtc_state *crtc_state);
2079 void intel_psr_disable(struct intel_dp *intel_dp,
2080 const struct intel_crtc_state *old_crtc_state);
2081 int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
2082 struct drm_modeset_acquire_ctx *ctx,
2084 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2085 unsigned frontbuffer_bits,
2086 enum fb_op_origin origin);
2087 void intel_psr_flush(struct drm_i915_private *dev_priv,
2088 unsigned frontbuffer_bits,
2089 enum fb_op_origin origin);
2090 void intel_psr_init(struct drm_i915_private *dev_priv);
2091 void intel_psr_compute_config(struct intel_dp *intel_dp,
2092 struct intel_crtc_state *crtc_state);
2093 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
2094 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
2095 void intel_psr_short_pulse(struct intel_dp *intel_dp);
2096 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
2098 bool intel_psr_enabled(struct intel_dp *intel_dp);
2100 /* intel_quirks.c */
2101 void intel_init_quirks(struct drm_i915_private *dev_priv);
2103 /* intel_runtime_pm.c */
2104 void intel_runtime_pm_init_early(struct drm_i915_private *dev_priv);
2105 int intel_power_domains_init(struct drm_i915_private *);
2106 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
2107 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
2108 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
2109 void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2110 void icl_display_core_uninit(struct drm_i915_private *dev_priv);
2111 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
2112 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
2114 enum i915_drm_suspend_mode {
2115 I915_DRM_SUSPEND_IDLE,
2116 I915_DRM_SUSPEND_MEM,
2117 I915_DRM_SUSPEND_HIBERNATE,
2120 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
2121 enum i915_drm_suspend_mode);
2122 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
2123 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2124 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
2125 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
2126 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
2127 void intel_runtime_pm_cleanup(struct drm_i915_private *dev_priv);
2129 intel_display_power_domain_str(enum intel_display_power_domain domain);
2131 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2132 enum intel_display_power_domain domain);
2133 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2134 enum intel_display_power_domain domain);
2135 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
2136 enum intel_display_power_domain domain);
2138 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
2139 enum intel_display_power_domain domain);
2140 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
2141 enum intel_display_power_domain domain);
2142 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2143 void intel_display_power_put(struct drm_i915_private *dev_priv,
2144 enum intel_display_power_domain domain,
2145 intel_wakeref_t wakeref);
2147 #define intel_display_power_put(i915, domain, wakeref) \
2148 intel_display_power_put_unchecked(i915, domain)
2150 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
2154 assert_rpm_device_not_suspended(struct drm_i915_private *i915)
2156 WARN_ONCE(i915->runtime_pm.suspended,
2157 "Device suspended during HW access\n");
2161 assert_rpm_wakelock_held(struct drm_i915_private *i915)
2163 assert_rpm_device_not_suspended(i915);
2164 WARN_ONCE(!atomic_read(&i915->runtime_pm.wakeref_count),
2165 "RPM wakelock ref not held during HW access");
2169 * disable_rpm_wakeref_asserts - disable the RPM assert checks
2170 * @i915: i915 device instance
2172 * This function disable asserts that check if we hold an RPM wakelock
2173 * reference, while keeping the device-not-suspended checks still enabled.
2174 * It's meant to be used only in special circumstances where our rule about
2175 * the wakelock refcount wrt. the device power state doesn't hold. According
2176 * to this rule at any point where we access the HW or want to keep the HW in
2177 * an active state we must hold an RPM wakelock reference acquired via one of
2178 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2179 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2180 * forcewake release timer, and the GPU RPS and hangcheck works. All other
2181 * users should avoid using this function.
2183 * Any calls to this function must have a symmetric call to
2184 * enable_rpm_wakeref_asserts().
2187 disable_rpm_wakeref_asserts(struct drm_i915_private *i915)
2189 atomic_inc(&i915->runtime_pm.wakeref_count);
2193 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2194 * @i915: i915 device instance
2196 * This function re-enables the RPM assert checks after disabling them with
2197 * disable_rpm_wakeref_asserts. It's meant to be used only in special
2198 * circumstances otherwise its use should be avoided.
2200 * Any calls to this function must have a symmetric call to
2201 * disable_rpm_wakeref_asserts().
2204 enable_rpm_wakeref_asserts(struct drm_i915_private *i915)
2206 atomic_dec(&i915->runtime_pm.wakeref_count);
2209 intel_wakeref_t intel_runtime_pm_get(struct drm_i915_private *i915);
2210 intel_wakeref_t intel_runtime_pm_get_if_in_use(struct drm_i915_private *i915);
2211 intel_wakeref_t intel_runtime_pm_get_noresume(struct drm_i915_private *i915);
2213 #define with_intel_runtime_pm(i915, wf) \
2214 for ((wf) = intel_runtime_pm_get(i915); (wf); \
2215 intel_runtime_pm_put((i915), (wf)), (wf) = 0)
2217 #define with_intel_runtime_pm_if_in_use(i915, wf) \
2218 for ((wf) = intel_runtime_pm_get_if_in_use(i915); (wf); \
2219 intel_runtime_pm_put((i915), (wf)), (wf) = 0)
2221 void intel_runtime_pm_put_unchecked(struct drm_i915_private *i915);
2222 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2223 void intel_runtime_pm_put(struct drm_i915_private *i915, intel_wakeref_t wref);
2225 #define intel_runtime_pm_put(i915, wref) intel_runtime_pm_put_unchecked(i915)
2228 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2229 void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
2230 struct drm_printer *p);
2232 static inline void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
2233 struct drm_printer *p)
2238 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2239 bool override, unsigned int mask);
2240 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2241 enum dpio_channel ch, bool override);
2245 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2246 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2247 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2248 void intel_update_watermarks(struct intel_crtc *crtc);
2249 void intel_init_pm(struct drm_i915_private *dev_priv);
2250 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2251 void intel_pm_setup(struct drm_i915_private *dev_priv);
2252 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2253 void intel_gpu_ips_teardown(void);
2254 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2255 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2256 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2257 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2258 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2259 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2260 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2261 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2262 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2263 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2264 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
2265 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
2266 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
2267 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
2268 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
2269 struct skl_ddb_entry *ddb_y,
2270 struct skl_ddb_entry *ddb_uv);
2271 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2272 struct skl_ddb_allocation *ddb /* out */);
2273 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
2274 struct skl_pipe_wm *out);
2275 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2276 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2277 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2278 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2279 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2280 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2281 const struct skl_wm_level *l2);
2282 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
2283 const struct skl_ddb_entry entries[],
2284 int num_entries, int ignore_idx);
2285 void skl_write_plane_wm(struct intel_plane *plane,
2286 const struct intel_crtc_state *crtc_state);
2287 void skl_write_cursor_wm(struct intel_plane *plane,
2288 const struct intel_crtc_state *crtc_state);
2289 bool ilk_disable_lp_wm(struct drm_device *dev);
2290 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2291 struct intel_crtc_state *cstate);
2292 void intel_init_ipc(struct drm_i915_private *dev_priv);
2293 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2296 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2297 i915_reg_t sdvo_reg, enum pipe *pipe);
2298 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2299 i915_reg_t reg, enum port port);
2302 /* intel_sprite.c */
2303 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2305 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2306 enum pipe pipe, int plane);
2307 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2308 struct drm_file *file_priv);
2309 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2310 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2311 int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2312 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2313 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2314 struct intel_plane *
2315 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2316 enum pipe pipe, enum plane_id plane_id);
2318 static inline bool icl_is_nv12_y_plane(enum plane_id id)
2320 /* Don't need to do a gen check, these planes are only available on gen11 */
2321 if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
2327 static inline bool icl_is_hdr_plane(struct intel_plane *plane)
2329 if (INTEL_GEN(to_i915(plane->base.dev)) < 11)
2332 return plane->id < PLANE_SPRITE2;
2336 void intel_tv_init(struct drm_i915_private *dev_priv);
2338 /* intel_atomic.c */
2339 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2340 const struct drm_connector_state *state,
2341 struct drm_property *property,
2343 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2344 struct drm_connector_state *state,
2345 struct drm_property *property,
2347 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2348 struct drm_connector_state *new_state);
2349 struct drm_connector_state *
2350 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2352 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2353 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2354 struct drm_crtc_state *state);
2355 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2356 void intel_atomic_state_clear(struct drm_atomic_state *);
2358 static inline struct intel_crtc_state *
2359 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2360 struct intel_crtc *crtc)
2362 struct drm_crtc_state *crtc_state;
2363 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2364 if (IS_ERR(crtc_state))
2365 return ERR_CAST(crtc_state);
2367 return to_intel_crtc_state(crtc_state);
2370 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2371 struct intel_crtc *intel_crtc,
2372 struct intel_crtc_state *crtc_state);
2374 /* intel_atomic_plane.c */
2375 struct intel_plane *intel_plane_alloc(void);
2376 void intel_plane_free(struct intel_plane *plane);
2377 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2378 void intel_plane_destroy_state(struct drm_plane *plane,
2379 struct drm_plane_state *state);
2380 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2381 void skl_update_planes_on_crtc(struct intel_atomic_state *state,
2382 struct intel_crtc *crtc);
2383 void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
2384 struct intel_crtc *crtc);
2385 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2386 struct intel_crtc_state *crtc_state,
2387 const struct intel_plane_state *old_plane_state,
2388 struct intel_plane_state *intel_state);
2391 void intel_color_init(struct intel_crtc *crtc);
2392 int intel_color_check(struct intel_crtc_state *crtc_state);
2393 void intel_color_commit(const struct intel_crtc_state *crtc_state);
2394 void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
2396 /* intel_lspcon.c */
2397 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2398 void lspcon_resume(struct intel_lspcon *lspcon);
2399 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2400 void lspcon_write_infoframe(struct intel_encoder *encoder,
2401 const struct intel_crtc_state *crtc_state,
2403 const void *buf, ssize_t len);
2404 void lspcon_set_infoframes(struct intel_encoder *encoder,
2406 const struct intel_crtc_state *crtc_state,
2407 const struct drm_connector_state *conn_state);
2408 bool lspcon_infoframe_enabled(struct intel_encoder *encoder,
2409 const struct intel_crtc_state *pipe_config);
2410 void lspcon_ycbcr420_config(struct drm_connector *connector,
2411 struct intel_crtc_state *crtc_state);
2413 /* intel_pipe_crc.c */
2414 #ifdef CONFIG_DEBUG_FS
2415 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
2416 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
2417 const char *source_name, size_t *values_cnt);
2418 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
2420 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2421 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2423 #define intel_crtc_set_crc_source NULL
2424 #define intel_crtc_verify_crc_source NULL
2425 #define intel_crtc_get_crc_sources NULL
2426 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2430 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2434 #endif /* __INTEL_DRV_H__ */