drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_dual_mode_helper.h>
  37 #include <drm/drm_dp_mst_helper.h>
  38 #include <drm/drm_rect.h>
  39 #include <drm/drm_atomic.h>
  40
  41 /**
  42  * _wait_for - magic (register) wait macro
  43  *
  44  * Does the right thing for modeset paths when run under kdgb or similar atomic
  45  * contexts. Note that it's important that we check the condition again after
  46  * having timed out, since the timeout could be due to preemption or similar and
  47  * we've never had a chance to check the condition before the timeout.
  48  *
  49  * TODO: When modesetting has fully transitioned to atomic, the below
  50  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  51  * added.
  52  */
  53 #define _wait_for(COND, US, W) ({ \
  54         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  55         int ret__ = 0;                                                  \
  56         while (!(COND)) {                                               \
  57                 if (time_after(jiffies, timeout__)) {                   \
  58                         if (!(COND))                                    \
  59                                 ret__ = -ETIMEDOUT;                     \
  60                         break;                                          \
  61                 }                                                       \
  62                 if ((W) && drm_can_sleep()) {                           \
  63                         usleep_range((W), (W)*2);                       \
  64                 } else {                                                \
  65                         cpu_relax();                                    \
  66                 }                                                       \
  67         }                                                               \
  68         ret__;                                                          \
  69 })
  70
  71 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  72
  73 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  74 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  75 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  76 #else
  77 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  78 #endif
  79
  80 #define _wait_for_atomic(COND, US, ATOMIC) \
  81 ({ \
  82         int cpu, ret, timeout = (US) * 1000; \
  83         u64 base; \
  84         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  85         BUILD_BUG_ON((US) > 50000); \
  86         if (!(ATOMIC)) { \
  87                 preempt_disable(); \
  88                 cpu = smp_processor_id(); \
  89         } \
  90         base = local_clock(); \
  91         for (;;) { \
  92                 u64 now = local_clock(); \
  93                 if (!(ATOMIC)) \
  94                         preempt_enable(); \
  95                 if (COND) { \
  96                         ret = 0; \
  97                         break; \
  98                 } \
  99                 if (now - base >= timeout) { \
 100                         ret = -ETIMEDOUT; \
 101                         break; \
 102                 } \
 103                 cpu_relax(); \
 104                 if (!(ATOMIC)) { \
 105                         preempt_disable(); \
 106                         if (unlikely(cpu != smp_processor_id())) { \
 107                                 timeout -= now - base; \
 108                                 cpu = smp_processor_id(); \
 109                                 base = local_clock(); \
 110                         } \
 111                 } \
 112         } \
 113         ret; \
 114 })
 115
 116 #define wait_for_us(COND, US) \
 117 ({ \
 118         int ret__; \
 119         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 120         if ((US) > 10) \
 121                 ret__ = _wait_for((COND), (US), 10); \
 122         else \
 123                 ret__ = _wait_for_atomic((COND), (US), 0); \
 124         ret__; \
 125 })
 126
 127 #define wait_for_atomic(COND, MS)       _wait_for_atomic((COND), (MS) * 1000, 1)
 128 #define wait_for_atomic_us(COND, US)    _wait_for_atomic((COND), (US), 1)
 129
 130 #define KHz(x) (1000 * (x))
 131 #define MHz(x) KHz(1000 * (x))
 132
 133 /*
 134  * Display related stuff
 135  */
 136
 137 /* store information about an Ixxx DVO */
 138 /* The i830->i865 use multiple DVOs with multiple i2cs */
 139 /* the i915, i945 have a single sDVO i2c bus - which is different */
 140 #define MAX_OUTPUTS 6
 141 /* maximum connectors per crtcs in the mode set */
 142
 143 /* Maximum cursor sizes */
 144 #define GEN2_CURSOR_WIDTH 64
 145 #define GEN2_CURSOR_HEIGHT 64
 146 #define MAX_CURSOR_WIDTH 256
 147 #define MAX_CURSOR_HEIGHT 256
 148
 149 #define INTEL_I2C_BUS_DVO 1
 150 #define INTEL_I2C_BUS_SDVO 2
 151
 152 /* these are outputs from the chip - integrated only
 153    external chips are via DVO or SDVO output */
 154 enum intel_output_type {
 155         INTEL_OUTPUT_UNUSED = 0,
 156         INTEL_OUTPUT_ANALOG = 1,
 157         INTEL_OUTPUT_DVO = 2,
 158         INTEL_OUTPUT_SDVO = 3,
 159         INTEL_OUTPUT_LVDS = 4,
 160         INTEL_OUTPUT_TVOUT = 5,
 161         INTEL_OUTPUT_HDMI = 6,
 162         INTEL_OUTPUT_DP = 7,
 163         INTEL_OUTPUT_EDP = 8,
 164         INTEL_OUTPUT_DSI = 9,
 165         INTEL_OUTPUT_UNKNOWN = 10,
 166         INTEL_OUTPUT_DP_MST = 11,
 167 };
 168
 169 #define INTEL_DVO_CHIP_NONE 0
 170 #define INTEL_DVO_CHIP_LVDS 1
 171 #define INTEL_DVO_CHIP_TMDS 2
 172 #define INTEL_DVO_CHIP_TVOUT 4
 173
 174 #define INTEL_DSI_VIDEO_MODE    0
 175 #define INTEL_DSI_COMMAND_MODE  1
 176
 177 struct intel_framebuffer {
 178         struct drm_framebuffer base;
 179         struct drm_i915_gem_object *obj;
 180         struct intel_rotation_info rot_info;
 181 };
 182
 183 struct intel_fbdev {
 184         struct drm_fb_helper helper;
 185         struct intel_framebuffer *fb;
 186         async_cookie_t cookie;
 187         int preferred_bpp;
 188 };
 189
 190 struct intel_encoder {
 191         struct drm_encoder base;
 192
 193         enum intel_output_type type;
 194         unsigned int cloneable;
 195         void (*hot_plug)(struct intel_encoder *);
 196         bool (*compute_config)(struct intel_encoder *,
 197                                struct intel_crtc_state *);
 198         void (*pre_pll_enable)(struct intel_encoder *);
 199         void (*pre_enable)(struct intel_encoder *);
 200         void (*enable)(struct intel_encoder *);
 201         void (*mode_set)(struct intel_encoder *intel_encoder);
 202         void (*disable)(struct intel_encoder *);
 203         void (*post_disable)(struct intel_encoder *);
 204         void (*post_pll_disable)(struct intel_encoder *);
 205         /* Read out the current hw state of this connector, returning true if
 206          * the encoder is active. If the encoder is enabled it also set the pipe
 207          * it is connected to in the pipe parameter. */
 208         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 209         /* Reconstructs the equivalent mode flags for the current hardware
 210          * state. This must be called _after_ display->get_pipe_config has
 211          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 212          * be set correctly before calling this function. */
 213         void (*get_config)(struct intel_encoder *,
 214                            struct intel_crtc_state *pipe_config);
 215         /*
 216          * Called during system suspend after all pending requests for the
 217          * encoder are flushed (for example for DP AUX transactions) and
 218          * device interrupts are disabled.
 219          */
 220         void (*suspend)(struct intel_encoder *);
 221         int crtc_mask;
 222         enum hpd_pin hpd_pin;
 223 };
 224
 225 struct intel_panel {
 226         struct drm_display_mode *fixed_mode;
 227         struct drm_display_mode *downclock_mode;
 228         int fitting_mode;
 229
 230         /* backlight */
 231         struct {
 232                 bool present;
 233                 u32 level;
 234                 u32 min;
 235                 u32 max;
 236                 bool enabled;
 237                 bool combination_mode;  /* gen 2/4 only */
 238                 bool active_low_pwm;
 239
 240                 /* PWM chip */
 241                 bool util_pin_active_low;       /* bxt+ */
 242                 u8 controller;          /* bxt+ only */
 243                 struct pwm_device *pwm;
 244
 245                 struct backlight_device *device;
 246
 247                 /* Connector and platform specific backlight functions */
 248                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 249                 uint32_t (*get)(struct intel_connector *connector);
 250                 void (*set)(struct intel_connector *connector, uint32_t level);
 251                 void (*disable)(struct intel_connector *connector);
 252                 void (*enable)(struct intel_connector *connector);
 253                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 254                                       uint32_t hz);
 255                 void (*power)(struct intel_connector *, bool enable);
 256         } backlight;
 257 };
 258
 259 struct intel_connector {
 260         struct drm_connector base;
 261         /*
 262          * The fixed encoder this connector is connected to.
 263          */
 264         struct intel_encoder *encoder;
 265
 266         /* Reads out the current hw, returning true if the connector is enabled
 267          * and active (i.e. dpms ON state). */
 268         bool (*get_hw_state)(struct intel_connector *);
 269
 270         /* Panel info for eDP and LVDS */
 271         struct intel_panel panel;
 272
 273         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 274         struct edid *edid;
 275         struct edid *detect_edid;
 276
 277         /* since POLL and HPD connectors may use the same HPD line keep the native
 278            state of connector->polled in case hotplug storm detection changes it */
 279         u8 polled;
 280
 281         void *port; /* store this opaque as its illegal to dereference it */
 282
 283         struct intel_dp *mst_port;
 284 };
 285
 286 struct dpll {
 287         /* given values */
 288         int n;
 289         int m1, m2;
 290         int p1, p2;
 291         /* derived values */
 292         int     dot;
 293         int     vco;
 294         int     m;
 295         int     p;
 296 };
 297
 298 struct intel_atomic_state {
 299         struct drm_atomic_state base;
 300
 301         unsigned int cdclk;
 302
 303         /*
 304          * Calculated device cdclk, can be different from cdclk
 305          * only when all crtc's are DPMS off.
 306          */
 307         unsigned int dev_cdclk;
 308
 309         bool dpll_set, modeset;
 310
 311         /*
 312          * Does this transaction change the pipes that are active?  This mask
 313          * tracks which CRTC's have changed their active state at the end of
 314          * the transaction (not counting the temporary disable during modesets).
 315          * This mask should only be non-zero when intel_state->modeset is true,
 316          * but the converse is not necessarily true; simply changing a mode may
 317          * not flip the final active status of any CRTC's
 318          */
 319         unsigned int active_pipe_changes;
 320
 321         unsigned int active_crtcs;
 322         unsigned int min_pixclk[I915_MAX_PIPES];
 323
 324         /* SKL/KBL Only */
 325         unsigned int cdclk_pll_vco;
 326
 327         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 328
 329         /*
 330          * Current watermarks can't be trusted during hardware readout, so
 331          * don't bother calculating intermediate watermarks.
 332          */
 333         bool skip_intermediate_wm;
 334
 335         /* Gen9+ only */
 336         struct skl_wm_values wm_results;
 337 };
 338
 339 struct intel_plane_state {
 340         struct drm_plane_state base;
 341         struct drm_rect clip;
 342
 343         /*
 344          * scaler_id
 345          *    = -1 : not using a scaler
 346          *    >=  0 : using a scalers
 347          *
 348          * plane requiring a scaler:
 349          *   - During check_plane, its bit is set in
 350          *     crtc_state->scaler_state.scaler_users by calling helper function
 351          *     update_scaler_plane.
 352          *   - scaler_id indicates the scaler it got assigned.
 353          *
 354          * plane doesn't require a scaler:
 355          *   - this can happen when scaling is no more required or plane simply
 356          *     got disabled.
 357          *   - During check_plane, corresponding bit is reset in
 358          *     crtc_state->scaler_state.scaler_users by calling helper function
 359          *     update_scaler_plane.
 360          */
 361         int scaler_id;
 362
 363         struct drm_intel_sprite_colorkey ckey;
 364
 365         /* async flip related structures */
 366         struct drm_i915_gem_request *wait_req;
 367 };
 368
 369 struct intel_initial_plane_config {
 370         struct intel_framebuffer *fb;
 371         unsigned int tiling;
 372         int size;
 373         u32 base;
 374 };
 375
 376 #define SKL_MIN_SRC_W 8
 377 #define SKL_MAX_SRC_W 4096
 378 #define SKL_MIN_SRC_H 8
 379 #define SKL_MAX_SRC_H 4096
 380 #define SKL_MIN_DST_W 8
 381 #define SKL_MAX_DST_W 4096
 382 #define SKL_MIN_DST_H 8
 383 #define SKL_MAX_DST_H 4096
 384
 385 struct intel_scaler {
 386         int in_use;
 387         uint32_t mode;
 388 };
 389
 390 struct intel_crtc_scaler_state {
 391 #define SKL_NUM_SCALERS 2
 392         struct intel_scaler scalers[SKL_NUM_SCALERS];
 393
 394         /*
 395          * scaler_users: keeps track of users requesting scalers on this crtc.
 396          *
 397          *     If a bit is set, a user is using a scaler.
 398          *     Here user can be a plane or crtc as defined below:
 399          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 400          *       bit 31    - crtc
 401          *
 402          * Instead of creating a new index to cover planes and crtc, using
 403          * existing drm_plane_index for planes which is well less than 31
 404          * planes and bit 31 for crtc. This should be fine to cover all
 405          * our platforms.
 406          *
 407          * intel_atomic_setup_scalers will setup available scalers to users
 408          * requesting scalers. It will gracefully fail if request exceeds
 409          * avilability.
 410          */
 411 #define SKL_CRTC_INDEX 31
 412         unsigned scaler_users;
 413
 414         /* scaler used by crtc for panel fitting purpose */
 415         int scaler_id;
 416 };
 417
 418 /* drm_mode->private_flags */
 419 #define I915_MODE_FLAG_INHERITED 1
 420
 421 struct intel_pipe_wm {
 422         struct intel_wm_level wm[5];
 423         struct intel_wm_level raw_wm[5];
 424         uint32_t linetime;
 425         bool fbc_wm_enabled;
 426         bool pipe_enabled;
 427         bool sprites_enabled;
 428         bool sprites_scaled;
 429 };
 430
 431 struct skl_pipe_wm {
 432         struct skl_wm_level wm[8];
 433         struct skl_wm_level trans_wm;
 434         uint32_t linetime;
 435 };
 436
 437 struct intel_crtc_wm_state {
 438         union {
 439                 struct {
 440                         /*
 441                          * Intermediate watermarks; these can be
 442                          * programmed immediately since they satisfy
 443                          * both the current configuration we're
 444                          * switching away from and the new
 445                          * configuration we're switching to.
 446                          */
 447                         struct intel_pipe_wm intermediate;
 448
 449                         /*
 450                          * Optimal watermarks, programmed post-vblank
 451                          * when this state is committed.
 452                          */
 453                         struct intel_pipe_wm optimal;
 454                 } ilk;
 455
 456                 struct {
 457                         /* gen9+ only needs 1-step wm programming */
 458                         struct skl_pipe_wm optimal;
 459
 460                         /* cached plane data rate */
 461                         unsigned plane_data_rate[I915_MAX_PLANES];
 462                         unsigned plane_y_data_rate[I915_MAX_PLANES];
 463
 464                         /* minimum block allocation */
 465                         uint16_t minimum_blocks[I915_MAX_PLANES];
 466                         uint16_t minimum_y_blocks[I915_MAX_PLANES];
 467                 } skl;
 468         };
 469
 470         /*
 471          * Platforms with two-step watermark programming will need to
 472          * update watermark programming post-vblank to switch from the
 473          * safe intermediate watermarks to the optimal final
 474          * watermarks.
 475          */
 476         bool need_postvbl_update;
 477 };
 478
 479 struct intel_crtc_state {
 480         struct drm_crtc_state base;
 481
 482         /**
 483          * quirks - bitfield with hw state readout quirks
 484          *
 485          * For various reasons the hw state readout code might not be able to
 486          * completely faithfully read out the current state. These cases are
 487          * tracked with quirk flags so that fastboot and state checker can act
 488          * accordingly.
 489          */
 490 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 491         unsigned long quirks;
 492
 493         unsigned fb_bits; /* framebuffers to flip */
 494         bool update_pipe; /* can a fast modeset be performed? */
 495         bool disable_cxsr;
 496         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 497         bool fb_changed; /* fb on any of the planes is changed */
 498
 499         /* Pipe source size (ie. panel fitter input size)
 500          * All planes will be positioned inside this space,
 501          * and get clipped at the edges. */
 502         int pipe_src_w, pipe_src_h;
 503
 504         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 505          * between pch encoders and cpu encoders. */
 506         bool has_pch_encoder;
 507
 508         /* Are we sending infoframes on the attached port */
 509         bool has_infoframe;
 510
 511         /* CPU Transcoder for the pipe. Currently this can only differ from the
 512          * pipe on Haswell and later (where we have a special eDP transcoder)
 513          * and Broxton (where we have special DSI transcoders). */
 514         enum transcoder cpu_transcoder;
 515
 516         /*
 517          * Use reduced/limited/broadcast rbg range, compressing from the full
 518          * range fed into the crtcs.
 519          */
 520         bool limited_color_range;
 521
 522         /* Bitmask of encoder types (enum intel_output_type)
 523          * driven by the pipe.
 524          */
 525         unsigned int output_types;
 526
 527         /* Whether we should send NULL infoframes. Required for audio. */
 528         bool has_hdmi_sink;
 529
 530         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 531          * has_dp_encoder is set. */
 532         bool has_audio;
 533
 534         /*
 535          * Enable dithering, used when the selected pipe bpp doesn't match the
 536          * plane bpp.
 537          */
 538         bool dither;
 539
 540         /* Controls for the clock computation, to override various stages. */
 541         bool clock_set;
 542
 543         /* SDVO TV has a bunch of special case. To make multifunction encoders
 544          * work correctly, we need to track this at runtime.*/
 545         bool sdvo_tv_clock;
 546
 547         /*
 548          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 549          * required. This is set in the 2nd loop of calling encoder's
 550          * ->compute_config if the first pick doesn't work out.
 551          */
 552         bool bw_constrained;
 553
 554         /* Settings for the intel dpll used on pretty much everything but
 555          * haswell. */
 556         struct dpll dpll;
 557
 558         /* Selected dpll when shared or NULL. */
 559         struct intel_shared_dpll *shared_dpll;
 560
 561         /*
 562          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 563          * - enum skl_dpll on SKL
 564          */
 565         uint32_t ddi_pll_sel;
 566
 567         /* Actual register state of the dpll, for shared dpll cross-checking. */
 568         struct intel_dpll_hw_state dpll_hw_state;
 569
 570         /* DSI PLL registers */
 571         struct {
 572                 u32 ctrl, div;
 573         } dsi_pll;
 574
 575         int pipe_bpp;
 576         struct intel_link_m_n dp_m_n;
 577
 578         /* m2_n2 for eDP downclock */
 579         struct intel_link_m_n dp_m2_n2;
 580         bool has_drrs;
 581
 582         /*
 583          * Frequence the dpll for the port should run at. Differs from the
 584          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 585          * already multiplied by pixel_multiplier.
 586          */
 587         int port_clock;
 588
 589         /* Used by SDVO (and if we ever fix it, HDMI). */
 590         unsigned pixel_multiplier;
 591
 592         uint8_t lane_count;
 593
 594         /*
 595          * Used by platforms having DP/HDMI PHY with programmable lane
 596          * latency optimization.
 597          */
 598         uint8_t lane_lat_optim_mask;
 599
 600         /* Panel fitter controls for gen2-gen4 + VLV */
 601         struct {
 602                 u32 control;
 603                 u32 pgm_ratios;
 604                 u32 lvds_border_bits;
 605         } gmch_pfit;
 606
 607         /* Panel fitter placement and size for Ironlake+ */
 608         struct {
 609                 u32 pos;
 610                 u32 size;
 611                 bool enabled;
 612                 bool force_thru;
 613         } pch_pfit;
 614
 615         /* FDI configuration, only valid if has_pch_encoder is set. */
 616         int fdi_lanes;
 617         struct intel_link_m_n fdi_m_n;
 618
 619         bool ips_enabled;
 620
 621         bool enable_fbc;
 622
 623         bool double_wide;
 624
 625         bool dp_encoder_is_mst;
 626         int pbn;
 627
 628         struct intel_crtc_scaler_state scaler_state;
 629
 630         /* w/a for waiting 2 vblanks during crtc enable */
 631         enum pipe hsw_workaround_pipe;
 632
 633         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 634         bool disable_lp_wm;
 635
 636         struct intel_crtc_wm_state wm;
 637
 638         /* Gamma mode programmed on the pipe */
 639         uint32_t gamma_mode;
 640 };
 641
 642 struct vlv_wm_state {
 643         struct vlv_pipe_wm wm[3];
 644         struct vlv_sr_wm sr[3];
 645         uint8_t num_active_planes;
 646         uint8_t num_levels;
 647         uint8_t level;
 648         bool cxsr;
 649 };
 650
 651 struct intel_crtc {
 652         struct drm_crtc base;
 653         enum pipe pipe;
 654         enum plane plane;
 655         u8 lut_r[256], lut_g[256], lut_b[256];
 656         /*
 657          * Whether the crtc and the connected output pipeline is active. Implies
 658          * that crtc->enabled is set, i.e. the current mode configuration has
 659          * some outputs connected to this crtc.
 660          */
 661         bool active;
 662         unsigned long enabled_power_domains;
 663         bool lowfreq_avail;
 664         struct intel_overlay *overlay;
 665         struct intel_flip_work *flip_work;
 666
 667         atomic_t unpin_work_count;
 668
 669         /* Display surface base address adjustement for pageflips. Note that on
 670          * gen4+ this only adjusts up to a tile, offsets within a tile are
 671          * handled in the hw itself (with the TILEOFF register). */
 672         u32 dspaddr_offset;
 673         int adjusted_x;
 674         int adjusted_y;
 675
 676         uint32_t cursor_addr;
 677         uint32_t cursor_cntl;
 678         uint32_t cursor_size;
 679         uint32_t cursor_base;
 680
 681         struct intel_crtc_state *config;
 682
 683         /* reset counter value when the last flip was submitted */
 684         unsigned int reset_counter;
 685
 686         /* Access to these should be protected by dev_priv->irq_lock. */
 687         bool cpu_fifo_underrun_disabled;
 688         bool pch_fifo_underrun_disabled;
 689
 690         /* per-pipe watermark state */
 691         struct {
 692                 /* watermarks currently being used  */
 693                 union {
 694                         struct intel_pipe_wm ilk;
 695                         struct skl_pipe_wm skl;
 696                 } active;
 697
 698                 /* allow CxSR on this pipe */
 699                 bool cxsr_allowed;
 700         } wm;
 701
 702         int scanline_offset;
 703
 704         struct {
 705                 unsigned start_vbl_count;
 706                 ktime_t start_vbl_time;
 707                 int min_vbl, max_vbl;
 708                 int scanline_start;
 709         } debug;
 710
 711         /* scalers available on this crtc */
 712         int num_scalers;
 713
 714         struct vlv_wm_state wm_state;
 715 };
 716
 717 struct intel_plane_wm_parameters {
 718         uint32_t horiz_pixels;
 719         uint32_t vert_pixels;
 720         /*
 721          *   For packed pixel formats:
 722          *     bytes_per_pixel - holds bytes per pixel
 723          *   For planar pixel formats:
 724          *     bytes_per_pixel - holds bytes per pixel for uv-plane
 725          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 726          */
 727         uint8_t bytes_per_pixel;
 728         uint8_t y_bytes_per_pixel;
 729         bool enabled;
 730         bool scaled;
 731         u64 tiling;
 732         unsigned int rotation;
 733         uint16_t fifo_size;
 734 };
 735
 736 struct intel_plane {
 737         struct drm_plane base;
 738         int plane;
 739         enum pipe pipe;
 740         bool can_scale;
 741         int max_downscale;
 742         uint32_t frontbuffer_bit;
 743
 744         /* Since we need to change the watermarks before/after
 745          * enabling/disabling the planes, we need to store the parameters here
 746          * as the other pieces of the struct may not reflect the values we want
 747          * for the watermark calculations. Currently only Haswell uses this.
 748          */
 749         struct intel_plane_wm_parameters wm;
 750
 751         /*
 752          * NOTE: Do not place new plane state fields here (e.g., when adding
 753          * new plane properties).  New runtime state should now be placed in
 754          * the intel_plane_state structure and accessed via plane_state.
 755          */
 756
 757         void (*update_plane)(struct drm_plane *plane,
 758                              const struct intel_crtc_state *crtc_state,
 759                              const struct intel_plane_state *plane_state);
 760         void (*disable_plane)(struct drm_plane *plane,
 761                               struct drm_crtc *crtc);
 762         int (*check_plane)(struct drm_plane *plane,
 763                            struct intel_crtc_state *crtc_state,
 764                            struct intel_plane_state *state);
 765 };
 766
 767 struct intel_watermark_params {
 768         unsigned long fifo_size;
 769         unsigned long max_wm;
 770         unsigned long default_wm;
 771         unsigned long guard_size;
 772         unsigned long cacheline_size;
 773 };
 774
 775 struct cxsr_latency {
 776         int is_desktop;
 777         int is_ddr3;
 778         unsigned long fsb_freq;
 779         unsigned long mem_freq;
 780         unsigned long display_sr;
 781         unsigned long display_hpll_disable;
 782         unsigned long cursor_sr;
 783         unsigned long cursor_hpll_disable;
 784 };
 785
 786 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 787 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 788 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 789 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 790 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 791 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 792 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 793 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 794 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 795
 796 struct intel_hdmi {
 797         i915_reg_t hdmi_reg;
 798         int ddc_bus;
 799         struct {
 800                 enum drm_dp_dual_mode_type type;
 801                 int max_tmds_clock;
 802         } dp_dual_mode;
 803         bool limited_color_range;
 804         bool color_range_auto;
 805         bool has_hdmi_sink;
 806         bool has_audio;
 807         enum hdmi_force_audio force_audio;
 808         bool rgb_quant_range_selectable;
 809         enum hdmi_picture_aspect aspect_ratio;
 810         struct intel_connector *attached_connector;
 811         void (*write_infoframe)(struct drm_encoder *encoder,
 812                                 enum hdmi_infoframe_type type,
 813                                 const void *frame, ssize_t len);
 814         void (*set_infoframes)(struct drm_encoder *encoder,
 815                                bool enable,
 816                                const struct drm_display_mode *adjusted_mode);
 817         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 818                                   const struct intel_crtc_state *pipe_config);
 819 };
 820
 821 struct intel_dp_mst_encoder;
 822 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 823
 824 /*
 825  * enum link_m_n_set:
 826  *      When platform provides two set of M_N registers for dp, we can
 827  *      program them and switch between them incase of DRRS.
 828  *      But When only one such register is provided, we have to program the
 829  *      required divider value on that registers itself based on the DRRS state.
 830  *
 831  * M1_N1        : Program dp_m_n on M1_N1 registers
 832  *                        dp_m2_n2 on M2_N2 registers (If supported)
 833  *
 834  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 835  *                        M2_N2 registers are not supported
 836  */
 837
 838 enum link_m_n_set {
 839         /* Sets the m1_n1 and m2_n2 */
 840         M1_N1 = 0,
 841         M2_N2
 842 };
 843
 844 struct intel_dp {
 845         i915_reg_t output_reg;
 846         i915_reg_t aux_ch_ctl_reg;
 847         i915_reg_t aux_ch_data_reg[5];
 848         uint32_t DP;
 849         int link_rate;
 850         uint8_t lane_count;
 851         uint8_t sink_count;
 852         bool link_mst;
 853         bool has_audio;
 854         bool detect_done;
 855         enum hdmi_force_audio force_audio;
 856         bool limited_color_range;
 857         bool color_range_auto;
 858         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 859         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 860         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 861         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 862         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 863         uint8_t num_sink_rates;
 864         int sink_rates[DP_MAX_SUPPORTED_RATES];
 865         struct drm_dp_aux aux;
 866         uint8_t train_set[4];
 867         int panel_power_up_delay;
 868         int panel_power_down_delay;
 869         int panel_power_cycle_delay;
 870         int backlight_on_delay;
 871         int backlight_off_delay;
 872         struct delayed_work panel_vdd_work;
 873         bool want_panel_vdd;
 874         unsigned long last_power_on;
 875         unsigned long last_backlight_off;
 876         ktime_t panel_power_off_time;
 877
 878         struct notifier_block edp_notifier;
 879
 880         /*
 881          * Pipe whose power sequencer is currently locked into
 882          * this port. Only relevant on VLV/CHV.
 883          */
 884         enum pipe pps_pipe;
 885         /*
 886          * Set if the sequencer may be reset due to a power transition,
 887          * requiring a reinitialization. Only relevant on BXT.
 888          */
 889         bool pps_reset;
 890         struct edp_power_seq pps_delays;
 891
 892         bool can_mst; /* this port supports mst */
 893         bool is_mst;
 894         int active_mst_links;
 895         /* connector directly attached - won't be use for modeset in mst world */
 896         struct intel_connector *attached_connector;
 897
 898         /* mst connector list */
 899         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 900         struct drm_dp_mst_topology_mgr mst_mgr;
 901
 902         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 903         /*
 904          * This function returns the value we have to program the AUX_CTL
 905          * register with to kick off an AUX transaction.
 906          */
 907         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 908                                      bool has_aux_irq,
 909                                      int send_bytes,
 910                                      uint32_t aux_clock_divider);
 911
 912         /* This is called before a link training is starterd */
 913         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 914
 915         /* Displayport compliance testing */
 916         unsigned long compliance_test_type;
 917         unsigned long compliance_test_data;
 918         bool compliance_test_active;
 919 };
 920
 921 struct intel_digital_port {
 922         struct intel_encoder base;
 923         enum port port;
 924         u32 saved_port_bits;
 925         struct intel_dp dp;
 926         struct intel_hdmi hdmi;
 927         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 928         bool release_cl2_override;
 929         uint8_t max_lanes;
 930         /* for communication with audio component; protected by av_mutex */
 931         const struct drm_connector *audio_connector;
 932 };
 933
 934 struct intel_dp_mst_encoder {
 935         struct intel_encoder base;
 936         enum pipe pipe;
 937         struct intel_digital_port *primary;
 938         struct intel_connector *connector;
 939 };
 940
 941 static inline enum dpio_channel
 942 vlv_dport_to_channel(struct intel_digital_port *dport)
 943 {
 944         switch (dport->port) {
 945         case PORT_B:
 946         case PORT_D:
 947                 return DPIO_CH0;
 948         case PORT_C:
 949                 return DPIO_CH1;
 950         default:
 951                 BUG();
 952         }
 953 }
 954
 955 static inline enum dpio_phy
 956 vlv_dport_to_phy(struct intel_digital_port *dport)
 957 {
 958         switch (dport->port) {
 959         case PORT_B:
 960         case PORT_C:
 961                 return DPIO_PHY0;
 962         case PORT_D:
 963                 return DPIO_PHY1;
 964         default:
 965                 BUG();
 966         }
 967 }
 968
 969 static inline enum dpio_channel
 970 vlv_pipe_to_channel(enum pipe pipe)
 971 {
 972         switch (pipe) {
 973         case PIPE_A:
 974         case PIPE_C:
 975                 return DPIO_CH0;
 976         case PIPE_B:
 977                 return DPIO_CH1;
 978         default:
 979                 BUG();
 980         }
 981 }
 982
 983 static inline struct drm_crtc *
 984 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 985 {
 986         struct drm_i915_private *dev_priv = to_i915(dev);
 987         return dev_priv->pipe_to_crtc_mapping[pipe];
 988 }
 989
 990 static inline struct drm_crtc *
 991 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 992 {
 993         struct drm_i915_private *dev_priv = to_i915(dev);
 994         return dev_priv->plane_to_crtc_mapping[plane];
 995 }
 996
 997 struct intel_flip_work {
 998         struct work_struct unpin_work;
 999         struct work_struct mmio_work;
1000
1001         struct drm_crtc *crtc;
1002         struct drm_framebuffer *old_fb;
1003         struct drm_i915_gem_object *pending_flip_obj;
1004         struct drm_pending_vblank_event *event;
1005         atomic_t pending;
1006         u32 flip_count;
1007         u32 gtt_offset;
1008         struct drm_i915_gem_request *flip_queued_req;
1009         u32 flip_queued_vblank;
1010         u32 flip_ready_vblank;
1011         unsigned int rotation;
1012 };
1013
1014 struct intel_load_detect_pipe {
1015         struct drm_atomic_state *restore_state;
1016 };
1017
1018 static inline struct intel_encoder *
1019 intel_attached_encoder(struct drm_connector *connector)
1020 {
1021         return to_intel_connector(connector)->encoder;
1022 }
1023
1024 static inline struct intel_digital_port *
1025 enc_to_dig_port(struct drm_encoder *encoder)
1026 {
1027         return container_of(encoder, struct intel_digital_port, base.base);
1028 }
1029
1030 static inline struct intel_dp_mst_encoder *
1031 enc_to_mst(struct drm_encoder *encoder)
1032 {
1033         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1034 }
1035
1036 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1037 {
1038         return &enc_to_dig_port(encoder)->dp;
1039 }
1040
1041 static inline struct intel_digital_port *
1042 dp_to_dig_port(struct intel_dp *intel_dp)
1043 {
1044         return container_of(intel_dp, struct intel_digital_port, dp);
1045 }
1046
1047 static inline struct intel_digital_port *
1048 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1049 {
1050         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1051 }
1052
1053 /*
1054  * Returns the number of planes for this pipe, ie the number of sprites + 1
1055  * (primary plane). This doesn't count the cursor plane then.
1056  */
1057 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1058 {
1059         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1060 }
1061
1062 /* intel_fifo_underrun.c */
1063 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1064                                            enum pipe pipe, bool enable);
1065 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1066                                            enum transcoder pch_transcoder,
1067                                            bool enable);
1068 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1069                                          enum pipe pipe);
1070 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1071                                          enum transcoder pch_transcoder);
1072 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1073 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1074
1075 /* i915_irq.c */
1076 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1077 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1078 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1079 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1080 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1081 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1082 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1083 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1084 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1085 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1086 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1087 {
1088         /*
1089          * We only use drm_irq_uninstall() at unload and VT switch, so
1090          * this is the only thing we need to check.
1091          */
1092         return dev_priv->pm.irqs_enabled;
1093 }
1094
1095 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1096 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1097                                      unsigned int pipe_mask);
1098 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1099                                      unsigned int pipe_mask);
1100
1101 /* intel_crt.c */
1102 void intel_crt_init(struct drm_device *dev);
1103 void intel_crt_reset(struct drm_encoder *encoder);
1104
1105 /* intel_ddi.c */
1106 void intel_ddi_clk_select(struct intel_encoder *encoder,
1107                           const struct intel_crtc_state *pipe_config);
1108 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
1109 void hsw_fdi_link_train(struct drm_crtc *crtc);
1110 void intel_ddi_init(struct drm_device *dev, enum port port);
1111 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1112 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1113 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1114 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1115                                        enum transcoder cpu_transcoder);
1116 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1117 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1118 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1119                           struct intel_crtc_state *crtc_state);
1120 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1121 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1122 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1123 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1124 void intel_ddi_get_config(struct intel_encoder *encoder,
1125                           struct intel_crtc_state *pipe_config);
1126 struct intel_encoder *
1127 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1128
1129 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1130 void intel_ddi_clock_get(struct intel_encoder *encoder,
1131                          struct intel_crtc_state *pipe_config);
1132 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1133 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1134
1135 unsigned int intel_fb_align_height(struct drm_device *dev,
1136                                    unsigned int height,
1137                                    uint32_t pixel_format,
1138                                    uint64_t fb_format_modifier);
1139 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1140                               uint64_t fb_modifier, uint32_t pixel_format);
1141
1142 /* intel_audio.c */
1143 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1144 void intel_audio_codec_enable(struct intel_encoder *encoder);
1145 void intel_audio_codec_disable(struct intel_encoder *encoder);
1146 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1147 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1148
1149 /* intel_display.c */
1150 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1151 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1152 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1153                       const char *name, u32 reg, int ref_freq);
1154 extern const struct drm_plane_funcs intel_plane_funcs;
1155 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1156 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1157 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1158 void intel_mark_busy(struct drm_i915_private *dev_priv);
1159 void intel_mark_idle(struct drm_i915_private *dev_priv);
1160 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1161 int intel_display_suspend(struct drm_device *dev);
1162 void intel_encoder_destroy(struct drm_encoder *encoder);
1163 int intel_connector_init(struct intel_connector *);
1164 struct intel_connector *intel_connector_alloc(void);
1165 bool intel_connector_get_hw_state(struct intel_connector *connector);
1166 void intel_connector_attach_encoder(struct intel_connector *connector,
1167                                     struct intel_encoder *encoder);
1168 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1169                                              struct drm_crtc *crtc);
1170 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1171 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1172                                 struct drm_file *file_priv);
1173 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1174                                              enum pipe pipe);
1175 static inline bool
1176 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1177                     enum intel_output_type type)
1178 {
1179         return crtc_state->output_types & (1 << type);
1180 }
1181 static inline bool
1182 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1183 {
1184         return crtc_state->output_types &
1185                 ((1 << INTEL_OUTPUT_DP) |
1186                  (1 << INTEL_OUTPUT_DP_MST) |
1187                  (1 << INTEL_OUTPUT_EDP));
1188 }
1189 static inline void
1190 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1191 {
1192         drm_wait_one_vblank(dev, pipe);
1193 }
1194 static inline void
1195 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1196 {
1197         const struct intel_crtc *crtc =
1198                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1199
1200         if (crtc->active)
1201                 intel_wait_for_vblank(dev, pipe);
1202 }
1203
1204 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1205
1206 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1207 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1208                          struct intel_digital_port *dport,
1209                          unsigned int expected_mask);
1210 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1211                                 struct drm_display_mode *mode,
1212                                 struct intel_load_detect_pipe *old,
1213                                 struct drm_modeset_acquire_ctx *ctx);
1214 void intel_release_load_detect_pipe(struct drm_connector *connector,
1215                                     struct intel_load_detect_pipe *old,
1216                                     struct drm_modeset_acquire_ctx *ctx);
1217 int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1218                                unsigned int rotation);
1219 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1220 struct drm_framebuffer *
1221 __intel_framebuffer_create(struct drm_device *dev,
1222                            struct drm_mode_fb_cmd2 *mode_cmd,
1223                            struct drm_i915_gem_object *obj);
1224 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1225 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1226 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1227 int intel_prepare_plane_fb(struct drm_plane *plane,
1228                            const struct drm_plane_state *new_state);
1229 void intel_cleanup_plane_fb(struct drm_plane *plane,
1230                             const struct drm_plane_state *old_state);
1231 int intel_plane_atomic_get_property(struct drm_plane *plane,
1232                                     const struct drm_plane_state *state,
1233                                     struct drm_property *property,
1234                                     uint64_t *val);
1235 int intel_plane_atomic_set_property(struct drm_plane *plane,
1236                                     struct drm_plane_state *state,
1237                                     struct drm_property *property,
1238                                     uint64_t val);
1239 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1240                                     struct drm_plane_state *plane_state);
1241
1242 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1243                                uint64_t fb_modifier, unsigned int cpp);
1244
1245 static inline bool
1246 intel_rotation_90_or_270(unsigned int rotation)
1247 {
1248         return rotation & (DRM_ROTATE_90 | DRM_ROTATE_270);
1249 }
1250
1251 void intel_create_rotation_property(struct drm_device *dev,
1252                                         struct intel_plane *plane);
1253
1254 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1255                                     enum pipe pipe);
1256
1257 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1258                      const struct dpll *dpll);
1259 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1260 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1261
1262 /* modesetting asserts */
1263 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1264                            enum pipe pipe);
1265 void assert_pll(struct drm_i915_private *dev_priv,
1266                 enum pipe pipe, bool state);
1267 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1268 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1269 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1270 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1271 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1272 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1273                        enum pipe pipe, bool state);
1274 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1275 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1276 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1277 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1278 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1279 u32 intel_compute_tile_offset(int *x, int *y,
1280                               const struct drm_framebuffer *fb, int plane,
1281                               unsigned int pitch,
1282                               unsigned int rotation);
1283 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1284 void intel_finish_reset(struct drm_i915_private *dev_priv);
1285 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1286 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1287 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1288 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1289 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1290 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1291 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1292                             enum dpio_phy phy);
1293 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1294                               enum dpio_phy phy);
1295 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1296 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1297 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1298 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1299 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1300 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1301 unsigned int skl_cdclk_get_vco(unsigned int freq);
1302 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1303 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1304 void intel_dp_get_m_n(struct intel_crtc *crtc,
1305                       struct intel_crtc_state *pipe_config);
1306 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1307 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1308 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1309                         struct dpll *best_clock);
1310 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1311
1312 bool intel_crtc_active(struct drm_crtc *crtc);
1313 void hsw_enable_ips(struct intel_crtc *crtc);
1314 void hsw_disable_ips(struct intel_crtc *crtc);
1315 enum intel_display_power_domain
1316 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1317 enum intel_display_power_domain
1318 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1319 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1320                                  struct intel_crtc_state *pipe_config);
1321
1322 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1323 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1324
1325 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1326                            struct drm_i915_gem_object *obj,
1327                            unsigned int plane);
1328
1329 u32 skl_plane_ctl_format(uint32_t pixel_format);
1330 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1331 u32 skl_plane_ctl_rotation(unsigned int rotation);
1332
1333 /* intel_csr.c */
1334 void intel_csr_ucode_init(struct drm_i915_private *);
1335 void intel_csr_load_program(struct drm_i915_private *);
1336 void intel_csr_ucode_fini(struct drm_i915_private *);
1337 void intel_csr_ucode_suspend(struct drm_i915_private *);
1338 void intel_csr_ucode_resume(struct drm_i915_private *);
1339
1340 /* intel_dp.c */
1341 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1342 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1343                              struct intel_connector *intel_connector);
1344 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1345                               const struct intel_crtc_state *pipe_config);
1346 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1347 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1348 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1349 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1350 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1351 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1352 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1353 bool intel_dp_compute_config(struct intel_encoder *encoder,
1354                              struct intel_crtc_state *pipe_config);
1355 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1356 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1357                                   bool long_hpd);
1358 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1359 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1360 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1361 void intel_edp_panel_on(struct intel_dp *intel_dp);
1362 void intel_edp_panel_off(struct intel_dp *intel_dp);
1363 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1364 void intel_dp_mst_suspend(struct drm_device *dev);
1365 void intel_dp_mst_resume(struct drm_device *dev);
1366 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1367 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1368 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1369 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1370 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1371 void intel_plane_destroy(struct drm_plane *plane);
1372 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1373 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1374 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1375                                unsigned int frontbuffer_bits);
1376 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1377                           unsigned int frontbuffer_bits);
1378 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1379                                   struct intel_digital_port *port);
1380
1381 void
1382 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1383                                        uint8_t dp_train_pat);
1384 void
1385 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1386 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1387 uint8_t
1388 intel_dp_voltage_max(struct intel_dp *intel_dp);
1389 uint8_t
1390 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1391 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1392                            uint8_t *link_bw, uint8_t *rate_select);
1393 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1394 bool
1395 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1396
1397 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1398 {
1399         return ~((1 << lane_count) - 1) & 0xf;
1400 }
1401
1402 /* intel_dp_aux_backlight.c */
1403 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1404
1405 /* intel_dp_mst.c */
1406 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1407 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1408 /* intel_dsi.c */
1409 void intel_dsi_init(struct drm_device *dev);
1410
1411 /* intel_dsi_dcs_backlight.c */
1412 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1413
1414 /* intel_dvo.c */
1415 void intel_dvo_init(struct drm_device *dev);
1416 /* intel_hotplug.c */
1417 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1418
1419
1420 /* legacy fbdev emulation in intel_fbdev.c */
1421 #ifdef CONFIG_DRM_FBDEV_EMULATION
1422 extern int intel_fbdev_init(struct drm_device *dev);
1423 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1424 extern void intel_fbdev_fini(struct drm_device *dev);
1425 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1426 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1427 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1428 #else
1429 static inline int intel_fbdev_init(struct drm_device *dev)
1430 {
1431         return 0;
1432 }
1433
1434 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1435 {
1436 }
1437
1438 static inline void intel_fbdev_fini(struct drm_device *dev)
1439 {
1440 }
1441
1442 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1443 {
1444 }
1445
1446 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1447 {
1448 }
1449 #endif
1450
1451 /* intel_fbc.c */
1452 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1453                            struct drm_atomic_state *state);
1454 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1455 void intel_fbc_pre_update(struct intel_crtc *crtc,
1456                           struct intel_crtc_state *crtc_state,
1457                           struct intel_plane_state *plane_state);
1458 void intel_fbc_post_update(struct intel_crtc *crtc);
1459 void intel_fbc_init(struct drm_i915_private *dev_priv);
1460 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1461 void intel_fbc_enable(struct intel_crtc *crtc,
1462                       struct intel_crtc_state *crtc_state,
1463                       struct intel_plane_state *plane_state);
1464 void intel_fbc_disable(struct intel_crtc *crtc);
1465 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1466 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1467                           unsigned int frontbuffer_bits,
1468                           enum fb_op_origin origin);
1469 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1470                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1471 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1472
1473 /* intel_hdmi.c */
1474 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1475 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1476                                struct intel_connector *intel_connector);
1477 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1478 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1479                                struct intel_crtc_state *pipe_config);
1480 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1481
1482
1483 /* intel_lvds.c */
1484 void intel_lvds_init(struct drm_device *dev);
1485 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1486 bool intel_is_dual_link_lvds(struct drm_device *dev);
1487
1488
1489 /* intel_modes.c */
1490 int intel_connector_update_modes(struct drm_connector *connector,
1491                                  struct edid *edid);
1492 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1493 void intel_attach_force_audio_property(struct drm_connector *connector);
1494 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1495 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1496
1497
1498 /* intel_overlay.c */
1499 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1500 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1501 int intel_overlay_switch_off(struct intel_overlay *overlay);
1502 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1503                                   struct drm_file *file_priv);
1504 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1505                               struct drm_file *file_priv);
1506 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1507
1508
1509 /* intel_panel.c */
1510 int intel_panel_init(struct intel_panel *panel,
1511                      struct drm_display_mode *fixed_mode,
1512                      struct drm_display_mode *downclock_mode);
1513 void intel_panel_fini(struct intel_panel *panel);
1514 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1515                             struct drm_display_mode *adjusted_mode);
1516 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1517                              struct intel_crtc_state *pipe_config,
1518                              int fitting_mode);
1519 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1520                               struct intel_crtc_state *pipe_config,
1521                               int fitting_mode);
1522 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1523                                     u32 level, u32 max);
1524 int intel_panel_setup_backlight(struct drm_connector *connector,
1525                                 enum pipe pipe);
1526 void intel_panel_enable_backlight(struct intel_connector *connector);
1527 void intel_panel_disable_backlight(struct intel_connector *connector);
1528 void intel_panel_destroy_backlight(struct drm_connector *connector);
1529 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1530 extern struct drm_display_mode *intel_find_panel_downclock(
1531                                 struct drm_device *dev,
1532                                 struct drm_display_mode *fixed_mode,
1533                                 struct drm_connector *connector);
1534
1535 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1536 int intel_backlight_device_register(struct intel_connector *connector);
1537 void intel_backlight_device_unregister(struct intel_connector *connector);
1538 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1539 static int intel_backlight_device_register(struct intel_connector *connector)
1540 {
1541         return 0;
1542 }
1543 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1544 {
1545 }
1546 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1547
1548
1549 /* intel_psr.c */
1550 void intel_psr_enable(struct intel_dp *intel_dp);
1551 void intel_psr_disable(struct intel_dp *intel_dp);
1552 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1553                           unsigned frontbuffer_bits);
1554 void intel_psr_flush(struct drm_i915_private *dev_priv,
1555                      unsigned frontbuffer_bits,
1556                      enum fb_op_origin origin);
1557 void intel_psr_init(struct drm_device *dev);
1558 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1559                                    unsigned frontbuffer_bits);
1560
1561 /* intel_runtime_pm.c */
1562 int intel_power_domains_init(struct drm_i915_private *);
1563 void intel_power_domains_fini(struct drm_i915_private *);
1564 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1565 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1566 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1567 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1568 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1569 const char *
1570 intel_display_power_domain_str(enum intel_display_power_domain domain);
1571
1572 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1573                                     enum intel_display_power_domain domain);
1574 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1575                                       enum intel_display_power_domain domain);
1576 void intel_display_power_get(struct drm_i915_private *dev_priv,
1577                              enum intel_display_power_domain domain);
1578 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1579                                         enum intel_display_power_domain domain);
1580 void intel_display_power_put(struct drm_i915_private *dev_priv,
1581                              enum intel_display_power_domain domain);
1582
1583 static inline void
1584 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1585 {
1586         WARN_ONCE(dev_priv->pm.suspended,
1587                   "Device suspended during HW access\n");
1588 }
1589
1590 static inline void
1591 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1592 {
1593         assert_rpm_device_not_suspended(dev_priv);
1594         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1595          * too much noise. */
1596         if (!atomic_read(&dev_priv->pm.wakeref_count))
1597                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1598 }
1599
1600 static inline int
1601 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1602 {
1603         int seq = atomic_read(&dev_priv->pm.atomic_seq);
1604
1605         assert_rpm_wakelock_held(dev_priv);
1606
1607         return seq;
1608 }
1609
1610 static inline void
1611 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1612 {
1613         WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1614                   "HW access outside of RPM atomic section\n");
1615 }
1616
1617 /**
1618  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1619  * @dev_priv: i915 device instance
1620  *
1621  * This function disable asserts that check if we hold an RPM wakelock
1622  * reference, while keeping the device-not-suspended checks still enabled.
1623  * It's meant to be used only in special circumstances where our rule about
1624  * the wakelock refcount wrt. the device power state doesn't hold. According
1625  * to this rule at any point where we access the HW or want to keep the HW in
1626  * an active state we must hold an RPM wakelock reference acquired via one of
1627  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1628  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1629  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1630  * users should avoid using this function.
1631  *
1632  * Any calls to this function must have a symmetric call to
1633  * enable_rpm_wakeref_asserts().
1634  */
1635 static inline void
1636 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1637 {
1638         atomic_inc(&dev_priv->pm.wakeref_count);
1639 }
1640
1641 /**
1642  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1643  * @dev_priv: i915 device instance
1644  *
1645  * This function re-enables the RPM assert checks after disabling them with
1646  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1647  * circumstances otherwise its use should be avoided.
1648  *
1649  * Any calls to this function must have a symmetric call to
1650  * disable_rpm_wakeref_asserts().
1651  */
1652 static inline void
1653 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1654 {
1655         atomic_dec(&dev_priv->pm.wakeref_count);
1656 }
1657
1658 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1659 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1660 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1661 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1662
1663 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1664
1665 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1666                              bool override, unsigned int mask);
1667 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1668                           enum dpio_channel ch, bool override);
1669
1670
1671 /* intel_pm.c */
1672 void intel_init_clock_gating(struct drm_device *dev);
1673 void intel_suspend_hw(struct drm_device *dev);
1674 int ilk_wm_max_level(const struct drm_device *dev);
1675 void intel_update_watermarks(struct drm_crtc *crtc);
1676 void intel_init_pm(struct drm_device *dev);
1677 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1678 void intel_pm_setup(struct drm_device *dev);
1679 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1680 void intel_gpu_ips_teardown(void);
1681 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1682 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1683 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1684 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1685 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1686 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1687 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1688 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1689 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1690 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1691 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1692                     struct intel_rps_client *rps,
1693                     unsigned long submitted);
1694 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1695 void vlv_wm_get_hw_state(struct drm_device *dev);
1696 void ilk_wm_get_hw_state(struct drm_device *dev);
1697 void skl_wm_get_hw_state(struct drm_device *dev);
1698 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1699                           struct skl_ddb_allocation *ddb /* out */);
1700 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1701 bool ilk_disable_lp_wm(struct drm_device *dev);
1702 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1703 static inline int intel_enable_rc6(void)
1704 {
1705         return i915.enable_rc6;
1706 }
1707
1708 /* intel_sdvo.c */
1709 bool intel_sdvo_init(struct drm_device *dev,
1710                      i915_reg_t reg, enum port port);
1711
1712
1713 /* intel_sprite.c */
1714 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1715                              int usecs);
1716 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1717 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1718                               struct drm_file *file_priv);
1719 void intel_pipe_update_start(struct intel_crtc *crtc);
1720 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1721
1722 /* intel_tv.c */
1723 void intel_tv_init(struct drm_device *dev);
1724
1725 /* intel_atomic.c */
1726 int intel_connector_atomic_get_property(struct drm_connector *connector,
1727                                         const struct drm_connector_state *state,
1728                                         struct drm_property *property,
1729                                         uint64_t *val);
1730 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1731 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1732                                struct drm_crtc_state *state);
1733 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1734 void intel_atomic_state_clear(struct drm_atomic_state *);
1735 struct intel_shared_dpll_config *
1736 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1737
1738 static inline struct intel_crtc_state *
1739 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1740                             struct intel_crtc *crtc)
1741 {
1742         struct drm_crtc_state *crtc_state;
1743         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1744         if (IS_ERR(crtc_state))
1745                 return ERR_CAST(crtc_state);
1746
1747         return to_intel_crtc_state(crtc_state);
1748 }
1749
1750 static inline struct intel_plane_state *
1751 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1752                                       struct intel_plane *plane)
1753 {
1754         struct drm_plane_state *plane_state;
1755
1756         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1757
1758         return to_intel_plane_state(plane_state);
1759 }
1760
1761 int intel_atomic_setup_scalers(struct drm_device *dev,
1762         struct intel_crtc *intel_crtc,
1763         struct intel_crtc_state *crtc_state);
1764
1765 /* intel_atomic_plane.c */
1766 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1767 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1768 void intel_plane_destroy_state(struct drm_plane *plane,
1769                                struct drm_plane_state *state);
1770 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1771
1772 /* intel_color.c */
1773 void intel_color_init(struct drm_crtc *crtc);
1774 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1775 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1776 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1777
1778 #endif /* __INTEL_DRV_H__ */