2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
44 * __wait_for - magic wait macro
46 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
47 * important that we check the condition again after having timed out, since the
48 * timeout could be due to preemption or similar and we've never had a chance to
49 * check the condition before the timeout.
51 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
52 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
53 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
57 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
59 /* Guarantee COND check prior to timeout */ \
69 usleep_range(wait__, wait__ * 2); \
70 if (wait__ < (Wmax)) \
76 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
78 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
80 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
81 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
82 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
84 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
87 #define _wait_for_atomic(COND, US, ATOMIC) \
89 int cpu, ret, timeout = (US) * 1000; \
91 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
94 cpu = smp_processor_id(); \
96 base = local_clock(); \
98 u64 now = local_clock(); \
101 /* Guarantee COND check prior to timeout */ \
107 if (now - base >= timeout) { \
114 if (unlikely(cpu != smp_processor_id())) { \
115 timeout -= now - base; \
116 cpu = smp_processor_id(); \
117 base = local_clock(); \
124 #define wait_for_us(COND, US) \
127 BUILD_BUG_ON(!__builtin_constant_p(US)); \
129 ret__ = _wait_for((COND), (US), 10, 10); \
131 ret__ = _wait_for_atomic((COND), (US), 0); \
135 #define wait_for_atomic_us(COND, US) \
137 BUILD_BUG_ON(!__builtin_constant_p(US)); \
138 BUILD_BUG_ON((US) > 50000); \
139 _wait_for_atomic((COND), (US), 1); \
142 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
144 #define KHz(x) (1000 * (x))
145 #define MHz(x) KHz(1000 * (x))
147 #define KBps(x) (1000 * (x))
148 #define MBps(x) KBps(1000 * (x))
149 #define GBps(x) ((u64)1000 * MBps((x)))
152 * Display related stuff
155 /* store information about an Ixxx DVO */
156 /* The i830->i865 use multiple DVOs with multiple i2cs */
157 /* the i915, i945 have a single sDVO i2c bus - which is different */
158 #define MAX_OUTPUTS 6
159 /* maximum connectors per crtcs in the mode set */
161 #define INTEL_I2C_BUS_DVO 1
162 #define INTEL_I2C_BUS_SDVO 2
164 /* these are outputs from the chip - integrated only
165 external chips are via DVO or SDVO output */
166 enum intel_output_type {
167 INTEL_OUTPUT_UNUSED = 0,
168 INTEL_OUTPUT_ANALOG = 1,
169 INTEL_OUTPUT_DVO = 2,
170 INTEL_OUTPUT_SDVO = 3,
171 INTEL_OUTPUT_LVDS = 4,
172 INTEL_OUTPUT_TVOUT = 5,
173 INTEL_OUTPUT_HDMI = 6,
175 INTEL_OUTPUT_EDP = 8,
176 INTEL_OUTPUT_DSI = 9,
177 INTEL_OUTPUT_DDI = 10,
178 INTEL_OUTPUT_DP_MST = 11,
181 #define INTEL_DVO_CHIP_NONE 0
182 #define INTEL_DVO_CHIP_LVDS 1
183 #define INTEL_DVO_CHIP_TMDS 2
184 #define INTEL_DVO_CHIP_TVOUT 4
186 #define INTEL_DSI_VIDEO_MODE 0
187 #define INTEL_DSI_COMMAND_MODE 1
189 struct intel_framebuffer {
190 struct drm_framebuffer base;
191 struct intel_rotation_info rot_info;
193 /* for each plane in the normal GTT view */
197 /* for each plane in the rotated GTT view */
200 unsigned int pitch; /* pixels */
205 struct drm_fb_helper helper;
206 struct intel_framebuffer *fb;
207 struct i915_vma *vma;
208 unsigned long vma_flags;
209 async_cookie_t cookie;
213 struct intel_encoder {
214 struct drm_encoder base;
216 enum intel_output_type type;
218 unsigned int cloneable;
219 bool (*hotplug)(struct intel_encoder *encoder,
220 struct intel_connector *connector);
221 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
222 struct intel_crtc_state *,
223 struct drm_connector_state *);
224 bool (*compute_config)(struct intel_encoder *,
225 struct intel_crtc_state *,
226 struct drm_connector_state *);
227 void (*pre_pll_enable)(struct intel_encoder *,
228 const struct intel_crtc_state *,
229 const struct drm_connector_state *);
230 void (*pre_enable)(struct intel_encoder *,
231 const struct intel_crtc_state *,
232 const struct drm_connector_state *);
233 void (*enable)(struct intel_encoder *,
234 const struct intel_crtc_state *,
235 const struct drm_connector_state *);
236 void (*disable)(struct intel_encoder *,
237 const struct intel_crtc_state *,
238 const struct drm_connector_state *);
239 void (*post_disable)(struct intel_encoder *,
240 const struct intel_crtc_state *,
241 const struct drm_connector_state *);
242 void (*post_pll_disable)(struct intel_encoder *,
243 const struct intel_crtc_state *,
244 const struct drm_connector_state *);
245 /* Read out the current hw state of this connector, returning true if
246 * the encoder is active. If the encoder is enabled it also set the pipe
247 * it is connected to in the pipe parameter. */
248 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
249 /* Reconstructs the equivalent mode flags for the current hardware
250 * state. This must be called _after_ display->get_pipe_config has
251 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
252 * be set correctly before calling this function. */
253 void (*get_config)(struct intel_encoder *,
254 struct intel_crtc_state *pipe_config);
255 /* Returns a mask of power domains that need to be referenced as part
256 * of the hardware state readout code. */
257 u64 (*get_power_domains)(struct intel_encoder *encoder,
258 struct intel_crtc_state *crtc_state);
260 * Called during system suspend after all pending requests for the
261 * encoder are flushed (for example for DP AUX transactions) and
262 * device interrupts are disabled.
264 void (*suspend)(struct intel_encoder *);
266 enum hpd_pin hpd_pin;
267 enum intel_display_power_domain power_domain;
268 /* for communication with audio component; protected by av_mutex */
269 const struct drm_connector *audio_connector;
273 struct drm_display_mode *fixed_mode;
274 struct drm_display_mode *downclock_mode;
283 bool combination_mode; /* gen 2/4 only */
285 bool alternate_pwm_increment; /* lpt+ */
288 bool util_pin_active_low; /* bxt+ */
289 u8 controller; /* bxt+ only */
290 struct pwm_device *pwm;
292 struct backlight_device *device;
294 /* Connector and platform specific backlight functions */
295 int (*setup)(struct intel_connector *connector, enum pipe pipe);
296 uint32_t (*get)(struct intel_connector *connector);
297 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
298 void (*disable)(const struct drm_connector_state *conn_state);
299 void (*enable)(const struct intel_crtc_state *crtc_state,
300 const struct drm_connector_state *conn_state);
301 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
303 void (*power)(struct intel_connector *, bool enable);
307 struct intel_digital_port;
310 * This structure serves as a translation layer between the generic HDCP code
311 * and the bus-specific code. What that means is that HDCP over HDMI differs
312 * from HDCP over DP, so to account for these differences, we need to
313 * communicate with the receiver through this shim.
315 * For completeness, the 2 buses differ in the following ways:
317 * HDCP registers on the receiver are set via DP AUX for DP, and
318 * they are set via DDC for HDMI.
319 * - Receiver register offsets
320 * The offsets of the registers are different for DP vs. HDMI
321 * - Receiver register masks/offsets
322 * For instance, the ready bit for the KSV fifo is in a different
323 * place on DP vs HDMI
324 * - Receiver register names
325 * Seriously. In the DP spec, the 16-bit register containing
326 * downstream information is called BINFO, on HDMI it's called
327 * BSTATUS. To confuse matters further, DP has a BSTATUS register
328 * with a completely different definition.
330 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
331 * be read 3 keys at a time
333 * Since Aksv is hidden in hardware, there's different procedures
334 * to send it over DP AUX vs DDC
336 struct intel_hdcp_shim {
337 /* Outputs the transmitter's An and Aksv values to the receiver. */
338 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
340 /* Reads the receiver's key selection vector */
341 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
344 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
345 * definitions are the same in the respective specs, but the names are
346 * different. Call it BSTATUS since that's the name the HDMI spec
347 * uses and it was there first.
349 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
352 /* Determines whether a repeater is present downstream */
353 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
354 bool *repeater_present);
356 /* Reads the receiver's Ri' value */
357 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
359 /* Determines if the receiver's KSV FIFO is ready for consumption */
360 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
363 /* Reads the ksv fifo for num_downstream devices */
364 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
365 int num_downstream, u8 *ksv_fifo);
367 /* Reads a 32-bit part of V' from the receiver */
368 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
371 /* Enables HDCP signalling on the port */
372 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
375 /* Ensures the link is still protected */
376 bool (*check_link)(struct intel_digital_port *intel_dig_port);
378 /* Detects panel's hdcp capability. This is optional for HDMI. */
379 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
383 struct intel_connector {
384 struct drm_connector base;
386 * The fixed encoder this connector is connected to.
388 struct intel_encoder *encoder;
390 /* ACPI device id for ACPI and driver cooperation */
393 /* Reads out the current hw, returning true if the connector is enabled
394 * and active (i.e. dpms ON state). */
395 bool (*get_hw_state)(struct intel_connector *);
397 /* Panel info for eDP and LVDS */
398 struct intel_panel panel;
400 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
402 struct edid *detect_edid;
404 /* since POLL and HPD connectors may use the same HPD line keep the native
405 state of connector->polled in case hotplug storm detection changes it */
408 void *port; /* store this opaque as its illegal to dereference it */
410 struct intel_dp *mst_port;
412 /* Work struct to schedule a uevent on link train failure */
413 struct work_struct modeset_retry_work;
415 const struct intel_hdcp_shim *hdcp_shim;
416 struct mutex hdcp_mutex;
417 uint64_t hdcp_value; /* protected by hdcp_mutex */
418 struct delayed_work hdcp_check_work;
419 struct work_struct hdcp_prop_work;
422 struct intel_digital_connector_state {
423 struct drm_connector_state base;
425 enum hdmi_force_audio force_audio;
429 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
443 struct intel_atomic_state {
444 struct drm_atomic_state base;
448 * Logical state of cdclk (used for all scaling, watermark,
449 * etc. calculations and checks). This is computed as if all
450 * enabled crtcs were active.
452 struct intel_cdclk_state logical;
455 * Actual state of cdclk, can be different from the logical
456 * state only when all crtc's are DPMS off.
458 struct intel_cdclk_state actual;
461 bool dpll_set, modeset;
464 * Does this transaction change the pipes that are active? This mask
465 * tracks which CRTC's have changed their active state at the end of
466 * the transaction (not counting the temporary disable during modesets).
467 * This mask should only be non-zero when intel_state->modeset is true,
468 * but the converse is not necessarily true; simply changing a mode may
469 * not flip the final active status of any CRTC's
471 unsigned int active_pipe_changes;
473 unsigned int active_crtcs;
474 /* minimum acceptable cdclk for each pipe */
475 int min_cdclk[I915_MAX_PIPES];
476 /* minimum acceptable voltage level for each pipe */
477 u8 min_voltage_level[I915_MAX_PIPES];
479 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
482 * Current watermarks can't be trusted during hardware readout, so
483 * don't bother calculating intermediate watermarks.
485 bool skip_intermediate_wm;
488 struct skl_ddb_values wm_results;
490 struct i915_sw_fence commit_ready;
492 struct llist_node freed;
495 struct intel_plane_state {
496 struct drm_plane_state base;
497 struct i915_vma *vma;
499 #define PLANE_HAS_FENCE BIT(0)
510 /* plane control register */
513 /* plane color control register */
518 * = -1 : not using a scaler
519 * >= 0 : using a scalers
521 * plane requiring a scaler:
522 * - During check_plane, its bit is set in
523 * crtc_state->scaler_state.scaler_users by calling helper function
524 * update_scaler_plane.
525 * - scaler_id indicates the scaler it got assigned.
527 * plane doesn't require a scaler:
528 * - this can happen when scaling is no more required or plane simply
530 * - During check_plane, corresponding bit is reset in
531 * crtc_state->scaler_state.scaler_users by calling helper function
532 * update_scaler_plane.
536 struct drm_intel_sprite_colorkey ckey;
539 struct intel_initial_plane_config {
540 struct intel_framebuffer *fb;
546 #define SKL_MIN_SRC_W 8
547 #define SKL_MAX_SRC_W 4096
548 #define SKL_MIN_SRC_H 8
549 #define SKL_MAX_SRC_H 4096
550 #define SKL_MIN_DST_W 8
551 #define SKL_MAX_DST_W 4096
552 #define SKL_MIN_DST_H 8
553 #define SKL_MAX_DST_H 4096
554 #define ICL_MAX_SRC_W 5120
555 #define ICL_MAX_SRC_H 4096
556 #define ICL_MAX_DST_W 5120
557 #define ICL_MAX_DST_H 4096
558 #define SKL_MIN_YUV_420_SRC_W 16
559 #define SKL_MIN_YUV_420_SRC_H 16
561 struct intel_scaler {
566 struct intel_crtc_scaler_state {
567 #define SKL_NUM_SCALERS 2
568 struct intel_scaler scalers[SKL_NUM_SCALERS];
571 * scaler_users: keeps track of users requesting scalers on this crtc.
573 * If a bit is set, a user is using a scaler.
574 * Here user can be a plane or crtc as defined below:
575 * bits 0-30 - plane (bit position is index from drm_plane_index)
578 * Instead of creating a new index to cover planes and crtc, using
579 * existing drm_plane_index for planes which is well less than 31
580 * planes and bit 31 for crtc. This should be fine to cover all
583 * intel_atomic_setup_scalers will setup available scalers to users
584 * requesting scalers. It will gracefully fail if request exceeds
587 #define SKL_CRTC_INDEX 31
588 unsigned scaler_users;
590 /* scaler used by crtc for panel fitting purpose */
594 /* drm_mode->private_flags */
595 #define I915_MODE_FLAG_INHERITED 1
596 /* Flag to get scanline using frame time stamps */
597 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
599 struct intel_pipe_wm {
600 struct intel_wm_level wm[5];
604 bool sprites_enabled;
608 struct skl_plane_wm {
609 struct skl_wm_level wm[8];
610 struct skl_wm_level uv_wm[8];
611 struct skl_wm_level trans_wm;
616 struct skl_plane_wm planes[I915_MAX_PLANES];
623 VLV_WM_LEVEL_DDR_DVFS,
627 struct vlv_wm_state {
628 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
629 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
634 struct vlv_fifo_state {
635 u16 plane[I915_MAX_PLANES];
645 struct g4x_wm_state {
646 struct g4x_pipe_wm wm;
648 struct g4x_sr_wm hpll;
654 struct intel_crtc_wm_state {
658 * Intermediate watermarks; these can be
659 * programmed immediately since they satisfy
660 * both the current configuration we're
661 * switching away from and the new
662 * configuration we're switching to.
664 struct intel_pipe_wm intermediate;
667 * Optimal watermarks, programmed post-vblank
668 * when this state is committed.
670 struct intel_pipe_wm optimal;
674 /* gen9+ only needs 1-step wm programming */
675 struct skl_pipe_wm optimal;
676 struct skl_ddb_entry ddb;
680 /* "raw" watermarks (not inverted) */
681 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
682 /* intermediate watermarks (inverted) */
683 struct vlv_wm_state intermediate;
684 /* optimal watermarks (inverted) */
685 struct vlv_wm_state optimal;
686 /* display FIFO split */
687 struct vlv_fifo_state fifo_state;
691 /* "raw" watermarks */
692 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
693 /* intermediate watermarks */
694 struct g4x_wm_state intermediate;
695 /* optimal watermarks */
696 struct g4x_wm_state optimal;
701 * Platforms with two-step watermark programming will need to
702 * update watermark programming post-vblank to switch from the
703 * safe intermediate watermarks to the optimal final
706 bool need_postvbl_update;
709 struct intel_crtc_state {
710 struct drm_crtc_state base;
713 * quirks - bitfield with hw state readout quirks
715 * For various reasons the hw state readout code might not be able to
716 * completely faithfully read out the current state. These cases are
717 * tracked with quirk flags so that fastboot and state checker can act
720 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
721 unsigned long quirks;
723 unsigned fb_bits; /* framebuffers to flip */
724 bool update_pipe; /* can a fast modeset be performed? */
726 bool update_wm_pre, update_wm_post; /* watermarks are updated */
727 bool fb_changed; /* fb on any of the planes is changed */
728 bool fifo_changed; /* FIFO split is changed */
730 /* Pipe source size (ie. panel fitter input size)
731 * All planes will be positioned inside this space,
732 * and get clipped at the edges. */
733 int pipe_src_w, pipe_src_h;
736 * Pipe pixel rate, adjusted for
737 * panel fitter/pipe scaler downscaling.
739 unsigned int pixel_rate;
741 /* Whether to set up the PCH/FDI. Note that we never allow sharing
742 * between pch encoders and cpu encoders. */
743 bool has_pch_encoder;
745 /* Are we sending infoframes on the attached port */
748 /* CPU Transcoder for the pipe. Currently this can only differ from the
749 * pipe on Haswell and later (where we have a special eDP transcoder)
750 * and Broxton (where we have special DSI transcoders). */
751 enum transcoder cpu_transcoder;
754 * Use reduced/limited/broadcast rbg range, compressing from the full
755 * range fed into the crtcs.
757 bool limited_color_range;
759 /* Bitmask of encoder types (enum intel_output_type)
760 * driven by the pipe.
762 unsigned int output_types;
764 /* Whether we should send NULL infoframes. Required for audio. */
767 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
768 * has_dp_encoder is set. */
772 * Enable dithering, used when the selected pipe bpp doesn't match the
778 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
779 * compliance video pattern tests.
780 * Disable dither only if it is a compliance test request for
783 bool dither_force_disable;
785 /* Controls for the clock computation, to override various stages. */
788 /* SDVO TV has a bunch of special case. To make multifunction encoders
789 * work correctly, we need to track this at runtime.*/
793 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
794 * required. This is set in the 2nd loop of calling encoder's
795 * ->compute_config if the first pick doesn't work out.
799 /* Settings for the intel dpll used on pretty much everything but
803 /* Selected dpll when shared or NULL. */
804 struct intel_shared_dpll *shared_dpll;
806 /* Actual register state of the dpll, for shared dpll cross-checking. */
807 struct intel_dpll_hw_state dpll_hw_state;
809 /* DSI PLL registers */
815 struct intel_link_m_n dp_m_n;
817 /* m2_n2 for eDP downclock */
818 struct intel_link_m_n dp_m2_n2;
825 * Frequence the dpll for the port should run at. Differs from the
826 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
827 * already multiplied by pixel_multiplier.
831 /* Used by SDVO (and if we ever fix it, HDMI). */
832 unsigned pixel_multiplier;
837 * Used by platforms having DP/HDMI PHY with programmable lane
838 * latency optimization.
840 uint8_t lane_lat_optim_mask;
842 /* minimum acceptable voltage level */
843 u8 min_voltage_level;
845 /* Panel fitter controls for gen2-gen4 + VLV */
849 u32 lvds_border_bits;
852 /* Panel fitter placement and size for Ironlake+ */
860 /* FDI configuration, only valid if has_pch_encoder is set. */
862 struct intel_link_m_n fdi_m_n;
865 bool ips_force_disable;
873 struct intel_crtc_scaler_state scaler_state;
875 /* w/a for waiting 2 vblanks during crtc enable */
876 enum pipe hsw_workaround_pipe;
878 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
881 struct intel_crtc_wm_state wm;
883 /* Gamma mode programmed on the pipe */
886 /* bitmask of visible planes (enum plane_id) */
890 /* HDMI scrambling status */
891 bool hdmi_scrambling;
893 /* HDMI High TMDS char rate ratio */
894 bool hdmi_high_tmds_clock_ratio;
896 /* output format is YCBCR 4:2:0 */
901 struct drm_crtc base;
904 * Whether the crtc and the connected output pipeline is active. Implies
905 * that crtc->enabled is set, i.e. the current mode configuration has
906 * some outputs connected to this crtc.
910 unsigned long long enabled_power_domains;
911 struct intel_overlay *overlay;
913 struct intel_crtc_state *config;
915 /* global reset count when the last flip was submitted */
916 unsigned int reset_count;
918 /* Access to these should be protected by dev_priv->irq_lock. */
919 bool cpu_fifo_underrun_disabled;
920 bool pch_fifo_underrun_disabled;
922 /* per-pipe watermark state */
924 /* watermarks currently being used */
926 struct intel_pipe_wm ilk;
927 struct vlv_wm_state vlv;
928 struct g4x_wm_state g4x;
935 unsigned start_vbl_count;
936 ktime_t start_vbl_time;
937 int min_vbl, max_vbl;
941 /* scalers available on this crtc */
946 struct drm_plane base;
947 enum i9xx_plane_id i9xx_plane;
954 uint32_t frontbuffer_bit;
957 u32 base, cntl, size;
961 * NOTE: Do not place new plane state fields here (e.g., when adding
962 * new plane properties). New runtime state should now be placed in
963 * the intel_plane_state structure and accessed via plane_state.
966 void (*update_plane)(struct intel_plane *plane,
967 const struct intel_crtc_state *crtc_state,
968 const struct intel_plane_state *plane_state);
969 void (*disable_plane)(struct intel_plane *plane,
970 struct intel_crtc *crtc);
971 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
972 int (*check_plane)(struct intel_plane *plane,
973 struct intel_crtc_state *crtc_state,
974 struct intel_plane_state *state);
977 struct intel_watermark_params {
985 struct cxsr_latency {
991 u16 display_hpll_disable;
993 u16 cursor_hpll_disable;
996 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
997 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
998 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
999 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1000 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1001 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1002 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1003 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1004 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1007 i915_reg_t hdmi_reg;
1010 enum drm_dp_dual_mode_type type;
1015 bool rgb_quant_range_selectable;
1016 struct intel_connector *attached_connector;
1019 struct intel_dp_mst_encoder;
1020 #define DP_MAX_DOWNSTREAM_PORTS 0x10
1023 * enum link_m_n_set:
1024 * When platform provides two set of M_N registers for dp, we can
1025 * program them and switch between them incase of DRRS.
1026 * But When only one such register is provided, we have to program the
1027 * required divider value on that registers itself based on the DRRS state.
1029 * M1_N1 : Program dp_m_n on M1_N1 registers
1030 * dp_m2_n2 on M2_N2 registers (If supported)
1032 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1033 * M2_N2 registers are not supported
1037 /* Sets the m1_n1 and m2_n2 */
1042 struct intel_dp_compliance_data {
1044 uint8_t video_pattern;
1045 uint16_t hdisplay, vdisplay;
1049 struct intel_dp_compliance {
1050 unsigned long test_type;
1051 struct intel_dp_compliance_data test_data;
1058 i915_reg_t output_reg;
1067 bool reset_link_params;
1069 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1070 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1071 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1072 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1074 int num_source_rates;
1075 const int *source_rates;
1076 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1078 int sink_rates[DP_MAX_SUPPORTED_RATES];
1079 bool use_rate_select;
1080 /* intersection of source and sink rates */
1081 int num_common_rates;
1082 int common_rates[DP_MAX_SUPPORTED_RATES];
1083 /* Max lane count for the current link */
1084 int max_link_lane_count;
1085 /* Max rate for the current link */
1087 /* sink or branch descriptor */
1088 struct drm_dp_desc desc;
1089 struct drm_dp_aux aux;
1090 enum intel_display_power_domain aux_power_domain;
1091 uint8_t train_set[4];
1092 int panel_power_up_delay;
1093 int panel_power_down_delay;
1094 int panel_power_cycle_delay;
1095 int backlight_on_delay;
1096 int backlight_off_delay;
1097 struct delayed_work panel_vdd_work;
1098 bool want_panel_vdd;
1099 unsigned long last_power_on;
1100 unsigned long last_backlight_off;
1101 ktime_t panel_power_off_time;
1103 struct notifier_block edp_notifier;
1106 * Pipe whose power sequencer is currently locked into
1107 * this port. Only relevant on VLV/CHV.
1111 * Pipe currently driving the port. Used for preventing
1112 * the use of the PPS for any pipe currentrly driving
1113 * external DP as that will mess things up on VLV.
1115 enum pipe active_pipe;
1117 * Set if the sequencer may be reset due to a power transition,
1118 * requiring a reinitialization. Only relevant on BXT.
1121 struct edp_power_seq pps_delays;
1123 bool can_mst; /* this port supports mst */
1125 int active_mst_links;
1126 /* connector directly attached - won't be use for modeset in mst world */
1127 struct intel_connector *attached_connector;
1129 /* mst connector list */
1130 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1131 struct drm_dp_mst_topology_mgr mst_mgr;
1133 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1135 * This function returns the value we have to program the AUX_CTL
1136 * register with to kick off an AUX transaction.
1138 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1140 uint32_t aux_clock_divider);
1142 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1143 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1145 /* This is called before a link training is starterd */
1146 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1148 /* Displayport compliance testing */
1149 struct intel_dp_compliance compliance;
1152 struct intel_lspcon {
1154 enum drm_lspcon_mode mode;
1157 struct intel_digital_port {
1158 struct intel_encoder base;
1159 u32 saved_port_bits;
1161 struct intel_hdmi hdmi;
1162 struct intel_lspcon lspcon;
1163 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1164 bool release_cl2_override;
1166 enum intel_display_power_domain ddi_io_power_domain;
1168 void (*write_infoframe)(struct drm_encoder *encoder,
1169 const struct intel_crtc_state *crtc_state,
1171 const void *frame, ssize_t len);
1172 void (*set_infoframes)(struct drm_encoder *encoder,
1174 const struct intel_crtc_state *crtc_state,
1175 const struct drm_connector_state *conn_state);
1176 bool (*infoframe_enabled)(struct drm_encoder *encoder,
1177 const struct intel_crtc_state *pipe_config);
1180 struct intel_dp_mst_encoder {
1181 struct intel_encoder base;
1183 struct intel_digital_port *primary;
1184 struct intel_connector *connector;
1187 static inline enum dpio_channel
1188 vlv_dport_to_channel(struct intel_digital_port *dport)
1190 switch (dport->base.port) {
1201 static inline enum dpio_phy
1202 vlv_dport_to_phy(struct intel_digital_port *dport)
1204 switch (dport->base.port) {
1215 static inline enum dpio_channel
1216 vlv_pipe_to_channel(enum pipe pipe)
1229 static inline struct intel_crtc *
1230 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1232 return dev_priv->pipe_to_crtc_mapping[pipe];
1235 static inline struct intel_crtc *
1236 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1238 return dev_priv->plane_to_crtc_mapping[plane];
1241 struct intel_load_detect_pipe {
1242 struct drm_atomic_state *restore_state;
1245 static inline struct intel_encoder *
1246 intel_attached_encoder(struct drm_connector *connector)
1248 return to_intel_connector(connector)->encoder;
1251 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1253 switch (encoder->type) {
1254 case INTEL_OUTPUT_DDI:
1255 case INTEL_OUTPUT_DP:
1256 case INTEL_OUTPUT_EDP:
1257 case INTEL_OUTPUT_HDMI:
1264 static inline struct intel_digital_port *
1265 enc_to_dig_port(struct drm_encoder *encoder)
1267 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1269 if (intel_encoder_is_dig_port(intel_encoder))
1270 return container_of(encoder, struct intel_digital_port,
1276 static inline struct intel_dp_mst_encoder *
1277 enc_to_mst(struct drm_encoder *encoder)
1279 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1282 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1284 return &enc_to_dig_port(encoder)->dp;
1287 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1289 switch (encoder->type) {
1290 case INTEL_OUTPUT_DP:
1291 case INTEL_OUTPUT_EDP:
1293 case INTEL_OUTPUT_DDI:
1294 /* Skip pure HDMI/DVI DDI encoders */
1295 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1301 static inline struct intel_digital_port *
1302 dp_to_dig_port(struct intel_dp *intel_dp)
1304 return container_of(intel_dp, struct intel_digital_port, dp);
1307 static inline struct intel_lspcon *
1308 dp_to_lspcon(struct intel_dp *intel_dp)
1310 return &dp_to_dig_port(intel_dp)->lspcon;
1313 static inline struct intel_digital_port *
1314 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1316 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1319 static inline struct intel_plane_state *
1320 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1321 struct intel_plane *plane)
1323 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1327 static inline struct intel_crtc_state *
1328 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1329 struct intel_crtc *crtc)
1331 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1335 static inline struct intel_crtc_state *
1336 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1337 struct intel_crtc *crtc)
1339 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1343 /* intel_fifo_underrun.c */
1344 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, bool enable);
1346 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1347 enum pipe pch_transcoder,
1349 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1351 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1352 enum pipe pch_transcoder);
1353 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1354 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1357 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1358 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1359 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1360 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1361 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1362 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1363 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1364 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1366 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1369 return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1372 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1373 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1374 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1377 * We only use drm_irq_uninstall() at unload and VT switch, so
1378 * this is the only thing we need to check.
1380 return dev_priv->runtime_pm.irqs_enabled;
1383 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1384 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1386 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1388 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1389 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1390 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1393 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1394 i915_reg_t adpa_reg, enum pipe *pipe);
1395 void intel_crt_init(struct drm_i915_private *dev_priv);
1396 void intel_crt_reset(struct drm_encoder *encoder);
1399 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1400 const struct intel_crtc_state *old_crtc_state,
1401 const struct drm_connector_state *old_conn_state);
1402 void hsw_fdi_link_train(struct intel_crtc *crtc,
1403 const struct intel_crtc_state *crtc_state);
1404 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1405 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1406 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1407 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1408 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1409 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
1410 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1411 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1412 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1413 void intel_ddi_get_config(struct intel_encoder *encoder,
1414 struct intel_crtc_state *pipe_config);
1416 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1418 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1419 struct intel_crtc_state *crtc_state);
1420 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1421 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1422 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1423 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1425 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1427 void icl_map_plls_to_ports(struct drm_crtc *crtc,
1428 struct intel_crtc_state *crtc_state,
1429 struct drm_atomic_state *old_state);
1430 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
1431 struct intel_crtc_state *crtc_state,
1432 struct drm_atomic_state *old_state);
1434 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1435 int plane, unsigned int height);
1438 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1439 void intel_audio_codec_enable(struct intel_encoder *encoder,
1440 const struct intel_crtc_state *crtc_state,
1441 const struct drm_connector_state *conn_state);
1442 void intel_audio_codec_disable(struct intel_encoder *encoder,
1443 const struct intel_crtc_state *old_crtc_state,
1444 const struct drm_connector_state *old_conn_state);
1445 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1446 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1447 void intel_audio_init(struct drm_i915_private *dev_priv);
1448 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1451 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1452 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1453 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1454 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1455 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1456 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1457 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1458 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1459 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1460 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1461 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1462 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1463 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1464 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1465 const struct intel_cdclk_state *b);
1466 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1467 const struct intel_cdclk_state *b);
1468 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1469 const struct intel_cdclk_state *cdclk_state);
1470 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1471 const char *context);
1473 /* intel_display.c */
1474 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1475 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1476 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1477 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1478 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1479 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1480 const char *name, u32 reg, int ref_freq);
1481 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1482 const char *name, u32 reg);
1483 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1484 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1485 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1486 unsigned int intel_fb_xy_to_linear(int x, int y,
1487 const struct intel_plane_state *state,
1489 void intel_add_fb_offsets(int *x, int *y,
1490 const struct intel_plane_state *state, int plane);
1491 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1492 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1493 void intel_mark_busy(struct drm_i915_private *dev_priv);
1494 void intel_mark_idle(struct drm_i915_private *dev_priv);
1495 int intel_display_suspend(struct drm_device *dev);
1496 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1497 void intel_encoder_destroy(struct drm_encoder *encoder);
1498 int intel_connector_init(struct intel_connector *);
1499 struct intel_connector *intel_connector_alloc(void);
1500 void intel_connector_free(struct intel_connector *connector);
1501 bool intel_connector_get_hw_state(struct intel_connector *connector);
1502 void intel_connector_attach_encoder(struct intel_connector *connector,
1503 struct intel_encoder *encoder);
1504 struct drm_display_mode *
1505 intel_encoder_current_mode(struct intel_encoder *encoder);
1506 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1507 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1510 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1511 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1512 struct drm_file *file_priv);
1513 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1516 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1517 enum intel_output_type type)
1519 return crtc_state->output_types & (1 << type);
1522 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1524 return crtc_state->output_types &
1525 ((1 << INTEL_OUTPUT_DP) |
1526 (1 << INTEL_OUTPUT_DP_MST) |
1527 (1 << INTEL_OUTPUT_EDP));
1530 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1532 drm_wait_one_vblank(&dev_priv->drm, pipe);
1535 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1537 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1540 intel_wait_for_vblank(dev_priv, pipe);
1543 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1545 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1546 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1547 struct intel_digital_port *dport,
1548 unsigned int expected_mask);
1549 int intel_get_load_detect_pipe(struct drm_connector *connector,
1550 const struct drm_display_mode *mode,
1551 struct intel_load_detect_pipe *old,
1552 struct drm_modeset_acquire_ctx *ctx);
1553 void intel_release_load_detect_pipe(struct drm_connector *connector,
1554 struct intel_load_detect_pipe *old,
1555 struct drm_modeset_acquire_ctx *ctx);
1557 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1558 unsigned int rotation,
1560 unsigned long *out_flags);
1561 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1562 struct drm_framebuffer *
1563 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1564 struct drm_mode_fb_cmd2 *mode_cmd);
1565 int intel_prepare_plane_fb(struct drm_plane *plane,
1566 struct drm_plane_state *new_state);
1567 void intel_cleanup_plane_fb(struct drm_plane *plane,
1568 struct drm_plane_state *old_state);
1569 int intel_plane_atomic_get_property(struct drm_plane *plane,
1570 const struct drm_plane_state *state,
1571 struct drm_property *property,
1573 int intel_plane_atomic_set_property(struct drm_plane *plane,
1574 struct drm_plane_state *state,
1575 struct drm_property *property,
1577 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1578 struct drm_crtc_state *crtc_state,
1579 const struct intel_plane_state *old_plane_state,
1580 struct drm_plane_state *plane_state);
1582 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1585 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1586 const struct dpll *dpll);
1587 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1588 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1590 /* modesetting asserts */
1591 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1593 void assert_pll(struct drm_i915_private *dev_priv,
1594 enum pipe pipe, bool state);
1595 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1596 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1597 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1598 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1599 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1600 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1601 enum pipe pipe, bool state);
1602 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1603 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1604 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1605 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1606 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1607 u32 intel_compute_tile_offset(int *x, int *y,
1608 const struct intel_plane_state *state, int plane);
1609 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1610 void intel_finish_reset(struct drm_i915_private *dev_priv);
1611 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1612 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1613 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1614 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1615 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1616 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1617 unsigned int skl_cdclk_get_vco(unsigned int freq);
1618 void intel_dp_get_m_n(struct intel_crtc *crtc,
1619 struct intel_crtc_state *pipe_config);
1620 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1621 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1622 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1623 struct dpll *best_clock);
1624 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1626 bool intel_crtc_active(struct intel_crtc *crtc);
1627 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1628 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1629 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1630 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1631 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1632 struct intel_crtc_state *pipe_config);
1633 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1634 struct intel_crtc_state *crtc_state);
1636 u16 skl_scaler_calc_phase(int sub, bool chroma_center);
1637 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1638 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1639 uint32_t pixel_format);
1641 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1643 return i915_ggtt_offset(state->vma);
1646 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1647 const struct intel_plane_state *plane_state);
1648 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1649 const struct intel_plane_state *plane_state);
1650 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1651 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1652 unsigned int rotation);
1653 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
1654 struct intel_plane_state *plane_state);
1655 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1656 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1659 void intel_csr_ucode_init(struct drm_i915_private *);
1660 void intel_csr_load_program(struct drm_i915_private *);
1661 void intel_csr_ucode_fini(struct drm_i915_private *);
1662 void intel_csr_ucode_suspend(struct drm_i915_private *);
1663 void intel_csr_ucode_resume(struct drm_i915_private *);
1666 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1667 i915_reg_t dp_reg, enum port port,
1669 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1671 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1672 struct intel_connector *intel_connector);
1673 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1674 int link_rate, uint8_t lane_count,
1676 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1677 int link_rate, uint8_t lane_count);
1678 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1679 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1680 int intel_dp_retrain_link(struct intel_encoder *encoder,
1681 struct drm_modeset_acquire_ctx *ctx);
1682 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1683 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1684 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1685 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1686 bool intel_dp_compute_config(struct intel_encoder *encoder,
1687 struct intel_crtc_state *pipe_config,
1688 struct drm_connector_state *conn_state);
1689 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1690 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1691 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1693 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1694 const struct drm_connector_state *conn_state);
1695 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1696 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1697 void intel_edp_panel_on(struct intel_dp *intel_dp);
1698 void intel_edp_panel_off(struct intel_dp *intel_dp);
1699 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1700 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1701 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1702 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1703 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1704 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1705 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1706 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1707 void intel_plane_destroy(struct drm_plane *plane);
1708 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1709 const struct intel_crtc_state *crtc_state);
1710 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1711 const struct intel_crtc_state *crtc_state);
1712 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1713 unsigned int frontbuffer_bits);
1714 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1715 unsigned int frontbuffer_bits);
1718 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1719 uint8_t dp_train_pat);
1721 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1722 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1724 intel_dp_voltage_max(struct intel_dp *intel_dp);
1726 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1727 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1728 uint8_t *link_bw, uint8_t *rate_select);
1729 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1730 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1732 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1734 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1736 return ~((1 << lane_count) - 1) & 0xf;
1739 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1740 int intel_dp_link_required(int pixel_clock, int bpp);
1741 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1742 bool intel_digital_port_connected(struct intel_encoder *encoder);
1744 /* intel_dp_aux_backlight.c */
1745 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1747 /* intel_dp_mst.c */
1748 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1749 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1751 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1753 /* intel_dsi_dcs_backlight.c */
1754 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1757 void intel_dvo_init(struct drm_i915_private *dev_priv);
1758 /* intel_hotplug.c */
1759 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1760 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1761 struct intel_connector *connector);
1763 /* legacy fbdev emulation in intel_fbdev.c */
1764 #ifdef CONFIG_DRM_FBDEV_EMULATION
1765 extern int intel_fbdev_init(struct drm_device *dev);
1766 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1767 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1768 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1769 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1770 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1771 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1773 static inline int intel_fbdev_init(struct drm_device *dev)
1778 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1782 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1786 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1790 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1794 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1798 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1804 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1805 struct intel_atomic_state *state);
1806 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1807 void intel_fbc_pre_update(struct intel_crtc *crtc,
1808 struct intel_crtc_state *crtc_state,
1809 struct intel_plane_state *plane_state);
1810 void intel_fbc_post_update(struct intel_crtc *crtc);
1811 void intel_fbc_init(struct drm_i915_private *dev_priv);
1812 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1813 void intel_fbc_enable(struct intel_crtc *crtc,
1814 struct intel_crtc_state *crtc_state,
1815 struct intel_plane_state *plane_state);
1816 void intel_fbc_disable(struct intel_crtc *crtc);
1817 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1818 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1819 unsigned int frontbuffer_bits,
1820 enum fb_op_origin origin);
1821 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1822 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1823 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1824 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1825 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1828 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1830 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1831 struct intel_connector *intel_connector);
1832 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1833 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1834 struct intel_crtc_state *pipe_config,
1835 struct drm_connector_state *conn_state);
1836 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1837 struct drm_connector *connector,
1838 bool high_tmds_clock_ratio,
1840 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1841 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1845 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
1846 i915_reg_t lvds_reg, enum pipe *pipe);
1847 void intel_lvds_init(struct drm_i915_private *dev_priv);
1848 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1849 bool intel_is_dual_link_lvds(struct drm_device *dev);
1853 int intel_connector_update_modes(struct drm_connector *connector,
1855 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1856 void intel_attach_force_audio_property(struct drm_connector *connector);
1857 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1858 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1861 /* intel_overlay.c */
1862 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1863 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1864 int intel_overlay_switch_off(struct intel_overlay *overlay);
1865 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1866 struct drm_file *file_priv);
1867 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1868 struct drm_file *file_priv);
1869 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1873 int intel_panel_init(struct intel_panel *panel,
1874 struct drm_display_mode *fixed_mode,
1875 struct drm_display_mode *downclock_mode);
1876 void intel_panel_fini(struct intel_panel *panel);
1877 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1878 struct drm_display_mode *adjusted_mode);
1879 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1880 struct intel_crtc_state *pipe_config,
1882 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1883 struct intel_crtc_state *pipe_config,
1885 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1886 u32 level, u32 max);
1887 int intel_panel_setup_backlight(struct drm_connector *connector,
1889 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1890 const struct drm_connector_state *conn_state);
1891 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1892 void intel_panel_destroy_backlight(struct drm_connector *connector);
1893 extern struct drm_display_mode *intel_find_panel_downclock(
1894 struct drm_i915_private *dev_priv,
1895 struct drm_display_mode *fixed_mode,
1896 struct drm_connector *connector);
1898 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1899 int intel_backlight_device_register(struct intel_connector *connector);
1900 void intel_backlight_device_unregister(struct intel_connector *connector);
1901 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1902 static inline int intel_backlight_device_register(struct intel_connector *connector)
1906 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1909 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1912 void intel_hdcp_atomic_check(struct drm_connector *connector,
1913 struct drm_connector_state *old_state,
1914 struct drm_connector_state *new_state);
1915 int intel_hdcp_init(struct intel_connector *connector,
1916 const struct intel_hdcp_shim *hdcp_shim);
1917 int intel_hdcp_enable(struct intel_connector *connector);
1918 int intel_hdcp_disable(struct intel_connector *connector);
1919 int intel_hdcp_check_link(struct intel_connector *connector);
1920 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
1923 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
1924 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
1925 void intel_psr_enable(struct intel_dp *intel_dp,
1926 const struct intel_crtc_state *crtc_state);
1927 void intel_psr_disable(struct intel_dp *intel_dp,
1928 const struct intel_crtc_state *old_crtc_state);
1929 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1930 unsigned frontbuffer_bits,
1931 enum fb_op_origin origin);
1932 void intel_psr_flush(struct drm_i915_private *dev_priv,
1933 unsigned frontbuffer_bits,
1934 enum fb_op_origin origin);
1935 void intel_psr_init(struct drm_i915_private *dev_priv);
1936 void intel_psr_compute_config(struct intel_dp *intel_dp,
1937 struct intel_crtc_state *crtc_state);
1938 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
1939 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
1940 void intel_psr_short_pulse(struct intel_dp *intel_dp);
1941 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);
1943 /* intel_runtime_pm.c */
1944 int intel_power_domains_init(struct drm_i915_private *);
1945 void intel_power_domains_fini(struct drm_i915_private *);
1946 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1947 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1948 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1949 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1950 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1951 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1953 intel_display_power_domain_str(enum intel_display_power_domain domain);
1955 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1956 enum intel_display_power_domain domain);
1957 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1958 enum intel_display_power_domain domain);
1959 void intel_display_power_get(struct drm_i915_private *dev_priv,
1960 enum intel_display_power_domain domain);
1961 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1962 enum intel_display_power_domain domain);
1963 void intel_display_power_put(struct drm_i915_private *dev_priv,
1964 enum intel_display_power_domain domain);
1965 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
1969 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1971 WARN_ONCE(dev_priv->runtime_pm.suspended,
1972 "Device suspended during HW access\n");
1976 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1978 assert_rpm_device_not_suspended(dev_priv);
1979 WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
1980 "RPM wakelock ref not held during HW access");
1984 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1985 * @dev_priv: i915 device instance
1987 * This function disable asserts that check if we hold an RPM wakelock
1988 * reference, while keeping the device-not-suspended checks still enabled.
1989 * It's meant to be used only in special circumstances where our rule about
1990 * the wakelock refcount wrt. the device power state doesn't hold. According
1991 * to this rule at any point where we access the HW or want to keep the HW in
1992 * an active state we must hold an RPM wakelock reference acquired via one of
1993 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1994 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1995 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1996 * users should avoid using this function.
1998 * Any calls to this function must have a symmetric call to
1999 * enable_rpm_wakeref_asserts().
2002 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2004 atomic_inc(&dev_priv->runtime_pm.wakeref_count);
2008 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2009 * @dev_priv: i915 device instance
2011 * This function re-enables the RPM assert checks after disabling them with
2012 * disable_rpm_wakeref_asserts. It's meant to be used only in special
2013 * circumstances otherwise its use should be avoided.
2015 * Any calls to this function must have a symmetric call to
2016 * disable_rpm_wakeref_asserts().
2019 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2021 atomic_dec(&dev_priv->runtime_pm.wakeref_count);
2024 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2025 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2026 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2027 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2029 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
2031 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2032 bool override, unsigned int mask);
2033 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2034 enum dpio_channel ch, bool override);
2038 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2039 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2040 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2041 void intel_update_watermarks(struct intel_crtc *crtc);
2042 void intel_init_pm(struct drm_i915_private *dev_priv);
2043 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2044 void intel_pm_setup(struct drm_i915_private *dev_priv);
2045 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2046 void intel_gpu_ips_teardown(void);
2047 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2048 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2049 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2050 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2051 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2052 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2053 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2054 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2055 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2056 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2057 void g4x_wm_get_hw_state(struct drm_device *dev);
2058 void vlv_wm_get_hw_state(struct drm_device *dev);
2059 void ilk_wm_get_hw_state(struct drm_device *dev);
2060 void skl_wm_get_hw_state(struct drm_device *dev);
2061 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2062 struct skl_ddb_allocation *ddb /* out */);
2063 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2064 struct skl_pipe_wm *out);
2065 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2066 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2067 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2068 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2069 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2070 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2071 const struct skl_wm_level *l2);
2072 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
2073 const struct skl_ddb_entry **entries,
2074 const struct skl_ddb_entry *ddb,
2076 bool ilk_disable_lp_wm(struct drm_device *dev);
2077 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2078 struct intel_crtc_state *cstate);
2079 void intel_init_ipc(struct drm_i915_private *dev_priv);
2080 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2083 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2084 i915_reg_t sdvo_reg, enum pipe *pipe);
2085 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2086 i915_reg_t reg, enum port port);
2089 /* intel_sprite.c */
2090 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2092 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2093 enum pipe pipe, int plane);
2094 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2095 struct drm_file *file_priv);
2096 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2097 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2098 void skl_update_plane(struct intel_plane *plane,
2099 const struct intel_crtc_state *crtc_state,
2100 const struct intel_plane_state *plane_state);
2101 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
2102 bool skl_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe);
2103 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
2104 enum pipe pipe, enum plane_id plane_id);
2105 bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
2106 enum pipe pipe, enum plane_id plane_id);
2109 void intel_tv_init(struct drm_i915_private *dev_priv);
2111 /* intel_atomic.c */
2112 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2113 const struct drm_connector_state *state,
2114 struct drm_property *property,
2116 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2117 struct drm_connector_state *state,
2118 struct drm_property *property,
2120 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2121 struct drm_connector_state *new_state);
2122 struct drm_connector_state *
2123 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2125 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2126 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2127 struct drm_crtc_state *state);
2128 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2129 void intel_atomic_state_clear(struct drm_atomic_state *);
2131 static inline struct intel_crtc_state *
2132 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2133 struct intel_crtc *crtc)
2135 struct drm_crtc_state *crtc_state;
2136 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2137 if (IS_ERR(crtc_state))
2138 return ERR_CAST(crtc_state);
2140 return to_intel_crtc_state(crtc_state);
2143 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2144 struct intel_crtc *intel_crtc,
2145 struct intel_crtc_state *crtc_state);
2147 /* intel_atomic_plane.c */
2148 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2149 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2150 void intel_plane_destroy_state(struct drm_plane *plane,
2151 struct drm_plane_state *state);
2152 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2153 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2154 struct intel_crtc_state *crtc_state,
2155 const struct intel_plane_state *old_plane_state,
2156 struct intel_plane_state *intel_state);
2159 void intel_color_init(struct drm_crtc *crtc);
2160 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2161 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2162 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2164 /* intel_lspcon.c */
2165 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2166 void lspcon_resume(struct intel_lspcon *lspcon);
2167 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2169 /* intel_pipe_crc.c */
2170 #ifdef CONFIG_DEBUG_FS
2171 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2172 size_t *values_cnt);
2173 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2174 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2176 #define intel_crtc_set_crc_source NULL
2177 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2181 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2185 #endif /* __INTEL_DRV_H__ */