drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42
  43 /**
  44  * _wait_for - magic (register) wait macro
  45  *
  46  * Does the right thing for modeset paths when run under kdgb or similar atomic
  47  * contexts. Note that it's important that we check the condition again after
  48  * having timed out, since the timeout could be due to preemption or similar and
  49  * we've never had a chance to check the condition before the timeout.
  50  */
  51 #define _wait_for(COND, US, Wmin, Wmax) ({ \
  52         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  53         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  54         int ret__;                                                      \
  55         might_sleep();                                                  \
  56         for (;;) {                                                      \
  57                 bool expired__ = time_after(jiffies, timeout__);        \
  58                 if (COND) {                                             \
  59                         ret__ = 0;                                      \
  60                         break;                                          \
  61                 }                                                       \
  62                 if (expired__) {                                        \
  63                         ret__ = -ETIMEDOUT;                             \
  64                         break;                                          \
  65                 }                                                       \
  66                 usleep_range(wait__, wait__ * 2);                       \
  67                 if (wait__ < (Wmax))                                    \
  68                         wait__ <<= 1;                                   \
  69         }                                                               \
  70         ret__;                                                          \
  71 })
  72
  73 #define wait_for(COND, MS)      _wait_for((COND), (MS) * 1000, 10, 1000)
  74
  75 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  76 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  77 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  78 #else
  79 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  80 #endif
  81
  82 #define _wait_for_atomic(COND, US, ATOMIC) \
  83 ({ \
  84         int cpu, ret, timeout = (US) * 1000; \
  85         u64 base; \
  86         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  87         if (!(ATOMIC)) { \
  88                 preempt_disable(); \
  89                 cpu = smp_processor_id(); \
  90         } \
  91         base = local_clock(); \
  92         for (;;) { \
  93                 u64 now = local_clock(); \
  94                 if (!(ATOMIC)) \
  95                         preempt_enable(); \
  96                 if (COND) { \
  97                         ret = 0; \
  98                         break; \
  99                 } \
 100                 if (now - base >= timeout) { \
 101                         ret = -ETIMEDOUT; \
 102                         break; \
 103                 } \
 104                 cpu_relax(); \
 105                 if (!(ATOMIC)) { \
 106                         preempt_disable(); \
 107                         if (unlikely(cpu != smp_processor_id())) { \
 108                                 timeout -= now - base; \
 109                                 cpu = smp_processor_id(); \
 110                                 base = local_clock(); \
 111                         } \
 112                 } \
 113         } \
 114         ret; \
 115 })
 116
 117 #define wait_for_us(COND, US) \
 118 ({ \
 119         int ret__; \
 120         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 121         if ((US) > 10) \
 122                 ret__ = _wait_for((COND), (US), 10, 10); \
 123         else \
 124                 ret__ = _wait_for_atomic((COND), (US), 0); \
 125         ret__; \
 126 })
 127
 128 #define wait_for_atomic_us(COND, US) \
 129 ({ \
 130         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 131         BUILD_BUG_ON((US) > 50000); \
 132         _wait_for_atomic((COND), (US), 1); \
 133 })
 134
 135 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 136
 137 #define KHz(x) (1000 * (x))
 138 #define MHz(x) KHz(1000 * (x))
 139
 140 /*
 141  * Display related stuff
 142  */
 143
 144 /* store information about an Ixxx DVO */
 145 /* The i830->i865 use multiple DVOs with multiple i2cs */
 146 /* the i915, i945 have a single sDVO i2c bus - which is different */
 147 #define MAX_OUTPUTS 6
 148 /* maximum connectors per crtcs in the mode set */
 149
 150 /* Maximum cursor sizes */
 151 #define GEN2_CURSOR_WIDTH 64
 152 #define GEN2_CURSOR_HEIGHT 64
 153 #define MAX_CURSOR_WIDTH 256
 154 #define MAX_CURSOR_HEIGHT 256
 155
 156 #define INTEL_I2C_BUS_DVO 1
 157 #define INTEL_I2C_BUS_SDVO 2
 158
 159 /* these are outputs from the chip - integrated only
 160    external chips are via DVO or SDVO output */
 161 enum intel_output_type {
 162         INTEL_OUTPUT_UNUSED = 0,
 163         INTEL_OUTPUT_ANALOG = 1,
 164         INTEL_OUTPUT_DVO = 2,
 165         INTEL_OUTPUT_SDVO = 3,
 166         INTEL_OUTPUT_LVDS = 4,
 167         INTEL_OUTPUT_TVOUT = 5,
 168         INTEL_OUTPUT_HDMI = 6,
 169         INTEL_OUTPUT_DP = 7,
 170         INTEL_OUTPUT_EDP = 8,
 171         INTEL_OUTPUT_DSI = 9,
 172         INTEL_OUTPUT_DDI = 10,
 173         INTEL_OUTPUT_DP_MST = 11,
 174 };
 175
 176 #define INTEL_DVO_CHIP_NONE 0
 177 #define INTEL_DVO_CHIP_LVDS 1
 178 #define INTEL_DVO_CHIP_TMDS 2
 179 #define INTEL_DVO_CHIP_TVOUT 4
 180
 181 #define INTEL_DSI_VIDEO_MODE    0
 182 #define INTEL_DSI_COMMAND_MODE  1
 183
 184 struct intel_framebuffer {
 185         struct drm_framebuffer base;
 186         struct drm_i915_gem_object *obj;
 187         struct intel_rotation_info rot_info;
 188
 189         /* for each plane in the normal GTT view */
 190         struct {
 191                 unsigned int x, y;
 192         } normal[2];
 193         /* for each plane in the rotated GTT view */
 194         struct {
 195                 unsigned int x, y;
 196                 unsigned int pitch; /* pixels */
 197         } rotated[2];
 198 };
 199
 200 struct intel_fbdev {
 201         struct drm_fb_helper helper;
 202         struct intel_framebuffer *fb;
 203         struct i915_vma *vma;
 204         unsigned long vma_flags;
 205         async_cookie_t cookie;
 206         int preferred_bpp;
 207 };
 208
 209 struct intel_encoder {
 210         struct drm_encoder base;
 211
 212         enum intel_output_type type;
 213         enum port port;
 214         unsigned int cloneable;
 215         void (*hot_plug)(struct intel_encoder *);
 216         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 217                                                       struct intel_crtc_state *,
 218                                                       struct drm_connector_state *);
 219         bool (*compute_config)(struct intel_encoder *,
 220                                struct intel_crtc_state *,
 221                                struct drm_connector_state *);
 222         void (*pre_pll_enable)(struct intel_encoder *,
 223                                const struct intel_crtc_state *,
 224                                const struct drm_connector_state *);
 225         void (*pre_enable)(struct intel_encoder *,
 226                            const struct intel_crtc_state *,
 227                            const struct drm_connector_state *);
 228         void (*enable)(struct intel_encoder *,
 229                        const struct intel_crtc_state *,
 230                        const struct drm_connector_state *);
 231         void (*disable)(struct intel_encoder *,
 232                         const struct intel_crtc_state *,
 233                         const struct drm_connector_state *);
 234         void (*post_disable)(struct intel_encoder *,
 235                              const struct intel_crtc_state *,
 236                              const struct drm_connector_state *);
 237         void (*post_pll_disable)(struct intel_encoder *,
 238                                  const struct intel_crtc_state *,
 239                                  const struct drm_connector_state *);
 240         /* Read out the current hw state of this connector, returning true if
 241          * the encoder is active. If the encoder is enabled it also set the pipe
 242          * it is connected to in the pipe parameter. */
 243         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 244         /* Reconstructs the equivalent mode flags for the current hardware
 245          * state. This must be called _after_ display->get_pipe_config has
 246          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 247          * be set correctly before calling this function. */
 248         void (*get_config)(struct intel_encoder *,
 249                            struct intel_crtc_state *pipe_config);
 250         /* Returns a mask of power domains that need to be referenced as part
 251          * of the hardware state readout code. */
 252         u64 (*get_power_domains)(struct intel_encoder *encoder);
 253         /*
 254          * Called during system suspend after all pending requests for the
 255          * encoder are flushed (for example for DP AUX transactions) and
 256          * device interrupts are disabled.
 257          */
 258         void (*suspend)(struct intel_encoder *);
 259         int crtc_mask;
 260         enum hpd_pin hpd_pin;
 261         enum intel_display_power_domain power_domain;
 262         /* for communication with audio component; protected by av_mutex */
 263         const struct drm_connector *audio_connector;
 264 };
 265
 266 struct intel_panel {
 267         struct drm_display_mode *fixed_mode;
 268         struct drm_display_mode *alt_fixed_mode;
 269         struct drm_display_mode *downclock_mode;
 270
 271         /* backlight */
 272         struct {
 273                 bool present;
 274                 u32 level;
 275                 u32 min;
 276                 u32 max;
 277                 bool enabled;
 278                 bool combination_mode;  /* gen 2/4 only */
 279                 bool active_low_pwm;
 280                 bool alternate_pwm_increment;   /* lpt+ */
 281
 282                 /* PWM chip */
 283                 bool util_pin_active_low;       /* bxt+ */
 284                 u8 controller;          /* bxt+ only */
 285                 struct pwm_device *pwm;
 286
 287                 struct backlight_device *device;
 288
 289                 /* Connector and platform specific backlight functions */
 290                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 291                 uint32_t (*get)(struct intel_connector *connector);
 292                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
 293                 void (*disable)(const struct drm_connector_state *conn_state);
 294                 void (*enable)(const struct intel_crtc_state *crtc_state,
 295                                const struct drm_connector_state *conn_state);
 296                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 297                                       uint32_t hz);
 298                 void (*power)(struct intel_connector *, bool enable);
 299         } backlight;
 300 };
 301
 302 struct intel_connector {
 303         struct drm_connector base;
 304         /*
 305          * The fixed encoder this connector is connected to.
 306          */
 307         struct intel_encoder *encoder;
 308
 309         /* ACPI device id for ACPI and driver cooperation */
 310         u32 acpi_device_id;
 311
 312         /* Reads out the current hw, returning true if the connector is enabled
 313          * and active (i.e. dpms ON state). */
 314         bool (*get_hw_state)(struct intel_connector *);
 315
 316         /* Panel info for eDP and LVDS */
 317         struct intel_panel panel;
 318
 319         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 320         struct edid *edid;
 321         struct edid *detect_edid;
 322
 323         /* since POLL and HPD connectors may use the same HPD line keep the native
 324            state of connector->polled in case hotplug storm detection changes it */
 325         u8 polled;
 326
 327         void *port; /* store this opaque as its illegal to dereference it */
 328
 329         struct intel_dp *mst_port;
 330
 331         /* Work struct to schedule a uevent on link train failure */
 332         struct work_struct modeset_retry_work;
 333 };
 334
 335 struct intel_digital_connector_state {
 336         struct drm_connector_state base;
 337
 338         enum hdmi_force_audio force_audio;
 339         int broadcast_rgb;
 340 };
 341
 342 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 343
 344 struct dpll {
 345         /* given values */
 346         int n;
 347         int m1, m2;
 348         int p1, p2;
 349         /* derived values */
 350         int     dot;
 351         int     vco;
 352         int     m;
 353         int     p;
 354 };
 355
 356 struct intel_atomic_state {
 357         struct drm_atomic_state base;
 358
 359         struct {
 360                 /*
 361                  * Logical state of cdclk (used for all scaling, watermark,
 362                  * etc. calculations and checks). This is computed as if all
 363                  * enabled crtcs were active.
 364                  */
 365                 struct intel_cdclk_state logical;
 366
 367                 /*
 368                  * Actual state of cdclk, can be different from the logical
 369                  * state only when all crtc's are DPMS off.
 370                  */
 371                 struct intel_cdclk_state actual;
 372         } cdclk;
 373
 374         bool dpll_set, modeset;
 375
 376         /*
 377          * Does this transaction change the pipes that are active?  This mask
 378          * tracks which CRTC's have changed their active state at the end of
 379          * the transaction (not counting the temporary disable during modesets).
 380          * This mask should only be non-zero when intel_state->modeset is true,
 381          * but the converse is not necessarily true; simply changing a mode may
 382          * not flip the final active status of any CRTC's
 383          */
 384         unsigned int active_pipe_changes;
 385
 386         unsigned int active_crtcs;
 387         /* minimum acceptable cdclk for each pipe */
 388         int min_cdclk[I915_MAX_PIPES];
 389         /* minimum acceptable voltage level for each pipe */
 390         u8 min_voltage_level[I915_MAX_PIPES];
 391
 392         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 393
 394         /*
 395          * Current watermarks can't be trusted during hardware readout, so
 396          * don't bother calculating intermediate watermarks.
 397          */
 398         bool skip_intermediate_wm;
 399
 400         /* Gen9+ only */
 401         struct skl_wm_values wm_results;
 402
 403         struct i915_sw_fence commit_ready;
 404
 405         struct llist_node freed;
 406 };
 407
 408 struct intel_plane_state {
 409         struct drm_plane_state base;
 410         struct drm_rect clip;
 411         struct i915_vma *vma;
 412         unsigned long flags;
 413 #define PLANE_HAS_FENCE BIT(0)
 414
 415         struct {
 416                 u32 offset;
 417                 int x, y;
 418         } main;
 419         struct {
 420                 u32 offset;
 421                 int x, y;
 422         } aux;
 423
 424         /* plane control register */
 425         u32 ctl;
 426
 427         /* plane color control register */
 428         u32 color_ctl;
 429
 430         /*
 431          * scaler_id
 432          *    = -1 : not using a scaler
 433          *    >=  0 : using a scalers
 434          *
 435          * plane requiring a scaler:
 436          *   - During check_plane, its bit is set in
 437          *     crtc_state->scaler_state.scaler_users by calling helper function
 438          *     update_scaler_plane.
 439          *   - scaler_id indicates the scaler it got assigned.
 440          *
 441          * plane doesn't require a scaler:
 442          *   - this can happen when scaling is no more required or plane simply
 443          *     got disabled.
 444          *   - During check_plane, corresponding bit is reset in
 445          *     crtc_state->scaler_state.scaler_users by calling helper function
 446          *     update_scaler_plane.
 447          */
 448         int scaler_id;
 449
 450         struct drm_intel_sprite_colorkey ckey;
 451 };
 452
 453 struct intel_initial_plane_config {
 454         struct intel_framebuffer *fb;
 455         unsigned int tiling;
 456         int size;
 457         u32 base;
 458 };
 459
 460 #define SKL_MIN_SRC_W 8
 461 #define SKL_MAX_SRC_W 4096
 462 #define SKL_MIN_SRC_H 8
 463 #define SKL_MAX_SRC_H 4096
 464 #define SKL_MIN_DST_W 8
 465 #define SKL_MAX_DST_W 4096
 466 #define SKL_MIN_DST_H 8
 467 #define SKL_MAX_DST_H 4096
 468
 469 struct intel_scaler {
 470         int in_use;
 471         uint32_t mode;
 472 };
 473
 474 struct intel_crtc_scaler_state {
 475 #define SKL_NUM_SCALERS 2
 476         struct intel_scaler scalers[SKL_NUM_SCALERS];
 477
 478         /*
 479          * scaler_users: keeps track of users requesting scalers on this crtc.
 480          *
 481          *     If a bit is set, a user is using a scaler.
 482          *     Here user can be a plane or crtc as defined below:
 483          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 484          *       bit 31    - crtc
 485          *
 486          * Instead of creating a new index to cover planes and crtc, using
 487          * existing drm_plane_index for planes which is well less than 31
 488          * planes and bit 31 for crtc. This should be fine to cover all
 489          * our platforms.
 490          *
 491          * intel_atomic_setup_scalers will setup available scalers to users
 492          * requesting scalers. It will gracefully fail if request exceeds
 493          * avilability.
 494          */
 495 #define SKL_CRTC_INDEX 31
 496         unsigned scaler_users;
 497
 498         /* scaler used by crtc for panel fitting purpose */
 499         int scaler_id;
 500 };
 501
 502 /* drm_mode->private_flags */
 503 #define I915_MODE_FLAG_INHERITED 1
 504 /* Flag to get scanline using frame time stamps */
 505 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 506
 507 struct intel_pipe_wm {
 508         struct intel_wm_level wm[5];
 509         uint32_t linetime;
 510         bool fbc_wm_enabled;
 511         bool pipe_enabled;
 512         bool sprites_enabled;
 513         bool sprites_scaled;
 514 };
 515
 516 struct skl_plane_wm {
 517         struct skl_wm_level wm[8];
 518         struct skl_wm_level trans_wm;
 519 };
 520
 521 struct skl_pipe_wm {
 522         struct skl_plane_wm planes[I915_MAX_PLANES];
 523         uint32_t linetime;
 524 };
 525
 526 enum vlv_wm_level {
 527         VLV_WM_LEVEL_PM2,
 528         VLV_WM_LEVEL_PM5,
 529         VLV_WM_LEVEL_DDR_DVFS,
 530         NUM_VLV_WM_LEVELS,
 531 };
 532
 533 struct vlv_wm_state {
 534         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 535         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 536         uint8_t num_levels;
 537         bool cxsr;
 538 };
 539
 540 struct vlv_fifo_state {
 541         u16 plane[I915_MAX_PLANES];
 542 };
 543
 544 enum g4x_wm_level {
 545         G4X_WM_LEVEL_NORMAL,
 546         G4X_WM_LEVEL_SR,
 547         G4X_WM_LEVEL_HPLL,
 548         NUM_G4X_WM_LEVELS,
 549 };
 550
 551 struct g4x_wm_state {
 552         struct g4x_pipe_wm wm;
 553         struct g4x_sr_wm sr;
 554         struct g4x_sr_wm hpll;
 555         bool cxsr;
 556         bool hpll_en;
 557         bool fbc_en;
 558 };
 559
 560 struct intel_crtc_wm_state {
 561         union {
 562                 struct {
 563                         /*
 564                          * Intermediate watermarks; these can be
 565                          * programmed immediately since they satisfy
 566                          * both the current configuration we're
 567                          * switching away from and the new
 568                          * configuration we're switching to.
 569                          */
 570                         struct intel_pipe_wm intermediate;
 571
 572                         /*
 573                          * Optimal watermarks, programmed post-vblank
 574                          * when this state is committed.
 575                          */
 576                         struct intel_pipe_wm optimal;
 577                 } ilk;
 578
 579                 struct {
 580                         /* gen9+ only needs 1-step wm programming */
 581                         struct skl_pipe_wm optimal;
 582                         struct skl_ddb_entry ddb;
 583                 } skl;
 584
 585                 struct {
 586                         /* "raw" watermarks (not inverted) */
 587                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 588                         /* intermediate watermarks (inverted) */
 589                         struct vlv_wm_state intermediate;
 590                         /* optimal watermarks (inverted) */
 591                         struct vlv_wm_state optimal;
 592                         /* display FIFO split */
 593                         struct vlv_fifo_state fifo_state;
 594                 } vlv;
 595
 596                 struct {
 597                         /* "raw" watermarks */
 598                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 599                         /* intermediate watermarks */
 600                         struct g4x_wm_state intermediate;
 601                         /* optimal watermarks */
 602                         struct g4x_wm_state optimal;
 603                 } g4x;
 604         };
 605
 606         /*
 607          * Platforms with two-step watermark programming will need to
 608          * update watermark programming post-vblank to switch from the
 609          * safe intermediate watermarks to the optimal final
 610          * watermarks.
 611          */
 612         bool need_postvbl_update;
 613 };
 614
 615 struct intel_crtc_state {
 616         struct drm_crtc_state base;
 617
 618         /**
 619          * quirks - bitfield with hw state readout quirks
 620          *
 621          * For various reasons the hw state readout code might not be able to
 622          * completely faithfully read out the current state. These cases are
 623          * tracked with quirk flags so that fastboot and state checker can act
 624          * accordingly.
 625          */
 626 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 627         unsigned long quirks;
 628
 629         unsigned fb_bits; /* framebuffers to flip */
 630         bool update_pipe; /* can a fast modeset be performed? */
 631         bool disable_cxsr;
 632         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 633         bool fb_changed; /* fb on any of the planes is changed */
 634         bool fifo_changed; /* FIFO split is changed */
 635
 636         /* Pipe source size (ie. panel fitter input size)
 637          * All planes will be positioned inside this space,
 638          * and get clipped at the edges. */
 639         int pipe_src_w, pipe_src_h;
 640
 641         /*
 642          * Pipe pixel rate, adjusted for
 643          * panel fitter/pipe scaler downscaling.
 644          */
 645         unsigned int pixel_rate;
 646
 647         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 648          * between pch encoders and cpu encoders. */
 649         bool has_pch_encoder;
 650
 651         /* Are we sending infoframes on the attached port */
 652         bool has_infoframe;
 653
 654         /* CPU Transcoder for the pipe. Currently this can only differ from the
 655          * pipe on Haswell and later (where we have a special eDP transcoder)
 656          * and Broxton (where we have special DSI transcoders). */
 657         enum transcoder cpu_transcoder;
 658
 659         /*
 660          * Use reduced/limited/broadcast rbg range, compressing from the full
 661          * range fed into the crtcs.
 662          */
 663         bool limited_color_range;
 664
 665         /* Bitmask of encoder types (enum intel_output_type)
 666          * driven by the pipe.
 667          */
 668         unsigned int output_types;
 669
 670         /* Whether we should send NULL infoframes. Required for audio. */
 671         bool has_hdmi_sink;
 672
 673         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 674          * has_dp_encoder is set. */
 675         bool has_audio;
 676
 677         /*
 678          * Enable dithering, used when the selected pipe bpp doesn't match the
 679          * plane bpp.
 680          */
 681         bool dither;
 682
 683         /*
 684          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 685          * compliance video pattern tests.
 686          * Disable dither only if it is a compliance test request for
 687          * 18bpp.
 688          */
 689         bool dither_force_disable;
 690
 691         /* Controls for the clock computation, to override various stages. */
 692         bool clock_set;
 693
 694         /* SDVO TV has a bunch of special case. To make multifunction encoders
 695          * work correctly, we need to track this at runtime.*/
 696         bool sdvo_tv_clock;
 697
 698         /*
 699          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 700          * required. This is set in the 2nd loop of calling encoder's
 701          * ->compute_config if the first pick doesn't work out.
 702          */
 703         bool bw_constrained;
 704
 705         /* Settings for the intel dpll used on pretty much everything but
 706          * haswell. */
 707         struct dpll dpll;
 708
 709         /* Selected dpll when shared or NULL. */
 710         struct intel_shared_dpll *shared_dpll;
 711
 712         /* Actual register state of the dpll, for shared dpll cross-checking. */
 713         struct intel_dpll_hw_state dpll_hw_state;
 714
 715         /* DSI PLL registers */
 716         struct {
 717                 u32 ctrl, div;
 718         } dsi_pll;
 719
 720         int pipe_bpp;
 721         struct intel_link_m_n dp_m_n;
 722
 723         /* m2_n2 for eDP downclock */
 724         struct intel_link_m_n dp_m2_n2;
 725         bool has_drrs;
 726
 727         bool has_psr;
 728         bool has_psr2;
 729
 730         /*
 731          * Frequence the dpll for the port should run at. Differs from the
 732          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 733          * already multiplied by pixel_multiplier.
 734          */
 735         int port_clock;
 736
 737         /* Used by SDVO (and if we ever fix it, HDMI). */
 738         unsigned pixel_multiplier;
 739
 740         uint8_t lane_count;
 741
 742         /*
 743          * Used by platforms having DP/HDMI PHY with programmable lane
 744          * latency optimization.
 745          */
 746         uint8_t lane_lat_optim_mask;
 747
 748         /* minimum acceptable voltage level */
 749         u8 min_voltage_level;
 750
 751         /* Panel fitter controls for gen2-gen4 + VLV */
 752         struct {
 753                 u32 control;
 754                 u32 pgm_ratios;
 755                 u32 lvds_border_bits;
 756         } gmch_pfit;
 757
 758         /* Panel fitter placement and size for Ironlake+ */
 759         struct {
 760                 u32 pos;
 761                 u32 size;
 762                 bool enabled;
 763                 bool force_thru;
 764         } pch_pfit;
 765
 766         /* FDI configuration, only valid if has_pch_encoder is set. */
 767         int fdi_lanes;
 768         struct intel_link_m_n fdi_m_n;
 769
 770         bool ips_enabled;
 771         bool ips_force_disable;
 772
 773         bool enable_fbc;
 774
 775         bool double_wide;
 776
 777         int pbn;
 778
 779         struct intel_crtc_scaler_state scaler_state;
 780
 781         /* w/a for waiting 2 vblanks during crtc enable */
 782         enum pipe hsw_workaround_pipe;
 783
 784         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 785         bool disable_lp_wm;
 786
 787         struct intel_crtc_wm_state wm;
 788
 789         /* Gamma mode programmed on the pipe */
 790         uint32_t gamma_mode;
 791
 792         /* bitmask of visible planes (enum plane_id) */
 793         u8 active_planes;
 794
 795         /* HDMI scrambling status */
 796         bool hdmi_scrambling;
 797
 798         /* HDMI High TMDS char rate ratio */
 799         bool hdmi_high_tmds_clock_ratio;
 800
 801         /* output format is YCBCR 4:2:0 */
 802         bool ycbcr420;
 803 };
 804
 805 struct intel_crtc {
 806         struct drm_crtc base;
 807         enum pipe pipe;
 808         /*
 809          * Whether the crtc and the connected output pipeline is active. Implies
 810          * that crtc->enabled is set, i.e. the current mode configuration has
 811          * some outputs connected to this crtc.
 812          */
 813         bool active;
 814         u8 plane_ids_mask;
 815         unsigned long long enabled_power_domains;
 816         struct intel_overlay *overlay;
 817
 818         struct intel_crtc_state *config;
 819
 820         /* global reset count when the last flip was submitted */
 821         unsigned int reset_count;
 822
 823         /* Access to these should be protected by dev_priv->irq_lock. */
 824         bool cpu_fifo_underrun_disabled;
 825         bool pch_fifo_underrun_disabled;
 826
 827         /* per-pipe watermark state */
 828         struct {
 829                 /* watermarks currently being used  */
 830                 union {
 831                         struct intel_pipe_wm ilk;
 832                         struct vlv_wm_state vlv;
 833                         struct g4x_wm_state g4x;
 834                 } active;
 835         } wm;
 836
 837         int scanline_offset;
 838
 839         struct {
 840                 unsigned start_vbl_count;
 841                 ktime_t start_vbl_time;
 842                 int min_vbl, max_vbl;
 843                 int scanline_start;
 844         } debug;
 845
 846         /* scalers available on this crtc */
 847         int num_scalers;
 848 };
 849
 850 struct intel_plane {
 851         struct drm_plane base;
 852         enum i9xx_plane_id i9xx_plane;
 853         enum plane_id id;
 854         enum pipe pipe;
 855         bool can_scale;
 856         int max_downscale;
 857         uint32_t frontbuffer_bit;
 858
 859         struct {
 860                 u32 base, cntl, size;
 861         } cursor;
 862
 863         /*
 864          * NOTE: Do not place new plane state fields here (e.g., when adding
 865          * new plane properties).  New runtime state should now be placed in
 866          * the intel_plane_state structure and accessed via plane_state.
 867          */
 868
 869         void (*update_plane)(struct intel_plane *plane,
 870                              const struct intel_crtc_state *crtc_state,
 871                              const struct intel_plane_state *plane_state);
 872         void (*disable_plane)(struct intel_plane *plane,
 873                               struct intel_crtc *crtc);
 874         bool (*get_hw_state)(struct intel_plane *plane);
 875         int (*check_plane)(struct intel_plane *plane,
 876                            struct intel_crtc_state *crtc_state,
 877                            struct intel_plane_state *state);
 878 };
 879
 880 struct intel_watermark_params {
 881         u16 fifo_size;
 882         u16 max_wm;
 883         u8 default_wm;
 884         u8 guard_size;
 885         u8 cacheline_size;
 886 };
 887
 888 struct cxsr_latency {
 889         bool is_desktop : 1;
 890         bool is_ddr3 : 1;
 891         u16 fsb_freq;
 892         u16 mem_freq;
 893         u16 display_sr;
 894         u16 display_hpll_disable;
 895         u16 cursor_sr;
 896         u16 cursor_hpll_disable;
 897 };
 898
 899 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 900 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 901 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 902 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 903 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 904 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 905 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 906 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 907 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 908
 909 struct intel_hdmi {
 910         i915_reg_t hdmi_reg;
 911         int ddc_bus;
 912         struct {
 913                 enum drm_dp_dual_mode_type type;
 914                 int max_tmds_clock;
 915         } dp_dual_mode;
 916         bool has_hdmi_sink;
 917         bool has_audio;
 918         bool rgb_quant_range_selectable;
 919         struct intel_connector *attached_connector;
 920 };
 921
 922 struct intel_dp_mst_encoder;
 923 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 924
 925 /*
 926  * enum link_m_n_set:
 927  *      When platform provides two set of M_N registers for dp, we can
 928  *      program them and switch between them incase of DRRS.
 929  *      But When only one such register is provided, we have to program the
 930  *      required divider value on that registers itself based on the DRRS state.
 931  *
 932  * M1_N1        : Program dp_m_n on M1_N1 registers
 933  *                        dp_m2_n2 on M2_N2 registers (If supported)
 934  *
 935  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 936  *                        M2_N2 registers are not supported
 937  */
 938
 939 enum link_m_n_set {
 940         /* Sets the m1_n1 and m2_n2 */
 941         M1_N1 = 0,
 942         M2_N2
 943 };
 944
 945 struct intel_dp_compliance_data {
 946         unsigned long edid;
 947         uint8_t video_pattern;
 948         uint16_t hdisplay, vdisplay;
 949         uint8_t bpc;
 950 };
 951
 952 struct intel_dp_compliance {
 953         unsigned long test_type;
 954         struct intel_dp_compliance_data test_data;
 955         bool test_active;
 956         int test_link_rate;
 957         u8 test_lane_count;
 958 };
 959
 960 struct intel_dp {
 961         i915_reg_t output_reg;
 962         i915_reg_t aux_ch_ctl_reg;
 963         i915_reg_t aux_ch_data_reg[5];
 964         uint32_t DP;
 965         int link_rate;
 966         uint8_t lane_count;
 967         uint8_t sink_count;
 968         bool link_mst;
 969         bool has_audio;
 970         bool detect_done;
 971         bool channel_eq_status;
 972         bool reset_link_params;
 973         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 974         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 975         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 976         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 977         /* source rates */
 978         int num_source_rates;
 979         const int *source_rates;
 980         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
 981         int num_sink_rates;
 982         int sink_rates[DP_MAX_SUPPORTED_RATES];
 983         bool use_rate_select;
 984         /* intersection of source and sink rates */
 985         int num_common_rates;
 986         int common_rates[DP_MAX_SUPPORTED_RATES];
 987         /* Max lane count for the current link */
 988         int max_link_lane_count;
 989         /* Max rate for the current link */
 990         int max_link_rate;
 991         /* sink or branch descriptor */
 992         struct drm_dp_desc desc;
 993         struct drm_dp_aux aux;
 994         enum intel_display_power_domain aux_power_domain;
 995         uint8_t train_set[4];
 996         int panel_power_up_delay;
 997         int panel_power_down_delay;
 998         int panel_power_cycle_delay;
 999         int backlight_on_delay;
1000         int backlight_off_delay;
1001         struct delayed_work panel_vdd_work;
1002         bool want_panel_vdd;
1003         unsigned long last_power_on;
1004         unsigned long last_backlight_off;
1005         ktime_t panel_power_off_time;
1006
1007         struct notifier_block edp_notifier;
1008
1009         /*
1010          * Pipe whose power sequencer is currently locked into
1011          * this port. Only relevant on VLV/CHV.
1012          */
1013         enum pipe pps_pipe;
1014         /*
1015          * Pipe currently driving the port. Used for preventing
1016          * the use of the PPS for any pipe currentrly driving
1017          * external DP as that will mess things up on VLV.
1018          */
1019         enum pipe active_pipe;
1020         /*
1021          * Set if the sequencer may be reset due to a power transition,
1022          * requiring a reinitialization. Only relevant on BXT.
1023          */
1024         bool pps_reset;
1025         struct edp_power_seq pps_delays;
1026
1027         bool can_mst; /* this port supports mst */
1028         bool is_mst;
1029         int active_mst_links;
1030         /* connector directly attached - won't be use for modeset in mst world */
1031         struct intel_connector *attached_connector;
1032
1033         /* mst connector list */
1034         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1035         struct drm_dp_mst_topology_mgr mst_mgr;
1036
1037         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1038         /*
1039          * This function returns the value we have to program the AUX_CTL
1040          * register with to kick off an AUX transaction.
1041          */
1042         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1043                                      bool has_aux_irq,
1044                                      int send_bytes,
1045                                      uint32_t aux_clock_divider);
1046
1047         /* This is called before a link training is starterd */
1048         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1049
1050         /* Displayport compliance testing */
1051         struct intel_dp_compliance compliance;
1052 };
1053
1054 struct intel_lspcon {
1055         bool active;
1056         enum drm_lspcon_mode mode;
1057 };
1058
1059 struct intel_digital_port {
1060         struct intel_encoder base;
1061         u32 saved_port_bits;
1062         struct intel_dp dp;
1063         struct intel_hdmi hdmi;
1064         struct intel_lspcon lspcon;
1065         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1066         bool release_cl2_override;
1067         uint8_t max_lanes;
1068         enum intel_display_power_domain ddi_io_power_domain;
1069
1070         void (*write_infoframe)(struct drm_encoder *encoder,
1071                                 const struct intel_crtc_state *crtc_state,
1072                                 unsigned int type,
1073                                 const void *frame, ssize_t len);
1074         void (*set_infoframes)(struct drm_encoder *encoder,
1075                                bool enable,
1076                                const struct intel_crtc_state *crtc_state,
1077                                const struct drm_connector_state *conn_state);
1078         bool (*infoframe_enabled)(struct drm_encoder *encoder,
1079                                   const struct intel_crtc_state *pipe_config);
1080 };
1081
1082 struct intel_dp_mst_encoder {
1083         struct intel_encoder base;
1084         enum pipe pipe;
1085         struct intel_digital_port *primary;
1086         struct intel_connector *connector;
1087 };
1088
1089 static inline enum dpio_channel
1090 vlv_dport_to_channel(struct intel_digital_port *dport)
1091 {
1092         switch (dport->base.port) {
1093         case PORT_B:
1094         case PORT_D:
1095                 return DPIO_CH0;
1096         case PORT_C:
1097                 return DPIO_CH1;
1098         default:
1099                 BUG();
1100         }
1101 }
1102
1103 static inline enum dpio_phy
1104 vlv_dport_to_phy(struct intel_digital_port *dport)
1105 {
1106         switch (dport->base.port) {
1107         case PORT_B:
1108         case PORT_C:
1109                 return DPIO_PHY0;
1110         case PORT_D:
1111                 return DPIO_PHY1;
1112         default:
1113                 BUG();
1114         }
1115 }
1116
1117 static inline enum dpio_channel
1118 vlv_pipe_to_channel(enum pipe pipe)
1119 {
1120         switch (pipe) {
1121         case PIPE_A:
1122         case PIPE_C:
1123                 return DPIO_CH0;
1124         case PIPE_B:
1125                 return DPIO_CH1;
1126         default:
1127                 BUG();
1128         }
1129 }
1130
1131 static inline struct intel_crtc *
1132 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1133 {
1134         return dev_priv->pipe_to_crtc_mapping[pipe];
1135 }
1136
1137 static inline struct intel_crtc *
1138 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1139 {
1140         return dev_priv->plane_to_crtc_mapping[plane];
1141 }
1142
1143 struct intel_load_detect_pipe {
1144         struct drm_atomic_state *restore_state;
1145 };
1146
1147 static inline struct intel_encoder *
1148 intel_attached_encoder(struct drm_connector *connector)
1149 {
1150         return to_intel_connector(connector)->encoder;
1151 }
1152
1153 static inline struct intel_digital_port *
1154 enc_to_dig_port(struct drm_encoder *encoder)
1155 {
1156         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1157
1158         switch (intel_encoder->type) {
1159         case INTEL_OUTPUT_DDI:
1160                 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1161         case INTEL_OUTPUT_DP:
1162         case INTEL_OUTPUT_EDP:
1163         case INTEL_OUTPUT_HDMI:
1164                 return container_of(encoder, struct intel_digital_port,
1165                                     base.base);
1166         default:
1167                 return NULL;
1168         }
1169 }
1170
1171 static inline struct intel_dp_mst_encoder *
1172 enc_to_mst(struct drm_encoder *encoder)
1173 {
1174         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1175 }
1176
1177 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1178 {
1179         return &enc_to_dig_port(encoder)->dp;
1180 }
1181
1182 static inline struct intel_digital_port *
1183 dp_to_dig_port(struct intel_dp *intel_dp)
1184 {
1185         return container_of(intel_dp, struct intel_digital_port, dp);
1186 }
1187
1188 static inline struct intel_lspcon *
1189 dp_to_lspcon(struct intel_dp *intel_dp)
1190 {
1191         return &dp_to_dig_port(intel_dp)->lspcon;
1192 }
1193
1194 static inline struct intel_digital_port *
1195 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1196 {
1197         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1198 }
1199
1200 static inline struct intel_plane_state *
1201 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1202                                  struct intel_plane *plane)
1203 {
1204         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1205                                                                    &plane->base));
1206 }
1207
1208 static inline struct intel_crtc_state *
1209 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1210                                 struct intel_crtc *crtc)
1211 {
1212         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1213                                                                  &crtc->base));
1214 }
1215
1216 static inline struct intel_crtc_state *
1217 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1218                                 struct intel_crtc *crtc)
1219 {
1220         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1221                                                                  &crtc->base));
1222 }
1223
1224 /* intel_fifo_underrun.c */
1225 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1226                                            enum pipe pipe, bool enable);
1227 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1228                                            enum pipe pch_transcoder,
1229                                            bool enable);
1230 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1231                                          enum pipe pipe);
1232 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1233                                          enum pipe pch_transcoder);
1234 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1235 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1236
1237 /* i915_irq.c */
1238 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1239 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1240 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1241 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1242 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1243 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1244 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1245
1246 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1247                                             u32 mask)
1248 {
1249         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1250 }
1251
1252 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1253 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1254 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1255 {
1256         /*
1257          * We only use drm_irq_uninstall() at unload and VT switch, so
1258          * this is the only thing we need to check.
1259          */
1260         return dev_priv->runtime_pm.irqs_enabled;
1261 }
1262
1263 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1264 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1265                                      u8 pipe_mask);
1266 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1267                                      u8 pipe_mask);
1268 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1269 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1270 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1271
1272 /* intel_crt.c */
1273 void intel_crt_init(struct drm_i915_private *dev_priv);
1274 void intel_crt_reset(struct drm_encoder *encoder);
1275
1276 /* intel_ddi.c */
1277 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1278                                 const struct intel_crtc_state *old_crtc_state,
1279                                 const struct drm_connector_state *old_conn_state);
1280 void hsw_fdi_link_train(struct intel_crtc *crtc,
1281                         const struct intel_crtc_state *crtc_state);
1282 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1283 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1284 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1285 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1286                                        enum transcoder cpu_transcoder);
1287 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1288 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1289 struct intel_encoder *
1290 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1291 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1292 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1293 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1294 void intel_ddi_get_config(struct intel_encoder *encoder,
1295                           struct intel_crtc_state *pipe_config);
1296
1297 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1298                                     bool state);
1299 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1300                                          struct intel_crtc_state *crtc_state);
1301 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1302 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1303 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1304
1305 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1306                                    int plane, unsigned int height);
1307
1308 /* intel_audio.c */
1309 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1310 void intel_audio_codec_enable(struct intel_encoder *encoder,
1311                               const struct intel_crtc_state *crtc_state,
1312                               const struct drm_connector_state *conn_state);
1313 void intel_audio_codec_disable(struct intel_encoder *encoder,
1314                                const struct intel_crtc_state *old_crtc_state,
1315                                const struct drm_connector_state *old_conn_state);
1316 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1317 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1318 void intel_audio_init(struct drm_i915_private *dev_priv);
1319 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1320
1321 /* intel_cdclk.c */
1322 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1323 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1324 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1325 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1326 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1327 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1328 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1329 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1330 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1331 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1332 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1333 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1334 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1335 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1336                                const struct intel_cdclk_state *b);
1337 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1338                          const struct intel_cdclk_state *b);
1339 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1340                      const struct intel_cdclk_state *cdclk_state);
1341 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1342                             const char *context);
1343
1344 /* intel_display.c */
1345 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1346 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1347 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1348 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1349 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1350 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1351                       const char *name, u32 reg, int ref_freq);
1352 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1353                            const char *name, u32 reg);
1354 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1355 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1356 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1357 unsigned int intel_fb_xy_to_linear(int x, int y,
1358                                    const struct intel_plane_state *state,
1359                                    int plane);
1360 void intel_add_fb_offsets(int *x, int *y,
1361                           const struct intel_plane_state *state, int plane);
1362 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1363 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1364 void intel_mark_busy(struct drm_i915_private *dev_priv);
1365 void intel_mark_idle(struct drm_i915_private *dev_priv);
1366 int intel_display_suspend(struct drm_device *dev);
1367 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1368 void intel_encoder_destroy(struct drm_encoder *encoder);
1369 int intel_connector_init(struct intel_connector *);
1370 struct intel_connector *intel_connector_alloc(void);
1371 void intel_connector_free(struct intel_connector *connector);
1372 bool intel_connector_get_hw_state(struct intel_connector *connector);
1373 void intel_connector_attach_encoder(struct intel_connector *connector,
1374                                     struct intel_encoder *encoder);
1375 struct drm_display_mode *
1376 intel_encoder_current_mode(struct intel_encoder *encoder);
1377
1378 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1379 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1380                                       struct drm_file *file_priv);
1381 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1382                                              enum pipe pipe);
1383 static inline bool
1384 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1385                     enum intel_output_type type)
1386 {
1387         return crtc_state->output_types & (1 << type);
1388 }
1389 static inline bool
1390 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1391 {
1392         return crtc_state->output_types &
1393                 ((1 << INTEL_OUTPUT_DP) |
1394                  (1 << INTEL_OUTPUT_DP_MST) |
1395                  (1 << INTEL_OUTPUT_EDP));
1396 }
1397 static inline void
1398 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1399 {
1400         drm_wait_one_vblank(&dev_priv->drm, pipe);
1401 }
1402 static inline void
1403 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1404 {
1405         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1406
1407         if (crtc->active)
1408                 intel_wait_for_vblank(dev_priv, pipe);
1409 }
1410
1411 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1412
1413 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1414 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1415                          struct intel_digital_port *dport,
1416                          unsigned int expected_mask);
1417 int intel_get_load_detect_pipe(struct drm_connector *connector,
1418                                const struct drm_display_mode *mode,
1419                                struct intel_load_detect_pipe *old,
1420                                struct drm_modeset_acquire_ctx *ctx);
1421 void intel_release_load_detect_pipe(struct drm_connector *connector,
1422                                     struct intel_load_detect_pipe *old,
1423                                     struct drm_modeset_acquire_ctx *ctx);
1424 struct i915_vma *
1425 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1426                            unsigned int rotation,
1427                            bool uses_fence,
1428                            unsigned long *out_flags);
1429 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1430 struct drm_framebuffer *
1431 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1432                          struct drm_mode_fb_cmd2 *mode_cmd);
1433 int intel_prepare_plane_fb(struct drm_plane *plane,
1434                            struct drm_plane_state *new_state);
1435 void intel_cleanup_plane_fb(struct drm_plane *plane,
1436                             struct drm_plane_state *old_state);
1437 int intel_plane_atomic_get_property(struct drm_plane *plane,
1438                                     const struct drm_plane_state *state,
1439                                     struct drm_property *property,
1440                                     uint64_t *val);
1441 int intel_plane_atomic_set_property(struct drm_plane *plane,
1442                                     struct drm_plane_state *state,
1443                                     struct drm_property *property,
1444                                     uint64_t val);
1445 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1446                                     struct drm_crtc_state *crtc_state,
1447                                     const struct intel_plane_state *old_plane_state,
1448                                     struct drm_plane_state *plane_state);
1449
1450 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1451                                     enum pipe pipe);
1452
1453 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1454                      const struct dpll *dpll);
1455 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1456 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1457
1458 /* modesetting asserts */
1459 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1460                            enum pipe pipe);
1461 void assert_pll(struct drm_i915_private *dev_priv,
1462                 enum pipe pipe, bool state);
1463 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1464 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1465 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1466 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1467 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1468 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1469                        enum pipe pipe, bool state);
1470 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1471 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1472 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1473 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1474 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1475 u32 intel_compute_tile_offset(int *x, int *y,
1476                               const struct intel_plane_state *state, int plane);
1477 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1478 void intel_finish_reset(struct drm_i915_private *dev_priv);
1479 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1480 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1481 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1482 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1483 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1484 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1485 unsigned int skl_cdclk_get_vco(unsigned int freq);
1486 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1487 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1488 void intel_dp_get_m_n(struct intel_crtc *crtc,
1489                       struct intel_crtc_state *pipe_config);
1490 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1491 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1492 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1493                         struct dpll *best_clock);
1494 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1495
1496 bool intel_crtc_active(struct intel_crtc *crtc);
1497 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1498 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1499 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1500 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1501 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1502                                  struct intel_crtc_state *pipe_config);
1503
1504 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1505 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1506
1507 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1508 {
1509         return i915_ggtt_offset(state->vma);
1510 }
1511
1512 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1513                         const struct intel_plane_state *plane_state);
1514 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1515                   const struct intel_plane_state *plane_state);
1516 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1517                      unsigned int rotation);
1518 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
1519                             struct intel_plane_state *plane_state);
1520 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1521
1522 /* intel_csr.c */
1523 void intel_csr_ucode_init(struct drm_i915_private *);
1524 void intel_csr_load_program(struct drm_i915_private *);
1525 void intel_csr_ucode_fini(struct drm_i915_private *);
1526 void intel_csr_ucode_suspend(struct drm_i915_private *);
1527 void intel_csr_ucode_resume(struct drm_i915_private *);
1528
1529 /* intel_dp.c */
1530 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1531                    enum port port);
1532 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1533                              struct intel_connector *intel_connector);
1534 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1535                               int link_rate, uint8_t lane_count,
1536                               bool link_mst);
1537 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1538                                             int link_rate, uint8_t lane_count);
1539 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1540 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1541 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1542 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1543 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1544 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1545 int intel_dp_sink_crc(struct intel_dp *intel_dp,
1546                       struct intel_crtc_state *crtc_state, u8 *crc);
1547 bool intel_dp_compute_config(struct intel_encoder *encoder,
1548                              struct intel_crtc_state *pipe_config,
1549                              struct drm_connector_state *conn_state);
1550 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1551 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1552 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1553                                   bool long_hpd);
1554 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1555                             const struct drm_connector_state *conn_state);
1556 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1557 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1558 void intel_edp_panel_on(struct intel_dp *intel_dp);
1559 void intel_edp_panel_off(struct intel_dp *intel_dp);
1560 void intel_dp_mst_suspend(struct drm_device *dev);
1561 void intel_dp_mst_resume(struct drm_device *dev);
1562 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1563 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1564 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1565 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1566 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1567 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1568 void intel_plane_destroy(struct drm_plane *plane);
1569 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1570                            const struct intel_crtc_state *crtc_state);
1571 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1572                             const struct intel_crtc_state *crtc_state);
1573 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1574                                unsigned int frontbuffer_bits);
1575 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1576                           unsigned int frontbuffer_bits);
1577
1578 void
1579 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1580                                        uint8_t dp_train_pat);
1581 void
1582 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1583 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1584 uint8_t
1585 intel_dp_voltage_max(struct intel_dp *intel_dp);
1586 uint8_t
1587 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1588 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1589                            uint8_t *link_bw, uint8_t *rate_select);
1590 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1591 bool
1592 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1593
1594 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1595 {
1596         return ~((1 << lane_count) - 1) & 0xf;
1597 }
1598
1599 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1600 int intel_dp_link_required(int pixel_clock, int bpp);
1601 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1602 bool intel_digital_port_connected(struct intel_encoder *encoder);
1603
1604 /* intel_dp_aux_backlight.c */
1605 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1606
1607 /* intel_dp_mst.c */
1608 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1609 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1610 /* intel_dsi.c */
1611 void intel_dsi_init(struct drm_i915_private *dev_priv);
1612
1613 /* intel_dsi_dcs_backlight.c */
1614 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1615
1616 /* intel_dvo.c */
1617 void intel_dvo_init(struct drm_i915_private *dev_priv);
1618 /* intel_hotplug.c */
1619 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1620
1621
1622 /* legacy fbdev emulation in intel_fbdev.c */
1623 #ifdef CONFIG_DRM_FBDEV_EMULATION
1624 extern int intel_fbdev_init(struct drm_device *dev);
1625 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1626 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1627 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1628 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1629 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1630 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1631 #else
1632 static inline int intel_fbdev_init(struct drm_device *dev)
1633 {
1634         return 0;
1635 }
1636
1637 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1638 {
1639 }
1640
1641 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1642 {
1643 }
1644
1645 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1646 {
1647 }
1648
1649 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1650 {
1651 }
1652
1653 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1654 {
1655 }
1656
1657 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1658 {
1659 }
1660 #endif
1661
1662 /* intel_fbc.c */
1663 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1664                            struct intel_atomic_state *state);
1665 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1666 void intel_fbc_pre_update(struct intel_crtc *crtc,
1667                           struct intel_crtc_state *crtc_state,
1668                           struct intel_plane_state *plane_state);
1669 void intel_fbc_post_update(struct intel_crtc *crtc);
1670 void intel_fbc_init(struct drm_i915_private *dev_priv);
1671 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1672 void intel_fbc_enable(struct intel_crtc *crtc,
1673                       struct intel_crtc_state *crtc_state,
1674                       struct intel_plane_state *plane_state);
1675 void intel_fbc_disable(struct intel_crtc *crtc);
1676 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1677 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1678                           unsigned int frontbuffer_bits,
1679                           enum fb_op_origin origin);
1680 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1681                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1682 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1683 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1684
1685 /* intel_hdmi.c */
1686 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1687                      enum port port);
1688 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1689                                struct intel_connector *intel_connector);
1690 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1691 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1692                                struct intel_crtc_state *pipe_config,
1693                                struct drm_connector_state *conn_state);
1694 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1695                                        struct drm_connector *connector,
1696                                        bool high_tmds_clock_ratio,
1697                                        bool scrambling);
1698 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1699 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1700
1701
1702 /* intel_lvds.c */
1703 void intel_lvds_init(struct drm_i915_private *dev_priv);
1704 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1705 bool intel_is_dual_link_lvds(struct drm_device *dev);
1706
1707
1708 /* intel_modes.c */
1709 int intel_connector_update_modes(struct drm_connector *connector,
1710                                  struct edid *edid);
1711 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1712 void intel_attach_force_audio_property(struct drm_connector *connector);
1713 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1714 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1715
1716
1717 /* intel_overlay.c */
1718 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1719 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1720 int intel_overlay_switch_off(struct intel_overlay *overlay);
1721 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1722                                   struct drm_file *file_priv);
1723 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1724                               struct drm_file *file_priv);
1725 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1726
1727
1728 /* intel_panel.c */
1729 int intel_panel_init(struct intel_panel *panel,
1730                      struct drm_display_mode *fixed_mode,
1731                      struct drm_display_mode *alt_fixed_mode,
1732                      struct drm_display_mode *downclock_mode);
1733 void intel_panel_fini(struct intel_panel *panel);
1734 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1735                             struct drm_display_mode *adjusted_mode);
1736 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1737                              struct intel_crtc_state *pipe_config,
1738                              int fitting_mode);
1739 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1740                               struct intel_crtc_state *pipe_config,
1741                               int fitting_mode);
1742 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1743                                     u32 level, u32 max);
1744 int intel_panel_setup_backlight(struct drm_connector *connector,
1745                                 enum pipe pipe);
1746 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1747                                   const struct drm_connector_state *conn_state);
1748 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1749 void intel_panel_destroy_backlight(struct drm_connector *connector);
1750 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1751 extern struct drm_display_mode *intel_find_panel_downclock(
1752                                 struct drm_i915_private *dev_priv,
1753                                 struct drm_display_mode *fixed_mode,
1754                                 struct drm_connector *connector);
1755
1756 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1757 int intel_backlight_device_register(struct intel_connector *connector);
1758 void intel_backlight_device_unregister(struct intel_connector *connector);
1759 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1760 static inline int intel_backlight_device_register(struct intel_connector *connector)
1761 {
1762         return 0;
1763 }
1764 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1765 {
1766 }
1767 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1768
1769
1770 /* intel_psr.c */
1771 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
1772 void intel_psr_enable(struct intel_dp *intel_dp,
1773                       const struct intel_crtc_state *crtc_state);
1774 void intel_psr_disable(struct intel_dp *intel_dp,
1775                       const struct intel_crtc_state *old_crtc_state);
1776 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1777                           unsigned frontbuffer_bits);
1778 void intel_psr_flush(struct drm_i915_private *dev_priv,
1779                      unsigned frontbuffer_bits,
1780                      enum fb_op_origin origin);
1781 void intel_psr_init(struct drm_i915_private *dev_priv);
1782 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1783                                    unsigned frontbuffer_bits);
1784 void intel_psr_compute_config(struct intel_dp *intel_dp,
1785                               struct intel_crtc_state *crtc_state);
1786
1787 /* intel_runtime_pm.c */
1788 int intel_power_domains_init(struct drm_i915_private *);
1789 void intel_power_domains_fini(struct drm_i915_private *);
1790 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1791 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1792 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1793 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1794 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1795 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1796 const char *
1797 intel_display_power_domain_str(enum intel_display_power_domain domain);
1798
1799 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1800                                     enum intel_display_power_domain domain);
1801 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1802                                       enum intel_display_power_domain domain);
1803 void intel_display_power_get(struct drm_i915_private *dev_priv,
1804                              enum intel_display_power_domain domain);
1805 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1806                                         enum intel_display_power_domain domain);
1807 void intel_display_power_put(struct drm_i915_private *dev_priv,
1808                              enum intel_display_power_domain domain);
1809
1810 static inline void
1811 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1812 {
1813         WARN_ONCE(dev_priv->runtime_pm.suspended,
1814                   "Device suspended during HW access\n");
1815 }
1816
1817 static inline void
1818 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1819 {
1820         assert_rpm_device_not_suspended(dev_priv);
1821         WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
1822                   "RPM wakelock ref not held during HW access");
1823 }
1824
1825 /**
1826  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1827  * @dev_priv: i915 device instance
1828  *
1829  * This function disable asserts that check if we hold an RPM wakelock
1830  * reference, while keeping the device-not-suspended checks still enabled.
1831  * It's meant to be used only in special circumstances where our rule about
1832  * the wakelock refcount wrt. the device power state doesn't hold. According
1833  * to this rule at any point where we access the HW or want to keep the HW in
1834  * an active state we must hold an RPM wakelock reference acquired via one of
1835  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1836  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1837  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1838  * users should avoid using this function.
1839  *
1840  * Any calls to this function must have a symmetric call to
1841  * enable_rpm_wakeref_asserts().
1842  */
1843 static inline void
1844 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1845 {
1846         atomic_inc(&dev_priv->runtime_pm.wakeref_count);
1847 }
1848
1849 /**
1850  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1851  * @dev_priv: i915 device instance
1852  *
1853  * This function re-enables the RPM assert checks after disabling them with
1854  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1855  * circumstances otherwise its use should be avoided.
1856  *
1857  * Any calls to this function must have a symmetric call to
1858  * disable_rpm_wakeref_asserts().
1859  */
1860 static inline void
1861 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1862 {
1863         atomic_dec(&dev_priv->runtime_pm.wakeref_count);
1864 }
1865
1866 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1867 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1868 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1869 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1870
1871 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1872
1873 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1874                              bool override, unsigned int mask);
1875 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1876                           enum dpio_channel ch, bool override);
1877
1878
1879 /* intel_pm.c */
1880 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1881 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1882 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1883 void intel_update_watermarks(struct intel_crtc *crtc);
1884 void intel_init_pm(struct drm_i915_private *dev_priv);
1885 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1886 void intel_pm_setup(struct drm_i915_private *dev_priv);
1887 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1888 void intel_gpu_ips_teardown(void);
1889 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1890 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1891 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1892 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1893 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1894 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1895 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1896 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1897 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1898 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
1899 void g4x_wm_get_hw_state(struct drm_device *dev);
1900 void vlv_wm_get_hw_state(struct drm_device *dev);
1901 void ilk_wm_get_hw_state(struct drm_device *dev);
1902 void skl_wm_get_hw_state(struct drm_device *dev);
1903 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1904                           struct skl_ddb_allocation *ddb /* out */);
1905 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1906                               struct skl_pipe_wm *out);
1907 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
1908 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
1909 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1910 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1911 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1912 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1913                          const struct skl_wm_level *l2);
1914 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
1915                                  const struct skl_ddb_entry **entries,
1916                                  const struct skl_ddb_entry *ddb,
1917                                  int ignore);
1918 bool ilk_disable_lp_wm(struct drm_device *dev);
1919 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
1920                                   struct intel_crtc_state *cstate);
1921 void intel_init_ipc(struct drm_i915_private *dev_priv);
1922 void intel_enable_ipc(struct drm_i915_private *dev_priv);
1923
1924 /* intel_sdvo.c */
1925 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1926                      i915_reg_t reg, enum port port);
1927
1928
1929 /* intel_sprite.c */
1930 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1931                              int usecs);
1932 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1933                                               enum pipe pipe, int plane);
1934 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
1935                                     struct drm_file *file_priv);
1936 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
1937 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
1938 void skl_update_plane(struct intel_plane *plane,
1939                       const struct intel_crtc_state *crtc_state,
1940                       const struct intel_plane_state *plane_state);
1941 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
1942 bool skl_plane_get_hw_state(struct intel_plane *plane);
1943 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
1944                        enum pipe pipe, enum plane_id plane_id);
1945
1946 /* intel_tv.c */
1947 void intel_tv_init(struct drm_i915_private *dev_priv);
1948
1949 /* intel_atomic.c */
1950 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
1951                                                 const struct drm_connector_state *state,
1952                                                 struct drm_property *property,
1953                                                 uint64_t *val);
1954 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
1955                                                 struct drm_connector_state *state,
1956                                                 struct drm_property *property,
1957                                                 uint64_t val);
1958 int intel_digital_connector_atomic_check(struct drm_connector *conn,
1959                                          struct drm_connector_state *new_state);
1960 struct drm_connector_state *
1961 intel_digital_connector_duplicate_state(struct drm_connector *connector);
1962
1963 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1964 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1965                                struct drm_crtc_state *state);
1966 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1967 void intel_atomic_state_clear(struct drm_atomic_state *);
1968
1969 static inline struct intel_crtc_state *
1970 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1971                             struct intel_crtc *crtc)
1972 {
1973         struct drm_crtc_state *crtc_state;
1974         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1975         if (IS_ERR(crtc_state))
1976                 return ERR_CAST(crtc_state);
1977
1978         return to_intel_crtc_state(crtc_state);
1979 }
1980
1981 static inline struct intel_crtc_state *
1982 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1983                                      struct intel_crtc *crtc)
1984 {
1985         struct drm_crtc_state *crtc_state;
1986
1987         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1988
1989         if (crtc_state)
1990                 return to_intel_crtc_state(crtc_state);
1991         else
1992                 return NULL;
1993 }
1994
1995 static inline struct intel_plane_state *
1996 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1997                                       struct intel_plane *plane)
1998 {
1999         struct drm_plane_state *plane_state;
2000
2001         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
2002
2003         return to_intel_plane_state(plane_state);
2004 }
2005
2006 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2007                                struct intel_crtc *intel_crtc,
2008                                struct intel_crtc_state *crtc_state);
2009
2010 /* intel_atomic_plane.c */
2011 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2012 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2013 void intel_plane_destroy_state(struct drm_plane *plane,
2014                                struct drm_plane_state *state);
2015 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2016 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2017                                         struct intel_crtc_state *crtc_state,
2018                                         const struct intel_plane_state *old_plane_state,
2019                                         struct intel_plane_state *intel_state);
2020
2021 /* intel_color.c */
2022 void intel_color_init(struct drm_crtc *crtc);
2023 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2024 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2025 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2026
2027 /* intel_lspcon.c */
2028 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2029 void lspcon_resume(struct intel_lspcon *lspcon);
2030 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2031
2032 /* intel_pipe_crc.c */
2033 int intel_pipe_crc_create(struct drm_minor *minor);
2034 #ifdef CONFIG_DEBUG_FS
2035 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2036                               size_t *values_cnt);
2037 #else
2038 #define intel_crtc_set_crc_source NULL
2039 #endif
2040 extern const struct file_operations i915_display_crc_ctl_fops;
2041 #endif /* __INTEL_DRV_H__ */