drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <linux/stackdepot.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_probe_helper.h>
  41 #include <drm/drm_rect.h>
  42 #include <drm/drm_vblank.h>
  43 #include <drm/drm_atomic.h>
  44 #include <drm/i915_mei_hdcp_interface.h>
  45 #include <media/cec-notifier.h>
  46
  47 struct drm_printer;
  48
  49 /**
  50  * __wait_for - magic wait macro
  51  *
  52  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
  53  * important that we check the condition again after having timed out, since the
  54  * timeout could be due to preemption or similar and we've never had a chance to
  55  * check the condition before the timeout.
  56  */
  57 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
  58         const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
  59         long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
  60         int ret__;                                                      \
  61         might_sleep();                                                  \
  62         for (;;) {                                                      \
  63                 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
  64                 OP;                                                     \
  65                 /* Guarantee COND check prior to timeout */             \
  66                 barrier();                                              \
  67                 if (COND) {                                             \
  68                         ret__ = 0;                                      \
  69                         break;                                          \
  70                 }                                                       \
  71                 if (expired__) {                                        \
  72                         ret__ = -ETIMEDOUT;                             \
  73                         break;                                          \
  74                 }                                                       \
  75                 usleep_range(wait__, wait__ * 2);                       \
  76                 if (wait__ < (Wmax))                                    \
  77                         wait__ <<= 1;                                   \
  78         }                                                               \
  79         ret__;                                                          \
  80 })
  81
  82 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
  83                                                    (Wmax))
  84 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 10, 1000)
  85
  86 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  87 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  88 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  89 #else
  90 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  91 #endif
  92
  93 #define _wait_for_atomic(COND, US, ATOMIC) \
  94 ({ \
  95         int cpu, ret, timeout = (US) * 1000; \
  96         u64 base; \
  97         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  98         if (!(ATOMIC)) { \
  99                 preempt_disable(); \
 100                 cpu = smp_processor_id(); \
 101         } \
 102         base = local_clock(); \
 103         for (;;) { \
 104                 u64 now = local_clock(); \
 105                 if (!(ATOMIC)) \
 106                         preempt_enable(); \
 107                 /* Guarantee COND check prior to timeout */ \
 108                 barrier(); \
 109                 if (COND) { \
 110                         ret = 0; \
 111                         break; \
 112                 } \
 113                 if (now - base >= timeout) { \
 114                         ret = -ETIMEDOUT; \
 115                         break; \
 116                 } \
 117                 cpu_relax(); \
 118                 if (!(ATOMIC)) { \
 119                         preempt_disable(); \
 120                         if (unlikely(cpu != smp_processor_id())) { \
 121                                 timeout -= now - base; \
 122                                 cpu = smp_processor_id(); \
 123                                 base = local_clock(); \
 124                         } \
 125                 } \
 126         } \
 127         ret; \
 128 })
 129
 130 #define wait_for_us(COND, US) \
 131 ({ \
 132         int ret__; \
 133         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 134         if ((US) > 10) \
 135                 ret__ = _wait_for((COND), (US), 10, 10); \
 136         else \
 137                 ret__ = _wait_for_atomic((COND), (US), 0); \
 138         ret__; \
 139 })
 140
 141 #define wait_for_atomic_us(COND, US) \
 142 ({ \
 143         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 144         BUILD_BUG_ON((US) > 50000); \
 145         _wait_for_atomic((COND), (US), 1); \
 146 })
 147
 148 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 149
 150 #define KHz(x) (1000 * (x))
 151 #define MHz(x) KHz(1000 * (x))
 152
 153 #define KBps(x) (1000 * (x))
 154 #define MBps(x) KBps(1000 * (x))
 155 #define GBps(x) ((u64)1000 * MBps((x)))
 156
 157 /*
 158  * Display related stuff
 159  */
 160
 161 /* store information about an Ixxx DVO */
 162 /* The i830->i865 use multiple DVOs with multiple i2cs */
 163 /* the i915, i945 have a single sDVO i2c bus - which is different */
 164 #define MAX_OUTPUTS 6
 165 /* maximum connectors per crtcs in the mode set */
 166
 167 #define INTEL_I2C_BUS_DVO 1
 168 #define INTEL_I2C_BUS_SDVO 2
 169
 170 /* these are outputs from the chip - integrated only
 171    external chips are via DVO or SDVO output */
 172 enum intel_output_type {
 173         INTEL_OUTPUT_UNUSED = 0,
 174         INTEL_OUTPUT_ANALOG = 1,
 175         INTEL_OUTPUT_DVO = 2,
 176         INTEL_OUTPUT_SDVO = 3,
 177         INTEL_OUTPUT_LVDS = 4,
 178         INTEL_OUTPUT_TVOUT = 5,
 179         INTEL_OUTPUT_HDMI = 6,
 180         INTEL_OUTPUT_DP = 7,
 181         INTEL_OUTPUT_EDP = 8,
 182         INTEL_OUTPUT_DSI = 9,
 183         INTEL_OUTPUT_DDI = 10,
 184         INTEL_OUTPUT_DP_MST = 11,
 185 };
 186
 187 #define INTEL_DVO_CHIP_NONE 0
 188 #define INTEL_DVO_CHIP_LVDS 1
 189 #define INTEL_DVO_CHIP_TMDS 2
 190 #define INTEL_DVO_CHIP_TVOUT 4
 191
 192 #define INTEL_DSI_VIDEO_MODE    0
 193 #define INTEL_DSI_COMMAND_MODE  1
 194
 195 struct intel_framebuffer {
 196         struct drm_framebuffer base;
 197         struct intel_rotation_info rot_info;
 198
 199         /* for each plane in the normal GTT view */
 200         struct {
 201                 unsigned int x, y;
 202         } normal[2];
 203         /* for each plane in the rotated GTT view */
 204         struct {
 205                 unsigned int x, y;
 206                 unsigned int pitch; /* pixels */
 207         } rotated[2];
 208 };
 209
 210 struct intel_fbdev {
 211         struct drm_fb_helper helper;
 212         struct intel_framebuffer *fb;
 213         struct i915_vma *vma;
 214         unsigned long vma_flags;
 215         async_cookie_t cookie;
 216         int preferred_bpp;
 217
 218         /* Whether or not fbdev hpd processing is temporarily suspended */
 219         bool hpd_suspended : 1;
 220         /* Set when a hotplug was received while HPD processing was
 221          * suspended
 222          */
 223         bool hpd_waiting : 1;
 224
 225         /* Protects hpd_suspended */
 226         struct mutex hpd_lock;
 227 };
 228
 229 struct intel_encoder {
 230         struct drm_encoder base;
 231
 232         enum intel_output_type type;
 233         enum port port;
 234         unsigned int cloneable;
 235         bool (*hotplug)(struct intel_encoder *encoder,
 236                         struct intel_connector *connector);
 237         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 238                                                       struct intel_crtc_state *,
 239                                                       struct drm_connector_state *);
 240         int (*compute_config)(struct intel_encoder *,
 241                               struct intel_crtc_state *,
 242                               struct drm_connector_state *);
 243         void (*pre_pll_enable)(struct intel_encoder *,
 244                                const struct intel_crtc_state *,
 245                                const struct drm_connector_state *);
 246         void (*pre_enable)(struct intel_encoder *,
 247                            const struct intel_crtc_state *,
 248                            const struct drm_connector_state *);
 249         void (*enable)(struct intel_encoder *,
 250                        const struct intel_crtc_state *,
 251                        const struct drm_connector_state *);
 252         void (*disable)(struct intel_encoder *,
 253                         const struct intel_crtc_state *,
 254                         const struct drm_connector_state *);
 255         void (*post_disable)(struct intel_encoder *,
 256                              const struct intel_crtc_state *,
 257                              const struct drm_connector_state *);
 258         void (*post_pll_disable)(struct intel_encoder *,
 259                                  const struct intel_crtc_state *,
 260                                  const struct drm_connector_state *);
 261         void (*update_pipe)(struct intel_encoder *,
 262                             const struct intel_crtc_state *,
 263                             const struct drm_connector_state *);
 264         /* Read out the current hw state of this connector, returning true if
 265          * the encoder is active. If the encoder is enabled it also set the pipe
 266          * it is connected to in the pipe parameter. */
 267         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 268         /* Reconstructs the equivalent mode flags for the current hardware
 269          * state. This must be called _after_ display->get_pipe_config has
 270          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 271          * be set correctly before calling this function. */
 272         void (*get_config)(struct intel_encoder *,
 273                            struct intel_crtc_state *pipe_config);
 274         /* Returns a mask of power domains that need to be referenced as part
 275          * of the hardware state readout code. */
 276         u64 (*get_power_domains)(struct intel_encoder *encoder,
 277                                  struct intel_crtc_state *crtc_state);
 278         /*
 279          * Called during system suspend after all pending requests for the
 280          * encoder are flushed (for example for DP AUX transactions) and
 281          * device interrupts are disabled.
 282          */
 283         void (*suspend)(struct intel_encoder *);
 284         int crtc_mask;
 285         enum hpd_pin hpd_pin;
 286         enum intel_display_power_domain power_domain;
 287         /* for communication with audio component; protected by av_mutex */
 288         const struct drm_connector *audio_connector;
 289 };
 290
 291 struct intel_panel {
 292         struct drm_display_mode *fixed_mode;
 293         struct drm_display_mode *downclock_mode;
 294
 295         /* backlight */
 296         struct {
 297                 bool present;
 298                 u32 level;
 299                 u32 min;
 300                 u32 max;
 301                 bool enabled;
 302                 bool combination_mode;  /* gen 2/4 only */
 303                 bool active_low_pwm;
 304                 bool alternate_pwm_increment;   /* lpt+ */
 305
 306                 /* PWM chip */
 307                 bool util_pin_active_low;       /* bxt+ */
 308                 u8 controller;          /* bxt+ only */
 309                 struct pwm_device *pwm;
 310
 311                 struct backlight_device *device;
 312
 313                 /* Connector and platform specific backlight functions */
 314                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 315                 u32 (*get)(struct intel_connector *connector);
 316                 void (*set)(const struct drm_connector_state *conn_state, u32 level);
 317                 void (*disable)(const struct drm_connector_state *conn_state);
 318                 void (*enable)(const struct intel_crtc_state *crtc_state,
 319                                const struct drm_connector_state *conn_state);
 320                 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
 321                 void (*power)(struct intel_connector *, bool enable);
 322         } backlight;
 323 };
 324
 325 struct intel_digital_port;
 326
 327 enum check_link_response {
 328         HDCP_LINK_PROTECTED     = 0,
 329         HDCP_TOPOLOGY_CHANGE,
 330         HDCP_LINK_INTEGRITY_FAILURE,
 331         HDCP_REAUTH_REQUEST
 332 };
 333
 334 /*
 335  * This structure serves as a translation layer between the generic HDCP code
 336  * and the bus-specific code. What that means is that HDCP over HDMI differs
 337  * from HDCP over DP, so to account for these differences, we need to
 338  * communicate with the receiver through this shim.
 339  *
 340  * For completeness, the 2 buses differ in the following ways:
 341  *      - DP AUX vs. DDC
 342  *              HDCP registers on the receiver are set via DP AUX for DP, and
 343  *              they are set via DDC for HDMI.
 344  *      - Receiver register offsets
 345  *              The offsets of the registers are different for DP vs. HDMI
 346  *      - Receiver register masks/offsets
 347  *              For instance, the ready bit for the KSV fifo is in a different
 348  *              place on DP vs HDMI
 349  *      - Receiver register names
 350  *              Seriously. In the DP spec, the 16-bit register containing
 351  *              downstream information is called BINFO, on HDMI it's called
 352  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
 353  *              with a completely different definition.
 354  *      - KSV FIFO
 355  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
 356  *              be read 3 keys at a time
 357  *      - Aksv output
 358  *              Since Aksv is hidden in hardware, there's different procedures
 359  *              to send it over DP AUX vs DDC
 360  */
 361 struct intel_hdcp_shim {
 362         /* Outputs the transmitter's An and Aksv values to the receiver. */
 363         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
 364
 365         /* Reads the receiver's key selection vector */
 366         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
 367
 368         /*
 369          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
 370          * definitions are the same in the respective specs, but the names are
 371          * different. Call it BSTATUS since that's the name the HDMI spec
 372          * uses and it was there first.
 373          */
 374         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
 375                             u8 *bstatus);
 376
 377         /* Determines whether a repeater is present downstream */
 378         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
 379                                 bool *repeater_present);
 380
 381         /* Reads the receiver's Ri' value */
 382         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
 383
 384         /* Determines if the receiver's KSV FIFO is ready for consumption */
 385         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
 386                               bool *ksv_ready);
 387
 388         /* Reads the ksv fifo for num_downstream devices */
 389         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
 390                              int num_downstream, u8 *ksv_fifo);
 391
 392         /* Reads a 32-bit part of V' from the receiver */
 393         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
 394                                  int i, u32 *part);
 395
 396         /* Enables HDCP signalling on the port */
 397         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
 398                                  bool enable);
 399
 400         /* Ensures the link is still protected */
 401         bool (*check_link)(struct intel_digital_port *intel_dig_port);
 402
 403         /* Detects panel's hdcp capability. This is optional for HDMI. */
 404         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
 405                             bool *hdcp_capable);
 406
 407         /* HDCP adaptation(DP/HDMI) required on the port */
 408         enum hdcp_wired_protocol protocol;
 409
 410         /* Detects whether sink is HDCP2.2 capable */
 411         int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
 412                                 bool *capable);
 413
 414         /* Write HDCP2.2 messages */
 415         int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
 416                              void *buf, size_t size);
 417
 418         /* Read HDCP2.2 messages */
 419         int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
 420                             u8 msg_id, void *buf, size_t size);
 421
 422         /*
 423          * Implementation of DP HDCP2.2 Errata for the communication of stream
 424          * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
 425          * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
 426          */
 427         int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
 428                                   bool is_repeater, u8 type);
 429
 430         /* HDCP2.2 Link Integrity Check */
 431         int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
 432 };
 433
 434 struct intel_hdcp {
 435         const struct intel_hdcp_shim *shim;
 436         /* Mutex for hdcp state of the connector */
 437         struct mutex mutex;
 438         u64 value;
 439         struct delayed_work check_work;
 440         struct work_struct prop_work;
 441
 442         /* HDCP1.4 Encryption status */
 443         bool hdcp_encrypted;
 444
 445         /* HDCP2.2 related definitions */
 446         /* Flag indicates whether this connector supports HDCP2.2 or not. */
 447         bool hdcp2_supported;
 448
 449         /* HDCP2.2 Encryption status */
 450         bool hdcp2_encrypted;
 451
 452         /*
 453          * Content Stream Type defined by content owner. TYPE0(0x0) content can
 454          * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
 455          * content can flow only through a link protected by HDCP2.2.
 456          */
 457         u8 content_type;
 458         struct hdcp_port_data port_data;
 459
 460         bool is_paired;
 461         bool is_repeater;
 462
 463         /*
 464          * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
 465          * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
 466          * When it rolls over re-auth has to be triggered.
 467          */
 468         u32 seq_num_v;
 469
 470         /*
 471          * Count of RepeaterAuth_Stream_Manage msg propagated.
 472          * Initialized to 0 on AKE_INIT. Incremented after every successful
 473          * transmission of RepeaterAuth_Stream_Manage message. When it rolls
 474          * over re-Auth has to be triggered.
 475          */
 476         u32 seq_num_m;
 477
 478         /*
 479          * Work queue to signal the CP_IRQ. Used for the waiters to read the
 480          * available information from HDCP DP sink.
 481          */
 482         wait_queue_head_t cp_irq_queue;
 483         atomic_t cp_irq_count;
 484         int cp_irq_count_cached;
 485 };
 486
 487 struct intel_connector {
 488         struct drm_connector base;
 489         /*
 490          * The fixed encoder this connector is connected to.
 491          */
 492         struct intel_encoder *encoder;
 493
 494         /* ACPI device id for ACPI and driver cooperation */
 495         u32 acpi_device_id;
 496
 497         /* Reads out the current hw, returning true if the connector is enabled
 498          * and active (i.e. dpms ON state). */
 499         bool (*get_hw_state)(struct intel_connector *);
 500
 501         /* Panel info for eDP and LVDS */
 502         struct intel_panel panel;
 503
 504         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 505         struct edid *edid;
 506         struct edid *detect_edid;
 507
 508         /* since POLL and HPD connectors may use the same HPD line keep the native
 509            state of connector->polled in case hotplug storm detection changes it */
 510         u8 polled;
 511
 512         void *port; /* store this opaque as its illegal to dereference it */
 513
 514         struct intel_dp *mst_port;
 515
 516         /* Work struct to schedule a uevent on link train failure */
 517         struct work_struct modeset_retry_work;
 518
 519         struct intel_hdcp hdcp;
 520 };
 521
 522 struct intel_digital_connector_state {
 523         struct drm_connector_state base;
 524
 525         enum hdmi_force_audio force_audio;
 526         int broadcast_rgb;
 527 };
 528
 529 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 530
 531 struct dpll {
 532         /* given values */
 533         int n;
 534         int m1, m2;
 535         int p1, p2;
 536         /* derived values */
 537         int     dot;
 538         int     vco;
 539         int     m;
 540         int     p;
 541 };
 542
 543 struct intel_atomic_state {
 544         struct drm_atomic_state base;
 545
 546         struct {
 547                 /*
 548                  * Logical state of cdclk (used for all scaling, watermark,
 549                  * etc. calculations and checks). This is computed as if all
 550                  * enabled crtcs were active.
 551                  */
 552                 struct intel_cdclk_state logical;
 553
 554                 /*
 555                  * Actual state of cdclk, can be different from the logical
 556                  * state only when all crtc's are DPMS off.
 557                  */
 558                 struct intel_cdclk_state actual;
 559
 560                 int force_min_cdclk;
 561                 bool force_min_cdclk_changed;
 562                 /* pipe to which cd2x update is synchronized */
 563                 enum pipe pipe;
 564         } cdclk;
 565
 566         bool dpll_set, modeset;
 567
 568         /*
 569          * Does this transaction change the pipes that are active?  This mask
 570          * tracks which CRTC's have changed their active state at the end of
 571          * the transaction (not counting the temporary disable during modesets).
 572          * This mask should only be non-zero when intel_state->modeset is true,
 573          * but the converse is not necessarily true; simply changing a mode may
 574          * not flip the final active status of any CRTC's
 575          */
 576         unsigned int active_pipe_changes;
 577
 578         unsigned int active_crtcs;
 579         /* minimum acceptable cdclk for each pipe */
 580         int min_cdclk[I915_MAX_PIPES];
 581         /* minimum acceptable voltage level for each pipe */
 582         u8 min_voltage_level[I915_MAX_PIPES];
 583
 584         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 585
 586         /*
 587          * Current watermarks can't be trusted during hardware readout, so
 588          * don't bother calculating intermediate watermarks.
 589          */
 590         bool skip_intermediate_wm;
 591
 592         bool rps_interactive;
 593
 594         /* Gen9+ only */
 595         struct skl_ddb_values wm_results;
 596
 597         struct i915_sw_fence commit_ready;
 598
 599         struct llist_node freed;
 600 };
 601
 602 struct intel_plane_state {
 603         struct drm_plane_state base;
 604         struct i915_ggtt_view view;
 605         struct i915_vma *vma;
 606         unsigned long flags;
 607 #define PLANE_HAS_FENCE BIT(0)
 608
 609         struct {
 610                 u32 offset;
 611                 /*
 612                  * Plane stride in:
 613                  * bytes for 0/180 degree rotation
 614                  * pixels for 90/270 degree rotation
 615                  */
 616                 u32 stride;
 617                 int x, y;
 618         } color_plane[2];
 619
 620         /* plane control register */
 621         u32 ctl;
 622
 623         /* plane color control register */
 624         u32 color_ctl;
 625
 626         /*
 627          * scaler_id
 628          *    = -1 : not using a scaler
 629          *    >=  0 : using a scalers
 630          *
 631          * plane requiring a scaler:
 632          *   - During check_plane, its bit is set in
 633          *     crtc_state->scaler_state.scaler_users by calling helper function
 634          *     update_scaler_plane.
 635          *   - scaler_id indicates the scaler it got assigned.
 636          *
 637          * plane doesn't require a scaler:
 638          *   - this can happen when scaling is no more required or plane simply
 639          *     got disabled.
 640          *   - During check_plane, corresponding bit is reset in
 641          *     crtc_state->scaler_state.scaler_users by calling helper function
 642          *     update_scaler_plane.
 643          */
 644         int scaler_id;
 645
 646         /*
 647          * linked_plane:
 648          *
 649          * ICL planar formats require 2 planes that are updated as pairs.
 650          * This member is used to make sure the other plane is also updated
 651          * when required, and for update_slave() to find the correct
 652          * plane_state to pass as argument.
 653          */
 654         struct intel_plane *linked_plane;
 655
 656         /*
 657          * slave:
 658          * If set don't update use the linked plane's state for updating
 659          * this plane during atomic commit with the update_slave() callback.
 660          *
 661          * It's also used by the watermark code to ignore wm calculations on
 662          * this plane. They're calculated by the linked plane's wm code.
 663          */
 664         u32 slave;
 665
 666         struct drm_intel_sprite_colorkey ckey;
 667 };
 668
 669 struct intel_initial_plane_config {
 670         struct intel_framebuffer *fb;
 671         unsigned int tiling;
 672         int size;
 673         u32 base;
 674         u8 rotation;
 675 };
 676
 677 #define SKL_MIN_SRC_W 8
 678 #define SKL_MAX_SRC_W 4096
 679 #define SKL_MIN_SRC_H 8
 680 #define SKL_MAX_SRC_H 4096
 681 #define SKL_MIN_DST_W 8
 682 #define SKL_MAX_DST_W 4096
 683 #define SKL_MIN_DST_H 8
 684 #define SKL_MAX_DST_H 4096
 685 #define ICL_MAX_SRC_W 5120
 686 #define ICL_MAX_SRC_H 4096
 687 #define ICL_MAX_DST_W 5120
 688 #define ICL_MAX_DST_H 4096
 689 #define SKL_MIN_YUV_420_SRC_W 16
 690 #define SKL_MIN_YUV_420_SRC_H 16
 691
 692 struct intel_scaler {
 693         int in_use;
 694         u32 mode;
 695 };
 696
 697 struct intel_crtc_scaler_state {
 698 #define SKL_NUM_SCALERS 2
 699         struct intel_scaler scalers[SKL_NUM_SCALERS];
 700
 701         /*
 702          * scaler_users: keeps track of users requesting scalers on this crtc.
 703          *
 704          *     If a bit is set, a user is using a scaler.
 705          *     Here user can be a plane or crtc as defined below:
 706          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 707          *       bit 31    - crtc
 708          *
 709          * Instead of creating a new index to cover planes and crtc, using
 710          * existing drm_plane_index for planes which is well less than 31
 711          * planes and bit 31 for crtc. This should be fine to cover all
 712          * our platforms.
 713          *
 714          * intel_atomic_setup_scalers will setup available scalers to users
 715          * requesting scalers. It will gracefully fail if request exceeds
 716          * avilability.
 717          */
 718 #define SKL_CRTC_INDEX 31
 719         unsigned scaler_users;
 720
 721         /* scaler used by crtc for panel fitting purpose */
 722         int scaler_id;
 723 };
 724
 725 /* drm_mode->private_flags */
 726 #define I915_MODE_FLAG_INHERITED (1<<0)
 727 /* Flag to get scanline using frame time stamps */
 728 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 729 /* Flag to use the scanline counter instead of the pixel counter */
 730 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
 731
 732 struct intel_pipe_wm {
 733         struct intel_wm_level wm[5];
 734         u32 linetime;
 735         bool fbc_wm_enabled;
 736         bool pipe_enabled;
 737         bool sprites_enabled;
 738         bool sprites_scaled;
 739 };
 740
 741 struct skl_plane_wm {
 742         struct skl_wm_level wm[8];
 743         struct skl_wm_level uv_wm[8];
 744         struct skl_wm_level trans_wm;
 745         bool is_planar;
 746 };
 747
 748 struct skl_pipe_wm {
 749         struct skl_plane_wm planes[I915_MAX_PLANES];
 750         u32 linetime;
 751 };
 752
 753 enum vlv_wm_level {
 754         VLV_WM_LEVEL_PM2,
 755         VLV_WM_LEVEL_PM5,
 756         VLV_WM_LEVEL_DDR_DVFS,
 757         NUM_VLV_WM_LEVELS,
 758 };
 759
 760 struct vlv_wm_state {
 761         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 762         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 763         u8 num_levels;
 764         bool cxsr;
 765 };
 766
 767 struct vlv_fifo_state {
 768         u16 plane[I915_MAX_PLANES];
 769 };
 770
 771 enum g4x_wm_level {
 772         G4X_WM_LEVEL_NORMAL,
 773         G4X_WM_LEVEL_SR,
 774         G4X_WM_LEVEL_HPLL,
 775         NUM_G4X_WM_LEVELS,
 776 };
 777
 778 struct g4x_wm_state {
 779         struct g4x_pipe_wm wm;
 780         struct g4x_sr_wm sr;
 781         struct g4x_sr_wm hpll;
 782         bool cxsr;
 783         bool hpll_en;
 784         bool fbc_en;
 785 };
 786
 787 struct intel_crtc_wm_state {
 788         union {
 789                 struct {
 790                         /*
 791                          * Intermediate watermarks; these can be
 792                          * programmed immediately since they satisfy
 793                          * both the current configuration we're
 794                          * switching away from and the new
 795                          * configuration we're switching to.
 796                          */
 797                         struct intel_pipe_wm intermediate;
 798
 799                         /*
 800                          * Optimal watermarks, programmed post-vblank
 801                          * when this state is committed.
 802                          */
 803                         struct intel_pipe_wm optimal;
 804                 } ilk;
 805
 806                 struct {
 807                         /* gen9+ only needs 1-step wm programming */
 808                         struct skl_pipe_wm optimal;
 809                         struct skl_ddb_entry ddb;
 810                         struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
 811                         struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
 812                 } skl;
 813
 814                 struct {
 815                         /* "raw" watermarks (not inverted) */
 816                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 817                         /* intermediate watermarks (inverted) */
 818                         struct vlv_wm_state intermediate;
 819                         /* optimal watermarks (inverted) */
 820                         struct vlv_wm_state optimal;
 821                         /* display FIFO split */
 822                         struct vlv_fifo_state fifo_state;
 823                 } vlv;
 824
 825                 struct {
 826                         /* "raw" watermarks */
 827                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 828                         /* intermediate watermarks */
 829                         struct g4x_wm_state intermediate;
 830                         /* optimal watermarks */
 831                         struct g4x_wm_state optimal;
 832                 } g4x;
 833         };
 834
 835         /*
 836          * Platforms with two-step watermark programming will need to
 837          * update watermark programming post-vblank to switch from the
 838          * safe intermediate watermarks to the optimal final
 839          * watermarks.
 840          */
 841         bool need_postvbl_update;
 842 };
 843
 844 enum intel_output_format {
 845         INTEL_OUTPUT_FORMAT_INVALID,
 846         INTEL_OUTPUT_FORMAT_RGB,
 847         INTEL_OUTPUT_FORMAT_YCBCR420,
 848         INTEL_OUTPUT_FORMAT_YCBCR444,
 849 };
 850
 851 struct intel_crtc_state {
 852         struct drm_crtc_state base;
 853
 854         /**
 855          * quirks - bitfield with hw state readout quirks
 856          *
 857          * For various reasons the hw state readout code might not be able to
 858          * completely faithfully read out the current state. These cases are
 859          * tracked with quirk flags so that fastboot and state checker can act
 860          * accordingly.
 861          */
 862 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 863         unsigned long quirks;
 864
 865         unsigned fb_bits; /* framebuffers to flip */
 866         bool update_pipe; /* can a fast modeset be performed? */
 867         bool disable_cxsr;
 868         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 869         bool fb_changed; /* fb on any of the planes is changed */
 870         bool fifo_changed; /* FIFO split is changed */
 871
 872         /* Pipe source size (ie. panel fitter input size)
 873          * All planes will be positioned inside this space,
 874          * and get clipped at the edges. */
 875         int pipe_src_w, pipe_src_h;
 876
 877         /*
 878          * Pipe pixel rate, adjusted for
 879          * panel fitter/pipe scaler downscaling.
 880          */
 881         unsigned int pixel_rate;
 882
 883         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 884          * between pch encoders and cpu encoders. */
 885         bool has_pch_encoder;
 886
 887         /* Are we sending infoframes on the attached port */
 888         bool has_infoframe;
 889
 890         /* CPU Transcoder for the pipe. Currently this can only differ from the
 891          * pipe on Haswell and later (where we have a special eDP transcoder)
 892          * and Broxton (where we have special DSI transcoders). */
 893         enum transcoder cpu_transcoder;
 894
 895         /*
 896          * Use reduced/limited/broadcast rbg range, compressing from the full
 897          * range fed into the crtcs.
 898          */
 899         bool limited_color_range;
 900
 901         /* Bitmask of encoder types (enum intel_output_type)
 902          * driven by the pipe.
 903          */
 904         unsigned int output_types;
 905
 906         /* Whether we should send NULL infoframes. Required for audio. */
 907         bool has_hdmi_sink;
 908
 909         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 910          * has_dp_encoder is set. */
 911         bool has_audio;
 912
 913         /*
 914          * Enable dithering, used when the selected pipe bpp doesn't match the
 915          * plane bpp.
 916          */
 917         bool dither;
 918
 919         /*
 920          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 921          * compliance video pattern tests.
 922          * Disable dither only if it is a compliance test request for
 923          * 18bpp.
 924          */
 925         bool dither_force_disable;
 926
 927         /* Controls for the clock computation, to override various stages. */
 928         bool clock_set;
 929
 930         /* SDVO TV has a bunch of special case. To make multifunction encoders
 931          * work correctly, we need to track this at runtime.*/
 932         bool sdvo_tv_clock;
 933
 934         /*
 935          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 936          * required. This is set in the 2nd loop of calling encoder's
 937          * ->compute_config if the first pick doesn't work out.
 938          */
 939         bool bw_constrained;
 940
 941         /* Settings for the intel dpll used on pretty much everything but
 942          * haswell. */
 943         struct dpll dpll;
 944
 945         /* Selected dpll when shared or NULL. */
 946         struct intel_shared_dpll *shared_dpll;
 947
 948         /* Actual register state of the dpll, for shared dpll cross-checking. */
 949         struct intel_dpll_hw_state dpll_hw_state;
 950
 951         /* DSI PLL registers */
 952         struct {
 953                 u32 ctrl, div;
 954         } dsi_pll;
 955
 956         int pipe_bpp;
 957         struct intel_link_m_n dp_m_n;
 958
 959         /* m2_n2 for eDP downclock */
 960         struct intel_link_m_n dp_m2_n2;
 961         bool has_drrs;
 962
 963         bool has_psr;
 964         bool has_psr2;
 965
 966         /*
 967          * Frequence the dpll for the port should run at. Differs from the
 968          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 969          * already multiplied by pixel_multiplier.
 970          */
 971         int port_clock;
 972
 973         /* Used by SDVO (and if we ever fix it, HDMI). */
 974         unsigned pixel_multiplier;
 975
 976         u8 lane_count;
 977
 978         /*
 979          * Used by platforms having DP/HDMI PHY with programmable lane
 980          * latency optimization.
 981          */
 982         u8 lane_lat_optim_mask;
 983
 984         /* minimum acceptable voltage level */
 985         u8 min_voltage_level;
 986
 987         /* Panel fitter controls for gen2-gen4 + VLV */
 988         struct {
 989                 u32 control;
 990                 u32 pgm_ratios;
 991                 u32 lvds_border_bits;
 992         } gmch_pfit;
 993
 994         /* Panel fitter placement and size for Ironlake+ */
 995         struct {
 996                 u32 pos;
 997                 u32 size;
 998                 bool enabled;
 999                 bool force_thru;
1000         } pch_pfit;
1001
1002         /* FDI configuration, only valid if has_pch_encoder is set. */
1003         int fdi_lanes;
1004         struct intel_link_m_n fdi_m_n;
1005
1006         bool ips_enabled;
1007
1008         bool crc_enabled;
1009
1010         bool enable_fbc;
1011
1012         bool double_wide;
1013
1014         int pbn;
1015
1016         struct intel_crtc_scaler_state scaler_state;
1017
1018         /* w/a for waiting 2 vblanks during crtc enable */
1019         enum pipe hsw_workaround_pipe;
1020
1021         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1022         bool disable_lp_wm;
1023
1024         struct intel_crtc_wm_state wm;
1025
1026         /* Gamma mode programmed on the pipe */
1027         u32 gamma_mode;
1028
1029         union {
1030                 /* CSC mode programmed on the pipe */
1031                 u32 csc_mode;
1032
1033                 /* CHV CGM mode */
1034                 u32 cgm_mode;
1035         };
1036
1037         /* bitmask of visible planes (enum plane_id) */
1038         u8 active_planes;
1039         u8 nv12_planes;
1040         u8 c8_planes;
1041
1042         /* bitmask of planes that will be updated during the commit */
1043         u8 update_planes;
1044
1045         struct {
1046                 u32 enable;
1047                 u32 gcp;
1048                 union hdmi_infoframe avi;
1049                 union hdmi_infoframe spd;
1050                 union hdmi_infoframe hdmi;
1051         } infoframes;
1052
1053         /* HDMI scrambling status */
1054         bool hdmi_scrambling;
1055
1056         /* HDMI High TMDS char rate ratio */
1057         bool hdmi_high_tmds_clock_ratio;
1058
1059         /* Output format RGB/YCBCR etc */
1060         enum intel_output_format output_format;
1061
1062         /* Output down scaling is done in LSPCON device */
1063         bool lspcon_downsampling;
1064
1065         /* enable pipe gamma? */
1066         bool gamma_enable;
1067
1068         /* enable pipe csc? */
1069         bool csc_enable;
1070
1071         /* Display Stream compression state */
1072         struct {
1073                 bool compression_enable;
1074                 bool dsc_split;
1075                 u16 compressed_bpp;
1076                 u8 slice_count;
1077         } dsc_params;
1078         struct drm_dsc_config dp_dsc_cfg;
1079
1080         /* Forward Error correction State */
1081         bool fec_enable;
1082 };
1083
1084 struct intel_crtc {
1085         struct drm_crtc base;
1086         enum pipe pipe;
1087         /*
1088          * Whether the crtc and the connected output pipeline is active. Implies
1089          * that crtc->enabled is set, i.e. the current mode configuration has
1090          * some outputs connected to this crtc.
1091          */
1092         bool active;
1093         u8 plane_ids_mask;
1094         unsigned long long enabled_power_domains;
1095         struct intel_overlay *overlay;
1096
1097         struct intel_crtc_state *config;
1098
1099         /* Access to these should be protected by dev_priv->irq_lock. */
1100         bool cpu_fifo_underrun_disabled;
1101         bool pch_fifo_underrun_disabled;
1102
1103         /* per-pipe watermark state */
1104         struct {
1105                 /* watermarks currently being used  */
1106                 union {
1107                         struct intel_pipe_wm ilk;
1108                         struct vlv_wm_state vlv;
1109                         struct g4x_wm_state g4x;
1110                 } active;
1111         } wm;
1112
1113         int scanline_offset;
1114
1115         struct {
1116                 unsigned start_vbl_count;
1117                 ktime_t start_vbl_time;
1118                 int min_vbl, max_vbl;
1119                 int scanline_start;
1120         } debug;
1121
1122         /* scalers available on this crtc */
1123         int num_scalers;
1124 };
1125
1126 struct intel_plane {
1127         struct drm_plane base;
1128         enum i9xx_plane_id i9xx_plane;
1129         enum plane_id id;
1130         enum pipe pipe;
1131         bool has_fbc;
1132         bool has_ccs;
1133         u32 frontbuffer_bit;
1134
1135         struct {
1136                 u32 base, cntl, size;
1137         } cursor;
1138
1139         /*
1140          * NOTE: Do not place new plane state fields here (e.g., when adding
1141          * new plane properties).  New runtime state should now be placed in
1142          * the intel_plane_state structure and accessed via plane_state.
1143          */
1144
1145         unsigned int (*max_stride)(struct intel_plane *plane,
1146                                    u32 pixel_format, u64 modifier,
1147                                    unsigned int rotation);
1148         void (*update_plane)(struct intel_plane *plane,
1149                              const struct intel_crtc_state *crtc_state,
1150                              const struct intel_plane_state *plane_state);
1151         void (*update_slave)(struct intel_plane *plane,
1152                              const struct intel_crtc_state *crtc_state,
1153                              const struct intel_plane_state *plane_state);
1154         void (*disable_plane)(struct intel_plane *plane,
1155                               const struct intel_crtc_state *crtc_state);
1156         bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1157         int (*check_plane)(struct intel_crtc_state *crtc_state,
1158                            struct intel_plane_state *plane_state);
1159 };
1160
1161 struct intel_watermark_params {
1162         u16 fifo_size;
1163         u16 max_wm;
1164         u8 default_wm;
1165         u8 guard_size;
1166         u8 cacheline_size;
1167 };
1168
1169 struct cxsr_latency {
1170         bool is_desktop : 1;
1171         bool is_ddr3 : 1;
1172         u16 fsb_freq;
1173         u16 mem_freq;
1174         u16 display_sr;
1175         u16 display_hpll_disable;
1176         u16 cursor_sr;
1177         u16 cursor_hpll_disable;
1178 };
1179
1180 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1181 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1182 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1183 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1184 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1185 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1186 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1187 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1188 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1189
1190 struct intel_hdmi {
1191         i915_reg_t hdmi_reg;
1192         int ddc_bus;
1193         struct {
1194                 enum drm_dp_dual_mode_type type;
1195                 int max_tmds_clock;
1196         } dp_dual_mode;
1197         bool has_hdmi_sink;
1198         bool has_audio;
1199         struct intel_connector *attached_connector;
1200         struct cec_notifier *cec_notifier;
1201 };
1202
1203 struct intel_dp_mst_encoder;
1204 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1205
1206 /*
1207  * enum link_m_n_set:
1208  *      When platform provides two set of M_N registers for dp, we can
1209  *      program them and switch between them incase of DRRS.
1210  *      But When only one such register is provided, we have to program the
1211  *      required divider value on that registers itself based on the DRRS state.
1212  *
1213  * M1_N1        : Program dp_m_n on M1_N1 registers
1214  *                        dp_m2_n2 on M2_N2 registers (If supported)
1215  *
1216  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1217  *                        M2_N2 registers are not supported
1218  */
1219
1220 enum link_m_n_set {
1221         /* Sets the m1_n1 and m2_n2 */
1222         M1_N1 = 0,
1223         M2_N2
1224 };
1225
1226 struct intel_dp_compliance_data {
1227         unsigned long edid;
1228         u8 video_pattern;
1229         u16 hdisplay, vdisplay;
1230         u8 bpc;
1231 };
1232
1233 struct intel_dp_compliance {
1234         unsigned long test_type;
1235         struct intel_dp_compliance_data test_data;
1236         bool test_active;
1237         int test_link_rate;
1238         u8 test_lane_count;
1239 };
1240
1241 struct intel_dp {
1242         i915_reg_t output_reg;
1243         u32 DP;
1244         int link_rate;
1245         u8 lane_count;
1246         u8 sink_count;
1247         bool link_mst;
1248         bool link_trained;
1249         bool has_audio;
1250         bool reset_link_params;
1251         u8 dpcd[DP_RECEIVER_CAP_SIZE];
1252         u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1253         u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1254         u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1255         u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1256         u8 fec_capable;
1257         /* source rates */
1258         int num_source_rates;
1259         const int *source_rates;
1260         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1261         int num_sink_rates;
1262         int sink_rates[DP_MAX_SUPPORTED_RATES];
1263         bool use_rate_select;
1264         /* intersection of source and sink rates */
1265         int num_common_rates;
1266         int common_rates[DP_MAX_SUPPORTED_RATES];
1267         /* Max lane count for the current link */
1268         int max_link_lane_count;
1269         /* Max rate for the current link */
1270         int max_link_rate;
1271         /* sink or branch descriptor */
1272         struct drm_dp_desc desc;
1273         struct drm_dp_aux aux;
1274         u8 train_set[4];
1275         int panel_power_up_delay;
1276         int panel_power_down_delay;
1277         int panel_power_cycle_delay;
1278         int backlight_on_delay;
1279         int backlight_off_delay;
1280         struct delayed_work panel_vdd_work;
1281         bool want_panel_vdd;
1282         unsigned long last_power_on;
1283         unsigned long last_backlight_off;
1284         ktime_t panel_power_off_time;
1285
1286         struct notifier_block edp_notifier;
1287
1288         /*
1289          * Pipe whose power sequencer is currently locked into
1290          * this port. Only relevant on VLV/CHV.
1291          */
1292         enum pipe pps_pipe;
1293         /*
1294          * Pipe currently driving the port. Used for preventing
1295          * the use of the PPS for any pipe currentrly driving
1296          * external DP as that will mess things up on VLV.
1297          */
1298         enum pipe active_pipe;
1299         /*
1300          * Set if the sequencer may be reset due to a power transition,
1301          * requiring a reinitialization. Only relevant on BXT.
1302          */
1303         bool pps_reset;
1304         struct edp_power_seq pps_delays;
1305
1306         bool can_mst; /* this port supports mst */
1307         bool is_mst;
1308         int active_mst_links;
1309         /* connector directly attached - won't be use for modeset in mst world */
1310         struct intel_connector *attached_connector;
1311
1312         /* mst connector list */
1313         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1314         struct drm_dp_mst_topology_mgr mst_mgr;
1315
1316         u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1317         /*
1318          * This function returns the value we have to program the AUX_CTL
1319          * register with to kick off an AUX transaction.
1320          */
1321         u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1322                                 u32 aux_clock_divider);
1323
1324         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1325         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1326
1327         /* This is called before a link training is starterd */
1328         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1329
1330         /* Displayport compliance testing */
1331         struct intel_dp_compliance compliance;
1332
1333         /* Display stream compression testing */
1334         bool force_dsc_en;
1335 };
1336
1337 enum lspcon_vendor {
1338         LSPCON_VENDOR_MCA,
1339         LSPCON_VENDOR_PARADE
1340 };
1341
1342 struct intel_lspcon {
1343         bool active;
1344         enum drm_lspcon_mode mode;
1345         enum lspcon_vendor vendor;
1346 };
1347
1348 struct intel_digital_port {
1349         struct intel_encoder base;
1350         u32 saved_port_bits;
1351         struct intel_dp dp;
1352         struct intel_hdmi hdmi;
1353         struct intel_lspcon lspcon;
1354         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1355         bool release_cl2_override;
1356         u8 max_lanes;
1357         /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1358         enum aux_ch aux_ch;
1359         enum intel_display_power_domain ddi_io_power_domain;
1360         bool tc_legacy_port:1;
1361         enum tc_port_type tc_type;
1362
1363         void (*write_infoframe)(struct intel_encoder *encoder,
1364                                 const struct intel_crtc_state *crtc_state,
1365                                 unsigned int type,
1366                                 const void *frame, ssize_t len);
1367         void (*read_infoframe)(struct intel_encoder *encoder,
1368                                const struct intel_crtc_state *crtc_state,
1369                                unsigned int type,
1370                                void *frame, ssize_t len);
1371         void (*set_infoframes)(struct intel_encoder *encoder,
1372                                bool enable,
1373                                const struct intel_crtc_state *crtc_state,
1374                                const struct drm_connector_state *conn_state);
1375         u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1376                                   const struct intel_crtc_state *pipe_config);
1377 };
1378
1379 struct intel_dp_mst_encoder {
1380         struct intel_encoder base;
1381         enum pipe pipe;
1382         struct intel_digital_port *primary;
1383         struct intel_connector *connector;
1384 };
1385
1386 static inline enum dpio_channel
1387 vlv_dport_to_channel(struct intel_digital_port *dport)
1388 {
1389         switch (dport->base.port) {
1390         case PORT_B:
1391         case PORT_D:
1392                 return DPIO_CH0;
1393         case PORT_C:
1394                 return DPIO_CH1;
1395         default:
1396                 BUG();
1397         }
1398 }
1399
1400 static inline enum dpio_phy
1401 vlv_dport_to_phy(struct intel_digital_port *dport)
1402 {
1403         switch (dport->base.port) {
1404         case PORT_B:
1405         case PORT_C:
1406                 return DPIO_PHY0;
1407         case PORT_D:
1408                 return DPIO_PHY1;
1409         default:
1410                 BUG();
1411         }
1412 }
1413
1414 static inline enum dpio_channel
1415 vlv_pipe_to_channel(enum pipe pipe)
1416 {
1417         switch (pipe) {
1418         case PIPE_A:
1419         case PIPE_C:
1420                 return DPIO_CH0;
1421         case PIPE_B:
1422                 return DPIO_CH1;
1423         default:
1424                 BUG();
1425         }
1426 }
1427
1428 static inline struct intel_crtc *
1429 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1430 {
1431         return dev_priv->pipe_to_crtc_mapping[pipe];
1432 }
1433
1434 static inline struct intel_crtc *
1435 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1436 {
1437         return dev_priv->plane_to_crtc_mapping[plane];
1438 }
1439
1440 struct intel_load_detect_pipe {
1441         struct drm_atomic_state *restore_state;
1442 };
1443
1444 static inline struct intel_encoder *
1445 intel_attached_encoder(struct drm_connector *connector)
1446 {
1447         return to_intel_connector(connector)->encoder;
1448 }
1449
1450 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1451 {
1452         switch (encoder->type) {
1453         case INTEL_OUTPUT_DDI:
1454         case INTEL_OUTPUT_DP:
1455         case INTEL_OUTPUT_EDP:
1456         case INTEL_OUTPUT_HDMI:
1457                 return true;
1458         default:
1459                 return false;
1460         }
1461 }
1462
1463 static inline struct intel_digital_port *
1464 enc_to_dig_port(struct drm_encoder *encoder)
1465 {
1466         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1467
1468         if (intel_encoder_is_dig_port(intel_encoder))
1469                 return container_of(encoder, struct intel_digital_port,
1470                                     base.base);
1471         else
1472                 return NULL;
1473 }
1474
1475 static inline struct intel_digital_port *
1476 conn_to_dig_port(struct intel_connector *connector)
1477 {
1478         return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1479 }
1480
1481 static inline struct intel_dp_mst_encoder *
1482 enc_to_mst(struct drm_encoder *encoder)
1483 {
1484         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1485 }
1486
1487 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1488 {
1489         return &enc_to_dig_port(encoder)->dp;
1490 }
1491
1492 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1493 {
1494         switch (encoder->type) {
1495         case INTEL_OUTPUT_DP:
1496         case INTEL_OUTPUT_EDP:
1497                 return true;
1498         case INTEL_OUTPUT_DDI:
1499                 /* Skip pure HDMI/DVI DDI encoders */
1500                 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1501         default:
1502                 return false;
1503         }
1504 }
1505
1506 static inline struct intel_lspcon *
1507 enc_to_intel_lspcon(struct drm_encoder *encoder)
1508 {
1509         return &enc_to_dig_port(encoder)->lspcon;
1510 }
1511
1512 static inline struct intel_digital_port *
1513 dp_to_dig_port(struct intel_dp *intel_dp)
1514 {
1515         return container_of(intel_dp, struct intel_digital_port, dp);
1516 }
1517
1518 static inline struct intel_lspcon *
1519 dp_to_lspcon(struct intel_dp *intel_dp)
1520 {
1521         return &dp_to_dig_port(intel_dp)->lspcon;
1522 }
1523
1524 static inline struct drm_i915_private *
1525 dp_to_i915(struct intel_dp *intel_dp)
1526 {
1527         return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1528 }
1529
1530 static inline struct intel_digital_port *
1531 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1532 {
1533         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1534 }
1535
1536 static inline struct intel_plane_state *
1537 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1538                                  struct intel_plane *plane)
1539 {
1540         struct drm_plane_state *ret =
1541                 drm_atomic_get_plane_state(&state->base, &plane->base);
1542
1543         if (IS_ERR(ret))
1544                 return ERR_CAST(ret);
1545
1546         return to_intel_plane_state(ret);
1547 }
1548
1549 static inline struct intel_plane_state *
1550 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1551                                  struct intel_plane *plane)
1552 {
1553         return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1554                                                                    &plane->base));
1555 }
1556
1557 static inline struct intel_plane_state *
1558 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1559                                  struct intel_plane *plane)
1560 {
1561         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1562                                                                    &plane->base));
1563 }
1564
1565 static inline struct intel_crtc_state *
1566 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1567                                 struct intel_crtc *crtc)
1568 {
1569         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1570                                                                  &crtc->base));
1571 }
1572
1573 static inline struct intel_crtc_state *
1574 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1575                                 struct intel_crtc *crtc)
1576 {
1577         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1578                                                                  &crtc->base));
1579 }
1580
1581 /* intel_fifo_underrun.c */
1582 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1583                                            enum pipe pipe, bool enable);
1584 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1585                                            enum pipe pch_transcoder,
1586                                            bool enable);
1587 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1588                                          enum pipe pipe);
1589 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1590                                          enum pipe pch_transcoder);
1591 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1592 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1593
1594 /* i915_irq.c */
1595 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
1596 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
1597 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1598 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1599 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1600 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1601 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1602 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1603
1604 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1605                                             u32 mask)
1606 {
1607         return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1608 }
1609
1610 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1611 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1612 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1613 {
1614         /*
1615          * We only use drm_irq_uninstall() at unload and VT switch, so
1616          * this is the only thing we need to check.
1617          */
1618         return dev_priv->runtime_pm.irqs_enabled;
1619 }
1620
1621 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1622 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1623                                      u8 pipe_mask);
1624 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1625                                      u8 pipe_mask);
1626 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1627 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1628 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1629
1630 /* intel_crt.c */
1631 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1632                             i915_reg_t adpa_reg, enum pipe *pipe);
1633 void intel_crt_init(struct drm_i915_private *dev_priv);
1634 void intel_crt_reset(struct drm_encoder *encoder);
1635
1636 /* intel_ddi.c */
1637 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1638                                 const struct intel_crtc_state *old_crtc_state,
1639                                 const struct drm_connector_state *old_conn_state);
1640 void hsw_fdi_link_train(struct intel_crtc *crtc,
1641                         const struct intel_crtc_state *crtc_state);
1642 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1643 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1644 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1645 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1646 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1647 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1648 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1649 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1650 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1651 void intel_ddi_get_config(struct intel_encoder *encoder,
1652                           struct intel_crtc_state *pipe_config);
1653
1654 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1655                                     bool state);
1656 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1657                                          struct intel_crtc_state *crtc_state);
1658 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1659 u32 ddi_signal_levels(struct intel_dp *intel_dp);
1660 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1661 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1662                                  u8 voltage_swing);
1663 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1664                                      bool enable);
1665 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
1666 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1667                         struct intel_dpll_hw_state *state);
1668
1669 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1670                                    int color_plane, unsigned int height);
1671
1672 /* intel_audio.c */
1673 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1674 void intel_audio_codec_enable(struct intel_encoder *encoder,
1675                               const struct intel_crtc_state *crtc_state,
1676                               const struct drm_connector_state *conn_state);
1677 void intel_audio_codec_disable(struct intel_encoder *encoder,
1678                                const struct intel_crtc_state *old_crtc_state,
1679                                const struct drm_connector_state *old_conn_state);
1680 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1681 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1682 void intel_audio_init(struct drm_i915_private *dev_priv);
1683 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1684
1685 /* intel_cdclk.c */
1686 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1687 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1688 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1689 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1690 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1691 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1692 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1693 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1694 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1695 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1696 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1697 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1698 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1699 bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv,
1700                                    const struct intel_cdclk_state *a,
1701                                    const struct intel_cdclk_state *b);
1702 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1703                                const struct intel_cdclk_state *b);
1704 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1705                          const struct intel_cdclk_state *b);
1706 void intel_cdclk_swap_state(struct intel_atomic_state *state);
1707 void
1708 intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
1709                                  const struct intel_cdclk_state *old_state,
1710                                  const struct intel_cdclk_state *new_state,
1711                                  enum pipe pipe);
1712 void
1713 intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
1714                                   const struct intel_cdclk_state *old_state,
1715                                   const struct intel_cdclk_state *new_state,
1716                                   enum pipe pipe);
1717 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1718                             const char *context);
1719
1720 /* intel_display.c */
1721 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1722 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1723 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1724 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1725 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1726                       const char *name, u32 reg, int ref_freq);
1727 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1728                            const char *name, u32 reg);
1729 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1730 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1731 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1732 unsigned int intel_fb_xy_to_linear(int x, int y,
1733                                    const struct intel_plane_state *state,
1734                                    int plane);
1735 void intel_add_fb_offsets(int *x, int *y,
1736                           const struct intel_plane_state *state, int plane);
1737 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1738 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1739 void intel_mark_busy(struct drm_i915_private *dev_priv);
1740 void intel_mark_idle(struct drm_i915_private *dev_priv);
1741 int intel_display_suspend(struct drm_device *dev);
1742 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1743 void intel_encoder_destroy(struct drm_encoder *encoder);
1744 struct drm_display_mode *
1745 intel_encoder_current_mode(struct intel_encoder *encoder);
1746 bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
1747 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1748 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1749                               enum port port);
1750 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1751                                       struct drm_file *file_priv);
1752 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1753                                              enum pipe pipe);
1754 static inline bool
1755 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1756                     enum intel_output_type type)
1757 {
1758         return crtc_state->output_types & (1 << type);
1759 }
1760 static inline bool
1761 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1762 {
1763         return crtc_state->output_types &
1764                 ((1 << INTEL_OUTPUT_DP) |
1765                  (1 << INTEL_OUTPUT_DP_MST) |
1766                  (1 << INTEL_OUTPUT_EDP));
1767 }
1768 static inline void
1769 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1770 {
1771         drm_wait_one_vblank(&dev_priv->drm, pipe);
1772 }
1773 static inline void
1774 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1775 {
1776         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1777
1778         if (crtc->active)
1779                 intel_wait_for_vblank(dev_priv, pipe);
1780 }
1781
1782 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1783
1784 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1785 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1786                          struct intel_digital_port *dport,
1787                          unsigned int expected_mask);
1788 int intel_get_load_detect_pipe(struct drm_connector *connector,
1789                                const struct drm_display_mode *mode,
1790                                struct intel_load_detect_pipe *old,
1791                                struct drm_modeset_acquire_ctx *ctx);
1792 void intel_release_load_detect_pipe(struct drm_connector *connector,
1793                                     struct intel_load_detect_pipe *old,
1794                                     struct drm_modeset_acquire_ctx *ctx);
1795 struct i915_vma *
1796 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1797                            const struct i915_ggtt_view *view,
1798                            bool uses_fence,
1799                            unsigned long *out_flags);
1800 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1801 struct drm_framebuffer *
1802 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1803                          struct drm_mode_fb_cmd2 *mode_cmd);
1804 int intel_prepare_plane_fb(struct drm_plane *plane,
1805                            struct drm_plane_state *new_state);
1806 void intel_cleanup_plane_fb(struct drm_plane *plane,
1807                             struct drm_plane_state *old_state);
1808 int intel_plane_atomic_get_property(struct drm_plane *plane,
1809                                     const struct drm_plane_state *state,
1810                                     struct drm_property *property,
1811                                     u64 *val);
1812 int intel_plane_atomic_set_property(struct drm_plane *plane,
1813                                     struct drm_plane_state *state,
1814                                     struct drm_property *property,
1815                                     u64 val);
1816 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1817                                     struct drm_crtc_state *crtc_state,
1818                                     const struct intel_plane_state *old_plane_state,
1819                                     struct drm_plane_state *plane_state);
1820
1821 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1822                                     enum pipe pipe);
1823
1824 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1825                      const struct dpll *dpll);
1826 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1827 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1828
1829 /* modesetting asserts */
1830 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1831                            enum pipe pipe);
1832 void assert_pll(struct drm_i915_private *dev_priv,
1833                 enum pipe pipe, bool state);
1834 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1835 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1836 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1837 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1838 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1839 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1840                        enum pipe pipe, bool state);
1841 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1842 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1843 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1844 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1845 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1846 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1847 void intel_finish_reset(struct drm_i915_private *dev_priv);
1848 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1849 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1850 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1851 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1852 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1853 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1854 unsigned int skl_cdclk_get_vco(unsigned int freq);
1855 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1856 void intel_dp_get_m_n(struct intel_crtc *crtc,
1857                       struct intel_crtc_state *pipe_config);
1858 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
1859                       enum link_m_n_set m_n);
1860 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1861 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1862                         struct dpll *best_clock);
1863 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1864
1865 bool intel_crtc_active(struct intel_crtc *crtc);
1866 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1867 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1868 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1869 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1870 enum intel_display_power_domain
1871 intel_aux_power_domain(struct intel_digital_port *dig_port);
1872 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1873                                  struct intel_crtc_state *pipe_config);
1874 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1875                                   struct intel_crtc_state *crtc_state);
1876
1877 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
1878 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1879 int skl_max_scale(const struct intel_crtc_state *crtc_state,
1880                   u32 pixel_format);
1881
1882 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1883 {
1884         return i915_ggtt_offset(state->vma);
1885 }
1886
1887 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1888                         const struct intel_plane_state *plane_state);
1889 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
1890 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1891                   const struct intel_plane_state *plane_state);
1892 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
1893 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
1894                      int plane);
1895 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1896 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1897 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1898 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
1899                                    u32 pixel_format, u64 modifier,
1900                                    unsigned int rotation);
1901
1902 /* intel_connector.c */
1903 int intel_connector_init(struct intel_connector *connector);
1904 struct intel_connector *intel_connector_alloc(void);
1905 void intel_connector_free(struct intel_connector *connector);
1906 void intel_connector_destroy(struct drm_connector *connector);
1907 int intel_connector_register(struct drm_connector *connector);
1908 void intel_connector_unregister(struct drm_connector *connector);
1909 void intel_connector_attach_encoder(struct intel_connector *connector,
1910                                     struct intel_encoder *encoder);
1911 bool intel_connector_get_hw_state(struct intel_connector *connector);
1912 enum pipe intel_connector_get_pipe(struct intel_connector *connector);
1913 int intel_connector_update_modes(struct drm_connector *connector,
1914                                  struct edid *edid);
1915 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1916 void intel_attach_force_audio_property(struct drm_connector *connector);
1917 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1918 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1919 void intel_attach_colorspace_property(struct drm_connector *connector);
1920
1921 /* intel_csr.c */
1922 void intel_csr_ucode_init(struct drm_i915_private *);
1923 void intel_csr_load_program(struct drm_i915_private *);
1924 void intel_csr_ucode_fini(struct drm_i915_private *);
1925 void intel_csr_ucode_suspend(struct drm_i915_private *);
1926 void intel_csr_ucode_resume(struct drm_i915_private *);
1927
1928 /* intel_dp.c */
1929 struct link_config_limits {
1930         int min_clock, max_clock;
1931         int min_lane_count, max_lane_count;
1932         int min_bpp, max_bpp;
1933 };
1934 void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1935                                        struct intel_crtc_state *pipe_config,
1936                                        struct link_config_limits *limits);
1937 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
1938                                   const struct drm_connector_state *conn_state);
1939 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1940                            i915_reg_t dp_reg, enum port port,
1941                            enum pipe *pipe);
1942 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1943                    enum port port);
1944 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1945                              struct intel_connector *intel_connector);
1946 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1947                               int link_rate, u8 lane_count,
1948                               bool link_mst);
1949 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1950                                             int link_rate, u8 lane_count);
1951 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1952 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1953 int intel_dp_retrain_link(struct intel_encoder *encoder,
1954                           struct drm_modeset_acquire_ctx *ctx);
1955 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1956 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
1957                                            const struct intel_crtc_state *crtc_state,
1958                                            bool enable);
1959 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1960 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1961 void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
1962 int intel_dp_compute_config(struct intel_encoder *encoder,
1963                             struct intel_crtc_state *pipe_config,
1964                             struct drm_connector_state *conn_state);
1965 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1966 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1967 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1968                                   bool long_hpd);
1969 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1970                             const struct drm_connector_state *conn_state);
1971 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1972 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1973 void intel_edp_panel_on(struct intel_dp *intel_dp);
1974 void intel_edp_panel_off(struct intel_dp *intel_dp);
1975 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1976 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1977 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1978 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1979 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1980 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1981 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1982 u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
1983 void intel_plane_destroy(struct drm_plane *plane);
1984 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1985                            const struct intel_crtc_state *crtc_state);
1986 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1987                             const struct intel_crtc_state *crtc_state);
1988 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1989                                unsigned int frontbuffer_bits);
1990 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1991                           unsigned int frontbuffer_bits);
1992
1993 void
1994 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1995                                        u8 dp_train_pat);
1996 void
1997 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1998 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1999 u8
2000 intel_dp_voltage_max(struct intel_dp *intel_dp);
2001 u8
2002 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing);
2003 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
2004                            u8 *link_bw, u8 *rate_select);
2005 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
2006 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
2007 bool
2008 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE]);
2009 u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
2010                                 int mode_clock, int mode_hdisplay);
2011 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
2012                                 int mode_hdisplay);
2013
2014 /* intel_vdsc.c */
2015 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
2016                                 struct intel_crtc_state *pipe_config);
2017 enum intel_display_power_domain
2018 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
2019
2020 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
2021 {
2022         return ~((1 << lane_count) - 1) & 0xf;
2023 }
2024
2025 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
2026 int intel_dp_link_required(int pixel_clock, int bpp);
2027 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
2028 bool intel_digital_port_connected(struct intel_encoder *encoder);
2029 void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
2030                            struct intel_digital_port *dig_port);
2031
2032 /* intel_dp_aux_backlight.c */
2033 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
2034
2035 /* intel_dp_mst.c */
2036 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
2037 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
2038 /* vlv_dsi.c */
2039 void vlv_dsi_init(struct drm_i915_private *dev_priv);
2040
2041 /* icl_dsi.c */
2042 void icl_dsi_init(struct drm_i915_private *dev_priv);
2043
2044 /* intel_dsi_dcs_backlight.c */
2045 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
2046
2047 /* intel_dvo.c */
2048 void intel_dvo_init(struct drm_i915_private *dev_priv);
2049 /* intel_hotplug.c */
2050 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
2051 bool intel_encoder_hotplug(struct intel_encoder *encoder,
2052                            struct intel_connector *connector);
2053
2054 /* legacy fbdev emulation in intel_fbdev.c */
2055 #ifdef CONFIG_DRM_FBDEV_EMULATION
2056 extern int intel_fbdev_init(struct drm_device *dev);
2057 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
2058 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
2059 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
2060 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
2061 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
2062 extern void intel_fbdev_restore_mode(struct drm_device *dev);
2063 #else
2064 static inline int intel_fbdev_init(struct drm_device *dev)
2065 {
2066         return 0;
2067 }
2068
2069 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
2070 {
2071 }
2072
2073 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
2074 {
2075 }
2076
2077 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
2078 {
2079 }
2080
2081 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
2082 {
2083 }
2084
2085 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
2086 {
2087 }
2088
2089 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
2090 {
2091 }
2092 #endif
2093
2094 /* intel_fbc.c */
2095 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
2096                            struct intel_atomic_state *state);
2097 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
2098 void intel_fbc_pre_update(struct intel_crtc *crtc,
2099                           struct intel_crtc_state *crtc_state,
2100                           struct intel_plane_state *plane_state);
2101 void intel_fbc_post_update(struct intel_crtc *crtc);
2102 void intel_fbc_init(struct drm_i915_private *dev_priv);
2103 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
2104 void intel_fbc_enable(struct intel_crtc *crtc,
2105                       struct intel_crtc_state *crtc_state,
2106                       struct intel_plane_state *plane_state);
2107 void intel_fbc_disable(struct intel_crtc *crtc);
2108 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
2109 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
2110                           unsigned int frontbuffer_bits,
2111                           enum fb_op_origin origin);
2112 void intel_fbc_flush(struct drm_i915_private *dev_priv,
2113                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
2114 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
2115 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
2116 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
2117
2118 /* intel_hdmi.c */
2119 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
2120                      enum port port);
2121 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2122                                struct intel_connector *intel_connector);
2123 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
2124 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2125                               struct intel_crtc_state *pipe_config,
2126                               struct drm_connector_state *conn_state);
2127 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2128                                        struct drm_connector *connector,
2129                                        bool high_tmds_clock_ratio,
2130                                        bool scrambling);
2131 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
2132 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
2133 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
2134                                   const struct intel_crtc_state *crtc_state);
2135 u32 intel_hdmi_infoframe_enable(unsigned int type);
2136 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
2137                                    struct intel_crtc_state *crtc_state);
2138 void intel_read_infoframe(struct intel_encoder *encoder,
2139                           const struct intel_crtc_state *crtc_state,
2140                           enum hdmi_infoframe_type type,
2141                           union hdmi_infoframe *frame);
2142
2143 /* intel_lvds.c */
2144 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
2145                              i915_reg_t lvds_reg, enum pipe *pipe);
2146 void intel_lvds_init(struct drm_i915_private *dev_priv);
2147 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv);
2148 bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv);
2149
2150 /* intel_overlay.c */
2151 void intel_overlay_setup(struct drm_i915_private *dev_priv);
2152 void intel_overlay_cleanup(struct drm_i915_private *dev_priv);
2153 int intel_overlay_switch_off(struct intel_overlay *overlay);
2154 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
2155                                   struct drm_file *file_priv);
2156 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
2157                               struct drm_file *file_priv);
2158 void intel_overlay_reset(struct drm_i915_private *dev_priv);
2159
2160
2161 /* intel_panel.c */
2162 int intel_panel_init(struct intel_panel *panel,
2163                      struct drm_display_mode *fixed_mode,
2164                      struct drm_display_mode *downclock_mode);
2165 void intel_panel_fini(struct intel_panel *panel);
2166 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
2167                             struct drm_display_mode *adjusted_mode);
2168 void intel_pch_panel_fitting(struct intel_crtc *crtc,
2169                              struct intel_crtc_state *pipe_config,
2170                              int fitting_mode);
2171 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
2172                               struct intel_crtc_state *pipe_config,
2173                               int fitting_mode);
2174 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
2175                                     u32 level, u32 max);
2176 int intel_panel_setup_backlight(struct drm_connector *connector,
2177                                 enum pipe pipe);
2178 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
2179                                   const struct drm_connector_state *conn_state);
2180 void intel_panel_update_backlight(struct intel_encoder *encoder,
2181                                   const struct intel_crtc_state *crtc_state,
2182                                   const struct drm_connector_state *conn_state);
2183 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
2184 struct drm_display_mode *
2185 intel_panel_edid_downclock_mode(struct intel_connector *connector,
2186                                 const struct drm_display_mode *fixed_mode);
2187 struct drm_display_mode *
2188 intel_panel_edid_fixed_mode(struct intel_connector *connector);
2189 struct drm_display_mode *
2190 intel_panel_vbt_fixed_mode(struct intel_connector *connector);
2191
2192 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
2193 int intel_backlight_device_register(struct intel_connector *connector);
2194 void intel_backlight_device_unregister(struct intel_connector *connector);
2195 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2196 static inline int intel_backlight_device_register(struct intel_connector *connector)
2197 {
2198         return 0;
2199 }
2200 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
2201 {
2202 }
2203 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
2204
2205 /* intel_hdcp.c */
2206 void intel_hdcp_atomic_check(struct drm_connector *connector,
2207                              struct drm_connector_state *old_state,
2208                              struct drm_connector_state *new_state);
2209 int intel_hdcp_init(struct intel_connector *connector,
2210                     const struct intel_hdcp_shim *hdcp_shim);
2211 int intel_hdcp_enable(struct intel_connector *connector);
2212 int intel_hdcp_disable(struct intel_connector *connector);
2213 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
2214 bool intel_hdcp_capable(struct intel_connector *connector);
2215 void intel_hdcp_component_init(struct drm_i915_private *dev_priv);
2216 void intel_hdcp_component_fini(struct drm_i915_private *dev_priv);
2217 void intel_hdcp_cleanup(struct intel_connector *connector);
2218 void intel_hdcp_handle_cp_irq(struct intel_connector *connector);
2219
2220 /* intel_psr.c */
2221 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
2222 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
2223 void intel_psr_enable(struct intel_dp *intel_dp,
2224                       const struct intel_crtc_state *crtc_state);
2225 void intel_psr_disable(struct intel_dp *intel_dp,
2226                       const struct intel_crtc_state *old_crtc_state);
2227 void intel_psr_update(struct intel_dp *intel_dp,
2228                       const struct intel_crtc_state *crtc_state);
2229 int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 value);
2230 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2231                           unsigned frontbuffer_bits,
2232                           enum fb_op_origin origin);
2233 void intel_psr_flush(struct drm_i915_private *dev_priv,
2234                      unsigned frontbuffer_bits,
2235                      enum fb_op_origin origin);
2236 void intel_psr_init(struct drm_i915_private *dev_priv);
2237 void intel_psr_compute_config(struct intel_dp *intel_dp,
2238                               struct intel_crtc_state *crtc_state);
2239 void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
2240 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
2241 void intel_psr_short_pulse(struct intel_dp *intel_dp);
2242 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
2243                             u32 *out_value);
2244 bool intel_psr_enabled(struct intel_dp *intel_dp);
2245
2246 /* intel_quirks.c */
2247 void intel_init_quirks(struct drm_i915_private *dev_priv);
2248
2249 /* intel_runtime_pm.c */
2250 void intel_runtime_pm_init_early(struct drm_i915_private *dev_priv);
2251 int intel_power_domains_init(struct drm_i915_private *);
2252 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
2253 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
2254 void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
2255 void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2256 void icl_display_core_uninit(struct drm_i915_private *dev_priv);
2257 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
2258 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
2259
2260 enum i915_drm_suspend_mode {
2261         I915_DRM_SUSPEND_IDLE,
2262         I915_DRM_SUSPEND_MEM,
2263         I915_DRM_SUSPEND_HIBERNATE,
2264 };
2265
2266 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
2267                                  enum i915_drm_suspend_mode);
2268 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
2269 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
2270 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
2271 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
2272 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
2273 void intel_runtime_pm_cleanup(struct drm_i915_private *dev_priv);
2274 const char *
2275 intel_display_power_domain_str(enum intel_display_power_domain domain);
2276
2277 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2278                                     enum intel_display_power_domain domain);
2279 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
2280                                       enum intel_display_power_domain domain);
2281 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
2282                                         enum intel_display_power_domain domain);
2283 intel_wakeref_t
2284 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
2285                                    enum intel_display_power_domain domain);
2286 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
2287                                        enum intel_display_power_domain domain);
2288 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2289 void intel_display_power_put(struct drm_i915_private *dev_priv,
2290                              enum intel_display_power_domain domain,
2291                              intel_wakeref_t wakeref);
2292 #else
2293 #define intel_display_power_put(i915, domain, wakeref) \
2294         intel_display_power_put_unchecked(i915, domain)
2295 #endif
2296 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
2297                             u8 req_slices);
2298
2299 static inline void
2300 assert_rpm_device_not_suspended(struct i915_runtime_pm *rpm)
2301 {
2302         WARN_ONCE(rpm->suspended,
2303                   "Device suspended during HW access\n");
2304 }
2305
2306 static inline void
2307 __assert_rpm_wakelock_held(struct i915_runtime_pm *rpm)
2308 {
2309         assert_rpm_device_not_suspended(rpm);
2310         WARN_ONCE(!atomic_read(&rpm->wakeref_count),
2311                   "RPM wakelock ref not held during HW access");
2312 }
2313
2314 static inline void
2315 assert_rpm_wakelock_held(struct drm_i915_private *i915)
2316 {
2317         __assert_rpm_wakelock_held(&i915->runtime_pm);
2318 }
2319
2320 /**
2321  * disable_rpm_wakeref_asserts - disable the RPM assert checks
2322  * @i915: i915 device instance
2323  *
2324  * This function disable asserts that check if we hold an RPM wakelock
2325  * reference, while keeping the device-not-suspended checks still enabled.
2326  * It's meant to be used only in special circumstances where our rule about
2327  * the wakelock refcount wrt. the device power state doesn't hold. According
2328  * to this rule at any point where we access the HW or want to keep the HW in
2329  * an active state we must hold an RPM wakelock reference acquired via one of
2330  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
2331  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
2332  * forcewake release timer, and the GPU RPS and hangcheck works. All other
2333  * users should avoid using this function.
2334  *
2335  * Any calls to this function must have a symmetric call to
2336  * enable_rpm_wakeref_asserts().
2337  */
2338 static inline void
2339 disable_rpm_wakeref_asserts(struct drm_i915_private *i915)
2340 {
2341         atomic_inc(&i915->runtime_pm.wakeref_count);
2342 }
2343
2344 /**
2345  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2346  * @i915: i915 device instance
2347  *
2348  * This function re-enables the RPM assert checks after disabling them with
2349  * disable_rpm_wakeref_asserts. It's meant to be used only in special
2350  * circumstances otherwise its use should be avoided.
2351  *
2352  * Any calls to this function must have a symmetric call to
2353  * disable_rpm_wakeref_asserts().
2354  */
2355 static inline void
2356 enable_rpm_wakeref_asserts(struct drm_i915_private *i915)
2357 {
2358         atomic_dec(&i915->runtime_pm.wakeref_count);
2359 }
2360
2361 intel_wakeref_t intel_runtime_pm_get(struct drm_i915_private *i915);
2362 intel_wakeref_t intel_runtime_pm_get_if_in_use(struct drm_i915_private *i915);
2363 intel_wakeref_t intel_runtime_pm_get_noresume(struct drm_i915_private *i915);
2364
2365 #define with_intel_runtime_pm(i915, wf) \
2366         for ((wf) = intel_runtime_pm_get(i915); (wf); \
2367              intel_runtime_pm_put((i915), (wf)), (wf) = 0)
2368
2369 #define with_intel_runtime_pm_if_in_use(i915, wf) \
2370         for ((wf) = intel_runtime_pm_get_if_in_use(i915); (wf); \
2371              intel_runtime_pm_put((i915), (wf)), (wf) = 0)
2372
2373 void intel_runtime_pm_put_unchecked(struct drm_i915_private *i915);
2374 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2375 void intel_runtime_pm_put(struct drm_i915_private *i915, intel_wakeref_t wref);
2376 #else
2377 #define intel_runtime_pm_put(i915, wref) intel_runtime_pm_put_unchecked(i915)
2378 #endif
2379
2380 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
2381 void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
2382                                     struct drm_printer *p);
2383 #else
2384 static inline void print_intel_runtime_pm_wakeref(struct drm_i915_private *i915,
2385                                                   struct drm_printer *p)
2386 {
2387 }
2388 #endif
2389
2390 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2391                              bool override, unsigned int mask);
2392 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2393                           enum dpio_channel ch, bool override);
2394
2395
2396 /* intel_pm.c */
2397 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2398 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2399 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2400 void intel_update_watermarks(struct intel_crtc *crtc);
2401 void intel_init_pm(struct drm_i915_private *dev_priv);
2402 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2403 void intel_pm_setup(struct drm_i915_private *dev_priv);
2404 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2405 void intel_gpu_ips_teardown(void);
2406 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2407 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2408 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2409 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2410 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2411 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2412 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2413 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2414 void gen6_rps_boost(struct i915_request *rq);
2415 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
2416 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
2417 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
2418 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
2419 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
2420                                struct skl_ddb_entry *ddb_y,
2421                                struct skl_ddb_entry *ddb_uv);
2422 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2423                           struct skl_ddb_allocation *ddb /* out */);
2424 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
2425                               struct skl_pipe_wm *out);
2426 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2427 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2428 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2429 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2430 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2431 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2432                          const struct skl_wm_level *l2);
2433 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
2434                                  const struct skl_ddb_entry entries[],
2435                                  int num_entries, int ignore_idx);
2436 void skl_write_plane_wm(struct intel_plane *plane,
2437                         const struct intel_crtc_state *crtc_state);
2438 void skl_write_cursor_wm(struct intel_plane *plane,
2439                          const struct intel_crtc_state *crtc_state);
2440 bool ilk_disable_lp_wm(struct drm_device *dev);
2441 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2442                                   struct intel_crtc_state *cstate);
2443 void intel_init_ipc(struct drm_i915_private *dev_priv);
2444 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2445
2446 /* intel_sdvo.c */
2447 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2448                              i915_reg_t sdvo_reg, enum pipe *pipe);
2449 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2450                      i915_reg_t reg, enum port port);
2451
2452
2453 /* intel_sprite.c */
2454 bool is_planar_yuv_format(u32 pixelformat);
2455 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2456                              int usecs);
2457 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2458                                               enum pipe pipe, int plane);
2459 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2460                                     struct drm_file *file_priv);
2461 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2462 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2463 int intel_plane_check_stride(const struct intel_plane_state *plane_state);
2464 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
2465 int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
2466 struct intel_plane *
2467 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2468                            enum pipe pipe, enum plane_id plane_id);
2469
2470 static inline bool icl_is_nv12_y_plane(enum plane_id id)
2471 {
2472         /* Don't need to do a gen check, these planes are only available on gen11 */
2473         if (id == PLANE_SPRITE4 || id == PLANE_SPRITE5)
2474                 return true;
2475
2476         return false;
2477 }
2478
2479 static inline bool icl_is_hdr_plane(struct drm_i915_private *dev_priv,
2480                                     enum plane_id plane_id)
2481 {
2482         if (INTEL_GEN(dev_priv) < 11)
2483                 return false;
2484
2485         return plane_id < PLANE_SPRITE2;
2486 }
2487
2488 /* intel_tv.c */
2489 void intel_tv_init(struct drm_i915_private *dev_priv);
2490
2491 /* intel_atomic.c */
2492 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2493                                                 const struct drm_connector_state *state,
2494                                                 struct drm_property *property,
2495                                                 u64 *val);
2496 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2497                                                 struct drm_connector_state *state,
2498                                                 struct drm_property *property,
2499                                                 u64 val);
2500 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2501                                          struct drm_connector_state *new_state);
2502 struct drm_connector_state *
2503 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2504
2505 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2506 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2507                                struct drm_crtc_state *state);
2508 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2509 void intel_atomic_state_clear(struct drm_atomic_state *);
2510
2511 static inline struct intel_crtc_state *
2512 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2513                             struct intel_crtc *crtc)
2514 {
2515         struct drm_crtc_state *crtc_state;
2516         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2517         if (IS_ERR(crtc_state))
2518                 return ERR_CAST(crtc_state);
2519
2520         return to_intel_crtc_state(crtc_state);
2521 }
2522
2523 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2524                                struct intel_crtc *intel_crtc,
2525                                struct intel_crtc_state *crtc_state);
2526
2527 /* intel_atomic_plane.c */
2528 void intel_update_plane(struct intel_plane *plane,
2529                         const struct intel_crtc_state *crtc_state,
2530                         const struct intel_plane_state *plane_state);
2531 void intel_update_slave(struct intel_plane *plane,
2532                         const struct intel_crtc_state *crtc_state,
2533                         const struct intel_plane_state *plane_state);
2534 void intel_disable_plane(struct intel_plane *plane,
2535                          const struct intel_crtc_state *crtc_state);
2536 struct intel_plane *intel_plane_alloc(void);
2537 void intel_plane_free(struct intel_plane *plane);
2538 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2539 void intel_plane_destroy_state(struct drm_plane *plane,
2540                                struct drm_plane_state *state);
2541 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2542 void skl_update_planes_on_crtc(struct intel_atomic_state *state,
2543                                struct intel_crtc *crtc);
2544 void i9xx_update_planes_on_crtc(struct intel_atomic_state *state,
2545                                 struct intel_crtc *crtc);
2546 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2547                                         struct intel_crtc_state *crtc_state,
2548                                         const struct intel_plane_state *old_plane_state,
2549                                         struct intel_plane_state *intel_state);
2550
2551 /* intel_color.c */
2552 void intel_color_init(struct intel_crtc *crtc);
2553 int intel_color_check(struct intel_crtc_state *crtc_state);
2554 void intel_color_commit(const struct intel_crtc_state *crtc_state);
2555 void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
2556
2557 /* intel_lspcon.c */
2558 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2559 void lspcon_resume(struct intel_lspcon *lspcon);
2560 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2561 void lspcon_write_infoframe(struct intel_encoder *encoder,
2562                             const struct intel_crtc_state *crtc_state,
2563                             unsigned int type,
2564                             const void *buf, ssize_t len);
2565 void lspcon_read_infoframe(struct intel_encoder *encoder,
2566                            const struct intel_crtc_state *crtc_state,
2567                            unsigned int type,
2568                            void *frame, ssize_t len);
2569 void lspcon_set_infoframes(struct intel_encoder *encoder,
2570                            bool enable,
2571                            const struct intel_crtc_state *crtc_state,
2572                            const struct drm_connector_state *conn_state);
2573 u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
2574                               const struct intel_crtc_state *pipe_config);
2575 void lspcon_ycbcr420_config(struct drm_connector *connector,
2576                             struct intel_crtc_state *crtc_state);
2577
2578 /* intel_pipe_crc.c */
2579 #ifdef CONFIG_DEBUG_FS
2580 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name);
2581 int intel_crtc_verify_crc_source(struct drm_crtc *crtc,
2582                                  const char *source_name, size_t *values_cnt);
2583 const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
2584                                               size_t *count);
2585 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2586 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2587 #else
2588 #define intel_crtc_set_crc_source NULL
2589 #define intel_crtc_verify_crc_source NULL
2590 #define intel_crtc_get_crc_sources NULL
2591 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2592 {
2593 }
2594
2595 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2596 {
2597 }
2598 #endif
2599 #endif /* __INTEL_DRV_H__ */