drivers/gpu/drm/i915/intel_dram.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include "i915_drv.h"
   7 #include "i915_reg.h"
   8 #include "intel_dram.h"
   9 #include "intel_mchbar_regs.h"
  10 #include "intel_pcode.h"
  11
  12 struct dram_dimm_info {
  13         u16 size;
  14         u8 width, ranks;
  15 };
  16
  17 struct dram_channel_info {
  18         struct dram_dimm_info dimm_l, dimm_s;
  19         u8 ranks;
  20         bool is_16gb_dimm;
  21 };
  22
  23 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
  24
  25 static const char *intel_dram_type_str(enum intel_dram_type type)
  26 {
  27         static const char * const str[] = {
  28                 DRAM_TYPE_STR(UNKNOWN),
  29                 DRAM_TYPE_STR(DDR3),
  30                 DRAM_TYPE_STR(DDR4),
  31                 DRAM_TYPE_STR(LPDDR3),
  32                 DRAM_TYPE_STR(LPDDR4),
  33         };
  34
  35         if (type >= ARRAY_SIZE(str))
  36                 type = INTEL_DRAM_UNKNOWN;
  37
  38         return str[type];
  39 }
  40
  41 #undef DRAM_TYPE_STR
  42
  43 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
  44 {
  45         return dimm->ranks * 64 / (dimm->width ?: 1);
  46 }
  47
  48 /* Returns total Gb for the whole DIMM */
  49 static int skl_get_dimm_size(u16 val)
  50 {
  51         return (val & SKL_DRAM_SIZE_MASK) * 8;
  52 }
  53
  54 static int skl_get_dimm_width(u16 val)
  55 {
  56         if (skl_get_dimm_size(val) == 0)
  57                 return 0;
  58
  59         switch (val & SKL_DRAM_WIDTH_MASK) {
  60         case SKL_DRAM_WIDTH_X8:
  61         case SKL_DRAM_WIDTH_X16:
  62         case SKL_DRAM_WIDTH_X32:
  63                 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
  64                 return 8 << val;
  65         default:
  66                 MISSING_CASE(val);
  67                 return 0;
  68         }
  69 }
  70
  71 static int skl_get_dimm_ranks(u16 val)
  72 {
  73         if (skl_get_dimm_size(val) == 0)
  74                 return 0;
  75
  76         val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
  77
  78         return val + 1;
  79 }
  80
  81 /* Returns total Gb for the whole DIMM */
  82 static int icl_get_dimm_size(u16 val)
  83 {
  84         return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;
  85 }
  86
  87 static int icl_get_dimm_width(u16 val)
  88 {
  89         if (icl_get_dimm_size(val) == 0)
  90                 return 0;
  91
  92         switch (val & ICL_DRAM_WIDTH_MASK) {
  93         case ICL_DRAM_WIDTH_X8:
  94         case ICL_DRAM_WIDTH_X16:
  95         case ICL_DRAM_WIDTH_X32:
  96                 val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
  97                 return 8 << val;
  98         default:
  99                 MISSING_CASE(val);
 100                 return 0;
 101         }
 102 }
 103
 104 static int icl_get_dimm_ranks(u16 val)
 105 {
 106         if (icl_get_dimm_size(val) == 0)
 107                 return 0;
 108
 109         val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;
 110
 111         return val + 1;
 112 }
 113
 114 static bool
 115 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
 116 {
 117         /* Convert total Gb to Gb per DRAM device */
 118         return dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
 119 }
 120
 121 static void
 122 skl_dram_get_dimm_info(struct drm_i915_private *i915,
 123                        struct dram_dimm_info *dimm,
 124                        int channel, char dimm_name, u16 val)
 125 {
 126         if (GRAPHICS_VER(i915) >= 11) {
 127                 dimm->size = icl_get_dimm_size(val);
 128                 dimm->width = icl_get_dimm_width(val);
 129                 dimm->ranks = icl_get_dimm_ranks(val);
 130         } else {
 131                 dimm->size = skl_get_dimm_size(val);
 132                 dimm->width = skl_get_dimm_width(val);
 133                 dimm->ranks = skl_get_dimm_ranks(val);
 134         }
 135
 136         drm_dbg_kms(&i915->drm,
 137                     "CH%u DIMM %c size: %u Gb, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
 138                     channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
 139                     yesno(skl_is_16gb_dimm(dimm)));
 140 }
 141
 142 static int
 143 skl_dram_get_channel_info(struct drm_i915_private *i915,
 144                           struct dram_channel_info *ch,
 145                           int channel, u32 val)
 146 {
 147         skl_dram_get_dimm_info(i915, &ch->dimm_l,
 148                                channel, 'L', val & 0xffff);
 149         skl_dram_get_dimm_info(i915, &ch->dimm_s,
 150                                channel, 'S', val >> 16);
 151
 152         if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
 153                 drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel);
 154                 return -EINVAL;
 155         }
 156
 157         if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
 158                 ch->ranks = 2;
 159         else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
 160                 ch->ranks = 2;
 161         else
 162                 ch->ranks = 1;
 163
 164         ch->is_16gb_dimm = skl_is_16gb_dimm(&ch->dimm_l) ||
 165                 skl_is_16gb_dimm(&ch->dimm_s);
 166
 167         drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb DIMMs: %s\n",
 168                     channel, ch->ranks, yesno(ch->is_16gb_dimm));
 169
 170         return 0;
 171 }
 172
 173 static bool
 174 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
 175                         const struct dram_channel_info *ch1)
 176 {
 177         return !memcmp(ch0, ch1, sizeof(*ch0)) &&
 178                 (ch0->dimm_s.size == 0 ||
 179                  !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
 180 }
 181
 182 static int
 183 skl_dram_get_channels_info(struct drm_i915_private *i915)
 184 {
 185         struct dram_info *dram_info = &i915->dram_info;
 186         struct dram_channel_info ch0 = {}, ch1 = {};
 187         u32 val;
 188         int ret;
 189
 190         val = intel_uncore_read(&i915->uncore,
 191                                 SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
 192         ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
 193         if (ret == 0)
 194                 dram_info->num_channels++;
 195
 196         val = intel_uncore_read(&i915->uncore,
 197                                 SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
 198         ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
 199         if (ret == 0)
 200                 dram_info->num_channels++;
 201
 202         if (dram_info->num_channels == 0) {
 203                 drm_info(&i915->drm, "Number of memory channels is zero\n");
 204                 return -EINVAL;
 205         }
 206
 207         if (ch0.ranks == 0 && ch1.ranks == 0) {
 208                 drm_info(&i915->drm, "couldn't get memory rank information\n");
 209                 return -EINVAL;
 210         }
 211
 212         dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
 213
 214         dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
 215
 216         drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n",
 217                     yesno(dram_info->symmetric_memory));
 218
 219         return 0;
 220 }
 221
 222 static enum intel_dram_type
 223 skl_get_dram_type(struct drm_i915_private *i915)
 224 {
 225         u32 val;
 226
 227         val = intel_uncore_read(&i915->uncore,
 228                                 SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
 229
 230         switch (val & SKL_DRAM_DDR_TYPE_MASK) {
 231         case SKL_DRAM_DDR_TYPE_DDR3:
 232                 return INTEL_DRAM_DDR3;
 233         case SKL_DRAM_DDR_TYPE_DDR4:
 234                 return INTEL_DRAM_DDR4;
 235         case SKL_DRAM_DDR_TYPE_LPDDR3:
 236                 return INTEL_DRAM_LPDDR3;
 237         case SKL_DRAM_DDR_TYPE_LPDDR4:
 238                 return INTEL_DRAM_LPDDR4;
 239         default:
 240                 MISSING_CASE(val);
 241                 return INTEL_DRAM_UNKNOWN;
 242         }
 243 }
 244
 245 static int
 246 skl_get_dram_info(struct drm_i915_private *i915)
 247 {
 248         struct dram_info *dram_info = &i915->dram_info;
 249         int ret;
 250
 251         dram_info->type = skl_get_dram_type(i915);
 252         drm_dbg_kms(&i915->drm, "DRAM type: %s\n",
 253                     intel_dram_type_str(dram_info->type));
 254
 255         ret = skl_dram_get_channels_info(i915);
 256         if (ret)
 257                 return ret;
 258
 259         return 0;
 260 }
 261
 262 /* Returns Gb per DRAM device */
 263 static int bxt_get_dimm_size(u32 val)
 264 {
 265         switch (val & BXT_DRAM_SIZE_MASK) {
 266         case BXT_DRAM_SIZE_4GBIT:
 267                 return 4;
 268         case BXT_DRAM_SIZE_6GBIT:
 269                 return 6;
 270         case BXT_DRAM_SIZE_8GBIT:
 271                 return 8;
 272         case BXT_DRAM_SIZE_12GBIT:
 273                 return 12;
 274         case BXT_DRAM_SIZE_16GBIT:
 275                 return 16;
 276         default:
 277                 MISSING_CASE(val);
 278                 return 0;
 279         }
 280 }
 281
 282 static int bxt_get_dimm_width(u32 val)
 283 {
 284         if (!bxt_get_dimm_size(val))
 285                 return 0;
 286
 287         val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
 288
 289         return 8 << val;
 290 }
 291
 292 static int bxt_get_dimm_ranks(u32 val)
 293 {
 294         if (!bxt_get_dimm_size(val))
 295                 return 0;
 296
 297         switch (val & BXT_DRAM_RANK_MASK) {
 298         case BXT_DRAM_RANK_SINGLE:
 299                 return 1;
 300         case BXT_DRAM_RANK_DUAL:
 301                 return 2;
 302         default:
 303                 MISSING_CASE(val);
 304                 return 0;
 305         }
 306 }
 307
 308 static enum intel_dram_type bxt_get_dimm_type(u32 val)
 309 {
 310         if (!bxt_get_dimm_size(val))
 311                 return INTEL_DRAM_UNKNOWN;
 312
 313         switch (val & BXT_DRAM_TYPE_MASK) {
 314         case BXT_DRAM_TYPE_DDR3:
 315                 return INTEL_DRAM_DDR3;
 316         case BXT_DRAM_TYPE_LPDDR3:
 317                 return INTEL_DRAM_LPDDR3;
 318         case BXT_DRAM_TYPE_DDR4:
 319                 return INTEL_DRAM_DDR4;
 320         case BXT_DRAM_TYPE_LPDDR4:
 321                 return INTEL_DRAM_LPDDR4;
 322         default:
 323                 MISSING_CASE(val);
 324                 return INTEL_DRAM_UNKNOWN;
 325         }
 326 }
 327
 328 static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val)
 329 {
 330         dimm->width = bxt_get_dimm_width(val);
 331         dimm->ranks = bxt_get_dimm_ranks(val);
 332
 333         /*
 334          * Size in register is Gb per DRAM device. Convert to total
 335          * Gb to match the way we report this for non-LP platforms.
 336          */
 337         dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm);
 338 }
 339
 340 static int bxt_get_dram_info(struct drm_i915_private *i915)
 341 {
 342         struct dram_info *dram_info = &i915->dram_info;
 343         u32 val;
 344         u8 valid_ranks = 0;
 345         int i;
 346
 347         /*
 348          * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
 349          */
 350         for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
 351                 struct dram_dimm_info dimm;
 352                 enum intel_dram_type type;
 353
 354                 val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i));
 355                 if (val == 0xFFFFFFFF)
 356                         continue;
 357
 358                 dram_info->num_channels++;
 359
 360                 bxt_get_dimm_info(&dimm, val);
 361                 type = bxt_get_dimm_type(val);
 362
 363                 drm_WARN_ON(&i915->drm, type != INTEL_DRAM_UNKNOWN &&
 364                             dram_info->type != INTEL_DRAM_UNKNOWN &&
 365                             dram_info->type != type);
 366
 367                 drm_dbg_kms(&i915->drm,
 368                             "CH%u DIMM size: %u Gb, width: X%u, ranks: %u, type: %s\n",
 369                             i - BXT_D_CR_DRP0_DUNIT_START,
 370                             dimm.size, dimm.width, dimm.ranks,
 371                             intel_dram_type_str(type));
 372
 373                 if (valid_ranks == 0)
 374                         valid_ranks = dimm.ranks;
 375
 376                 if (type != INTEL_DRAM_UNKNOWN)
 377                         dram_info->type = type;
 378         }
 379
 380         if (dram_info->type == INTEL_DRAM_UNKNOWN || valid_ranks == 0) {
 381                 drm_info(&i915->drm, "couldn't get memory information\n");
 382                 return -EINVAL;
 383         }
 384
 385         return 0;
 386 }
 387
 388 static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
 389 {
 390         struct dram_info *dram_info = &dev_priv->dram_info;
 391         u32 val = 0;
 392         int ret;
 393
 394         ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
 395                              ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
 396         if (ret)
 397                 return ret;
 398
 399         if (GRAPHICS_VER(dev_priv) == 12) {
 400                 switch (val & 0xf) {
 401                 case 0:
 402                         dram_info->type = INTEL_DRAM_DDR4;
 403                         break;
 404                 case 1:
 405                         dram_info->type = INTEL_DRAM_DDR5;
 406                         break;
 407                 case 2:
 408                         dram_info->type = INTEL_DRAM_LPDDR5;
 409                         break;
 410                 case 3:
 411                         dram_info->type = INTEL_DRAM_LPDDR4;
 412                         break;
 413                 case 4:
 414                         dram_info->type = INTEL_DRAM_DDR3;
 415                         break;
 416                 case 5:
 417                         dram_info->type = INTEL_DRAM_LPDDR3;
 418                         break;
 419                 default:
 420                         MISSING_CASE(val & 0xf);
 421                         return -EINVAL;
 422                 }
 423         } else {
 424                 switch (val & 0xf) {
 425                 case 0:
 426                         dram_info->type = INTEL_DRAM_DDR4;
 427                         break;
 428                 case 1:
 429                         dram_info->type = INTEL_DRAM_DDR3;
 430                         break;
 431                 case 2:
 432                         dram_info->type = INTEL_DRAM_LPDDR3;
 433                         break;
 434                 case 3:
 435                         dram_info->type = INTEL_DRAM_LPDDR4;
 436                         break;
 437                 default:
 438                         MISSING_CASE(val & 0xf);
 439                         return -EINVAL;
 440                 }
 441         }
 442
 443         dram_info->num_channels = (val & 0xf0) >> 4;
 444         dram_info->num_qgv_points = (val & 0xf00) >> 8;
 445         dram_info->num_psf_gv_points = (val & 0x3000) >> 12;
 446
 447         return 0;
 448 }
 449
 450 static int gen11_get_dram_info(struct drm_i915_private *i915)
 451 {
 452         int ret = skl_get_dram_info(i915);
 453
 454         if (ret)
 455                 return ret;
 456
 457         return icl_pcode_read_mem_global_info(i915);
 458 }
 459
 460 static int gen12_get_dram_info(struct drm_i915_private *i915)
 461 {
 462         i915->dram_info.wm_lv_0_adjust_needed = false;
 463
 464         return icl_pcode_read_mem_global_info(i915);
 465 }
 466
 467 void intel_dram_detect(struct drm_i915_private *i915)
 468 {
 469         struct dram_info *dram_info = &i915->dram_info;
 470         int ret;
 471
 472         if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915))
 473                 return;
 474
 475         /*
 476          * Assume level 0 watermark latency adjustment is needed until proven
 477          * otherwise, this w/a is not needed by bxt/glk.
 478          */
 479         dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);
 480
 481         if (GRAPHICS_VER(i915) >= 12)
 482                 ret = gen12_get_dram_info(i915);
 483         else if (GRAPHICS_VER(i915) >= 11)
 484                 ret = gen11_get_dram_info(i915);
 485         else if (IS_GEN9_LP(i915))
 486                 ret = bxt_get_dram_info(i915);
 487         else
 488                 ret = skl_get_dram_info(i915);
 489         if (ret)
 490                 return;
 491
 492         drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels);
 493
 494         drm_dbg_kms(&i915->drm, "Watermark level 0 adjustment needed: %s\n",
 495                     yesno(dram_info->wm_lv_0_adjust_needed));
 496 }
 497
 498 static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
 499 {
 500         static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
 501         static const u8 sets[4] = { 1, 1, 2, 2 };
 502
 503         return EDRAM_NUM_BANKS(cap) *
 504                 ways[EDRAM_WAYS_IDX(cap)] *
 505                 sets[EDRAM_SETS_IDX(cap)];
 506 }
 507
 508 void intel_dram_edram_detect(struct drm_i915_private *i915)
 509 {
 510         u32 edram_cap = 0;
 511
 512         if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9))
 513                 return;
 514
 515         edram_cap = __raw_uncore_read32(&i915->uncore, HSW_EDRAM_CAP);
 516
 517         /* NB: We can't write IDICR yet because we don't have gt funcs set up */
 518
 519         if (!(edram_cap & EDRAM_ENABLED))
 520                 return;
 521
 522         /*
 523          * The needed capability bits for size calculation are not there with
 524          * pre gen9 so return 128MB always.
 525          */
 526         if (GRAPHICS_VER(i915) < 9)
 527                 i915->edram_size_mb = 128;
 528         else
 529                 i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap);
 530
 531         drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb);
 532 }