drivers/gpu/drm/i915/intel_dpll_mgr.c

   1 /*
   2  * Copyright © 2006-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_drv.h"
  25
  26 /**
  27  * DOC: Display PLLs
  28  *
  29  * Display PLLs used for driving outputs vary by platform. While some have
  30  * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
  31  * from a pool. In the latter scenario, it is possible that multiple pipes
  32  * share a PLL if their configurations match.
  33  *
  34  * This file provides an abstraction over display PLLs. The function
  35  * intel_shared_dpll_init() initializes the PLLs for the given platform.  The
  36  * users of a PLL are tracked and that tracking is integrated with the atomic
  37  * modest interface. During an atomic operation, a PLL can be requested for a
  38  * given CRTC and encoder configuration by calling intel_get_shared_dpll() and
  39  * a previously used PLL can be released with intel_release_shared_dpll().
  40  * Changes to the users are first staged in the atomic state, and then made
  41  * effective by calling intel_shared_dpll_swap_state() during the atomic
  42  * commit phase.
  43  */
  44
  45 static void
  46 intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
  47                                   struct intel_shared_dpll_state *shared_dpll)
  48 {
  49         enum intel_dpll_id i;
  50
  51         /* Copy shared dpll state */
  52         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  53                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  54
  55                 shared_dpll[i] = pll->state;
  56         }
  57 }
  58
  59 static struct intel_shared_dpll_state *
  60 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
  61 {
  62         struct intel_atomic_state *state = to_intel_atomic_state(s);
  63
  64         WARN_ON(!drm_modeset_is_locked(&s->dev->mode_config.connection_mutex));
  65
  66         if (!state->dpll_set) {
  67                 state->dpll_set = true;
  68
  69                 intel_atomic_duplicate_dpll_state(to_i915(s->dev),
  70                                                   state->shared_dpll);
  71         }
  72
  73         return state->shared_dpll;
  74 }
  75
  76 /**
  77  * intel_get_shared_dpll_by_id - get a DPLL given its id
  78  * @dev_priv: i915 device instance
  79  * @id: pll id
  80  *
  81  * Returns:
  82  * A pointer to the DPLL with @id
  83  */
  84 struct intel_shared_dpll *
  85 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
  86                             enum intel_dpll_id id)
  87 {
  88         return &dev_priv->shared_dplls[id];
  89 }
  90
  91 /**
  92  * intel_get_shared_dpll_id - get the id of a DPLL
  93  * @dev_priv: i915 device instance
  94  * @pll: the DPLL
  95  *
  96  * Returns:
  97  * The id of @pll
  98  */
  99 enum intel_dpll_id
 100 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
 101                          struct intel_shared_dpll *pll)
 102 {
 103         if (WARN_ON(pll < dev_priv->shared_dplls||
 104                     pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll]))
 105                 return -1;
 106
 107         return (enum intel_dpll_id) (pll - dev_priv->shared_dplls);
 108 }
 109
 110 /* For ILK+ */
 111 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 112                         struct intel_shared_dpll *pll,
 113                         bool state)
 114 {
 115         bool cur_state;
 116         struct intel_dpll_hw_state hw_state;
 117
 118         if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
 119                 return;
 120
 121         cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state);
 122         I915_STATE_WARN(cur_state != state,
 123              "%s assertion failure (expected %s, current %s)\n",
 124                         pll->info->name, onoff(state), onoff(cur_state));
 125 }
 126
 127 /**
 128  * intel_prepare_shared_dpll - call a dpll's prepare hook
 129  * @crtc_state: CRTC, and its state, which has a shared dpll
 130  *
 131  * This calls the PLL's prepare hook if it has one and if the PLL is not
 132  * already enabled. The prepare hook is platform specific.
 133  */
 134 void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state)
 135 {
 136         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 137         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 138         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 139
 140         if (WARN_ON(pll == NULL))
 141                 return;
 142
 143         mutex_lock(&dev_priv->dpll_lock);
 144         WARN_ON(!pll->state.crtc_mask);
 145         if (!pll->active_mask) {
 146                 DRM_DEBUG_DRIVER("setting up %s\n", pll->info->name);
 147                 WARN_ON(pll->on);
 148                 assert_shared_dpll_disabled(dev_priv, pll);
 149
 150                 pll->info->funcs->prepare(dev_priv, pll);
 151         }
 152         mutex_unlock(&dev_priv->dpll_lock);
 153 }
 154
 155 /**
 156  * intel_enable_shared_dpll - enable a CRTC's shared DPLL
 157  * @crtc_state: CRTC, and its state, which has a shared DPLL
 158  *
 159  * Enable the shared DPLL used by @crtc.
 160  */
 161 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
 162 {
 163         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 164         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 165         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 166         unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
 167         unsigned int old_mask;
 168
 169         if (WARN_ON(pll == NULL))
 170                 return;
 171
 172         mutex_lock(&dev_priv->dpll_lock);
 173         old_mask = pll->active_mask;
 174
 175         if (WARN_ON(!(pll->state.crtc_mask & crtc_mask)) ||
 176             WARN_ON(pll->active_mask & crtc_mask))
 177                 goto out;
 178
 179         pll->active_mask |= crtc_mask;
 180
 181         DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n",
 182                       pll->info->name, pll->active_mask, pll->on,
 183                       crtc->base.base.id);
 184
 185         if (old_mask) {
 186                 WARN_ON(!pll->on);
 187                 assert_shared_dpll_enabled(dev_priv, pll);
 188                 goto out;
 189         }
 190         WARN_ON(pll->on);
 191
 192         DRM_DEBUG_KMS("enabling %s\n", pll->info->name);
 193         pll->info->funcs->enable(dev_priv, pll);
 194         pll->on = true;
 195
 196 out:
 197         mutex_unlock(&dev_priv->dpll_lock);
 198 }
 199
 200 /**
 201  * intel_disable_shared_dpll - disable a CRTC's shared DPLL
 202  * @crtc_state: CRTC, and its state, which has a shared DPLL
 203  *
 204  * Disable the shared DPLL used by @crtc.
 205  */
 206 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
 207 {
 208         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 209         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 210         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 211         unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
 212
 213         /* PCH only available on ILK+ */
 214         if (INTEL_GEN(dev_priv) < 5)
 215                 return;
 216
 217         if (pll == NULL)
 218                 return;
 219
 220         mutex_lock(&dev_priv->dpll_lock);
 221         if (WARN_ON(!(pll->active_mask & crtc_mask)))
 222                 goto out;
 223
 224         DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n",
 225                       pll->info->name, pll->active_mask, pll->on,
 226                       crtc->base.base.id);
 227
 228         assert_shared_dpll_enabled(dev_priv, pll);
 229         WARN_ON(!pll->on);
 230
 231         pll->active_mask &= ~crtc_mask;
 232         if (pll->active_mask)
 233                 goto out;
 234
 235         DRM_DEBUG_KMS("disabling %s\n", pll->info->name);
 236         pll->info->funcs->disable(dev_priv, pll);
 237         pll->on = false;
 238
 239 out:
 240         mutex_unlock(&dev_priv->dpll_lock);
 241 }
 242
 243 static struct intel_shared_dpll *
 244 intel_find_shared_dpll(struct intel_crtc *crtc,
 245                        struct intel_crtc_state *crtc_state,
 246                        enum intel_dpll_id range_min,
 247                        enum intel_dpll_id range_max)
 248 {
 249         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 250         struct intel_shared_dpll *pll, *unused_pll = NULL;
 251         struct intel_shared_dpll_state *shared_dpll;
 252         enum intel_dpll_id i;
 253
 254         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
 255
 256         for (i = range_min; i <= range_max; i++) {
 257                 pll = &dev_priv->shared_dplls[i];
 258
 259                 /* Only want to check enabled timings first */
 260                 if (shared_dpll[i].crtc_mask == 0) {
 261                         if (!unused_pll)
 262                                 unused_pll = pll;
 263                         continue;
 264                 }
 265
 266                 if (memcmp(&crtc_state->dpll_hw_state,
 267                            &shared_dpll[i].hw_state,
 268                            sizeof(crtc_state->dpll_hw_state)) == 0) {
 269                         DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",
 270                                       crtc->base.base.id, crtc->base.name,
 271                                       pll->info->name,
 272                                       shared_dpll[i].crtc_mask,
 273                                       pll->active_mask);
 274                         return pll;
 275                 }
 276         }
 277
 278         /* Ok no matching timings, maybe there's a free one? */
 279         if (unused_pll) {
 280                 DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n",
 281                               crtc->base.base.id, crtc->base.name,
 282                               unused_pll->info->name);
 283                 return unused_pll;
 284         }
 285
 286         return NULL;
 287 }
 288
 289 static void
 290 intel_reference_shared_dpll(struct intel_shared_dpll *pll,
 291                             struct intel_crtc_state *crtc_state)
 292 {
 293         struct intel_shared_dpll_state *shared_dpll;
 294         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 295         const enum intel_dpll_id id = pll->info->id;
 296
 297         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
 298
 299         if (shared_dpll[id].crtc_mask == 0)
 300                 shared_dpll[id].hw_state =
 301                         crtc_state->dpll_hw_state;
 302
 303         crtc_state->shared_dpll = pll;
 304         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name,
 305                          pipe_name(crtc->pipe));
 306
 307         shared_dpll[id].crtc_mask |= 1 << crtc->pipe;
 308 }
 309
 310 /**
 311  * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
 312  * @state: atomic state
 313  *
 314  * This is the dpll version of drm_atomic_helper_swap_state() since the
 315  * helper does not handle driver-specific global state.
 316  *
 317  * For consistency with atomic helpers this function does a complete swap,
 318  * i.e. it also puts the current state into @state, even though there is no
 319  * need for that at this moment.
 320  */
 321 void intel_shared_dpll_swap_state(struct drm_atomic_state *state)
 322 {
 323         struct drm_i915_private *dev_priv = to_i915(state->dev);
 324         struct intel_shared_dpll_state *shared_dpll;
 325         struct intel_shared_dpll *pll;
 326         enum intel_dpll_id i;
 327
 328         if (!to_intel_atomic_state(state)->dpll_set)
 329                 return;
 330
 331         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
 332         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 333                 struct intel_shared_dpll_state tmp;
 334
 335                 pll = &dev_priv->shared_dplls[i];
 336
 337                 tmp = pll->state;
 338                 pll->state = shared_dpll[i];
 339                 shared_dpll[i] = tmp;
 340         }
 341 }
 342
 343 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
 344                                       struct intel_shared_dpll *pll,
 345                                       struct intel_dpll_hw_state *hw_state)
 346 {
 347         const enum intel_dpll_id id = pll->info->id;
 348         intel_wakeref_t wakeref;
 349         u32 val;
 350
 351         wakeref = intel_display_power_get_if_enabled(dev_priv,
 352                                                      POWER_DOMAIN_PLLS);
 353         if (!wakeref)
 354                 return false;
 355
 356         val = I915_READ(PCH_DPLL(id));
 357         hw_state->dpll = val;
 358         hw_state->fp0 = I915_READ(PCH_FP0(id));
 359         hw_state->fp1 = I915_READ(PCH_FP1(id));
 360
 361         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
 362
 363         return val & DPLL_VCO_ENABLE;
 364 }
 365
 366 static void ibx_pch_dpll_prepare(struct drm_i915_private *dev_priv,
 367                                  struct intel_shared_dpll *pll)
 368 {
 369         const enum intel_dpll_id id = pll->info->id;
 370
 371         I915_WRITE(PCH_FP0(id), pll->state.hw_state.fp0);
 372         I915_WRITE(PCH_FP1(id), pll->state.hw_state.fp1);
 373 }
 374
 375 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 376 {
 377         u32 val;
 378         bool enabled;
 379
 380         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
 381
 382         val = I915_READ(PCH_DREF_CONTROL);
 383         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 384                             DREF_SUPERSPREAD_SOURCE_MASK));
 385         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
 386 }
 387
 388 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
 389                                 struct intel_shared_dpll *pll)
 390 {
 391         const enum intel_dpll_id id = pll->info->id;
 392
 393         /* PCH refclock must be enabled first */
 394         ibx_assert_pch_refclk_enabled(dev_priv);
 395
 396         I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
 397
 398         /* Wait for the clocks to stabilize. */
 399         POSTING_READ(PCH_DPLL(id));
 400         udelay(150);
 401
 402         /* The pixel multiplier can only be updated once the
 403          * DPLL is enabled and the clocks are stable.
 404          *
 405          * So write it again.
 406          */
 407         I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
 408         POSTING_READ(PCH_DPLL(id));
 409         udelay(200);
 410 }
 411
 412 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
 413                                  struct intel_shared_dpll *pll)
 414 {
 415         const enum intel_dpll_id id = pll->info->id;
 416
 417         I915_WRITE(PCH_DPLL(id), 0);
 418         POSTING_READ(PCH_DPLL(id));
 419         udelay(200);
 420 }
 421
 422 static struct intel_shared_dpll *
 423 ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
 424              struct intel_encoder *encoder)
 425 {
 426         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 427         struct intel_shared_dpll *pll;
 428         enum intel_dpll_id i;
 429
 430         if (HAS_PCH_IBX(dev_priv)) {
 431                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
 432                 i = (enum intel_dpll_id) crtc->pipe;
 433                 pll = &dev_priv->shared_dplls[i];
 434
 435                 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
 436                               crtc->base.base.id, crtc->base.name,
 437                               pll->info->name);
 438         } else {
 439                 pll = intel_find_shared_dpll(crtc, crtc_state,
 440                                              DPLL_ID_PCH_PLL_A,
 441                                              DPLL_ID_PCH_PLL_B);
 442         }
 443
 444         if (!pll)
 445                 return NULL;
 446
 447         /* reference the pll */
 448         intel_reference_shared_dpll(pll, crtc_state);
 449
 450         return pll;
 451 }
 452
 453 static void ibx_dump_hw_state(struct drm_i915_private *dev_priv,
 454                               struct intel_dpll_hw_state *hw_state)
 455 {
 456         DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
 457                       "fp0: 0x%x, fp1: 0x%x\n",
 458                       hw_state->dpll,
 459                       hw_state->dpll_md,
 460                       hw_state->fp0,
 461                       hw_state->fp1);
 462 }
 463
 464 static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
 465         .prepare = ibx_pch_dpll_prepare,
 466         .enable = ibx_pch_dpll_enable,
 467         .disable = ibx_pch_dpll_disable,
 468         .get_hw_state = ibx_pch_dpll_get_hw_state,
 469 };
 470
 471 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
 472                                struct intel_shared_dpll *pll)
 473 {
 474         const enum intel_dpll_id id = pll->info->id;
 475
 476         I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll);
 477         POSTING_READ(WRPLL_CTL(id));
 478         udelay(20);
 479 }
 480
 481 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
 482                                 struct intel_shared_dpll *pll)
 483 {
 484         I915_WRITE(SPLL_CTL, pll->state.hw_state.spll);
 485         POSTING_READ(SPLL_CTL);
 486         udelay(20);
 487 }
 488
 489 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
 490                                   struct intel_shared_dpll *pll)
 491 {
 492         const enum intel_dpll_id id = pll->info->id;
 493         u32 val;
 494
 495         val = I915_READ(WRPLL_CTL(id));
 496         I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
 497         POSTING_READ(WRPLL_CTL(id));
 498 }
 499
 500 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
 501                                  struct intel_shared_dpll *pll)
 502 {
 503         u32 val;
 504
 505         val = I915_READ(SPLL_CTL);
 506         I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
 507         POSTING_READ(SPLL_CTL);
 508 }
 509
 510 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
 511                                        struct intel_shared_dpll *pll,
 512                                        struct intel_dpll_hw_state *hw_state)
 513 {
 514         const enum intel_dpll_id id = pll->info->id;
 515         intel_wakeref_t wakeref;
 516         u32 val;
 517
 518         wakeref = intel_display_power_get_if_enabled(dev_priv,
 519                                                      POWER_DOMAIN_PLLS);
 520         if (!wakeref)
 521                 return false;
 522
 523         val = I915_READ(WRPLL_CTL(id));
 524         hw_state->wrpll = val;
 525
 526         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
 527
 528         return val & WRPLL_PLL_ENABLE;
 529 }
 530
 531 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
 532                                       struct intel_shared_dpll *pll,
 533                                       struct intel_dpll_hw_state *hw_state)
 534 {
 535         intel_wakeref_t wakeref;
 536         u32 val;
 537
 538         wakeref = intel_display_power_get_if_enabled(dev_priv,
 539                                                      POWER_DOMAIN_PLLS);
 540         if (!wakeref)
 541                 return false;
 542
 543         val = I915_READ(SPLL_CTL);
 544         hw_state->spll = val;
 545
 546         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
 547
 548         return val & SPLL_PLL_ENABLE;
 549 }
 550
 551 #define LC_FREQ 2700
 552 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
 553
 554 #define P_MIN 2
 555 #define P_MAX 64
 556 #define P_INC 2
 557
 558 /* Constraints for PLL good behavior */
 559 #define REF_MIN 48
 560 #define REF_MAX 400
 561 #define VCO_MIN 2400
 562 #define VCO_MAX 4800
 563
 564 struct hsw_wrpll_rnp {
 565         unsigned p, n2, r2;
 566 };
 567
 568 static unsigned hsw_wrpll_get_budget_for_freq(int clock)
 569 {
 570         unsigned budget;
 571
 572         switch (clock) {
 573         case 25175000:
 574         case 25200000:
 575         case 27000000:
 576         case 27027000:
 577         case 37762500:
 578         case 37800000:
 579         case 40500000:
 580         case 40541000:
 581         case 54000000:
 582         case 54054000:
 583         case 59341000:
 584         case 59400000:
 585         case 72000000:
 586         case 74176000:
 587         case 74250000:
 588         case 81000000:
 589         case 81081000:
 590         case 89012000:
 591         case 89100000:
 592         case 108000000:
 593         case 108108000:
 594         case 111264000:
 595         case 111375000:
 596         case 148352000:
 597         case 148500000:
 598         case 162000000:
 599         case 162162000:
 600         case 222525000:
 601         case 222750000:
 602         case 296703000:
 603         case 297000000:
 604                 budget = 0;
 605                 break;
 606         case 233500000:
 607         case 245250000:
 608         case 247750000:
 609         case 253250000:
 610         case 298000000:
 611                 budget = 1500;
 612                 break;
 613         case 169128000:
 614         case 169500000:
 615         case 179500000:
 616         case 202000000:
 617                 budget = 2000;
 618                 break;
 619         case 256250000:
 620         case 262500000:
 621         case 270000000:
 622         case 272500000:
 623         case 273750000:
 624         case 280750000:
 625         case 281250000:
 626         case 286000000:
 627         case 291750000:
 628                 budget = 4000;
 629                 break;
 630         case 267250000:
 631         case 268500000:
 632                 budget = 5000;
 633                 break;
 634         default:
 635                 budget = 1000;
 636                 break;
 637         }
 638
 639         return budget;
 640 }
 641
 642 static void hsw_wrpll_update_rnp(u64 freq2k, unsigned int budget,
 643                                  unsigned int r2, unsigned int n2,
 644                                  unsigned int p,
 645                                  struct hsw_wrpll_rnp *best)
 646 {
 647         u64 a, b, c, d, diff, diff_best;
 648
 649         /* No best (r,n,p) yet */
 650         if (best->p == 0) {
 651                 best->p = p;
 652                 best->n2 = n2;
 653                 best->r2 = r2;
 654                 return;
 655         }
 656
 657         /*
 658          * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
 659          * freq2k.
 660          *
 661          * delta = 1e6 *
 662          *         abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
 663          *         freq2k;
 664          *
 665          * and we would like delta <= budget.
 666          *
 667          * If the discrepancy is above the PPM-based budget, always prefer to
 668          * improve upon the previous solution.  However, if you're within the
 669          * budget, try to maximize Ref * VCO, that is N / (P * R^2).
 670          */
 671         a = freq2k * budget * p * r2;
 672         b = freq2k * budget * best->p * best->r2;
 673         diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
 674         diff_best = abs_diff(freq2k * best->p * best->r2,
 675                              LC_FREQ_2K * best->n2);
 676         c = 1000000 * diff;
 677         d = 1000000 * diff_best;
 678
 679         if (a < c && b < d) {
 680                 /* If both are above the budget, pick the closer */
 681                 if (best->p * best->r2 * diff < p * r2 * diff_best) {
 682                         best->p = p;
 683                         best->n2 = n2;
 684                         best->r2 = r2;
 685                 }
 686         } else if (a >= c && b < d) {
 687                 /* If A is below the threshold but B is above it?  Update. */
 688                 best->p = p;
 689                 best->n2 = n2;
 690                 best->r2 = r2;
 691         } else if (a >= c && b >= d) {
 692                 /* Both are below the limit, so pick the higher n2/(r2*r2) */
 693                 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
 694                         best->p = p;
 695                         best->n2 = n2;
 696                         best->r2 = r2;
 697                 }
 698         }
 699         /* Otherwise a < c && b >= d, do nothing */
 700 }
 701
 702 static void
 703 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 704                         unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
 705 {
 706         u64 freq2k;
 707         unsigned p, n2, r2;
 708         struct hsw_wrpll_rnp best = { 0, 0, 0 };
 709         unsigned budget;
 710
 711         freq2k = clock / 100;
 712
 713         budget = hsw_wrpll_get_budget_for_freq(clock);
 714
 715         /* Special case handling for 540 pixel clock: bypass WR PLL entirely
 716          * and directly pass the LC PLL to it. */
 717         if (freq2k == 5400000) {
 718                 *n2_out = 2;
 719                 *p_out = 1;
 720                 *r2_out = 2;
 721                 return;
 722         }
 723
 724         /*
 725          * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
 726          * the WR PLL.
 727          *
 728          * We want R so that REF_MIN <= Ref <= REF_MAX.
 729          * Injecting R2 = 2 * R gives:
 730          *   REF_MAX * r2 > LC_FREQ * 2 and
 731          *   REF_MIN * r2 < LC_FREQ * 2
 732          *
 733          * Which means the desired boundaries for r2 are:
 734          *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
 735          *
 736          */
 737         for (r2 = LC_FREQ * 2 / REF_MAX + 1;
 738              r2 <= LC_FREQ * 2 / REF_MIN;
 739              r2++) {
 740
 741                 /*
 742                  * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
 743                  *
 744                  * Once again we want VCO_MIN <= VCO <= VCO_MAX.
 745                  * Injecting R2 = 2 * R and N2 = 2 * N, we get:
 746                  *   VCO_MAX * r2 > n2 * LC_FREQ and
 747                  *   VCO_MIN * r2 < n2 * LC_FREQ)
 748                  *
 749                  * Which means the desired boundaries for n2 are:
 750                  * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
 751                  */
 752                 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
 753                      n2 <= VCO_MAX * r2 / LC_FREQ;
 754                      n2++) {
 755
 756                         for (p = P_MIN; p <= P_MAX; p += P_INC)
 757                                 hsw_wrpll_update_rnp(freq2k, budget,
 758                                                      r2, n2, p, &best);
 759                 }
 760         }
 761
 762         *n2_out = best.n2;
 763         *p_out = best.p;
 764         *r2_out = best.r2;
 765 }
 766
 767 static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(int clock,
 768                                                        struct intel_crtc *crtc,
 769                                                        struct intel_crtc_state *crtc_state)
 770 {
 771         struct intel_shared_dpll *pll;
 772         u32 val;
 773         unsigned int p, n2, r2;
 774
 775         hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 776
 777         val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
 778               WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 779               WRPLL_DIVIDER_POST(p);
 780
 781         crtc_state->dpll_hw_state.wrpll = val;
 782
 783         pll = intel_find_shared_dpll(crtc, crtc_state,
 784                                      DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
 785
 786         if (!pll)
 787                 return NULL;
 788
 789         return pll;
 790 }
 791
 792 static struct intel_shared_dpll *
 793 hsw_ddi_dp_get_dpll(struct intel_encoder *encoder, int clock)
 794 {
 795         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 796         struct intel_shared_dpll *pll;
 797         enum intel_dpll_id pll_id;
 798
 799         switch (clock / 2) {
 800         case 81000:
 801                 pll_id = DPLL_ID_LCPLL_810;
 802                 break;
 803         case 135000:
 804                 pll_id = DPLL_ID_LCPLL_1350;
 805                 break;
 806         case 270000:
 807                 pll_id = DPLL_ID_LCPLL_2700;
 808                 break;
 809         default:
 810                 DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock);
 811                 return NULL;
 812         }
 813
 814         pll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
 815
 816         if (!pll)
 817                 return NULL;
 818
 819         return pll;
 820 }
 821
 822 static struct intel_shared_dpll *
 823 hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
 824              struct intel_encoder *encoder)
 825 {
 826         struct intel_shared_dpll *pll;
 827         int clock = crtc_state->port_clock;
 828
 829         memset(&crtc_state->dpll_hw_state, 0,
 830                sizeof(crtc_state->dpll_hw_state));
 831
 832         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 833                 pll = hsw_ddi_hdmi_get_dpll(clock, crtc, crtc_state);
 834         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
 835                 pll = hsw_ddi_dp_get_dpll(encoder, clock);
 836         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 837                 if (WARN_ON(crtc_state->port_clock / 2 != 135000))
 838                         return NULL;
 839
 840                 crtc_state->dpll_hw_state.spll =
 841                         SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
 842
 843                 pll = intel_find_shared_dpll(crtc, crtc_state,
 844                                              DPLL_ID_SPLL, DPLL_ID_SPLL);
 845         } else {
 846                 return NULL;
 847         }
 848
 849         if (!pll)
 850                 return NULL;
 851
 852         intel_reference_shared_dpll(pll, crtc_state);
 853
 854         return pll;
 855 }
 856
 857 static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
 858                               struct intel_dpll_hw_state *hw_state)
 859 {
 860         DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
 861                       hw_state->wrpll, hw_state->spll);
 862 }
 863
 864 static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
 865         .enable = hsw_ddi_wrpll_enable,
 866         .disable = hsw_ddi_wrpll_disable,
 867         .get_hw_state = hsw_ddi_wrpll_get_hw_state,
 868 };
 869
 870 static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
 871         .enable = hsw_ddi_spll_enable,
 872         .disable = hsw_ddi_spll_disable,
 873         .get_hw_state = hsw_ddi_spll_get_hw_state,
 874 };
 875
 876 static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
 877                                  struct intel_shared_dpll *pll)
 878 {
 879 }
 880
 881 static void hsw_ddi_lcpll_disable(struct drm_i915_private *dev_priv,
 882                                   struct intel_shared_dpll *pll)
 883 {
 884 }
 885
 886 static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv,
 887                                        struct intel_shared_dpll *pll,
 888                                        struct intel_dpll_hw_state *hw_state)
 889 {
 890         return true;
 891 }
 892
 893 static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
 894         .enable = hsw_ddi_lcpll_enable,
 895         .disable = hsw_ddi_lcpll_disable,
 896         .get_hw_state = hsw_ddi_lcpll_get_hw_state,
 897 };
 898
 899 struct skl_dpll_regs {
 900         i915_reg_t ctl, cfgcr1, cfgcr2;
 901 };
 902
 903 /* this array is indexed by the *shared* pll id */
 904 static const struct skl_dpll_regs skl_dpll_regs[4] = {
 905         {
 906                 /* DPLL 0 */
 907                 .ctl = LCPLL1_CTL,
 908                 /* DPLL 0 doesn't support HDMI mode */
 909         },
 910         {
 911                 /* DPLL 1 */
 912                 .ctl = LCPLL2_CTL,
 913                 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
 914                 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
 915         },
 916         {
 917                 /* DPLL 2 */
 918                 .ctl = WRPLL_CTL(0),
 919                 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
 920                 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
 921         },
 922         {
 923                 /* DPLL 3 */
 924                 .ctl = WRPLL_CTL(1),
 925                 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
 926                 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
 927         },
 928 };
 929
 930 static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
 931                                     struct intel_shared_dpll *pll)
 932 {
 933         const enum intel_dpll_id id = pll->info->id;
 934         u32 val;
 935
 936         val = I915_READ(DPLL_CTRL1);
 937
 938         val &= ~(DPLL_CTRL1_HDMI_MODE(id) |
 939                  DPLL_CTRL1_SSC(id) |
 940                  DPLL_CTRL1_LINK_RATE_MASK(id));
 941         val |= pll->state.hw_state.ctrl1 << (id * 6);
 942
 943         I915_WRITE(DPLL_CTRL1, val);
 944         POSTING_READ(DPLL_CTRL1);
 945 }
 946
 947 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
 948                                struct intel_shared_dpll *pll)
 949 {
 950         const struct skl_dpll_regs *regs = skl_dpll_regs;
 951         const enum intel_dpll_id id = pll->info->id;
 952
 953         skl_ddi_pll_write_ctrl1(dev_priv, pll);
 954
 955         I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1);
 956         I915_WRITE(regs[id].cfgcr2, pll->state.hw_state.cfgcr2);
 957         POSTING_READ(regs[id].cfgcr1);
 958         POSTING_READ(regs[id].cfgcr2);
 959
 960         /* the enable bit is always bit 31 */
 961         I915_WRITE(regs[id].ctl,
 962                    I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE);
 963
 964         if (intel_wait_for_register(dev_priv,
 965                                     DPLL_STATUS,
 966                                     DPLL_LOCK(id),
 967                                     DPLL_LOCK(id),
 968                                     5))
 969                 DRM_ERROR("DPLL %d not locked\n", id);
 970 }
 971
 972 static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv,
 973                                  struct intel_shared_dpll *pll)
 974 {
 975         skl_ddi_pll_write_ctrl1(dev_priv, pll);
 976 }
 977
 978 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
 979                                 struct intel_shared_dpll *pll)
 980 {
 981         const struct skl_dpll_regs *regs = skl_dpll_regs;
 982         const enum intel_dpll_id id = pll->info->id;
 983
 984         /* the enable bit is always bit 31 */
 985         I915_WRITE(regs[id].ctl,
 986                    I915_READ(regs[id].ctl) & ~LCPLL_PLL_ENABLE);
 987         POSTING_READ(regs[id].ctl);
 988 }
 989
 990 static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv,
 991                                   struct intel_shared_dpll *pll)
 992 {
 993 }
 994
 995 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 996                                      struct intel_shared_dpll *pll,
 997                                      struct intel_dpll_hw_state *hw_state)
 998 {
 999         u32 val;
1000         const struct skl_dpll_regs *regs = skl_dpll_regs;
1001         const enum intel_dpll_id id = pll->info->id;
1002         intel_wakeref_t wakeref;
1003         bool ret;
1004
1005         wakeref = intel_display_power_get_if_enabled(dev_priv,
1006                                                      POWER_DOMAIN_PLLS);
1007         if (!wakeref)
1008                 return false;
1009
1010         ret = false;
1011
1012         val = I915_READ(regs[id].ctl);
1013         if (!(val & LCPLL_PLL_ENABLE))
1014                 goto out;
1015
1016         val = I915_READ(DPLL_CTRL1);
1017         hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1018
1019         /* avoid reading back stale values if HDMI mode is not enabled */
1020         if (val & DPLL_CTRL1_HDMI_MODE(id)) {
1021                 hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1);
1022                 hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2);
1023         }
1024         ret = true;
1025
1026 out:
1027         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
1028
1029         return ret;
1030 }
1031
1032 static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
1033                                        struct intel_shared_dpll *pll,
1034                                        struct intel_dpll_hw_state *hw_state)
1035 {
1036         const struct skl_dpll_regs *regs = skl_dpll_regs;
1037         const enum intel_dpll_id id = pll->info->id;
1038         intel_wakeref_t wakeref;
1039         u32 val;
1040         bool ret;
1041
1042         wakeref = intel_display_power_get_if_enabled(dev_priv,
1043                                                      POWER_DOMAIN_PLLS);
1044         if (!wakeref)
1045                 return false;
1046
1047         ret = false;
1048
1049         /* DPLL0 is always enabled since it drives CDCLK */
1050         val = I915_READ(regs[id].ctl);
1051         if (WARN_ON(!(val & LCPLL_PLL_ENABLE)))
1052                 goto out;
1053
1054         val = I915_READ(DPLL_CTRL1);
1055         hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1056
1057         ret = true;
1058
1059 out:
1060         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
1061
1062         return ret;
1063 }
1064
1065 struct skl_wrpll_context {
1066         u64 min_deviation;              /* current minimal deviation */
1067         u64 central_freq;               /* chosen central freq */
1068         u64 dco_freq;                   /* chosen dco freq */
1069         unsigned int p;                 /* chosen divider */
1070 };
1071
1072 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1073 {
1074         memset(ctx, 0, sizeof(*ctx));
1075
1076         ctx->min_deviation = U64_MAX;
1077 }
1078
1079 /* DCO freq must be within +1%/-6%  of the DCO central freq */
1080 #define SKL_DCO_MAX_PDEVIATION  100
1081 #define SKL_DCO_MAX_NDEVIATION  600
1082
1083 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1084                                   u64 central_freq,
1085                                   u64 dco_freq,
1086                                   unsigned int divider)
1087 {
1088         u64 deviation;
1089
1090         deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1091                               central_freq);
1092
1093         /* positive deviation */
1094         if (dco_freq >= central_freq) {
1095                 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1096                     deviation < ctx->min_deviation) {
1097                         ctx->min_deviation = deviation;
1098                         ctx->central_freq = central_freq;
1099                         ctx->dco_freq = dco_freq;
1100                         ctx->p = divider;
1101                 }
1102         /* negative deviation */
1103         } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1104                    deviation < ctx->min_deviation) {
1105                 ctx->min_deviation = deviation;
1106                 ctx->central_freq = central_freq;
1107                 ctx->dco_freq = dco_freq;
1108                 ctx->p = divider;
1109         }
1110 }
1111
1112 static void skl_wrpll_get_multipliers(unsigned int p,
1113                                       unsigned int *p0 /* out */,
1114                                       unsigned int *p1 /* out */,
1115                                       unsigned int *p2 /* out */)
1116 {
1117         /* even dividers */
1118         if (p % 2 == 0) {
1119                 unsigned int half = p / 2;
1120
1121                 if (half == 1 || half == 2 || half == 3 || half == 5) {
1122                         *p0 = 2;
1123                         *p1 = 1;
1124                         *p2 = half;
1125                 } else if (half % 2 == 0) {
1126                         *p0 = 2;
1127                         *p1 = half / 2;
1128                         *p2 = 2;
1129                 } else if (half % 3 == 0) {
1130                         *p0 = 3;
1131                         *p1 = half / 3;
1132                         *p2 = 2;
1133                 } else if (half % 7 == 0) {
1134                         *p0 = 7;
1135                         *p1 = half / 7;
1136                         *p2 = 2;
1137                 }
1138         } else if (p == 3 || p == 9) {  /* 3, 5, 7, 9, 15, 21, 35 */
1139                 *p0 = 3;
1140                 *p1 = 1;
1141                 *p2 = p / 3;
1142         } else if (p == 5 || p == 7) {
1143                 *p0 = p;
1144                 *p1 = 1;
1145                 *p2 = 1;
1146         } else if (p == 15) {
1147                 *p0 = 3;
1148                 *p1 = 1;
1149                 *p2 = 5;
1150         } else if (p == 21) {
1151                 *p0 = 7;
1152                 *p1 = 1;
1153                 *p2 = 3;
1154         } else if (p == 35) {
1155                 *p0 = 7;
1156                 *p1 = 1;
1157                 *p2 = 5;
1158         }
1159 }
1160
1161 struct skl_wrpll_params {
1162         u32 dco_fraction;
1163         u32 dco_integer;
1164         u32 qdiv_ratio;
1165         u32 qdiv_mode;
1166         u32 kdiv;
1167         u32 pdiv;
1168         u32 central_freq;
1169 };
1170
1171 static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1172                                       u64 afe_clock,
1173                                       u64 central_freq,
1174                                       u32 p0, u32 p1, u32 p2)
1175 {
1176         u64 dco_freq;
1177
1178         switch (central_freq) {
1179         case 9600000000ULL:
1180                 params->central_freq = 0;
1181                 break;
1182         case 9000000000ULL:
1183                 params->central_freq = 1;
1184                 break;
1185         case 8400000000ULL:
1186                 params->central_freq = 3;
1187         }
1188
1189         switch (p0) {
1190         case 1:
1191                 params->pdiv = 0;
1192                 break;
1193         case 2:
1194                 params->pdiv = 1;
1195                 break;
1196         case 3:
1197                 params->pdiv = 2;
1198                 break;
1199         case 7:
1200                 params->pdiv = 4;
1201                 break;
1202         default:
1203                 WARN(1, "Incorrect PDiv\n");
1204         }
1205
1206         switch (p2) {
1207         case 5:
1208                 params->kdiv = 0;
1209                 break;
1210         case 2:
1211                 params->kdiv = 1;
1212                 break;
1213         case 3:
1214                 params->kdiv = 2;
1215                 break;
1216         case 1:
1217                 params->kdiv = 3;
1218                 break;
1219         default:
1220                 WARN(1, "Incorrect KDiv\n");
1221         }
1222
1223         params->qdiv_ratio = p1;
1224         params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1225
1226         dco_freq = p0 * p1 * p2 * afe_clock;
1227
1228         /*
1229          * Intermediate values are in Hz.
1230          * Divide by MHz to match bsepc
1231          */
1232         params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
1233         params->dco_fraction =
1234                 div_u64((div_u64(dco_freq, 24) -
1235                          params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1236 }
1237
1238 static bool
1239 skl_ddi_calculate_wrpll(int clock /* in Hz */,
1240                         struct skl_wrpll_params *wrpll_params)
1241 {
1242         u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1243         u64 dco_central_freq[3] = { 8400000000ULL,
1244                                     9000000000ULL,
1245                                     9600000000ULL };
1246         static const int even_dividers[] = {  4,  6,  8, 10, 12, 14, 16, 18, 20,
1247                                              24, 28, 30, 32, 36, 40, 42, 44,
1248                                              48, 52, 54, 56, 60, 64, 66, 68,
1249                                              70, 72, 76, 78, 80, 84, 88, 90,
1250                                              92, 96, 98 };
1251         static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1252         static const struct {
1253                 const int *list;
1254                 int n_dividers;
1255         } dividers[] = {
1256                 { even_dividers, ARRAY_SIZE(even_dividers) },
1257                 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1258         };
1259         struct skl_wrpll_context ctx;
1260         unsigned int dco, d, i;
1261         unsigned int p0, p1, p2;
1262
1263         skl_wrpll_context_init(&ctx);
1264
1265         for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1266                 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1267                         for (i = 0; i < dividers[d].n_dividers; i++) {
1268                                 unsigned int p = dividers[d].list[i];
1269                                 u64 dco_freq = p * afe_clock;
1270
1271                                 skl_wrpll_try_divider(&ctx,
1272                                                       dco_central_freq[dco],
1273                                                       dco_freq,
1274                                                       p);
1275                                 /*
1276                                  * Skip the remaining dividers if we're sure to
1277                                  * have found the definitive divider, we can't
1278                                  * improve a 0 deviation.
1279                                  */
1280                                 if (ctx.min_deviation == 0)
1281                                         goto skip_remaining_dividers;
1282                         }
1283                 }
1284
1285 skip_remaining_dividers:
1286                 /*
1287                  * If a solution is found with an even divider, prefer
1288                  * this one.
1289                  */
1290                 if (d == 0 && ctx.p)
1291                         break;
1292         }
1293
1294         if (!ctx.p) {
1295                 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
1296                 return false;
1297         }
1298
1299         /*
1300          * gcc incorrectly analyses that these can be used without being
1301          * initialized. To be fair, it's hard to guess.
1302          */
1303         p0 = p1 = p2 = 0;
1304         skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1305         skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1306                                   p0, p1, p2);
1307
1308         return true;
1309 }
1310
1311 static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
1312                                       struct intel_crtc_state *crtc_state,
1313                                       int clock)
1314 {
1315         u32 ctrl1, cfgcr1, cfgcr2;
1316         struct skl_wrpll_params wrpll_params = { 0, };
1317
1318         /*
1319          * See comment in intel_dpll_hw_state to understand why we always use 0
1320          * as the DPLL id in this function.
1321          */
1322         ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1323
1324         ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1325
1326         if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1327                 return false;
1328
1329         cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1330                 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1331                 wrpll_params.dco_integer;
1332
1333         cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1334                 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1335                 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1336                 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1337                 wrpll_params.central_freq;
1338
1339         memset(&crtc_state->dpll_hw_state, 0,
1340                sizeof(crtc_state->dpll_hw_state));
1341
1342         crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1343         crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1344         crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1345         return true;
1346 }
1347
1348 static bool
1349 skl_ddi_dp_set_dpll_hw_state(int clock,
1350                              struct intel_dpll_hw_state *dpll_hw_state)
1351 {
1352         u32 ctrl1;
1353
1354         /*
1355          * See comment in intel_dpll_hw_state to understand why we always use 0
1356          * as the DPLL id in this function.
1357          */
1358         ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1359         switch (clock / 2) {
1360         case 81000:
1361                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1362                 break;
1363         case 135000:
1364                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1365                 break;
1366         case 270000:
1367                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1368                 break;
1369                 /* eDP 1.4 rates */
1370         case 162000:
1371                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
1372                 break;
1373         case 108000:
1374                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
1375                 break;
1376         case 216000:
1377                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
1378                 break;
1379         }
1380
1381         dpll_hw_state->ctrl1 = ctrl1;
1382         return true;
1383 }
1384
1385 static struct intel_shared_dpll *
1386 skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1387              struct intel_encoder *encoder)
1388 {
1389         struct intel_shared_dpll *pll;
1390         int clock = crtc_state->port_clock;
1391         bool bret;
1392         struct intel_dpll_hw_state dpll_hw_state;
1393
1394         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
1395
1396         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1397                 bret = skl_ddi_hdmi_pll_dividers(crtc, crtc_state, clock);
1398                 if (!bret) {
1399                         DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
1400                         return NULL;
1401                 }
1402         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1403                 bret = skl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state);
1404                 if (!bret) {
1405                         DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
1406                         return NULL;
1407                 }
1408                 crtc_state->dpll_hw_state = dpll_hw_state;
1409         } else {
1410                 return NULL;
1411         }
1412
1413         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1414                 pll = intel_find_shared_dpll(crtc, crtc_state,
1415                                              DPLL_ID_SKL_DPLL0,
1416                                              DPLL_ID_SKL_DPLL0);
1417         else
1418                 pll = intel_find_shared_dpll(crtc, crtc_state,
1419                                              DPLL_ID_SKL_DPLL1,
1420                                              DPLL_ID_SKL_DPLL3);
1421         if (!pll)
1422                 return NULL;
1423
1424         intel_reference_shared_dpll(pll, crtc_state);
1425
1426         return pll;
1427 }
1428
1429 static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
1430                               struct intel_dpll_hw_state *hw_state)
1431 {
1432         DRM_DEBUG_KMS("dpll_hw_state: "
1433                       "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
1434                       hw_state->ctrl1,
1435                       hw_state->cfgcr1,
1436                       hw_state->cfgcr2);
1437 }
1438
1439 static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
1440         .enable = skl_ddi_pll_enable,
1441         .disable = skl_ddi_pll_disable,
1442         .get_hw_state = skl_ddi_pll_get_hw_state,
1443 };
1444
1445 static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
1446         .enable = skl_ddi_dpll0_enable,
1447         .disable = skl_ddi_dpll0_disable,
1448         .get_hw_state = skl_ddi_dpll0_get_hw_state,
1449 };
1450
1451 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
1452                                 struct intel_shared_dpll *pll)
1453 {
1454         u32 temp;
1455         enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1456         enum dpio_phy phy;
1457         enum dpio_channel ch;
1458
1459         bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
1460
1461         /* Non-SSC reference */
1462         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1463         temp |= PORT_PLL_REF_SEL;
1464         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1465
1466         if (IS_GEMINILAKE(dev_priv)) {
1467                 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1468                 temp |= PORT_PLL_POWER_ENABLE;
1469                 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1470
1471                 if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
1472                                  PORT_PLL_POWER_STATE), 200))
1473                         DRM_ERROR("Power state not set for PLL:%d\n", port);
1474         }
1475
1476         /* Disable 10 bit clock */
1477         temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
1478         temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1479         I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
1480
1481         /* Write P1 & P2 */
1482         temp = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
1483         temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
1484         temp |= pll->state.hw_state.ebb0;
1485         I915_WRITE(BXT_PORT_PLL_EBB_0(phy, ch), temp);
1486
1487         /* Write M2 integer */
1488         temp = I915_READ(BXT_PORT_PLL(phy, ch, 0));
1489         temp &= ~PORT_PLL_M2_MASK;
1490         temp |= pll->state.hw_state.pll0;
1491         I915_WRITE(BXT_PORT_PLL(phy, ch, 0), temp);
1492
1493         /* Write N */
1494         temp = I915_READ(BXT_PORT_PLL(phy, ch, 1));
1495         temp &= ~PORT_PLL_N_MASK;
1496         temp |= pll->state.hw_state.pll1;
1497         I915_WRITE(BXT_PORT_PLL(phy, ch, 1), temp);
1498
1499         /* Write M2 fraction */
1500         temp = I915_READ(BXT_PORT_PLL(phy, ch, 2));
1501         temp &= ~PORT_PLL_M2_FRAC_MASK;
1502         temp |= pll->state.hw_state.pll2;
1503         I915_WRITE(BXT_PORT_PLL(phy, ch, 2), temp);
1504
1505         /* Write M2 fraction enable */
1506         temp = I915_READ(BXT_PORT_PLL(phy, ch, 3));
1507         temp &= ~PORT_PLL_M2_FRAC_ENABLE;
1508         temp |= pll->state.hw_state.pll3;
1509         I915_WRITE(BXT_PORT_PLL(phy, ch, 3), temp);
1510
1511         /* Write coeff */
1512         temp = I915_READ(BXT_PORT_PLL(phy, ch, 6));
1513         temp &= ~PORT_PLL_PROP_COEFF_MASK;
1514         temp &= ~PORT_PLL_INT_COEFF_MASK;
1515         temp &= ~PORT_PLL_GAIN_CTL_MASK;
1516         temp |= pll->state.hw_state.pll6;
1517         I915_WRITE(BXT_PORT_PLL(phy, ch, 6), temp);
1518
1519         /* Write calibration val */
1520         temp = I915_READ(BXT_PORT_PLL(phy, ch, 8));
1521         temp &= ~PORT_PLL_TARGET_CNT_MASK;
1522         temp |= pll->state.hw_state.pll8;
1523         I915_WRITE(BXT_PORT_PLL(phy, ch, 8), temp);
1524
1525         temp = I915_READ(BXT_PORT_PLL(phy, ch, 9));
1526         temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
1527         temp |= pll->state.hw_state.pll9;
1528         I915_WRITE(BXT_PORT_PLL(phy, ch, 9), temp);
1529
1530         temp = I915_READ(BXT_PORT_PLL(phy, ch, 10));
1531         temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
1532         temp &= ~PORT_PLL_DCO_AMP_MASK;
1533         temp |= pll->state.hw_state.pll10;
1534         I915_WRITE(BXT_PORT_PLL(phy, ch, 10), temp);
1535
1536         /* Recalibrate with new settings */
1537         temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
1538         temp |= PORT_PLL_RECALIBRATE;
1539         I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
1540         temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1541         temp |= pll->state.hw_state.ebb4;
1542         I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp);
1543
1544         /* Enable PLL */
1545         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1546         temp |= PORT_PLL_ENABLE;
1547         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1548         POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1549
1550         if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
1551                         200))
1552                 DRM_ERROR("PLL %d not locked\n", port);
1553
1554         if (IS_GEMINILAKE(dev_priv)) {
1555                 temp = I915_READ(BXT_PORT_TX_DW5_LN0(phy, ch));
1556                 temp |= DCC_DELAY_RANGE_2;
1557                 I915_WRITE(BXT_PORT_TX_DW5_GRP(phy, ch), temp);
1558         }
1559
1560         /*
1561          * While we write to the group register to program all lanes at once we
1562          * can read only lane registers and we pick lanes 0/1 for that.
1563          */
1564         temp = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
1565         temp &= ~LANE_STAGGER_MASK;
1566         temp &= ~LANESTAGGER_STRAP_OVRD;
1567         temp |= pll->state.hw_state.pcsdw12;
1568         I915_WRITE(BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
1569 }
1570
1571 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
1572                                         struct intel_shared_dpll *pll)
1573 {
1574         enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1575         u32 temp;
1576
1577         temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1578         temp &= ~PORT_PLL_ENABLE;
1579         I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1580         POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1581
1582         if (IS_GEMINILAKE(dev_priv)) {
1583                 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1584                 temp &= ~PORT_PLL_POWER_ENABLE;
1585                 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1586
1587                 if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) &
1588                                 PORT_PLL_POWER_STATE), 200))
1589                         DRM_ERROR("Power state not reset for PLL:%d\n", port);
1590         }
1591 }
1592
1593 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1594                                         struct intel_shared_dpll *pll,
1595                                         struct intel_dpll_hw_state *hw_state)
1596 {
1597         enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1598         intel_wakeref_t wakeref;
1599         enum dpio_phy phy;
1600         enum dpio_channel ch;
1601         u32 val;
1602         bool ret;
1603
1604         bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
1605
1606         wakeref = intel_display_power_get_if_enabled(dev_priv,
1607                                                      POWER_DOMAIN_PLLS);
1608         if (!wakeref)
1609                 return false;
1610
1611         ret = false;
1612
1613         val = I915_READ(BXT_PORT_PLL_ENABLE(port));
1614         if (!(val & PORT_PLL_ENABLE))
1615                 goto out;
1616
1617         hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch));
1618         hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
1619
1620         hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
1621         hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
1622
1623         hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0));
1624         hw_state->pll0 &= PORT_PLL_M2_MASK;
1625
1626         hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1));
1627         hw_state->pll1 &= PORT_PLL_N_MASK;
1628
1629         hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2));
1630         hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
1631
1632         hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3));
1633         hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
1634
1635         hw_state->pll6 = I915_READ(BXT_PORT_PLL(phy, ch, 6));
1636         hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
1637                           PORT_PLL_INT_COEFF_MASK |
1638                           PORT_PLL_GAIN_CTL_MASK;
1639
1640         hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8));
1641         hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
1642
1643         hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9));
1644         hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
1645
1646         hw_state->pll10 = I915_READ(BXT_PORT_PLL(phy, ch, 10));
1647         hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
1648                            PORT_PLL_DCO_AMP_MASK;
1649
1650         /*
1651          * While we write to the group register to program all lanes at once we
1652          * can read only lane registers. We configure all lanes the same way, so
1653          * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
1654          */
1655         hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch));
1656         if (I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
1657                 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
1658                                  hw_state->pcsdw12,
1659                                  I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)));
1660         hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
1661
1662         ret = true;
1663
1664 out:
1665         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
1666
1667         return ret;
1668 }
1669
1670 /* bxt clock parameters */
1671 struct bxt_clk_div {
1672         int clock;
1673         u32 p1;
1674         u32 p2;
1675         u32 m2_int;
1676         u32 m2_frac;
1677         bool m2_frac_en;
1678         u32 n;
1679
1680         int vco;
1681 };
1682
1683 /* pre-calculated values for DP linkrates */
1684 static const struct bxt_clk_div bxt_dp_clk_val[] = {
1685         {162000, 4, 2, 32, 1677722, 1, 1},
1686         {270000, 4, 1, 27,       0, 0, 1},
1687         {540000, 2, 1, 27,       0, 0, 1},
1688         {216000, 3, 2, 32, 1677722, 1, 1},
1689         {243000, 4, 1, 24, 1258291, 1, 1},
1690         {324000, 4, 1, 32, 1677722, 1, 1},
1691         {432000, 3, 1, 32, 1677722, 1, 1}
1692 };
1693
1694 static bool
1695 bxt_ddi_hdmi_pll_dividers(struct intel_crtc *intel_crtc,
1696                           struct intel_crtc_state *crtc_state, int clock,
1697                           struct bxt_clk_div *clk_div)
1698 {
1699         struct dpll best_clock;
1700
1701         /* Calculate HDMI div */
1702         /*
1703          * FIXME: tie the following calculation into
1704          * i9xx_crtc_compute_clock
1705          */
1706         if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1707                 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1708                                  clock, pipe_name(intel_crtc->pipe));
1709                 return false;
1710         }
1711
1712         clk_div->p1 = best_clock.p1;
1713         clk_div->p2 = best_clock.p2;
1714         WARN_ON(best_clock.m1 != 2);
1715         clk_div->n = best_clock.n;
1716         clk_div->m2_int = best_clock.m2 >> 22;
1717         clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
1718         clk_div->m2_frac_en = clk_div->m2_frac != 0;
1719
1720         clk_div->vco = best_clock.vco;
1721
1722         return true;
1723 }
1724
1725 static void bxt_ddi_dp_pll_dividers(int clock, struct bxt_clk_div *clk_div)
1726 {
1727         int i;
1728
1729         *clk_div = bxt_dp_clk_val[0];
1730         for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1731                 if (bxt_dp_clk_val[i].clock == clock) {
1732                         *clk_div = bxt_dp_clk_val[i];
1733                         break;
1734                 }
1735         }
1736
1737         clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
1738 }
1739
1740 static bool bxt_ddi_set_dpll_hw_state(int clock,
1741                           struct bxt_clk_div *clk_div,
1742                           struct intel_dpll_hw_state *dpll_hw_state)
1743 {
1744         int vco = clk_div->vco;
1745         u32 prop_coef, int_coef, gain_ctl, targ_cnt;
1746         u32 lanestagger;
1747
1748         if (vco >= 6200000 && vco <= 6700000) {
1749                 prop_coef = 4;
1750                 int_coef = 9;
1751                 gain_ctl = 3;
1752                 targ_cnt = 8;
1753         } else if ((vco > 5400000 && vco < 6200000) ||
1754                         (vco >= 4800000 && vco < 5400000)) {
1755                 prop_coef = 5;
1756                 int_coef = 11;
1757                 gain_ctl = 3;
1758                 targ_cnt = 9;
1759         } else if (vco == 5400000) {
1760                 prop_coef = 3;
1761                 int_coef = 8;
1762                 gain_ctl = 1;
1763                 targ_cnt = 9;
1764         } else {
1765                 DRM_ERROR("Invalid VCO\n");
1766                 return false;
1767         }
1768
1769         if (clock > 270000)
1770                 lanestagger = 0x18;
1771         else if (clock > 135000)
1772                 lanestagger = 0x0d;
1773         else if (clock > 67000)
1774                 lanestagger = 0x07;
1775         else if (clock > 33000)
1776                 lanestagger = 0x04;
1777         else
1778                 lanestagger = 0x02;
1779
1780         dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
1781         dpll_hw_state->pll0 = clk_div->m2_int;
1782         dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
1783         dpll_hw_state->pll2 = clk_div->m2_frac;
1784
1785         if (clk_div->m2_frac_en)
1786                 dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
1787
1788         dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef);
1789         dpll_hw_state->pll6 |= PORT_PLL_GAIN_CTL(gain_ctl);
1790
1791         dpll_hw_state->pll8 = targ_cnt;
1792
1793         dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1794
1795         dpll_hw_state->pll10 =
1796                 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1797                 | PORT_PLL_DCO_AMP_OVR_EN_H;
1798
1799         dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1800
1801         dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger;
1802
1803         return true;
1804 }
1805
1806 static bool
1807 bxt_ddi_dp_set_dpll_hw_state(int clock,
1808                              struct intel_dpll_hw_state *dpll_hw_state)
1809 {
1810         struct bxt_clk_div clk_div = {0};
1811
1812         bxt_ddi_dp_pll_dividers(clock, &clk_div);
1813
1814         return bxt_ddi_set_dpll_hw_state(clock, &clk_div, dpll_hw_state);
1815 }
1816
1817 static bool
1818 bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc *intel_crtc,
1819                                struct intel_crtc_state *crtc_state, int clock,
1820                                struct intel_dpll_hw_state *dpll_hw_state)
1821 {
1822         struct bxt_clk_div clk_div = { };
1823
1824         bxt_ddi_hdmi_pll_dividers(intel_crtc, crtc_state, clock, &clk_div);
1825
1826         return bxt_ddi_set_dpll_hw_state(clock, &clk_div, dpll_hw_state);
1827 }
1828
1829 static struct intel_shared_dpll *
1830 bxt_get_dpll(struct intel_crtc *crtc,
1831                 struct intel_crtc_state *crtc_state,
1832                 struct intel_encoder *encoder)
1833 {
1834         struct intel_dpll_hw_state dpll_hw_state = { };
1835         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1836         struct intel_shared_dpll *pll;
1837         int i, clock = crtc_state->port_clock;
1838
1839         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
1840             !bxt_ddi_hdmi_set_dpll_hw_state(crtc, crtc_state, clock,
1841                                             &dpll_hw_state))
1842                 return NULL;
1843
1844         if (intel_crtc_has_dp_encoder(crtc_state) &&
1845             !bxt_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state))
1846                 return NULL;
1847
1848         memset(&crtc_state->dpll_hw_state, 0,
1849                sizeof(crtc_state->dpll_hw_state));
1850
1851         crtc_state->dpll_hw_state = dpll_hw_state;
1852
1853         /* 1:1 mapping between ports and PLLs */
1854         i = (enum intel_dpll_id) encoder->port;
1855         pll = intel_get_shared_dpll_by_id(dev_priv, i);
1856
1857         DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
1858                       crtc->base.base.id, crtc->base.name, pll->info->name);
1859
1860         intel_reference_shared_dpll(pll, crtc_state);
1861
1862         return pll;
1863 }
1864
1865 static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,
1866                               struct intel_dpll_hw_state *hw_state)
1867 {
1868         DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
1869                       "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
1870                       "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
1871                       hw_state->ebb0,
1872                       hw_state->ebb4,
1873                       hw_state->pll0,
1874                       hw_state->pll1,
1875                       hw_state->pll2,
1876                       hw_state->pll3,
1877                       hw_state->pll6,
1878                       hw_state->pll8,
1879                       hw_state->pll9,
1880                       hw_state->pll10,
1881                       hw_state->pcsdw12);
1882 }
1883
1884 static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
1885         .enable = bxt_ddi_pll_enable,
1886         .disable = bxt_ddi_pll_disable,
1887         .get_hw_state = bxt_ddi_pll_get_hw_state,
1888 };
1889
1890 static void intel_ddi_pll_init(struct drm_device *dev)
1891 {
1892         struct drm_i915_private *dev_priv = to_i915(dev);
1893
1894         if (INTEL_GEN(dev_priv) < 9) {
1895                 u32 val = I915_READ(LCPLL_CTL);
1896
1897                 /*
1898                  * The LCPLL register should be turned on by the BIOS. For now
1899                  * let's just check its state and print errors in case
1900                  * something is wrong.  Don't even try to turn it on.
1901                  */
1902
1903                 if (val & LCPLL_CD_SOURCE_FCLK)
1904                         DRM_ERROR("CDCLK source is not LCPLL\n");
1905
1906                 if (val & LCPLL_PLL_DISABLE)
1907                         DRM_ERROR("LCPLL is disabled\n");
1908         }
1909 }
1910
1911 struct intel_dpll_mgr {
1912         const struct dpll_info *dpll_info;
1913
1914         struct intel_shared_dpll *(*get_dpll)(struct intel_crtc *crtc,
1915                                               struct intel_crtc_state *crtc_state,
1916                                               struct intel_encoder *encoder);
1917
1918         void (*dump_hw_state)(struct drm_i915_private *dev_priv,
1919                               struct intel_dpll_hw_state *hw_state);
1920 };
1921
1922 static const struct dpll_info pch_plls[] = {
1923         { "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
1924         { "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
1925         { },
1926 };
1927
1928 static const struct intel_dpll_mgr pch_pll_mgr = {
1929         .dpll_info = pch_plls,
1930         .get_dpll = ibx_get_dpll,
1931         .dump_hw_state = ibx_dump_hw_state,
1932 };
1933
1934 static const struct dpll_info hsw_plls[] = {
1935         { "WRPLL 1",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1,     0 },
1936         { "WRPLL 2",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2,     0 },
1937         { "SPLL",       &hsw_ddi_spll_funcs,  DPLL_ID_SPLL,       0 },
1938         { "LCPLL 810",  &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810,  INTEL_DPLL_ALWAYS_ON },
1939         { "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON },
1940         { "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON },
1941         { },
1942 };
1943
1944 static const struct intel_dpll_mgr hsw_pll_mgr = {
1945         .dpll_info = hsw_plls,
1946         .get_dpll = hsw_get_dpll,
1947         .dump_hw_state = hsw_dump_hw_state,
1948 };
1949
1950 static const struct dpll_info skl_plls[] = {
1951         { "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
1952         { "DPLL 1", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL1, 0 },
1953         { "DPLL 2", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL2, 0 },
1954         { "DPLL 3", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL3, 0 },
1955         { },
1956 };
1957
1958 static const struct intel_dpll_mgr skl_pll_mgr = {
1959         .dpll_info = skl_plls,
1960         .get_dpll = skl_get_dpll,
1961         .dump_hw_state = skl_dump_hw_state,
1962 };
1963
1964 static const struct dpll_info bxt_plls[] = {
1965         { "PORT PLL A", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
1966         { "PORT PLL B", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
1967         { "PORT PLL C", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
1968         { },
1969 };
1970
1971 static const struct intel_dpll_mgr bxt_pll_mgr = {
1972         .dpll_info = bxt_plls,
1973         .get_dpll = bxt_get_dpll,
1974         .dump_hw_state = bxt_dump_hw_state,
1975 };
1976
1977 static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
1978                                struct intel_shared_dpll *pll)
1979 {
1980         const enum intel_dpll_id id = pll->info->id;
1981         u32 val;
1982
1983         /* 1. Enable DPLL power in DPLL_ENABLE. */
1984         val = I915_READ(CNL_DPLL_ENABLE(id));
1985         val |= PLL_POWER_ENABLE;
1986         I915_WRITE(CNL_DPLL_ENABLE(id), val);
1987
1988         /* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
1989         if (intel_wait_for_register(dev_priv,
1990                                     CNL_DPLL_ENABLE(id),
1991                                     PLL_POWER_STATE,
1992                                     PLL_POWER_STATE,
1993                                     5))
1994                 DRM_ERROR("PLL %d Power not enabled\n", id);
1995
1996         /*
1997          * 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
1998          * select DP mode, and set DP link rate.
1999          */
2000         val = pll->state.hw_state.cfgcr0;
2001         I915_WRITE(CNL_DPLL_CFGCR0(id), val);
2002
2003         /* 4. Reab back to ensure writes completed */
2004         POSTING_READ(CNL_DPLL_CFGCR0(id));
2005
2006         /* 3. Configure DPLL_CFGCR0 */
2007         /* Avoid touch CFGCR1 if HDMI mode is not enabled */
2008         if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
2009                 val = pll->state.hw_state.cfgcr1;
2010                 I915_WRITE(CNL_DPLL_CFGCR1(id), val);
2011                 /* 4. Reab back to ensure writes completed */
2012                 POSTING_READ(CNL_DPLL_CFGCR1(id));
2013         }
2014
2015         /*
2016          * 5. If the frequency will result in a change to the voltage
2017          * requirement, follow the Display Voltage Frequency Switching
2018          * Sequence Before Frequency Change
2019          *
2020          * Note: DVFS is actually handled via the cdclk code paths,
2021          * hence we do nothing here.
2022          */
2023
2024         /* 6. Enable DPLL in DPLL_ENABLE. */
2025         val = I915_READ(CNL_DPLL_ENABLE(id));
2026         val |= PLL_ENABLE;
2027         I915_WRITE(CNL_DPLL_ENABLE(id), val);
2028
2029         /* 7. Wait for PLL lock status in DPLL_ENABLE. */
2030         if (intel_wait_for_register(dev_priv,
2031                                     CNL_DPLL_ENABLE(id),
2032                                     PLL_LOCK,
2033                                     PLL_LOCK,
2034                                     5))
2035                 DRM_ERROR("PLL %d not locked\n", id);
2036
2037         /*
2038          * 8. If the frequency will result in a change to the voltage
2039          * requirement, follow the Display Voltage Frequency Switching
2040          * Sequence After Frequency Change
2041          *
2042          * Note: DVFS is actually handled via the cdclk code paths,
2043          * hence we do nothing here.
2044          */
2045
2046         /*
2047          * 9. turn on the clock for the DDI and map the DPLL to the DDI
2048          * Done at intel_ddi_clk_select
2049          */
2050 }
2051
2052 static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2053                                 struct intel_shared_dpll *pll)
2054 {
2055         const enum intel_dpll_id id = pll->info->id;
2056         u32 val;
2057
2058         /*
2059          * 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
2060          * Done at intel_ddi_post_disable
2061          */
2062
2063         /*
2064          * 2. If the frequency will result in a change to the voltage
2065          * requirement, follow the Display Voltage Frequency Switching
2066          * Sequence Before Frequency Change
2067          *
2068          * Note: DVFS is actually handled via the cdclk code paths,
2069          * hence we do nothing here.
2070          */
2071
2072         /* 3. Disable DPLL through DPLL_ENABLE. */
2073         val = I915_READ(CNL_DPLL_ENABLE(id));
2074         val &= ~PLL_ENABLE;
2075         I915_WRITE(CNL_DPLL_ENABLE(id), val);
2076
2077         /* 4. Wait for PLL not locked status in DPLL_ENABLE. */
2078         if (intel_wait_for_register(dev_priv,
2079                                     CNL_DPLL_ENABLE(id),
2080                                     PLL_LOCK,
2081                                     0,
2082                                     5))
2083                 DRM_ERROR("PLL %d locked\n", id);
2084
2085         /*
2086          * 5. If the frequency will result in a change to the voltage
2087          * requirement, follow the Display Voltage Frequency Switching
2088          * Sequence After Frequency Change
2089          *
2090          * Note: DVFS is actually handled via the cdclk code paths,
2091          * hence we do nothing here.
2092          */
2093
2094         /* 6. Disable DPLL power in DPLL_ENABLE. */
2095         val = I915_READ(CNL_DPLL_ENABLE(id));
2096         val &= ~PLL_POWER_ENABLE;
2097         I915_WRITE(CNL_DPLL_ENABLE(id), val);
2098
2099         /* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
2100         if (intel_wait_for_register(dev_priv,
2101                                     CNL_DPLL_ENABLE(id),
2102                                     PLL_POWER_STATE,
2103                                     0,
2104                                     5))
2105                 DRM_ERROR("PLL %d Power not disabled\n", id);
2106 }
2107
2108 static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2109                                      struct intel_shared_dpll *pll,
2110                                      struct intel_dpll_hw_state *hw_state)
2111 {
2112         const enum intel_dpll_id id = pll->info->id;
2113         intel_wakeref_t wakeref;
2114         u32 val;
2115         bool ret;
2116
2117         wakeref = intel_display_power_get_if_enabled(dev_priv,
2118                                                      POWER_DOMAIN_PLLS);
2119         if (!wakeref)
2120                 return false;
2121
2122         ret = false;
2123
2124         val = I915_READ(CNL_DPLL_ENABLE(id));
2125         if (!(val & PLL_ENABLE))
2126                 goto out;
2127
2128         val = I915_READ(CNL_DPLL_CFGCR0(id));
2129         hw_state->cfgcr0 = val;
2130
2131         /* avoid reading back stale values if HDMI mode is not enabled */
2132         if (val & DPLL_CFGCR0_HDMI_MODE) {
2133                 hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(id));
2134         }
2135         ret = true;
2136
2137 out:
2138         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
2139
2140         return ret;
2141 }
2142
2143 static void cnl_wrpll_get_multipliers(int bestdiv, int *pdiv,
2144                                       int *qdiv, int *kdiv)
2145 {
2146         /* even dividers */
2147         if (bestdiv % 2 == 0) {
2148                 if (bestdiv == 2) {
2149                         *pdiv = 2;
2150                         *qdiv = 1;
2151                         *kdiv = 1;
2152                 } else if (bestdiv % 4 == 0) {
2153                         *pdiv = 2;
2154                         *qdiv = bestdiv / 4;
2155                         *kdiv = 2;
2156                 } else if (bestdiv % 6 == 0) {
2157                         *pdiv = 3;
2158                         *qdiv = bestdiv / 6;
2159                         *kdiv = 2;
2160                 } else if (bestdiv % 5 == 0) {
2161                         *pdiv = 5;
2162                         *qdiv = bestdiv / 10;
2163                         *kdiv = 2;
2164                 } else if (bestdiv % 14 == 0) {
2165                         *pdiv = 7;
2166                         *qdiv = bestdiv / 14;
2167                         *kdiv = 2;
2168                 }
2169         } else {
2170                 if (bestdiv == 3 || bestdiv == 5 || bestdiv == 7) {
2171                         *pdiv = bestdiv;
2172                         *qdiv = 1;
2173                         *kdiv = 1;
2174                 } else { /* 9, 15, 21 */
2175                         *pdiv = bestdiv / 3;
2176                         *qdiv = 1;
2177                         *kdiv = 3;
2178                 }
2179         }
2180 }
2181
2182 static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
2183                                       u32 dco_freq, u32 ref_freq,
2184                                       int pdiv, int qdiv, int kdiv)
2185 {
2186         u32 dco;
2187
2188         switch (kdiv) {
2189         case 1:
2190                 params->kdiv = 1;
2191                 break;
2192         case 2:
2193                 params->kdiv = 2;
2194                 break;
2195         case 3:
2196                 params->kdiv = 4;
2197                 break;
2198         default:
2199                 WARN(1, "Incorrect KDiv\n");
2200         }
2201
2202         switch (pdiv) {
2203         case 2:
2204                 params->pdiv = 1;
2205                 break;
2206         case 3:
2207                 params->pdiv = 2;
2208                 break;
2209         case 5:
2210                 params->pdiv = 4;
2211                 break;
2212         case 7:
2213                 params->pdiv = 8;
2214                 break;
2215         default:
2216                 WARN(1, "Incorrect PDiv\n");
2217         }
2218
2219         WARN_ON(kdiv != 2 && qdiv != 1);
2220
2221         params->qdiv_ratio = qdiv;
2222         params->qdiv_mode = (qdiv == 1) ? 0 : 1;
2223
2224         dco = div_u64((u64)dco_freq << 15, ref_freq);
2225
2226         params->dco_integer = dco >> 15;
2227         params->dco_fraction = dco & 0x7fff;
2228 }
2229
2230 int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv)
2231 {
2232         int ref_clock = dev_priv->cdclk.hw.ref;
2233
2234         /*
2235          * For ICL+, the spec states: if reference frequency is 38.4,
2236          * use 19.2 because the DPLL automatically divides that by 2.
2237          */
2238         if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400)
2239                 ref_clock = 19200;
2240
2241         return ref_clock;
2242 }
2243
2244 static bool
2245 cnl_ddi_calculate_wrpll(int clock,
2246                         struct drm_i915_private *dev_priv,
2247                         struct skl_wrpll_params *wrpll_params)
2248 {
2249         u32 afe_clock = clock * 5;
2250         u32 ref_clock;
2251         u32 dco_min = 7998000;
2252         u32 dco_max = 10000000;
2253         u32 dco_mid = (dco_min + dco_max) / 2;
2254         static const int dividers[] = {  2,  4,  6,  8, 10, 12,  14,  16,
2255                                          18, 20, 24, 28, 30, 32,  36,  40,
2256                                          42, 44, 48, 50, 52, 54,  56,  60,
2257                                          64, 66, 68, 70, 72, 76,  78,  80,
2258                                          84, 88, 90, 92, 96, 98, 100, 102,
2259                                           3,  5,  7,  9, 15, 21 };
2260         u32 dco, best_dco = 0, dco_centrality = 0;
2261         u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
2262         int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
2263
2264         for (d = 0; d < ARRAY_SIZE(dividers); d++) {
2265                 dco = afe_clock * dividers[d];
2266
2267                 if ((dco <= dco_max) && (dco >= dco_min)) {
2268                         dco_centrality = abs(dco - dco_mid);
2269
2270                         if (dco_centrality < best_dco_centrality) {
2271                                 best_dco_centrality = dco_centrality;
2272                                 best_div = dividers[d];
2273                                 best_dco = dco;
2274                         }
2275                 }
2276         }
2277
2278         if (best_div == 0)
2279                 return false;
2280
2281         cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
2282
2283         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
2284
2285         cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock, pdiv, qdiv,
2286                                   kdiv);
2287
2288         return true;
2289 }
2290
2291 static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
2292                                       struct intel_crtc_state *crtc_state,
2293                                       int clock)
2294 {
2295         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2296         u32 cfgcr0, cfgcr1;
2297         struct skl_wrpll_params wrpll_params = { 0, };
2298
2299         cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
2300
2301         if (!cnl_ddi_calculate_wrpll(clock, dev_priv, &wrpll_params))
2302                 return false;
2303
2304         cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
2305                 wrpll_params.dco_integer;
2306
2307         cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(wrpll_params.qdiv_ratio) |
2308                 DPLL_CFGCR1_QDIV_MODE(wrpll_params.qdiv_mode) |
2309                 DPLL_CFGCR1_KDIV(wrpll_params.kdiv) |
2310                 DPLL_CFGCR1_PDIV(wrpll_params.pdiv) |
2311                 DPLL_CFGCR1_CENTRAL_FREQ;
2312
2313         memset(&crtc_state->dpll_hw_state, 0,
2314                sizeof(crtc_state->dpll_hw_state));
2315
2316         crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
2317         crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
2318         return true;
2319 }
2320
2321 static bool
2322 cnl_ddi_dp_set_dpll_hw_state(int clock,
2323                              struct intel_dpll_hw_state *dpll_hw_state)
2324 {
2325         u32 cfgcr0;
2326
2327         cfgcr0 = DPLL_CFGCR0_SSC_ENABLE;
2328
2329         switch (clock / 2) {
2330         case 81000:
2331                 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810;
2332                 break;
2333         case 135000:
2334                 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1350;
2335                 break;
2336         case 270000:
2337                 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2700;
2338                 break;
2339                 /* eDP 1.4 rates */
2340         case 162000:
2341                 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1620;
2342                 break;
2343         case 108000:
2344                 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1080;
2345                 break;
2346         case 216000:
2347                 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_2160;
2348                 break;
2349         case 324000:
2350                 /* Some SKUs may require elevated I/O voltage to support this */
2351                 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_3240;
2352                 break;
2353         case 405000:
2354                 /* Some SKUs may require elevated I/O voltage to support this */
2355                 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_4050;
2356                 break;
2357         }
2358
2359         dpll_hw_state->cfgcr0 = cfgcr0;
2360         return true;
2361 }
2362
2363 static struct intel_shared_dpll *
2364 cnl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
2365              struct intel_encoder *encoder)
2366 {
2367         struct intel_shared_dpll *pll;
2368         int clock = crtc_state->port_clock;
2369         bool bret;
2370         struct intel_dpll_hw_state dpll_hw_state;
2371
2372         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
2373
2374         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2375                 bret = cnl_ddi_hdmi_pll_dividers(crtc, crtc_state, clock);
2376                 if (!bret) {
2377                         DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
2378                         return NULL;
2379                 }
2380         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
2381                 bret = cnl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state);
2382                 if (!bret) {
2383                         DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
2384                         return NULL;
2385                 }
2386                 crtc_state->dpll_hw_state = dpll_hw_state;
2387         } else {
2388                 DRM_DEBUG_KMS("Skip DPLL setup for output_types 0x%x\n",
2389                               crtc_state->output_types);
2390                 return NULL;
2391         }
2392
2393         pll = intel_find_shared_dpll(crtc, crtc_state,
2394                                      DPLL_ID_SKL_DPLL0,
2395                                      DPLL_ID_SKL_DPLL2);
2396         if (!pll) {
2397                 DRM_DEBUG_KMS("No PLL selected\n");
2398                 return NULL;
2399         }
2400
2401         intel_reference_shared_dpll(pll, crtc_state);
2402
2403         return pll;
2404 }
2405
2406 static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
2407                               struct intel_dpll_hw_state *hw_state)
2408 {
2409         DRM_DEBUG_KMS("dpll_hw_state: "
2410                       "cfgcr0: 0x%x, cfgcr1: 0x%x\n",
2411                       hw_state->cfgcr0,
2412                       hw_state->cfgcr1);
2413 }
2414
2415 static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
2416         .enable = cnl_ddi_pll_enable,
2417         .disable = cnl_ddi_pll_disable,
2418         .get_hw_state = cnl_ddi_pll_get_hw_state,
2419 };
2420
2421 static const struct dpll_info cnl_plls[] = {
2422         { "DPLL 0", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
2423         { "DPLL 1", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
2424         { "DPLL 2", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
2425         { },
2426 };
2427
2428 static const struct intel_dpll_mgr cnl_pll_mgr = {
2429         .dpll_info = cnl_plls,
2430         .get_dpll = cnl_get_dpll,
2431         .dump_hw_state = cnl_dump_hw_state,
2432 };
2433
2434 /*
2435  * These values alrea already adjusted: they're the bits we write to the
2436  * registers, not the logical values.
2437  */
2438 static const struct skl_wrpll_params icl_dp_combo_pll_24MHz_values[] = {
2439         { .dco_integer = 0x151, .dco_fraction = 0x4000,         /* [0]: 5.4 */
2440           .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2441         { .dco_integer = 0x151, .dco_fraction = 0x4000,         /* [1]: 2.7 */
2442           .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2443         { .dco_integer = 0x151, .dco_fraction = 0x4000,         /* [2]: 1.62 */
2444           .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2445         { .dco_integer = 0x151, .dco_fraction = 0x4000,         /* [3]: 3.24 */
2446           .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2447         { .dco_integer = 0x168, .dco_fraction = 0x0000,         /* [4]: 2.16 */
2448           .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2},
2449         { .dco_integer = 0x168, .dco_fraction = 0x0000,         /* [5]: 4.32 */
2450           .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2451         { .dco_integer = 0x195, .dco_fraction = 0x0000,         /* [6]: 6.48 */
2452           .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2453         { .dco_integer = 0x151, .dco_fraction = 0x4000,         /* [7]: 8.1 */
2454           .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2455 };
2456
2457 /* Also used for 38.4 MHz values. */
2458 static const struct skl_wrpll_params icl_dp_combo_pll_19_2MHz_values[] = {
2459         { .dco_integer = 0x1A5, .dco_fraction = 0x7000,         /* [0]: 5.4 */
2460           .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2461         { .dco_integer = 0x1A5, .dco_fraction = 0x7000,         /* [1]: 2.7 */
2462           .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2463         { .dco_integer = 0x1A5, .dco_fraction = 0x7000,         /* [2]: 1.62 */
2464           .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2465         { .dco_integer = 0x1A5, .dco_fraction = 0x7000,         /* [3]: 3.24 */
2466           .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2467         { .dco_integer = 0x1C2, .dco_fraction = 0x0000,         /* [4]: 2.16 */
2468           .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2},
2469         { .dco_integer = 0x1C2, .dco_fraction = 0x0000,         /* [5]: 4.32 */
2470           .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
2471         { .dco_integer = 0x1FA, .dco_fraction = 0x2000,         /* [6]: 6.48 */
2472           .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2473         { .dco_integer = 0x1A5, .dco_fraction = 0x7000,         /* [7]: 8.1 */
2474           .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
2475 };
2476
2477 static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
2478         .dco_integer = 0x151, .dco_fraction = 0x4000,
2479         .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2480 };
2481
2482 static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
2483         .dco_integer = 0x1A5, .dco_fraction = 0x7000,
2484         .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2485 };
2486
2487 static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int clock,
2488                                   struct skl_wrpll_params *pll_params)
2489 {
2490         const struct skl_wrpll_params *params;
2491
2492         params = dev_priv->cdclk.hw.ref == 24000 ?
2493                         icl_dp_combo_pll_24MHz_values :
2494                         icl_dp_combo_pll_19_2MHz_values;
2495
2496         switch (clock) {
2497         case 540000:
2498                 *pll_params = params[0];
2499                 break;
2500         case 270000:
2501                 *pll_params = params[1];
2502                 break;
2503         case 162000:
2504                 *pll_params = params[2];
2505                 break;
2506         case 324000:
2507                 *pll_params = params[3];
2508                 break;
2509         case 216000:
2510                 *pll_params = params[4];
2511                 break;
2512         case 432000:
2513                 *pll_params = params[5];
2514                 break;
2515         case 648000:
2516                 *pll_params = params[6];
2517                 break;
2518         case 810000:
2519                 *pll_params = params[7];
2520                 break;
2521         default:
2522                 MISSING_CASE(clock);
2523                 return false;
2524         }
2525
2526         return true;
2527 }
2528
2529 static bool icl_calc_tbt_pll(struct drm_i915_private *dev_priv, int clock,
2530                              struct skl_wrpll_params *pll_params)
2531 {
2532         *pll_params = dev_priv->cdclk.hw.ref == 24000 ?
2533                         icl_tbt_pll_24MHz_values : icl_tbt_pll_19_2MHz_values;
2534         return true;
2535 }
2536
2537 static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
2538                                 struct intel_encoder *encoder, int clock,
2539                                 struct intel_dpll_hw_state *pll_state)
2540 {
2541         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2542         u32 cfgcr0, cfgcr1;
2543         struct skl_wrpll_params pll_params = { 0 };
2544         bool ret;
2545
2546         if (intel_port_is_tc(dev_priv, encoder->port))
2547                 ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);
2548         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
2549                  intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
2550                 ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params);
2551         else
2552                 ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params);
2553
2554         if (!ret)
2555                 return false;
2556
2557         cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
2558                  pll_params.dco_integer;
2559
2560         cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
2561                  DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
2562                  DPLL_CFGCR1_KDIV(pll_params.kdiv) |
2563                  DPLL_CFGCR1_PDIV(pll_params.pdiv) |
2564                  DPLL_CFGCR1_CENTRAL_FREQ_8400;
2565
2566         pll_state->cfgcr0 = cfgcr0;
2567         pll_state->cfgcr1 = cfgcr1;
2568         return true;
2569 }
2570
2571 int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
2572                                u32 pll_id)
2573 {
2574         u32 cfgcr0, cfgcr1;
2575         u32 pdiv, kdiv, qdiv_mode, qdiv_ratio, dco_integer, dco_fraction;
2576         const struct skl_wrpll_params *params;
2577         int index, n_entries, link_clock;
2578
2579         /* Read back values from DPLL CFGCR registers */
2580         cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
2581         cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
2582
2583         dco_integer = cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK;
2584         dco_fraction = (cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
2585                 DPLL_CFGCR0_DCO_FRACTION_SHIFT;
2586         pdiv = (cfgcr1 & DPLL_CFGCR1_PDIV_MASK) >> DPLL_CFGCR1_PDIV_SHIFT;
2587         kdiv = (cfgcr1 & DPLL_CFGCR1_KDIV_MASK) >> DPLL_CFGCR1_KDIV_SHIFT;
2588         qdiv_mode = (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) >>
2589                 DPLL_CFGCR1_QDIV_MODE_SHIFT;
2590         qdiv_ratio = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
2591                 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
2592
2593         params = dev_priv->cdclk.hw.ref == 24000 ?
2594                 icl_dp_combo_pll_24MHz_values :
2595                 icl_dp_combo_pll_19_2MHz_values;
2596         n_entries = ARRAY_SIZE(icl_dp_combo_pll_24MHz_values);
2597
2598         for (index = 0; index < n_entries; index++) {
2599                 if (dco_integer == params[index].dco_integer &&
2600                     dco_fraction == params[index].dco_fraction &&
2601                     pdiv == params[index].pdiv &&
2602                     kdiv == params[index].kdiv &&
2603                     qdiv_mode == params[index].qdiv_mode &&
2604                     qdiv_ratio == params[index].qdiv_ratio)
2605                         break;
2606         }
2607
2608         /* Map PLL Index to Link Clock */
2609         switch (index) {
2610         default:
2611                 MISSING_CASE(index);
2612                 /* fall through */
2613         case 0:
2614                 link_clock = 540000;
2615                 break;
2616         case 1:
2617                 link_clock = 270000;
2618                 break;
2619         case 2:
2620                 link_clock = 162000;
2621                 break;
2622         case 3:
2623                 link_clock = 324000;
2624                 break;
2625         case 4:
2626                 link_clock = 216000;
2627                 break;
2628         case 5:
2629                 link_clock = 432000;
2630                 break;
2631         case 6:
2632                 link_clock = 648000;
2633                 break;
2634         case 7:
2635                 link_clock = 810000;
2636                 break;
2637         }
2638
2639         return link_clock;
2640 }
2641
2642 static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
2643 {
2644         return id - DPLL_ID_ICL_MGPLL1;
2645 }
2646
2647 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
2648 {
2649         return tc_port + DPLL_ID_ICL_MGPLL1;
2650 }
2651
2652 bool intel_dpll_is_combophy(enum intel_dpll_id id)
2653 {
2654         return id == DPLL_ID_ICL_DPLL0 || id == DPLL_ID_ICL_DPLL1;
2655 }
2656
2657 static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
2658                                      u32 *target_dco_khz,
2659                                      struct intel_dpll_hw_state *state)
2660 {
2661         u32 dco_min_freq, dco_max_freq;
2662         int div1_vals[] = {7, 5, 3, 2};
2663         unsigned int i;
2664         int div2;
2665
2666         dco_min_freq = is_dp ? 8100000 : use_ssc ? 8000000 : 7992000;
2667         dco_max_freq = is_dp ? 8100000 : 10000000;
2668
2669         for (i = 0; i < ARRAY_SIZE(div1_vals); i++) {
2670                 int div1 = div1_vals[i];
2671
2672                 for (div2 = 10; div2 > 0; div2--) {
2673                         int dco = div1 * div2 * clock_khz * 5;
2674                         int a_divratio, tlinedrv, inputsel;
2675                         u32 hsdiv;
2676
2677                         if (dco < dco_min_freq || dco > dco_max_freq)
2678                                 continue;
2679
2680                         if (div2 >= 2) {
2681                                 a_divratio = is_dp ? 10 : 5;
2682                                 tlinedrv = 2;
2683                         } else {
2684                                 a_divratio = 5;
2685                                 tlinedrv = 0;
2686                         }
2687                         inputsel = is_dp ? 0 : 1;
2688
2689                         switch (div1) {
2690                         default:
2691                                 MISSING_CASE(div1);
2692                                 /* fall through */
2693                         case 2:
2694                                 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2;
2695                                 break;
2696                         case 3:
2697                                 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3;
2698                                 break;
2699                         case 5:
2700                                 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5;
2701                                 break;
2702                         case 7:
2703                                 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7;
2704                                 break;
2705                         }
2706
2707                         *target_dco_khz = dco;
2708
2709                         state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1);
2710
2711                         state->mg_clktop2_coreclkctl1 =
2712                                 MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(a_divratio);
2713
2714                         state->mg_clktop2_hsclkctl =
2715                                 MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |
2716                                 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |
2717                                 hsdiv |
2718                                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);
2719
2720                         return true;
2721                 }
2722         }
2723
2724         return false;
2725 }
2726
2727 /*
2728  * The specification for this function uses real numbers, so the math had to be
2729  * adapted to integer-only calculation, that's why it looks so different.
2730  */
2731 static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
2732                                   struct intel_encoder *encoder, int clock,
2733                                   struct intel_dpll_hw_state *pll_state)
2734 {
2735         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2736         int refclk_khz = dev_priv->cdclk.hw.ref;
2737         u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
2738         u32 iref_ndiv, iref_trim, iref_pulse_w;
2739         u32 prop_coeff, int_coeff;
2740         u32 tdc_targetcnt, feedfwgain;
2741         u64 ssc_stepsize, ssc_steplen, ssc_steplog;
2742         u64 tmp;
2743         bool use_ssc = false;
2744         bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
2745
2746         if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
2747                                       pll_state)) {
2748                 DRM_DEBUG_KMS("Failed to find divisors for clock %d\n", clock);
2749                 return false;
2750         }
2751
2752         m1div = 2;
2753         m2div_int = dco_khz / (refclk_khz * m1div);
2754         if (m2div_int > 255) {
2755                 m1div = 4;
2756                 m2div_int = dco_khz / (refclk_khz * m1div);
2757                 if (m2div_int > 255) {
2758                         DRM_DEBUG_KMS("Failed to find mdiv for clock %d\n",
2759                                       clock);
2760                         return false;
2761                 }
2762         }
2763         m2div_rem = dco_khz % (refclk_khz * m1div);
2764
2765         tmp = (u64)m2div_rem * (1 << 22);
2766         do_div(tmp, refclk_khz * m1div);
2767         m2div_frac = tmp;
2768
2769         switch (refclk_khz) {
2770         case 19200:
2771                 iref_ndiv = 1;
2772                 iref_trim = 28;
2773                 iref_pulse_w = 1;
2774                 break;
2775         case 24000:
2776                 iref_ndiv = 1;
2777                 iref_trim = 25;
2778                 iref_pulse_w = 2;
2779                 break;
2780         case 38400:
2781                 iref_ndiv = 2;
2782                 iref_trim = 28;
2783                 iref_pulse_w = 1;
2784                 break;
2785         default:
2786                 MISSING_CASE(refclk_khz);
2787                 return false;
2788         }
2789
2790         /*
2791          * tdc_res = 0.000003
2792          * tdc_targetcnt = int(2 / (tdc_res * 8 * 50 * 1.1) / refclk_mhz + 0.5)
2793          *
2794          * The multiplication by 1000 is due to refclk MHz to KHz conversion. It
2795          * was supposed to be a division, but we rearranged the operations of
2796          * the formula to avoid early divisions so we don't multiply the
2797          * rounding errors.
2798          *
2799          * 0.000003 * 8 * 50 * 1.1 = 0.00132, also known as 132 / 100000, which
2800          * we also rearrange to work with integers.
2801          *
2802          * The 0.5 transformed to 5 results in a multiplication by 10 and the
2803          * last division by 10.
2804          */
2805         tdc_targetcnt = (2 * 1000 * 100000 * 10 / (132 * refclk_khz) + 5) / 10;
2806
2807         /*
2808          * Here we divide dco_khz by 10 in order to allow the dividend to fit in
2809          * 32 bits. That's not a problem since we round the division down
2810          * anyway.
2811          */
2812         feedfwgain = (use_ssc || m2div_rem > 0) ?
2813                 m1div * 1000000 * 100 / (dco_khz * 3 / 10) : 0;
2814
2815         if (dco_khz >= 9000000) {
2816                 prop_coeff = 5;
2817                 int_coeff = 10;
2818         } else {
2819                 prop_coeff = 4;
2820                 int_coeff = 8;
2821         }
2822
2823         if (use_ssc) {
2824                 tmp = (u64)dco_khz * 47 * 32;
2825                 do_div(tmp, refclk_khz * m1div * 10000);
2826                 ssc_stepsize = tmp;
2827
2828                 tmp = (u64)dco_khz * 1000;
2829                 ssc_steplen = DIV_ROUND_UP_ULL(tmp, 32 * 2 * 32);
2830         } else {
2831                 ssc_stepsize = 0;
2832                 ssc_steplen = 0;
2833         }
2834         ssc_steplog = 4;
2835
2836         pll_state->mg_pll_div0 = (m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
2837                                   MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
2838                                   MG_PLL_DIV0_FBDIV_INT(m2div_int);
2839
2840         pll_state->mg_pll_div1 = MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
2841                                  MG_PLL_DIV1_DITHER_DIV_2 |
2842                                  MG_PLL_DIV1_NDIVRATIO(1) |
2843                                  MG_PLL_DIV1_FBPREDIV(m1div);
2844
2845         pll_state->mg_pll_lf = MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
2846                                MG_PLL_LF_AFCCNTSEL_512 |
2847                                MG_PLL_LF_GAINCTRL(1) |
2848                                MG_PLL_LF_INT_COEFF(int_coeff) |
2849                                MG_PLL_LF_PROP_COEFF(prop_coeff);
2850
2851         pll_state->mg_pll_frac_lock = MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
2852                                       MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
2853                                       MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
2854                                       MG_PLL_FRAC_LOCK_DCODITHEREN |
2855                                       MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
2856         if (use_ssc || m2div_rem > 0)
2857                 pll_state->mg_pll_frac_lock |= MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
2858
2859         pll_state->mg_pll_ssc = (use_ssc ? MG_PLL_SSC_EN : 0) |
2860                                 MG_PLL_SSC_TYPE(2) |
2861                                 MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
2862                                 MG_PLL_SSC_STEPNUM(ssc_steplog) |
2863                                 MG_PLL_SSC_FLLEN |
2864                                 MG_PLL_SSC_STEPSIZE(ssc_stepsize);
2865
2866         pll_state->mg_pll_tdc_coldst_bias = MG_PLL_TDC_COLDST_COLDSTART |
2867                                             MG_PLL_TDC_COLDST_IREFINT_EN |
2868                                             MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
2869                                             MG_PLL_TDC_TDCOVCCORR_EN |
2870                                             MG_PLL_TDC_TDCSEL(3);
2871
2872         pll_state->mg_pll_bias = MG_PLL_BIAS_BIAS_GB_SEL(3) |
2873                                  MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
2874                                  MG_PLL_BIAS_BIAS_BONUS(10) |
2875                                  MG_PLL_BIAS_BIASCAL_EN |
2876                                  MG_PLL_BIAS_CTRIM(12) |
2877                                  MG_PLL_BIAS_VREF_RDAC(4) |
2878                                  MG_PLL_BIAS_IREFTRIM(iref_trim);
2879
2880         if (refclk_khz == 38400) {
2881                 pll_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
2882                 pll_state->mg_pll_bias_mask = 0;
2883         } else {
2884                 pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
2885                 pll_state->mg_pll_bias_mask = -1U;
2886         }
2887
2888         pll_state->mg_pll_tdc_coldst_bias &= pll_state->mg_pll_tdc_coldst_bias_mask;
2889         pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
2890
2891         return true;
2892 }
2893
2894 static struct intel_shared_dpll *
2895 icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
2896              struct intel_encoder *encoder)
2897 {
2898         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2899         struct intel_digital_port *intel_dig_port;
2900         struct intel_shared_dpll *pll;
2901         struct intel_dpll_hw_state pll_state = {};
2902         enum port port = encoder->port;
2903         enum intel_dpll_id min, max;
2904         int clock = crtc_state->port_clock;
2905         bool ret;
2906
2907         if (intel_port_is_combophy(dev_priv, port)) {
2908                 min = DPLL_ID_ICL_DPLL0;
2909                 max = DPLL_ID_ICL_DPLL1;
2910                 ret = icl_calc_dpll_state(crtc_state, encoder, clock,
2911                                           &pll_state);
2912         } else if (intel_port_is_tc(dev_priv, port)) {
2913                 if (encoder->type == INTEL_OUTPUT_DP_MST) {
2914                         struct intel_dp_mst_encoder *mst_encoder;
2915
2916                         mst_encoder = enc_to_mst(&encoder->base);
2917                         intel_dig_port = mst_encoder->primary;
2918                 } else {
2919                         intel_dig_port = enc_to_dig_port(&encoder->base);
2920                 }
2921
2922                 if (intel_dig_port->tc_type == TC_PORT_TBT) {
2923                         min = DPLL_ID_ICL_TBTPLL;
2924                         max = min;
2925                         ret = icl_calc_dpll_state(crtc_state, encoder, clock,
2926                                                   &pll_state);
2927                 } else {
2928                         enum tc_port tc_port;
2929
2930                         tc_port = intel_port_to_tc(dev_priv, port);
2931                         min = icl_tc_port_to_pll_id(tc_port);
2932                         max = min;
2933                         ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,
2934                                                     &pll_state);
2935                 }
2936         } else {
2937                 MISSING_CASE(port);
2938                 return NULL;
2939         }
2940
2941         if (!ret) {
2942                 DRM_DEBUG_KMS("Could not calculate PLL state.\n");
2943                 return NULL;
2944         }
2945
2946         crtc_state->dpll_hw_state = pll_state;
2947
2948         pll = intel_find_shared_dpll(crtc, crtc_state, min, max);
2949         if (!pll) {
2950                 DRM_DEBUG_KMS("No PLL selected\n");
2951                 return NULL;
2952         }
2953
2954         intel_reference_shared_dpll(pll, crtc_state);
2955
2956         return pll;
2957 }
2958
2959 static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
2960 {
2961         if (intel_dpll_is_combophy(id))
2962                 return CNL_DPLL_ENABLE(id);
2963         else if (id == DPLL_ID_ICL_TBTPLL)
2964                 return TBT_PLL_ENABLE;
2965
2966         return MG_PLL_ENABLE(icl_pll_id_to_tc_port(id));
2967 }
2968
2969 static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
2970                                  struct intel_shared_dpll *pll,
2971                                  struct intel_dpll_hw_state *hw_state)
2972 {
2973         const enum intel_dpll_id id = pll->info->id;
2974         intel_wakeref_t wakeref;
2975         bool ret = false;
2976         u32 val;
2977
2978         wakeref = intel_display_power_get_if_enabled(dev_priv,
2979                                                      POWER_DOMAIN_PLLS);
2980         if (!wakeref)
2981                 return false;
2982
2983         val = I915_READ(icl_pll_id_to_enable_reg(id));
2984         if (!(val & PLL_ENABLE))
2985                 goto out;
2986
2987         if (intel_dpll_is_combophy(id) ||
2988             id == DPLL_ID_ICL_TBTPLL) {
2989                 hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
2990                 hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
2991         } else {
2992                 enum tc_port tc_port = icl_pll_id_to_tc_port(id);
2993
2994                 hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(tc_port));
2995                 hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
2996
2997                 hw_state->mg_clktop2_coreclkctl1 =
2998                         I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port));
2999                 hw_state->mg_clktop2_coreclkctl1 &=
3000                         MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3001
3002                 hw_state->mg_clktop2_hsclkctl =
3003                         I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port));
3004                 hw_state->mg_clktop2_hsclkctl &=
3005                         MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3006                         MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3007                         MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3008                         MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
3009
3010                 hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port));
3011                 hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(tc_port));
3012                 hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(tc_port));
3013                 hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(tc_port));
3014                 hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(tc_port));
3015
3016                 hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(tc_port));
3017                 hw_state->mg_pll_tdc_coldst_bias =
3018                         I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
3019
3020                 if (dev_priv->cdclk.hw.ref == 38400) {
3021                         hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
3022                         hw_state->mg_pll_bias_mask = 0;
3023                 } else {
3024                         hw_state->mg_pll_tdc_coldst_bias_mask = -1U;
3025                         hw_state->mg_pll_bias_mask = -1U;
3026                 }
3027
3028                 hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask;
3029                 hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
3030         }
3031
3032         ret = true;
3033 out:
3034         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS, wakeref);
3035         return ret;
3036 }
3037
3038 static void icl_dpll_write(struct drm_i915_private *dev_priv,
3039                            struct intel_shared_dpll *pll)
3040 {
3041         struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3042         const enum intel_dpll_id id = pll->info->id;
3043
3044         I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
3045         I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
3046         POSTING_READ(ICL_DPLL_CFGCR1(id));
3047 }
3048
3049 static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
3050                              struct intel_shared_dpll *pll)
3051 {
3052         struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3053         enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
3054         u32 val;
3055
3056         /*
3057          * Some of the following registers have reserved fields, so program
3058          * these with RMW based on a mask. The mask can be fixed or generated
3059          * during the calc/readout phase if the mask depends on some other HW
3060          * state like refclk, see icl_calc_mg_pll_state().
3061          */
3062         val = I915_READ(MG_REFCLKIN_CTL(tc_port));
3063         val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3064         val |= hw_state->mg_refclkin_ctl;
3065         I915_WRITE(MG_REFCLKIN_CTL(tc_port), val);
3066
3067         val = I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port));
3068         val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3069         val |= hw_state->mg_clktop2_coreclkctl1;
3070         I915_WRITE(MG_CLKTOP2_CORECLKCTL1(tc_port), val);
3071
3072         val = I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port));
3073         val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3074                  MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3075                  MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3076                  MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
3077         val |= hw_state->mg_clktop2_hsclkctl;
3078         I915_WRITE(MG_CLKTOP2_HSCLKCTL(tc_port), val);
3079
3080         I915_WRITE(MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
3081         I915_WRITE(MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
3082         I915_WRITE(MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
3083         I915_WRITE(MG_PLL_FRAC_LOCK(tc_port), hw_state->mg_pll_frac_lock);
3084         I915_WRITE(MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
3085
3086         val = I915_READ(MG_PLL_BIAS(tc_port));
3087         val &= ~hw_state->mg_pll_bias_mask;
3088         val |= hw_state->mg_pll_bias;
3089         I915_WRITE(MG_PLL_BIAS(tc_port), val);
3090
3091         val = I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
3092         val &= ~hw_state->mg_pll_tdc_coldst_bias_mask;
3093         val |= hw_state->mg_pll_tdc_coldst_bias;
3094         I915_WRITE(MG_PLL_TDC_COLDST_BIAS(tc_port), val);
3095
3096         POSTING_READ(MG_PLL_TDC_COLDST_BIAS(tc_port));
3097 }
3098
3099 static void icl_pll_enable(struct drm_i915_private *dev_priv,
3100                            struct intel_shared_dpll *pll)
3101 {
3102         const enum intel_dpll_id id = pll->info->id;
3103         i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
3104         u32 val;
3105
3106         val = I915_READ(enable_reg);
3107         val |= PLL_POWER_ENABLE;
3108         I915_WRITE(enable_reg, val);
3109
3110         /*
3111          * The spec says we need to "wait" but it also says it should be
3112          * immediate.
3113          */
3114         if (intel_wait_for_register(dev_priv, enable_reg, PLL_POWER_STATE,
3115                                     PLL_POWER_STATE, 1))
3116                 DRM_ERROR("PLL %d Power not enabled\n", id);
3117
3118         if (intel_dpll_is_combophy(id) || id == DPLL_ID_ICL_TBTPLL)
3119                 icl_dpll_write(dev_priv, pll);
3120         else
3121                 icl_mg_pll_write(dev_priv, pll);
3122
3123         /*
3124          * DVFS pre sequence would be here, but in our driver the cdclk code
3125          * paths should already be setting the appropriate voltage, hence we do
3126          * nothign here.
3127          */
3128
3129         val = I915_READ(enable_reg);
3130         val |= PLL_ENABLE;
3131         I915_WRITE(enable_reg, val);
3132
3133         if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, PLL_LOCK,
3134                                     1)) /* 600us actually. */
3135                 DRM_ERROR("PLL %d not locked\n", id);
3136
3137         /* DVFS post sequence would be here. See the comment above. */
3138 }
3139
3140 static void icl_pll_disable(struct drm_i915_private *dev_priv,
3141                             struct intel_shared_dpll *pll)
3142 {
3143         const enum intel_dpll_id id = pll->info->id;
3144         i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
3145         u32 val;
3146
3147         /* The first steps are done by intel_ddi_post_disable(). */
3148
3149         /*
3150          * DVFS pre sequence would be here, but in our driver the cdclk code
3151          * paths should already be setting the appropriate voltage, hence we do
3152          * nothign here.
3153          */
3154
3155         val = I915_READ(enable_reg);
3156         val &= ~PLL_ENABLE;
3157         I915_WRITE(enable_reg, val);
3158
3159         /* Timeout is actually 1us. */
3160         if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, 0, 1))
3161                 DRM_ERROR("PLL %d locked\n", id);
3162
3163         /* DVFS post sequence would be here. See the comment above. */
3164
3165         val = I915_READ(enable_reg);
3166         val &= ~PLL_POWER_ENABLE;
3167         I915_WRITE(enable_reg, val);
3168
3169         /*
3170          * The spec says we need to "wait" but it also says it should be
3171          * immediate.
3172          */
3173         if (intel_wait_for_register(dev_priv, enable_reg, PLL_POWER_STATE, 0,
3174                                     1))
3175                 DRM_ERROR("PLL %d Power not disabled\n", id);
3176 }
3177
3178 static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
3179                               struct intel_dpll_hw_state *hw_state)
3180 {
3181         DRM_DEBUG_KMS("dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "
3182                       "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "
3183                       "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
3184                       "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, "
3185                       "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
3186                       "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n",
3187                       hw_state->cfgcr0, hw_state->cfgcr1,
3188                       hw_state->mg_refclkin_ctl,
3189                       hw_state->mg_clktop2_coreclkctl1,
3190                       hw_state->mg_clktop2_hsclkctl,
3191                       hw_state->mg_pll_div0,
3192                       hw_state->mg_pll_div1,
3193                       hw_state->mg_pll_lf,
3194                       hw_state->mg_pll_frac_lock,
3195                       hw_state->mg_pll_ssc,
3196                       hw_state->mg_pll_bias,
3197                       hw_state->mg_pll_tdc_coldst_bias);
3198 }
3199
3200 static const struct intel_shared_dpll_funcs icl_pll_funcs = {
3201         .enable = icl_pll_enable,
3202         .disable = icl_pll_disable,
3203         .get_hw_state = icl_pll_get_hw_state,
3204 };
3205
3206 static const struct dpll_info icl_plls[] = {
3207         { "DPLL 0",   &icl_pll_funcs, DPLL_ID_ICL_DPLL0,  0 },
3208         { "DPLL 1",   &icl_pll_funcs, DPLL_ID_ICL_DPLL1,  0 },
3209         { "TBT PLL",  &icl_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
3210         { "MG PLL 1", &icl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
3211         { "MG PLL 2", &icl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
3212         { "MG PLL 3", &icl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
3213         { "MG PLL 4", &icl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
3214         { },
3215 };
3216
3217 static const struct intel_dpll_mgr icl_pll_mgr = {
3218         .dpll_info = icl_plls,
3219         .get_dpll = icl_get_dpll,
3220         .dump_hw_state = icl_dump_hw_state,
3221 };
3222
3223 /**
3224  * intel_shared_dpll_init - Initialize shared DPLLs
3225  * @dev: drm device
3226  *
3227  * Initialize shared DPLLs for @dev.
3228  */
3229 void intel_shared_dpll_init(struct drm_device *dev)
3230 {
3231         struct drm_i915_private *dev_priv = to_i915(dev);
3232         const struct intel_dpll_mgr *dpll_mgr = NULL;
3233         const struct dpll_info *dpll_info;
3234         int i;
3235
3236         if (IS_ICELAKE(dev_priv))
3237                 dpll_mgr = &icl_pll_mgr;
3238         else if (IS_CANNONLAKE(dev_priv))
3239                 dpll_mgr = &cnl_pll_mgr;
3240         else if (IS_GEN9_BC(dev_priv))
3241                 dpll_mgr = &skl_pll_mgr;
3242         else if (IS_GEN9_LP(dev_priv))
3243                 dpll_mgr = &bxt_pll_mgr;
3244         else if (HAS_DDI(dev_priv))
3245                 dpll_mgr = &hsw_pll_mgr;
3246         else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
3247                 dpll_mgr = &pch_pll_mgr;
3248
3249         if (!dpll_mgr) {
3250                 dev_priv->num_shared_dpll = 0;
3251                 return;
3252         }
3253
3254         dpll_info = dpll_mgr->dpll_info;
3255
3256         for (i = 0; dpll_info[i].name; i++) {
3257                 WARN_ON(i != dpll_info[i].id);
3258                 dev_priv->shared_dplls[i].info = &dpll_info[i];
3259         }
3260
3261         dev_priv->dpll_mgr = dpll_mgr;
3262         dev_priv->num_shared_dpll = i;
3263         mutex_init(&dev_priv->dpll_lock);
3264
3265         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
3266
3267         /* FIXME: Move this to a more suitable place */
3268         if (HAS_DDI(dev_priv))
3269                 intel_ddi_pll_init(dev);
3270 }
3271
3272 /**
3273  * intel_get_shared_dpll - get a shared DPLL for CRTC and encoder combination
3274  * @crtc: CRTC
3275  * @crtc_state: atomic state for @crtc
3276  * @encoder: encoder
3277  *
3278  * Find an appropriate DPLL for the given CRTC and encoder combination. A
3279  * reference from the @crtc to the returned pll is registered in the atomic
3280  * state. That configuration is made effective by calling
3281  * intel_shared_dpll_swap_state(). The reference should be released by calling
3282  * intel_release_shared_dpll().
3283  *
3284  * Returns:
3285  * A shared DPLL to be used by @crtc and @encoder with the given @crtc_state.
3286  */
3287 struct intel_shared_dpll *
3288 intel_get_shared_dpll(struct intel_crtc *crtc,
3289                       struct intel_crtc_state *crtc_state,
3290                       struct intel_encoder *encoder)
3291 {
3292         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3293         const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
3294
3295         if (WARN_ON(!dpll_mgr))
3296                 return NULL;
3297
3298         return dpll_mgr->get_dpll(crtc, crtc_state, encoder);
3299 }
3300
3301 /**
3302  * intel_release_shared_dpll - end use of DPLL by CRTC in atomic state
3303  * @dpll: dpll in use by @crtc
3304  * @crtc: crtc
3305  * @state: atomic state
3306  *
3307  * This function releases the reference from @crtc to @dpll from the
3308  * atomic @state. The new configuration is made effective by calling
3309  * intel_shared_dpll_swap_state().
3310  */
3311 void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
3312                                struct intel_crtc *crtc,
3313                                struct drm_atomic_state *state)
3314 {
3315         struct intel_shared_dpll_state *shared_dpll_state;
3316
3317         shared_dpll_state = intel_atomic_get_shared_dpll_state(state);
3318         shared_dpll_state[dpll->info->id].crtc_mask &= ~(1 << crtc->pipe);
3319 }
3320
3321 /**
3322  * intel_shared_dpll_dump_hw_state - write hw_state to dmesg
3323  * @dev_priv: i915 drm device
3324  * @hw_state: hw state to be written to the log
3325  *
3326  * Write the relevant values in @hw_state to dmesg using DRM_DEBUG_KMS.
3327  */
3328 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
3329                               struct intel_dpll_hw_state *hw_state)
3330 {
3331         if (dev_priv->dpll_mgr) {
3332                 dev_priv->dpll_mgr->dump_hw_state(dev_priv, hw_state);
3333         } else {
3334                 /* fallback for platforms that don't use the shared dpll
3335                  * infrastructure
3336                  */
3337                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
3338                               "fp0: 0x%x, fp1: 0x%x\n",
3339                               hw_state->dpll,
3340                               hw_state->dpll_md,
3341                               hw_state->fp0,
3342                               hw_state->fp1);
3343         }
3344 }