drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include "intel_drv.h"
  43 #include <drm/i915_drm.h>
  44 #include "i915_drv.h"
  45
  46 #define DP_DPRX_ESI_LEN 14
  47
  48 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
  49 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER      61440
  50 #define DP_DSC_MIN_SUPPORTED_BPC                8
  51 #define DP_DSC_MAX_SUPPORTED_BPC                10
  52
  53 /* DP DSC throughput values used for slice count calculations KPixels/s */
  54 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  55 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  56 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  57
  58 /* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
  59 #define DP_DSC_FEC_OVERHEAD_FACTOR              976
  60
  61 /* Compliance test status bits  */
  62 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  63 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  64 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  65 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  66
  67 struct dp_link_dpll {
  68         int clock;
  69         struct dpll dpll;
  70 };
  71
  72 static const struct dp_link_dpll g4x_dpll[] = {
  73         { 162000,
  74                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  75         { 270000,
  76                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  77 };
  78
  79 static const struct dp_link_dpll pch_dpll[] = {
  80         { 162000,
  81                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  82         { 270000,
  83                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  84 };
  85
  86 static const struct dp_link_dpll vlv_dpll[] = {
  87         { 162000,
  88                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  89         { 270000,
  90                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  91 };
  92
  93 /*
  94  * CHV supports eDP 1.4 that have  more link rates.
  95  * Below only provides the fixed rate but exclude variable rate.
  96  */
  97 static const struct dp_link_dpll chv_dpll[] = {
  98         /*
  99          * CHV requires to program fractional division for m2.
 100          * m2 is stored in fixed point format using formula below
 101          * (m2_int << 22) | m2_fraction
 102          */
 103         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 104                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 105         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 106                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 107 };
 108
 109 /* Constants for DP DSC configurations */
 110 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 111
 112 /* With Single pipe configuration, HW is capable of supporting maximum
 113  * of 4 slices per line.
 114  */
 115 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 116
 117 /**
 118  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 119  * @intel_dp: DP struct
 120  *
 121  * If a CPU or PCH DP output is attached to an eDP panel, this function
 122  * will return true, and false otherwise.
 123  */
 124 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 125 {
 126         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 127
 128         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 129 }
 130
 131 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 132 {
 133         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 134 }
 135
 136 static void intel_dp_link_down(struct intel_encoder *encoder,
 137                                const struct intel_crtc_state *old_crtc_state);
 138 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 139 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 140 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 141                                            const struct intel_crtc_state *crtc_state);
 142 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 143                                       enum pipe pipe);
 144 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 145
 146 /* update sink rates from dpcd */
 147 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 148 {
 149         static const int dp_rates[] = {
 150                 162000, 270000, 540000, 810000
 151         };
 152         int i, max_rate;
 153
 154         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 155
 156         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 157                 if (dp_rates[i] > max_rate)
 158                         break;
 159                 intel_dp->sink_rates[i] = dp_rates[i];
 160         }
 161
 162         intel_dp->num_sink_rates = i;
 163 }
 164
 165 /* Get length of rates array potentially limited by max_rate. */
 166 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 167 {
 168         int i;
 169
 170         /* Limit results by potentially reduced max rate */
 171         for (i = 0; i < len; i++) {
 172                 if (rates[len - i - 1] <= max_rate)
 173                         return len - i;
 174         }
 175
 176         return 0;
 177 }
 178
 179 /* Get length of common rates array potentially limited by max_rate. */
 180 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 181                                           int max_rate)
 182 {
 183         return intel_dp_rate_limit_len(intel_dp->common_rates,
 184                                        intel_dp->num_common_rates, max_rate);
 185 }
 186
 187 /* Theoretical max between source and sink */
 188 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 189 {
 190         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 191 }
 192
 193 static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
 194 {
 195         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 196         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 197         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
 198         u32 lane_info;
 199
 200         if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
 201                 return 4;
 202
 203         lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
 204                      DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
 205                     DP_LANE_ASSIGNMENT_SHIFT(tc_port);
 206
 207         switch (lane_info) {
 208         default:
 209                 MISSING_CASE(lane_info);
 210         case 1:
 211         case 2:
 212         case 4:
 213         case 8:
 214                 return 1;
 215         case 3:
 216         case 12:
 217                 return 2;
 218         case 15:
 219                 return 4;
 220         }
 221 }
 222
 223 /* Theoretical max between source and sink */
 224 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 225 {
 226         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 227         int source_max = intel_dig_port->max_lanes;
 228         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 229         int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
 230
 231         return min3(source_max, sink_max, fia_max);
 232 }
 233
 234 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 235 {
 236         return intel_dp->max_link_lane_count;
 237 }
 238
 239 int
 240 intel_dp_link_required(int pixel_clock, int bpp)
 241 {
 242         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 243         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 244 }
 245
 246 int
 247 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 248 {
 249         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 250          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 251          * is transmitted every LS_Clk per lane, there is no need to account for
 252          * the channel encoding that is done in the PHY layer here.
 253          */
 254
 255         return max_link_clock * max_lanes;
 256 }
 257
 258 static int
 259 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 260 {
 261         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 262         struct intel_encoder *encoder = &intel_dig_port->base;
 263         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 264         int max_dotclk = dev_priv->max_dotclk_freq;
 265         int ds_max_dotclk;
 266
 267         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 268
 269         if (type != DP_DS_PORT_TYPE_VGA)
 270                 return max_dotclk;
 271
 272         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 273                                                     intel_dp->downstream_ports);
 274
 275         if (ds_max_dotclk != 0)
 276                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 277
 278         return max_dotclk;
 279 }
 280
 281 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 282 {
 283         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 284         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 285         enum port port = dig_port->base.port;
 286
 287         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 288
 289         /* Low voltage SKUs are limited to max of 5.4G */
 290         if (voltage == VOLTAGE_INFO_0_85V)
 291                 return 540000;
 292
 293         /* For this SKU 8.1G is supported in all ports */
 294         if (IS_CNL_WITH_PORT_F(dev_priv))
 295                 return 810000;
 296
 297         /* For other SKUs, max rate on ports A and D is 5.4G */
 298         if (port == PORT_A || port == PORT_D)
 299                 return 540000;
 300
 301         return 810000;
 302 }
 303
 304 static int icl_max_source_rate(struct intel_dp *intel_dp)
 305 {
 306         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 307         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 308         enum port port = dig_port->base.port;
 309
 310         if (intel_port_is_combophy(dev_priv, port) &&
 311             !intel_dp_is_edp(intel_dp))
 312                 return 540000;
 313
 314         return 810000;
 315 }
 316
 317 static void
 318 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 319 {
 320         /* The values must be in increasing order */
 321         static const int cnl_rates[] = {
 322                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 323         };
 324         static const int bxt_rates[] = {
 325                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 326         };
 327         static const int skl_rates[] = {
 328                 162000, 216000, 270000, 324000, 432000, 540000
 329         };
 330         static const int hsw_rates[] = {
 331                 162000, 270000, 540000
 332         };
 333         static const int g4x_rates[] = {
 334                 162000, 270000
 335         };
 336         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 337         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 338         const struct ddi_vbt_port_info *info =
 339                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 340         const int *source_rates;
 341         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 342
 343         /* This should only be done once */
 344         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 345
 346         if (INTEL_GEN(dev_priv) >= 10) {
 347                 source_rates = cnl_rates;
 348                 size = ARRAY_SIZE(cnl_rates);
 349                 if (IS_GEN10(dev_priv))
 350                         max_rate = cnl_max_source_rate(intel_dp);
 351                 else
 352                         max_rate = icl_max_source_rate(intel_dp);
 353         } else if (IS_GEN9_LP(dev_priv)) {
 354                 source_rates = bxt_rates;
 355                 size = ARRAY_SIZE(bxt_rates);
 356         } else if (IS_GEN9_BC(dev_priv)) {
 357                 source_rates = skl_rates;
 358                 size = ARRAY_SIZE(skl_rates);
 359         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 360                    IS_BROADWELL(dev_priv)) {
 361                 source_rates = hsw_rates;
 362                 size = ARRAY_SIZE(hsw_rates);
 363         } else {
 364                 source_rates = g4x_rates;
 365                 size = ARRAY_SIZE(g4x_rates);
 366         }
 367
 368         if (max_rate && vbt_max_rate)
 369                 max_rate = min(max_rate, vbt_max_rate);
 370         else if (vbt_max_rate)
 371                 max_rate = vbt_max_rate;
 372
 373         if (max_rate)
 374                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 375
 376         intel_dp->source_rates = source_rates;
 377         intel_dp->num_source_rates = size;
 378 }
 379
 380 static int intersect_rates(const int *source_rates, int source_len,
 381                            const int *sink_rates, int sink_len,
 382                            int *common_rates)
 383 {
 384         int i = 0, j = 0, k = 0;
 385
 386         while (i < source_len && j < sink_len) {
 387                 if (source_rates[i] == sink_rates[j]) {
 388                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 389                                 return k;
 390                         common_rates[k] = source_rates[i];
 391                         ++k;
 392                         ++i;
 393                         ++j;
 394                 } else if (source_rates[i] < sink_rates[j]) {
 395                         ++i;
 396                 } else {
 397                         ++j;
 398                 }
 399         }
 400         return k;
 401 }
 402
 403 /* return index of rate in rates array, or -1 if not found */
 404 static int intel_dp_rate_index(const int *rates, int len, int rate)
 405 {
 406         int i;
 407
 408         for (i = 0; i < len; i++)
 409                 if (rate == rates[i])
 410                         return i;
 411
 412         return -1;
 413 }
 414
 415 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 416 {
 417         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 418
 419         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 420                                                      intel_dp->num_source_rates,
 421                                                      intel_dp->sink_rates,
 422                                                      intel_dp->num_sink_rates,
 423                                                      intel_dp->common_rates);
 424
 425         /* Paranoia, there should always be something in common. */
 426         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 427                 intel_dp->common_rates[0] = 162000;
 428                 intel_dp->num_common_rates = 1;
 429         }
 430 }
 431
 432 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 433                                        uint8_t lane_count)
 434 {
 435         /*
 436          * FIXME: we need to synchronize the current link parameters with
 437          * hardware readout. Currently fast link training doesn't work on
 438          * boot-up.
 439          */
 440         if (link_rate == 0 ||
 441             link_rate > intel_dp->max_link_rate)
 442                 return false;
 443
 444         if (lane_count == 0 ||
 445             lane_count > intel_dp_max_lane_count(intel_dp))
 446                 return false;
 447
 448         return true;
 449 }
 450
 451 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 452                                                      int link_rate,
 453                                                      uint8_t lane_count)
 454 {
 455         const struct drm_display_mode *fixed_mode =
 456                 intel_dp->attached_connector->panel.fixed_mode;
 457         int mode_rate, max_rate;
 458
 459         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 460         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 461         if (mode_rate > max_rate)
 462                 return false;
 463
 464         return true;
 465 }
 466
 467 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 468                                             int link_rate, uint8_t lane_count)
 469 {
 470         int index;
 471
 472         index = intel_dp_rate_index(intel_dp->common_rates,
 473                                     intel_dp->num_common_rates,
 474                                     link_rate);
 475         if (index > 0) {
 476                 if (intel_dp_is_edp(intel_dp) &&
 477                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 478                                                               intel_dp->common_rates[index - 1],
 479                                                               lane_count)) {
 480                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 481                         return 0;
 482                 }
 483                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 484                 intel_dp->max_link_lane_count = lane_count;
 485         } else if (lane_count > 1) {
 486                 if (intel_dp_is_edp(intel_dp) &&
 487                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 488                                                               intel_dp_max_common_rate(intel_dp),
 489                                                               lane_count >> 1)) {
 490                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 491                         return 0;
 492                 }
 493                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 494                 intel_dp->max_link_lane_count = lane_count >> 1;
 495         } else {
 496                 DRM_ERROR("Link Training Unsuccessful\n");
 497                 return -1;
 498         }
 499
 500         return 0;
 501 }
 502
 503 static enum drm_mode_status
 504 intel_dp_mode_valid(struct drm_connector *connector,
 505                     struct drm_display_mode *mode)
 506 {
 507         struct intel_dp *intel_dp = intel_attached_dp(connector);
 508         struct intel_connector *intel_connector = to_intel_connector(connector);
 509         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 510         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 511         int target_clock = mode->clock;
 512         int max_rate, mode_rate, max_lanes, max_link_clock;
 513         int max_dotclk;
 514         u16 dsc_max_output_bpp = 0;
 515         u8 dsc_slice_count = 0;
 516
 517         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 518                 return MODE_NO_DBLESCAN;
 519
 520         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 521
 522         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 523                 if (mode->hdisplay > fixed_mode->hdisplay)
 524                         return MODE_PANEL;
 525
 526                 if (mode->vdisplay > fixed_mode->vdisplay)
 527                         return MODE_PANEL;
 528
 529                 target_clock = fixed_mode->clock;
 530         }
 531
 532         max_link_clock = intel_dp_max_link_rate(intel_dp);
 533         max_lanes = intel_dp_max_lane_count(intel_dp);
 534
 535         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 536         mode_rate = intel_dp_link_required(target_clock, 18);
 537
 538         /*
 539          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 540          * integer value since we support only integer values of bpp.
 541          */
 542         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 543             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 544                 if (intel_dp_is_edp(intel_dp)) {
 545                         dsc_max_output_bpp =
 546                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 547                         dsc_slice_count =
 548                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 549                                                                 true);
 550                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 551                         dsc_max_output_bpp =
 552                                 intel_dp_dsc_get_output_bpp(max_link_clock,
 553                                                             max_lanes,
 554                                                             target_clock,
 555                                                             mode->hdisplay) >> 4;
 556                         dsc_slice_count =
 557                                 intel_dp_dsc_get_slice_count(intel_dp,
 558                                                              target_clock,
 559                                                              mode->hdisplay);
 560                 }
 561         }
 562
 563         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
 564             target_clock > max_dotclk)
 565                 return MODE_CLOCK_HIGH;
 566
 567         if (mode->clock < 10000)
 568                 return MODE_CLOCK_LOW;
 569
 570         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 571                 return MODE_H_ILLEGAL;
 572
 573         return MODE_OK;
 574 }
 575
 576 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 577 {
 578         int     i;
 579         uint32_t v = 0;
 580
 581         if (src_bytes > 4)
 582                 src_bytes = 4;
 583         for (i = 0; i < src_bytes; i++)
 584                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 585         return v;
 586 }
 587
 588 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 589 {
 590         int i;
 591         if (dst_bytes > 4)
 592                 dst_bytes = 4;
 593         for (i = 0; i < dst_bytes; i++)
 594                 dst[i] = src >> ((3-i) * 8);
 595 }
 596
 597 static void
 598 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 599 static void
 600 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 601                                               bool force_disable_vdd);
 602 static void
 603 intel_dp_pps_init(struct intel_dp *intel_dp);
 604
 605 static void pps_lock(struct intel_dp *intel_dp)
 606 {
 607         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 608
 609         /*
 610          * See intel_power_sequencer_reset() why we need
 611          * a power domain reference here.
 612          */
 613         intel_display_power_get(dev_priv,
 614                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 615
 616         mutex_lock(&dev_priv->pps_mutex);
 617 }
 618
 619 static void pps_unlock(struct intel_dp *intel_dp)
 620 {
 621         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 622
 623         mutex_unlock(&dev_priv->pps_mutex);
 624
 625         intel_display_power_put(dev_priv,
 626                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 627 }
 628
 629 static void
 630 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 631 {
 632         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 633         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 634         enum pipe pipe = intel_dp->pps_pipe;
 635         bool pll_enabled, release_cl_override = false;
 636         enum dpio_phy phy = DPIO_PHY(pipe);
 637         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 638         uint32_t DP;
 639
 640         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 641                  "skipping pipe %c power sequencer kick due to port %c being active\n",
 642                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 643                 return;
 644
 645         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 646                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 647
 648         /* Preserve the BIOS-computed detected bit. This is
 649          * supposed to be read-only.
 650          */
 651         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 652         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 653         DP |= DP_PORT_WIDTH(1);
 654         DP |= DP_LINK_TRAIN_PAT_1;
 655
 656         if (IS_CHERRYVIEW(dev_priv))
 657                 DP |= DP_PIPE_SEL_CHV(pipe);
 658         else
 659                 DP |= DP_PIPE_SEL(pipe);
 660
 661         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 662
 663         /*
 664          * The DPLL for the pipe must be enabled for this to work.
 665          * So enable temporarily it if it's not already enabled.
 666          */
 667         if (!pll_enabled) {
 668                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 669                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 670
 671                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 672                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 673                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 674                                   pipe_name(pipe));
 675                         return;
 676                 }
 677         }
 678
 679         /*
 680          * Similar magic as in intel_dp_enable_port().
 681          * We _must_ do this port enable + disable trick
 682          * to make this power sequencer lock onto the port.
 683          * Otherwise even VDD force bit won't work.
 684          */
 685         I915_WRITE(intel_dp->output_reg, DP);
 686         POSTING_READ(intel_dp->output_reg);
 687
 688         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 689         POSTING_READ(intel_dp->output_reg);
 690
 691         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 692         POSTING_READ(intel_dp->output_reg);
 693
 694         if (!pll_enabled) {
 695                 vlv_force_pll_off(dev_priv, pipe);
 696
 697                 if (release_cl_override)
 698                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 699         }
 700 }
 701
 702 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 703 {
 704         struct intel_encoder *encoder;
 705         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 706
 707         /*
 708          * We don't have power sequencer currently.
 709          * Pick one that's not used by other ports.
 710          */
 711         for_each_intel_dp(&dev_priv->drm, encoder) {
 712                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 713
 714                 if (encoder->type == INTEL_OUTPUT_EDP) {
 715                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 716                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 717
 718                         if (intel_dp->pps_pipe != INVALID_PIPE)
 719                                 pipes &= ~(1 << intel_dp->pps_pipe);
 720                 } else {
 721                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 722
 723                         if (intel_dp->active_pipe != INVALID_PIPE)
 724                                 pipes &= ~(1 << intel_dp->active_pipe);
 725                 }
 726         }
 727
 728         if (pipes == 0)
 729                 return INVALID_PIPE;
 730
 731         return ffs(pipes) - 1;
 732 }
 733
 734 static enum pipe
 735 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 736 {
 737         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 738         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 739         enum pipe pipe;
 740
 741         lockdep_assert_held(&dev_priv->pps_mutex);
 742
 743         /* We should never land here with regular DP ports */
 744         WARN_ON(!intel_dp_is_edp(intel_dp));
 745
 746         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 747                 intel_dp->active_pipe != intel_dp->pps_pipe);
 748
 749         if (intel_dp->pps_pipe != INVALID_PIPE)
 750                 return intel_dp->pps_pipe;
 751
 752         pipe = vlv_find_free_pps(dev_priv);
 753
 754         /*
 755          * Didn't find one. This should not happen since there
 756          * are two power sequencers and up to two eDP ports.
 757          */
 758         if (WARN_ON(pipe == INVALID_PIPE))
 759                 pipe = PIPE_A;
 760
 761         vlv_steal_power_sequencer(dev_priv, pipe);
 762         intel_dp->pps_pipe = pipe;
 763
 764         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 765                       pipe_name(intel_dp->pps_pipe),
 766                       port_name(intel_dig_port->base.port));
 767
 768         /* init power sequencer on this pipe and port */
 769         intel_dp_init_panel_power_sequencer(intel_dp);
 770         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 771
 772         /*
 773          * Even vdd force doesn't work until we've made
 774          * the power sequencer lock in on the port.
 775          */
 776         vlv_power_sequencer_kick(intel_dp);
 777
 778         return intel_dp->pps_pipe;
 779 }
 780
 781 static int
 782 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 783 {
 784         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 785         int backlight_controller = dev_priv->vbt.backlight.controller;
 786
 787         lockdep_assert_held(&dev_priv->pps_mutex);
 788
 789         /* We should never land here with regular DP ports */
 790         WARN_ON(!intel_dp_is_edp(intel_dp));
 791
 792         if (!intel_dp->pps_reset)
 793                 return backlight_controller;
 794
 795         intel_dp->pps_reset = false;
 796
 797         /*
 798          * Only the HW needs to be reprogrammed, the SW state is fixed and
 799          * has been setup during connector init.
 800          */
 801         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 802
 803         return backlight_controller;
 804 }
 805
 806 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 807                                enum pipe pipe);
 808
 809 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 810                                enum pipe pipe)
 811 {
 812         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 813 }
 814
 815 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 816                                 enum pipe pipe)
 817 {
 818         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 819 }
 820
 821 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 822                          enum pipe pipe)
 823 {
 824         return true;
 825 }
 826
 827 static enum pipe
 828 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 829                      enum port port,
 830                      vlv_pipe_check pipe_check)
 831 {
 832         enum pipe pipe;
 833
 834         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 835                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 836                         PANEL_PORT_SELECT_MASK;
 837
 838                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 839                         continue;
 840
 841                 if (!pipe_check(dev_priv, pipe))
 842                         continue;
 843
 844                 return pipe;
 845         }
 846
 847         return INVALID_PIPE;
 848 }
 849
 850 static void
 851 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 852 {
 853         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 854         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 855         enum port port = intel_dig_port->base.port;
 856
 857         lockdep_assert_held(&dev_priv->pps_mutex);
 858
 859         /* try to find a pipe with this port selected */
 860         /* first pick one where the panel is on */
 861         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 862                                                   vlv_pipe_has_pp_on);
 863         /* didn't find one? pick one where vdd is on */
 864         if (intel_dp->pps_pipe == INVALID_PIPE)
 865                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 866                                                           vlv_pipe_has_vdd_on);
 867         /* didn't find one? pick one with just the correct port */
 868         if (intel_dp->pps_pipe == INVALID_PIPE)
 869                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 870                                                           vlv_pipe_any);
 871
 872         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 873         if (intel_dp->pps_pipe == INVALID_PIPE) {
 874                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 875                               port_name(port));
 876                 return;
 877         }
 878
 879         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 880                       port_name(port), pipe_name(intel_dp->pps_pipe));
 881
 882         intel_dp_init_panel_power_sequencer(intel_dp);
 883         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 884 }
 885
 886 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 887 {
 888         struct intel_encoder *encoder;
 889
 890         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 891                     !IS_GEN9_LP(dev_priv)))
 892                 return;
 893
 894         /*
 895          * We can't grab pps_mutex here due to deadlock with power_domain
 896          * mutex when power_domain functions are called while holding pps_mutex.
 897          * That also means that in order to use pps_pipe the code needs to
 898          * hold both a power domain reference and pps_mutex, and the power domain
 899          * reference get/put must be done while _not_ holding pps_mutex.
 900          * pps_{lock,unlock}() do these steps in the correct order, so one
 901          * should use them always.
 902          */
 903
 904         for_each_intel_dp(&dev_priv->drm, encoder) {
 905                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 906
 907                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 908
 909                 if (encoder->type != INTEL_OUTPUT_EDP)
 910                         continue;
 911
 912                 if (IS_GEN9_LP(dev_priv))
 913                         intel_dp->pps_reset = true;
 914                 else
 915                         intel_dp->pps_pipe = INVALID_PIPE;
 916         }
 917 }
 918
 919 struct pps_registers {
 920         i915_reg_t pp_ctrl;
 921         i915_reg_t pp_stat;
 922         i915_reg_t pp_on;
 923         i915_reg_t pp_off;
 924         i915_reg_t pp_div;
 925 };
 926
 927 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 928                                     struct pps_registers *regs)
 929 {
 930         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 931         int pps_idx = 0;
 932
 933         memset(regs, 0, sizeof(*regs));
 934
 935         if (IS_GEN9_LP(dev_priv))
 936                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 937         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 938                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 939
 940         regs->pp_ctrl = PP_CONTROL(pps_idx);
 941         regs->pp_stat = PP_STATUS(pps_idx);
 942         regs->pp_on = PP_ON_DELAYS(pps_idx);
 943         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 944         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
 945             !HAS_PCH_ICP(dev_priv))
 946                 regs->pp_div = PP_DIVISOR(pps_idx);
 947 }
 948
 949 static i915_reg_t
 950 _pp_ctrl_reg(struct intel_dp *intel_dp)
 951 {
 952         struct pps_registers regs;
 953
 954         intel_pps_get_registers(intel_dp, &regs);
 955
 956         return regs.pp_ctrl;
 957 }
 958
 959 static i915_reg_t
 960 _pp_stat_reg(struct intel_dp *intel_dp)
 961 {
 962         struct pps_registers regs;
 963
 964         intel_pps_get_registers(intel_dp, &regs);
 965
 966         return regs.pp_stat;
 967 }
 968
 969 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 970    This function only applicable when panel PM state is not to be tracked */
 971 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 972                               void *unused)
 973 {
 974         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 975                                                  edp_notifier);
 976         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 977
 978         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 979                 return 0;
 980
 981         pps_lock(intel_dp);
 982
 983         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 984                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 985                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 986                 u32 pp_div;
 987
 988                 pp_ctrl_reg = PP_CONTROL(pipe);
 989                 pp_div_reg  = PP_DIVISOR(pipe);
 990                 pp_div = I915_READ(pp_div_reg);
 991                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 992
 993                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 994                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 995                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 996                 msleep(intel_dp->panel_power_cycle_delay);
 997         }
 998
 999         pps_unlock(intel_dp);
1000
1001         return 0;
1002 }
1003
1004 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1005 {
1006         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1007
1008         lockdep_assert_held(&dev_priv->pps_mutex);
1009
1010         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1011             intel_dp->pps_pipe == INVALID_PIPE)
1012                 return false;
1013
1014         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1015 }
1016
1017 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1018 {
1019         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1020
1021         lockdep_assert_held(&dev_priv->pps_mutex);
1022
1023         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1024             intel_dp->pps_pipe == INVALID_PIPE)
1025                 return false;
1026
1027         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1028 }
1029
1030 static void
1031 intel_dp_check_edp(struct intel_dp *intel_dp)
1032 {
1033         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1034
1035         if (!intel_dp_is_edp(intel_dp))
1036                 return;
1037
1038         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1039                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1040                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1041                               I915_READ(_pp_stat_reg(intel_dp)),
1042                               I915_READ(_pp_ctrl_reg(intel_dp)));
1043         }
1044 }
1045
1046 static uint32_t
1047 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1048 {
1049         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1050         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1051         uint32_t status;
1052         bool done;
1053
1054 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1055         done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
1056                                   msecs_to_jiffies_timeout(10));
1057         if (!done)
1058                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1059 #undef C
1060
1061         return status;
1062 }
1063
1064 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1065 {
1066         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1067
1068         if (index)
1069                 return 0;
1070
1071         /*
1072          * The clock divider is based off the hrawclk, and would like to run at
1073          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1074          */
1075         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1076 }
1077
1078 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1079 {
1080         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1081         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1082
1083         if (index)
1084                 return 0;
1085
1086         /*
1087          * The clock divider is based off the cdclk or PCH rawclk, and would
1088          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1089          * divide by 2000 and use that
1090          */
1091         if (dig_port->aux_ch == AUX_CH_A)
1092                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1093         else
1094                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1095 }
1096
1097 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1098 {
1099         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1100         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1101
1102         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1103                 /* Workaround for non-ULT HSW */
1104                 switch (index) {
1105                 case 0: return 63;
1106                 case 1: return 72;
1107                 default: return 0;
1108                 }
1109         }
1110
1111         return ilk_get_aux_clock_divider(intel_dp, index);
1112 }
1113
1114 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1115 {
1116         /*
1117          * SKL doesn't need us to program the AUX clock divider (Hardware will
1118          * derive the clock from CDCLK automatically). We still implement the
1119          * get_aux_clock_divider vfunc to plug-in into the existing code.
1120          */
1121         return index ? 0 : 1;
1122 }
1123
1124 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1125                                      int send_bytes,
1126                                      uint32_t aux_clock_divider)
1127 {
1128         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1129         struct drm_i915_private *dev_priv =
1130                         to_i915(intel_dig_port->base.base.dev);
1131         uint32_t precharge, timeout;
1132
1133         if (IS_GEN6(dev_priv))
1134                 precharge = 3;
1135         else
1136                 precharge = 5;
1137
1138         if (IS_BROADWELL(dev_priv))
1139                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1140         else
1141                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1142
1143         return DP_AUX_CH_CTL_SEND_BUSY |
1144                DP_AUX_CH_CTL_DONE |
1145                DP_AUX_CH_CTL_INTERRUPT |
1146                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1147                timeout |
1148                DP_AUX_CH_CTL_RECEIVE_ERROR |
1149                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1150                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1151                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1152 }
1153
1154 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1155                                       int send_bytes,
1156                                       uint32_t unused)
1157 {
1158         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1159         uint32_t ret;
1160
1161         ret = DP_AUX_CH_CTL_SEND_BUSY |
1162               DP_AUX_CH_CTL_DONE |
1163               DP_AUX_CH_CTL_INTERRUPT |
1164               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1165               DP_AUX_CH_CTL_TIME_OUT_MAX |
1166               DP_AUX_CH_CTL_RECEIVE_ERROR |
1167               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1168               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1169               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1170
1171         if (intel_dig_port->tc_type == TC_PORT_TBT)
1172                 ret |= DP_AUX_CH_CTL_TBT_IO;
1173
1174         return ret;
1175 }
1176
1177 static int
1178 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1179                   const uint8_t *send, int send_bytes,
1180                   uint8_t *recv, int recv_size,
1181                   u32 aux_send_ctl_flags)
1182 {
1183         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1184         struct drm_i915_private *dev_priv =
1185                         to_i915(intel_dig_port->base.base.dev);
1186         i915_reg_t ch_ctl, ch_data[5];
1187         uint32_t aux_clock_divider;
1188         int i, ret, recv_bytes;
1189         uint32_t status;
1190         int try, clock = 0;
1191         bool vdd;
1192
1193         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1194         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1195                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1196
1197         pps_lock(intel_dp);
1198
1199         /*
1200          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1201          * In such cases we want to leave VDD enabled and it's up to upper layers
1202          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1203          * ourselves.
1204          */
1205         vdd = edp_panel_vdd_on(intel_dp);
1206
1207         /* dp aux is extremely sensitive to irq latency, hence request the
1208          * lowest possible wakeup latency and so prevent the cpu from going into
1209          * deep sleep states.
1210          */
1211         pm_qos_update_request(&dev_priv->pm_qos, 0);
1212
1213         intel_dp_check_edp(intel_dp);
1214
1215         /* Try to wait for any previous AUX channel activity */
1216         for (try = 0; try < 3; try++) {
1217                 status = I915_READ_NOTRACE(ch_ctl);
1218                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1219                         break;
1220                 msleep(1);
1221         }
1222
1223         if (try == 3) {
1224                 static u32 last_status = -1;
1225                 const u32 status = I915_READ(ch_ctl);
1226
1227                 if (status != last_status) {
1228                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1229                              status);
1230                         last_status = status;
1231                 }
1232
1233                 ret = -EBUSY;
1234                 goto out;
1235         }
1236
1237         /* Only 5 data registers! */
1238         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1239                 ret = -E2BIG;
1240                 goto out;
1241         }
1242
1243         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1244                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1245                                                           send_bytes,
1246                                                           aux_clock_divider);
1247
1248                 send_ctl |= aux_send_ctl_flags;
1249
1250                 /* Must try at least 3 times according to DP spec */
1251                 for (try = 0; try < 5; try++) {
1252                         /* Load the send data into the aux channel data registers */
1253                         for (i = 0; i < send_bytes; i += 4)
1254                                 I915_WRITE(ch_data[i >> 2],
1255                                            intel_dp_pack_aux(send + i,
1256                                                              send_bytes - i));
1257
1258                         /* Send the command and wait for it to complete */
1259                         I915_WRITE(ch_ctl, send_ctl);
1260
1261                         status = intel_dp_aux_wait_done(intel_dp);
1262
1263                         /* Clear done status and any errors */
1264                         I915_WRITE(ch_ctl,
1265                                    status |
1266                                    DP_AUX_CH_CTL_DONE |
1267                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1268                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1269
1270                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1271                          *   400us delay required for errors and timeouts
1272                          *   Timeout errors from the HW already meet this
1273                          *   requirement so skip to next iteration
1274                          */
1275                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1276                                 continue;
1277
1278                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1279                                 usleep_range(400, 500);
1280                                 continue;
1281                         }
1282                         if (status & DP_AUX_CH_CTL_DONE)
1283                                 goto done;
1284                 }
1285         }
1286
1287         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1288                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1289                 ret = -EBUSY;
1290                 goto out;
1291         }
1292
1293 done:
1294         /* Check for timeout or receive error.
1295          * Timeouts occur when the sink is not connected
1296          */
1297         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1298                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1299                 ret = -EIO;
1300                 goto out;
1301         }
1302
1303         /* Timeouts occur when the device isn't connected, so they're
1304          * "normal" -- don't fill the kernel log with these */
1305         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1306                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1307                 ret = -ETIMEDOUT;
1308                 goto out;
1309         }
1310
1311         /* Unload any bytes sent back from the other side */
1312         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1313                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1314
1315         /*
1316          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1317          * We have no idea of what happened so we return -EBUSY so
1318          * drm layer takes care for the necessary retries.
1319          */
1320         if (recv_bytes == 0 || recv_bytes > 20) {
1321                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1322                               recv_bytes);
1323                 ret = -EBUSY;
1324                 goto out;
1325         }
1326
1327         if (recv_bytes > recv_size)
1328                 recv_bytes = recv_size;
1329
1330         for (i = 0; i < recv_bytes; i += 4)
1331                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1332                                     recv + i, recv_bytes - i);
1333
1334         ret = recv_bytes;
1335 out:
1336         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1337
1338         if (vdd)
1339                 edp_panel_vdd_off(intel_dp, false);
1340
1341         pps_unlock(intel_dp);
1342
1343         return ret;
1344 }
1345
1346 #define BARE_ADDRESS_SIZE       3
1347 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1348
1349 static void
1350 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1351                     const struct drm_dp_aux_msg *msg)
1352 {
1353         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1354         txbuf[1] = (msg->address >> 8) & 0xff;
1355         txbuf[2] = msg->address & 0xff;
1356         txbuf[3] = msg->size - 1;
1357 }
1358
1359 static ssize_t
1360 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1361 {
1362         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1363         uint8_t txbuf[20], rxbuf[20];
1364         size_t txsize, rxsize;
1365         int ret;
1366
1367         intel_dp_aux_header(txbuf, msg);
1368
1369         switch (msg->request & ~DP_AUX_I2C_MOT) {
1370         case DP_AUX_NATIVE_WRITE:
1371         case DP_AUX_I2C_WRITE:
1372         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1373                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1374                 rxsize = 2; /* 0 or 1 data bytes */
1375
1376                 if (WARN_ON(txsize > 20))
1377                         return -E2BIG;
1378
1379                 WARN_ON(!msg->buffer != !msg->size);
1380
1381                 if (msg->buffer)
1382                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1383
1384                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1385                                         rxbuf, rxsize, 0);
1386                 if (ret > 0) {
1387                         msg->reply = rxbuf[0] >> 4;
1388
1389                         if (ret > 1) {
1390                                 /* Number of bytes written in a short write. */
1391                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1392                         } else {
1393                                 /* Return payload size. */
1394                                 ret = msg->size;
1395                         }
1396                 }
1397                 break;
1398
1399         case DP_AUX_NATIVE_READ:
1400         case DP_AUX_I2C_READ:
1401                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1402                 rxsize = msg->size + 1;
1403
1404                 if (WARN_ON(rxsize > 20))
1405                         return -E2BIG;
1406
1407                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1408                                         rxbuf, rxsize, 0);
1409                 if (ret > 0) {
1410                         msg->reply = rxbuf[0] >> 4;
1411                         /*
1412                          * Assume happy day, and copy the data. The caller is
1413                          * expected to check msg->reply before touching it.
1414                          *
1415                          * Return payload size.
1416                          */
1417                         ret--;
1418                         memcpy(msg->buffer, rxbuf + 1, ret);
1419                 }
1420                 break;
1421
1422         default:
1423                 ret = -EINVAL;
1424                 break;
1425         }
1426
1427         return ret;
1428 }
1429
1430
1431 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1432 {
1433         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1434         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1435         enum aux_ch aux_ch = dig_port->aux_ch;
1436
1437         switch (aux_ch) {
1438         case AUX_CH_B:
1439         case AUX_CH_C:
1440         case AUX_CH_D:
1441                 return DP_AUX_CH_CTL(aux_ch);
1442         default:
1443                 MISSING_CASE(aux_ch);
1444                 return DP_AUX_CH_CTL(AUX_CH_B);
1445         }
1446 }
1447
1448 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1449 {
1450         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1451         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1452         enum aux_ch aux_ch = dig_port->aux_ch;
1453
1454         switch (aux_ch) {
1455         case AUX_CH_B:
1456         case AUX_CH_C:
1457         case AUX_CH_D:
1458                 return DP_AUX_CH_DATA(aux_ch, index);
1459         default:
1460                 MISSING_CASE(aux_ch);
1461                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1462         }
1463 }
1464
1465 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1466 {
1467         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1468         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1469         enum aux_ch aux_ch = dig_port->aux_ch;
1470
1471         switch (aux_ch) {
1472         case AUX_CH_A:
1473                 return DP_AUX_CH_CTL(aux_ch);
1474         case AUX_CH_B:
1475         case AUX_CH_C:
1476         case AUX_CH_D:
1477                 return PCH_DP_AUX_CH_CTL(aux_ch);
1478         default:
1479                 MISSING_CASE(aux_ch);
1480                 return DP_AUX_CH_CTL(AUX_CH_A);
1481         }
1482 }
1483
1484 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1485 {
1486         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1487         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1488         enum aux_ch aux_ch = dig_port->aux_ch;
1489
1490         switch (aux_ch) {
1491         case AUX_CH_A:
1492                 return DP_AUX_CH_DATA(aux_ch, index);
1493         case AUX_CH_B:
1494         case AUX_CH_C:
1495         case AUX_CH_D:
1496                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1497         default:
1498                 MISSING_CASE(aux_ch);
1499                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1500         }
1501 }
1502
1503 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1504 {
1505         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1506         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1507         enum aux_ch aux_ch = dig_port->aux_ch;
1508
1509         switch (aux_ch) {
1510         case AUX_CH_A:
1511         case AUX_CH_B:
1512         case AUX_CH_C:
1513         case AUX_CH_D:
1514         case AUX_CH_E:
1515         case AUX_CH_F:
1516                 return DP_AUX_CH_CTL(aux_ch);
1517         default:
1518                 MISSING_CASE(aux_ch);
1519                 return DP_AUX_CH_CTL(AUX_CH_A);
1520         }
1521 }
1522
1523 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1524 {
1525         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1526         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1527         enum aux_ch aux_ch = dig_port->aux_ch;
1528
1529         switch (aux_ch) {
1530         case AUX_CH_A:
1531         case AUX_CH_B:
1532         case AUX_CH_C:
1533         case AUX_CH_D:
1534         case AUX_CH_E:
1535         case AUX_CH_F:
1536                 return DP_AUX_CH_DATA(aux_ch, index);
1537         default:
1538                 MISSING_CASE(aux_ch);
1539                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1540         }
1541 }
1542
1543 static void
1544 intel_dp_aux_fini(struct intel_dp *intel_dp)
1545 {
1546         kfree(intel_dp->aux.name);
1547 }
1548
1549 static void
1550 intel_dp_aux_init(struct intel_dp *intel_dp)
1551 {
1552         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1553         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1554         struct intel_encoder *encoder = &dig_port->base;
1555
1556         if (INTEL_GEN(dev_priv) >= 9) {
1557                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1558                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1559         } else if (HAS_PCH_SPLIT(dev_priv)) {
1560                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1561                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1562         } else {
1563                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1564                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1565         }
1566
1567         if (INTEL_GEN(dev_priv) >= 9)
1568                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1569         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1570                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1571         else if (HAS_PCH_SPLIT(dev_priv))
1572                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1573         else
1574                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1575
1576         if (INTEL_GEN(dev_priv) >= 9)
1577                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1578         else
1579                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1580
1581         drm_dp_aux_init(&intel_dp->aux);
1582
1583         /* Failure to allocate our preferred name is not critical */
1584         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1585                                        port_name(encoder->port));
1586         intel_dp->aux.transfer = intel_dp_aux_transfer;
1587 }
1588
1589 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1590 {
1591         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1592
1593         return max_rate >= 540000;
1594 }
1595
1596 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1597 {
1598         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1599
1600         return max_rate >= 810000;
1601 }
1602
1603 static void
1604 intel_dp_set_clock(struct intel_encoder *encoder,
1605                    struct intel_crtc_state *pipe_config)
1606 {
1607         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1608         const struct dp_link_dpll *divisor = NULL;
1609         int i, count = 0;
1610
1611         if (IS_G4X(dev_priv)) {
1612                 divisor = g4x_dpll;
1613                 count = ARRAY_SIZE(g4x_dpll);
1614         } else if (HAS_PCH_SPLIT(dev_priv)) {
1615                 divisor = pch_dpll;
1616                 count = ARRAY_SIZE(pch_dpll);
1617         } else if (IS_CHERRYVIEW(dev_priv)) {
1618                 divisor = chv_dpll;
1619                 count = ARRAY_SIZE(chv_dpll);
1620         } else if (IS_VALLEYVIEW(dev_priv)) {
1621                 divisor = vlv_dpll;
1622                 count = ARRAY_SIZE(vlv_dpll);
1623         }
1624
1625         if (divisor && count) {
1626                 for (i = 0; i < count; i++) {
1627                         if (pipe_config->port_clock == divisor[i].clock) {
1628                                 pipe_config->dpll = divisor[i].dpll;
1629                                 pipe_config->clock_set = true;
1630                                 break;
1631                         }
1632                 }
1633         }
1634 }
1635
1636 static void snprintf_int_array(char *str, size_t len,
1637                                const int *array, int nelem)
1638 {
1639         int i;
1640
1641         str[0] = '\0';
1642
1643         for (i = 0; i < nelem; i++) {
1644                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1645                 if (r >= len)
1646                         return;
1647                 str += r;
1648                 len -= r;
1649         }
1650 }
1651
1652 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1653 {
1654         char str[128]; /* FIXME: too big for stack? */
1655
1656         if ((drm_debug & DRM_UT_KMS) == 0)
1657                 return;
1658
1659         snprintf_int_array(str, sizeof(str),
1660                            intel_dp->source_rates, intel_dp->num_source_rates);
1661         DRM_DEBUG_KMS("source rates: %s\n", str);
1662
1663         snprintf_int_array(str, sizeof(str),
1664                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1665         DRM_DEBUG_KMS("sink rates: %s\n", str);
1666
1667         snprintf_int_array(str, sizeof(str),
1668                            intel_dp->common_rates, intel_dp->num_common_rates);
1669         DRM_DEBUG_KMS("common rates: %s\n", str);
1670 }
1671
1672 int
1673 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1674 {
1675         int len;
1676
1677         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1678         if (WARN_ON(len <= 0))
1679                 return 162000;
1680
1681         return intel_dp->common_rates[len - 1];
1682 }
1683
1684 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1685 {
1686         int i = intel_dp_rate_index(intel_dp->sink_rates,
1687                                     intel_dp->num_sink_rates, rate);
1688
1689         if (WARN_ON(i < 0))
1690                 i = 0;
1691
1692         return i;
1693 }
1694
1695 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1696                            uint8_t *link_bw, uint8_t *rate_select)
1697 {
1698         /* eDP 1.4 rate select method. */
1699         if (intel_dp->use_rate_select) {
1700                 *link_bw = 0;
1701                 *rate_select =
1702                         intel_dp_rate_select(intel_dp, port_clock);
1703         } else {
1704                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1705                 *rate_select = 0;
1706         }
1707 }
1708
1709 struct link_config_limits {
1710         int min_clock, max_clock;
1711         int min_lane_count, max_lane_count;
1712         int min_bpp, max_bpp;
1713 };
1714
1715 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1716                                          const struct intel_crtc_state *pipe_config)
1717 {
1718         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1719
1720         return INTEL_GEN(dev_priv) >= 11 &&
1721                 pipe_config->cpu_transcoder != TRANSCODER_A;
1722 }
1723
1724 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1725                                   const struct intel_crtc_state *pipe_config)
1726 {
1727         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1728                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1729 }
1730
1731 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1732                                          const struct intel_crtc_state *pipe_config)
1733 {
1734         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1735
1736         return INTEL_GEN(dev_priv) >= 10 &&
1737                 pipe_config->cpu_transcoder != TRANSCODER_A;
1738 }
1739
1740 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1741                                   const struct intel_crtc_state *pipe_config)
1742 {
1743         if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1744                 return false;
1745
1746         return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1747                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1748 }
1749
1750 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1751                                 struct intel_crtc_state *pipe_config)
1752 {
1753         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1754         struct intel_connector *intel_connector = intel_dp->attached_connector;
1755         int bpp, bpc;
1756
1757         bpp = pipe_config->pipe_bpp;
1758         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1759
1760         if (bpc > 0)
1761                 bpp = min(bpp, 3*bpc);
1762
1763         if (intel_dp_is_edp(intel_dp)) {
1764                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1765                 if (intel_connector->base.display_info.bpc == 0 &&
1766                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1767                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1768                                       dev_priv->vbt.edp.bpp);
1769                         bpp = dev_priv->vbt.edp.bpp;
1770                 }
1771         }
1772
1773         return bpp;
1774 }
1775
1776 /* Adjust link config limits based on compliance test requests. */
1777 static void
1778 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1779                                   struct intel_crtc_state *pipe_config,
1780                                   struct link_config_limits *limits)
1781 {
1782         /* For DP Compliance we override the computed bpp for the pipe */
1783         if (intel_dp->compliance.test_data.bpc != 0) {
1784                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1785
1786                 limits->min_bpp = limits->max_bpp = bpp;
1787                 pipe_config->dither_force_disable = bpp == 6 * 3;
1788
1789                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1790         }
1791
1792         /* Use values requested by Compliance Test Request */
1793         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1794                 int index;
1795
1796                 /* Validate the compliance test data since max values
1797                  * might have changed due to link train fallback.
1798                  */
1799                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1800                                                intel_dp->compliance.test_lane_count)) {
1801                         index = intel_dp_rate_index(intel_dp->common_rates,
1802                                                     intel_dp->num_common_rates,
1803                                                     intel_dp->compliance.test_link_rate);
1804                         if (index >= 0)
1805                                 limits->min_clock = limits->max_clock = index;
1806                         limits->min_lane_count = limits->max_lane_count =
1807                                 intel_dp->compliance.test_lane_count;
1808                 }
1809         }
1810 }
1811
1812 /* Optimize link config in order: max bpp, min clock, min lanes */
1813 static bool
1814 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1815                                   struct intel_crtc_state *pipe_config,
1816                                   const struct link_config_limits *limits)
1817 {
1818         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1819         int bpp, clock, lane_count;
1820         int mode_rate, link_clock, link_avail;
1821
1822         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1823                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1824                                                    bpp);
1825
1826                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1827                         for (lane_count = limits->min_lane_count;
1828                              lane_count <= limits->max_lane_count;
1829                              lane_count <<= 1) {
1830                                 link_clock = intel_dp->common_rates[clock];
1831                                 link_avail = intel_dp_max_data_rate(link_clock,
1832                                                                     lane_count);
1833
1834                                 if (mode_rate <= link_avail) {
1835                                         pipe_config->lane_count = lane_count;
1836                                         pipe_config->pipe_bpp = bpp;
1837                                         pipe_config->port_clock = link_clock;
1838
1839                                         return true;
1840                                 }
1841                         }
1842                 }
1843         }
1844
1845         return false;
1846 }
1847
1848 /* Optimize link config in order: max bpp, min lanes, min clock */
1849 static bool
1850 intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
1851                                   struct intel_crtc_state *pipe_config,
1852                                   const struct link_config_limits *limits)
1853 {
1854         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1855         int bpp, clock, lane_count;
1856         int mode_rate, link_clock, link_avail;
1857
1858         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1859                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1860                                                    bpp);
1861
1862                 for (lane_count = limits->min_lane_count;
1863                      lane_count <= limits->max_lane_count;
1864                      lane_count <<= 1) {
1865                         for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1866                                 link_clock = intel_dp->common_rates[clock];
1867                                 link_avail = intel_dp_max_data_rate(link_clock,
1868                                                                     lane_count);
1869
1870                                 if (mode_rate <= link_avail) {
1871                                         pipe_config->lane_count = lane_count;
1872                                         pipe_config->pipe_bpp = bpp;
1873                                         pipe_config->port_clock = link_clock;
1874
1875                                         return true;
1876                                 }
1877                         }
1878                 }
1879         }
1880
1881         return false;
1882 }
1883
1884 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1885 {
1886         int i, num_bpc;
1887         u8 dsc_bpc[3] = {0};
1888
1889         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1890                                                        dsc_bpc);
1891         for (i = 0; i < num_bpc; i++) {
1892                 if (dsc_max_bpc >= dsc_bpc[i])
1893                         return dsc_bpc[i] * 3;
1894         }
1895
1896         return 0;
1897 }
1898
1899 static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1900                                         struct intel_crtc_state *pipe_config,
1901                                         struct drm_connector_state *conn_state,
1902                                         struct link_config_limits *limits)
1903 {
1904         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1905         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1906         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1907         u8 dsc_max_bpc;
1908         int pipe_bpp;
1909
1910         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1911                 return false;
1912
1913         dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
1914                             conn_state->max_requested_bpc);
1915
1916         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1917         if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
1918                 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
1919                 return false;
1920         }
1921
1922         /*
1923          * For now enable DSC for max bpp, max link rate, max lane count.
1924          * Optimize this later for the minimum possible link rate/lane count
1925          * with DSC enabled for the requested mode.
1926          */
1927         pipe_config->pipe_bpp = pipe_bpp;
1928         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1929         pipe_config->lane_count = limits->max_lane_count;
1930
1931         if (intel_dp_is_edp(intel_dp)) {
1932                 pipe_config->dsc_params.compressed_bpp =
1933                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1934                               pipe_config->pipe_bpp);
1935                 pipe_config->dsc_params.slice_count =
1936                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1937                                                         true);
1938         } else {
1939                 u16 dsc_max_output_bpp;
1940                 u8 dsc_dp_slice_count;
1941
1942                 dsc_max_output_bpp =
1943                         intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
1944                                                     pipe_config->lane_count,
1945                                                     adjusted_mode->crtc_clock,
1946                                                     adjusted_mode->crtc_hdisplay);
1947                 dsc_dp_slice_count =
1948                         intel_dp_dsc_get_slice_count(intel_dp,
1949                                                      adjusted_mode->crtc_clock,
1950                                                      adjusted_mode->crtc_hdisplay);
1951                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1952                         DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
1953                         return false;
1954                 }
1955                 pipe_config->dsc_params.compressed_bpp = min_t(u16,
1956                                                                dsc_max_output_bpp >> 4,
1957                                                                pipe_config->pipe_bpp);
1958                 pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
1959         }
1960         /*
1961          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1962          * is greater than the maximum Cdclock and if slice count is even
1963          * then we need to use 2 VDSC instances.
1964          */
1965         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
1966                 if (pipe_config->dsc_params.slice_count > 1) {
1967                         pipe_config->dsc_params.dsc_split = true;
1968                 } else {
1969                         DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
1970                         return false;
1971                 }
1972         }
1973         if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
1974                 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
1975                               "Compressed BPP = %d\n",
1976                               pipe_config->pipe_bpp,
1977                               pipe_config->dsc_params.compressed_bpp);
1978                 return false;
1979         }
1980         pipe_config->dsc_params.compression_enable = true;
1981         DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
1982                       "Compressed Bpp = %d Slice Count = %d\n",
1983                       pipe_config->pipe_bpp,
1984                       pipe_config->dsc_params.compressed_bpp,
1985                       pipe_config->dsc_params.slice_count);
1986
1987         return true;
1988 }
1989
1990 static bool
1991 intel_dp_compute_link_config(struct intel_encoder *encoder,
1992                              struct intel_crtc_state *pipe_config,
1993                              struct drm_connector_state *conn_state)
1994 {
1995         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1996         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1997         struct link_config_limits limits;
1998         int common_len;
1999         bool ret;
2000
2001         common_len = intel_dp_common_len_rate_limit(intel_dp,
2002                                                     intel_dp->max_link_rate);
2003
2004         /* No common link rates between source and sink */
2005         WARN_ON(common_len <= 0);
2006
2007         limits.min_clock = 0;
2008         limits.max_clock = common_len - 1;
2009
2010         limits.min_lane_count = 1;
2011         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2012
2013         limits.min_bpp = 6 * 3;
2014         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2015
2016         if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
2017                 /*
2018                  * Use the maximum clock and number of lanes the eDP panel
2019                  * advertizes being capable of. The eDP 1.3 and earlier panels
2020                  * are generally designed to support only a single clock and
2021                  * lane configuration, and typically these values correspond to
2022                  * the native resolution of the panel. With eDP 1.4 rate select
2023                  * and DSC, this is decreasingly the case, and we need to be
2024                  * able to select less than maximum link config.
2025                  */
2026                 limits.min_lane_count = limits.max_lane_count;
2027                 limits.min_clock = limits.max_clock;
2028         }
2029
2030         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2031
2032         DRM_DEBUG_KMS("DP link computation with max lane count %i "
2033                       "max rate %d max bpp %d pixel clock %iKHz\n",
2034                       limits.max_lane_count,
2035                       intel_dp->common_rates[limits.max_clock],
2036                       limits.max_bpp, adjusted_mode->crtc_clock);
2037
2038         if (intel_dp_is_edp(intel_dp))
2039                 /*
2040                  * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
2041                  * section A.1: "It is recommended that the minimum number of
2042                  * lanes be used, using the minimum link rate allowed for that
2043                  * lane configuration."
2044                  *
2045                  * Note that we use the max clock and lane count for eDP 1.3 and
2046                  * earlier, and fast vs. wide is irrelevant.
2047                  */
2048                 ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config,
2049                                                         &limits);
2050         else
2051                 /* Optimize for slow and wide. */
2052                 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2053                                                         &limits);
2054
2055         /* enable compression if the mode doesn't fit available BW */
2056         if (!ret) {
2057                 if (!intel_dp_dsc_compute_config(intel_dp, pipe_config,
2058                                                  conn_state, &limits))
2059                         return false;
2060         }
2061
2062         if (pipe_config->dsc_params.compression_enable) {
2063                 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2064                               pipe_config->lane_count, pipe_config->port_clock,
2065                               pipe_config->pipe_bpp,
2066                               pipe_config->dsc_params.compressed_bpp);
2067
2068                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2069                               intel_dp_link_required(adjusted_mode->crtc_clock,
2070                                                      pipe_config->dsc_params.compressed_bpp),
2071                               intel_dp_max_data_rate(pipe_config->port_clock,
2072                                                      pipe_config->lane_count));
2073         } else {
2074                 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2075                               pipe_config->lane_count, pipe_config->port_clock,
2076                               pipe_config->pipe_bpp);
2077
2078                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2079                               intel_dp_link_required(adjusted_mode->crtc_clock,
2080                                                      pipe_config->pipe_bpp),
2081                               intel_dp_max_data_rate(pipe_config->port_clock,
2082                                                      pipe_config->lane_count));
2083         }
2084         return true;
2085 }
2086
2087 bool
2088 intel_dp_compute_config(struct intel_encoder *encoder,
2089                         struct intel_crtc_state *pipe_config,
2090                         struct drm_connector_state *conn_state)
2091 {
2092         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2093         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2094         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2095         struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2096         enum port port = encoder->port;
2097         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2098         struct intel_connector *intel_connector = intel_dp->attached_connector;
2099         struct intel_digital_connector_state *intel_conn_state =
2100                 to_intel_digital_connector_state(conn_state);
2101         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2102                                            DP_DPCD_QUIRK_CONSTANT_N);
2103
2104         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2105                 pipe_config->has_pch_encoder = true;
2106
2107         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2108         if (lspcon->active)
2109                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2110
2111         pipe_config->has_drrs = false;
2112         if (IS_G4X(dev_priv) || port == PORT_A)
2113                 pipe_config->has_audio = false;
2114         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2115                 pipe_config->has_audio = intel_dp->has_audio;
2116         else
2117                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2118
2119         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2120                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2121                                        adjusted_mode);
2122
2123                 if (INTEL_GEN(dev_priv) >= 9) {
2124                         int ret;
2125
2126                         ret = skl_update_scaler_crtc(pipe_config);
2127                         if (ret)
2128                                 return ret;
2129                 }
2130
2131                 if (HAS_GMCH_DISPLAY(dev_priv))
2132                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2133                                                  conn_state->scaling_mode);
2134                 else
2135                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2136                                                 conn_state->scaling_mode);
2137         }
2138
2139         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2140                 return false;
2141
2142         if (HAS_GMCH_DISPLAY(dev_priv) &&
2143             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2144                 return false;
2145
2146         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2147                 return false;
2148
2149         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2150                                   intel_dp_supports_fec(intel_dp, pipe_config);
2151
2152         if (!intel_dp_compute_link_config(encoder, pipe_config, conn_state))
2153                 return false;
2154
2155         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2156                 /*
2157                  * See:
2158                  * CEA-861-E - 5.1 Default Encoding Parameters
2159                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2160                  */
2161                 pipe_config->limited_color_range =
2162                         pipe_config->pipe_bpp != 18 &&
2163                         drm_default_rgb_quant_range(adjusted_mode) ==
2164                         HDMI_QUANTIZATION_RANGE_LIMITED;
2165         } else {
2166                 pipe_config->limited_color_range =
2167                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2168         }
2169
2170         if (!pipe_config->dsc_params.compression_enable)
2171                 intel_link_compute_m_n(pipe_config->pipe_bpp,
2172                                        pipe_config->lane_count,
2173                                        adjusted_mode->crtc_clock,
2174                                        pipe_config->port_clock,
2175                                        &pipe_config->dp_m_n,
2176                                        constant_n);
2177         else
2178                 intel_link_compute_m_n(pipe_config->dsc_params.compressed_bpp,
2179                                        pipe_config->lane_count,
2180                                        adjusted_mode->crtc_clock,
2181                                        pipe_config->port_clock,
2182                                        &pipe_config->dp_m_n,
2183                                        constant_n);
2184
2185         if (intel_connector->panel.downclock_mode != NULL &&
2186                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2187                         pipe_config->has_drrs = true;
2188                         intel_link_compute_m_n(pipe_config->pipe_bpp,
2189                                                pipe_config->lane_count,
2190                                                intel_connector->panel.downclock_mode->clock,
2191                                                pipe_config->port_clock,
2192                                                &pipe_config->dp_m2_n2,
2193                                                constant_n);
2194         }
2195
2196         if (!HAS_DDI(dev_priv))
2197                 intel_dp_set_clock(encoder, pipe_config);
2198
2199         intel_psr_compute_config(intel_dp, pipe_config);
2200
2201         return true;
2202 }
2203
2204 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2205                               int link_rate, uint8_t lane_count,
2206                               bool link_mst)
2207 {
2208         intel_dp->link_trained = false;
2209         intel_dp->link_rate = link_rate;
2210         intel_dp->lane_count = lane_count;
2211         intel_dp->link_mst = link_mst;
2212 }
2213
2214 static void intel_dp_prepare(struct intel_encoder *encoder,
2215                              const struct intel_crtc_state *pipe_config)
2216 {
2217         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2218         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2219         enum port port = encoder->port;
2220         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2221         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2222
2223         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2224                                  pipe_config->lane_count,
2225                                  intel_crtc_has_type(pipe_config,
2226                                                      INTEL_OUTPUT_DP_MST));
2227
2228         /*
2229          * There are four kinds of DP registers:
2230          *
2231          *      IBX PCH
2232          *      SNB CPU
2233          *      IVB CPU
2234          *      CPT PCH
2235          *
2236          * IBX PCH and CPU are the same for almost everything,
2237          * except that the CPU DP PLL is configured in this
2238          * register
2239          *
2240          * CPT PCH is quite different, having many bits moved
2241          * to the TRANS_DP_CTL register instead. That
2242          * configuration happens (oddly) in ironlake_pch_enable
2243          */
2244
2245         /* Preserve the BIOS-computed detected bit. This is
2246          * supposed to be read-only.
2247          */
2248         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2249
2250         /* Handle DP bits in common between all three register formats */
2251         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2252         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2253
2254         /* Split out the IBX/CPU vs CPT settings */
2255
2256         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2257                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2258                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2259                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2260                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2261                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2262
2263                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2264                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2265
2266                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2267         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2268                 u32 trans_dp;
2269
2270                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2271
2272                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2273                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2274                         trans_dp |= TRANS_DP_ENH_FRAMING;
2275                 else
2276                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2277                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2278         } else {
2279                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2280                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2281
2282                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2283                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2284                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2285                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2286                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2287
2288                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2289                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2290
2291                 if (IS_CHERRYVIEW(dev_priv))
2292                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2293                 else
2294                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2295         }
2296 }
2297
2298 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2299 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2300
2301 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2302 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2303
2304 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2305 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2306
2307 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2308
2309 static void wait_panel_status(struct intel_dp *intel_dp,
2310                                        u32 mask,
2311                                        u32 value)
2312 {
2313         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2314         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2315
2316         lockdep_assert_held(&dev_priv->pps_mutex);
2317
2318         intel_pps_verify_state(intel_dp);
2319
2320         pp_stat_reg = _pp_stat_reg(intel_dp);
2321         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2322
2323         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2324                         mask, value,
2325                         I915_READ(pp_stat_reg),
2326                         I915_READ(pp_ctrl_reg));
2327
2328         if (intel_wait_for_register(dev_priv,
2329                                     pp_stat_reg, mask, value,
2330                                     5000))
2331                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2332                                 I915_READ(pp_stat_reg),
2333                                 I915_READ(pp_ctrl_reg));
2334
2335         DRM_DEBUG_KMS("Wait complete\n");
2336 }
2337
2338 static void wait_panel_on(struct intel_dp *intel_dp)
2339 {
2340         DRM_DEBUG_KMS("Wait for panel power on\n");
2341         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2342 }
2343
2344 static void wait_panel_off(struct intel_dp *intel_dp)
2345 {
2346         DRM_DEBUG_KMS("Wait for panel power off time\n");
2347         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2348 }
2349
2350 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2351 {
2352         ktime_t panel_power_on_time;
2353         s64 panel_power_off_duration;
2354
2355         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2356
2357         /* take the difference of currrent time and panel power off time
2358          * and then make panel wait for t11_t12 if needed. */
2359         panel_power_on_time = ktime_get_boottime();
2360         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2361
2362         /* When we disable the VDD override bit last we have to do the manual
2363          * wait. */
2364         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2365                 wait_remaining_ms_from_jiffies(jiffies,
2366                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2367
2368         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2369 }
2370
2371 static void wait_backlight_on(struct intel_dp *intel_dp)
2372 {
2373         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2374                                        intel_dp->backlight_on_delay);
2375 }
2376
2377 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2378 {
2379         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2380                                        intel_dp->backlight_off_delay);
2381 }
2382
2383 /* Read the current pp_control value, unlocking the register if it
2384  * is locked
2385  */
2386
2387 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2388 {
2389         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2390         u32 control;
2391
2392         lockdep_assert_held(&dev_priv->pps_mutex);
2393
2394         control = I915_READ(_pp_ctrl_reg(intel_dp));
2395         if (WARN_ON(!HAS_DDI(dev_priv) &&
2396                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2397                 control &= ~PANEL_UNLOCK_MASK;
2398                 control |= PANEL_UNLOCK_REGS;
2399         }
2400         return control;
2401 }
2402
2403 /*
2404  * Must be paired with edp_panel_vdd_off().
2405  * Must hold pps_mutex around the whole on/off sequence.
2406  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2407  */
2408 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2409 {
2410         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2411         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2412         u32 pp;
2413         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2414         bool need_to_disable = !intel_dp->want_panel_vdd;
2415
2416         lockdep_assert_held(&dev_priv->pps_mutex);
2417
2418         if (!intel_dp_is_edp(intel_dp))
2419                 return false;
2420
2421         cancel_delayed_work(&intel_dp->panel_vdd_work);
2422         intel_dp->want_panel_vdd = true;
2423
2424         if (edp_have_panel_vdd(intel_dp))
2425                 return need_to_disable;
2426
2427         intel_display_power_get(dev_priv,
2428                                 intel_aux_power_domain(intel_dig_port));
2429
2430         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2431                       port_name(intel_dig_port->base.port));
2432
2433         if (!edp_have_panel_power(intel_dp))
2434                 wait_panel_power_cycle(intel_dp);
2435
2436         pp = ironlake_get_pp_control(intel_dp);
2437         pp |= EDP_FORCE_VDD;
2438
2439         pp_stat_reg = _pp_stat_reg(intel_dp);
2440         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2441
2442         I915_WRITE(pp_ctrl_reg, pp);
2443         POSTING_READ(pp_ctrl_reg);
2444         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2445                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2446         /*
2447          * If the panel wasn't on, delay before accessing aux channel
2448          */
2449         if (!edp_have_panel_power(intel_dp)) {
2450                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2451                               port_name(intel_dig_port->base.port));
2452                 msleep(intel_dp->panel_power_up_delay);
2453         }
2454
2455         return need_to_disable;
2456 }
2457
2458 /*
2459  * Must be paired with intel_edp_panel_vdd_off() or
2460  * intel_edp_panel_off().
2461  * Nested calls to these functions are not allowed since
2462  * we drop the lock. Caller must use some higher level
2463  * locking to prevent nested calls from other threads.
2464  */
2465 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2466 {
2467         bool vdd;
2468
2469         if (!intel_dp_is_edp(intel_dp))
2470                 return;
2471
2472         pps_lock(intel_dp);
2473         vdd = edp_panel_vdd_on(intel_dp);
2474         pps_unlock(intel_dp);
2475
2476         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2477              port_name(dp_to_dig_port(intel_dp)->base.port));
2478 }
2479
2480 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2481 {
2482         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2483         struct intel_digital_port *intel_dig_port =
2484                 dp_to_dig_port(intel_dp);
2485         u32 pp;
2486         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2487
2488         lockdep_assert_held(&dev_priv->pps_mutex);
2489
2490         WARN_ON(intel_dp->want_panel_vdd);
2491
2492         if (!edp_have_panel_vdd(intel_dp))
2493                 return;
2494
2495         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2496                       port_name(intel_dig_port->base.port));
2497
2498         pp = ironlake_get_pp_control(intel_dp);
2499         pp &= ~EDP_FORCE_VDD;
2500
2501         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2502         pp_stat_reg = _pp_stat_reg(intel_dp);
2503
2504         I915_WRITE(pp_ctrl_reg, pp);
2505         POSTING_READ(pp_ctrl_reg);
2506
2507         /* Make sure sequencer is idle before allowing subsequent activity */
2508         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2509         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2510
2511         if ((pp & PANEL_POWER_ON) == 0)
2512                 intel_dp->panel_power_off_time = ktime_get_boottime();
2513
2514         intel_display_power_put(dev_priv,
2515                                 intel_aux_power_domain(intel_dig_port));
2516 }
2517
2518 static void edp_panel_vdd_work(struct work_struct *__work)
2519 {
2520         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2521                                                  struct intel_dp, panel_vdd_work);
2522
2523         pps_lock(intel_dp);
2524         if (!intel_dp->want_panel_vdd)
2525                 edp_panel_vdd_off_sync(intel_dp);
2526         pps_unlock(intel_dp);
2527 }
2528
2529 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2530 {
2531         unsigned long delay;
2532
2533         /*
2534          * Queue the timer to fire a long time from now (relative to the power
2535          * down delay) to keep the panel power up across a sequence of
2536          * operations.
2537          */
2538         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2539         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2540 }
2541
2542 /*
2543  * Must be paired with edp_panel_vdd_on().
2544  * Must hold pps_mutex around the whole on/off sequence.
2545  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2546  */
2547 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2548 {
2549         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2550
2551         lockdep_assert_held(&dev_priv->pps_mutex);
2552
2553         if (!intel_dp_is_edp(intel_dp))
2554                 return;
2555
2556         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2557              port_name(dp_to_dig_port(intel_dp)->base.port));
2558
2559         intel_dp->want_panel_vdd = false;
2560
2561         if (sync)
2562                 edp_panel_vdd_off_sync(intel_dp);
2563         else
2564                 edp_panel_vdd_schedule_off(intel_dp);
2565 }
2566
2567 static void edp_panel_on(struct intel_dp *intel_dp)
2568 {
2569         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2570         u32 pp;
2571         i915_reg_t pp_ctrl_reg;
2572
2573         lockdep_assert_held(&dev_priv->pps_mutex);
2574
2575         if (!intel_dp_is_edp(intel_dp))
2576                 return;
2577
2578         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2579                       port_name(dp_to_dig_port(intel_dp)->base.port));
2580
2581         if (WARN(edp_have_panel_power(intel_dp),
2582                  "eDP port %c panel power already on\n",
2583                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2584                 return;
2585
2586         wait_panel_power_cycle(intel_dp);
2587
2588         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2589         pp = ironlake_get_pp_control(intel_dp);
2590         if (IS_GEN5(dev_priv)) {
2591                 /* ILK workaround: disable reset around power sequence */
2592                 pp &= ~PANEL_POWER_RESET;
2593                 I915_WRITE(pp_ctrl_reg, pp);
2594                 POSTING_READ(pp_ctrl_reg);
2595         }
2596
2597         pp |= PANEL_POWER_ON;
2598         if (!IS_GEN5(dev_priv))
2599                 pp |= PANEL_POWER_RESET;
2600
2601         I915_WRITE(pp_ctrl_reg, pp);
2602         POSTING_READ(pp_ctrl_reg);
2603
2604         wait_panel_on(intel_dp);
2605         intel_dp->last_power_on = jiffies;
2606
2607         if (IS_GEN5(dev_priv)) {
2608                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2609                 I915_WRITE(pp_ctrl_reg, pp);
2610                 POSTING_READ(pp_ctrl_reg);
2611         }
2612 }
2613
2614 void intel_edp_panel_on(struct intel_dp *intel_dp)
2615 {
2616         if (!intel_dp_is_edp(intel_dp))
2617                 return;
2618
2619         pps_lock(intel_dp);
2620         edp_panel_on(intel_dp);
2621         pps_unlock(intel_dp);
2622 }
2623
2624
2625 static void edp_panel_off(struct intel_dp *intel_dp)
2626 {
2627         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2628         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2629         u32 pp;
2630         i915_reg_t pp_ctrl_reg;
2631
2632         lockdep_assert_held(&dev_priv->pps_mutex);
2633
2634         if (!intel_dp_is_edp(intel_dp))
2635                 return;
2636
2637         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2638                       port_name(dig_port->base.port));
2639
2640         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2641              port_name(dig_port->base.port));
2642
2643         pp = ironlake_get_pp_control(intel_dp);
2644         /* We need to switch off panel power _and_ force vdd, for otherwise some
2645          * panels get very unhappy and cease to work. */
2646         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2647                 EDP_BLC_ENABLE);
2648
2649         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2650
2651         intel_dp->want_panel_vdd = false;
2652
2653         I915_WRITE(pp_ctrl_reg, pp);
2654         POSTING_READ(pp_ctrl_reg);
2655
2656         wait_panel_off(intel_dp);
2657         intel_dp->panel_power_off_time = ktime_get_boottime();
2658
2659         /* We got a reference when we enabled the VDD. */
2660         intel_display_power_put(dev_priv, intel_aux_power_domain(dig_port));
2661 }
2662
2663 void intel_edp_panel_off(struct intel_dp *intel_dp)
2664 {
2665         if (!intel_dp_is_edp(intel_dp))
2666                 return;
2667
2668         pps_lock(intel_dp);
2669         edp_panel_off(intel_dp);
2670         pps_unlock(intel_dp);
2671 }
2672
2673 /* Enable backlight in the panel power control. */
2674 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2675 {
2676         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2677         u32 pp;
2678         i915_reg_t pp_ctrl_reg;
2679
2680         /*
2681          * If we enable the backlight right away following a panel power
2682          * on, we may see slight flicker as the panel syncs with the eDP
2683          * link.  So delay a bit to make sure the image is solid before
2684          * allowing it to appear.
2685          */
2686         wait_backlight_on(intel_dp);
2687
2688         pps_lock(intel_dp);
2689
2690         pp = ironlake_get_pp_control(intel_dp);
2691         pp |= EDP_BLC_ENABLE;
2692
2693         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2694
2695         I915_WRITE(pp_ctrl_reg, pp);
2696         POSTING_READ(pp_ctrl_reg);
2697
2698         pps_unlock(intel_dp);
2699 }
2700
2701 /* Enable backlight PWM and backlight PP control. */
2702 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2703                             const struct drm_connector_state *conn_state)
2704 {
2705         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2706
2707         if (!intel_dp_is_edp(intel_dp))
2708                 return;
2709
2710         DRM_DEBUG_KMS("\n");
2711
2712         intel_panel_enable_backlight(crtc_state, conn_state);
2713         _intel_edp_backlight_on(intel_dp);
2714 }
2715
2716 /* Disable backlight in the panel power control. */
2717 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2718 {
2719         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2720         u32 pp;
2721         i915_reg_t pp_ctrl_reg;
2722
2723         if (!intel_dp_is_edp(intel_dp))
2724                 return;
2725
2726         pps_lock(intel_dp);
2727
2728         pp = ironlake_get_pp_control(intel_dp);
2729         pp &= ~EDP_BLC_ENABLE;
2730
2731         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2732
2733         I915_WRITE(pp_ctrl_reg, pp);
2734         POSTING_READ(pp_ctrl_reg);
2735
2736         pps_unlock(intel_dp);
2737
2738         intel_dp->last_backlight_off = jiffies;
2739         edp_wait_backlight_off(intel_dp);
2740 }
2741
2742 /* Disable backlight PP control and backlight PWM. */
2743 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2744 {
2745         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2746
2747         if (!intel_dp_is_edp(intel_dp))
2748                 return;
2749
2750         DRM_DEBUG_KMS("\n");
2751
2752         _intel_edp_backlight_off(intel_dp);
2753         intel_panel_disable_backlight(old_conn_state);
2754 }
2755
2756 /*
2757  * Hook for controlling the panel power control backlight through the bl_power
2758  * sysfs attribute. Take care to handle multiple calls.
2759  */
2760 static void intel_edp_backlight_power(struct intel_connector *connector,
2761                                       bool enable)
2762 {
2763         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2764         bool is_enabled;
2765
2766         pps_lock(intel_dp);
2767         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2768         pps_unlock(intel_dp);
2769
2770         if (is_enabled == enable)
2771                 return;
2772
2773         DRM_DEBUG_KMS("panel power control backlight %s\n",
2774                       enable ? "enable" : "disable");
2775
2776         if (enable)
2777                 _intel_edp_backlight_on(intel_dp);
2778         else
2779                 _intel_edp_backlight_off(intel_dp);
2780 }
2781
2782 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2783 {
2784         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2785         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2786         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2787
2788         I915_STATE_WARN(cur_state != state,
2789                         "DP port %c state assertion failure (expected %s, current %s)\n",
2790                         port_name(dig_port->base.port),
2791                         onoff(state), onoff(cur_state));
2792 }
2793 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2794
2795 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2796 {
2797         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2798
2799         I915_STATE_WARN(cur_state != state,
2800                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2801                         onoff(state), onoff(cur_state));
2802 }
2803 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2804 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2805
2806 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2807                                 const struct intel_crtc_state *pipe_config)
2808 {
2809         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2810         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2811
2812         assert_pipe_disabled(dev_priv, crtc->pipe);
2813         assert_dp_port_disabled(intel_dp);
2814         assert_edp_pll_disabled(dev_priv);
2815
2816         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2817                       pipe_config->port_clock);
2818
2819         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2820
2821         if (pipe_config->port_clock == 162000)
2822                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2823         else
2824                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2825
2826         I915_WRITE(DP_A, intel_dp->DP);
2827         POSTING_READ(DP_A);
2828         udelay(500);
2829
2830         /*
2831          * [DevILK] Work around required when enabling DP PLL
2832          * while a pipe is enabled going to FDI:
2833          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2834          * 2. Program DP PLL enable
2835          */
2836         if (IS_GEN5(dev_priv))
2837                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2838
2839         intel_dp->DP |= DP_PLL_ENABLE;
2840
2841         I915_WRITE(DP_A, intel_dp->DP);
2842         POSTING_READ(DP_A);
2843         udelay(200);
2844 }
2845
2846 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2847                                  const struct intel_crtc_state *old_crtc_state)
2848 {
2849         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2850         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2851
2852         assert_pipe_disabled(dev_priv, crtc->pipe);
2853         assert_dp_port_disabled(intel_dp);
2854         assert_edp_pll_enabled(dev_priv);
2855
2856         DRM_DEBUG_KMS("disabling eDP PLL\n");
2857
2858         intel_dp->DP &= ~DP_PLL_ENABLE;
2859
2860         I915_WRITE(DP_A, intel_dp->DP);
2861         POSTING_READ(DP_A);
2862         udelay(200);
2863 }
2864
2865 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2866 {
2867         /*
2868          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2869          * be capable of signalling downstream hpd with a long pulse.
2870          * Whether or not that means D3 is safe to use is not clear,
2871          * but let's assume so until proven otherwise.
2872          *
2873          * FIXME should really check all downstream ports...
2874          */
2875         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2876                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2877                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2878 }
2879
2880 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2881                                            const struct intel_crtc_state *crtc_state,
2882                                            bool enable)
2883 {
2884         int ret;
2885
2886         if (!crtc_state->dsc_params.compression_enable)
2887                 return;
2888
2889         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2890                                  enable ? DP_DECOMPRESSION_EN : 0);
2891         if (ret < 0)
2892                 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
2893                               enable ? "enable" : "disable");
2894 }
2895
2896 /* If the sink supports it, try to set the power state appropriately */
2897 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2898 {
2899         int ret, i;
2900
2901         /* Should have a valid DPCD by this point */
2902         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2903                 return;
2904
2905         if (mode != DRM_MODE_DPMS_ON) {
2906                 if (downstream_hpd_needs_d0(intel_dp))
2907                         return;
2908
2909                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2910                                          DP_SET_POWER_D3);
2911         } else {
2912                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2913
2914                 /*
2915                  * When turning on, we need to retry for 1ms to give the sink
2916                  * time to wake up.
2917                  */
2918                 for (i = 0; i < 3; i++) {
2919                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2920                                                  DP_SET_POWER_D0);
2921                         if (ret == 1)
2922                                 break;
2923                         msleep(1);
2924                 }
2925
2926                 if (ret == 1 && lspcon->active)
2927                         lspcon_wait_pcon_mode(lspcon);
2928         }
2929
2930         if (ret != 1)
2931                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2932                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2933 }
2934
2935 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2936                                  enum port port, enum pipe *pipe)
2937 {
2938         enum pipe p;
2939
2940         for_each_pipe(dev_priv, p) {
2941                 u32 val = I915_READ(TRANS_DP_CTL(p));
2942
2943                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2944                         *pipe = p;
2945                         return true;
2946                 }
2947         }
2948
2949         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2950
2951         /* must initialize pipe to something for the asserts */
2952         *pipe = PIPE_A;
2953
2954         return false;
2955 }
2956
2957 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2958                            i915_reg_t dp_reg, enum port port,
2959                            enum pipe *pipe)
2960 {
2961         bool ret;
2962         u32 val;
2963
2964         val = I915_READ(dp_reg);
2965
2966         ret = val & DP_PORT_EN;
2967
2968         /* asserts want to know the pipe even if the port is disabled */
2969         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2970                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2971         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2972                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2973         else if (IS_CHERRYVIEW(dev_priv))
2974                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2975         else
2976                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2977
2978         return ret;
2979 }
2980
2981 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2982                                   enum pipe *pipe)
2983 {
2984         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2985         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2986         bool ret;
2987
2988         if (!intel_display_power_get_if_enabled(dev_priv,
2989                                                 encoder->power_domain))
2990                 return false;
2991
2992         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
2993                                     encoder->port, pipe);
2994
2995         intel_display_power_put(dev_priv, encoder->power_domain);
2996
2997         return ret;
2998 }
2999
3000 static void intel_dp_get_config(struct intel_encoder *encoder,
3001                                 struct intel_crtc_state *pipe_config)
3002 {
3003         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3004         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3005         u32 tmp, flags = 0;
3006         enum port port = encoder->port;
3007         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3008
3009         if (encoder->type == INTEL_OUTPUT_EDP)
3010                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3011         else
3012                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3013
3014         tmp = I915_READ(intel_dp->output_reg);
3015
3016         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3017
3018         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3019                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3020
3021                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3022                         flags |= DRM_MODE_FLAG_PHSYNC;
3023                 else
3024                         flags |= DRM_MODE_FLAG_NHSYNC;
3025
3026                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3027                         flags |= DRM_MODE_FLAG_PVSYNC;
3028                 else
3029                         flags |= DRM_MODE_FLAG_NVSYNC;
3030         } else {
3031                 if (tmp & DP_SYNC_HS_HIGH)
3032                         flags |= DRM_MODE_FLAG_PHSYNC;
3033                 else
3034                         flags |= DRM_MODE_FLAG_NHSYNC;
3035
3036                 if (tmp & DP_SYNC_VS_HIGH)
3037                         flags |= DRM_MODE_FLAG_PVSYNC;
3038                 else
3039                         flags |= DRM_MODE_FLAG_NVSYNC;
3040         }
3041
3042         pipe_config->base.adjusted_mode.flags |= flags;
3043
3044         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3045                 pipe_config->limited_color_range = true;
3046
3047         pipe_config->lane_count =
3048                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3049
3050         intel_dp_get_m_n(crtc, pipe_config);
3051
3052         if (port == PORT_A) {
3053                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3054                         pipe_config->port_clock = 162000;
3055                 else
3056                         pipe_config->port_clock = 270000;
3057         }
3058
3059         pipe_config->base.adjusted_mode.crtc_clock =
3060                 intel_dotclock_calculate(pipe_config->port_clock,
3061                                          &pipe_config->dp_m_n);
3062
3063         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3064             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3065                 /*
3066                  * This is a big fat ugly hack.
3067                  *
3068                  * Some machines in UEFI boot mode provide us a VBT that has 18
3069                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3070                  * unknown we fail to light up. Yet the same BIOS boots up with
3071                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3072                  * max, not what it tells us to use.
3073                  *
3074                  * Note: This will still be broken if the eDP panel is not lit
3075                  * up by the BIOS, and thus we can't get the mode at module
3076                  * load.
3077                  */
3078                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3079                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3080                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3081         }
3082 }
3083
3084 static void intel_disable_dp(struct intel_encoder *encoder,
3085                              const struct intel_crtc_state *old_crtc_state,
3086                              const struct drm_connector_state *old_conn_state)
3087 {
3088         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3089
3090         intel_dp->link_trained = false;
3091
3092         if (old_crtc_state->has_audio)
3093                 intel_audio_codec_disable(encoder,
3094                                           old_crtc_state, old_conn_state);
3095
3096         /* Make sure the panel is off before trying to change the mode. But also
3097          * ensure that we have vdd while we switch off the panel. */
3098         intel_edp_panel_vdd_on(intel_dp);
3099         intel_edp_backlight_off(old_conn_state);
3100         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3101         intel_edp_panel_off(intel_dp);
3102 }
3103
3104 static void g4x_disable_dp(struct intel_encoder *encoder,
3105                            const struct intel_crtc_state *old_crtc_state,
3106                            const struct drm_connector_state *old_conn_state)
3107 {
3108         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3109 }
3110
3111 static void vlv_disable_dp(struct intel_encoder *encoder,
3112                            const struct intel_crtc_state *old_crtc_state,
3113                            const struct drm_connector_state *old_conn_state)
3114 {
3115         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3116 }
3117
3118 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3119                                 const struct intel_crtc_state *old_crtc_state,
3120                                 const struct drm_connector_state *old_conn_state)
3121 {
3122         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3123         enum port port = encoder->port;
3124
3125         /*
3126          * Bspec does not list a specific disable sequence for g4x DP.
3127          * Follow the ilk+ sequence (disable pipe before the port) for
3128          * g4x DP as it does not suffer from underruns like the normal
3129          * g4x modeset sequence (disable pipe after the port).
3130          */
3131         intel_dp_link_down(encoder, old_crtc_state);
3132
3133         /* Only ilk+ has port A */
3134         if (port == PORT_A)
3135                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3136 }
3137
3138 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3139                                 const struct intel_crtc_state *old_crtc_state,
3140                                 const struct drm_connector_state *old_conn_state)
3141 {
3142         intel_dp_link_down(encoder, old_crtc_state);
3143 }
3144
3145 static void chv_post_disable_dp(struct intel_encoder *encoder,
3146                                 const struct intel_crtc_state *old_crtc_state,
3147                                 const struct drm_connector_state *old_conn_state)
3148 {
3149         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3150
3151         intel_dp_link_down(encoder, old_crtc_state);
3152
3153         mutex_lock(&dev_priv->sb_lock);
3154
3155         /* Assert data lane reset */
3156         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3157
3158         mutex_unlock(&dev_priv->sb_lock);
3159 }
3160
3161 static void
3162 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3163                          uint32_t *DP,
3164                          uint8_t dp_train_pat)
3165 {
3166         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3167         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3168         enum port port = intel_dig_port->base.port;
3169         uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3170
3171         if (dp_train_pat & train_pat_mask)
3172                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3173                               dp_train_pat & train_pat_mask);
3174
3175         if (HAS_DDI(dev_priv)) {
3176                 uint32_t temp = I915_READ(DP_TP_CTL(port));
3177
3178                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3179                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3180                 else
3181                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3182
3183                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3184                 switch (dp_train_pat & train_pat_mask) {
3185                 case DP_TRAINING_PATTERN_DISABLE:
3186                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3187
3188                         break;
3189                 case DP_TRAINING_PATTERN_1:
3190                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3191                         break;
3192                 case DP_TRAINING_PATTERN_2:
3193                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3194                         break;
3195                 case DP_TRAINING_PATTERN_3:
3196                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3197                         break;
3198                 case DP_TRAINING_PATTERN_4:
3199                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3200                         break;
3201                 }
3202                 I915_WRITE(DP_TP_CTL(port), temp);
3203
3204         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3205                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3206                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3207
3208                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3209                 case DP_TRAINING_PATTERN_DISABLE:
3210                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3211                         break;
3212                 case DP_TRAINING_PATTERN_1:
3213                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3214                         break;
3215                 case DP_TRAINING_PATTERN_2:
3216                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3217                         break;
3218                 case DP_TRAINING_PATTERN_3:
3219                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3220                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3221                         break;
3222                 }
3223
3224         } else {
3225                 *DP &= ~DP_LINK_TRAIN_MASK;
3226
3227                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3228                 case DP_TRAINING_PATTERN_DISABLE:
3229                         *DP |= DP_LINK_TRAIN_OFF;
3230                         break;
3231                 case DP_TRAINING_PATTERN_1:
3232                         *DP |= DP_LINK_TRAIN_PAT_1;
3233                         break;
3234                 case DP_TRAINING_PATTERN_2:
3235                         *DP |= DP_LINK_TRAIN_PAT_2;
3236                         break;
3237                 case DP_TRAINING_PATTERN_3:
3238                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3239                         *DP |= DP_LINK_TRAIN_PAT_2;
3240                         break;
3241                 }
3242         }
3243 }
3244
3245 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3246                                  const struct intel_crtc_state *old_crtc_state)
3247 {
3248         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3249
3250         /* enable with pattern 1 (as per spec) */
3251
3252         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3253
3254         /*
3255          * Magic for VLV/CHV. We _must_ first set up the register
3256          * without actually enabling the port, and then do another
3257          * write to enable the port. Otherwise link training will
3258          * fail when the power sequencer is freshly used for this port.
3259          */
3260         intel_dp->DP |= DP_PORT_EN;
3261         if (old_crtc_state->has_audio)
3262                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3263
3264         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3265         POSTING_READ(intel_dp->output_reg);
3266 }
3267
3268 static void intel_enable_dp(struct intel_encoder *encoder,
3269                             const struct intel_crtc_state *pipe_config,
3270                             const struct drm_connector_state *conn_state)
3271 {
3272         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3273         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3274         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3275         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
3276         enum pipe pipe = crtc->pipe;
3277
3278         if (WARN_ON(dp_reg & DP_PORT_EN))
3279                 return;
3280
3281         pps_lock(intel_dp);
3282
3283         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3284                 vlv_init_panel_power_sequencer(encoder, pipe_config);
3285
3286         intel_dp_enable_port(intel_dp, pipe_config);
3287
3288         edp_panel_vdd_on(intel_dp);
3289         edp_panel_on(intel_dp);
3290         edp_panel_vdd_off(intel_dp, true);
3291
3292         pps_unlock(intel_dp);
3293
3294         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3295                 unsigned int lane_mask = 0x0;
3296
3297                 if (IS_CHERRYVIEW(dev_priv))
3298                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3299
3300                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3301                                     lane_mask);
3302         }
3303
3304         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3305         intel_dp_start_link_train(intel_dp);
3306         intel_dp_stop_link_train(intel_dp);
3307
3308         if (pipe_config->has_audio) {
3309                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3310                                  pipe_name(pipe));
3311                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3312         }
3313 }
3314
3315 static void g4x_enable_dp(struct intel_encoder *encoder,
3316                           const struct intel_crtc_state *pipe_config,
3317                           const struct drm_connector_state *conn_state)
3318 {
3319         intel_enable_dp(encoder, pipe_config, conn_state);
3320         intel_edp_backlight_on(pipe_config, conn_state);
3321 }
3322
3323 static void vlv_enable_dp(struct intel_encoder *encoder,
3324                           const struct intel_crtc_state *pipe_config,
3325                           const struct drm_connector_state *conn_state)
3326 {
3327         intel_edp_backlight_on(pipe_config, conn_state);
3328 }
3329
3330 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3331                               const struct intel_crtc_state *pipe_config,
3332                               const struct drm_connector_state *conn_state)
3333 {
3334         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3335         enum port port = encoder->port;
3336
3337         intel_dp_prepare(encoder, pipe_config);
3338
3339         /* Only ilk+ has port A */
3340         if (port == PORT_A)
3341                 ironlake_edp_pll_on(intel_dp, pipe_config);
3342 }
3343
3344 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3345 {
3346         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3347         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3348         enum pipe pipe = intel_dp->pps_pipe;
3349         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3350
3351         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3352
3353         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3354                 return;
3355
3356         edp_panel_vdd_off_sync(intel_dp);
3357
3358         /*
3359          * VLV seems to get confused when multiple power sequencers
3360          * have the same port selected (even if only one has power/vdd
3361          * enabled). The failure manifests as vlv_wait_port_ready() failing
3362          * CHV on the other hand doesn't seem to mind having the same port
3363          * selected in multiple power sequencers, but let's clear the
3364          * port select always when logically disconnecting a power sequencer
3365          * from a port.
3366          */
3367         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3368                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3369         I915_WRITE(pp_on_reg, 0);
3370         POSTING_READ(pp_on_reg);
3371
3372         intel_dp->pps_pipe = INVALID_PIPE;
3373 }
3374
3375 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3376                                       enum pipe pipe)
3377 {
3378         struct intel_encoder *encoder;
3379
3380         lockdep_assert_held(&dev_priv->pps_mutex);
3381
3382         for_each_intel_dp(&dev_priv->drm, encoder) {
3383                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3384                 enum port port = encoder->port;
3385
3386                 WARN(intel_dp->active_pipe == pipe,
3387                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3388                      pipe_name(pipe), port_name(port));
3389
3390                 if (intel_dp->pps_pipe != pipe)
3391                         continue;
3392
3393                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3394                               pipe_name(pipe), port_name(port));
3395
3396                 /* make sure vdd is off before we steal it */
3397                 vlv_detach_power_sequencer(intel_dp);
3398         }
3399 }
3400
3401 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3402                                            const struct intel_crtc_state *crtc_state)
3403 {
3404         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3405         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3406         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3407
3408         lockdep_assert_held(&dev_priv->pps_mutex);
3409
3410         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3411
3412         if (intel_dp->pps_pipe != INVALID_PIPE &&
3413             intel_dp->pps_pipe != crtc->pipe) {
3414                 /*
3415                  * If another power sequencer was being used on this
3416                  * port previously make sure to turn off vdd there while
3417                  * we still have control of it.
3418                  */
3419                 vlv_detach_power_sequencer(intel_dp);
3420         }
3421
3422         /*
3423          * We may be stealing the power
3424          * sequencer from another port.
3425          */
3426         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3427
3428         intel_dp->active_pipe = crtc->pipe;
3429
3430         if (!intel_dp_is_edp(intel_dp))
3431                 return;
3432
3433         /* now it's all ours */
3434         intel_dp->pps_pipe = crtc->pipe;
3435
3436         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3437                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3438
3439         /* init power sequencer on this pipe and port */
3440         intel_dp_init_panel_power_sequencer(intel_dp);
3441         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3442 }
3443
3444 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3445                               const struct intel_crtc_state *pipe_config,
3446                               const struct drm_connector_state *conn_state)
3447 {
3448         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3449
3450         intel_enable_dp(encoder, pipe_config, conn_state);
3451 }
3452
3453 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3454                                   const struct intel_crtc_state *pipe_config,
3455                                   const struct drm_connector_state *conn_state)
3456 {
3457         intel_dp_prepare(encoder, pipe_config);
3458
3459         vlv_phy_pre_pll_enable(encoder, pipe_config);
3460 }
3461
3462 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3463                               const struct intel_crtc_state *pipe_config,
3464                               const struct drm_connector_state *conn_state)
3465 {
3466         chv_phy_pre_encoder_enable(encoder, pipe_config);
3467
3468         intel_enable_dp(encoder, pipe_config, conn_state);
3469
3470         /* Second common lane will stay alive on its own now */
3471         chv_phy_release_cl2_override(encoder);
3472 }
3473
3474 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3475                                   const struct intel_crtc_state *pipe_config,
3476                                   const struct drm_connector_state *conn_state)
3477 {
3478         intel_dp_prepare(encoder, pipe_config);
3479
3480         chv_phy_pre_pll_enable(encoder, pipe_config);
3481 }
3482
3483 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3484                                     const struct intel_crtc_state *old_crtc_state,
3485                                     const struct drm_connector_state *old_conn_state)
3486 {
3487         chv_phy_post_pll_disable(encoder, old_crtc_state);
3488 }
3489
3490 /*
3491  * Fetch AUX CH registers 0x202 - 0x207 which contain
3492  * link status information
3493  */
3494 bool
3495 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3496 {
3497         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3498                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3499 }
3500
3501 /* These are source-specific values. */
3502 uint8_t
3503 intel_dp_voltage_max(struct intel_dp *intel_dp)
3504 {
3505         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3506         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3507         enum port port = encoder->port;
3508
3509         if (HAS_DDI(dev_priv))
3510                 return intel_ddi_dp_voltage_max(encoder);
3511         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3512                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3513         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3514                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3515         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3516                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3517         else
3518                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3519 }
3520
3521 uint8_t
3522 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3523 {
3524         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3525         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3526         enum port port = encoder->port;
3527
3528         if (HAS_DDI(dev_priv)) {
3529                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3530         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3531                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3532                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3533                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3534                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3535                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3536                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3537                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3538                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3539                 default:
3540                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3541                 }
3542         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3543                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3544                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3545                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3546                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3547                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3548                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3549                 default:
3550                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3551                 }
3552         } else {
3553                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3554                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3555                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3556                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3557                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3558                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3559                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3560                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3561                 default:
3562                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3563                 }
3564         }
3565 }
3566
3567 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3568 {
3569         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3570         unsigned long demph_reg_value, preemph_reg_value,
3571                 uniqtranscale_reg_value;
3572         uint8_t train_set = intel_dp->train_set[0];
3573
3574         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3575         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3576                 preemph_reg_value = 0x0004000;
3577                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3578                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3579                         demph_reg_value = 0x2B405555;
3580                         uniqtranscale_reg_value = 0x552AB83A;
3581                         break;
3582                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3583                         demph_reg_value = 0x2B404040;
3584                         uniqtranscale_reg_value = 0x5548B83A;
3585                         break;
3586                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3587                         demph_reg_value = 0x2B245555;
3588                         uniqtranscale_reg_value = 0x5560B83A;
3589                         break;
3590                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3591                         demph_reg_value = 0x2B405555;
3592                         uniqtranscale_reg_value = 0x5598DA3A;
3593                         break;
3594                 default:
3595                         return 0;
3596                 }
3597                 break;
3598         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3599                 preemph_reg_value = 0x0002000;
3600                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3601                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3602                         demph_reg_value = 0x2B404040;
3603                         uniqtranscale_reg_value = 0x5552B83A;
3604                         break;
3605                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3606                         demph_reg_value = 0x2B404848;
3607                         uniqtranscale_reg_value = 0x5580B83A;
3608                         break;
3609                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3610                         demph_reg_value = 0x2B404040;
3611                         uniqtranscale_reg_value = 0x55ADDA3A;
3612                         break;
3613                 default:
3614                         return 0;
3615                 }
3616                 break;
3617         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3618                 preemph_reg_value = 0x0000000;
3619                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3620                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3621                         demph_reg_value = 0x2B305555;
3622                         uniqtranscale_reg_value = 0x5570B83A;
3623                         break;
3624                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3625                         demph_reg_value = 0x2B2B4040;
3626                         uniqtranscale_reg_value = 0x55ADDA3A;
3627                         break;
3628                 default:
3629                         return 0;
3630                 }
3631                 break;
3632         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3633                 preemph_reg_value = 0x0006000;
3634                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3635                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3636                         demph_reg_value = 0x1B405555;
3637                         uniqtranscale_reg_value = 0x55ADDA3A;
3638                         break;
3639                 default:
3640                         return 0;
3641                 }
3642                 break;
3643         default:
3644                 return 0;
3645         }
3646
3647         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3648                                  uniqtranscale_reg_value, 0);
3649
3650         return 0;
3651 }
3652
3653 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3654 {
3655         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3656         u32 deemph_reg_value, margin_reg_value;
3657         bool uniq_trans_scale = false;
3658         uint8_t train_set = intel_dp->train_set[0];
3659
3660         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3661         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3662                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3663                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3664                         deemph_reg_value = 128;
3665                         margin_reg_value = 52;
3666                         break;
3667                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3668                         deemph_reg_value = 128;
3669                         margin_reg_value = 77;
3670                         break;
3671                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3672                         deemph_reg_value = 128;
3673                         margin_reg_value = 102;
3674                         break;
3675                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3676                         deemph_reg_value = 128;
3677                         margin_reg_value = 154;
3678                         uniq_trans_scale = true;
3679                         break;
3680                 default:
3681                         return 0;
3682                 }
3683                 break;
3684         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3685                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3686                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3687                         deemph_reg_value = 85;
3688                         margin_reg_value = 78;
3689                         break;
3690                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3691                         deemph_reg_value = 85;
3692                         margin_reg_value = 116;
3693                         break;
3694                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3695                         deemph_reg_value = 85;
3696                         margin_reg_value = 154;
3697                         break;
3698                 default:
3699                         return 0;
3700                 }
3701                 break;
3702         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3703                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3704                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3705                         deemph_reg_value = 64;
3706                         margin_reg_value = 104;
3707                         break;
3708                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3709                         deemph_reg_value = 64;
3710                         margin_reg_value = 154;
3711                         break;
3712                 default:
3713                         return 0;
3714                 }
3715                 break;
3716         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3717                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3718                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3719                         deemph_reg_value = 43;
3720                         margin_reg_value = 154;
3721                         break;
3722                 default:
3723                         return 0;
3724                 }
3725                 break;
3726         default:
3727                 return 0;
3728         }
3729
3730         chv_set_phy_signal_level(encoder, deemph_reg_value,
3731                                  margin_reg_value, uniq_trans_scale);
3732
3733         return 0;
3734 }
3735
3736 static uint32_t
3737 g4x_signal_levels(uint8_t train_set)
3738 {
3739         uint32_t        signal_levels = 0;
3740
3741         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3742         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3743         default:
3744                 signal_levels |= DP_VOLTAGE_0_4;
3745                 break;
3746         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3747                 signal_levels |= DP_VOLTAGE_0_6;
3748                 break;
3749         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3750                 signal_levels |= DP_VOLTAGE_0_8;
3751                 break;
3752         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3753                 signal_levels |= DP_VOLTAGE_1_2;
3754                 break;
3755         }
3756         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3757         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3758         default:
3759                 signal_levels |= DP_PRE_EMPHASIS_0;
3760                 break;
3761         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3762                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3763                 break;
3764         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3765                 signal_levels |= DP_PRE_EMPHASIS_6;
3766                 break;
3767         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3768                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3769                 break;
3770         }
3771         return signal_levels;
3772 }
3773
3774 /* SNB CPU eDP voltage swing and pre-emphasis control */
3775 static uint32_t
3776 snb_cpu_edp_signal_levels(uint8_t train_set)
3777 {
3778         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3779                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3780         switch (signal_levels) {
3781         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3782         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3783                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3784         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3785                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3786         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3787         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3788                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3789         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3790         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3791                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3792         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3793         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3794                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3795         default:
3796                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3797                               "0x%x\n", signal_levels);
3798                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3799         }
3800 }
3801
3802 /* IVB CPU eDP voltage swing and pre-emphasis control */
3803 static uint32_t
3804 ivb_cpu_edp_signal_levels(uint8_t train_set)
3805 {
3806         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3807                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3808         switch (signal_levels) {
3809         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3810                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3811         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3812                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3813         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3814                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3815
3816         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3817                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3818         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3819                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3820
3821         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3822                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3823         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3824                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3825
3826         default:
3827                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3828                               "0x%x\n", signal_levels);
3829                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3830         }
3831 }
3832
3833 void
3834 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3835 {
3836         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3837         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3838         enum port port = intel_dig_port->base.port;
3839         uint32_t signal_levels, mask = 0;
3840         uint8_t train_set = intel_dp->train_set[0];
3841
3842         if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
3843                 signal_levels = bxt_signal_levels(intel_dp);
3844         } else if (HAS_DDI(dev_priv)) {
3845                 signal_levels = ddi_signal_levels(intel_dp);
3846                 mask = DDI_BUF_EMP_MASK;
3847         } else if (IS_CHERRYVIEW(dev_priv)) {
3848                 signal_levels = chv_signal_levels(intel_dp);
3849         } else if (IS_VALLEYVIEW(dev_priv)) {
3850                 signal_levels = vlv_signal_levels(intel_dp);
3851         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3852                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3853                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3854         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3855                 signal_levels = snb_cpu_edp_signal_levels(train_set);
3856                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3857         } else {
3858                 signal_levels = g4x_signal_levels(train_set);
3859                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3860         }
3861
3862         if (mask)
3863                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3864
3865         DRM_DEBUG_KMS("Using vswing level %d\n",
3866                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3867         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3868                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3869                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3870
3871         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3872
3873         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3874         POSTING_READ(intel_dp->output_reg);
3875 }
3876
3877 void
3878 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3879                                        uint8_t dp_train_pat)
3880 {
3881         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3882         struct drm_i915_private *dev_priv =
3883                 to_i915(intel_dig_port->base.base.dev);
3884
3885         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3886
3887         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3888         POSTING_READ(intel_dp->output_reg);
3889 }
3890
3891 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3892 {
3893         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3894         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3895         enum port port = intel_dig_port->base.port;
3896         uint32_t val;
3897
3898         if (!HAS_DDI(dev_priv))
3899                 return;
3900
3901         val = I915_READ(DP_TP_CTL(port));
3902         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3903         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3904         I915_WRITE(DP_TP_CTL(port), val);
3905
3906         /*
3907          * On PORT_A we can have only eDP in SST mode. There the only reason
3908          * we need to set idle transmission mode is to work around a HW issue
3909          * where we enable the pipe while not in idle link-training mode.
3910          * In this case there is requirement to wait for a minimum number of
3911          * idle patterns to be sent.
3912          */
3913         if (port == PORT_A)
3914                 return;
3915
3916         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3917                                     DP_TP_STATUS_IDLE_DONE,
3918                                     DP_TP_STATUS_IDLE_DONE,
3919                                     1))
3920                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3921 }
3922
3923 static void
3924 intel_dp_link_down(struct intel_encoder *encoder,
3925                    const struct intel_crtc_state *old_crtc_state)
3926 {
3927         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3928         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3929         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3930         enum port port = encoder->port;
3931         uint32_t DP = intel_dp->DP;
3932
3933         if (WARN_ON(HAS_DDI(dev_priv)))
3934                 return;
3935
3936         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3937                 return;
3938
3939         DRM_DEBUG_KMS("\n");
3940
3941         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3942             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3943                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3944                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3945         } else {
3946                 DP &= ~DP_LINK_TRAIN_MASK;
3947                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3948         }
3949         I915_WRITE(intel_dp->output_reg, DP);
3950         POSTING_READ(intel_dp->output_reg);
3951
3952         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3953         I915_WRITE(intel_dp->output_reg, DP);
3954         POSTING_READ(intel_dp->output_reg);
3955
3956         /*
3957          * HW workaround for IBX, we need to move the port
3958          * to transcoder A after disabling it to allow the
3959          * matching HDMI port to be enabled on transcoder A.
3960          */
3961         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3962                 /*
3963                  * We get CPU/PCH FIFO underruns on the other pipe when
3964                  * doing the workaround. Sweep them under the rug.
3965                  */
3966                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3967                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3968
3969                 /* always enable with pattern 1 (as per spec) */
3970                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
3971                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
3972                         DP_LINK_TRAIN_PAT_1;
3973                 I915_WRITE(intel_dp->output_reg, DP);
3974                 POSTING_READ(intel_dp->output_reg);
3975
3976                 DP &= ~DP_PORT_EN;
3977                 I915_WRITE(intel_dp->output_reg, DP);
3978                 POSTING_READ(intel_dp->output_reg);
3979
3980                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3981                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3982                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3983         }
3984
3985         msleep(intel_dp->panel_power_down_delay);
3986
3987         intel_dp->DP = DP;
3988
3989         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3990                 pps_lock(intel_dp);
3991                 intel_dp->active_pipe = INVALID_PIPE;
3992                 pps_unlock(intel_dp);
3993         }
3994 }
3995
3996 bool
3997 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3998 {
3999         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4000                              sizeof(intel_dp->dpcd)) < 0)
4001                 return false; /* aux transfer failed */
4002
4003         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4004
4005         return intel_dp->dpcd[DP_DPCD_REV] != 0;
4006 }
4007
4008 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4009 {
4010         /*
4011          * Clear the cached register set to avoid using stale values
4012          * for the sinks that do not support DSC.
4013          */
4014         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4015
4016         /* Clear fec_capable to avoid using stale values */
4017         intel_dp->fec_capable = 0;
4018
4019         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4020         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4021             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4022                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4023                                      intel_dp->dsc_dpcd,
4024                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4025                         DRM_ERROR("Failed to read DPCD register 0x%x\n",
4026                                   DP_DSC_SUPPORT);
4027
4028                 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4029                               (int)sizeof(intel_dp->dsc_dpcd),
4030                               intel_dp->dsc_dpcd);
4031
4032                 /* FEC is supported only on DP 1.4 */
4033                 if (!intel_dp_is_edp(intel_dp) &&
4034                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4035                                       &intel_dp->fec_capable) < 0)
4036                         DRM_ERROR("Failed to read FEC DPCD register\n");
4037
4038                 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4039         }
4040 }
4041
4042 static bool
4043 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4044 {
4045         struct drm_i915_private *dev_priv =
4046                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4047
4048         /* this function is meant to be called only once */
4049         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4050
4051         if (!intel_dp_read_dpcd(intel_dp))
4052                 return false;
4053
4054         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4055                          drm_dp_is_branch(intel_dp->dpcd));
4056
4057         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4058                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4059                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4060
4061         /*
4062          * Read the eDP display control registers.
4063          *
4064          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4065          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4066          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4067          * method). The display control registers should read zero if they're
4068          * not supported anyway.
4069          */
4070         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4071                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4072                              sizeof(intel_dp->edp_dpcd))
4073                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
4074                               intel_dp->edp_dpcd);
4075
4076         /*
4077          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4078          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4079          */
4080         intel_psr_init_dpcd(intel_dp);
4081
4082         /* Read the eDP 1.4+ supported link rates. */
4083         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4084                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4085                 int i;
4086
4087                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4088                                 sink_rates, sizeof(sink_rates));
4089
4090                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4091                         int val = le16_to_cpu(sink_rates[i]);
4092
4093                         if (val == 0)
4094                                 break;
4095
4096                         /* Value read multiplied by 200kHz gives the per-lane
4097                          * link rate in kHz. The source rates are, however,
4098                          * stored in terms of LS_Clk kHz. The full conversion
4099                          * back to symbols is
4100                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4101                          */
4102                         intel_dp->sink_rates[i] = (val * 200) / 10;
4103                 }
4104                 intel_dp->num_sink_rates = i;
4105         }
4106
4107         /*
4108          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4109          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4110          */
4111         if (intel_dp->num_sink_rates)
4112                 intel_dp->use_rate_select = true;
4113         else
4114                 intel_dp_set_sink_rates(intel_dp);
4115
4116         intel_dp_set_common_rates(intel_dp);
4117
4118         /* Read the eDP DSC DPCD registers */
4119         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4120                 intel_dp_get_dsc_sink_cap(intel_dp);
4121
4122         return true;
4123 }
4124
4125
4126 static bool
4127 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4128 {
4129         if (!intel_dp_read_dpcd(intel_dp))
4130                 return false;
4131
4132         /* Don't clobber cached eDP rates. */
4133         if (!intel_dp_is_edp(intel_dp)) {
4134                 intel_dp_set_sink_rates(intel_dp);
4135                 intel_dp_set_common_rates(intel_dp);
4136         }
4137
4138         /*
4139          * Some eDP panels do not set a valid value for sink count, that is why
4140          * it don't care about read it here and in intel_edp_init_dpcd().
4141          */
4142         if (!intel_dp_is_edp(intel_dp)) {
4143                 u8 count;
4144                 ssize_t r;
4145
4146                 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4147                 if (r < 1)
4148                         return false;
4149
4150                 /*
4151                  * Sink count can change between short pulse hpd hence
4152                  * a member variable in intel_dp will track any changes
4153                  * between short pulse interrupts.
4154                  */
4155                 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4156
4157                 /*
4158                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4159                  * a dongle is present but no display. Unless we require to know
4160                  * if a dongle is present or not, we don't need to update
4161                  * downstream port information. So, an early return here saves
4162                  * time from performing other operations which are not required.
4163                  */
4164                 if (!intel_dp->sink_count)
4165                         return false;
4166         }
4167
4168         if (!drm_dp_is_branch(intel_dp->dpcd))
4169                 return true; /* native DP sink */
4170
4171         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4172                 return true; /* no per-port downstream info */
4173
4174         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4175                              intel_dp->downstream_ports,
4176                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4177                 return false; /* downstream port status fetch failed */
4178
4179         return true;
4180 }
4181
4182 static bool
4183 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4184 {
4185         u8 mstm_cap;
4186
4187         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4188                 return false;
4189
4190         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4191                 return false;
4192
4193         return mstm_cap & DP_MST_CAP;
4194 }
4195
4196 static bool
4197 intel_dp_can_mst(struct intel_dp *intel_dp)
4198 {
4199         return i915_modparams.enable_dp_mst &&
4200                 intel_dp->can_mst &&
4201                 intel_dp_sink_can_mst(intel_dp);
4202 }
4203
4204 static void
4205 intel_dp_configure_mst(struct intel_dp *intel_dp)
4206 {
4207         struct intel_encoder *encoder =
4208                 &dp_to_dig_port(intel_dp)->base;
4209         bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4210
4211         DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
4212                       port_name(encoder->port), yesno(intel_dp->can_mst),
4213                       yesno(sink_can_mst), yesno(i915_modparams.enable_dp_mst));
4214
4215         if (!intel_dp->can_mst)
4216                 return;
4217
4218         intel_dp->is_mst = sink_can_mst &&
4219                 i915_modparams.enable_dp_mst;
4220
4221         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4222                                         intel_dp->is_mst);
4223 }
4224
4225 static bool
4226 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4227 {
4228         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4229                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4230                 DP_DPRX_ESI_LEN;
4231 }
4232
4233 u16 intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
4234                                 int mode_clock, int mode_hdisplay)
4235 {
4236         u16 bits_per_pixel, max_bpp_small_joiner_ram;
4237         int i;
4238
4239         /*
4240          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
4241          * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
4242          * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
4243          * for MST -> TimeSlotsPerMTP has to be calculated
4244          */
4245         bits_per_pixel = (link_clock * lane_count * 8 *
4246                           DP_DSC_FEC_OVERHEAD_FACTOR) /
4247                 mode_clock;
4248
4249         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
4250         max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
4251                 mode_hdisplay;
4252
4253         /*
4254          * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
4255          * check, output bpp from small joiner RAM check)
4256          */
4257         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
4258
4259         /* Error out if the max bpp is less than smallest allowed valid bpp */
4260         if (bits_per_pixel < valid_dsc_bpp[0]) {
4261                 DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
4262                 return 0;
4263         }
4264
4265         /* Find the nearest match in the array of known BPPs from VESA */
4266         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
4267                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
4268                         break;
4269         }
4270         bits_per_pixel = valid_dsc_bpp[i];
4271
4272         /*
4273          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
4274          * fractional part is 0
4275          */
4276         return bits_per_pixel << 4;
4277 }
4278
4279 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
4280                                 int mode_clock,
4281                                 int mode_hdisplay)
4282 {
4283         u8 min_slice_count, i;
4284         int max_slice_width;
4285
4286         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
4287                 min_slice_count = DIV_ROUND_UP(mode_clock,
4288                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
4289         else
4290                 min_slice_count = DIV_ROUND_UP(mode_clock,
4291                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
4292
4293         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
4294         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
4295                 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
4296                               max_slice_width);
4297                 return 0;
4298         }
4299         /* Also take into account max slice width */
4300         min_slice_count = min_t(uint8_t, min_slice_count,
4301                                 DIV_ROUND_UP(mode_hdisplay,
4302                                              max_slice_width));
4303
4304         /* Find the closest match to the valid slice count values */
4305         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
4306                 if (valid_dsc_slicecount[i] >
4307                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
4308                                                     false))
4309                         break;
4310                 if (min_slice_count  <= valid_dsc_slicecount[i])
4311                         return valid_dsc_slicecount[i];
4312         }
4313
4314         DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
4315         return 0;
4316 }
4317
4318 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4319 {
4320         int status = 0;
4321         int test_link_rate;
4322         uint8_t test_lane_count, test_link_bw;
4323         /* (DP CTS 1.2)
4324          * 4.3.1.11
4325          */
4326         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4327         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4328                                    &test_lane_count);
4329
4330         if (status <= 0) {
4331                 DRM_DEBUG_KMS("Lane count read failed\n");
4332                 return DP_TEST_NAK;
4333         }
4334         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4335
4336         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4337                                    &test_link_bw);
4338         if (status <= 0) {
4339                 DRM_DEBUG_KMS("Link Rate read failed\n");
4340                 return DP_TEST_NAK;
4341         }
4342         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4343
4344         /* Validate the requested link rate and lane count */
4345         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4346                                         test_lane_count))
4347                 return DP_TEST_NAK;
4348
4349         intel_dp->compliance.test_lane_count = test_lane_count;
4350         intel_dp->compliance.test_link_rate = test_link_rate;
4351
4352         return DP_TEST_ACK;
4353 }
4354
4355 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4356 {
4357         uint8_t test_pattern;
4358         uint8_t test_misc;
4359         __be16 h_width, v_height;
4360         int status = 0;
4361
4362         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4363         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4364                                    &test_pattern);
4365         if (status <= 0) {
4366                 DRM_DEBUG_KMS("Test pattern read failed\n");
4367                 return DP_TEST_NAK;
4368         }
4369         if (test_pattern != DP_COLOR_RAMP)
4370                 return DP_TEST_NAK;
4371
4372         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4373                                   &h_width, 2);
4374         if (status <= 0) {
4375                 DRM_DEBUG_KMS("H Width read failed\n");
4376                 return DP_TEST_NAK;
4377         }
4378
4379         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4380                                   &v_height, 2);
4381         if (status <= 0) {
4382                 DRM_DEBUG_KMS("V Height read failed\n");
4383                 return DP_TEST_NAK;
4384         }
4385
4386         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4387                                    &test_misc);
4388         if (status <= 0) {
4389                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4390                 return DP_TEST_NAK;
4391         }
4392         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4393                 return DP_TEST_NAK;
4394         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4395                 return DP_TEST_NAK;
4396         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4397         case DP_TEST_BIT_DEPTH_6:
4398                 intel_dp->compliance.test_data.bpc = 6;
4399                 break;
4400         case DP_TEST_BIT_DEPTH_8:
4401                 intel_dp->compliance.test_data.bpc = 8;
4402                 break;
4403         default:
4404                 return DP_TEST_NAK;
4405         }
4406
4407         intel_dp->compliance.test_data.video_pattern = test_pattern;
4408         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4409         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4410         /* Set test active flag here so userspace doesn't interrupt things */
4411         intel_dp->compliance.test_active = 1;
4412
4413         return DP_TEST_ACK;
4414 }
4415
4416 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4417 {
4418         uint8_t test_result = DP_TEST_ACK;
4419         struct intel_connector *intel_connector = intel_dp->attached_connector;
4420         struct drm_connector *connector = &intel_connector->base;
4421
4422         if (intel_connector->detect_edid == NULL ||
4423             connector->edid_corrupt ||
4424             intel_dp->aux.i2c_defer_count > 6) {
4425                 /* Check EDID read for NACKs, DEFERs and corruption
4426                  * (DP CTS 1.2 Core r1.1)
4427                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4428                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4429                  *    4.2.2.6 : EDID corruption detected
4430                  * Use failsafe mode for all cases
4431                  */
4432                 if (intel_dp->aux.i2c_nack_count > 0 ||
4433                         intel_dp->aux.i2c_defer_count > 0)
4434                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4435                                       intel_dp->aux.i2c_nack_count,
4436                                       intel_dp->aux.i2c_defer_count);
4437                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4438         } else {
4439                 struct edid *block = intel_connector->detect_edid;
4440
4441                 /* We have to write the checksum
4442                  * of the last block read
4443                  */
4444                 block += intel_connector->detect_edid->extensions;
4445
4446                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4447                                        block->checksum) <= 0)
4448                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4449
4450                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4451                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4452         }
4453
4454         /* Set test active flag here so userspace doesn't interrupt things */
4455         intel_dp->compliance.test_active = 1;
4456
4457         return test_result;
4458 }
4459
4460 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4461 {
4462         uint8_t test_result = DP_TEST_NAK;
4463         return test_result;
4464 }
4465
4466 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4467 {
4468         uint8_t response = DP_TEST_NAK;
4469         uint8_t request = 0;
4470         int status;
4471
4472         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4473         if (status <= 0) {
4474                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4475                 goto update_status;
4476         }
4477
4478         switch (request) {
4479         case DP_TEST_LINK_TRAINING:
4480                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4481                 response = intel_dp_autotest_link_training(intel_dp);
4482                 break;
4483         case DP_TEST_LINK_VIDEO_PATTERN:
4484                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4485                 response = intel_dp_autotest_video_pattern(intel_dp);
4486                 break;
4487         case DP_TEST_LINK_EDID_READ:
4488                 DRM_DEBUG_KMS("EDID test requested\n");
4489                 response = intel_dp_autotest_edid(intel_dp);
4490                 break;
4491         case DP_TEST_LINK_PHY_TEST_PATTERN:
4492                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4493                 response = intel_dp_autotest_phy_pattern(intel_dp);
4494                 break;
4495         default:
4496                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4497                 break;
4498         }
4499
4500         if (response & DP_TEST_ACK)
4501                 intel_dp->compliance.test_type = request;
4502
4503 update_status:
4504         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4505         if (status <= 0)
4506                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4507 }
4508
4509 static int
4510 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4511 {
4512         bool bret;
4513
4514         if (intel_dp->is_mst) {
4515                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4516                 int ret = 0;
4517                 int retry;
4518                 bool handled;
4519
4520                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4521                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4522 go_again:
4523                 if (bret == true) {
4524
4525                         /* check link status - esi[10] = 0x200c */
4526                         if (intel_dp->active_mst_links > 0 &&
4527                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4528                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4529                                 intel_dp_start_link_train(intel_dp);
4530                                 intel_dp_stop_link_train(intel_dp);
4531                         }
4532
4533                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4534                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4535
4536                         if (handled) {
4537                                 for (retry = 0; retry < 3; retry++) {
4538                                         int wret;
4539                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4540                                                                  DP_SINK_COUNT_ESI+1,
4541                                                                  &esi[1], 3);
4542                                         if (wret == 3) {
4543                                                 break;
4544                                         }
4545                                 }
4546
4547                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4548                                 if (bret == true) {
4549                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4550                                         goto go_again;
4551                                 }
4552                         } else
4553                                 ret = 0;
4554
4555                         return ret;
4556                 } else {
4557                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4558                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4559                         intel_dp->is_mst = false;
4560                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4561                         /* send a hotplug event */
4562                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4563                 }
4564         }
4565         return -EINVAL;
4566 }
4567
4568 static bool
4569 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4570 {
4571         u8 link_status[DP_LINK_STATUS_SIZE];
4572
4573         if (!intel_dp->link_trained)
4574                 return false;
4575
4576         /*
4577          * While PSR source HW is enabled, it will control main-link sending
4578          * frames, enabling and disabling it so trying to do a retrain will fail
4579          * as the link would or not be on or it could mix training patterns
4580          * and frame data at the same time causing retrain to fail.
4581          * Also when exiting PSR, HW will retrain the link anyways fixing
4582          * any link status error.
4583          */
4584         if (intel_psr_enabled(intel_dp))
4585                 return false;
4586
4587         if (!intel_dp_get_link_status(intel_dp, link_status))
4588                 return false;
4589
4590         /*
4591          * Validate the cached values of intel_dp->link_rate and
4592          * intel_dp->lane_count before attempting to retrain.
4593          */
4594         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4595                                         intel_dp->lane_count))
4596                 return false;
4597
4598         /* Retrain if Channel EQ or CR not ok */
4599         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4600 }
4601
4602 int intel_dp_retrain_link(struct intel_encoder *encoder,
4603                           struct drm_modeset_acquire_ctx *ctx)
4604 {
4605         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4606         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4607         struct intel_connector *connector = intel_dp->attached_connector;
4608         struct drm_connector_state *conn_state;
4609         struct intel_crtc_state *crtc_state;
4610         struct intel_crtc *crtc;
4611         int ret;
4612
4613         /* FIXME handle the MST connectors as well */
4614
4615         if (!connector || connector->base.status != connector_status_connected)
4616                 return 0;
4617
4618         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4619                                ctx);
4620         if (ret)
4621                 return ret;
4622
4623         conn_state = connector->base.state;
4624
4625         crtc = to_intel_crtc(conn_state->crtc);
4626         if (!crtc)
4627                 return 0;
4628
4629         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4630         if (ret)
4631                 return ret;
4632
4633         crtc_state = to_intel_crtc_state(crtc->base.state);
4634
4635         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4636
4637         if (!crtc_state->base.active)
4638                 return 0;
4639
4640         if (conn_state->commit &&
4641             !try_wait_for_completion(&conn_state->commit->hw_done))
4642                 return 0;
4643
4644         if (!intel_dp_needs_link_retrain(intel_dp))
4645                 return 0;
4646
4647         /* Suppress underruns caused by re-training */
4648         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4649         if (crtc_state->has_pch_encoder)
4650                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4651                                                       intel_crtc_pch_transcoder(crtc), false);
4652
4653         intel_dp_start_link_train(intel_dp);
4654         intel_dp_stop_link_train(intel_dp);
4655
4656         /* Keep underrun reporting disabled until things are stable */
4657         intel_wait_for_vblank(dev_priv, crtc->pipe);
4658
4659         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4660         if (crtc_state->has_pch_encoder)
4661                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4662                                                       intel_crtc_pch_transcoder(crtc), true);
4663
4664         return 0;
4665 }
4666
4667 /*
4668  * If display is now connected check links status,
4669  * there has been known issues of link loss triggering
4670  * long pulse.
4671  *
4672  * Some sinks (eg. ASUS PB287Q) seem to perform some
4673  * weird HPD ping pong during modesets. So we can apparently
4674  * end up with HPD going low during a modeset, and then
4675  * going back up soon after. And once that happens we must
4676  * retrain the link to get a picture. That's in case no
4677  * userspace component reacted to intermittent HPD dip.
4678  */
4679 static bool intel_dp_hotplug(struct intel_encoder *encoder,
4680                              struct intel_connector *connector)
4681 {
4682         struct drm_modeset_acquire_ctx ctx;
4683         bool changed;
4684         int ret;
4685
4686         changed = intel_encoder_hotplug(encoder, connector);
4687
4688         drm_modeset_acquire_init(&ctx, 0);
4689
4690         for (;;) {
4691                 ret = intel_dp_retrain_link(encoder, &ctx);
4692
4693                 if (ret == -EDEADLK) {
4694                         drm_modeset_backoff(&ctx);
4695                         continue;
4696                 }
4697
4698                 break;
4699         }
4700
4701         drm_modeset_drop_locks(&ctx);
4702         drm_modeset_acquire_fini(&ctx);
4703         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4704
4705         return changed;
4706 }
4707
4708 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
4709 {
4710         u8 val;
4711
4712         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4713                 return;
4714
4715         if (drm_dp_dpcd_readb(&intel_dp->aux,
4716                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4717                 return;
4718
4719         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4720
4721         if (val & DP_AUTOMATED_TEST_REQUEST)
4722                 intel_dp_handle_test_request(intel_dp);
4723
4724         if (val & DP_CP_IRQ)
4725                 intel_hdcp_check_link(intel_dp->attached_connector);
4726
4727         if (val & DP_SINK_SPECIFIC_IRQ)
4728                 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
4729 }
4730
4731 /*
4732  * According to DP spec
4733  * 5.1.2:
4734  *  1. Read DPCD
4735  *  2. Configure link according to Receiver Capabilities
4736  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4737  *  4. Check link status on receipt of hot-plug interrupt
4738  *
4739  * intel_dp_short_pulse -  handles short pulse interrupts
4740  * when full detection is not required.
4741  * Returns %true if short pulse is handled and full detection
4742  * is NOT required and %false otherwise.
4743  */
4744 static bool
4745 intel_dp_short_pulse(struct intel_dp *intel_dp)
4746 {
4747         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4748         u8 old_sink_count = intel_dp->sink_count;
4749         bool ret;
4750
4751         /*
4752          * Clearing compliance test variables to allow capturing
4753          * of values for next automated test request.
4754          */
4755         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4756
4757         /*
4758          * Now read the DPCD to see if it's actually running
4759          * If the current value of sink count doesn't match with
4760          * the value that was stored earlier or dpcd read failed
4761          * we need to do full detection
4762          */
4763         ret = intel_dp_get_dpcd(intel_dp);
4764
4765         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4766                 /* No need to proceed if we are going to do full detect */
4767                 return false;
4768         }
4769
4770         intel_dp_check_service_irq(intel_dp);
4771
4772         /* Handle CEC interrupts, if any */
4773         drm_dp_cec_irq(&intel_dp->aux);
4774
4775         /* defer to the hotplug work for link retraining if needed */
4776         if (intel_dp_needs_link_retrain(intel_dp))
4777                 return false;
4778
4779         intel_psr_short_pulse(intel_dp);
4780
4781         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4782                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4783                 /* Send a Hotplug Uevent to userspace to start modeset */
4784                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4785         }
4786
4787         return true;
4788 }
4789
4790 /* XXX this is probably wrong for multiple downstream ports */
4791 static enum drm_connector_status
4792 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4793 {
4794         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4795         uint8_t *dpcd = intel_dp->dpcd;
4796         uint8_t type;
4797
4798         if (lspcon->active)
4799                 lspcon_resume(lspcon);
4800
4801         if (!intel_dp_get_dpcd(intel_dp))
4802                 return connector_status_disconnected;
4803
4804         if (intel_dp_is_edp(intel_dp))
4805                 return connector_status_connected;
4806
4807         /* if there's no downstream port, we're done */
4808         if (!drm_dp_is_branch(dpcd))
4809                 return connector_status_connected;
4810
4811         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4812         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4813             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4814
4815                 return intel_dp->sink_count ?
4816                 connector_status_connected : connector_status_disconnected;
4817         }
4818
4819         if (intel_dp_can_mst(intel_dp))
4820                 return connector_status_connected;
4821
4822         /* If no HPD, poke DDC gently */
4823         if (drm_probe_ddc(&intel_dp->aux.ddc))
4824                 return connector_status_connected;
4825
4826         /* Well we tried, say unknown for unreliable port types */
4827         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4828                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4829                 if (type == DP_DS_PORT_TYPE_VGA ||
4830                     type == DP_DS_PORT_TYPE_NON_EDID)
4831                         return connector_status_unknown;
4832         } else {
4833                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4834                         DP_DWN_STRM_PORT_TYPE_MASK;
4835                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4836                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4837                         return connector_status_unknown;
4838         }
4839
4840         /* Anything else is out of spec, warn and ignore */
4841         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4842         return connector_status_disconnected;
4843 }
4844
4845 static enum drm_connector_status
4846 edp_detect(struct intel_dp *intel_dp)
4847 {
4848         return connector_status_connected;
4849 }
4850
4851 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4852 {
4853         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4854         u32 bit;
4855
4856         switch (encoder->hpd_pin) {
4857         case HPD_PORT_B:
4858                 bit = SDE_PORTB_HOTPLUG;
4859                 break;
4860         case HPD_PORT_C:
4861                 bit = SDE_PORTC_HOTPLUG;
4862                 break;
4863         case HPD_PORT_D:
4864                 bit = SDE_PORTD_HOTPLUG;
4865                 break;
4866         default:
4867                 MISSING_CASE(encoder->hpd_pin);
4868                 return false;
4869         }
4870
4871         return I915_READ(SDEISR) & bit;
4872 }
4873
4874 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4875 {
4876         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4877         u32 bit;
4878
4879         switch (encoder->hpd_pin) {
4880         case HPD_PORT_B:
4881                 bit = SDE_PORTB_HOTPLUG_CPT;
4882                 break;
4883         case HPD_PORT_C:
4884                 bit = SDE_PORTC_HOTPLUG_CPT;
4885                 break;
4886         case HPD_PORT_D:
4887                 bit = SDE_PORTD_HOTPLUG_CPT;
4888                 break;
4889         default:
4890                 MISSING_CASE(encoder->hpd_pin);
4891                 return false;
4892         }
4893
4894         return I915_READ(SDEISR) & bit;
4895 }
4896
4897 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4898 {
4899         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4900         u32 bit;
4901
4902         switch (encoder->hpd_pin) {
4903         case HPD_PORT_A:
4904                 bit = SDE_PORTA_HOTPLUG_SPT;
4905                 break;
4906         case HPD_PORT_E:
4907                 bit = SDE_PORTE_HOTPLUG_SPT;
4908                 break;
4909         default:
4910                 return cpt_digital_port_connected(encoder);
4911         }
4912
4913         return I915_READ(SDEISR) & bit;
4914 }
4915
4916 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4917 {
4918         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4919         u32 bit;
4920
4921         switch (encoder->hpd_pin) {
4922         case HPD_PORT_B:
4923                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4924                 break;
4925         case HPD_PORT_C:
4926                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4927                 break;
4928         case HPD_PORT_D:
4929                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4930                 break;
4931         default:
4932                 MISSING_CASE(encoder->hpd_pin);
4933                 return false;
4934         }
4935
4936         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4937 }
4938
4939 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4940 {
4941         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4942         u32 bit;
4943
4944         switch (encoder->hpd_pin) {
4945         case HPD_PORT_B:
4946                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4947                 break;
4948         case HPD_PORT_C:
4949                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4950                 break;
4951         case HPD_PORT_D:
4952                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4953                 break;
4954         default:
4955                 MISSING_CASE(encoder->hpd_pin);
4956                 return false;
4957         }
4958
4959         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4960 }
4961
4962 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
4963 {
4964         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4965
4966         if (encoder->hpd_pin == HPD_PORT_A)
4967                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4968         else
4969                 return ibx_digital_port_connected(encoder);
4970 }
4971
4972 static bool snb_digital_port_connected(struct intel_encoder *encoder)
4973 {
4974         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4975
4976         if (encoder->hpd_pin == HPD_PORT_A)
4977                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4978         else
4979                 return cpt_digital_port_connected(encoder);
4980 }
4981
4982 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
4983 {
4984         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4985
4986         if (encoder->hpd_pin == HPD_PORT_A)
4987                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4988         else
4989                 return cpt_digital_port_connected(encoder);
4990 }
4991
4992 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4993 {
4994         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4995
4996         if (encoder->hpd_pin == HPD_PORT_A)
4997                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4998         else
4999                 return cpt_digital_port_connected(encoder);
5000 }
5001
5002 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5003 {
5004         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5005         u32 bit;
5006
5007         switch (encoder->hpd_pin) {
5008         case HPD_PORT_A:
5009                 bit = BXT_DE_PORT_HP_DDIA;
5010                 break;
5011         case HPD_PORT_B:
5012                 bit = BXT_DE_PORT_HP_DDIB;
5013                 break;
5014         case HPD_PORT_C:
5015                 bit = BXT_DE_PORT_HP_DDIC;
5016                 break;
5017         default:
5018                 MISSING_CASE(encoder->hpd_pin);
5019                 return false;
5020         }
5021
5022         return I915_READ(GEN8_DE_PORT_ISR) & bit;
5023 }
5024
5025 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
5026                                      struct intel_digital_port *intel_dig_port)
5027 {
5028         enum port port = intel_dig_port->base.port;
5029
5030         return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
5031 }
5032
5033 static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
5034                                     struct intel_digital_port *intel_dig_port,
5035                                     bool is_legacy, bool is_typec, bool is_tbt)
5036 {
5037         enum port port = intel_dig_port->base.port;
5038         enum tc_port_type old_type = intel_dig_port->tc_type;
5039         const char *type_str;
5040
5041         WARN_ON(is_legacy + is_typec + is_tbt != 1);
5042
5043         if (is_legacy) {
5044                 intel_dig_port->tc_type = TC_PORT_LEGACY;
5045                 type_str = "legacy";
5046         } else if (is_typec) {
5047                 intel_dig_port->tc_type = TC_PORT_TYPEC;
5048                 type_str = "typec";
5049         } else if (is_tbt) {
5050                 intel_dig_port->tc_type = TC_PORT_TBT;
5051                 type_str = "tbt";
5052         } else {
5053                 return;
5054         }
5055
5056         /* Types are not supposed to be changed at runtime. */
5057         WARN_ON(old_type != TC_PORT_UNKNOWN &&
5058                 old_type != intel_dig_port->tc_type);
5059
5060         if (old_type != intel_dig_port->tc_type)
5061                 DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
5062                               type_str);
5063 }
5064
5065 static void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
5066                                   struct intel_digital_port *dig_port);
5067
5068 /*
5069  * This function implements the first part of the Connect Flow described by our
5070  * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
5071  * lanes, EDID, etc) is done as needed in the typical places.
5072  *
5073  * Unlike the other ports, type-C ports are not available to use as soon as we
5074  * get a hotplug. The type-C PHYs can be shared between multiple controllers:
5075  * display, USB, etc. As a result, handshaking through FIA is required around
5076  * connect and disconnect to cleanly transfer ownership with the controller and
5077  * set the type-C power state.
5078  *
5079  * We could opt to only do the connect flow when we actually try to use the AUX
5080  * channels or do a modeset, then immediately run the disconnect flow after
5081  * usage, but there are some implications on this for a dynamic environment:
5082  * things may go away or change behind our backs. So for now our driver is
5083  * always trying to acquire ownership of the controller as soon as it gets an
5084  * interrupt (or polls state and sees a port is connected) and only gives it
5085  * back when it sees a disconnect. Implementation of a more fine-grained model
5086  * will require a lot of coordination with user space and thorough testing for
5087  * the extra possible cases.
5088  */
5089 static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
5090                                struct intel_digital_port *dig_port)
5091 {
5092         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
5093         u32 val;
5094
5095         if (dig_port->tc_type != TC_PORT_LEGACY &&
5096             dig_port->tc_type != TC_PORT_TYPEC)
5097                 return true;
5098
5099         val = I915_READ(PORT_TX_DFLEXDPPMS);
5100         if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
5101                 DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
5102                 return false;
5103         }
5104
5105         /*
5106          * This function may be called many times in a row without an HPD event
5107          * in between, so try to avoid the write when we can.
5108          */
5109         val = I915_READ(PORT_TX_DFLEXDPCSSS);
5110         if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
5111                 val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
5112                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
5113         }
5114
5115         /*
5116          * Now we have to re-check the live state, in case the port recently
5117          * became disconnected. Not necessary for legacy mode.
5118          */
5119         if (dig_port->tc_type == TC_PORT_TYPEC &&
5120             !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
5121                 DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
5122                 icl_tc_phy_disconnect(dev_priv, dig_port);
5123                 return false;
5124         }
5125
5126         return true;
5127 }
5128
5129 /*
5130  * See the comment at the connect function. This implements the Disconnect
5131  * Flow.
5132  */
5133 static void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
5134                                   struct intel_digital_port *dig_port)
5135 {
5136         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
5137
5138         if (dig_port->tc_type == TC_PORT_UNKNOWN)
5139                 return;
5140
5141         /*
5142          * TBT disconnection flow is read the live status, what was done in
5143          * caller.
5144          */
5145         if (dig_port->tc_type == TC_PORT_TYPEC ||
5146             dig_port->tc_type == TC_PORT_LEGACY) {
5147                 u32 val;
5148
5149                 val = I915_READ(PORT_TX_DFLEXDPCSSS);
5150                 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
5151                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
5152         }
5153
5154         dig_port->tc_type = TC_PORT_UNKNOWN;
5155 }
5156
5157 /*
5158  * The type-C ports are different because even when they are connected, they may
5159  * not be available/usable by the graphics driver: see the comment on
5160  * icl_tc_phy_connect(). So in our driver instead of adding the additional
5161  * concept of "usable" and make everything check for "connected and usable" we
5162  * define a port as "connected" when it is not only connected, but also when it
5163  * is usable by the rest of the driver. That maintains the old assumption that
5164  * connected ports are usable, and avoids exposing to the users objects they
5165  * can't really use.
5166  */
5167 static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
5168                                   struct intel_digital_port *intel_dig_port)
5169 {
5170         enum port port = intel_dig_port->base.port;
5171         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
5172         bool is_legacy, is_typec, is_tbt;
5173         u32 dpsp;
5174
5175         is_legacy = I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port);
5176
5177         /*
5178          * The spec says we shouldn't be using the ISR bits for detecting
5179          * between TC and TBT. We should use DFLEXDPSP.
5180          */
5181         dpsp = I915_READ(PORT_TX_DFLEXDPSP);
5182         is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
5183         is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
5184
5185         if (!is_legacy && !is_typec && !is_tbt) {
5186                 icl_tc_phy_disconnect(dev_priv, intel_dig_port);
5187                 return false;
5188         }
5189
5190         icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
5191                                 is_tbt);
5192
5193         if (!icl_tc_phy_connect(dev_priv, intel_dig_port))
5194                 return false;
5195
5196         return true;
5197 }
5198
5199 static bool icl_digital_port_connected(struct intel_encoder *encoder)
5200 {
5201         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5202         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
5203
5204         if (intel_port_is_combophy(dev_priv, encoder->port))
5205                 return icl_combo_port_connected(dev_priv, dig_port);
5206         else if (intel_port_is_tc(dev_priv, encoder->port))
5207                 return icl_tc_port_connected(dev_priv, dig_port);
5208         else
5209                 MISSING_CASE(encoder->hpd_pin);
5210
5211         return false;
5212 }
5213
5214 /*
5215  * intel_digital_port_connected - is the specified port connected?
5216  * @encoder: intel_encoder
5217  *
5218  * In cases where there's a connector physically connected but it can't be used
5219  * by our hardware we also return false, since the rest of the driver should
5220  * pretty much treat the port as disconnected. This is relevant for type-C
5221  * (starting on ICL) where there's ownership involved.
5222  *
5223  * Return %true if port is connected, %false otherwise.
5224  */
5225 bool intel_digital_port_connected(struct intel_encoder *encoder)
5226 {
5227         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5228
5229         if (HAS_GMCH_DISPLAY(dev_priv)) {
5230                 if (IS_GM45(dev_priv))
5231                         return gm45_digital_port_connected(encoder);
5232                 else
5233                         return g4x_digital_port_connected(encoder);
5234         }
5235
5236         if (INTEL_GEN(dev_priv) >= 11)
5237                 return icl_digital_port_connected(encoder);
5238         else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv))
5239                 return spt_digital_port_connected(encoder);
5240         else if (IS_GEN9_LP(dev_priv))
5241                 return bxt_digital_port_connected(encoder);
5242         else if (IS_GEN8(dev_priv))
5243                 return bdw_digital_port_connected(encoder);
5244         else if (IS_GEN7(dev_priv))
5245                 return ivb_digital_port_connected(encoder);
5246         else if (IS_GEN6(dev_priv))
5247                 return snb_digital_port_connected(encoder);
5248         else if (IS_GEN5(dev_priv))
5249                 return ilk_digital_port_connected(encoder);
5250
5251         MISSING_CASE(INTEL_GEN(dev_priv));
5252         return false;
5253 }
5254
5255 static struct edid *
5256 intel_dp_get_edid(struct intel_dp *intel_dp)
5257 {
5258         struct intel_connector *intel_connector = intel_dp->attached_connector;
5259
5260         /* use cached edid if we have one */
5261         if (intel_connector->edid) {
5262                 /* invalid edid */
5263                 if (IS_ERR(intel_connector->edid))
5264                         return NULL;
5265
5266                 return drm_edid_duplicate(intel_connector->edid);
5267         } else
5268                 return drm_get_edid(&intel_connector->base,
5269                                     &intel_dp->aux.ddc);
5270 }
5271
5272 static void
5273 intel_dp_set_edid(struct intel_dp *intel_dp)
5274 {
5275         struct intel_connector *intel_connector = intel_dp->attached_connector;
5276         struct edid *edid;
5277
5278         intel_dp_unset_edid(intel_dp);
5279         edid = intel_dp_get_edid(intel_dp);
5280         intel_connector->detect_edid = edid;
5281
5282         intel_dp->has_audio = drm_detect_monitor_audio(edid);
5283         drm_dp_cec_set_edid(&intel_dp->aux, edid);
5284 }
5285
5286 static void
5287 intel_dp_unset_edid(struct intel_dp *intel_dp)
5288 {
5289         struct intel_connector *intel_connector = intel_dp->attached_connector;
5290
5291         drm_dp_cec_unset_edid(&intel_dp->aux);
5292         kfree(intel_connector->detect_edid);
5293         intel_connector->detect_edid = NULL;
5294
5295         intel_dp->has_audio = false;
5296 }
5297
5298 static int
5299 intel_dp_detect(struct drm_connector *connector,
5300                 struct drm_modeset_acquire_ctx *ctx,
5301                 bool force)
5302 {
5303         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5304         struct intel_dp *intel_dp = intel_attached_dp(connector);
5305         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5306         struct intel_encoder *encoder = &dig_port->base;
5307         enum drm_connector_status status;
5308         enum intel_display_power_domain aux_domain =
5309                 intel_aux_power_domain(dig_port);
5310
5311         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5312                       connector->base.id, connector->name);
5313         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5314
5315         intel_display_power_get(dev_priv, aux_domain);
5316
5317         /* Can't disconnect eDP */
5318         if (intel_dp_is_edp(intel_dp))
5319                 status = edp_detect(intel_dp);
5320         else if (intel_digital_port_connected(encoder))
5321                 status = intel_dp_detect_dpcd(intel_dp);
5322         else
5323                 status = connector_status_disconnected;
5324
5325         if (status == connector_status_disconnected) {
5326                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5327                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5328
5329                 if (intel_dp->is_mst) {
5330                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5331                                       intel_dp->is_mst,
5332                                       intel_dp->mst_mgr.mst_state);
5333                         intel_dp->is_mst = false;
5334                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5335                                                         intel_dp->is_mst);
5336                 }
5337
5338                 goto out;
5339         }
5340
5341         if (intel_dp->reset_link_params) {
5342                 /* Initial max link lane count */
5343                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5344
5345                 /* Initial max link rate */
5346                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5347
5348                 intel_dp->reset_link_params = false;
5349         }
5350
5351         intel_dp_print_rates(intel_dp);
5352
5353         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5354         if (INTEL_GEN(dev_priv) >= 11)
5355                 intel_dp_get_dsc_sink_cap(intel_dp);
5356
5357         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5358                          drm_dp_is_branch(intel_dp->dpcd));
5359
5360         intel_dp_configure_mst(intel_dp);
5361
5362         if (intel_dp->is_mst) {
5363                 /*
5364                  * If we are in MST mode then this connector
5365                  * won't appear connected or have anything
5366                  * with EDID on it
5367                  */
5368                 status = connector_status_disconnected;
5369                 goto out;
5370         }
5371
5372         /*
5373          * Some external monitors do not signal loss of link synchronization
5374          * with an IRQ_HPD, so force a link status check.
5375          */
5376         if (!intel_dp_is_edp(intel_dp)) {
5377                 int ret;
5378
5379                 ret = intel_dp_retrain_link(encoder, ctx);
5380                 if (ret) {
5381                         intel_display_power_put(dev_priv, aux_domain);
5382                         return ret;
5383                 }
5384         }
5385
5386         /*
5387          * Clearing NACK and defer counts to get their exact values
5388          * while reading EDID which are required by Compliance tests
5389          * 4.2.2.4 and 4.2.2.5
5390          */
5391         intel_dp->aux.i2c_nack_count = 0;
5392         intel_dp->aux.i2c_defer_count = 0;
5393
5394         intel_dp_set_edid(intel_dp);
5395         if (intel_dp_is_edp(intel_dp) ||
5396             to_intel_connector(connector)->detect_edid)
5397                 status = connector_status_connected;
5398
5399         intel_dp_check_service_irq(intel_dp);
5400
5401 out:
5402         if (status != connector_status_connected && !intel_dp->is_mst)
5403                 intel_dp_unset_edid(intel_dp);
5404
5405         intel_display_power_put(dev_priv, aux_domain);
5406         return status;
5407 }
5408
5409 static void
5410 intel_dp_force(struct drm_connector *connector)
5411 {
5412         struct intel_dp *intel_dp = intel_attached_dp(connector);
5413         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5414         struct intel_encoder *intel_encoder = &dig_port->base;
5415         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5416         enum intel_display_power_domain aux_domain =
5417                 intel_aux_power_domain(dig_port);
5418
5419         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5420                       connector->base.id, connector->name);
5421         intel_dp_unset_edid(intel_dp);
5422
5423         if (connector->status != connector_status_connected)
5424                 return;
5425
5426         intel_display_power_get(dev_priv, aux_domain);
5427
5428         intel_dp_set_edid(intel_dp);
5429
5430         intel_display_power_put(dev_priv, aux_domain);
5431 }
5432
5433 static int intel_dp_get_modes(struct drm_connector *connector)
5434 {
5435         struct intel_connector *intel_connector = to_intel_connector(connector);
5436         struct edid *edid;
5437
5438         edid = intel_connector->detect_edid;
5439         if (edid) {
5440                 int ret = intel_connector_update_modes(connector, edid);
5441                 if (ret)
5442                         return ret;
5443         }
5444
5445         /* if eDP has no EDID, fall back to fixed mode */
5446         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5447             intel_connector->panel.fixed_mode) {
5448                 struct drm_display_mode *mode;
5449
5450                 mode = drm_mode_duplicate(connector->dev,
5451                                           intel_connector->panel.fixed_mode);
5452                 if (mode) {
5453                         drm_mode_probed_add(connector, mode);
5454                         return 1;
5455                 }
5456         }
5457
5458         return 0;
5459 }
5460
5461 static int
5462 intel_dp_connector_register(struct drm_connector *connector)
5463 {
5464         struct intel_dp *intel_dp = intel_attached_dp(connector);
5465         struct drm_device *dev = connector->dev;
5466         int ret;
5467
5468         ret = intel_connector_register(connector);
5469         if (ret)
5470                 return ret;
5471
5472         i915_debugfs_connector_add(connector);
5473
5474         DRM_DEBUG_KMS("registering %s bus for %s\n",
5475                       intel_dp->aux.name, connector->kdev->kobj.name);
5476
5477         intel_dp->aux.dev = connector->kdev;
5478         ret = drm_dp_aux_register(&intel_dp->aux);
5479         if (!ret)
5480                 drm_dp_cec_register_connector(&intel_dp->aux,
5481                                               connector->name, dev->dev);
5482         return ret;
5483 }
5484
5485 static void
5486 intel_dp_connector_unregister(struct drm_connector *connector)
5487 {
5488         struct intel_dp *intel_dp = intel_attached_dp(connector);
5489
5490         drm_dp_cec_unregister_connector(&intel_dp->aux);
5491         drm_dp_aux_unregister(&intel_dp->aux);
5492         intel_connector_unregister(connector);
5493 }
5494
5495 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5496 {
5497         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5498         struct intel_dp *intel_dp = &intel_dig_port->dp;
5499
5500         intel_dp_mst_encoder_cleanup(intel_dig_port);
5501         if (intel_dp_is_edp(intel_dp)) {
5502                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5503                 /*
5504                  * vdd might still be enabled do to the delayed vdd off.
5505                  * Make sure vdd is actually turned off here.
5506                  */
5507                 pps_lock(intel_dp);
5508                 edp_panel_vdd_off_sync(intel_dp);
5509                 pps_unlock(intel_dp);
5510
5511                 if (intel_dp->edp_notifier.notifier_call) {
5512                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5513                         intel_dp->edp_notifier.notifier_call = NULL;
5514                 }
5515         }
5516
5517         intel_dp_aux_fini(intel_dp);
5518
5519         drm_encoder_cleanup(encoder);
5520         kfree(intel_dig_port);
5521 }
5522
5523 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5524 {
5525         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5526
5527         if (!intel_dp_is_edp(intel_dp))
5528                 return;
5529
5530         /*
5531          * vdd might still be enabled do to the delayed vdd off.
5532          * Make sure vdd is actually turned off here.
5533          */
5534         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5535         pps_lock(intel_dp);
5536         edp_panel_vdd_off_sync(intel_dp);
5537         pps_unlock(intel_dp);
5538 }
5539
5540 static
5541 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5542                                 u8 *an)
5543 {
5544         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5545         static const struct drm_dp_aux_msg msg = {
5546                 .request = DP_AUX_NATIVE_WRITE,
5547                 .address = DP_AUX_HDCP_AKSV,
5548                 .size = DRM_HDCP_KSV_LEN,
5549         };
5550         uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5551         ssize_t dpcd_ret;
5552         int ret;
5553
5554         /* Output An first, that's easy */
5555         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5556                                      an, DRM_HDCP_AN_LEN);
5557         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5558                 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5559                               dpcd_ret);
5560                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5561         }
5562
5563         /*
5564          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5565          * order to get it on the wire, we need to create the AUX header as if
5566          * we were writing the data, and then tickle the hardware to output the
5567          * data once the header is sent out.
5568          */
5569         intel_dp_aux_header(txbuf, &msg);
5570
5571         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5572                                 rxbuf, sizeof(rxbuf),
5573                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5574         if (ret < 0) {
5575                 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5576                 return ret;
5577         } else if (ret == 0) {
5578                 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5579                 return -EIO;
5580         }
5581
5582         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5583         return reply == DP_AUX_NATIVE_REPLY_ACK ? 0 : -EIO;
5584 }
5585
5586 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5587                                    u8 *bksv)
5588 {
5589         ssize_t ret;
5590         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5591                                DRM_HDCP_KSV_LEN);
5592         if (ret != DRM_HDCP_KSV_LEN) {
5593                 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5594                 return ret >= 0 ? -EIO : ret;
5595         }
5596         return 0;
5597 }
5598
5599 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5600                                       u8 *bstatus)
5601 {
5602         ssize_t ret;
5603         /*
5604          * For some reason the HDMI and DP HDCP specs call this register
5605          * definition by different names. In the HDMI spec, it's called BSTATUS,
5606          * but in DP it's called BINFO.
5607          */
5608         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5609                                bstatus, DRM_HDCP_BSTATUS_LEN);
5610         if (ret != DRM_HDCP_BSTATUS_LEN) {
5611                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5612                 return ret >= 0 ? -EIO : ret;
5613         }
5614         return 0;
5615 }
5616
5617 static
5618 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5619                              u8 *bcaps)
5620 {
5621         ssize_t ret;
5622
5623         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5624                                bcaps, 1);
5625         if (ret != 1) {
5626                 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
5627                 return ret >= 0 ? -EIO : ret;
5628         }
5629
5630         return 0;
5631 }
5632
5633 static
5634 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5635                                    bool *repeater_present)
5636 {
5637         ssize_t ret;
5638         u8 bcaps;
5639
5640         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5641         if (ret)
5642                 return ret;
5643
5644         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5645         return 0;
5646 }
5647
5648 static
5649 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5650                                 u8 *ri_prime)
5651 {
5652         ssize_t ret;
5653         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5654                                ri_prime, DRM_HDCP_RI_LEN);
5655         if (ret != DRM_HDCP_RI_LEN) {
5656                 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
5657                 return ret >= 0 ? -EIO : ret;
5658         }
5659         return 0;
5660 }
5661
5662 static
5663 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5664                                  bool *ksv_ready)
5665 {
5666         ssize_t ret;
5667         u8 bstatus;
5668         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5669                                &bstatus, 1);
5670         if (ret != 1) {
5671                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5672                 return ret >= 0 ? -EIO : ret;
5673         }
5674         *ksv_ready = bstatus & DP_BSTATUS_READY;
5675         return 0;
5676 }
5677
5678 static
5679 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5680                                 int num_downstream, u8 *ksv_fifo)
5681 {
5682         ssize_t ret;
5683         int i;
5684
5685         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5686         for (i = 0; i < num_downstream; i += 3) {
5687                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5688                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5689                                        DP_AUX_HDCP_KSV_FIFO,
5690                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5691                                        len);
5692                 if (ret != len) {
5693                         DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
5694                                       i, ret);
5695                         return ret >= 0 ? -EIO : ret;
5696                 }
5697         }
5698         return 0;
5699 }
5700
5701 static
5702 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5703                                     int i, u32 *part)
5704 {
5705         ssize_t ret;
5706
5707         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5708                 return -EINVAL;
5709
5710         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5711                                DP_AUX_HDCP_V_PRIME(i), part,
5712                                DRM_HDCP_V_PRIME_PART_LEN);
5713         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5714                 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5715                 return ret >= 0 ? -EIO : ret;
5716         }
5717         return 0;
5718 }
5719
5720 static
5721 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5722                                     bool enable)
5723 {
5724         /* Not used for single stream DisplayPort setups */
5725         return 0;
5726 }
5727
5728 static
5729 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5730 {
5731         ssize_t ret;
5732         u8 bstatus;
5733
5734         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5735                                &bstatus, 1);
5736         if (ret != 1) {
5737                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5738                 return false;
5739         }
5740
5741         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5742 }
5743
5744 static
5745 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5746                           bool *hdcp_capable)
5747 {
5748         ssize_t ret;
5749         u8 bcaps;
5750
5751         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5752         if (ret)
5753                 return ret;
5754
5755         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5756         return 0;
5757 }
5758
5759 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
5760         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
5761         .read_bksv = intel_dp_hdcp_read_bksv,
5762         .read_bstatus = intel_dp_hdcp_read_bstatus,
5763         .repeater_present = intel_dp_hdcp_repeater_present,
5764         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
5765         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
5766         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
5767         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
5768         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
5769         .check_link = intel_dp_hdcp_check_link,
5770         .hdcp_capable = intel_dp_hdcp_capable,
5771 };
5772
5773 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5774 {
5775         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5776         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5777
5778         lockdep_assert_held(&dev_priv->pps_mutex);
5779
5780         if (!edp_have_panel_vdd(intel_dp))
5781                 return;
5782
5783         /*
5784          * The VDD bit needs a power domain reference, so if the bit is
5785          * already enabled when we boot or resume, grab this reference and
5786          * schedule a vdd off, so we don't hold on to the reference
5787          * indefinitely.
5788          */
5789         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5790         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
5791
5792         edp_panel_vdd_schedule_off(intel_dp);
5793 }
5794
5795 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5796 {
5797         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5798         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5799         enum pipe pipe;
5800
5801         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
5802                                   encoder->port, &pipe))
5803                 return pipe;
5804
5805         return INVALID_PIPE;
5806 }
5807
5808 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5809 {
5810         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5811         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5812         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5813
5814         if (!HAS_DDI(dev_priv))
5815                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5816
5817         if (lspcon->active)
5818                 lspcon_resume(lspcon);
5819
5820         intel_dp->reset_link_params = true;
5821
5822         pps_lock(intel_dp);
5823
5824         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5825                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5826
5827         if (intel_dp_is_edp(intel_dp)) {
5828                 /* Reinit the power sequencer, in case BIOS did something with it. */
5829                 intel_dp_pps_init(intel_dp);
5830                 intel_edp_panel_vdd_sanitize(intel_dp);
5831         }
5832
5833         pps_unlock(intel_dp);
5834 }
5835
5836 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5837         .force = intel_dp_force,
5838         .fill_modes = drm_helper_probe_single_connector_modes,
5839         .atomic_get_property = intel_digital_connector_atomic_get_property,
5840         .atomic_set_property = intel_digital_connector_atomic_set_property,
5841         .late_register = intel_dp_connector_register,
5842         .early_unregister = intel_dp_connector_unregister,
5843         .destroy = intel_connector_destroy,
5844         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5845         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5846 };
5847
5848 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5849         .detect_ctx = intel_dp_detect,
5850         .get_modes = intel_dp_get_modes,
5851         .mode_valid = intel_dp_mode_valid,
5852         .atomic_check = intel_digital_connector_atomic_check,
5853 };
5854
5855 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5856         .reset = intel_dp_encoder_reset,
5857         .destroy = intel_dp_encoder_destroy,
5858 };
5859
5860 enum irqreturn
5861 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5862 {
5863         struct intel_dp *intel_dp = &intel_dig_port->dp;
5864         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5865         enum irqreturn ret = IRQ_NONE;
5866
5867         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5868                 /*
5869                  * vdd off can generate a long pulse on eDP which
5870                  * would require vdd on to handle it, and thus we
5871                  * would end up in an endless cycle of
5872                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5873                  */
5874                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5875                               port_name(intel_dig_port->base.port));
5876                 return IRQ_HANDLED;
5877         }
5878
5879         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5880                       port_name(intel_dig_port->base.port),
5881                       long_hpd ? "long" : "short");
5882
5883         if (long_hpd) {
5884                 intel_dp->reset_link_params = true;
5885                 return IRQ_NONE;
5886         }
5887
5888         intel_display_power_get(dev_priv,
5889                                 intel_aux_power_domain(intel_dig_port));
5890
5891         if (intel_dp->is_mst) {
5892                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5893                         /*
5894                          * If we were in MST mode, and device is not
5895                          * there, get out of MST mode
5896                          */
5897                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5898                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5899                         intel_dp->is_mst = false;
5900                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5901                                                         intel_dp->is_mst);
5902                         goto put_power;
5903                 }
5904         }
5905
5906         if (!intel_dp->is_mst) {
5907                 bool handled;
5908
5909                 handled = intel_dp_short_pulse(intel_dp);
5910
5911                 if (!handled)
5912                         goto put_power;
5913         }
5914
5915         ret = IRQ_HANDLED;
5916
5917 put_power:
5918         intel_display_power_put(dev_priv,
5919                                 intel_aux_power_domain(intel_dig_port));
5920
5921         return ret;
5922 }
5923
5924 /* check the VBT to see whether the eDP is on another port */
5925 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5926 {
5927         /*
5928          * eDP not supported on g4x. so bail out early just
5929          * for a bit extra safety in case the VBT is bonkers.
5930          */
5931         if (INTEL_GEN(dev_priv) < 5)
5932                 return false;
5933
5934         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5935                 return true;
5936
5937         return intel_bios_is_port_edp(dev_priv, port);
5938 }
5939
5940 static void
5941 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5942 {
5943         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5944         enum port port = dp_to_dig_port(intel_dp)->base.port;
5945
5946         if (!IS_G4X(dev_priv) && port != PORT_A)
5947                 intel_attach_force_audio_property(connector);
5948
5949         intel_attach_broadcast_rgb_property(connector);
5950         if (HAS_GMCH_DISPLAY(dev_priv))
5951                 drm_connector_attach_max_bpc_property(connector, 6, 10);
5952         else if (INTEL_GEN(dev_priv) >= 5)
5953                 drm_connector_attach_max_bpc_property(connector, 6, 12);
5954
5955         if (intel_dp_is_edp(intel_dp)) {
5956                 u32 allowed_scalers;
5957
5958                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5959                 if (!HAS_GMCH_DISPLAY(dev_priv))
5960                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5961
5962                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5963
5964                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5965
5966         }
5967 }
5968
5969 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5970 {
5971         intel_dp->panel_power_off_time = ktime_get_boottime();
5972         intel_dp->last_power_on = jiffies;
5973         intel_dp->last_backlight_off = jiffies;
5974 }
5975
5976 static void
5977 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
5978 {
5979         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5980         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5981         struct pps_registers regs;
5982
5983         intel_pps_get_registers(intel_dp, &regs);
5984
5985         /* Workaround: Need to write PP_CONTROL with the unlock key as
5986          * the very first thing. */
5987         pp_ctl = ironlake_get_pp_control(intel_dp);
5988
5989         pp_on = I915_READ(regs.pp_on);
5990         pp_off = I915_READ(regs.pp_off);
5991         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
5992             !HAS_PCH_ICP(dev_priv)) {
5993                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5994                 pp_div = I915_READ(regs.pp_div);
5995         }
5996
5997         /* Pull timing values out of registers */
5998         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5999                      PANEL_POWER_UP_DELAY_SHIFT;
6000
6001         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
6002                   PANEL_LIGHT_ON_DELAY_SHIFT;
6003
6004         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
6005                   PANEL_LIGHT_OFF_DELAY_SHIFT;
6006
6007         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
6008                    PANEL_POWER_DOWN_DELAY_SHIFT;
6009
6010         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
6011             HAS_PCH_ICP(dev_priv)) {
6012                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
6013                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
6014         } else {
6015                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
6016                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
6017         }
6018 }
6019
6020 static void
6021 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6022 {
6023         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6024                       state_name,
6025                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6026 }
6027
6028 static void
6029 intel_pps_verify_state(struct intel_dp *intel_dp)
6030 {
6031         struct edp_power_seq hw;
6032         struct edp_power_seq *sw = &intel_dp->pps_delays;
6033
6034         intel_pps_readout_hw_state(intel_dp, &hw);
6035
6036         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6037             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6038                 DRM_ERROR("PPS state mismatch\n");
6039                 intel_pps_dump_state("sw", sw);
6040                 intel_pps_dump_state("hw", &hw);
6041         }
6042 }
6043
6044 static void
6045 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6046 {
6047         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6048         struct edp_power_seq cur, vbt, spec,
6049                 *final = &intel_dp->pps_delays;
6050
6051         lockdep_assert_held(&dev_priv->pps_mutex);
6052
6053         /* already initialized? */
6054         if (final->t11_t12 != 0)
6055                 return;
6056
6057         intel_pps_readout_hw_state(intel_dp, &cur);
6058
6059         intel_pps_dump_state("cur", &cur);
6060
6061         vbt = dev_priv->vbt.edp.pps;
6062         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6063          * of 500ms appears to be too short. Ocassionally the panel
6064          * just fails to power back on. Increasing the delay to 800ms
6065          * seems sufficient to avoid this problem.
6066          */
6067         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6068                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6069                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6070                               vbt.t11_t12);
6071         }
6072         /* T11_T12 delay is special and actually in units of 100ms, but zero
6073          * based in the hw (so we need to add 100 ms). But the sw vbt
6074          * table multiplies it with 1000 to make it in units of 100usec,
6075          * too. */
6076         vbt.t11_t12 += 100 * 10;
6077
6078         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6079          * our hw here, which are all in 100usec. */
6080         spec.t1_t3 = 210 * 10;
6081         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6082         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6083         spec.t10 = 500 * 10;
6084         /* This one is special and actually in units of 100ms, but zero
6085          * based in the hw (so we need to add 100 ms). But the sw vbt
6086          * table multiplies it with 1000 to make it in units of 100usec,
6087          * too. */
6088         spec.t11_t12 = (510 + 100) * 10;
6089
6090         intel_pps_dump_state("vbt", &vbt);
6091
6092         /* Use the max of the register settings and vbt. If both are
6093          * unset, fall back to the spec limits. */
6094 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
6095                                        spec.field : \
6096                                        max(cur.field, vbt.field))
6097         assign_final(t1_t3);
6098         assign_final(t8);
6099         assign_final(t9);
6100         assign_final(t10);
6101         assign_final(t11_t12);
6102 #undef assign_final
6103
6104 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
6105         intel_dp->panel_power_up_delay = get_delay(t1_t3);
6106         intel_dp->backlight_on_delay = get_delay(t8);
6107         intel_dp->backlight_off_delay = get_delay(t9);
6108         intel_dp->panel_power_down_delay = get_delay(t10);
6109         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6110 #undef get_delay
6111
6112         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6113                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
6114                       intel_dp->panel_power_cycle_delay);
6115
6116         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6117                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
6118
6119         /*
6120          * We override the HW backlight delays to 1 because we do manual waits
6121          * on them. For T8, even BSpec recommends doing it. For T9, if we
6122          * don't do this, we'll end up waiting for the backlight off delay
6123          * twice: once when we do the manual sleep, and once when we disable
6124          * the panel and wait for the PP_STATUS bit to become zero.
6125          */
6126         final->t8 = 1;
6127         final->t9 = 1;
6128
6129         /*
6130          * HW has only a 100msec granularity for t11_t12 so round it up
6131          * accordingly.
6132          */
6133         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6134 }
6135
6136 static void
6137 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6138                                               bool force_disable_vdd)
6139 {
6140         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6141         u32 pp_on, pp_off, pp_div, port_sel = 0;
6142         int div = dev_priv->rawclk_freq / 1000;
6143         struct pps_registers regs;
6144         enum port port = dp_to_dig_port(intel_dp)->base.port;
6145         const struct edp_power_seq *seq = &intel_dp->pps_delays;
6146
6147         lockdep_assert_held(&dev_priv->pps_mutex);
6148
6149         intel_pps_get_registers(intel_dp, &regs);
6150
6151         /*
6152          * On some VLV machines the BIOS can leave the VDD
6153          * enabled even on power sequencers which aren't
6154          * hooked up to any port. This would mess up the
6155          * power domain tracking the first time we pick
6156          * one of these power sequencers for use since
6157          * edp_panel_vdd_on() would notice that the VDD was
6158          * already on and therefore wouldn't grab the power
6159          * domain reference. Disable VDD first to avoid this.
6160          * This also avoids spuriously turning the VDD on as
6161          * soon as the new power sequencer gets initialized.
6162          */
6163         if (force_disable_vdd) {
6164                 u32 pp = ironlake_get_pp_control(intel_dp);
6165
6166                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
6167
6168                 if (pp & EDP_FORCE_VDD)
6169                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
6170
6171                 pp &= ~EDP_FORCE_VDD;
6172
6173                 I915_WRITE(regs.pp_ctrl, pp);
6174         }
6175
6176         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
6177                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
6178         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
6179                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
6180         /* Compute the divisor for the pp clock, simply match the Bspec
6181          * formula. */
6182         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
6183             HAS_PCH_ICP(dev_priv)) {
6184                 pp_div = I915_READ(regs.pp_ctrl);
6185                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
6186                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
6187                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
6188         } else {
6189                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
6190                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
6191                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
6192         }
6193
6194         /* Haswell doesn't have any port selection bits for the panel
6195          * power sequencer any more. */
6196         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6197                 port_sel = PANEL_PORT_SELECT_VLV(port);
6198         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6199                 switch (port) {
6200                 case PORT_A:
6201                         port_sel = PANEL_PORT_SELECT_DPA;
6202                         break;
6203                 case PORT_C:
6204                         port_sel = PANEL_PORT_SELECT_DPC;
6205                         break;
6206                 case PORT_D:
6207                         port_sel = PANEL_PORT_SELECT_DPD;
6208                         break;
6209                 default:
6210                         MISSING_CASE(port);
6211                         break;
6212                 }
6213         }
6214
6215         pp_on |= port_sel;
6216
6217         I915_WRITE(regs.pp_on, pp_on);
6218         I915_WRITE(regs.pp_off, pp_off);
6219         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
6220             HAS_PCH_ICP(dev_priv))
6221                 I915_WRITE(regs.pp_ctrl, pp_div);
6222         else
6223                 I915_WRITE(regs.pp_div, pp_div);
6224
6225         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6226                       I915_READ(regs.pp_on),
6227                       I915_READ(regs.pp_off),
6228                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)  ||
6229                        HAS_PCH_ICP(dev_priv)) ?
6230                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
6231                       I915_READ(regs.pp_div));
6232 }
6233
6234 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6235 {
6236         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6237
6238         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6239                 vlv_initial_power_sequencer_setup(intel_dp);
6240         } else {
6241                 intel_dp_init_panel_power_sequencer(intel_dp);
6242                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6243         }
6244 }
6245
6246 /**
6247  * intel_dp_set_drrs_state - program registers for RR switch to take effect
6248  * @dev_priv: i915 device
6249  * @crtc_state: a pointer to the active intel_crtc_state
6250  * @refresh_rate: RR to be programmed
6251  *
6252  * This function gets called when refresh rate (RR) has to be changed from
6253  * one frequency to another. Switches can be between high and low RR
6254  * supported by the panel or to any other RR based on media playback (in
6255  * this case, RR value needs to be passed from user space).
6256  *
6257  * The caller of this function needs to take a lock on dev_priv->drrs.
6258  */
6259 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6260                                     const struct intel_crtc_state *crtc_state,
6261                                     int refresh_rate)
6262 {
6263         struct intel_encoder *encoder;
6264         struct intel_digital_port *dig_port = NULL;
6265         struct intel_dp *intel_dp = dev_priv->drrs.dp;
6266         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6267         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6268
6269         if (refresh_rate <= 0) {
6270                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6271                 return;
6272         }
6273
6274         if (intel_dp == NULL) {
6275                 DRM_DEBUG_KMS("DRRS not supported.\n");
6276                 return;
6277         }
6278
6279         dig_port = dp_to_dig_port(intel_dp);
6280         encoder = &dig_port->base;
6281
6282         if (!intel_crtc) {
6283                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6284                 return;
6285         }
6286
6287         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6288                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6289                 return;
6290         }
6291
6292         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6293                         refresh_rate)
6294                 index = DRRS_LOW_RR;
6295
6296         if (index == dev_priv->drrs.refresh_rate_type) {
6297                 DRM_DEBUG_KMS(
6298                         "DRRS requested for previously set RR...ignoring\n");
6299                 return;
6300         }
6301
6302         if (!crtc_state->base.active) {
6303                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6304                 return;
6305         }
6306
6307         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6308                 switch (index) {
6309                 case DRRS_HIGH_RR:
6310                         intel_dp_set_m_n(crtc_state, M1_N1);
6311                         break;
6312                 case DRRS_LOW_RR:
6313                         intel_dp_set_m_n(crtc_state, M2_N2);
6314                         break;
6315                 case DRRS_MAX_RR:
6316                 default:
6317                         DRM_ERROR("Unsupported refreshrate type\n");
6318                 }
6319         } else if (INTEL_GEN(dev_priv) > 6) {
6320                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6321                 u32 val;
6322
6323                 val = I915_READ(reg);
6324                 if (index > DRRS_HIGH_RR) {
6325                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6326                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6327                         else
6328                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6329                 } else {
6330                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6331                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6332                         else
6333                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6334                 }
6335                 I915_WRITE(reg, val);
6336         }
6337
6338         dev_priv->drrs.refresh_rate_type = index;
6339
6340         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6341 }
6342
6343 /**
6344  * intel_edp_drrs_enable - init drrs struct if supported
6345  * @intel_dp: DP struct
6346  * @crtc_state: A pointer to the active crtc state.
6347  *
6348  * Initializes frontbuffer_bits and drrs.dp
6349  */
6350 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6351                            const struct intel_crtc_state *crtc_state)
6352 {
6353         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6354
6355         if (!crtc_state->has_drrs) {
6356                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6357                 return;
6358         }
6359
6360         if (dev_priv->psr.enabled) {
6361                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6362                 return;
6363         }
6364
6365         mutex_lock(&dev_priv->drrs.mutex);
6366         if (WARN_ON(dev_priv->drrs.dp)) {
6367                 DRM_ERROR("DRRS already enabled\n");
6368                 goto unlock;
6369         }
6370
6371         dev_priv->drrs.busy_frontbuffer_bits = 0;
6372
6373         dev_priv->drrs.dp = intel_dp;
6374
6375 unlock:
6376         mutex_unlock(&dev_priv->drrs.mutex);
6377 }
6378
6379 /**
6380  * intel_edp_drrs_disable - Disable DRRS
6381  * @intel_dp: DP struct
6382  * @old_crtc_state: Pointer to old crtc_state.
6383  *
6384  */
6385 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6386                             const struct intel_crtc_state *old_crtc_state)
6387 {
6388         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6389
6390         if (!old_crtc_state->has_drrs)
6391                 return;
6392
6393         mutex_lock(&dev_priv->drrs.mutex);
6394         if (!dev_priv->drrs.dp) {
6395                 mutex_unlock(&dev_priv->drrs.mutex);
6396                 return;
6397         }
6398
6399         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6400                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
6401                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
6402
6403         dev_priv->drrs.dp = NULL;
6404         mutex_unlock(&dev_priv->drrs.mutex);
6405
6406         cancel_delayed_work_sync(&dev_priv->drrs.work);
6407 }
6408
6409 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6410 {
6411         struct drm_i915_private *dev_priv =
6412                 container_of(work, typeof(*dev_priv), drrs.work.work);
6413         struct intel_dp *intel_dp;
6414
6415         mutex_lock(&dev_priv->drrs.mutex);
6416
6417         intel_dp = dev_priv->drrs.dp;
6418
6419         if (!intel_dp)
6420                 goto unlock;
6421
6422         /*
6423          * The delayed work can race with an invalidate hence we need to
6424          * recheck.
6425          */
6426
6427         if (dev_priv->drrs.busy_frontbuffer_bits)
6428                 goto unlock;
6429
6430         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6431                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6432
6433                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6434                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
6435         }
6436
6437 unlock:
6438         mutex_unlock(&dev_priv->drrs.mutex);
6439 }
6440
6441 /**
6442  * intel_edp_drrs_invalidate - Disable Idleness DRRS
6443  * @dev_priv: i915 device
6444  * @frontbuffer_bits: frontbuffer plane tracking bits
6445  *
6446  * This function gets called everytime rendering on the given planes start.
6447  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6448  *
6449  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6450  */
6451 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6452                                unsigned int frontbuffer_bits)
6453 {
6454         struct drm_crtc *crtc;
6455         enum pipe pipe;
6456
6457         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6458                 return;
6459
6460         cancel_delayed_work(&dev_priv->drrs.work);
6461
6462         mutex_lock(&dev_priv->drrs.mutex);
6463         if (!dev_priv->drrs.dp) {
6464                 mutex_unlock(&dev_priv->drrs.mutex);
6465                 return;
6466         }
6467
6468         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6469         pipe = to_intel_crtc(crtc)->pipe;
6470
6471         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6472         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6473
6474         /* invalidate means busy screen hence upclock */
6475         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6476                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6477                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6478
6479         mutex_unlock(&dev_priv->drrs.mutex);
6480 }
6481
6482 /**
6483  * intel_edp_drrs_flush - Restart Idleness DRRS
6484  * @dev_priv: i915 device
6485  * @frontbuffer_bits: frontbuffer plane tracking bits
6486  *
6487  * This function gets called every time rendering on the given planes has
6488  * completed or flip on a crtc is completed. So DRRS should be upclocked
6489  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6490  * if no other planes are dirty.
6491  *
6492  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6493  */
6494 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6495                           unsigned int frontbuffer_bits)
6496 {
6497         struct drm_crtc *crtc;
6498         enum pipe pipe;
6499
6500         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6501                 return;
6502
6503         cancel_delayed_work(&dev_priv->drrs.work);
6504
6505         mutex_lock(&dev_priv->drrs.mutex);
6506         if (!dev_priv->drrs.dp) {
6507                 mutex_unlock(&dev_priv->drrs.mutex);
6508                 return;
6509         }
6510
6511         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6512         pipe = to_intel_crtc(crtc)->pipe;
6513
6514         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6515         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6516
6517         /* flush means busy screen hence upclock */
6518         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6519                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6520                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6521
6522         /*
6523          * flush also means no more activity hence schedule downclock, if all
6524          * other fbs are quiescent too
6525          */
6526         if (!dev_priv->drrs.busy_frontbuffer_bits)
6527                 schedule_delayed_work(&dev_priv->drrs.work,
6528                                 msecs_to_jiffies(1000));
6529         mutex_unlock(&dev_priv->drrs.mutex);
6530 }
6531
6532 /**
6533  * DOC: Display Refresh Rate Switching (DRRS)
6534  *
6535  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6536  * which enables swtching between low and high refresh rates,
6537  * dynamically, based on the usage scenario. This feature is applicable
6538  * for internal panels.
6539  *
6540  * Indication that the panel supports DRRS is given by the panel EDID, which
6541  * would list multiple refresh rates for one resolution.
6542  *
6543  * DRRS is of 2 types - static and seamless.
6544  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6545  * (may appear as a blink on screen) and is used in dock-undock scenario.
6546  * Seamless DRRS involves changing RR without any visual effect to the user
6547  * and can be used during normal system usage. This is done by programming
6548  * certain registers.
6549  *
6550  * Support for static/seamless DRRS may be indicated in the VBT based on
6551  * inputs from the panel spec.
6552  *
6553  * DRRS saves power by switching to low RR based on usage scenarios.
6554  *
6555  * The implementation is based on frontbuffer tracking implementation.  When
6556  * there is a disturbance on the screen triggered by user activity or a periodic
6557  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6558  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6559  * made.
6560  *
6561  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6562  * and intel_edp_drrs_flush() are called.
6563  *
6564  * DRRS can be further extended to support other internal panels and also
6565  * the scenario of video playback wherein RR is set based on the rate
6566  * requested by userspace.
6567  */
6568
6569 /**
6570  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6571  * @connector: eDP connector
6572  * @fixed_mode: preferred mode of panel
6573  *
6574  * This function is  called only once at driver load to initialize basic
6575  * DRRS stuff.
6576  *
6577  * Returns:
6578  * Downclock mode if panel supports it, else return NULL.
6579  * DRRS support is determined by the presence of downclock mode (apart
6580  * from VBT setting).
6581  */
6582 static struct drm_display_mode *
6583 intel_dp_drrs_init(struct intel_connector *connector,
6584                    struct drm_display_mode *fixed_mode)
6585 {
6586         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6587         struct drm_display_mode *downclock_mode = NULL;
6588
6589         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6590         mutex_init(&dev_priv->drrs.mutex);
6591
6592         if (INTEL_GEN(dev_priv) <= 6) {
6593                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6594                 return NULL;
6595         }
6596
6597         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6598                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6599                 return NULL;
6600         }
6601
6602         downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
6603                                                     &connector->base);
6604
6605         if (!downclock_mode) {
6606                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6607                 return NULL;
6608         }
6609
6610         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6611
6612         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6613         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6614         return downclock_mode;
6615 }
6616
6617 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6618                                      struct intel_connector *intel_connector)
6619 {
6620         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6621         struct drm_device *dev = &dev_priv->drm;
6622         struct drm_connector *connector = &intel_connector->base;
6623         struct drm_display_mode *fixed_mode = NULL;
6624         struct drm_display_mode *downclock_mode = NULL;
6625         bool has_dpcd;
6626         struct drm_display_mode *scan;
6627         struct edid *edid;
6628         enum pipe pipe = INVALID_PIPE;
6629
6630         if (!intel_dp_is_edp(intel_dp))
6631                 return true;
6632
6633         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
6634
6635         /*
6636          * On IBX/CPT we may get here with LVDS already registered. Since the
6637          * driver uses the only internal power sequencer available for both
6638          * eDP and LVDS bail out early in this case to prevent interfering
6639          * with an already powered-on LVDS power sequencer.
6640          */
6641         if (intel_get_lvds_encoder(&dev_priv->drm)) {
6642                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6643                 DRM_INFO("LVDS was detected, not registering eDP\n");
6644
6645                 return false;
6646         }
6647
6648         pps_lock(intel_dp);
6649
6650         intel_dp_init_panel_power_timestamps(intel_dp);
6651         intel_dp_pps_init(intel_dp);
6652         intel_edp_panel_vdd_sanitize(intel_dp);
6653
6654         pps_unlock(intel_dp);
6655
6656         /* Cache DPCD and EDID for edp. */
6657         has_dpcd = intel_edp_init_dpcd(intel_dp);
6658
6659         if (!has_dpcd) {
6660                 /* if this fails, presume the device is a ghost */
6661                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6662                 goto out_vdd_off;
6663         }
6664
6665         mutex_lock(&dev->mode_config.mutex);
6666         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6667         if (edid) {
6668                 if (drm_add_edid_modes(connector, edid)) {
6669                         drm_connector_update_edid_property(connector,
6670                                                                 edid);
6671                 } else {
6672                         kfree(edid);
6673                         edid = ERR_PTR(-EINVAL);
6674                 }
6675         } else {
6676                 edid = ERR_PTR(-ENOENT);
6677         }
6678         intel_connector->edid = edid;
6679
6680         /* prefer fixed mode from EDID if available */
6681         list_for_each_entry(scan, &connector->probed_modes, head) {
6682                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
6683                         fixed_mode = drm_mode_duplicate(dev, scan);
6684                         downclock_mode = intel_dp_drrs_init(
6685                                                 intel_connector, fixed_mode);
6686                         break;
6687                 }
6688         }
6689
6690         /* fallback to VBT if available for eDP */
6691         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
6692                 fixed_mode = drm_mode_duplicate(dev,
6693                                         dev_priv->vbt.lfp_lvds_vbt_mode);
6694                 if (fixed_mode) {
6695                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
6696                         connector->display_info.width_mm = fixed_mode->width_mm;
6697                         connector->display_info.height_mm = fixed_mode->height_mm;
6698                 }
6699         }
6700         mutex_unlock(&dev->mode_config.mutex);
6701
6702         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6703                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
6704                 register_reboot_notifier(&intel_dp->edp_notifier);
6705
6706                 /*
6707                  * Figure out the current pipe for the initial backlight setup.
6708                  * If the current pipe isn't valid, try the PPS pipe, and if that
6709                  * fails just assume pipe A.
6710                  */
6711                 pipe = vlv_active_pipe(intel_dp);
6712
6713                 if (pipe != PIPE_A && pipe != PIPE_B)
6714                         pipe = intel_dp->pps_pipe;
6715
6716                 if (pipe != PIPE_A && pipe != PIPE_B)
6717                         pipe = PIPE_A;
6718
6719                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6720                               pipe_name(pipe));
6721         }
6722
6723         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6724         intel_connector->panel.backlight.power = intel_edp_backlight_power;
6725         intel_panel_setup_backlight(connector, pipe);
6726
6727         if (fixed_mode)
6728                 drm_connector_init_panel_orientation_property(
6729                         connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
6730
6731         return true;
6732
6733 out_vdd_off:
6734         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6735         /*
6736          * vdd might still be enabled do to the delayed vdd off.
6737          * Make sure vdd is actually turned off here.
6738          */
6739         pps_lock(intel_dp);
6740         edp_panel_vdd_off_sync(intel_dp);
6741         pps_unlock(intel_dp);
6742
6743         return false;
6744 }
6745
6746 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6747 {
6748         struct intel_connector *intel_connector;
6749         struct drm_connector *connector;
6750
6751         intel_connector = container_of(work, typeof(*intel_connector),
6752                                        modeset_retry_work);
6753         connector = &intel_connector->base;
6754         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6755                       connector->name);
6756
6757         /* Grab the locks before changing connector property*/
6758         mutex_lock(&connector->dev->mode_config.mutex);
6759         /* Set connector link status to BAD and send a Uevent to notify
6760          * userspace to do a modeset.
6761          */
6762         drm_connector_set_link_status_property(connector,
6763                                                DRM_MODE_LINK_STATUS_BAD);
6764         mutex_unlock(&connector->dev->mode_config.mutex);
6765         /* Send Hotplug uevent so userspace can reprobe */
6766         drm_kms_helper_hotplug_event(connector->dev);
6767 }
6768
6769 bool
6770 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6771                         struct intel_connector *intel_connector)
6772 {
6773         struct drm_connector *connector = &intel_connector->base;
6774         struct intel_dp *intel_dp = &intel_dig_port->dp;
6775         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6776         struct drm_device *dev = intel_encoder->base.dev;
6777         struct drm_i915_private *dev_priv = to_i915(dev);
6778         enum port port = intel_encoder->port;
6779         int type;
6780
6781         /* Initialize the work for modeset in case of link train failure */
6782         INIT_WORK(&intel_connector->modeset_retry_work,
6783                   intel_dp_modeset_retry_work_fn);
6784
6785         if (WARN(intel_dig_port->max_lanes < 1,
6786                  "Not enough lanes (%d) for DP on port %c\n",
6787                  intel_dig_port->max_lanes, port_name(port)))
6788                 return false;
6789
6790         intel_dp_set_source_rates(intel_dp);
6791
6792         intel_dp->reset_link_params = true;
6793         intel_dp->pps_pipe = INVALID_PIPE;
6794         intel_dp->active_pipe = INVALID_PIPE;
6795
6796         /* intel_dp vfuncs */
6797         if (HAS_DDI(dev_priv))
6798                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6799
6800         /* Preserve the current hw state. */
6801         intel_dp->DP = I915_READ(intel_dp->output_reg);
6802         intel_dp->attached_connector = intel_connector;
6803
6804         if (intel_dp_is_port_edp(dev_priv, port))
6805                 type = DRM_MODE_CONNECTOR_eDP;
6806         else
6807                 type = DRM_MODE_CONNECTOR_DisplayPort;
6808
6809         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6810                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6811
6812         /*
6813          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6814          * for DP the encoder type can be set by the caller to
6815          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6816          */
6817         if (type == DRM_MODE_CONNECTOR_eDP)
6818                 intel_encoder->type = INTEL_OUTPUT_EDP;
6819
6820         /* eDP only on port B and/or C on vlv/chv */
6821         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6822                     intel_dp_is_edp(intel_dp) &&
6823                     port != PORT_B && port != PORT_C))
6824                 return false;
6825
6826         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6827                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6828                         port_name(port));
6829
6830         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6831         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6832
6833         if (!HAS_GMCH_DISPLAY(dev_priv))
6834                 connector->interlace_allowed = true;
6835         connector->doublescan_allowed = 0;
6836
6837         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
6838
6839         intel_dp_aux_init(intel_dp);
6840
6841         intel_connector_attach_encoder(intel_connector, intel_encoder);
6842
6843         if (HAS_DDI(dev_priv))
6844                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6845         else
6846                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6847
6848         /* init MST on ports that can support it */
6849         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6850             (port == PORT_B || port == PORT_C ||
6851              port == PORT_D || port == PORT_F))
6852                 intel_dp_mst_encoder_init(intel_dig_port,
6853                                           intel_connector->base.base.id);
6854
6855         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6856                 intel_dp_aux_fini(intel_dp);
6857                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6858                 goto fail;
6859         }
6860
6861         intel_dp_add_properties(intel_dp, connector);
6862
6863         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6864                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
6865                 if (ret)
6866                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6867         }
6868
6869         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6870          * 0xd.  Failure to do so will result in spurious interrupts being
6871          * generated on the port when a cable is not attached.
6872          */
6873         if (IS_G45(dev_priv)) {
6874                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6875                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6876         }
6877
6878         return true;
6879
6880 fail:
6881         drm_connector_cleanup(connector);
6882
6883         return false;
6884 }
6885
6886 bool intel_dp_init(struct drm_i915_private *dev_priv,
6887                    i915_reg_t output_reg,
6888                    enum port port)
6889 {
6890         struct intel_digital_port *intel_dig_port;
6891         struct intel_encoder *intel_encoder;
6892         struct drm_encoder *encoder;
6893         struct intel_connector *intel_connector;
6894
6895         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6896         if (!intel_dig_port)
6897                 return false;
6898
6899         intel_connector = intel_connector_alloc();
6900         if (!intel_connector)
6901                 goto err_connector_alloc;
6902
6903         intel_encoder = &intel_dig_port->base;
6904         encoder = &intel_encoder->base;
6905
6906         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6907                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6908                              "DP %c", port_name(port)))
6909                 goto err_encoder_init;
6910
6911         intel_encoder->hotplug = intel_dp_hotplug;
6912         intel_encoder->compute_config = intel_dp_compute_config;
6913         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6914         intel_encoder->get_config = intel_dp_get_config;
6915         intel_encoder->suspend = intel_dp_encoder_suspend;
6916         if (IS_CHERRYVIEW(dev_priv)) {
6917                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6918                 intel_encoder->pre_enable = chv_pre_enable_dp;
6919                 intel_encoder->enable = vlv_enable_dp;
6920                 intel_encoder->disable = vlv_disable_dp;
6921                 intel_encoder->post_disable = chv_post_disable_dp;
6922                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6923         } else if (IS_VALLEYVIEW(dev_priv)) {
6924                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6925                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6926                 intel_encoder->enable = vlv_enable_dp;
6927                 intel_encoder->disable = vlv_disable_dp;
6928                 intel_encoder->post_disable = vlv_post_disable_dp;
6929         } else {
6930                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6931                 intel_encoder->enable = g4x_enable_dp;
6932                 intel_encoder->disable = g4x_disable_dp;
6933                 intel_encoder->post_disable = g4x_post_disable_dp;
6934         }
6935
6936         intel_dig_port->dp.output_reg = output_reg;
6937         intel_dig_port->max_lanes = 4;
6938
6939         intel_encoder->type = INTEL_OUTPUT_DP;
6940         intel_encoder->power_domain = intel_port_to_power_domain(port);
6941         if (IS_CHERRYVIEW(dev_priv)) {
6942                 if (port == PORT_D)
6943                         intel_encoder->crtc_mask = 1 << 2;
6944                 else
6945                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6946         } else {
6947                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6948         }
6949         intel_encoder->cloneable = 0;
6950         intel_encoder->port = port;
6951
6952         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6953
6954         if (port != PORT_A)
6955                 intel_infoframe_init(intel_dig_port);
6956
6957         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
6958         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6959                 goto err_init_connector;
6960
6961         return true;
6962
6963 err_init_connector:
6964         drm_encoder_cleanup(encoder);
6965 err_encoder_init:
6966         kfree(intel_connector);
6967 err_connector_alloc:
6968         kfree(intel_dig_port);
6969         return false;
6970 }
6971
6972 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6973 {
6974         struct intel_encoder *encoder;
6975
6976         for_each_intel_encoder(&dev_priv->drm, encoder) {
6977                 struct intel_dp *intel_dp;
6978
6979                 if (encoder->type != INTEL_OUTPUT_DDI)
6980                         continue;
6981
6982                 intel_dp = enc_to_intel_dp(&encoder->base);
6983
6984                 if (!intel_dp->can_mst)
6985                         continue;
6986
6987                 if (intel_dp->is_mst)
6988                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6989         }
6990 }
6991
6992 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6993 {
6994         struct intel_encoder *encoder;
6995
6996         for_each_intel_encoder(&dev_priv->drm, encoder) {
6997                 struct intel_dp *intel_dp;
6998                 int ret;
6999
7000                 if (encoder->type != INTEL_OUTPUT_DDI)
7001                         continue;
7002
7003                 intel_dp = enc_to_intel_dp(&encoder->base);
7004
7005                 if (!intel_dp->can_mst)
7006                         continue;
7007
7008                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
7009                 if (ret)
7010                         intel_dp_check_mst_status(intel_dp);
7011         }
7012 }