2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_edid.h>
40 #include "intel_drv.h"
41 #include <drm/i915_drm.h>
44 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
46 /* Compliance test status bits */
47 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
48 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
50 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
57 static const struct dp_link_dpll gen4_dpll[] = {
59 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
61 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
64 static const struct dp_link_dpll pch_dpll[] = {
66 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
68 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
71 static const struct dp_link_dpll vlv_dpll[] = {
73 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
75 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
79 * CHV supports eDP 1.4 that have more link rates.
80 * Below only provides the fixed rate but exclude variable rate.
82 static const struct dp_link_dpll chv_dpll[] = {
84 * CHV requires to program fractional division for m2.
85 * m2 is stored in fixed point format using formula below
86 * (m2_int << 22) | m2_fraction
88 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
89 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
90 { 270000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
92 { 540000, /* m2_int = 27, m2_fraction = 0 */
93 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
96 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
97 324000, 432000, 540000 };
98 static const int skl_rates[] = { 162000, 216000, 270000,
99 324000, 432000, 540000 };
100 static const int default_rates[] = { 162000, 270000, 540000 };
103 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
104 * @intel_dp: DP struct
106 * If a CPU or PCH DP output is attached to an eDP panel, this function
107 * will return true, and false otherwise.
109 static bool is_edp(struct intel_dp *intel_dp)
111 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
113 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
116 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
118 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
120 return intel_dig_port->base.base.dev;
123 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
125 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
128 static void intel_dp_link_down(struct intel_dp *intel_dp);
129 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
130 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
131 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
132 static void vlv_steal_power_sequencer(struct drm_device *dev,
134 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
137 intel_dp_max_link_bw(struct intel_dp *intel_dp)
139 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
141 switch (max_link_bw) {
142 case DP_LINK_BW_1_62:
147 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
149 max_link_bw = DP_LINK_BW_1_62;
155 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
157 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
158 u8 source_max, sink_max;
160 source_max = intel_dig_port->max_lanes;
161 sink_max = intel_dp->max_sink_lane_count;
163 return min(source_max, sink_max);
167 intel_dp_link_required(int pixel_clock, int bpp)
169 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
170 return DIV_ROUND_UP(pixel_clock * bpp, 8);
174 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
176 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
177 * link rate that is generally expressed in Gbps. Since, 8 bits of data
178 * is transmitted every LS_Clk per lane, there is no need to account for
179 * the channel encoding that is done in the PHY layer here.
182 return max_link_clock * max_lanes;
186 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
188 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
189 struct intel_encoder *encoder = &intel_dig_port->base;
190 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
191 int max_dotclk = dev_priv->max_dotclk_freq;
194 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
196 if (type != DP_DS_PORT_TYPE_VGA)
199 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
200 intel_dp->downstream_ports);
202 if (ds_max_dotclk != 0)
203 max_dotclk = min(max_dotclk, ds_max_dotclk);
209 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
211 if (intel_dp->num_sink_rates) {
212 *sink_rates = intel_dp->sink_rates;
213 return intel_dp->num_sink_rates;
216 *sink_rates = default_rates;
218 return (intel_dp->max_sink_link_bw >> 3) + 1;
222 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
224 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
225 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
228 if (IS_GEN9_LP(dev_priv)) {
229 *source_rates = bxt_rates;
230 size = ARRAY_SIZE(bxt_rates);
231 } else if (IS_GEN9_BC(dev_priv)) {
232 *source_rates = skl_rates;
233 size = ARRAY_SIZE(skl_rates);
235 *source_rates = default_rates;
236 size = ARRAY_SIZE(default_rates);
239 /* This depends on the fact that 5.4 is last value in the array */
240 if (!intel_dp_source_supports_hbr2(intel_dp))
246 static int intersect_rates(const int *source_rates, int source_len,
247 const int *sink_rates, int sink_len,
250 int i = 0, j = 0, k = 0;
252 while (i < source_len && j < sink_len) {
253 if (source_rates[i] == sink_rates[j]) {
254 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
256 common_rates[k] = source_rates[i];
260 } else if (source_rates[i] < sink_rates[j]) {
269 static int intel_dp_common_rates(struct intel_dp *intel_dp,
272 const int *source_rates, *sink_rates;
273 int source_len, sink_len;
275 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
276 source_len = intel_dp_source_rates(intel_dp, &source_rates);
278 return intersect_rates(source_rates, source_len,
279 sink_rates, sink_len,
283 static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
284 int *common_rates, int link_rate)
289 common_len = intel_dp_common_rates(intel_dp, common_rates);
290 for (index = 0; index < common_len; index++) {
291 if (link_rate == common_rates[common_len - index - 1])
292 return common_len - index - 1;
298 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
299 int link_rate, uint8_t lane_count)
301 int common_rates[DP_MAX_SUPPORTED_RATES];
304 link_rate_index = intel_dp_link_rate_index(intel_dp,
307 if (link_rate_index > 0) {
308 intel_dp->max_sink_link_bw = drm_dp_link_rate_to_bw_code(common_rates[link_rate_index - 1]);
309 intel_dp->max_sink_lane_count = lane_count;
310 } else if (lane_count > 1) {
311 intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
312 intel_dp->max_sink_lane_count = lane_count >> 1;
314 DRM_ERROR("Link Training Unsuccessful\n");
321 static enum drm_mode_status
322 intel_dp_mode_valid(struct drm_connector *connector,
323 struct drm_display_mode *mode)
325 struct intel_dp *intel_dp = intel_attached_dp(connector);
326 struct intel_connector *intel_connector = to_intel_connector(connector);
327 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
328 int target_clock = mode->clock;
329 int max_rate, mode_rate, max_lanes, max_link_clock;
332 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
334 if (is_edp(intel_dp) && fixed_mode) {
335 if (mode->hdisplay > fixed_mode->hdisplay)
338 if (mode->vdisplay > fixed_mode->vdisplay)
341 target_clock = fixed_mode->clock;
344 max_link_clock = intel_dp_max_link_rate(intel_dp);
345 max_lanes = intel_dp_max_lane_count(intel_dp);
347 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
348 mode_rate = intel_dp_link_required(target_clock, 18);
350 if (mode_rate > max_rate || target_clock > max_dotclk)
351 return MODE_CLOCK_HIGH;
353 if (mode->clock < 10000)
354 return MODE_CLOCK_LOW;
356 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
357 return MODE_H_ILLEGAL;
362 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
369 for (i = 0; i < src_bytes; i++)
370 v |= ((uint32_t) src[i]) << ((3-i) * 8);
374 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
379 for (i = 0; i < dst_bytes; i++)
380 dst[i] = src >> ((3-i) * 8);
384 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
385 struct intel_dp *intel_dp);
387 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
388 struct intel_dp *intel_dp,
389 bool force_disable_vdd);
391 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
393 static void pps_lock(struct intel_dp *intel_dp)
395 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
396 struct intel_encoder *encoder = &intel_dig_port->base;
397 struct drm_device *dev = encoder->base.dev;
398 struct drm_i915_private *dev_priv = to_i915(dev);
401 * See vlv_power_sequencer_reset() why we need
402 * a power domain reference here.
404 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
406 mutex_lock(&dev_priv->pps_mutex);
409 static void pps_unlock(struct intel_dp *intel_dp)
411 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
412 struct intel_encoder *encoder = &intel_dig_port->base;
413 struct drm_device *dev = encoder->base.dev;
414 struct drm_i915_private *dev_priv = to_i915(dev);
416 mutex_unlock(&dev_priv->pps_mutex);
418 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
422 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
425 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
426 enum pipe pipe = intel_dp->pps_pipe;
427 bool pll_enabled, release_cl_override = false;
428 enum dpio_phy phy = DPIO_PHY(pipe);
429 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
432 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
433 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
434 pipe_name(pipe), port_name(intel_dig_port->port)))
437 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
438 pipe_name(pipe), port_name(intel_dig_port->port));
440 /* Preserve the BIOS-computed detected bit. This is
441 * supposed to be read-only.
443 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
444 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
445 DP |= DP_PORT_WIDTH(1);
446 DP |= DP_LINK_TRAIN_PAT_1;
448 if (IS_CHERRYVIEW(dev_priv))
449 DP |= DP_PIPE_SELECT_CHV(pipe);
450 else if (pipe == PIPE_B)
451 DP |= DP_PIPEB_SELECT;
453 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
456 * The DPLL for the pipe must be enabled for this to work.
457 * So enable temporarily it if it's not already enabled.
460 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
461 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
463 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
464 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
465 DRM_ERROR("Failed to force on pll for pipe %c!\n",
472 * Similar magic as in intel_dp_enable_port().
473 * We _must_ do this port enable + disable trick
474 * to make this power seqeuencer lock onto the port.
475 * Otherwise even VDD force bit won't work.
477 I915_WRITE(intel_dp->output_reg, DP);
478 POSTING_READ(intel_dp->output_reg);
480 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
481 POSTING_READ(intel_dp->output_reg);
483 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
484 POSTING_READ(intel_dp->output_reg);
487 vlv_force_pll_off(dev_priv, pipe);
489 if (release_cl_override)
490 chv_phy_powergate_ch(dev_priv, phy, ch, false);
494 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
496 struct intel_encoder *encoder;
497 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
500 * We don't have power sequencer currently.
501 * Pick one that's not used by other ports.
503 for_each_intel_encoder(&dev_priv->drm, encoder) {
504 struct intel_dp *intel_dp;
506 if (encoder->type != INTEL_OUTPUT_DP &&
507 encoder->type != INTEL_OUTPUT_EDP)
510 intel_dp = enc_to_intel_dp(&encoder->base);
512 if (encoder->type == INTEL_OUTPUT_EDP) {
513 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
514 intel_dp->active_pipe != intel_dp->pps_pipe);
516 if (intel_dp->pps_pipe != INVALID_PIPE)
517 pipes &= ~(1 << intel_dp->pps_pipe);
519 WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
521 if (intel_dp->active_pipe != INVALID_PIPE)
522 pipes &= ~(1 << intel_dp->active_pipe);
529 return ffs(pipes) - 1;
533 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
535 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
536 struct drm_device *dev = intel_dig_port->base.base.dev;
537 struct drm_i915_private *dev_priv = to_i915(dev);
540 lockdep_assert_held(&dev_priv->pps_mutex);
542 /* We should never land here with regular DP ports */
543 WARN_ON(!is_edp(intel_dp));
545 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
546 intel_dp->active_pipe != intel_dp->pps_pipe);
548 if (intel_dp->pps_pipe != INVALID_PIPE)
549 return intel_dp->pps_pipe;
551 pipe = vlv_find_free_pps(dev_priv);
554 * Didn't find one. This should not happen since there
555 * are two power sequencers and up to two eDP ports.
557 if (WARN_ON(pipe == INVALID_PIPE))
560 vlv_steal_power_sequencer(dev, pipe);
561 intel_dp->pps_pipe = pipe;
563 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
564 pipe_name(intel_dp->pps_pipe),
565 port_name(intel_dig_port->port));
567 /* init power sequencer on this pipe and port */
568 intel_dp_init_panel_power_sequencer(dev, intel_dp);
569 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
572 * Even vdd force doesn't work until we've made
573 * the power sequencer lock in on the port.
575 vlv_power_sequencer_kick(intel_dp);
577 return intel_dp->pps_pipe;
581 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
583 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
584 struct drm_device *dev = intel_dig_port->base.base.dev;
585 struct drm_i915_private *dev_priv = to_i915(dev);
587 lockdep_assert_held(&dev_priv->pps_mutex);
589 /* We should never land here with regular DP ports */
590 WARN_ON(!is_edp(intel_dp));
593 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
594 * mapping needs to be retrieved from VBT, for now just hard-code to
595 * use instance #0 always.
597 if (!intel_dp->pps_reset)
600 intel_dp->pps_reset = false;
603 * Only the HW needs to be reprogrammed, the SW state is fixed and
604 * has been setup during connector init.
606 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
611 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
614 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
617 return I915_READ(PP_STATUS(pipe)) & PP_ON;
620 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
623 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
626 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
633 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
635 vlv_pipe_check pipe_check)
639 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
640 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
641 PANEL_PORT_SELECT_MASK;
643 if (port_sel != PANEL_PORT_SELECT_VLV(port))
646 if (!pipe_check(dev_priv, pipe))
656 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
658 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
659 struct drm_device *dev = intel_dig_port->base.base.dev;
660 struct drm_i915_private *dev_priv = to_i915(dev);
661 enum port port = intel_dig_port->port;
663 lockdep_assert_held(&dev_priv->pps_mutex);
665 /* try to find a pipe with this port selected */
666 /* first pick one where the panel is on */
667 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
669 /* didn't find one? pick one where vdd is on */
670 if (intel_dp->pps_pipe == INVALID_PIPE)
671 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
672 vlv_pipe_has_vdd_on);
673 /* didn't find one? pick one with just the correct port */
674 if (intel_dp->pps_pipe == INVALID_PIPE)
675 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
678 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
679 if (intel_dp->pps_pipe == INVALID_PIPE) {
680 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
685 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
686 port_name(port), pipe_name(intel_dp->pps_pipe));
688 intel_dp_init_panel_power_sequencer(dev, intel_dp);
689 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
692 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
694 struct drm_device *dev = &dev_priv->drm;
695 struct intel_encoder *encoder;
697 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
698 !IS_GEN9_LP(dev_priv)))
702 * We can't grab pps_mutex here due to deadlock with power_domain
703 * mutex when power_domain functions are called while holding pps_mutex.
704 * That also means that in order to use pps_pipe the code needs to
705 * hold both a power domain reference and pps_mutex, and the power domain
706 * reference get/put must be done while _not_ holding pps_mutex.
707 * pps_{lock,unlock}() do these steps in the correct order, so one
708 * should use them always.
711 for_each_intel_encoder(dev, encoder) {
712 struct intel_dp *intel_dp;
714 if (encoder->type != INTEL_OUTPUT_DP &&
715 encoder->type != INTEL_OUTPUT_EDP)
718 intel_dp = enc_to_intel_dp(&encoder->base);
720 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
722 if (encoder->type != INTEL_OUTPUT_EDP)
725 if (IS_GEN9_LP(dev_priv))
726 intel_dp->pps_reset = true;
728 intel_dp->pps_pipe = INVALID_PIPE;
732 struct pps_registers {
740 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
741 struct intel_dp *intel_dp,
742 struct pps_registers *regs)
746 memset(regs, 0, sizeof(*regs));
748 if (IS_GEN9_LP(dev_priv))
749 pps_idx = bxt_power_sequencer_idx(intel_dp);
750 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
751 pps_idx = vlv_power_sequencer_pipe(intel_dp);
753 regs->pp_ctrl = PP_CONTROL(pps_idx);
754 regs->pp_stat = PP_STATUS(pps_idx);
755 regs->pp_on = PP_ON_DELAYS(pps_idx);
756 regs->pp_off = PP_OFF_DELAYS(pps_idx);
757 if (!IS_GEN9_LP(dev_priv))
758 regs->pp_div = PP_DIVISOR(pps_idx);
762 _pp_ctrl_reg(struct intel_dp *intel_dp)
764 struct pps_registers regs;
766 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
773 _pp_stat_reg(struct intel_dp *intel_dp)
775 struct pps_registers regs;
777 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
783 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
784 This function only applicable when panel PM state is not to be tracked */
785 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
788 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
790 struct drm_device *dev = intel_dp_to_dev(intel_dp);
791 struct drm_i915_private *dev_priv = to_i915(dev);
793 if (!is_edp(intel_dp) || code != SYS_RESTART)
798 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
799 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
800 i915_reg_t pp_ctrl_reg, pp_div_reg;
803 pp_ctrl_reg = PP_CONTROL(pipe);
804 pp_div_reg = PP_DIVISOR(pipe);
805 pp_div = I915_READ(pp_div_reg);
806 pp_div &= PP_REFERENCE_DIVIDER_MASK;
808 /* 0x1F write to PP_DIV_REG sets max cycle delay */
809 I915_WRITE(pp_div_reg, pp_div | 0x1F);
810 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
811 msleep(intel_dp->panel_power_cycle_delay);
814 pps_unlock(intel_dp);
819 static bool edp_have_panel_power(struct intel_dp *intel_dp)
821 struct drm_device *dev = intel_dp_to_dev(intel_dp);
822 struct drm_i915_private *dev_priv = to_i915(dev);
824 lockdep_assert_held(&dev_priv->pps_mutex);
826 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
827 intel_dp->pps_pipe == INVALID_PIPE)
830 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
833 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
835 struct drm_device *dev = intel_dp_to_dev(intel_dp);
836 struct drm_i915_private *dev_priv = to_i915(dev);
838 lockdep_assert_held(&dev_priv->pps_mutex);
840 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
841 intel_dp->pps_pipe == INVALID_PIPE)
844 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
848 intel_dp_check_edp(struct intel_dp *intel_dp)
850 struct drm_device *dev = intel_dp_to_dev(intel_dp);
851 struct drm_i915_private *dev_priv = to_i915(dev);
853 if (!is_edp(intel_dp))
856 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
857 WARN(1, "eDP powered off while attempting aux channel communication.\n");
858 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
859 I915_READ(_pp_stat_reg(intel_dp)),
860 I915_READ(_pp_ctrl_reg(intel_dp)));
865 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
867 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
868 struct drm_device *dev = intel_dig_port->base.base.dev;
869 struct drm_i915_private *dev_priv = to_i915(dev);
870 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
874 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
876 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
877 msecs_to_jiffies_timeout(10));
879 done = wait_for(C, 10) == 0;
881 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
888 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
890 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
891 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
897 * The clock divider is based off the hrawclk, and would like to run at
898 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
900 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
903 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
905 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
906 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
912 * The clock divider is based off the cdclk or PCH rawclk, and would
913 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
914 * divide by 2000 and use that
916 if (intel_dig_port->port == PORT_A)
917 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
919 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
922 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
924 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
925 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
927 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
928 /* Workaround for non-ULT HSW */
936 return ilk_get_aux_clock_divider(intel_dp, index);
939 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
942 * SKL doesn't need us to program the AUX clock divider (Hardware will
943 * derive the clock from CDCLK automatically). We still implement the
944 * get_aux_clock_divider vfunc to plug-in into the existing code.
946 return index ? 0 : 1;
949 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
952 uint32_t aux_clock_divider)
954 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
955 struct drm_i915_private *dev_priv =
956 to_i915(intel_dig_port->base.base.dev);
957 uint32_t precharge, timeout;
959 if (IS_GEN6(dev_priv))
964 if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
965 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
967 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
969 return DP_AUX_CH_CTL_SEND_BUSY |
971 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
972 DP_AUX_CH_CTL_TIME_OUT_ERROR |
974 DP_AUX_CH_CTL_RECEIVE_ERROR |
975 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
976 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
977 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
980 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
985 return DP_AUX_CH_CTL_SEND_BUSY |
987 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
988 DP_AUX_CH_CTL_TIME_OUT_ERROR |
989 DP_AUX_CH_CTL_TIME_OUT_1600us |
990 DP_AUX_CH_CTL_RECEIVE_ERROR |
991 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
992 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
993 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
997 intel_dp_aux_ch(struct intel_dp *intel_dp,
998 const uint8_t *send, int send_bytes,
999 uint8_t *recv, int recv_size)
1001 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1002 struct drm_i915_private *dev_priv =
1003 to_i915(intel_dig_port->base.base.dev);
1004 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1005 uint32_t aux_clock_divider;
1006 int i, ret, recv_bytes;
1009 bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1015 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1016 * In such cases we want to leave VDD enabled and it's up to upper layers
1017 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1020 vdd = edp_panel_vdd_on(intel_dp);
1022 /* dp aux is extremely sensitive to irq latency, hence request the
1023 * lowest possible wakeup latency and so prevent the cpu from going into
1024 * deep sleep states.
1026 pm_qos_update_request(&dev_priv->pm_qos, 0);
1028 intel_dp_check_edp(intel_dp);
1030 /* Try to wait for any previous AUX channel activity */
1031 for (try = 0; try < 3; try++) {
1032 status = I915_READ_NOTRACE(ch_ctl);
1033 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1039 static u32 last_status = -1;
1040 const u32 status = I915_READ(ch_ctl);
1042 if (status != last_status) {
1043 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1045 last_status = status;
1052 /* Only 5 data registers! */
1053 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1058 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1059 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1064 /* Must try at least 3 times according to DP spec */
1065 for (try = 0; try < 5; try++) {
1066 /* Load the send data into the aux channel data registers */
1067 for (i = 0; i < send_bytes; i += 4)
1068 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1069 intel_dp_pack_aux(send + i,
1072 /* Send the command and wait for it to complete */
1073 I915_WRITE(ch_ctl, send_ctl);
1075 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1077 /* Clear done status and any errors */
1080 DP_AUX_CH_CTL_DONE |
1081 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1082 DP_AUX_CH_CTL_RECEIVE_ERROR);
1084 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1087 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1088 * 400us delay required for errors and timeouts
1089 * Timeout errors from the HW already meet this
1090 * requirement so skip to next iteration
1092 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1093 usleep_range(400, 500);
1096 if (status & DP_AUX_CH_CTL_DONE)
1101 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1102 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1108 /* Check for timeout or receive error.
1109 * Timeouts occur when the sink is not connected
1111 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1112 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1117 /* Timeouts occur when the device isn't connected, so they're
1118 * "normal" -- don't fill the kernel log with these */
1119 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1120 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1125 /* Unload any bytes sent back from the other side */
1126 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1127 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1130 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1131 * We have no idea of what happened so we return -EBUSY so
1132 * drm layer takes care for the necessary retries.
1134 if (recv_bytes == 0 || recv_bytes > 20) {
1135 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1138 * FIXME: This patch was created on top of a series that
1139 * organize the retries at drm level. There EBUSY should
1140 * also take care for 1ms wait before retrying.
1141 * That aux retries re-org is still needed and after that is
1142 * merged we remove this sleep from here.
1144 usleep_range(1000, 1500);
1149 if (recv_bytes > recv_size)
1150 recv_bytes = recv_size;
1152 for (i = 0; i < recv_bytes; i += 4)
1153 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1154 recv + i, recv_bytes - i);
1158 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1161 edp_panel_vdd_off(intel_dp, false);
1163 pps_unlock(intel_dp);
1168 #define BARE_ADDRESS_SIZE 3
1169 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1171 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1173 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1174 uint8_t txbuf[20], rxbuf[20];
1175 size_t txsize, rxsize;
1178 txbuf[0] = (msg->request << 4) |
1179 ((msg->address >> 16) & 0xf);
1180 txbuf[1] = (msg->address >> 8) & 0xff;
1181 txbuf[2] = msg->address & 0xff;
1182 txbuf[3] = msg->size - 1;
1184 switch (msg->request & ~DP_AUX_I2C_MOT) {
1185 case DP_AUX_NATIVE_WRITE:
1186 case DP_AUX_I2C_WRITE:
1187 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1188 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1189 rxsize = 2; /* 0 or 1 data bytes */
1191 if (WARN_ON(txsize > 20))
1194 WARN_ON(!msg->buffer != !msg->size);
1197 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1199 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1201 msg->reply = rxbuf[0] >> 4;
1204 /* Number of bytes written in a short write. */
1205 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1207 /* Return payload size. */
1213 case DP_AUX_NATIVE_READ:
1214 case DP_AUX_I2C_READ:
1215 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1216 rxsize = msg->size + 1;
1218 if (WARN_ON(rxsize > 20))
1221 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1223 msg->reply = rxbuf[0] >> 4;
1225 * Assume happy day, and copy the data. The caller is
1226 * expected to check msg->reply before touching it.
1228 * Return payload size.
1231 memcpy(msg->buffer, rxbuf + 1, ret);
1243 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1246 const struct ddi_vbt_port_info *info =
1247 &dev_priv->vbt.ddi_port_info[port];
1250 if (!info->alternate_aux_channel) {
1251 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1252 port_name(port), port_name(port));
1256 switch (info->alternate_aux_channel) {
1270 MISSING_CASE(info->alternate_aux_channel);
1275 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1276 port_name(aux_port), port_name(port));
1281 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1288 return DP_AUX_CH_CTL(port);
1291 return DP_AUX_CH_CTL(PORT_B);
1295 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1296 enum port port, int index)
1302 return DP_AUX_CH_DATA(port, index);
1305 return DP_AUX_CH_DATA(PORT_B, index);
1309 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1314 return DP_AUX_CH_CTL(port);
1318 return PCH_DP_AUX_CH_CTL(port);
1321 return DP_AUX_CH_CTL(PORT_A);
1325 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1326 enum port port, int index)
1330 return DP_AUX_CH_DATA(port, index);
1334 return PCH_DP_AUX_CH_DATA(port, index);
1337 return DP_AUX_CH_DATA(PORT_A, index);
1341 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1349 return DP_AUX_CH_CTL(port);
1352 return DP_AUX_CH_CTL(PORT_A);
1356 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1357 enum port port, int index)
1364 return DP_AUX_CH_DATA(port, index);
1367 return DP_AUX_CH_DATA(PORT_A, index);
1371 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1374 if (INTEL_INFO(dev_priv)->gen >= 9)
1375 return skl_aux_ctl_reg(dev_priv, port);
1376 else if (HAS_PCH_SPLIT(dev_priv))
1377 return ilk_aux_ctl_reg(dev_priv, port);
1379 return g4x_aux_ctl_reg(dev_priv, port);
1382 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1383 enum port port, int index)
1385 if (INTEL_INFO(dev_priv)->gen >= 9)
1386 return skl_aux_data_reg(dev_priv, port, index);
1387 else if (HAS_PCH_SPLIT(dev_priv))
1388 return ilk_aux_data_reg(dev_priv, port, index);
1390 return g4x_aux_data_reg(dev_priv, port, index);
1393 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1395 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1396 enum port port = intel_aux_port(dev_priv,
1397 dp_to_dig_port(intel_dp)->port);
1400 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1401 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1402 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1406 intel_dp_aux_fini(struct intel_dp *intel_dp)
1408 kfree(intel_dp->aux.name);
1412 intel_dp_aux_init(struct intel_dp *intel_dp)
1414 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1415 enum port port = intel_dig_port->port;
1417 intel_aux_reg_init(intel_dp);
1418 drm_dp_aux_init(&intel_dp->aux);
1420 /* Failure to allocate our preferred name is not critical */
1421 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1422 intel_dp->aux.transfer = intel_dp_aux_transfer;
1425 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1427 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1428 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1430 if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1431 IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
1438 intel_dp_set_clock(struct intel_encoder *encoder,
1439 struct intel_crtc_state *pipe_config)
1441 struct drm_device *dev = encoder->base.dev;
1442 struct drm_i915_private *dev_priv = to_i915(dev);
1443 const struct dp_link_dpll *divisor = NULL;
1446 if (IS_G4X(dev_priv)) {
1447 divisor = gen4_dpll;
1448 count = ARRAY_SIZE(gen4_dpll);
1449 } else if (HAS_PCH_SPLIT(dev_priv)) {
1451 count = ARRAY_SIZE(pch_dpll);
1452 } else if (IS_CHERRYVIEW(dev_priv)) {
1454 count = ARRAY_SIZE(chv_dpll);
1455 } else if (IS_VALLEYVIEW(dev_priv)) {
1457 count = ARRAY_SIZE(vlv_dpll);
1460 if (divisor && count) {
1461 for (i = 0; i < count; i++) {
1462 if (pipe_config->port_clock == divisor[i].clock) {
1463 pipe_config->dpll = divisor[i].dpll;
1464 pipe_config->clock_set = true;
1471 static void snprintf_int_array(char *str, size_t len,
1472 const int *array, int nelem)
1478 for (i = 0; i < nelem; i++) {
1479 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1487 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1489 const int *source_rates, *sink_rates;
1490 int source_len, sink_len, common_len;
1491 int common_rates[DP_MAX_SUPPORTED_RATES];
1492 char str[128]; /* FIXME: too big for stack? */
1494 if ((drm_debug & DRM_UT_KMS) == 0)
1497 source_len = intel_dp_source_rates(intel_dp, &source_rates);
1498 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1499 DRM_DEBUG_KMS("source rates: %s\n", str);
1501 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1502 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1503 DRM_DEBUG_KMS("sink rates: %s\n", str);
1505 common_len = intel_dp_common_rates(intel_dp, common_rates);
1506 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1507 DRM_DEBUG_KMS("common rates: %s\n", str);
1511 __intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc)
1513 u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI :
1516 return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) ==
1520 bool intel_dp_read_desc(struct intel_dp *intel_dp)
1522 struct intel_dp_desc *desc = &intel_dp->desc;
1523 bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] &
1527 if (!__intel_dp_read_desc(intel_dp, desc))
1530 dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id));
1531 DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n",
1532 drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink",
1533 (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)",
1534 dev_id_len, desc->device_id,
1535 desc->hw_rev >> 4, desc->hw_rev & 0xf,
1536 desc->sw_major_rev, desc->sw_minor_rev);
1541 static int rate_to_index(int find, const int *rates)
1545 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1546 if (find == rates[i])
1553 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1555 int rates[DP_MAX_SUPPORTED_RATES] = {};
1558 len = intel_dp_common_rates(intel_dp, rates);
1559 if (WARN_ON(len <= 0))
1562 return rates[len - 1];
1565 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1567 return rate_to_index(rate, intel_dp->sink_rates);
1570 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1571 uint8_t *link_bw, uint8_t *rate_select)
1573 if (intel_dp->num_sink_rates) {
1576 intel_dp_rate_select(intel_dp, port_clock);
1578 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1583 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1584 struct intel_crtc_state *pipe_config)
1588 bpp = pipe_config->pipe_bpp;
1589 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1592 bpp = min(bpp, 3*bpc);
1594 /* For DP Compliance we override the computed bpp for the pipe */
1595 if (intel_dp->compliance.test_data.bpc != 0) {
1596 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
1597 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
1598 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1599 pipe_config->pipe_bpp);
1605 intel_dp_compute_config(struct intel_encoder *encoder,
1606 struct intel_crtc_state *pipe_config,
1607 struct drm_connector_state *conn_state)
1609 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1610 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1611 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1612 enum port port = dp_to_dig_port(intel_dp)->port;
1613 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1614 struct intel_connector *intel_connector = intel_dp->attached_connector;
1615 int lane_count, clock;
1616 int min_lane_count = 1;
1617 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1618 /* Conveniently, the link BW constants become indices with a shift...*/
1621 int link_rate_index;
1623 int link_avail, link_clock;
1624 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1626 uint8_t link_bw, rate_select;
1628 common_len = intel_dp_common_rates(intel_dp, common_rates);
1630 /* No common link rates between source and sink */
1631 WARN_ON(common_len <= 0);
1633 max_clock = common_len - 1;
1635 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1636 pipe_config->has_pch_encoder = true;
1638 pipe_config->has_drrs = false;
1639 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1641 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1642 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1645 if (INTEL_GEN(dev_priv) >= 9) {
1647 ret = skl_update_scaler_crtc(pipe_config);
1652 if (HAS_GMCH_DISPLAY(dev_priv))
1653 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1654 intel_connector->panel.fitting_mode);
1656 intel_pch_panel_fitting(intel_crtc, pipe_config,
1657 intel_connector->panel.fitting_mode);
1660 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1663 /* Use values requested by Compliance Test Request */
1664 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1665 link_rate_index = intel_dp_link_rate_index(intel_dp,
1667 intel_dp->compliance.test_link_rate);
1668 if (link_rate_index >= 0)
1669 min_clock = max_clock = link_rate_index;
1670 min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
1672 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1673 "max bw %d pixel clock %iKHz\n",
1674 max_lane_count, common_rates[max_clock],
1675 adjusted_mode->crtc_clock);
1677 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1678 * bpc in between. */
1679 bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1680 if (is_edp(intel_dp)) {
1682 /* Get bpp from vbt only for panels that dont have bpp in edid */
1683 if (intel_connector->base.display_info.bpc == 0 &&
1684 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1685 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1686 dev_priv->vbt.edp.bpp);
1687 bpp = dev_priv->vbt.edp.bpp;
1691 * Use the maximum clock and number of lanes the eDP panel
1692 * advertizes being capable of. The panels are generally
1693 * designed to support only a single clock and lane
1694 * configuration, and typically these values correspond to the
1695 * native resolution of the panel.
1697 min_lane_count = max_lane_count;
1698 min_clock = max_clock;
1701 for (; bpp >= 6*3; bpp -= 2*3) {
1702 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1705 for (clock = min_clock; clock <= max_clock; clock++) {
1706 for (lane_count = min_lane_count;
1707 lane_count <= max_lane_count;
1710 link_clock = common_rates[clock];
1711 link_avail = intel_dp_max_data_rate(link_clock,
1714 if (mode_rate <= link_avail) {
1724 if (intel_dp->color_range_auto) {
1727 * CEA-861-E - 5.1 Default Encoding Parameters
1728 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1730 pipe_config->limited_color_range =
1732 drm_default_rgb_quant_range(adjusted_mode) ==
1733 HDMI_QUANTIZATION_RANGE_LIMITED;
1735 pipe_config->limited_color_range =
1736 intel_dp->limited_color_range;
1739 pipe_config->lane_count = lane_count;
1741 pipe_config->pipe_bpp = bpp;
1742 pipe_config->port_clock = common_rates[clock];
1744 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1745 &link_bw, &rate_select);
1747 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1748 link_bw, rate_select, pipe_config->lane_count,
1749 pipe_config->port_clock, bpp);
1750 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1751 mode_rate, link_avail);
1753 intel_link_compute_m_n(bpp, lane_count,
1754 adjusted_mode->crtc_clock,
1755 pipe_config->port_clock,
1756 &pipe_config->dp_m_n);
1758 if (intel_connector->panel.downclock_mode != NULL &&
1759 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1760 pipe_config->has_drrs = true;
1761 intel_link_compute_m_n(bpp, lane_count,
1762 intel_connector->panel.downclock_mode->clock,
1763 pipe_config->port_clock,
1764 &pipe_config->dp_m2_n2);
1768 * DPLL0 VCO may need to be adjusted to get the correct
1769 * clock for eDP. This will affect cdclk as well.
1771 if (is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1774 switch (pipe_config->port_clock / 2) {
1784 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1787 if (!HAS_DDI(dev_priv))
1788 intel_dp_set_clock(encoder, pipe_config);
1793 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1794 int link_rate, uint8_t lane_count,
1797 intel_dp->link_rate = link_rate;
1798 intel_dp->lane_count = lane_count;
1799 intel_dp->link_mst = link_mst;
1802 static void intel_dp_prepare(struct intel_encoder *encoder,
1803 struct intel_crtc_state *pipe_config)
1805 struct drm_device *dev = encoder->base.dev;
1806 struct drm_i915_private *dev_priv = to_i915(dev);
1807 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1808 enum port port = dp_to_dig_port(intel_dp)->port;
1809 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1810 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1812 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1813 pipe_config->lane_count,
1814 intel_crtc_has_type(pipe_config,
1815 INTEL_OUTPUT_DP_MST));
1818 * There are four kinds of DP registers:
1825 * IBX PCH and CPU are the same for almost everything,
1826 * except that the CPU DP PLL is configured in this
1829 * CPT PCH is quite different, having many bits moved
1830 * to the TRANS_DP_CTL register instead. That
1831 * configuration happens (oddly) in ironlake_pch_enable
1834 /* Preserve the BIOS-computed detected bit. This is
1835 * supposed to be read-only.
1837 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1839 /* Handle DP bits in common between all three register formats */
1840 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1841 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1843 /* Split out the IBX/CPU vs CPT settings */
1845 if (IS_GEN7(dev_priv) && port == PORT_A) {
1846 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1847 intel_dp->DP |= DP_SYNC_HS_HIGH;
1848 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1849 intel_dp->DP |= DP_SYNC_VS_HIGH;
1850 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1852 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1853 intel_dp->DP |= DP_ENHANCED_FRAMING;
1855 intel_dp->DP |= crtc->pipe << 29;
1856 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1859 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1861 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1862 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1863 trans_dp |= TRANS_DP_ENH_FRAMING;
1865 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1866 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1868 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1869 intel_dp->DP |= DP_COLOR_RANGE_16_235;
1871 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1872 intel_dp->DP |= DP_SYNC_HS_HIGH;
1873 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1874 intel_dp->DP |= DP_SYNC_VS_HIGH;
1875 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1877 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1878 intel_dp->DP |= DP_ENHANCED_FRAMING;
1880 if (IS_CHERRYVIEW(dev_priv))
1881 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1882 else if (crtc->pipe == PIPE_B)
1883 intel_dp->DP |= DP_PIPEB_SELECT;
1887 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1888 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1890 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1891 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1893 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1894 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1896 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1897 struct intel_dp *intel_dp);
1899 static void wait_panel_status(struct intel_dp *intel_dp,
1903 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1904 struct drm_i915_private *dev_priv = to_i915(dev);
1905 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1907 lockdep_assert_held(&dev_priv->pps_mutex);
1909 intel_pps_verify_state(dev_priv, intel_dp);
1911 pp_stat_reg = _pp_stat_reg(intel_dp);
1912 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1914 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1916 I915_READ(pp_stat_reg),
1917 I915_READ(pp_ctrl_reg));
1919 if (intel_wait_for_register(dev_priv,
1920 pp_stat_reg, mask, value,
1922 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1923 I915_READ(pp_stat_reg),
1924 I915_READ(pp_ctrl_reg));
1926 DRM_DEBUG_KMS("Wait complete\n");
1929 static void wait_panel_on(struct intel_dp *intel_dp)
1931 DRM_DEBUG_KMS("Wait for panel power on\n");
1932 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1935 static void wait_panel_off(struct intel_dp *intel_dp)
1937 DRM_DEBUG_KMS("Wait for panel power off time\n");
1938 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1941 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1943 ktime_t panel_power_on_time;
1944 s64 panel_power_off_duration;
1946 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1948 /* take the difference of currrent time and panel power off time
1949 * and then make panel wait for t11_t12 if needed. */
1950 panel_power_on_time = ktime_get_boottime();
1951 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1953 /* When we disable the VDD override bit last we have to do the manual
1955 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1956 wait_remaining_ms_from_jiffies(jiffies,
1957 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1959 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1962 static void wait_backlight_on(struct intel_dp *intel_dp)
1964 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1965 intel_dp->backlight_on_delay);
1968 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1970 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1971 intel_dp->backlight_off_delay);
1974 /* Read the current pp_control value, unlocking the register if it
1978 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1980 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1981 struct drm_i915_private *dev_priv = to_i915(dev);
1984 lockdep_assert_held(&dev_priv->pps_mutex);
1986 control = I915_READ(_pp_ctrl_reg(intel_dp));
1987 if (WARN_ON(!HAS_DDI(dev_priv) &&
1988 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
1989 control &= ~PANEL_UNLOCK_MASK;
1990 control |= PANEL_UNLOCK_REGS;
1996 * Must be paired with edp_panel_vdd_off().
1997 * Must hold pps_mutex around the whole on/off sequence.
1998 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2000 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2002 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2003 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2004 struct drm_i915_private *dev_priv = to_i915(dev);
2006 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2007 bool need_to_disable = !intel_dp->want_panel_vdd;
2009 lockdep_assert_held(&dev_priv->pps_mutex);
2011 if (!is_edp(intel_dp))
2014 cancel_delayed_work(&intel_dp->panel_vdd_work);
2015 intel_dp->want_panel_vdd = true;
2017 if (edp_have_panel_vdd(intel_dp))
2018 return need_to_disable;
2020 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2022 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2023 port_name(intel_dig_port->port));
2025 if (!edp_have_panel_power(intel_dp))
2026 wait_panel_power_cycle(intel_dp);
2028 pp = ironlake_get_pp_control(intel_dp);
2029 pp |= EDP_FORCE_VDD;
2031 pp_stat_reg = _pp_stat_reg(intel_dp);
2032 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2034 I915_WRITE(pp_ctrl_reg, pp);
2035 POSTING_READ(pp_ctrl_reg);
2036 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2037 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2039 * If the panel wasn't on, delay before accessing aux channel
2041 if (!edp_have_panel_power(intel_dp)) {
2042 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2043 port_name(intel_dig_port->port));
2044 msleep(intel_dp->panel_power_up_delay);
2047 return need_to_disable;
2051 * Must be paired with intel_edp_panel_vdd_off() or
2052 * intel_edp_panel_off().
2053 * Nested calls to these functions are not allowed since
2054 * we drop the lock. Caller must use some higher level
2055 * locking to prevent nested calls from other threads.
2057 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2061 if (!is_edp(intel_dp))
2065 vdd = edp_panel_vdd_on(intel_dp);
2066 pps_unlock(intel_dp);
2068 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2069 port_name(dp_to_dig_port(intel_dp)->port));
2072 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2074 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2075 struct drm_i915_private *dev_priv = to_i915(dev);
2076 struct intel_digital_port *intel_dig_port =
2077 dp_to_dig_port(intel_dp);
2079 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2081 lockdep_assert_held(&dev_priv->pps_mutex);
2083 WARN_ON(intel_dp->want_panel_vdd);
2085 if (!edp_have_panel_vdd(intel_dp))
2088 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2089 port_name(intel_dig_port->port));
2091 pp = ironlake_get_pp_control(intel_dp);
2092 pp &= ~EDP_FORCE_VDD;
2094 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2095 pp_stat_reg = _pp_stat_reg(intel_dp);
2097 I915_WRITE(pp_ctrl_reg, pp);
2098 POSTING_READ(pp_ctrl_reg);
2100 /* Make sure sequencer is idle before allowing subsequent activity */
2101 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2102 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2104 if ((pp & PANEL_POWER_ON) == 0)
2105 intel_dp->panel_power_off_time = ktime_get_boottime();
2107 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2110 static void edp_panel_vdd_work(struct work_struct *__work)
2112 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2113 struct intel_dp, panel_vdd_work);
2116 if (!intel_dp->want_panel_vdd)
2117 edp_panel_vdd_off_sync(intel_dp);
2118 pps_unlock(intel_dp);
2121 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2123 unsigned long delay;
2126 * Queue the timer to fire a long time from now (relative to the power
2127 * down delay) to keep the panel power up across a sequence of
2130 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2131 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2135 * Must be paired with edp_panel_vdd_on().
2136 * Must hold pps_mutex around the whole on/off sequence.
2137 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2139 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2141 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2143 lockdep_assert_held(&dev_priv->pps_mutex);
2145 if (!is_edp(intel_dp))
2148 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2149 port_name(dp_to_dig_port(intel_dp)->port));
2151 intel_dp->want_panel_vdd = false;
2154 edp_panel_vdd_off_sync(intel_dp);
2156 edp_panel_vdd_schedule_off(intel_dp);
2159 static void edp_panel_on(struct intel_dp *intel_dp)
2161 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2162 struct drm_i915_private *dev_priv = to_i915(dev);
2164 i915_reg_t pp_ctrl_reg;
2166 lockdep_assert_held(&dev_priv->pps_mutex);
2168 if (!is_edp(intel_dp))
2171 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2172 port_name(dp_to_dig_port(intel_dp)->port));
2174 if (WARN(edp_have_panel_power(intel_dp),
2175 "eDP port %c panel power already on\n",
2176 port_name(dp_to_dig_port(intel_dp)->port)))
2179 wait_panel_power_cycle(intel_dp);
2181 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2182 pp = ironlake_get_pp_control(intel_dp);
2183 if (IS_GEN5(dev_priv)) {
2184 /* ILK workaround: disable reset around power sequence */
2185 pp &= ~PANEL_POWER_RESET;
2186 I915_WRITE(pp_ctrl_reg, pp);
2187 POSTING_READ(pp_ctrl_reg);
2190 pp |= PANEL_POWER_ON;
2191 if (!IS_GEN5(dev_priv))
2192 pp |= PANEL_POWER_RESET;
2194 I915_WRITE(pp_ctrl_reg, pp);
2195 POSTING_READ(pp_ctrl_reg);
2197 wait_panel_on(intel_dp);
2198 intel_dp->last_power_on = jiffies;
2200 if (IS_GEN5(dev_priv)) {
2201 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2202 I915_WRITE(pp_ctrl_reg, pp);
2203 POSTING_READ(pp_ctrl_reg);
2207 void intel_edp_panel_on(struct intel_dp *intel_dp)
2209 if (!is_edp(intel_dp))
2213 edp_panel_on(intel_dp);
2214 pps_unlock(intel_dp);
2218 static void edp_panel_off(struct intel_dp *intel_dp)
2220 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2221 struct drm_i915_private *dev_priv = to_i915(dev);
2223 i915_reg_t pp_ctrl_reg;
2225 lockdep_assert_held(&dev_priv->pps_mutex);
2227 if (!is_edp(intel_dp))
2230 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2231 port_name(dp_to_dig_port(intel_dp)->port));
2233 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2234 port_name(dp_to_dig_port(intel_dp)->port));
2236 pp = ironlake_get_pp_control(intel_dp);
2237 /* We need to switch off panel power _and_ force vdd, for otherwise some
2238 * panels get very unhappy and cease to work. */
2239 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2242 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2244 intel_dp->want_panel_vdd = false;
2246 I915_WRITE(pp_ctrl_reg, pp);
2247 POSTING_READ(pp_ctrl_reg);
2249 intel_dp->panel_power_off_time = ktime_get_boottime();
2250 wait_panel_off(intel_dp);
2252 /* We got a reference when we enabled the VDD. */
2253 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2256 void intel_edp_panel_off(struct intel_dp *intel_dp)
2258 if (!is_edp(intel_dp))
2262 edp_panel_off(intel_dp);
2263 pps_unlock(intel_dp);
2266 /* Enable backlight in the panel power control. */
2267 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2269 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2270 struct drm_device *dev = intel_dig_port->base.base.dev;
2271 struct drm_i915_private *dev_priv = to_i915(dev);
2273 i915_reg_t pp_ctrl_reg;
2276 * If we enable the backlight right away following a panel power
2277 * on, we may see slight flicker as the panel syncs with the eDP
2278 * link. So delay a bit to make sure the image is solid before
2279 * allowing it to appear.
2281 wait_backlight_on(intel_dp);
2285 pp = ironlake_get_pp_control(intel_dp);
2286 pp |= EDP_BLC_ENABLE;
2288 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2290 I915_WRITE(pp_ctrl_reg, pp);
2291 POSTING_READ(pp_ctrl_reg);
2293 pps_unlock(intel_dp);
2296 /* Enable backlight PWM and backlight PP control. */
2297 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2299 if (!is_edp(intel_dp))
2302 DRM_DEBUG_KMS("\n");
2304 intel_panel_enable_backlight(intel_dp->attached_connector);
2305 _intel_edp_backlight_on(intel_dp);
2308 /* Disable backlight in the panel power control. */
2309 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2311 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2312 struct drm_i915_private *dev_priv = to_i915(dev);
2314 i915_reg_t pp_ctrl_reg;
2316 if (!is_edp(intel_dp))
2321 pp = ironlake_get_pp_control(intel_dp);
2322 pp &= ~EDP_BLC_ENABLE;
2324 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2326 I915_WRITE(pp_ctrl_reg, pp);
2327 POSTING_READ(pp_ctrl_reg);
2329 pps_unlock(intel_dp);
2331 intel_dp->last_backlight_off = jiffies;
2332 edp_wait_backlight_off(intel_dp);
2335 /* Disable backlight PP control and backlight PWM. */
2336 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2338 if (!is_edp(intel_dp))
2341 DRM_DEBUG_KMS("\n");
2343 _intel_edp_backlight_off(intel_dp);
2344 intel_panel_disable_backlight(intel_dp->attached_connector);
2348 * Hook for controlling the panel power control backlight through the bl_power
2349 * sysfs attribute. Take care to handle multiple calls.
2351 static void intel_edp_backlight_power(struct intel_connector *connector,
2354 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2358 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2359 pps_unlock(intel_dp);
2361 if (is_enabled == enable)
2364 DRM_DEBUG_KMS("panel power control backlight %s\n",
2365 enable ? "enable" : "disable");
2368 _intel_edp_backlight_on(intel_dp);
2370 _intel_edp_backlight_off(intel_dp);
2373 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2375 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2376 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2377 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2379 I915_STATE_WARN(cur_state != state,
2380 "DP port %c state assertion failure (expected %s, current %s)\n",
2381 port_name(dig_port->port),
2382 onoff(state), onoff(cur_state));
2384 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2386 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2388 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2390 I915_STATE_WARN(cur_state != state,
2391 "eDP PLL state assertion failure (expected %s, current %s)\n",
2392 onoff(state), onoff(cur_state));
2394 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2395 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2397 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2398 struct intel_crtc_state *pipe_config)
2400 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2401 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2403 assert_pipe_disabled(dev_priv, crtc->pipe);
2404 assert_dp_port_disabled(intel_dp);
2405 assert_edp_pll_disabled(dev_priv);
2407 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2408 pipe_config->port_clock);
2410 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2412 if (pipe_config->port_clock == 162000)
2413 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2415 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2417 I915_WRITE(DP_A, intel_dp->DP);
2422 * [DevILK] Work around required when enabling DP PLL
2423 * while a pipe is enabled going to FDI:
2424 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2425 * 2. Program DP PLL enable
2427 if (IS_GEN5(dev_priv))
2428 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2430 intel_dp->DP |= DP_PLL_ENABLE;
2432 I915_WRITE(DP_A, intel_dp->DP);
2437 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2439 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2440 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2441 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2443 assert_pipe_disabled(dev_priv, crtc->pipe);
2444 assert_dp_port_disabled(intel_dp);
2445 assert_edp_pll_enabled(dev_priv);
2447 DRM_DEBUG_KMS("disabling eDP PLL\n");
2449 intel_dp->DP &= ~DP_PLL_ENABLE;
2451 I915_WRITE(DP_A, intel_dp->DP);
2456 /* If the sink supports it, try to set the power state appropriately */
2457 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2461 /* Should have a valid DPCD by this point */
2462 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2465 if (mode != DRM_MODE_DPMS_ON) {
2466 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2469 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2472 * When turning on, we need to retry for 1ms to give the sink
2475 for (i = 0; i < 3; i++) {
2476 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2483 if (ret == 1 && lspcon->active)
2484 lspcon_wait_pcon_mode(lspcon);
2488 DRM_DEBUG_KMS("failed to %s sink power state\n",
2489 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2492 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2495 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2496 enum port port = dp_to_dig_port(intel_dp)->port;
2497 struct drm_device *dev = encoder->base.dev;
2498 struct drm_i915_private *dev_priv = to_i915(dev);
2502 if (!intel_display_power_get_if_enabled(dev_priv,
2503 encoder->power_domain))
2508 tmp = I915_READ(intel_dp->output_reg);
2510 if (!(tmp & DP_PORT_EN))
2513 if (IS_GEN7(dev_priv) && port == PORT_A) {
2514 *pipe = PORT_TO_PIPE_CPT(tmp);
2515 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2518 for_each_pipe(dev_priv, p) {
2519 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2520 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2528 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2529 i915_mmio_reg_offset(intel_dp->output_reg));
2530 } else if (IS_CHERRYVIEW(dev_priv)) {
2531 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2533 *pipe = PORT_TO_PIPE(tmp);
2539 intel_display_power_put(dev_priv, encoder->power_domain);
2544 static void intel_dp_get_config(struct intel_encoder *encoder,
2545 struct intel_crtc_state *pipe_config)
2547 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2549 struct drm_device *dev = encoder->base.dev;
2550 struct drm_i915_private *dev_priv = to_i915(dev);
2551 enum port port = dp_to_dig_port(intel_dp)->port;
2552 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2554 tmp = I915_READ(intel_dp->output_reg);
2556 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2558 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2559 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2561 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2562 flags |= DRM_MODE_FLAG_PHSYNC;
2564 flags |= DRM_MODE_FLAG_NHSYNC;
2566 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2567 flags |= DRM_MODE_FLAG_PVSYNC;
2569 flags |= DRM_MODE_FLAG_NVSYNC;
2571 if (tmp & DP_SYNC_HS_HIGH)
2572 flags |= DRM_MODE_FLAG_PHSYNC;
2574 flags |= DRM_MODE_FLAG_NHSYNC;
2576 if (tmp & DP_SYNC_VS_HIGH)
2577 flags |= DRM_MODE_FLAG_PVSYNC;
2579 flags |= DRM_MODE_FLAG_NVSYNC;
2582 pipe_config->base.adjusted_mode.flags |= flags;
2584 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2585 pipe_config->limited_color_range = true;
2587 pipe_config->lane_count =
2588 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2590 intel_dp_get_m_n(crtc, pipe_config);
2592 if (port == PORT_A) {
2593 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2594 pipe_config->port_clock = 162000;
2596 pipe_config->port_clock = 270000;
2599 pipe_config->base.adjusted_mode.crtc_clock =
2600 intel_dotclock_calculate(pipe_config->port_clock,
2601 &pipe_config->dp_m_n);
2603 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2604 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2606 * This is a big fat ugly hack.
2608 * Some machines in UEFI boot mode provide us a VBT that has 18
2609 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2610 * unknown we fail to light up. Yet the same BIOS boots up with
2611 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2612 * max, not what it tells us to use.
2614 * Note: This will still be broken if the eDP panel is not lit
2615 * up by the BIOS, and thus we can't get the mode at module
2618 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2619 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2620 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2624 static void intel_disable_dp(struct intel_encoder *encoder,
2625 struct intel_crtc_state *old_crtc_state,
2626 struct drm_connector_state *old_conn_state)
2628 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2629 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2631 if (old_crtc_state->has_audio)
2632 intel_audio_codec_disable(encoder);
2634 if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2635 intel_psr_disable(intel_dp);
2637 /* Make sure the panel is off before trying to change the mode. But also
2638 * ensure that we have vdd while we switch off the panel. */
2639 intel_edp_panel_vdd_on(intel_dp);
2640 intel_edp_backlight_off(intel_dp);
2641 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2642 intel_edp_panel_off(intel_dp);
2644 /* disable the port before the pipe on g4x */
2645 if (INTEL_GEN(dev_priv) < 5)
2646 intel_dp_link_down(intel_dp);
2649 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2650 struct intel_crtc_state *old_crtc_state,
2651 struct drm_connector_state *old_conn_state)
2653 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2654 enum port port = dp_to_dig_port(intel_dp)->port;
2656 intel_dp_link_down(intel_dp);
2658 /* Only ilk+ has port A */
2660 ironlake_edp_pll_off(intel_dp);
2663 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2664 struct intel_crtc_state *old_crtc_state,
2665 struct drm_connector_state *old_conn_state)
2667 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2669 intel_dp_link_down(intel_dp);
2672 static void chv_post_disable_dp(struct intel_encoder *encoder,
2673 struct intel_crtc_state *old_crtc_state,
2674 struct drm_connector_state *old_conn_state)
2676 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2677 struct drm_device *dev = encoder->base.dev;
2678 struct drm_i915_private *dev_priv = to_i915(dev);
2680 intel_dp_link_down(intel_dp);
2682 mutex_lock(&dev_priv->sb_lock);
2684 /* Assert data lane reset */
2685 chv_data_lane_soft_reset(encoder, true);
2687 mutex_unlock(&dev_priv->sb_lock);
2691 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2693 uint8_t dp_train_pat)
2695 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2696 struct drm_device *dev = intel_dig_port->base.base.dev;
2697 struct drm_i915_private *dev_priv = to_i915(dev);
2698 enum port port = intel_dig_port->port;
2700 if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2701 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2702 dp_train_pat & DP_TRAINING_PATTERN_MASK);
2704 if (HAS_DDI(dev_priv)) {
2705 uint32_t temp = I915_READ(DP_TP_CTL(port));
2707 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2708 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2710 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2712 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2713 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2714 case DP_TRAINING_PATTERN_DISABLE:
2715 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2718 case DP_TRAINING_PATTERN_1:
2719 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2721 case DP_TRAINING_PATTERN_2:
2722 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2724 case DP_TRAINING_PATTERN_3:
2725 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2728 I915_WRITE(DP_TP_CTL(port), temp);
2730 } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2731 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2732 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2734 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2735 case DP_TRAINING_PATTERN_DISABLE:
2736 *DP |= DP_LINK_TRAIN_OFF_CPT;
2738 case DP_TRAINING_PATTERN_1:
2739 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2741 case DP_TRAINING_PATTERN_2:
2742 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2744 case DP_TRAINING_PATTERN_3:
2745 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2746 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2751 if (IS_CHERRYVIEW(dev_priv))
2752 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2754 *DP &= ~DP_LINK_TRAIN_MASK;
2756 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2757 case DP_TRAINING_PATTERN_DISABLE:
2758 *DP |= DP_LINK_TRAIN_OFF;
2760 case DP_TRAINING_PATTERN_1:
2761 *DP |= DP_LINK_TRAIN_PAT_1;
2763 case DP_TRAINING_PATTERN_2:
2764 *DP |= DP_LINK_TRAIN_PAT_2;
2766 case DP_TRAINING_PATTERN_3:
2767 if (IS_CHERRYVIEW(dev_priv)) {
2768 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2770 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2771 *DP |= DP_LINK_TRAIN_PAT_2;
2778 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2779 struct intel_crtc_state *old_crtc_state)
2781 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2782 struct drm_i915_private *dev_priv = to_i915(dev);
2784 /* enable with pattern 1 (as per spec) */
2786 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2789 * Magic for VLV/CHV. We _must_ first set up the register
2790 * without actually enabling the port, and then do another
2791 * write to enable the port. Otherwise link training will
2792 * fail when the power sequencer is freshly used for this port.
2794 intel_dp->DP |= DP_PORT_EN;
2795 if (old_crtc_state->has_audio)
2796 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2798 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2799 POSTING_READ(intel_dp->output_reg);
2802 static void intel_enable_dp(struct intel_encoder *encoder,
2803 struct intel_crtc_state *pipe_config,
2804 struct drm_connector_state *conn_state)
2806 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2807 struct drm_device *dev = encoder->base.dev;
2808 struct drm_i915_private *dev_priv = to_i915(dev);
2809 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2810 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2811 enum pipe pipe = crtc->pipe;
2813 if (WARN_ON(dp_reg & DP_PORT_EN))
2818 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2819 vlv_init_panel_power_sequencer(intel_dp);
2821 intel_dp_enable_port(intel_dp, pipe_config);
2823 edp_panel_vdd_on(intel_dp);
2824 edp_panel_on(intel_dp);
2825 edp_panel_vdd_off(intel_dp, true);
2827 pps_unlock(intel_dp);
2829 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2830 unsigned int lane_mask = 0x0;
2832 if (IS_CHERRYVIEW(dev_priv))
2833 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2835 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2839 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2840 intel_dp_start_link_train(intel_dp);
2841 intel_dp_stop_link_train(intel_dp);
2843 if (pipe_config->has_audio) {
2844 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2846 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2850 static void g4x_enable_dp(struct intel_encoder *encoder,
2851 struct intel_crtc_state *pipe_config,
2852 struct drm_connector_state *conn_state)
2854 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2856 intel_enable_dp(encoder, pipe_config, conn_state);
2857 intel_edp_backlight_on(intel_dp);
2860 static void vlv_enable_dp(struct intel_encoder *encoder,
2861 struct intel_crtc_state *pipe_config,
2862 struct drm_connector_state *conn_state)
2864 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2866 intel_edp_backlight_on(intel_dp);
2867 intel_psr_enable(intel_dp);
2870 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2871 struct intel_crtc_state *pipe_config,
2872 struct drm_connector_state *conn_state)
2874 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2875 enum port port = dp_to_dig_port(intel_dp)->port;
2877 intel_dp_prepare(encoder, pipe_config);
2879 /* Only ilk+ has port A */
2881 ironlake_edp_pll_on(intel_dp, pipe_config);
2884 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2886 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2887 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2888 enum pipe pipe = intel_dp->pps_pipe;
2889 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2891 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2893 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2896 edp_panel_vdd_off_sync(intel_dp);
2899 * VLV seems to get confused when multiple power seqeuencers
2900 * have the same port selected (even if only one has power/vdd
2901 * enabled). The failure manifests as vlv_wait_port_ready() failing
2902 * CHV on the other hand doesn't seem to mind having the same port
2903 * selected in multiple power seqeuencers, but let's clear the
2904 * port select always when logically disconnecting a power sequencer
2907 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2908 pipe_name(pipe), port_name(intel_dig_port->port));
2909 I915_WRITE(pp_on_reg, 0);
2910 POSTING_READ(pp_on_reg);
2912 intel_dp->pps_pipe = INVALID_PIPE;
2915 static void vlv_steal_power_sequencer(struct drm_device *dev,
2918 struct drm_i915_private *dev_priv = to_i915(dev);
2919 struct intel_encoder *encoder;
2921 lockdep_assert_held(&dev_priv->pps_mutex);
2923 for_each_intel_encoder(dev, encoder) {
2924 struct intel_dp *intel_dp;
2927 if (encoder->type != INTEL_OUTPUT_DP &&
2928 encoder->type != INTEL_OUTPUT_EDP)
2931 intel_dp = enc_to_intel_dp(&encoder->base);
2932 port = dp_to_dig_port(intel_dp)->port;
2934 WARN(intel_dp->active_pipe == pipe,
2935 "stealing pipe %c power sequencer from active (e)DP port %c\n",
2936 pipe_name(pipe), port_name(port));
2938 if (intel_dp->pps_pipe != pipe)
2941 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2942 pipe_name(pipe), port_name(port));
2944 /* make sure vdd is off before we steal it */
2945 vlv_detach_power_sequencer(intel_dp);
2949 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2951 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2952 struct intel_encoder *encoder = &intel_dig_port->base;
2953 struct drm_device *dev = encoder->base.dev;
2954 struct drm_i915_private *dev_priv = to_i915(dev);
2955 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2957 lockdep_assert_held(&dev_priv->pps_mutex);
2959 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2961 if (intel_dp->pps_pipe != INVALID_PIPE &&
2962 intel_dp->pps_pipe != crtc->pipe) {
2964 * If another power sequencer was being used on this
2965 * port previously make sure to turn off vdd there while
2966 * we still have control of it.
2968 vlv_detach_power_sequencer(intel_dp);
2972 * We may be stealing the power
2973 * sequencer from another port.
2975 vlv_steal_power_sequencer(dev, crtc->pipe);
2977 intel_dp->active_pipe = crtc->pipe;
2979 if (!is_edp(intel_dp))
2982 /* now it's all ours */
2983 intel_dp->pps_pipe = crtc->pipe;
2985 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2986 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2988 /* init power sequencer on this pipe and port */
2989 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2990 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
2993 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
2994 struct intel_crtc_state *pipe_config,
2995 struct drm_connector_state *conn_state)
2997 vlv_phy_pre_encoder_enable(encoder);
2999 intel_enable_dp(encoder, pipe_config, conn_state);
3002 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3003 struct intel_crtc_state *pipe_config,
3004 struct drm_connector_state *conn_state)
3006 intel_dp_prepare(encoder, pipe_config);
3008 vlv_phy_pre_pll_enable(encoder);
3011 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3012 struct intel_crtc_state *pipe_config,
3013 struct drm_connector_state *conn_state)
3015 chv_phy_pre_encoder_enable(encoder);
3017 intel_enable_dp(encoder, pipe_config, conn_state);
3019 /* Second common lane will stay alive on its own now */
3020 chv_phy_release_cl2_override(encoder);
3023 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3024 struct intel_crtc_state *pipe_config,
3025 struct drm_connector_state *conn_state)
3027 intel_dp_prepare(encoder, pipe_config);
3029 chv_phy_pre_pll_enable(encoder);
3032 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3033 struct intel_crtc_state *pipe_config,
3034 struct drm_connector_state *conn_state)
3036 chv_phy_post_pll_disable(encoder);
3040 * Fetch AUX CH registers 0x202 - 0x207 which contain
3041 * link status information
3044 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3046 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3047 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3050 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3052 uint8_t psr_caps = 0;
3054 drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps);
3055 return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3058 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3062 drm_dp_dpcd_readb(&intel_dp->aux,
3063 DP_DPRX_FEATURE_ENUMERATION_LIST,
3065 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3068 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3070 uint8_t alpm_caps = 0;
3072 drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &alpm_caps);
3073 return alpm_caps & DP_ALPM_CAP;
3076 /* These are source-specific values. */
3078 intel_dp_voltage_max(struct intel_dp *intel_dp)
3080 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3081 enum port port = dp_to_dig_port(intel_dp)->port;
3083 if (IS_GEN9_LP(dev_priv))
3084 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3085 else if (INTEL_GEN(dev_priv) >= 9) {
3086 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3087 return intel_ddi_dp_voltage_max(encoder);
3088 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3089 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3090 else if (IS_GEN7(dev_priv) && port == PORT_A)
3091 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3092 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3093 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3095 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3099 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3101 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3102 enum port port = dp_to_dig_port(intel_dp)->port;
3104 if (INTEL_GEN(dev_priv) >= 9) {
3105 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3106 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3107 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3108 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3109 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3110 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3111 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3112 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3113 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3115 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3117 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3118 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3119 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3120 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3121 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3122 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3123 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3124 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3127 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3129 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3130 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3131 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3132 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3133 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3134 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3136 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3137 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3139 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3141 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3142 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3143 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3144 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3145 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3146 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3147 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3149 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3152 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3153 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3154 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3155 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3156 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3157 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3158 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3159 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3161 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3166 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3168 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3169 unsigned long demph_reg_value, preemph_reg_value,
3170 uniqtranscale_reg_value;
3171 uint8_t train_set = intel_dp->train_set[0];
3173 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3174 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3175 preemph_reg_value = 0x0004000;
3176 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3178 demph_reg_value = 0x2B405555;
3179 uniqtranscale_reg_value = 0x552AB83A;
3181 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3182 demph_reg_value = 0x2B404040;
3183 uniqtranscale_reg_value = 0x5548B83A;
3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3186 demph_reg_value = 0x2B245555;
3187 uniqtranscale_reg_value = 0x5560B83A;
3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3190 demph_reg_value = 0x2B405555;
3191 uniqtranscale_reg_value = 0x5598DA3A;
3197 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3198 preemph_reg_value = 0x0002000;
3199 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3201 demph_reg_value = 0x2B404040;
3202 uniqtranscale_reg_value = 0x5552B83A;
3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3205 demph_reg_value = 0x2B404848;
3206 uniqtranscale_reg_value = 0x5580B83A;
3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3209 demph_reg_value = 0x2B404040;
3210 uniqtranscale_reg_value = 0x55ADDA3A;
3216 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3217 preemph_reg_value = 0x0000000;
3218 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3220 demph_reg_value = 0x2B305555;
3221 uniqtranscale_reg_value = 0x5570B83A;
3223 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3224 demph_reg_value = 0x2B2B4040;
3225 uniqtranscale_reg_value = 0x55ADDA3A;
3231 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3232 preemph_reg_value = 0x0006000;
3233 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3234 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3235 demph_reg_value = 0x1B405555;
3236 uniqtranscale_reg_value = 0x55ADDA3A;
3246 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3247 uniqtranscale_reg_value, 0);
3252 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3254 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3255 u32 deemph_reg_value, margin_reg_value;
3256 bool uniq_trans_scale = false;
3257 uint8_t train_set = intel_dp->train_set[0];
3259 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3260 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3261 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3262 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3263 deemph_reg_value = 128;
3264 margin_reg_value = 52;
3266 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3267 deemph_reg_value = 128;
3268 margin_reg_value = 77;
3270 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3271 deemph_reg_value = 128;
3272 margin_reg_value = 102;
3274 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3275 deemph_reg_value = 128;
3276 margin_reg_value = 154;
3277 uniq_trans_scale = true;
3283 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3284 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3286 deemph_reg_value = 85;
3287 margin_reg_value = 78;
3289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3290 deemph_reg_value = 85;
3291 margin_reg_value = 116;
3293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3294 deemph_reg_value = 85;
3295 margin_reg_value = 154;
3301 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3302 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3303 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3304 deemph_reg_value = 64;
3305 margin_reg_value = 104;
3307 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3308 deemph_reg_value = 64;
3309 margin_reg_value = 154;
3315 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3316 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3317 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3318 deemph_reg_value = 43;
3319 margin_reg_value = 154;
3329 chv_set_phy_signal_level(encoder, deemph_reg_value,
3330 margin_reg_value, uniq_trans_scale);
3336 gen4_signal_levels(uint8_t train_set)
3338 uint32_t signal_levels = 0;
3340 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3341 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3343 signal_levels |= DP_VOLTAGE_0_4;
3345 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3346 signal_levels |= DP_VOLTAGE_0_6;
3348 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3349 signal_levels |= DP_VOLTAGE_0_8;
3351 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3352 signal_levels |= DP_VOLTAGE_1_2;
3355 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3356 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3358 signal_levels |= DP_PRE_EMPHASIS_0;
3360 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3361 signal_levels |= DP_PRE_EMPHASIS_3_5;
3363 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3364 signal_levels |= DP_PRE_EMPHASIS_6;
3366 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3367 signal_levels |= DP_PRE_EMPHASIS_9_5;
3370 return signal_levels;
3373 /* Gen6's DP voltage swing and pre-emphasis control */
3375 gen6_edp_signal_levels(uint8_t train_set)
3377 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3378 DP_TRAIN_PRE_EMPHASIS_MASK);
3379 switch (signal_levels) {
3380 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3381 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3382 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3383 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3384 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3385 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3386 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3387 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3388 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3389 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3390 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3391 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3392 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3393 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3395 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3396 "0x%x\n", signal_levels);
3397 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3401 /* Gen7's DP voltage swing and pre-emphasis control */
3403 gen7_edp_signal_levels(uint8_t train_set)
3405 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3406 DP_TRAIN_PRE_EMPHASIS_MASK);
3407 switch (signal_levels) {
3408 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3409 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3410 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3411 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3412 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3413 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3415 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3416 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3417 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3418 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3420 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3421 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3422 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3423 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3426 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3427 "0x%x\n", signal_levels);
3428 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3433 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3435 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3436 enum port port = intel_dig_port->port;
3437 struct drm_device *dev = intel_dig_port->base.base.dev;
3438 struct drm_i915_private *dev_priv = to_i915(dev);
3439 uint32_t signal_levels, mask = 0;
3440 uint8_t train_set = intel_dp->train_set[0];
3442 if (HAS_DDI(dev_priv)) {
3443 signal_levels = ddi_signal_levels(intel_dp);
3445 if (IS_GEN9_LP(dev_priv))
3448 mask = DDI_BUF_EMP_MASK;
3449 } else if (IS_CHERRYVIEW(dev_priv)) {
3450 signal_levels = chv_signal_levels(intel_dp);
3451 } else if (IS_VALLEYVIEW(dev_priv)) {
3452 signal_levels = vlv_signal_levels(intel_dp);
3453 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3454 signal_levels = gen7_edp_signal_levels(train_set);
3455 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3456 } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3457 signal_levels = gen6_edp_signal_levels(train_set);
3458 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3460 signal_levels = gen4_signal_levels(train_set);
3461 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3465 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3467 DRM_DEBUG_KMS("Using vswing level %d\n",
3468 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3469 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3470 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3471 DP_TRAIN_PRE_EMPHASIS_SHIFT);
3473 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3475 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3476 POSTING_READ(intel_dp->output_reg);
3480 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3481 uint8_t dp_train_pat)
3483 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3484 struct drm_i915_private *dev_priv =
3485 to_i915(intel_dig_port->base.base.dev);
3487 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3489 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3490 POSTING_READ(intel_dp->output_reg);
3493 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3495 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3496 struct drm_device *dev = intel_dig_port->base.base.dev;
3497 struct drm_i915_private *dev_priv = to_i915(dev);
3498 enum port port = intel_dig_port->port;
3501 if (!HAS_DDI(dev_priv))
3504 val = I915_READ(DP_TP_CTL(port));
3505 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3506 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3507 I915_WRITE(DP_TP_CTL(port), val);
3510 * On PORT_A we can have only eDP in SST mode. There the only reason
3511 * we need to set idle transmission mode is to work around a HW issue
3512 * where we enable the pipe while not in idle link-training mode.
3513 * In this case there is requirement to wait for a minimum number of
3514 * idle patterns to be sent.
3519 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3520 DP_TP_STATUS_IDLE_DONE,
3521 DP_TP_STATUS_IDLE_DONE,
3523 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3527 intel_dp_link_down(struct intel_dp *intel_dp)
3529 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3530 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3531 enum port port = intel_dig_port->port;
3532 struct drm_device *dev = intel_dig_port->base.base.dev;
3533 struct drm_i915_private *dev_priv = to_i915(dev);
3534 uint32_t DP = intel_dp->DP;
3536 if (WARN_ON(HAS_DDI(dev_priv)))
3539 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3542 DRM_DEBUG_KMS("\n");
3544 if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3545 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3546 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3547 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3549 if (IS_CHERRYVIEW(dev_priv))
3550 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3552 DP &= ~DP_LINK_TRAIN_MASK;
3553 DP |= DP_LINK_TRAIN_PAT_IDLE;
3555 I915_WRITE(intel_dp->output_reg, DP);
3556 POSTING_READ(intel_dp->output_reg);
3558 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3559 I915_WRITE(intel_dp->output_reg, DP);
3560 POSTING_READ(intel_dp->output_reg);
3563 * HW workaround for IBX, we need to move the port
3564 * to transcoder A after disabling it to allow the
3565 * matching HDMI port to be enabled on transcoder A.
3567 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3569 * We get CPU/PCH FIFO underruns on the other pipe when
3570 * doing the workaround. Sweep them under the rug.
3572 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3573 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3575 /* always enable with pattern 1 (as per spec) */
3576 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3577 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3578 I915_WRITE(intel_dp->output_reg, DP);
3579 POSTING_READ(intel_dp->output_reg);
3582 I915_WRITE(intel_dp->output_reg, DP);
3583 POSTING_READ(intel_dp->output_reg);
3585 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3586 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3587 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3590 msleep(intel_dp->panel_power_down_delay);
3594 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3596 intel_dp->active_pipe = INVALID_PIPE;
3597 pps_unlock(intel_dp);
3602 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3604 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3605 sizeof(intel_dp->dpcd)) < 0)
3606 return false; /* aux transfer failed */
3608 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3610 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3614 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3616 struct drm_i915_private *dev_priv =
3617 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3619 /* this function is meant to be called only once */
3620 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3622 if (!intel_dp_read_dpcd(intel_dp))
3625 intel_dp_read_desc(intel_dp);
3627 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3628 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3629 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3631 /* Check if the panel supports PSR */
3632 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3634 sizeof(intel_dp->psr_dpcd));
3635 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3636 dev_priv->psr.sink_support = true;
3637 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3640 if (INTEL_GEN(dev_priv) >= 9 &&
3641 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3642 uint8_t frame_sync_cap;
3644 dev_priv->psr.sink_support = true;
3645 drm_dp_dpcd_read(&intel_dp->aux,
3646 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3647 &frame_sync_cap, 1);
3648 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3649 /* PSR2 needs frame sync as well */
3650 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3651 DRM_DEBUG_KMS("PSR2 %s on sink",
3652 dev_priv->psr.psr2_support ? "supported" : "not supported");
3654 if (dev_priv->psr.psr2_support) {
3655 dev_priv->psr.y_cord_support =
3656 intel_dp_get_y_cord_status(intel_dp);
3657 dev_priv->psr.colorimetry_support =
3658 intel_dp_get_colorimetry_status(intel_dp);
3659 dev_priv->psr.alpm =
3660 intel_dp_get_alpm_status(intel_dp);
3665 /* Read the eDP Display control capabilities registers */
3666 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3667 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3668 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3669 sizeof(intel_dp->edp_dpcd))
3670 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3671 intel_dp->edp_dpcd);
3673 /* Intermediate frequency support */
3674 if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3675 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3678 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3679 sink_rates, sizeof(sink_rates));
3681 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3682 int val = le16_to_cpu(sink_rates[i]);
3687 /* Value read multiplied by 200kHz gives the per-lane
3688 * link rate in kHz. The source rates are, however,
3689 * stored in terms of LS_Clk kHz. The full conversion
3690 * back to symbols is
3691 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3693 intel_dp->sink_rates[i] = (val * 200) / 10;
3695 intel_dp->num_sink_rates = i;
3703 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3705 if (!intel_dp_read_dpcd(intel_dp))
3708 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3709 &intel_dp->sink_count, 1) < 0)
3713 * Sink count can change between short pulse hpd hence
3714 * a member variable in intel_dp will track any changes
3715 * between short pulse interrupts.
3717 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3720 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3721 * a dongle is present but no display. Unless we require to know
3722 * if a dongle is present or not, we don't need to update
3723 * downstream port information. So, an early return here saves
3724 * time from performing other operations which are not required.
3726 if (!is_edp(intel_dp) && !intel_dp->sink_count)
3729 if (!drm_dp_is_branch(intel_dp->dpcd))
3730 return true; /* native DP sink */
3732 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3733 return true; /* no per-port downstream info */
3735 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3736 intel_dp->downstream_ports,
3737 DP_MAX_DOWNSTREAM_PORTS) < 0)
3738 return false; /* downstream port status fetch failed */
3744 intel_dp_can_mst(struct intel_dp *intel_dp)
3748 if (!i915.enable_dp_mst)
3751 if (!intel_dp->can_mst)
3754 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3757 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3760 return buf[0] & DP_MST_CAP;
3764 intel_dp_configure_mst(struct intel_dp *intel_dp)
3766 if (!i915.enable_dp_mst)
3769 if (!intel_dp->can_mst)
3772 intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3774 if (intel_dp->is_mst)
3775 DRM_DEBUG_KMS("Sink is MST capable\n");
3777 DRM_DEBUG_KMS("Sink is not MST capable\n");
3779 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3783 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3785 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3786 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3787 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3793 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3794 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3799 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3800 buf & ~DP_TEST_SINK_START) < 0) {
3801 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3807 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3809 if (drm_dp_dpcd_readb(&intel_dp->aux,
3810 DP_TEST_SINK_MISC, &buf) < 0) {
3814 count = buf & DP_TEST_COUNT_MASK;
3815 } while (--attempts && count);
3817 if (attempts == 0) {
3818 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3823 hsw_enable_ips(intel_crtc);
3827 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3829 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3830 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3831 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3835 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3838 if (!(buf & DP_TEST_CRC_SUPPORTED))
3841 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3844 if (buf & DP_TEST_SINK_START) {
3845 ret = intel_dp_sink_crc_stop(intel_dp);
3850 hsw_disable_ips(intel_crtc);
3852 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3853 buf | DP_TEST_SINK_START) < 0) {
3854 hsw_enable_ips(intel_crtc);
3858 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3862 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3864 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3865 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3866 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3871 ret = intel_dp_sink_crc_start(intel_dp);
3876 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3878 if (drm_dp_dpcd_readb(&intel_dp->aux,
3879 DP_TEST_SINK_MISC, &buf) < 0) {
3883 count = buf & DP_TEST_COUNT_MASK;
3885 } while (--attempts && count == 0);
3887 if (attempts == 0) {
3888 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3893 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3899 intel_dp_sink_crc_stop(intel_dp);
3904 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3906 return drm_dp_dpcd_read(&intel_dp->aux,
3907 DP_DEVICE_SERVICE_IRQ_VECTOR,
3908 sink_irq_vector, 1) == 1;
3912 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3916 ret = drm_dp_dpcd_read(&intel_dp->aux,
3918 sink_irq_vector, 14);
3925 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3928 int min_lane_count = 1;
3929 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
3930 int link_rate_index, test_link_rate;
3931 uint8_t test_lane_count, test_link_bw;
3935 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3936 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3940 DRM_DEBUG_KMS("Lane count read failed\n");
3943 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3944 /* Validate the requested lane count */
3945 if (test_lane_count < min_lane_count ||
3946 test_lane_count > intel_dp->max_sink_lane_count)
3949 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3952 DRM_DEBUG_KMS("Link Rate read failed\n");
3955 /* Validate the requested link rate */
3956 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3957 link_rate_index = intel_dp_link_rate_index(intel_dp,
3960 if (link_rate_index < 0)
3963 intel_dp->compliance.test_lane_count = test_lane_count;
3964 intel_dp->compliance.test_link_rate = test_link_rate;
3969 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3971 uint8_t test_pattern;
3973 __be16 h_width, v_height;
3976 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3977 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_PATTERN,
3980 DRM_DEBUG_KMS("Test pattern read failed\n");
3983 if (test_pattern != DP_COLOR_RAMP)
3986 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3989 DRM_DEBUG_KMS("H Width read failed\n");
3993 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3996 DRM_DEBUG_KMS("V Height read failed\n");
4000 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_MISC0,
4003 DRM_DEBUG_KMS("TEST MISC read failed\n");
4006 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4008 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4010 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4011 case DP_TEST_BIT_DEPTH_6:
4012 intel_dp->compliance.test_data.bpc = 6;
4014 case DP_TEST_BIT_DEPTH_8:
4015 intel_dp->compliance.test_data.bpc = 8;
4021 intel_dp->compliance.test_data.video_pattern = test_pattern;
4022 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4023 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4024 /* Set test active flag here so userspace doesn't interrupt things */
4025 intel_dp->compliance.test_active = 1;
4030 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4032 uint8_t test_result = DP_TEST_ACK;
4033 struct intel_connector *intel_connector = intel_dp->attached_connector;
4034 struct drm_connector *connector = &intel_connector->base;
4036 if (intel_connector->detect_edid == NULL ||
4037 connector->edid_corrupt ||
4038 intel_dp->aux.i2c_defer_count > 6) {
4039 /* Check EDID read for NACKs, DEFERs and corruption
4040 * (DP CTS 1.2 Core r1.1)
4041 * 4.2.2.4 : Failed EDID read, I2C_NAK
4042 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4043 * 4.2.2.6 : EDID corruption detected
4044 * Use failsafe mode for all cases
4046 if (intel_dp->aux.i2c_nack_count > 0 ||
4047 intel_dp->aux.i2c_defer_count > 0)
4048 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4049 intel_dp->aux.i2c_nack_count,
4050 intel_dp->aux.i2c_defer_count);
4051 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4053 struct edid *block = intel_connector->detect_edid;
4055 /* We have to write the checksum
4056 * of the last block read
4058 block += intel_connector->detect_edid->extensions;
4060 if (!drm_dp_dpcd_write(&intel_dp->aux,
4061 DP_TEST_EDID_CHECKSUM,
4064 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4066 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4067 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4070 /* Set test active flag here so userspace doesn't interrupt things */
4071 intel_dp->compliance.test_active = 1;
4076 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4078 uint8_t test_result = DP_TEST_NAK;
4082 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4084 uint8_t response = DP_TEST_NAK;
4085 uint8_t request = 0;
4088 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4090 DRM_DEBUG_KMS("Could not read test request from sink\n");
4095 case DP_TEST_LINK_TRAINING:
4096 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4097 response = intel_dp_autotest_link_training(intel_dp);
4099 case DP_TEST_LINK_VIDEO_PATTERN:
4100 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4101 response = intel_dp_autotest_video_pattern(intel_dp);
4103 case DP_TEST_LINK_EDID_READ:
4104 DRM_DEBUG_KMS("EDID test requested\n");
4105 response = intel_dp_autotest_edid(intel_dp);
4107 case DP_TEST_LINK_PHY_TEST_PATTERN:
4108 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4109 response = intel_dp_autotest_phy_pattern(intel_dp);
4112 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4116 if (response & DP_TEST_ACK)
4117 intel_dp->compliance.test_type = request;
4120 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4122 DRM_DEBUG_KMS("Could not write test response to sink\n");
4126 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4130 if (intel_dp->is_mst) {
4135 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4139 /* check link status - esi[10] = 0x200c */
4140 if (intel_dp->active_mst_links &&
4141 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4142 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4143 intel_dp_start_link_train(intel_dp);
4144 intel_dp_stop_link_train(intel_dp);
4147 DRM_DEBUG_KMS("got esi %3ph\n", esi);
4148 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4151 for (retry = 0; retry < 3; retry++) {
4153 wret = drm_dp_dpcd_write(&intel_dp->aux,
4154 DP_SINK_COUNT_ESI+1,
4161 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4163 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4171 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4172 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4173 intel_dp->is_mst = false;
4174 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4175 /* send a hotplug event */
4176 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4183 intel_dp_retrain_link(struct intel_dp *intel_dp)
4185 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4186 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4187 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4189 /* Suppress underruns caused by re-training */
4190 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4191 if (crtc->config->has_pch_encoder)
4192 intel_set_pch_fifo_underrun_reporting(dev_priv,
4193 intel_crtc_pch_transcoder(crtc), false);
4195 intel_dp_start_link_train(intel_dp);
4196 intel_dp_stop_link_train(intel_dp);
4198 /* Keep underrun reporting disabled until things are stable */
4199 intel_wait_for_vblank(dev_priv, crtc->pipe);
4201 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4202 if (crtc->config->has_pch_encoder)
4203 intel_set_pch_fifo_underrun_reporting(dev_priv,
4204 intel_crtc_pch_transcoder(crtc), true);
4208 intel_dp_check_link_status(struct intel_dp *intel_dp)
4210 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4211 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4212 u8 link_status[DP_LINK_STATUS_SIZE];
4214 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4216 if (!intel_dp_get_link_status(intel_dp, link_status)) {
4217 DRM_ERROR("Failed to get link status\n");
4221 if (!intel_encoder->base.crtc)
4224 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4227 /* FIXME: we need to synchronize this sort of stuff with hardware
4228 * readout. Currently fast link training doesn't work on boot-up. */
4229 if (!intel_dp->lane_count)
4232 /* Retrain if Channel EQ or CR not ok */
4233 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4234 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4235 intel_encoder->base.name);
4237 intel_dp_retrain_link(intel_dp);
4242 * According to DP spec
4245 * 2. Configure link according to Receiver Capabilities
4246 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4247 * 4. Check link status on receipt of hot-plug interrupt
4249 * intel_dp_short_pulse - handles short pulse interrupts
4250 * when full detection is not required.
4251 * Returns %true if short pulse is handled and full detection
4252 * is NOT required and %false otherwise.
4255 intel_dp_short_pulse(struct intel_dp *intel_dp)
4257 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4258 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4259 u8 sink_irq_vector = 0;
4260 u8 old_sink_count = intel_dp->sink_count;
4264 * Clearing compliance test variables to allow capturing
4265 * of values for next automated test request.
4267 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4270 * Now read the DPCD to see if it's actually running
4271 * If the current value of sink count doesn't match with
4272 * the value that was stored earlier or dpcd read failed
4273 * we need to do full detection
4275 ret = intel_dp_get_dpcd(intel_dp);
4277 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4278 /* No need to proceed if we are going to do full detect */
4282 /* Try to read the source of the interrupt */
4283 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4284 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4285 sink_irq_vector != 0) {
4286 /* Clear interrupt source */
4287 drm_dp_dpcd_writeb(&intel_dp->aux,
4288 DP_DEVICE_SERVICE_IRQ_VECTOR,
4291 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4292 intel_dp_handle_test_request(intel_dp);
4293 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4294 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4297 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4298 intel_dp_check_link_status(intel_dp);
4299 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4300 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4301 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4302 /* Send a Hotplug Uevent to userspace to start modeset */
4303 drm_kms_helper_hotplug_event(intel_encoder->base.dev);
4309 /* XXX this is probably wrong for multiple downstream ports */
4310 static enum drm_connector_status
4311 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4313 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4314 uint8_t *dpcd = intel_dp->dpcd;
4318 lspcon_resume(lspcon);
4320 if (!intel_dp_get_dpcd(intel_dp))
4321 return connector_status_disconnected;
4323 if (is_edp(intel_dp))
4324 return connector_status_connected;
4326 /* if there's no downstream port, we're done */
4327 if (!drm_dp_is_branch(dpcd))
4328 return connector_status_connected;
4330 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4331 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4332 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4334 return intel_dp->sink_count ?
4335 connector_status_connected : connector_status_disconnected;
4338 if (intel_dp_can_mst(intel_dp))
4339 return connector_status_connected;
4341 /* If no HPD, poke DDC gently */
4342 if (drm_probe_ddc(&intel_dp->aux.ddc))
4343 return connector_status_connected;
4345 /* Well we tried, say unknown for unreliable port types */
4346 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4347 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4348 if (type == DP_DS_PORT_TYPE_VGA ||
4349 type == DP_DS_PORT_TYPE_NON_EDID)
4350 return connector_status_unknown;
4352 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4353 DP_DWN_STRM_PORT_TYPE_MASK;
4354 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4355 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4356 return connector_status_unknown;
4359 /* Anything else is out of spec, warn and ignore */
4360 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4361 return connector_status_disconnected;
4364 static enum drm_connector_status
4365 edp_detect(struct intel_dp *intel_dp)
4367 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4368 struct drm_i915_private *dev_priv = to_i915(dev);
4369 enum drm_connector_status status;
4371 status = intel_panel_detect(dev_priv);
4372 if (status == connector_status_unknown)
4373 status = connector_status_connected;
4378 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4379 struct intel_digital_port *port)
4383 switch (port->port) {
4387 bit = SDE_PORTB_HOTPLUG;
4390 bit = SDE_PORTC_HOTPLUG;
4393 bit = SDE_PORTD_HOTPLUG;
4396 MISSING_CASE(port->port);
4400 return I915_READ(SDEISR) & bit;
4403 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4404 struct intel_digital_port *port)
4408 switch (port->port) {
4412 bit = SDE_PORTB_HOTPLUG_CPT;
4415 bit = SDE_PORTC_HOTPLUG_CPT;
4418 bit = SDE_PORTD_HOTPLUG_CPT;
4421 bit = SDE_PORTE_HOTPLUG_SPT;
4424 MISSING_CASE(port->port);
4428 return I915_READ(SDEISR) & bit;
4431 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4432 struct intel_digital_port *port)
4436 switch (port->port) {
4438 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4441 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4444 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4447 MISSING_CASE(port->port);
4451 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4454 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4455 struct intel_digital_port *port)
4459 switch (port->port) {
4461 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4464 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4467 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4470 MISSING_CASE(port->port);
4474 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4477 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4478 struct intel_digital_port *intel_dig_port)
4480 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4484 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4487 bit = BXT_DE_PORT_HP_DDIA;
4490 bit = BXT_DE_PORT_HP_DDIB;
4493 bit = BXT_DE_PORT_HP_DDIC;
4500 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4504 * intel_digital_port_connected - is the specified port connected?
4505 * @dev_priv: i915 private structure
4506 * @port: the port to test
4508 * Return %true if @port is connected, %false otherwise.
4510 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4511 struct intel_digital_port *port)
4513 if (HAS_PCH_IBX(dev_priv))
4514 return ibx_digital_port_connected(dev_priv, port);
4515 else if (HAS_PCH_SPLIT(dev_priv))
4516 return cpt_digital_port_connected(dev_priv, port);
4517 else if (IS_GEN9_LP(dev_priv))
4518 return bxt_digital_port_connected(dev_priv, port);
4519 else if (IS_GM45(dev_priv))
4520 return gm45_digital_port_connected(dev_priv, port);
4522 return g4x_digital_port_connected(dev_priv, port);
4525 static struct edid *
4526 intel_dp_get_edid(struct intel_dp *intel_dp)
4528 struct intel_connector *intel_connector = intel_dp->attached_connector;
4530 /* use cached edid if we have one */
4531 if (intel_connector->edid) {
4533 if (IS_ERR(intel_connector->edid))
4536 return drm_edid_duplicate(intel_connector->edid);
4538 return drm_get_edid(&intel_connector->base,
4539 &intel_dp->aux.ddc);
4543 intel_dp_set_edid(struct intel_dp *intel_dp)
4545 struct intel_connector *intel_connector = intel_dp->attached_connector;
4548 intel_dp_unset_edid(intel_dp);
4549 edid = intel_dp_get_edid(intel_dp);
4550 intel_connector->detect_edid = edid;
4552 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4553 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4555 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4559 intel_dp_unset_edid(struct intel_dp *intel_dp)
4561 struct intel_connector *intel_connector = intel_dp->attached_connector;
4563 kfree(intel_connector->detect_edid);
4564 intel_connector->detect_edid = NULL;
4566 intel_dp->has_audio = false;
4570 intel_dp_long_pulse(struct intel_connector *intel_connector)
4572 struct drm_connector *connector = &intel_connector->base;
4573 struct intel_dp *intel_dp = intel_attached_dp(connector);
4574 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4575 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4576 struct drm_device *dev = connector->dev;
4577 enum drm_connector_status status;
4578 u8 sink_irq_vector = 0;
4580 WARN_ON(!drm_modeset_is_locked(&connector->dev->mode_config.connection_mutex));
4582 intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain);
4584 /* Can't disconnect eDP, but you can close the lid... */
4585 if (is_edp(intel_dp))
4586 status = edp_detect(intel_dp);
4587 else if (intel_digital_port_connected(to_i915(dev),
4588 dp_to_dig_port(intel_dp)))
4589 status = intel_dp_detect_dpcd(intel_dp);
4591 status = connector_status_disconnected;
4593 if (status == connector_status_disconnected) {
4594 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4596 if (intel_dp->is_mst) {
4597 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4599 intel_dp->mst_mgr.mst_state);
4600 intel_dp->is_mst = false;
4601 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4608 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4609 intel_encoder->type = INTEL_OUTPUT_DP;
4611 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4612 yesno(intel_dp_source_supports_hbr2(intel_dp)),
4613 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4615 if (intel_dp->reset_link_params) {
4616 /* Set the max lane count for sink */
4617 intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
4619 /* Set the max link BW for sink */
4620 intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp);
4622 intel_dp->reset_link_params = false;
4625 intel_dp_print_rates(intel_dp);
4627 intel_dp_read_desc(intel_dp);
4629 intel_dp_configure_mst(intel_dp);
4631 if (intel_dp->is_mst) {
4633 * If we are in MST mode then this connector
4634 * won't appear connected or have anything
4637 status = connector_status_disconnected;
4641 * If display is now connected check links status,
4642 * there has been known issues of link loss triggerring
4645 * Some sinks (eg. ASUS PB287Q) seem to perform some
4646 * weird HPD ping pong during modesets. So we can apparently
4647 * end up with HPD going low during a modeset, and then
4648 * going back up soon after. And once that happens we must
4649 * retrain the link to get a picture. That's in case no
4650 * userspace component reacted to intermittent HPD dip.
4652 intel_dp_check_link_status(intel_dp);
4656 * Clearing NACK and defer counts to get their exact values
4657 * while reading EDID which are required by Compliance tests
4658 * 4.2.2.4 and 4.2.2.5
4660 intel_dp->aux.i2c_nack_count = 0;
4661 intel_dp->aux.i2c_defer_count = 0;
4663 intel_dp_set_edid(intel_dp);
4664 if (is_edp(intel_dp) || intel_connector->detect_edid)
4665 status = connector_status_connected;
4666 intel_dp->detect_done = true;
4668 /* Try to read the source of the interrupt */
4669 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4670 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4671 sink_irq_vector != 0) {
4672 /* Clear interrupt source */
4673 drm_dp_dpcd_writeb(&intel_dp->aux,
4674 DP_DEVICE_SERVICE_IRQ_VECTOR,
4677 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4678 intel_dp_handle_test_request(intel_dp);
4679 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4680 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4684 if (status != connector_status_connected && !intel_dp->is_mst)
4685 intel_dp_unset_edid(intel_dp);
4687 intel_display_power_put(to_i915(dev), intel_dp->aux_power_domain);
4692 intel_dp_detect(struct drm_connector *connector,
4693 struct drm_modeset_acquire_ctx *ctx,
4696 struct intel_dp *intel_dp = intel_attached_dp(connector);
4697 int status = connector->status;
4699 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4700 connector->base.id, connector->name);
4702 /* If full detect is not performed yet, do a full detect */
4703 if (!intel_dp->detect_done)
4704 status = intel_dp_long_pulse(intel_dp->attached_connector);
4706 intel_dp->detect_done = false;
4712 intel_dp_force(struct drm_connector *connector)
4714 struct intel_dp *intel_dp = intel_attached_dp(connector);
4715 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4716 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4718 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4719 connector->base.id, connector->name);
4720 intel_dp_unset_edid(intel_dp);
4722 if (connector->status != connector_status_connected)
4725 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4727 intel_dp_set_edid(intel_dp);
4729 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4731 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4732 intel_encoder->type = INTEL_OUTPUT_DP;
4735 static int intel_dp_get_modes(struct drm_connector *connector)
4737 struct intel_connector *intel_connector = to_intel_connector(connector);
4740 edid = intel_connector->detect_edid;
4742 int ret = intel_connector_update_modes(connector, edid);
4747 /* if eDP has no EDID, fall back to fixed mode */
4748 if (is_edp(intel_attached_dp(connector)) &&
4749 intel_connector->panel.fixed_mode) {
4750 struct drm_display_mode *mode;
4752 mode = drm_mode_duplicate(connector->dev,
4753 intel_connector->panel.fixed_mode);
4755 drm_mode_probed_add(connector, mode);
4764 intel_dp_detect_audio(struct drm_connector *connector)
4766 bool has_audio = false;
4769 edid = to_intel_connector(connector)->detect_edid;
4771 has_audio = drm_detect_monitor_audio(edid);
4777 intel_dp_set_property(struct drm_connector *connector,
4778 struct drm_property *property,
4781 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4782 struct intel_connector *intel_connector = to_intel_connector(connector);
4783 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4784 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4787 ret = drm_object_property_set_value(&connector->base, property, val);
4791 if (property == dev_priv->force_audio_property) {
4795 if (i == intel_dp->force_audio)
4798 intel_dp->force_audio = i;
4800 if (i == HDMI_AUDIO_AUTO)
4801 has_audio = intel_dp_detect_audio(connector);
4803 has_audio = (i == HDMI_AUDIO_ON);
4805 if (has_audio == intel_dp->has_audio)
4808 intel_dp->has_audio = has_audio;
4812 if (property == dev_priv->broadcast_rgb_property) {
4813 bool old_auto = intel_dp->color_range_auto;
4814 bool old_range = intel_dp->limited_color_range;
4817 case INTEL_BROADCAST_RGB_AUTO:
4818 intel_dp->color_range_auto = true;
4820 case INTEL_BROADCAST_RGB_FULL:
4821 intel_dp->color_range_auto = false;
4822 intel_dp->limited_color_range = false;
4824 case INTEL_BROADCAST_RGB_LIMITED:
4825 intel_dp->color_range_auto = false;
4826 intel_dp->limited_color_range = true;
4832 if (old_auto == intel_dp->color_range_auto &&
4833 old_range == intel_dp->limited_color_range)
4839 if (is_edp(intel_dp) &&
4840 property == connector->dev->mode_config.scaling_mode_property) {
4841 if (val == DRM_MODE_SCALE_NONE) {
4842 DRM_DEBUG_KMS("no scaling not supported\n");
4845 if (HAS_GMCH_DISPLAY(dev_priv) &&
4846 val == DRM_MODE_SCALE_CENTER) {
4847 DRM_DEBUG_KMS("centering not supported\n");
4851 if (intel_connector->panel.fitting_mode == val) {
4852 /* the eDP scaling property is not changed */
4855 intel_connector->panel.fitting_mode = val;
4863 if (intel_encoder->base.crtc)
4864 intel_crtc_restore_mode(intel_encoder->base.crtc);
4870 intel_dp_connector_register(struct drm_connector *connector)
4872 struct intel_dp *intel_dp = intel_attached_dp(connector);
4875 ret = intel_connector_register(connector);
4879 i915_debugfs_connector_add(connector);
4881 DRM_DEBUG_KMS("registering %s bus for %s\n",
4882 intel_dp->aux.name, connector->kdev->kobj.name);
4884 intel_dp->aux.dev = connector->kdev;
4885 return drm_dp_aux_register(&intel_dp->aux);
4889 intel_dp_connector_unregister(struct drm_connector *connector)
4891 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4892 intel_connector_unregister(connector);
4896 intel_dp_connector_destroy(struct drm_connector *connector)
4898 struct intel_connector *intel_connector = to_intel_connector(connector);
4900 kfree(intel_connector->detect_edid);
4902 if (!IS_ERR_OR_NULL(intel_connector->edid))
4903 kfree(intel_connector->edid);
4905 /* Can't call is_edp() since the encoder may have been destroyed
4907 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4908 intel_panel_fini(&intel_connector->panel);
4910 drm_connector_cleanup(connector);
4914 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4916 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4917 struct intel_dp *intel_dp = &intel_dig_port->dp;
4919 intel_dp_mst_encoder_cleanup(intel_dig_port);
4920 if (is_edp(intel_dp)) {
4921 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4923 * vdd might still be enabled do to the delayed vdd off.
4924 * Make sure vdd is actually turned off here.
4927 edp_panel_vdd_off_sync(intel_dp);
4928 pps_unlock(intel_dp);
4930 if (intel_dp->edp_notifier.notifier_call) {
4931 unregister_reboot_notifier(&intel_dp->edp_notifier);
4932 intel_dp->edp_notifier.notifier_call = NULL;
4936 intel_dp_aux_fini(intel_dp);
4938 drm_encoder_cleanup(encoder);
4939 kfree(intel_dig_port);
4942 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4944 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4946 if (!is_edp(intel_dp))
4950 * vdd might still be enabled do to the delayed vdd off.
4951 * Make sure vdd is actually turned off here.
4953 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4955 edp_panel_vdd_off_sync(intel_dp);
4956 pps_unlock(intel_dp);
4959 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4961 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4962 struct drm_device *dev = intel_dig_port->base.base.dev;
4963 struct drm_i915_private *dev_priv = to_i915(dev);
4965 lockdep_assert_held(&dev_priv->pps_mutex);
4967 if (!edp_have_panel_vdd(intel_dp))
4971 * The VDD bit needs a power domain reference, so if the bit is
4972 * already enabled when we boot or resume, grab this reference and
4973 * schedule a vdd off, so we don't hold on to the reference
4976 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4977 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4979 edp_panel_vdd_schedule_off(intel_dp);
4982 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
4984 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4986 if ((intel_dp->DP & DP_PORT_EN) == 0)
4987 return INVALID_PIPE;
4989 if (IS_CHERRYVIEW(dev_priv))
4990 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
4992 return PORT_TO_PIPE(intel_dp->DP);
4995 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4997 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4998 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4999 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5001 if (!HAS_DDI(dev_priv))
5002 intel_dp->DP = I915_READ(intel_dp->output_reg);
5005 lspcon_resume(lspcon);
5007 intel_dp->reset_link_params = true;
5011 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5012 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5014 if (is_edp(intel_dp)) {
5015 /* Reinit the power sequencer, in case BIOS did something with it. */
5016 intel_dp_pps_init(encoder->dev, intel_dp);
5017 intel_edp_panel_vdd_sanitize(intel_dp);
5020 pps_unlock(intel_dp);
5023 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5024 .dpms = drm_atomic_helper_connector_dpms,
5025 .force = intel_dp_force,
5026 .fill_modes = drm_helper_probe_single_connector_modes,
5027 .set_property = intel_dp_set_property,
5028 .atomic_get_property = intel_connector_atomic_get_property,
5029 .late_register = intel_dp_connector_register,
5030 .early_unregister = intel_dp_connector_unregister,
5031 .destroy = intel_dp_connector_destroy,
5032 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5033 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
5036 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5037 .detect_ctx = intel_dp_detect,
5038 .get_modes = intel_dp_get_modes,
5039 .mode_valid = intel_dp_mode_valid,
5042 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5043 .reset = intel_dp_encoder_reset,
5044 .destroy = intel_dp_encoder_destroy,
5048 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5050 struct intel_dp *intel_dp = &intel_dig_port->dp;
5051 struct drm_device *dev = intel_dig_port->base.base.dev;
5052 struct drm_i915_private *dev_priv = to_i915(dev);
5053 enum irqreturn ret = IRQ_NONE;
5055 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
5056 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
5057 intel_dig_port->base.type = INTEL_OUTPUT_DP;
5059 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5061 * vdd off can generate a long pulse on eDP which
5062 * would require vdd on to handle it, and thus we
5063 * would end up in an endless cycle of
5064 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5066 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5067 port_name(intel_dig_port->port));
5071 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5072 port_name(intel_dig_port->port),
5073 long_hpd ? "long" : "short");
5076 intel_dp->reset_link_params = true;
5077 intel_dp->detect_done = false;
5081 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5083 if (intel_dp->is_mst) {
5084 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5086 * If we were in MST mode, and device is not
5087 * there, get out of MST mode
5089 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5090 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5091 intel_dp->is_mst = false;
5092 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5094 intel_dp->detect_done = false;
5099 if (!intel_dp->is_mst) {
5100 if (!intel_dp_short_pulse(intel_dp)) {
5101 intel_dp->detect_done = false;
5109 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5114 /* check the VBT to see whether the eDP is on another port */
5115 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port)
5118 * eDP not supported on g4x. so bail out early just
5119 * for a bit extra safety in case the VBT is bonkers.
5121 if (INTEL_GEN(dev_priv) < 5)
5124 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5127 return intel_bios_is_port_edp(dev_priv, port);
5131 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5133 struct intel_connector *intel_connector = to_intel_connector(connector);
5135 intel_attach_force_audio_property(connector);
5136 intel_attach_broadcast_rgb_property(connector);
5137 intel_dp->color_range_auto = true;
5139 if (is_edp(intel_dp)) {
5140 drm_mode_create_scaling_mode_property(connector->dev);
5141 drm_object_attach_property(
5143 connector->dev->mode_config.scaling_mode_property,
5144 DRM_MODE_SCALE_ASPECT);
5145 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5149 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5151 intel_dp->panel_power_off_time = ktime_get_boottime();
5152 intel_dp->last_power_on = jiffies;
5153 intel_dp->last_backlight_off = jiffies;
5157 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
5158 struct intel_dp *intel_dp, struct edp_power_seq *seq)
5160 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5161 struct pps_registers regs;
5163 intel_pps_get_registers(dev_priv, intel_dp, ®s);
5165 /* Workaround: Need to write PP_CONTROL with the unlock key as
5166 * the very first thing. */
5167 pp_ctl = ironlake_get_pp_control(intel_dp);
5169 pp_on = I915_READ(regs.pp_on);
5170 pp_off = I915_READ(regs.pp_off);
5171 if (!IS_GEN9_LP(dev_priv)) {
5172 I915_WRITE(regs.pp_ctrl, pp_ctl);
5173 pp_div = I915_READ(regs.pp_div);
5176 /* Pull timing values out of registers */
5177 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5178 PANEL_POWER_UP_DELAY_SHIFT;
5180 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5181 PANEL_LIGHT_ON_DELAY_SHIFT;
5183 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5184 PANEL_LIGHT_OFF_DELAY_SHIFT;
5186 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5187 PANEL_POWER_DOWN_DELAY_SHIFT;
5189 if (IS_GEN9_LP(dev_priv)) {
5190 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5191 BXT_POWER_CYCLE_DELAY_SHIFT;
5193 seq->t11_t12 = (tmp - 1) * 1000;
5197 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5198 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5203 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5205 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5207 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5211 intel_pps_verify_state(struct drm_i915_private *dev_priv,
5212 struct intel_dp *intel_dp)
5214 struct edp_power_seq hw;
5215 struct edp_power_seq *sw = &intel_dp->pps_delays;
5217 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
5219 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5220 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5221 DRM_ERROR("PPS state mismatch\n");
5222 intel_pps_dump_state("sw", sw);
5223 intel_pps_dump_state("hw", &hw);
5228 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5229 struct intel_dp *intel_dp)
5231 struct drm_i915_private *dev_priv = to_i915(dev);
5232 struct edp_power_seq cur, vbt, spec,
5233 *final = &intel_dp->pps_delays;
5235 lockdep_assert_held(&dev_priv->pps_mutex);
5237 /* already initialized? */
5238 if (final->t11_t12 != 0)
5241 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5243 intel_pps_dump_state("cur", &cur);
5245 vbt = dev_priv->vbt.edp.pps;
5247 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5248 * our hw here, which are all in 100usec. */
5249 spec.t1_t3 = 210 * 10;
5250 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5251 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5252 spec.t10 = 500 * 10;
5253 /* This one is special and actually in units of 100ms, but zero
5254 * based in the hw (so we need to add 100 ms). But the sw vbt
5255 * table multiplies it with 1000 to make it in units of 100usec,
5257 spec.t11_t12 = (510 + 100) * 10;
5259 intel_pps_dump_state("vbt", &vbt);
5261 /* Use the max of the register settings and vbt. If both are
5262 * unset, fall back to the spec limits. */
5263 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5265 max(cur.field, vbt.field))
5266 assign_final(t1_t3);
5270 assign_final(t11_t12);
5273 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5274 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5275 intel_dp->backlight_on_delay = get_delay(t8);
5276 intel_dp->backlight_off_delay = get_delay(t9);
5277 intel_dp->panel_power_down_delay = get_delay(t10);
5278 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5281 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5282 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5283 intel_dp->panel_power_cycle_delay);
5285 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5286 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5289 * We override the HW backlight delays to 1 because we do manual waits
5290 * on them. For T8, even BSpec recommends doing it. For T9, if we
5291 * don't do this, we'll end up waiting for the backlight off delay
5292 * twice: once when we do the manual sleep, and once when we disable
5293 * the panel and wait for the PP_STATUS bit to become zero.
5300 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5301 struct intel_dp *intel_dp,
5302 bool force_disable_vdd)
5304 struct drm_i915_private *dev_priv = to_i915(dev);
5305 u32 pp_on, pp_off, pp_div, port_sel = 0;
5306 int div = dev_priv->rawclk_freq / 1000;
5307 struct pps_registers regs;
5308 enum port port = dp_to_dig_port(intel_dp)->port;
5309 const struct edp_power_seq *seq = &intel_dp->pps_delays;
5311 lockdep_assert_held(&dev_priv->pps_mutex);
5313 intel_pps_get_registers(dev_priv, intel_dp, ®s);
5316 * On some VLV machines the BIOS can leave the VDD
5317 * enabled even on power seqeuencers which aren't
5318 * hooked up to any port. This would mess up the
5319 * power domain tracking the first time we pick
5320 * one of these power sequencers for use since
5321 * edp_panel_vdd_on() would notice that the VDD was
5322 * already on and therefore wouldn't grab the power
5323 * domain reference. Disable VDD first to avoid this.
5324 * This also avoids spuriously turning the VDD on as
5325 * soon as the new power seqeuencer gets initialized.
5327 if (force_disable_vdd) {
5328 u32 pp = ironlake_get_pp_control(intel_dp);
5330 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5332 if (pp & EDP_FORCE_VDD)
5333 DRM_DEBUG_KMS("VDD already on, disabling first\n");
5335 pp &= ~EDP_FORCE_VDD;
5337 I915_WRITE(regs.pp_ctrl, pp);
5340 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5341 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5342 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5343 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5344 /* Compute the divisor for the pp clock, simply match the Bspec
5346 if (IS_GEN9_LP(dev_priv)) {
5347 pp_div = I915_READ(regs.pp_ctrl);
5348 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5349 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5350 << BXT_POWER_CYCLE_DELAY_SHIFT);
5352 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5353 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5354 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5357 /* Haswell doesn't have any port selection bits for the panel
5358 * power sequencer any more. */
5359 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5360 port_sel = PANEL_PORT_SELECT_VLV(port);
5361 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5363 port_sel = PANEL_PORT_SELECT_DPA;
5365 port_sel = PANEL_PORT_SELECT_DPD;
5370 I915_WRITE(regs.pp_on, pp_on);
5371 I915_WRITE(regs.pp_off, pp_off);
5372 if (IS_GEN9_LP(dev_priv))
5373 I915_WRITE(regs.pp_ctrl, pp_div);
5375 I915_WRITE(regs.pp_div, pp_div);
5377 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5378 I915_READ(regs.pp_on),
5379 I915_READ(regs.pp_off),
5380 IS_GEN9_LP(dev_priv) ?
5381 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5382 I915_READ(regs.pp_div));
5385 static void intel_dp_pps_init(struct drm_device *dev,
5386 struct intel_dp *intel_dp)
5388 struct drm_i915_private *dev_priv = to_i915(dev);
5390 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5391 vlv_initial_power_sequencer_setup(intel_dp);
5393 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5394 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
5399 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5400 * @dev_priv: i915 device
5401 * @crtc_state: a pointer to the active intel_crtc_state
5402 * @refresh_rate: RR to be programmed
5404 * This function gets called when refresh rate (RR) has to be changed from
5405 * one frequency to another. Switches can be between high and low RR
5406 * supported by the panel or to any other RR based on media playback (in
5407 * this case, RR value needs to be passed from user space).
5409 * The caller of this function needs to take a lock on dev_priv->drrs.
5411 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5412 struct intel_crtc_state *crtc_state,
5415 struct intel_encoder *encoder;
5416 struct intel_digital_port *dig_port = NULL;
5417 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5419 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5421 if (refresh_rate <= 0) {
5422 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5426 if (intel_dp == NULL) {
5427 DRM_DEBUG_KMS("DRRS not supported.\n");
5432 * FIXME: This needs proper synchronization with psr state for some
5433 * platforms that cannot have PSR and DRRS enabled at the same time.
5436 dig_port = dp_to_dig_port(intel_dp);
5437 encoder = &dig_port->base;
5438 intel_crtc = to_intel_crtc(encoder->base.crtc);
5441 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5445 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5446 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5450 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5452 index = DRRS_LOW_RR;
5454 if (index == dev_priv->drrs.refresh_rate_type) {
5456 "DRRS requested for previously set RR...ignoring\n");
5460 if (!crtc_state->base.active) {
5461 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5465 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5468 intel_dp_set_m_n(intel_crtc, M1_N1);
5471 intel_dp_set_m_n(intel_crtc, M2_N2);
5475 DRM_ERROR("Unsupported refreshrate type\n");
5477 } else if (INTEL_GEN(dev_priv) > 6) {
5478 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5481 val = I915_READ(reg);
5482 if (index > DRRS_HIGH_RR) {
5483 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5484 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5486 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5488 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5489 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5491 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5493 I915_WRITE(reg, val);
5496 dev_priv->drrs.refresh_rate_type = index;
5498 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5502 * intel_edp_drrs_enable - init drrs struct if supported
5503 * @intel_dp: DP struct
5504 * @crtc_state: A pointer to the active crtc state.
5506 * Initializes frontbuffer_bits and drrs.dp
5508 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5509 struct intel_crtc_state *crtc_state)
5511 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5512 struct drm_i915_private *dev_priv = to_i915(dev);
5514 if (!crtc_state->has_drrs) {
5515 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5519 mutex_lock(&dev_priv->drrs.mutex);
5520 if (WARN_ON(dev_priv->drrs.dp)) {
5521 DRM_ERROR("DRRS already enabled\n");
5525 dev_priv->drrs.busy_frontbuffer_bits = 0;
5527 dev_priv->drrs.dp = intel_dp;
5530 mutex_unlock(&dev_priv->drrs.mutex);
5534 * intel_edp_drrs_disable - Disable DRRS
5535 * @intel_dp: DP struct
5536 * @old_crtc_state: Pointer to old crtc_state.
5539 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5540 struct intel_crtc_state *old_crtc_state)
5542 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5543 struct drm_i915_private *dev_priv = to_i915(dev);
5545 if (!old_crtc_state->has_drrs)
5548 mutex_lock(&dev_priv->drrs.mutex);
5549 if (!dev_priv->drrs.dp) {
5550 mutex_unlock(&dev_priv->drrs.mutex);
5554 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5555 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5556 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5558 dev_priv->drrs.dp = NULL;
5559 mutex_unlock(&dev_priv->drrs.mutex);
5561 cancel_delayed_work_sync(&dev_priv->drrs.work);
5564 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5566 struct drm_i915_private *dev_priv =
5567 container_of(work, typeof(*dev_priv), drrs.work.work);
5568 struct intel_dp *intel_dp;
5570 mutex_lock(&dev_priv->drrs.mutex);
5572 intel_dp = dev_priv->drrs.dp;
5578 * The delayed work can race with an invalidate hence we need to
5582 if (dev_priv->drrs.busy_frontbuffer_bits)
5585 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5586 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5588 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5589 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5593 mutex_unlock(&dev_priv->drrs.mutex);
5597 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5598 * @dev_priv: i915 device
5599 * @frontbuffer_bits: frontbuffer plane tracking bits
5601 * This function gets called everytime rendering on the given planes start.
5602 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5604 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5606 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5607 unsigned int frontbuffer_bits)
5609 struct drm_crtc *crtc;
5612 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5615 cancel_delayed_work(&dev_priv->drrs.work);
5617 mutex_lock(&dev_priv->drrs.mutex);
5618 if (!dev_priv->drrs.dp) {
5619 mutex_unlock(&dev_priv->drrs.mutex);
5623 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5624 pipe = to_intel_crtc(crtc)->pipe;
5626 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5627 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5629 /* invalidate means busy screen hence upclock */
5630 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5631 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5632 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5634 mutex_unlock(&dev_priv->drrs.mutex);
5638 * intel_edp_drrs_flush - Restart Idleness DRRS
5639 * @dev_priv: i915 device
5640 * @frontbuffer_bits: frontbuffer plane tracking bits
5642 * This function gets called every time rendering on the given planes has
5643 * completed or flip on a crtc is completed. So DRRS should be upclocked
5644 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5645 * if no other planes are dirty.
5647 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5649 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5650 unsigned int frontbuffer_bits)
5652 struct drm_crtc *crtc;
5655 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5658 cancel_delayed_work(&dev_priv->drrs.work);
5660 mutex_lock(&dev_priv->drrs.mutex);
5661 if (!dev_priv->drrs.dp) {
5662 mutex_unlock(&dev_priv->drrs.mutex);
5666 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5667 pipe = to_intel_crtc(crtc)->pipe;
5669 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5670 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5672 /* flush means busy screen hence upclock */
5673 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5674 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5675 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5678 * flush also means no more activity hence schedule downclock, if all
5679 * other fbs are quiescent too
5681 if (!dev_priv->drrs.busy_frontbuffer_bits)
5682 schedule_delayed_work(&dev_priv->drrs.work,
5683 msecs_to_jiffies(1000));
5684 mutex_unlock(&dev_priv->drrs.mutex);
5688 * DOC: Display Refresh Rate Switching (DRRS)
5690 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5691 * which enables swtching between low and high refresh rates,
5692 * dynamically, based on the usage scenario. This feature is applicable
5693 * for internal panels.
5695 * Indication that the panel supports DRRS is given by the panel EDID, which
5696 * would list multiple refresh rates for one resolution.
5698 * DRRS is of 2 types - static and seamless.
5699 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5700 * (may appear as a blink on screen) and is used in dock-undock scenario.
5701 * Seamless DRRS involves changing RR without any visual effect to the user
5702 * and can be used during normal system usage. This is done by programming
5703 * certain registers.
5705 * Support for static/seamless DRRS may be indicated in the VBT based on
5706 * inputs from the panel spec.
5708 * DRRS saves power by switching to low RR based on usage scenarios.
5710 * The implementation is based on frontbuffer tracking implementation. When
5711 * there is a disturbance on the screen triggered by user activity or a periodic
5712 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5713 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5716 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5717 * and intel_edp_drrs_flush() are called.
5719 * DRRS can be further extended to support other internal panels and also
5720 * the scenario of video playback wherein RR is set based on the rate
5721 * requested by userspace.
5725 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5726 * @intel_connector: eDP connector
5727 * @fixed_mode: preferred mode of panel
5729 * This function is called only once at driver load to initialize basic
5733 * Downclock mode if panel supports it, else return NULL.
5734 * DRRS support is determined by the presence of downclock mode (apart
5735 * from VBT setting).
5737 static struct drm_display_mode *
5738 intel_dp_drrs_init(struct intel_connector *intel_connector,
5739 struct drm_display_mode *fixed_mode)
5741 struct drm_connector *connector = &intel_connector->base;
5742 struct drm_device *dev = connector->dev;
5743 struct drm_i915_private *dev_priv = to_i915(dev);
5744 struct drm_display_mode *downclock_mode = NULL;
5746 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5747 mutex_init(&dev_priv->drrs.mutex);
5749 if (INTEL_GEN(dev_priv) <= 6) {
5750 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5754 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5755 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5759 downclock_mode = intel_find_panel_downclock
5760 (dev_priv, fixed_mode, connector);
5762 if (!downclock_mode) {
5763 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5767 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5769 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5770 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5771 return downclock_mode;
5774 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5775 struct intel_connector *intel_connector)
5777 struct drm_connector *connector = &intel_connector->base;
5778 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5779 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5780 struct drm_device *dev = intel_encoder->base.dev;
5781 struct drm_i915_private *dev_priv = to_i915(dev);
5782 struct drm_display_mode *fixed_mode = NULL;
5783 struct drm_display_mode *downclock_mode = NULL;
5785 struct drm_display_mode *scan;
5787 enum pipe pipe = INVALID_PIPE;
5789 if (!is_edp(intel_dp))
5793 * On IBX/CPT we may get here with LVDS already registered. Since the
5794 * driver uses the only internal power sequencer available for both
5795 * eDP and LVDS bail out early in this case to prevent interfering
5796 * with an already powered-on LVDS power sequencer.
5798 if (intel_get_lvds_encoder(dev)) {
5799 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5800 DRM_INFO("LVDS was detected, not registering eDP\n");
5807 intel_dp_init_panel_power_timestamps(intel_dp);
5808 intel_dp_pps_init(dev, intel_dp);
5809 intel_edp_panel_vdd_sanitize(intel_dp);
5811 pps_unlock(intel_dp);
5813 /* Cache DPCD and EDID for edp. */
5814 has_dpcd = intel_edp_init_dpcd(intel_dp);
5817 /* if this fails, presume the device is a ghost */
5818 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5822 mutex_lock(&dev->mode_config.mutex);
5823 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5825 if (drm_add_edid_modes(connector, edid)) {
5826 drm_mode_connector_update_edid_property(connector,
5828 drm_edid_to_eld(connector, edid);
5831 edid = ERR_PTR(-EINVAL);
5834 edid = ERR_PTR(-ENOENT);
5836 intel_connector->edid = edid;
5838 /* prefer fixed mode from EDID if available */
5839 list_for_each_entry(scan, &connector->probed_modes, head) {
5840 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5841 fixed_mode = drm_mode_duplicate(dev, scan);
5842 downclock_mode = intel_dp_drrs_init(
5843 intel_connector, fixed_mode);
5848 /* fallback to VBT if available for eDP */
5849 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5850 fixed_mode = drm_mode_duplicate(dev,
5851 dev_priv->vbt.lfp_lvds_vbt_mode);
5853 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5854 connector->display_info.width_mm = fixed_mode->width_mm;
5855 connector->display_info.height_mm = fixed_mode->height_mm;
5858 mutex_unlock(&dev->mode_config.mutex);
5860 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5861 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5862 register_reboot_notifier(&intel_dp->edp_notifier);
5865 * Figure out the current pipe for the initial backlight setup.
5866 * If the current pipe isn't valid, try the PPS pipe, and if that
5867 * fails just assume pipe A.
5869 pipe = vlv_active_pipe(intel_dp);
5871 if (pipe != PIPE_A && pipe != PIPE_B)
5872 pipe = intel_dp->pps_pipe;
5874 if (pipe != PIPE_A && pipe != PIPE_B)
5877 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5881 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5882 intel_connector->panel.backlight.power = intel_edp_backlight_power;
5883 intel_panel_setup_backlight(connector, pipe);
5888 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5890 * vdd might still be enabled do to the delayed vdd off.
5891 * Make sure vdd is actually turned off here.
5894 edp_panel_vdd_off_sync(intel_dp);
5895 pps_unlock(intel_dp);
5900 /* Set up the hotplug pin and aux power domain. */
5902 intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
5904 struct intel_encoder *encoder = &intel_dig_port->base;
5905 struct intel_dp *intel_dp = &intel_dig_port->dp;
5907 switch (intel_dig_port->port) {
5909 encoder->hpd_pin = HPD_PORT_A;
5910 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A;
5913 encoder->hpd_pin = HPD_PORT_B;
5914 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B;
5917 encoder->hpd_pin = HPD_PORT_C;
5918 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C;
5921 encoder->hpd_pin = HPD_PORT_D;
5922 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5925 encoder->hpd_pin = HPD_PORT_E;
5927 /* FIXME: Check VBT for actual wiring of PORT E */
5928 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5931 MISSING_CASE(intel_dig_port->port);
5936 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5937 struct intel_connector *intel_connector)
5939 struct drm_connector *connector = &intel_connector->base;
5940 struct intel_dp *intel_dp = &intel_dig_port->dp;
5941 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5942 struct drm_device *dev = intel_encoder->base.dev;
5943 struct drm_i915_private *dev_priv = to_i915(dev);
5944 enum port port = intel_dig_port->port;
5947 if (WARN(intel_dig_port->max_lanes < 1,
5948 "Not enough lanes (%d) for DP on port %c\n",
5949 intel_dig_port->max_lanes, port_name(port)))
5952 intel_dp->reset_link_params = true;
5953 intel_dp->pps_pipe = INVALID_PIPE;
5954 intel_dp->active_pipe = INVALID_PIPE;
5956 /* intel_dp vfuncs */
5957 if (INTEL_GEN(dev_priv) >= 9)
5958 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5959 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5960 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5961 else if (HAS_PCH_SPLIT(dev_priv))
5962 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5964 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5966 if (INTEL_GEN(dev_priv) >= 9)
5967 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5969 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5971 if (HAS_DDI(dev_priv))
5972 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5974 /* Preserve the current hw state. */
5975 intel_dp->DP = I915_READ(intel_dp->output_reg);
5976 intel_dp->attached_connector = intel_connector;
5978 if (intel_dp_is_edp(dev_priv, port))
5979 type = DRM_MODE_CONNECTOR_eDP;
5981 type = DRM_MODE_CONNECTOR_DisplayPort;
5983 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5984 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5987 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5988 * for DP the encoder type can be set by the caller to
5989 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5991 if (type == DRM_MODE_CONNECTOR_eDP)
5992 intel_encoder->type = INTEL_OUTPUT_EDP;
5994 /* eDP only on port B and/or C on vlv/chv */
5995 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
5996 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5999 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6000 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6003 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6004 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6006 connector->interlace_allowed = true;
6007 connector->doublescan_allowed = 0;
6009 intel_dp_init_connector_port_info(intel_dig_port);
6011 intel_dp_aux_init(intel_dp);
6013 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6014 edp_panel_vdd_work);
6016 intel_connector_attach_encoder(intel_connector, intel_encoder);
6018 if (HAS_DDI(dev_priv))
6019 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6021 intel_connector->get_hw_state = intel_connector_get_hw_state;
6023 /* init MST on ports that can support it */
6024 if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
6025 (port == PORT_B || port == PORT_C || port == PORT_D))
6026 intel_dp_mst_encoder_init(intel_dig_port,
6027 intel_connector->base.base.id);
6029 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6030 intel_dp_aux_fini(intel_dp);
6031 intel_dp_mst_encoder_cleanup(intel_dig_port);
6035 intel_dp_add_properties(intel_dp, connector);
6037 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6038 * 0xd. Failure to do so will result in spurious interrupts being
6039 * generated on the port when a cable is not attached.
6041 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6042 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6043 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6049 drm_connector_cleanup(connector);
6054 bool intel_dp_init(struct drm_i915_private *dev_priv,
6055 i915_reg_t output_reg,
6058 struct intel_digital_port *intel_dig_port;
6059 struct intel_encoder *intel_encoder;
6060 struct drm_encoder *encoder;
6061 struct intel_connector *intel_connector;
6063 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6064 if (!intel_dig_port)
6067 intel_connector = intel_connector_alloc();
6068 if (!intel_connector)
6069 goto err_connector_alloc;
6071 intel_encoder = &intel_dig_port->base;
6072 encoder = &intel_encoder->base;
6074 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6075 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6076 "DP %c", port_name(port)))
6077 goto err_encoder_init;
6079 intel_encoder->compute_config = intel_dp_compute_config;
6080 intel_encoder->disable = intel_disable_dp;
6081 intel_encoder->get_hw_state = intel_dp_get_hw_state;
6082 intel_encoder->get_config = intel_dp_get_config;
6083 intel_encoder->suspend = intel_dp_encoder_suspend;
6084 if (IS_CHERRYVIEW(dev_priv)) {
6085 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6086 intel_encoder->pre_enable = chv_pre_enable_dp;
6087 intel_encoder->enable = vlv_enable_dp;
6088 intel_encoder->post_disable = chv_post_disable_dp;
6089 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6090 } else if (IS_VALLEYVIEW(dev_priv)) {
6091 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6092 intel_encoder->pre_enable = vlv_pre_enable_dp;
6093 intel_encoder->enable = vlv_enable_dp;
6094 intel_encoder->post_disable = vlv_post_disable_dp;
6096 intel_encoder->pre_enable = g4x_pre_enable_dp;
6097 intel_encoder->enable = g4x_enable_dp;
6098 if (INTEL_GEN(dev_priv) >= 5)
6099 intel_encoder->post_disable = ilk_post_disable_dp;
6102 intel_dig_port->port = port;
6103 intel_dig_port->dp.output_reg = output_reg;
6104 intel_dig_port->max_lanes = 4;
6106 intel_encoder->type = INTEL_OUTPUT_DP;
6107 intel_encoder->power_domain = intel_port_to_power_domain(port);
6108 if (IS_CHERRYVIEW(dev_priv)) {
6110 intel_encoder->crtc_mask = 1 << 2;
6112 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6114 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6116 intel_encoder->cloneable = 0;
6117 intel_encoder->port = port;
6119 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6120 dev_priv->hotplug.irq_port[port] = intel_dig_port;
6122 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6123 goto err_init_connector;
6128 drm_encoder_cleanup(encoder);
6130 kfree(intel_connector);
6131 err_connector_alloc:
6132 kfree(intel_dig_port);
6136 void intel_dp_mst_suspend(struct drm_device *dev)
6138 struct drm_i915_private *dev_priv = to_i915(dev);
6142 for (i = 0; i < I915_MAX_PORTS; i++) {
6143 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6145 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6148 if (intel_dig_port->dp.is_mst)
6149 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6153 void intel_dp_mst_resume(struct drm_device *dev)
6155 struct drm_i915_private *dev_priv = to_i915(dev);
6158 for (i = 0; i < I915_MAX_PORTS; i++) {
6159 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6162 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6165 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6167 intel_dp_check_mst_status(&intel_dig_port->dp);