drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_crtc_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 /* Compliance test status bits  */
  45 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  46 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  47 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  48 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49
  50 struct dp_link_dpll {
  51         int clock;
  52         struct dpll dpll;
  53 };
  54
  55 static const struct dp_link_dpll gen4_dpll[] = {
  56         { 162000,
  57                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  58         { 270000,
  59                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  60 };
  61
  62 static const struct dp_link_dpll pch_dpll[] = {
  63         { 162000,
  64                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  65         { 270000,
  66                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  67 };
  68
  69 static const struct dp_link_dpll vlv_dpll[] = {
  70         { 162000,
  71                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  72         { 270000,
  73                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  74 };
  75
  76 /*
  77  * CHV supports eDP 1.4 that have  more link rates.
  78  * Below only provides the fixed rate but exclude variable rate.
  79  */
  80 static const struct dp_link_dpll chv_dpll[] = {
  81         /*
  82          * CHV requires to program fractional division for m2.
  83          * m2 is stored in fixed point format using formula below
  84          * (m2_int << 22) | m2_fraction
  85          */
  86         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  87                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  88         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  89                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  90         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  92 };
  93
  94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  95                                   324000, 432000, 540000 };
  96 static const int skl_rates[] = { 162000, 216000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int default_rates[] = { 162000, 270000, 540000 };
  99
 100 /**
 101  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 102  * @intel_dp: DP struct
 103  *
 104  * If a CPU or PCH DP output is attached to an eDP panel, this function
 105  * will return true, and false otherwise.
 106  */
 107 static bool is_edp(struct intel_dp *intel_dp)
 108 {
 109         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 110
 111         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 112 }
 113
 114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 115 {
 116         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 117
 118         return intel_dig_port->base.base.dev;
 119 }
 120
 121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 122 {
 123         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 124 }
 125
 126 static void intel_dp_link_down(struct intel_dp *intel_dp);
 127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 130 static void vlv_steal_power_sequencer(struct drm_device *dev,
 131                                       enum pipe pipe);
 132 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 133
 134 static int
 135 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 136 {
 137         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 138
 139         switch (max_link_bw) {
 140         case DP_LINK_BW_1_62:
 141         case DP_LINK_BW_2_7:
 142         case DP_LINK_BW_5_4:
 143                 break;
 144         default:
 145                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 146                      max_link_bw);
 147                 max_link_bw = DP_LINK_BW_1_62;
 148                 break;
 149         }
 150         return max_link_bw;
 151 }
 152
 153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 154 {
 155         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 156         u8 source_max, sink_max;
 157
 158         source_max = intel_dig_port->max_lanes;
 159         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 160
 161         return min(source_max, sink_max);
 162 }
 163
 164 /*
 165  * The units on the numbers in the next two are... bizarre.  Examples will
 166  * make it clearer; this one parallels an example in the eDP spec.
 167  *
 168  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 169  *
 170  *     270000 * 1 * 8 / 10 == 216000
 171  *
 172  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 173  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 174  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 175  * 119000.  At 18bpp that's 2142000 kilobits per second.
 176  *
 177  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 178  * get the result in decakilobits instead of kilobits.
 179  */
 180
 181 static int
 182 intel_dp_link_required(int pixel_clock, int bpp)
 183 {
 184         return (pixel_clock * bpp + 9) / 10;
 185 }
 186
 187 static int
 188 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 189 {
 190         return (max_link_clock * max_lanes * 8) / 10;
 191 }
 192
 193 static int
 194 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 195 {
 196         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 197         struct intel_encoder *encoder = &intel_dig_port->base;
 198         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 199         int max_dotclk = dev_priv->max_dotclk_freq;
 200         int ds_max_dotclk;
 201
 202         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 203
 204         if (type != DP_DS_PORT_TYPE_VGA)
 205                 return max_dotclk;
 206
 207         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 208                                                     intel_dp->downstream_ports);
 209
 210         if (ds_max_dotclk != 0)
 211                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 212
 213         return max_dotclk;
 214 }
 215
 216 static enum drm_mode_status
 217 intel_dp_mode_valid(struct drm_connector *connector,
 218                     struct drm_display_mode *mode)
 219 {
 220         struct intel_dp *intel_dp = intel_attached_dp(connector);
 221         struct intel_connector *intel_connector = to_intel_connector(connector);
 222         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 223         int target_clock = mode->clock;
 224         int max_rate, mode_rate, max_lanes, max_link_clock;
 225         int max_dotclk;
 226
 227         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 228
 229         if (is_edp(intel_dp) && fixed_mode) {
 230                 if (mode->hdisplay > fixed_mode->hdisplay)
 231                         return MODE_PANEL;
 232
 233                 if (mode->vdisplay > fixed_mode->vdisplay)
 234                         return MODE_PANEL;
 235
 236                 target_clock = fixed_mode->clock;
 237         }
 238
 239         max_link_clock = intel_dp_max_link_rate(intel_dp);
 240         max_lanes = intel_dp_max_lane_count(intel_dp);
 241
 242         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 243         mode_rate = intel_dp_link_required(target_clock, 18);
 244
 245         if (mode_rate > max_rate || target_clock > max_dotclk)
 246                 return MODE_CLOCK_HIGH;
 247
 248         if (mode->clock < 10000)
 249                 return MODE_CLOCK_LOW;
 250
 251         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 252                 return MODE_H_ILLEGAL;
 253
 254         return MODE_OK;
 255 }
 256
 257 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 258 {
 259         int     i;
 260         uint32_t v = 0;
 261
 262         if (src_bytes > 4)
 263                 src_bytes = 4;
 264         for (i = 0; i < src_bytes; i++)
 265                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 266         return v;
 267 }
 268
 269 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 270 {
 271         int i;
 272         if (dst_bytes > 4)
 273                 dst_bytes = 4;
 274         for (i = 0; i < dst_bytes; i++)
 275                 dst[i] = src >> ((3-i) * 8);
 276 }
 277
 278 static void
 279 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 280                                     struct intel_dp *intel_dp);
 281 static void
 282 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 283                                               struct intel_dp *intel_dp);
 284 static void
 285 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
 286
 287 static void pps_lock(struct intel_dp *intel_dp)
 288 {
 289         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 290         struct intel_encoder *encoder = &intel_dig_port->base;
 291         struct drm_device *dev = encoder->base.dev;
 292         struct drm_i915_private *dev_priv = to_i915(dev);
 293         enum intel_display_power_domain power_domain;
 294
 295         /*
 296          * See vlv_power_sequencer_reset() why we need
 297          * a power domain reference here.
 298          */
 299         power_domain = intel_display_port_aux_power_domain(encoder);
 300         intel_display_power_get(dev_priv, power_domain);
 301
 302         mutex_lock(&dev_priv->pps_mutex);
 303 }
 304
 305 static void pps_unlock(struct intel_dp *intel_dp)
 306 {
 307         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 308         struct intel_encoder *encoder = &intel_dig_port->base;
 309         struct drm_device *dev = encoder->base.dev;
 310         struct drm_i915_private *dev_priv = to_i915(dev);
 311         enum intel_display_power_domain power_domain;
 312
 313         mutex_unlock(&dev_priv->pps_mutex);
 314
 315         power_domain = intel_display_port_aux_power_domain(encoder);
 316         intel_display_power_put(dev_priv, power_domain);
 317 }
 318
 319 static void
 320 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 321 {
 322         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 323         struct drm_device *dev = intel_dig_port->base.base.dev;
 324         struct drm_i915_private *dev_priv = to_i915(dev);
 325         enum pipe pipe = intel_dp->pps_pipe;
 326         bool pll_enabled, release_cl_override = false;
 327         enum dpio_phy phy = DPIO_PHY(pipe);
 328         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 329         uint32_t DP;
 330
 331         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 332                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 333                  pipe_name(pipe), port_name(intel_dig_port->port)))
 334                 return;
 335
 336         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 337                       pipe_name(pipe), port_name(intel_dig_port->port));
 338
 339         /* Preserve the BIOS-computed detected bit. This is
 340          * supposed to be read-only.
 341          */
 342         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 343         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 344         DP |= DP_PORT_WIDTH(1);
 345         DP |= DP_LINK_TRAIN_PAT_1;
 346
 347         if (IS_CHERRYVIEW(dev))
 348                 DP |= DP_PIPE_SELECT_CHV(pipe);
 349         else if (pipe == PIPE_B)
 350                 DP |= DP_PIPEB_SELECT;
 351
 352         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 353
 354         /*
 355          * The DPLL for the pipe must be enabled for this to work.
 356          * So enable temporarily it if it's not already enabled.
 357          */
 358         if (!pll_enabled) {
 359                 release_cl_override = IS_CHERRYVIEW(dev) &&
 360                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 361
 362                 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 363                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 364                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 365                                   pipe_name(pipe));
 366                         return;
 367                 }
 368         }
 369
 370         /*
 371          * Similar magic as in intel_dp_enable_port().
 372          * We _must_ do this port enable + disable trick
 373          * to make this power seqeuencer lock onto the port.
 374          * Otherwise even VDD force bit won't work.
 375          */
 376         I915_WRITE(intel_dp->output_reg, DP);
 377         POSTING_READ(intel_dp->output_reg);
 378
 379         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 380         POSTING_READ(intel_dp->output_reg);
 381
 382         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 383         POSTING_READ(intel_dp->output_reg);
 384
 385         if (!pll_enabled) {
 386                 vlv_force_pll_off(dev, pipe);
 387
 388                 if (release_cl_override)
 389                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 390         }
 391 }
 392
 393 static enum pipe
 394 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 395 {
 396         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 397         struct drm_device *dev = intel_dig_port->base.base.dev;
 398         struct drm_i915_private *dev_priv = to_i915(dev);
 399         struct intel_encoder *encoder;
 400         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 401         enum pipe pipe;
 402
 403         lockdep_assert_held(&dev_priv->pps_mutex);
 404
 405         /* We should never land here with regular DP ports */
 406         WARN_ON(!is_edp(intel_dp));
 407
 408         if (intel_dp->pps_pipe != INVALID_PIPE)
 409                 return intel_dp->pps_pipe;
 410
 411         /*
 412          * We don't have power sequencer currently.
 413          * Pick one that's not used by other ports.
 414          */
 415         for_each_intel_encoder(dev, encoder) {
 416                 struct intel_dp *tmp;
 417
 418                 if (encoder->type != INTEL_OUTPUT_EDP)
 419                         continue;
 420
 421                 tmp = enc_to_intel_dp(&encoder->base);
 422
 423                 if (tmp->pps_pipe != INVALID_PIPE)
 424                         pipes &= ~(1 << tmp->pps_pipe);
 425         }
 426
 427         /*
 428          * Didn't find one. This should not happen since there
 429          * are two power sequencers and up to two eDP ports.
 430          */
 431         if (WARN_ON(pipes == 0))
 432                 pipe = PIPE_A;
 433         else
 434                 pipe = ffs(pipes) - 1;
 435
 436         vlv_steal_power_sequencer(dev, pipe);
 437         intel_dp->pps_pipe = pipe;
 438
 439         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 440                       pipe_name(intel_dp->pps_pipe),
 441                       port_name(intel_dig_port->port));
 442
 443         /* init power sequencer on this pipe and port */
 444         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 445         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 446
 447         /*
 448          * Even vdd force doesn't work until we've made
 449          * the power sequencer lock in on the port.
 450          */
 451         vlv_power_sequencer_kick(intel_dp);
 452
 453         return intel_dp->pps_pipe;
 454 }
 455
 456 static int
 457 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 458 {
 459         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 460         struct drm_device *dev = intel_dig_port->base.base.dev;
 461         struct drm_i915_private *dev_priv = to_i915(dev);
 462
 463         lockdep_assert_held(&dev_priv->pps_mutex);
 464
 465         /* We should never land here with regular DP ports */
 466         WARN_ON(!is_edp(intel_dp));
 467
 468         /*
 469          * TODO: BXT has 2 PPS instances. The correct port->PPS instance
 470          * mapping needs to be retrieved from VBT, for now just hard-code to
 471          * use instance #0 always.
 472          */
 473         if (!intel_dp->pps_reset)
 474                 return 0;
 475
 476         intel_dp->pps_reset = false;
 477
 478         /*
 479          * Only the HW needs to be reprogrammed, the SW state is fixed and
 480          * has been setup during connector init.
 481          */
 482         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 483
 484         return 0;
 485 }
 486
 487 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 488                                enum pipe pipe);
 489
 490 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 491                                enum pipe pipe)
 492 {
 493         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 494 }
 495
 496 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 497                                 enum pipe pipe)
 498 {
 499         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 500 }
 501
 502 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 503                          enum pipe pipe)
 504 {
 505         return true;
 506 }
 507
 508 static enum pipe
 509 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 510                      enum port port,
 511                      vlv_pipe_check pipe_check)
 512 {
 513         enum pipe pipe;
 514
 515         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 516                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 517                         PANEL_PORT_SELECT_MASK;
 518
 519                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 520                         continue;
 521
 522                 if (!pipe_check(dev_priv, pipe))
 523                         continue;
 524
 525                 return pipe;
 526         }
 527
 528         return INVALID_PIPE;
 529 }
 530
 531 static void
 532 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 533 {
 534         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 535         struct drm_device *dev = intel_dig_port->base.base.dev;
 536         struct drm_i915_private *dev_priv = to_i915(dev);
 537         enum port port = intel_dig_port->port;
 538
 539         lockdep_assert_held(&dev_priv->pps_mutex);
 540
 541         /* try to find a pipe with this port selected */
 542         /* first pick one where the panel is on */
 543         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 544                                                   vlv_pipe_has_pp_on);
 545         /* didn't find one? pick one where vdd is on */
 546         if (intel_dp->pps_pipe == INVALID_PIPE)
 547                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 548                                                           vlv_pipe_has_vdd_on);
 549         /* didn't find one? pick one with just the correct port */
 550         if (intel_dp->pps_pipe == INVALID_PIPE)
 551                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 552                                                           vlv_pipe_any);
 553
 554         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 555         if (intel_dp->pps_pipe == INVALID_PIPE) {
 556                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 557                               port_name(port));
 558                 return;
 559         }
 560
 561         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 562                       port_name(port), pipe_name(intel_dp->pps_pipe));
 563
 564         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 565         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 566 }
 567
 568 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 569 {
 570         struct drm_device *dev = &dev_priv->drm;
 571         struct intel_encoder *encoder;
 572
 573         if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 574                     !IS_BROXTON(dev)))
 575                 return;
 576
 577         /*
 578          * We can't grab pps_mutex here due to deadlock with power_domain
 579          * mutex when power_domain functions are called while holding pps_mutex.
 580          * That also means that in order to use pps_pipe the code needs to
 581          * hold both a power domain reference and pps_mutex, and the power domain
 582          * reference get/put must be done while _not_ holding pps_mutex.
 583          * pps_{lock,unlock}() do these steps in the correct order, so one
 584          * should use them always.
 585          */
 586
 587         for_each_intel_encoder(dev, encoder) {
 588                 struct intel_dp *intel_dp;
 589
 590                 if (encoder->type != INTEL_OUTPUT_EDP)
 591                         continue;
 592
 593                 intel_dp = enc_to_intel_dp(&encoder->base);
 594                 if (IS_BROXTON(dev))
 595                         intel_dp->pps_reset = true;
 596                 else
 597                         intel_dp->pps_pipe = INVALID_PIPE;
 598         }
 599 }
 600
 601 struct pps_registers {
 602         i915_reg_t pp_ctrl;
 603         i915_reg_t pp_stat;
 604         i915_reg_t pp_on;
 605         i915_reg_t pp_off;
 606         i915_reg_t pp_div;
 607 };
 608
 609 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 610                                     struct intel_dp *intel_dp,
 611                                     struct pps_registers *regs)
 612 {
 613         int pps_idx = 0;
 614
 615         memset(regs, 0, sizeof(*regs));
 616
 617         if (IS_BROXTON(dev_priv))
 618                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 619         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 620                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 621
 622         regs->pp_ctrl = PP_CONTROL(pps_idx);
 623         regs->pp_stat = PP_STATUS(pps_idx);
 624         regs->pp_on = PP_ON_DELAYS(pps_idx);
 625         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 626         if (!IS_BROXTON(dev_priv))
 627                 regs->pp_div = PP_DIVISOR(pps_idx);
 628 }
 629
 630 static i915_reg_t
 631 _pp_ctrl_reg(struct intel_dp *intel_dp)
 632 {
 633         struct pps_registers regs;
 634
 635         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 636                                 &regs);
 637
 638         return regs.pp_ctrl;
 639 }
 640
 641 static i915_reg_t
 642 _pp_stat_reg(struct intel_dp *intel_dp)
 643 {
 644         struct pps_registers regs;
 645
 646         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 647                                 &regs);
 648
 649         return regs.pp_stat;
 650 }
 651
 652 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 653    This function only applicable when panel PM state is not to be tracked */
 654 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 655                               void *unused)
 656 {
 657         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 658                                                  edp_notifier);
 659         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 660         struct drm_i915_private *dev_priv = to_i915(dev);
 661
 662         if (!is_edp(intel_dp) || code != SYS_RESTART)
 663                 return 0;
 664
 665         pps_lock(intel_dp);
 666
 667         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 668                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 669                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 670                 u32 pp_div;
 671
 672                 pp_ctrl_reg = PP_CONTROL(pipe);
 673                 pp_div_reg  = PP_DIVISOR(pipe);
 674                 pp_div = I915_READ(pp_div_reg);
 675                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 676
 677                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 678                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 679                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 680                 msleep(intel_dp->panel_power_cycle_delay);
 681         }
 682
 683         pps_unlock(intel_dp);
 684
 685         return 0;
 686 }
 687
 688 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 689 {
 690         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 691         struct drm_i915_private *dev_priv = to_i915(dev);
 692
 693         lockdep_assert_held(&dev_priv->pps_mutex);
 694
 695         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 696             intel_dp->pps_pipe == INVALID_PIPE)
 697                 return false;
 698
 699         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 700 }
 701
 702 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 703 {
 704         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 705         struct drm_i915_private *dev_priv = to_i915(dev);
 706
 707         lockdep_assert_held(&dev_priv->pps_mutex);
 708
 709         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 710             intel_dp->pps_pipe == INVALID_PIPE)
 711                 return false;
 712
 713         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 714 }
 715
 716 static void
 717 intel_dp_check_edp(struct intel_dp *intel_dp)
 718 {
 719         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 720         struct drm_i915_private *dev_priv = to_i915(dev);
 721
 722         if (!is_edp(intel_dp))
 723                 return;
 724
 725         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 726                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 727                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 728                               I915_READ(_pp_stat_reg(intel_dp)),
 729                               I915_READ(_pp_ctrl_reg(intel_dp)));
 730         }
 731 }
 732
 733 static uint32_t
 734 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 735 {
 736         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 737         struct drm_device *dev = intel_dig_port->base.base.dev;
 738         struct drm_i915_private *dev_priv = to_i915(dev);
 739         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 740         uint32_t status;
 741         bool done;
 742
 743 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 744         if (has_aux_irq)
 745                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 746                                           msecs_to_jiffies_timeout(10));
 747         else
 748                 done = wait_for(C, 10) == 0;
 749         if (!done)
 750                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 751                           has_aux_irq);
 752 #undef C
 753
 754         return status;
 755 }
 756
 757 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 758 {
 759         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 760         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 761
 762         if (index)
 763                 return 0;
 764
 765         /*
 766          * The clock divider is based off the hrawclk, and would like to run at
 767          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 768          */
 769         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 770 }
 771
 772 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 773 {
 774         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 775         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 776
 777         if (index)
 778                 return 0;
 779
 780         /*
 781          * The clock divider is based off the cdclk or PCH rawclk, and would
 782          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 783          * divide by 2000 and use that
 784          */
 785         if (intel_dig_port->port == PORT_A)
 786                 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 787         else
 788                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 789 }
 790
 791 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 792 {
 793         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 794         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 795
 796         if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 797                 /* Workaround for non-ULT HSW */
 798                 switch (index) {
 799                 case 0: return 63;
 800                 case 1: return 72;
 801                 default: return 0;
 802                 }
 803         }
 804
 805         return ilk_get_aux_clock_divider(intel_dp, index);
 806 }
 807
 808 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 809 {
 810         /*
 811          * SKL doesn't need us to program the AUX clock divider (Hardware will
 812          * derive the clock from CDCLK automatically). We still implement the
 813          * get_aux_clock_divider vfunc to plug-in into the existing code.
 814          */
 815         return index ? 0 : 1;
 816 }
 817
 818 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
 819                                      bool has_aux_irq,
 820                                      int send_bytes,
 821                                      uint32_t aux_clock_divider)
 822 {
 823         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 824         struct drm_device *dev = intel_dig_port->base.base.dev;
 825         uint32_t precharge, timeout;
 826
 827         if (IS_GEN6(dev))
 828                 precharge = 3;
 829         else
 830                 precharge = 5;
 831
 832         if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
 833                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 834         else
 835                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 836
 837         return DP_AUX_CH_CTL_SEND_BUSY |
 838                DP_AUX_CH_CTL_DONE |
 839                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 840                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 841                timeout |
 842                DP_AUX_CH_CTL_RECEIVE_ERROR |
 843                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 844                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 845                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 846 }
 847
 848 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 849                                       bool has_aux_irq,
 850                                       int send_bytes,
 851                                       uint32_t unused)
 852 {
 853         return DP_AUX_CH_CTL_SEND_BUSY |
 854                DP_AUX_CH_CTL_DONE |
 855                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 856                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 857                DP_AUX_CH_CTL_TIME_OUT_1600us |
 858                DP_AUX_CH_CTL_RECEIVE_ERROR |
 859                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 860                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
 861                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 862 }
 863
 864 static int
 865 intel_dp_aux_ch(struct intel_dp *intel_dp,
 866                 const uint8_t *send, int send_bytes,
 867                 uint8_t *recv, int recv_size)
 868 {
 869         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 870         struct drm_device *dev = intel_dig_port->base.base.dev;
 871         struct drm_i915_private *dev_priv = to_i915(dev);
 872         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 873         uint32_t aux_clock_divider;
 874         int i, ret, recv_bytes;
 875         uint32_t status;
 876         int try, clock = 0;
 877         bool has_aux_irq = HAS_AUX_IRQ(dev);
 878         bool vdd;
 879
 880         pps_lock(intel_dp);
 881
 882         /*
 883          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 884          * In such cases we want to leave VDD enabled and it's up to upper layers
 885          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 886          * ourselves.
 887          */
 888         vdd = edp_panel_vdd_on(intel_dp);
 889
 890         /* dp aux is extremely sensitive to irq latency, hence request the
 891          * lowest possible wakeup latency and so prevent the cpu from going into
 892          * deep sleep states.
 893          */
 894         pm_qos_update_request(&dev_priv->pm_qos, 0);
 895
 896         intel_dp_check_edp(intel_dp);
 897
 898         /* Try to wait for any previous AUX channel activity */
 899         for (try = 0; try < 3; try++) {
 900                 status = I915_READ_NOTRACE(ch_ctl);
 901                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 902                         break;
 903                 msleep(1);
 904         }
 905
 906         if (try == 3) {
 907                 static u32 last_status = -1;
 908                 const u32 status = I915_READ(ch_ctl);
 909
 910                 if (status != last_status) {
 911                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
 912                              status);
 913                         last_status = status;
 914                 }
 915
 916                 ret = -EBUSY;
 917                 goto out;
 918         }
 919
 920         /* Only 5 data registers! */
 921         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 922                 ret = -E2BIG;
 923                 goto out;
 924         }
 925
 926         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 927                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 928                                                           has_aux_irq,
 929                                                           send_bytes,
 930                                                           aux_clock_divider);
 931
 932                 /* Must try at least 3 times according to DP spec */
 933                 for (try = 0; try < 5; try++) {
 934                         /* Load the send data into the aux channel data registers */
 935                         for (i = 0; i < send_bytes; i += 4)
 936                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
 937                                            intel_dp_pack_aux(send + i,
 938                                                              send_bytes - i));
 939
 940                         /* Send the command and wait for it to complete */
 941                         I915_WRITE(ch_ctl, send_ctl);
 942
 943                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 944
 945                         /* Clear done status and any errors */
 946                         I915_WRITE(ch_ctl,
 947                                    status |
 948                                    DP_AUX_CH_CTL_DONE |
 949                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 950                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 951
 952                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
 953                                 continue;
 954
 955                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
 956                          *   400us delay required for errors and timeouts
 957                          *   Timeout errors from the HW already meet this
 958                          *   requirement so skip to next iteration
 959                          */
 960                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 961                                 usleep_range(400, 500);
 962                                 continue;
 963                         }
 964                         if (status & DP_AUX_CH_CTL_DONE)
 965                                 goto done;
 966                 }
 967         }
 968
 969         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 970                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 971                 ret = -EBUSY;
 972                 goto out;
 973         }
 974
 975 done:
 976         /* Check for timeout or receive error.
 977          * Timeouts occur when the sink is not connected
 978          */
 979         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 980                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 981                 ret = -EIO;
 982                 goto out;
 983         }
 984
 985         /* Timeouts occur when the device isn't connected, so they're
 986          * "normal" -- don't fill the kernel log with these */
 987         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 988                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 989                 ret = -ETIMEDOUT;
 990                 goto out;
 991         }
 992
 993         /* Unload any bytes sent back from the other side */
 994         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 995                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 996
 997         /*
 998          * By BSpec: "Message sizes of 0 or >20 are not allowed."
 999          * We have no idea of what happened so we return -EBUSY so
1000          * drm layer takes care for the necessary retries.
1001          */
1002         if (recv_bytes == 0 || recv_bytes > 20) {
1003                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1004                               recv_bytes);
1005                 /*
1006                  * FIXME: This patch was created on top of a series that
1007                  * organize the retries at drm level. There EBUSY should
1008                  * also take care for 1ms wait before retrying.
1009                  * That aux retries re-org is still needed and after that is
1010                  * merged we remove this sleep from here.
1011                  */
1012                 usleep_range(1000, 1500);
1013                 ret = -EBUSY;
1014                 goto out;
1015         }
1016
1017         if (recv_bytes > recv_size)
1018                 recv_bytes = recv_size;
1019
1020         for (i = 0; i < recv_bytes; i += 4)
1021                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1022                                     recv + i, recv_bytes - i);
1023
1024         ret = recv_bytes;
1025 out:
1026         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1027
1028         if (vdd)
1029                 edp_panel_vdd_off(intel_dp, false);
1030
1031         pps_unlock(intel_dp);
1032
1033         return ret;
1034 }
1035
1036 #define BARE_ADDRESS_SIZE       3
1037 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1038 static ssize_t
1039 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1040 {
1041         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1042         uint8_t txbuf[20], rxbuf[20];
1043         size_t txsize, rxsize;
1044         int ret;
1045
1046         txbuf[0] = (msg->request << 4) |
1047                 ((msg->address >> 16) & 0xf);
1048         txbuf[1] = (msg->address >> 8) & 0xff;
1049         txbuf[2] = msg->address & 0xff;
1050         txbuf[3] = msg->size - 1;
1051
1052         switch (msg->request & ~DP_AUX_I2C_MOT) {
1053         case DP_AUX_NATIVE_WRITE:
1054         case DP_AUX_I2C_WRITE:
1055         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1056                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1057                 rxsize = 2; /* 0 or 1 data bytes */
1058
1059                 if (WARN_ON(txsize > 20))
1060                         return -E2BIG;
1061
1062                 WARN_ON(!msg->buffer != !msg->size);
1063
1064                 if (msg->buffer)
1065                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1066
1067                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1068                 if (ret > 0) {
1069                         msg->reply = rxbuf[0] >> 4;
1070
1071                         if (ret > 1) {
1072                                 /* Number of bytes written in a short write. */
1073                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1074                         } else {
1075                                 /* Return payload size. */
1076                                 ret = msg->size;
1077                         }
1078                 }
1079                 break;
1080
1081         case DP_AUX_NATIVE_READ:
1082         case DP_AUX_I2C_READ:
1083                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1084                 rxsize = msg->size + 1;
1085
1086                 if (WARN_ON(rxsize > 20))
1087                         return -E2BIG;
1088
1089                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1090                 if (ret > 0) {
1091                         msg->reply = rxbuf[0] >> 4;
1092                         /*
1093                          * Assume happy day, and copy the data. The caller is
1094                          * expected to check msg->reply before touching it.
1095                          *
1096                          * Return payload size.
1097                          */
1098                         ret--;
1099                         memcpy(msg->buffer, rxbuf + 1, ret);
1100                 }
1101                 break;
1102
1103         default:
1104                 ret = -EINVAL;
1105                 break;
1106         }
1107
1108         return ret;
1109 }
1110
1111 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1112                                        enum port port)
1113 {
1114         switch (port) {
1115         case PORT_B:
1116         case PORT_C:
1117         case PORT_D:
1118                 return DP_AUX_CH_CTL(port);
1119         default:
1120                 MISSING_CASE(port);
1121                 return DP_AUX_CH_CTL(PORT_B);
1122         }
1123 }
1124
1125 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1126                                         enum port port, int index)
1127 {
1128         switch (port) {
1129         case PORT_B:
1130         case PORT_C:
1131         case PORT_D:
1132                 return DP_AUX_CH_DATA(port, index);
1133         default:
1134                 MISSING_CASE(port);
1135                 return DP_AUX_CH_DATA(PORT_B, index);
1136         }
1137 }
1138
1139 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1140                                        enum port port)
1141 {
1142         switch (port) {
1143         case PORT_A:
1144                 return DP_AUX_CH_CTL(port);
1145         case PORT_B:
1146         case PORT_C:
1147         case PORT_D:
1148                 return PCH_DP_AUX_CH_CTL(port);
1149         default:
1150                 MISSING_CASE(port);
1151                 return DP_AUX_CH_CTL(PORT_A);
1152         }
1153 }
1154
1155 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1156                                         enum port port, int index)
1157 {
1158         switch (port) {
1159         case PORT_A:
1160                 return DP_AUX_CH_DATA(port, index);
1161         case PORT_B:
1162         case PORT_C:
1163         case PORT_D:
1164                 return PCH_DP_AUX_CH_DATA(port, index);
1165         default:
1166                 MISSING_CASE(port);
1167                 return DP_AUX_CH_DATA(PORT_A, index);
1168         }
1169 }
1170
1171 /*
1172  * On SKL we don't have Aux for port E so we rely
1173  * on VBT to set a proper alternate aux channel.
1174  */
1175 static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1176 {
1177         const struct ddi_vbt_port_info *info =
1178                 &dev_priv->vbt.ddi_port_info[PORT_E];
1179
1180         switch (info->alternate_aux_channel) {
1181         case DP_AUX_A:
1182                 return PORT_A;
1183         case DP_AUX_B:
1184                 return PORT_B;
1185         case DP_AUX_C:
1186                 return PORT_C;
1187         case DP_AUX_D:
1188                 return PORT_D;
1189         default:
1190                 MISSING_CASE(info->alternate_aux_channel);
1191                 return PORT_A;
1192         }
1193 }
1194
1195 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1196                                        enum port port)
1197 {
1198         if (port == PORT_E)
1199                 port = skl_porte_aux_port(dev_priv);
1200
1201         switch (port) {
1202         case PORT_A:
1203         case PORT_B:
1204         case PORT_C:
1205         case PORT_D:
1206                 return DP_AUX_CH_CTL(port);
1207         default:
1208                 MISSING_CASE(port);
1209                 return DP_AUX_CH_CTL(PORT_A);
1210         }
1211 }
1212
1213 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1214                                         enum port port, int index)
1215 {
1216         if (port == PORT_E)
1217                 port = skl_porte_aux_port(dev_priv);
1218
1219         switch (port) {
1220         case PORT_A:
1221         case PORT_B:
1222         case PORT_C:
1223         case PORT_D:
1224                 return DP_AUX_CH_DATA(port, index);
1225         default:
1226                 MISSING_CASE(port);
1227                 return DP_AUX_CH_DATA(PORT_A, index);
1228         }
1229 }
1230
1231 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1232                                          enum port port)
1233 {
1234         if (INTEL_INFO(dev_priv)->gen >= 9)
1235                 return skl_aux_ctl_reg(dev_priv, port);
1236         else if (HAS_PCH_SPLIT(dev_priv))
1237                 return ilk_aux_ctl_reg(dev_priv, port);
1238         else
1239                 return g4x_aux_ctl_reg(dev_priv, port);
1240 }
1241
1242 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1243                                           enum port port, int index)
1244 {
1245         if (INTEL_INFO(dev_priv)->gen >= 9)
1246                 return skl_aux_data_reg(dev_priv, port, index);
1247         else if (HAS_PCH_SPLIT(dev_priv))
1248                 return ilk_aux_data_reg(dev_priv, port, index);
1249         else
1250                 return g4x_aux_data_reg(dev_priv, port, index);
1251 }
1252
1253 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1254 {
1255         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1256         enum port port = dp_to_dig_port(intel_dp)->port;
1257         int i;
1258
1259         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1260         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1261                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1262 }
1263
1264 static void
1265 intel_dp_aux_fini(struct intel_dp *intel_dp)
1266 {
1267         kfree(intel_dp->aux.name);
1268 }
1269
1270 static void
1271 intel_dp_aux_init(struct intel_dp *intel_dp)
1272 {
1273         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1274         enum port port = intel_dig_port->port;
1275
1276         intel_aux_reg_init(intel_dp);
1277         drm_dp_aux_init(&intel_dp->aux);
1278
1279         /* Failure to allocate our preferred name is not critical */
1280         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1281         intel_dp->aux.transfer = intel_dp_aux_transfer;
1282 }
1283
1284 static int
1285 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1286 {
1287         if (intel_dp->num_sink_rates) {
1288                 *sink_rates = intel_dp->sink_rates;
1289                 return intel_dp->num_sink_rates;
1290         }
1291
1292         *sink_rates = default_rates;
1293
1294         return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1295 }
1296
1297 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1298 {
1299         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1300         struct drm_device *dev = dig_port->base.base.dev;
1301
1302         /* WaDisableHBR2:skl */
1303         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
1304                 return false;
1305
1306         if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1307             (INTEL_INFO(dev)->gen >= 9))
1308                 return true;
1309         else
1310                 return false;
1311 }
1312
1313 static int
1314 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
1315 {
1316         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1317         struct drm_device *dev = dig_port->base.base.dev;
1318         int size;
1319
1320         if (IS_BROXTON(dev)) {
1321                 *source_rates = bxt_rates;
1322                 size = ARRAY_SIZE(bxt_rates);
1323         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1324                 *source_rates = skl_rates;
1325                 size = ARRAY_SIZE(skl_rates);
1326         } else {
1327                 *source_rates = default_rates;
1328                 size = ARRAY_SIZE(default_rates);
1329         }
1330
1331         /* This depends on the fact that 5.4 is last value in the array */
1332         if (!intel_dp_source_supports_hbr2(intel_dp))
1333                 size--;
1334
1335         return size;
1336 }
1337
1338 static void
1339 intel_dp_set_clock(struct intel_encoder *encoder,
1340                    struct intel_crtc_state *pipe_config)
1341 {
1342         struct drm_device *dev = encoder->base.dev;
1343         const struct dp_link_dpll *divisor = NULL;
1344         int i, count = 0;
1345
1346         if (IS_G4X(dev)) {
1347                 divisor = gen4_dpll;
1348                 count = ARRAY_SIZE(gen4_dpll);
1349         } else if (HAS_PCH_SPLIT(dev)) {
1350                 divisor = pch_dpll;
1351                 count = ARRAY_SIZE(pch_dpll);
1352         } else if (IS_CHERRYVIEW(dev)) {
1353                 divisor = chv_dpll;
1354                 count = ARRAY_SIZE(chv_dpll);
1355         } else if (IS_VALLEYVIEW(dev)) {
1356                 divisor = vlv_dpll;
1357                 count = ARRAY_SIZE(vlv_dpll);
1358         }
1359
1360         if (divisor && count) {
1361                 for (i = 0; i < count; i++) {
1362                         if (pipe_config->port_clock == divisor[i].clock) {
1363                                 pipe_config->dpll = divisor[i].dpll;
1364                                 pipe_config->clock_set = true;
1365                                 break;
1366                         }
1367                 }
1368         }
1369 }
1370
1371 static int intersect_rates(const int *source_rates, int source_len,
1372                            const int *sink_rates, int sink_len,
1373                            int *common_rates)
1374 {
1375         int i = 0, j = 0, k = 0;
1376
1377         while (i < source_len && j < sink_len) {
1378                 if (source_rates[i] == sink_rates[j]) {
1379                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1380                                 return k;
1381                         common_rates[k] = source_rates[i];
1382                         ++k;
1383                         ++i;
1384                         ++j;
1385                 } else if (source_rates[i] < sink_rates[j]) {
1386                         ++i;
1387                 } else {
1388                         ++j;
1389                 }
1390         }
1391         return k;
1392 }
1393
1394 static int intel_dp_common_rates(struct intel_dp *intel_dp,
1395                                  int *common_rates)
1396 {
1397         const int *source_rates, *sink_rates;
1398         int source_len, sink_len;
1399
1400         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1401         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1402
1403         return intersect_rates(source_rates, source_len,
1404                                sink_rates, sink_len,
1405                                common_rates);
1406 }
1407
1408 static void snprintf_int_array(char *str, size_t len,
1409                                const int *array, int nelem)
1410 {
1411         int i;
1412
1413         str[0] = '\0';
1414
1415         for (i = 0; i < nelem; i++) {
1416                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1417                 if (r >= len)
1418                         return;
1419                 str += r;
1420                 len -= r;
1421         }
1422 }
1423
1424 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1425 {
1426         const int *source_rates, *sink_rates;
1427         int source_len, sink_len, common_len;
1428         int common_rates[DP_MAX_SUPPORTED_RATES];
1429         char str[128]; /* FIXME: too big for stack? */
1430
1431         if ((drm_debug & DRM_UT_KMS) == 0)
1432                 return;
1433
1434         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1435         snprintf_int_array(str, sizeof(str), source_rates, source_len);
1436         DRM_DEBUG_KMS("source rates: %s\n", str);
1437
1438         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1439         snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1440         DRM_DEBUG_KMS("sink rates: %s\n", str);
1441
1442         common_len = intel_dp_common_rates(intel_dp, common_rates);
1443         snprintf_int_array(str, sizeof(str), common_rates, common_len);
1444         DRM_DEBUG_KMS("common rates: %s\n", str);
1445 }
1446
1447 static void intel_dp_print_hw_revision(struct intel_dp *intel_dp)
1448 {
1449         uint8_t rev;
1450         int len;
1451
1452         if ((drm_debug & DRM_UT_KMS) == 0)
1453                 return;
1454
1455         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1456               DP_DWN_STRM_PORT_PRESENT))
1457                 return;
1458
1459         len = drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_HW_REV, &rev, 1);
1460         if (len < 0)
1461                 return;
1462
1463         DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev & 0xf0) >> 4, rev & 0xf);
1464 }
1465
1466 static void intel_dp_print_sw_revision(struct intel_dp *intel_dp)
1467 {
1468         uint8_t rev[2];
1469         int len;
1470
1471         if ((drm_debug & DRM_UT_KMS) == 0)
1472                 return;
1473
1474         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1475               DP_DWN_STRM_PORT_PRESENT))
1476                 return;
1477
1478         len = drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_SW_REV, &rev, 2);
1479         if (len < 0)
1480                 return;
1481
1482         DRM_DEBUG_KMS("sink sw revision: %d.%d\n", rev[0], rev[1]);
1483 }
1484
1485 static int rate_to_index(int find, const int *rates)
1486 {
1487         int i = 0;
1488
1489         for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1490                 if (find == rates[i])
1491                         break;
1492
1493         return i;
1494 }
1495
1496 int
1497 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1498 {
1499         int rates[DP_MAX_SUPPORTED_RATES] = {};
1500         int len;
1501
1502         len = intel_dp_common_rates(intel_dp, rates);
1503         if (WARN_ON(len <= 0))
1504                 return 162000;
1505
1506         return rates[len - 1];
1507 }
1508
1509 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1510 {
1511         return rate_to_index(rate, intel_dp->sink_rates);
1512 }
1513
1514 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1515                            uint8_t *link_bw, uint8_t *rate_select)
1516 {
1517         if (intel_dp->num_sink_rates) {
1518                 *link_bw = 0;
1519                 *rate_select =
1520                         intel_dp_rate_select(intel_dp, port_clock);
1521         } else {
1522                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1523                 *rate_select = 0;
1524         }
1525 }
1526
1527 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1528                                 struct intel_crtc_state *pipe_config)
1529 {
1530         int bpp, bpc;
1531
1532         bpp = pipe_config->pipe_bpp;
1533         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1534
1535         if (bpc > 0)
1536                 bpp = min(bpp, 3*bpc);
1537
1538         return bpp;
1539 }
1540
1541 bool
1542 intel_dp_compute_config(struct intel_encoder *encoder,
1543                         struct intel_crtc_state *pipe_config,
1544                         struct drm_connector_state *conn_state)
1545 {
1546         struct drm_device *dev = encoder->base.dev;
1547         struct drm_i915_private *dev_priv = to_i915(dev);
1548         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1549         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1550         enum port port = dp_to_dig_port(intel_dp)->port;
1551         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1552         struct intel_connector *intel_connector = intel_dp->attached_connector;
1553         int lane_count, clock;
1554         int min_lane_count = 1;
1555         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1556         /* Conveniently, the link BW constants become indices with a shift...*/
1557         int min_clock = 0;
1558         int max_clock;
1559         int bpp, mode_rate;
1560         int link_avail, link_clock;
1561         int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1562         int common_len;
1563         uint8_t link_bw, rate_select;
1564
1565         common_len = intel_dp_common_rates(intel_dp, common_rates);
1566
1567         /* No common link rates between source and sink */
1568         WARN_ON(common_len <= 0);
1569
1570         max_clock = common_len - 1;
1571
1572         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1573                 pipe_config->has_pch_encoder = true;
1574
1575         pipe_config->has_drrs = false;
1576         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1577
1578         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1579                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1580                                        adjusted_mode);
1581
1582                 if (INTEL_INFO(dev)->gen >= 9) {
1583                         int ret;
1584                         ret = skl_update_scaler_crtc(pipe_config);
1585                         if (ret)
1586                                 return ret;
1587                 }
1588
1589                 if (HAS_GMCH_DISPLAY(dev))
1590                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1591                                                  intel_connector->panel.fitting_mode);
1592                 else
1593                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1594                                                 intel_connector->panel.fitting_mode);
1595         }
1596
1597         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1598                 return false;
1599
1600         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1601                       "max bw %d pixel clock %iKHz\n",
1602                       max_lane_count, common_rates[max_clock],
1603                       adjusted_mode->crtc_clock);
1604
1605         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1606          * bpc in between. */
1607         bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1608         if (is_edp(intel_dp)) {
1609
1610                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1611                 if (intel_connector->base.display_info.bpc == 0 &&
1612                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1613                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1614                                       dev_priv->vbt.edp.bpp);
1615                         bpp = dev_priv->vbt.edp.bpp;
1616                 }
1617
1618                 /*
1619                  * Use the maximum clock and number of lanes the eDP panel
1620                  * advertizes being capable of. The panels are generally
1621                  * designed to support only a single clock and lane
1622                  * configuration, and typically these values correspond to the
1623                  * native resolution of the panel.
1624                  */
1625                 min_lane_count = max_lane_count;
1626                 min_clock = max_clock;
1627         }
1628
1629         for (; bpp >= 6*3; bpp -= 2*3) {
1630                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1631                                                    bpp);
1632
1633                 for (clock = min_clock; clock <= max_clock; clock++) {
1634                         for (lane_count = min_lane_count;
1635                                 lane_count <= max_lane_count;
1636                                 lane_count <<= 1) {
1637
1638                                 link_clock = common_rates[clock];
1639                                 link_avail = intel_dp_max_data_rate(link_clock,
1640                                                                     lane_count);
1641
1642                                 if (mode_rate <= link_avail) {
1643                                         goto found;
1644                                 }
1645                         }
1646                 }
1647         }
1648
1649         return false;
1650
1651 found:
1652         if (intel_dp->color_range_auto) {
1653                 /*
1654                  * See:
1655                  * CEA-861-E - 5.1 Default Encoding Parameters
1656                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1657                  */
1658                 pipe_config->limited_color_range =
1659                         bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1660         } else {
1661                 pipe_config->limited_color_range =
1662                         intel_dp->limited_color_range;
1663         }
1664
1665         pipe_config->lane_count = lane_count;
1666
1667         pipe_config->pipe_bpp = bpp;
1668         pipe_config->port_clock = common_rates[clock];
1669
1670         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1671                               &link_bw, &rate_select);
1672
1673         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1674                       link_bw, rate_select, pipe_config->lane_count,
1675                       pipe_config->port_clock, bpp);
1676         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1677                       mode_rate, link_avail);
1678
1679         intel_link_compute_m_n(bpp, lane_count,
1680                                adjusted_mode->crtc_clock,
1681                                pipe_config->port_clock,
1682                                &pipe_config->dp_m_n);
1683
1684         if (intel_connector->panel.downclock_mode != NULL &&
1685                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1686                         pipe_config->has_drrs = true;
1687                         intel_link_compute_m_n(bpp, lane_count,
1688                                 intel_connector->panel.downclock_mode->clock,
1689                                 pipe_config->port_clock,
1690                                 &pipe_config->dp_m2_n2);
1691         }
1692
1693         /*
1694          * DPLL0 VCO may need to be adjusted to get the correct
1695          * clock for eDP. This will affect cdclk as well.
1696          */
1697         if (is_edp(intel_dp) &&
1698             (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1699                 int vco;
1700
1701                 switch (pipe_config->port_clock / 2) {
1702                 case 108000:
1703                 case 216000:
1704                         vco = 8640000;
1705                         break;
1706                 default:
1707                         vco = 8100000;
1708                         break;
1709                 }
1710
1711                 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1712         }
1713
1714         if (!HAS_DDI(dev))
1715                 intel_dp_set_clock(encoder, pipe_config);
1716
1717         return true;
1718 }
1719
1720 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1721                               int link_rate, uint8_t lane_count,
1722                               bool link_mst)
1723 {
1724         intel_dp->link_rate = link_rate;
1725         intel_dp->lane_count = lane_count;
1726         intel_dp->link_mst = link_mst;
1727 }
1728
1729 static void intel_dp_prepare(struct intel_encoder *encoder,
1730                              struct intel_crtc_state *pipe_config)
1731 {
1732         struct drm_device *dev = encoder->base.dev;
1733         struct drm_i915_private *dev_priv = to_i915(dev);
1734         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1735         enum port port = dp_to_dig_port(intel_dp)->port;
1736         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1737         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1738
1739         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1740                                  pipe_config->lane_count,
1741                                  intel_crtc_has_type(pipe_config,
1742                                                      INTEL_OUTPUT_DP_MST));
1743
1744         /*
1745          * There are four kinds of DP registers:
1746          *
1747          *      IBX PCH
1748          *      SNB CPU
1749          *      IVB CPU
1750          *      CPT PCH
1751          *
1752          * IBX PCH and CPU are the same for almost everything,
1753          * except that the CPU DP PLL is configured in this
1754          * register
1755          *
1756          * CPT PCH is quite different, having many bits moved
1757          * to the TRANS_DP_CTL register instead. That
1758          * configuration happens (oddly) in ironlake_pch_enable
1759          */
1760
1761         /* Preserve the BIOS-computed detected bit. This is
1762          * supposed to be read-only.
1763          */
1764         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1765
1766         /* Handle DP bits in common between all three register formats */
1767         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1768         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1769
1770         /* Split out the IBX/CPU vs CPT settings */
1771
1772         if (IS_GEN7(dev) && port == PORT_A) {
1773                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1774                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1775                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1776                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1777                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1778
1779                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1780                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1781
1782                 intel_dp->DP |= crtc->pipe << 29;
1783         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1784                 u32 trans_dp;
1785
1786                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1787
1788                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1789                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1790                         trans_dp |= TRANS_DP_ENH_FRAMING;
1791                 else
1792                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1793                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1794         } else {
1795                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1796                     !IS_CHERRYVIEW(dev) && pipe_config->limited_color_range)
1797                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1798
1799                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1800                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1801                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1802                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1803                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1804
1805                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1806                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1807
1808                 if (IS_CHERRYVIEW(dev))
1809                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1810                 else if (crtc->pipe == PIPE_B)
1811                         intel_dp->DP |= DP_PIPEB_SELECT;
1812         }
1813 }
1814
1815 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1816 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1817
1818 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1819 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1820
1821 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1822 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1823
1824 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1825                                    struct intel_dp *intel_dp);
1826
1827 static void wait_panel_status(struct intel_dp *intel_dp,
1828                                        u32 mask,
1829                                        u32 value)
1830 {
1831         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1832         struct drm_i915_private *dev_priv = to_i915(dev);
1833         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1834
1835         lockdep_assert_held(&dev_priv->pps_mutex);
1836
1837         intel_pps_verify_state(dev_priv, intel_dp);
1838
1839         pp_stat_reg = _pp_stat_reg(intel_dp);
1840         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1841
1842         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1843                         mask, value,
1844                         I915_READ(pp_stat_reg),
1845                         I915_READ(pp_ctrl_reg));
1846
1847         if (intel_wait_for_register(dev_priv,
1848                                     pp_stat_reg, mask, value,
1849                                     5000))
1850                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1851                                 I915_READ(pp_stat_reg),
1852                                 I915_READ(pp_ctrl_reg));
1853
1854         DRM_DEBUG_KMS("Wait complete\n");
1855 }
1856
1857 static void wait_panel_on(struct intel_dp *intel_dp)
1858 {
1859         DRM_DEBUG_KMS("Wait for panel power on\n");
1860         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1861 }
1862
1863 static void wait_panel_off(struct intel_dp *intel_dp)
1864 {
1865         DRM_DEBUG_KMS("Wait for panel power off time\n");
1866         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1867 }
1868
1869 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1870 {
1871         ktime_t panel_power_on_time;
1872         s64 panel_power_off_duration;
1873
1874         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1875
1876         /* take the difference of currrent time and panel power off time
1877          * and then make panel wait for t11_t12 if needed. */
1878         panel_power_on_time = ktime_get_boottime();
1879         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1880
1881         /* When we disable the VDD override bit last we have to do the manual
1882          * wait. */
1883         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1884                 wait_remaining_ms_from_jiffies(jiffies,
1885                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1886
1887         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1888 }
1889
1890 static void wait_backlight_on(struct intel_dp *intel_dp)
1891 {
1892         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1893                                        intel_dp->backlight_on_delay);
1894 }
1895
1896 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1897 {
1898         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1899                                        intel_dp->backlight_off_delay);
1900 }
1901
1902 /* Read the current pp_control value, unlocking the register if it
1903  * is locked
1904  */
1905
1906 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1907 {
1908         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1909         struct drm_i915_private *dev_priv = to_i915(dev);
1910         u32 control;
1911
1912         lockdep_assert_held(&dev_priv->pps_mutex);
1913
1914         control = I915_READ(_pp_ctrl_reg(intel_dp));
1915         if (WARN_ON(!HAS_DDI(dev_priv) &&
1916                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
1917                 control &= ~PANEL_UNLOCK_MASK;
1918                 control |= PANEL_UNLOCK_REGS;
1919         }
1920         return control;
1921 }
1922
1923 /*
1924  * Must be paired with edp_panel_vdd_off().
1925  * Must hold pps_mutex around the whole on/off sequence.
1926  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1927  */
1928 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1929 {
1930         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1931         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1932         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1933         struct drm_i915_private *dev_priv = to_i915(dev);
1934         enum intel_display_power_domain power_domain;
1935         u32 pp;
1936         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1937         bool need_to_disable = !intel_dp->want_panel_vdd;
1938
1939         lockdep_assert_held(&dev_priv->pps_mutex);
1940
1941         if (!is_edp(intel_dp))
1942                 return false;
1943
1944         cancel_delayed_work(&intel_dp->panel_vdd_work);
1945         intel_dp->want_panel_vdd = true;
1946
1947         if (edp_have_panel_vdd(intel_dp))
1948                 return need_to_disable;
1949
1950         power_domain = intel_display_port_aux_power_domain(intel_encoder);
1951         intel_display_power_get(dev_priv, power_domain);
1952
1953         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1954                       port_name(intel_dig_port->port));
1955
1956         if (!edp_have_panel_power(intel_dp))
1957                 wait_panel_power_cycle(intel_dp);
1958
1959         pp = ironlake_get_pp_control(intel_dp);
1960         pp |= EDP_FORCE_VDD;
1961
1962         pp_stat_reg = _pp_stat_reg(intel_dp);
1963         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1964
1965         I915_WRITE(pp_ctrl_reg, pp);
1966         POSTING_READ(pp_ctrl_reg);
1967         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1968                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1969         /*
1970          * If the panel wasn't on, delay before accessing aux channel
1971          */
1972         if (!edp_have_panel_power(intel_dp)) {
1973                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1974                               port_name(intel_dig_port->port));
1975                 msleep(intel_dp->panel_power_up_delay);
1976         }
1977
1978         return need_to_disable;
1979 }
1980
1981 /*
1982  * Must be paired with intel_edp_panel_vdd_off() or
1983  * intel_edp_panel_off().
1984  * Nested calls to these functions are not allowed since
1985  * we drop the lock. Caller must use some higher level
1986  * locking to prevent nested calls from other threads.
1987  */
1988 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1989 {
1990         bool vdd;
1991
1992         if (!is_edp(intel_dp))
1993                 return;
1994
1995         pps_lock(intel_dp);
1996         vdd = edp_panel_vdd_on(intel_dp);
1997         pps_unlock(intel_dp);
1998
1999         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2000              port_name(dp_to_dig_port(intel_dp)->port));
2001 }
2002
2003 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2004 {
2005         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2006         struct drm_i915_private *dev_priv = to_i915(dev);
2007         struct intel_digital_port *intel_dig_port =
2008                 dp_to_dig_port(intel_dp);
2009         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2010         enum intel_display_power_domain power_domain;
2011         u32 pp;
2012         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2013
2014         lockdep_assert_held(&dev_priv->pps_mutex);
2015
2016         WARN_ON(intel_dp->want_panel_vdd);
2017
2018         if (!edp_have_panel_vdd(intel_dp))
2019                 return;
2020
2021         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2022                       port_name(intel_dig_port->port));
2023
2024         pp = ironlake_get_pp_control(intel_dp);
2025         pp &= ~EDP_FORCE_VDD;
2026
2027         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2028         pp_stat_reg = _pp_stat_reg(intel_dp);
2029
2030         I915_WRITE(pp_ctrl_reg, pp);
2031         POSTING_READ(pp_ctrl_reg);
2032
2033         /* Make sure sequencer is idle before allowing subsequent activity */
2034         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2035         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2036
2037         if ((pp & PANEL_POWER_ON) == 0)
2038                 intel_dp->panel_power_off_time = ktime_get_boottime();
2039
2040         power_domain = intel_display_port_aux_power_domain(intel_encoder);
2041         intel_display_power_put(dev_priv, power_domain);
2042 }
2043
2044 static void edp_panel_vdd_work(struct work_struct *__work)
2045 {
2046         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2047                                                  struct intel_dp, panel_vdd_work);
2048
2049         pps_lock(intel_dp);
2050         if (!intel_dp->want_panel_vdd)
2051                 edp_panel_vdd_off_sync(intel_dp);
2052         pps_unlock(intel_dp);
2053 }
2054
2055 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2056 {
2057         unsigned long delay;
2058
2059         /*
2060          * Queue the timer to fire a long time from now (relative to the power
2061          * down delay) to keep the panel power up across a sequence of
2062          * operations.
2063          */
2064         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2065         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2066 }
2067
2068 /*
2069  * Must be paired with edp_panel_vdd_on().
2070  * Must hold pps_mutex around the whole on/off sequence.
2071  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2072  */
2073 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2074 {
2075         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2076
2077         lockdep_assert_held(&dev_priv->pps_mutex);
2078
2079         if (!is_edp(intel_dp))
2080                 return;
2081
2082         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2083              port_name(dp_to_dig_port(intel_dp)->port));
2084
2085         intel_dp->want_panel_vdd = false;
2086
2087         if (sync)
2088                 edp_panel_vdd_off_sync(intel_dp);
2089         else
2090                 edp_panel_vdd_schedule_off(intel_dp);
2091 }
2092
2093 static void edp_panel_on(struct intel_dp *intel_dp)
2094 {
2095         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2096         struct drm_i915_private *dev_priv = to_i915(dev);
2097         u32 pp;
2098         i915_reg_t pp_ctrl_reg;
2099
2100         lockdep_assert_held(&dev_priv->pps_mutex);
2101
2102         if (!is_edp(intel_dp))
2103                 return;
2104
2105         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2106                       port_name(dp_to_dig_port(intel_dp)->port));
2107
2108         if (WARN(edp_have_panel_power(intel_dp),
2109                  "eDP port %c panel power already on\n",
2110                  port_name(dp_to_dig_port(intel_dp)->port)))
2111                 return;
2112
2113         wait_panel_power_cycle(intel_dp);
2114
2115         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2116         pp = ironlake_get_pp_control(intel_dp);
2117         if (IS_GEN5(dev)) {
2118                 /* ILK workaround: disable reset around power sequence */
2119                 pp &= ~PANEL_POWER_RESET;
2120                 I915_WRITE(pp_ctrl_reg, pp);
2121                 POSTING_READ(pp_ctrl_reg);
2122         }
2123
2124         pp |= PANEL_POWER_ON;
2125         if (!IS_GEN5(dev))
2126                 pp |= PANEL_POWER_RESET;
2127
2128         I915_WRITE(pp_ctrl_reg, pp);
2129         POSTING_READ(pp_ctrl_reg);
2130
2131         wait_panel_on(intel_dp);
2132         intel_dp->last_power_on = jiffies;
2133
2134         if (IS_GEN5(dev)) {
2135                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2136                 I915_WRITE(pp_ctrl_reg, pp);
2137                 POSTING_READ(pp_ctrl_reg);
2138         }
2139 }
2140
2141 void intel_edp_panel_on(struct intel_dp *intel_dp)
2142 {
2143         if (!is_edp(intel_dp))
2144                 return;
2145
2146         pps_lock(intel_dp);
2147         edp_panel_on(intel_dp);
2148         pps_unlock(intel_dp);
2149 }
2150
2151
2152 static void edp_panel_off(struct intel_dp *intel_dp)
2153 {
2154         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2155         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2156         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2157         struct drm_i915_private *dev_priv = to_i915(dev);
2158         enum intel_display_power_domain power_domain;
2159         u32 pp;
2160         i915_reg_t pp_ctrl_reg;
2161
2162         lockdep_assert_held(&dev_priv->pps_mutex);
2163
2164         if (!is_edp(intel_dp))
2165                 return;
2166
2167         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2168                       port_name(dp_to_dig_port(intel_dp)->port));
2169
2170         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2171              port_name(dp_to_dig_port(intel_dp)->port));
2172
2173         pp = ironlake_get_pp_control(intel_dp);
2174         /* We need to switch off panel power _and_ force vdd, for otherwise some
2175          * panels get very unhappy and cease to work. */
2176         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2177                 EDP_BLC_ENABLE);
2178
2179         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2180
2181         intel_dp->want_panel_vdd = false;
2182
2183         I915_WRITE(pp_ctrl_reg, pp);
2184         POSTING_READ(pp_ctrl_reg);
2185
2186         intel_dp->panel_power_off_time = ktime_get_boottime();
2187         wait_panel_off(intel_dp);
2188
2189         /* We got a reference when we enabled the VDD. */
2190         power_domain = intel_display_port_aux_power_domain(intel_encoder);
2191         intel_display_power_put(dev_priv, power_domain);
2192 }
2193
2194 void intel_edp_panel_off(struct intel_dp *intel_dp)
2195 {
2196         if (!is_edp(intel_dp))
2197                 return;
2198
2199         pps_lock(intel_dp);
2200         edp_panel_off(intel_dp);
2201         pps_unlock(intel_dp);
2202 }
2203
2204 /* Enable backlight in the panel power control. */
2205 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2206 {
2207         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2208         struct drm_device *dev = intel_dig_port->base.base.dev;
2209         struct drm_i915_private *dev_priv = to_i915(dev);
2210         u32 pp;
2211         i915_reg_t pp_ctrl_reg;
2212
2213         /*
2214          * If we enable the backlight right away following a panel power
2215          * on, we may see slight flicker as the panel syncs with the eDP
2216          * link.  So delay a bit to make sure the image is solid before
2217          * allowing it to appear.
2218          */
2219         wait_backlight_on(intel_dp);
2220
2221         pps_lock(intel_dp);
2222
2223         pp = ironlake_get_pp_control(intel_dp);
2224         pp |= EDP_BLC_ENABLE;
2225
2226         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2227
2228         I915_WRITE(pp_ctrl_reg, pp);
2229         POSTING_READ(pp_ctrl_reg);
2230
2231         pps_unlock(intel_dp);
2232 }
2233
2234 /* Enable backlight PWM and backlight PP control. */
2235 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2236 {
2237         if (!is_edp(intel_dp))
2238                 return;
2239
2240         DRM_DEBUG_KMS("\n");
2241
2242         intel_panel_enable_backlight(intel_dp->attached_connector);
2243         _intel_edp_backlight_on(intel_dp);
2244 }
2245
2246 /* Disable backlight in the panel power control. */
2247 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2248 {
2249         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2250         struct drm_i915_private *dev_priv = to_i915(dev);
2251         u32 pp;
2252         i915_reg_t pp_ctrl_reg;
2253
2254         if (!is_edp(intel_dp))
2255                 return;
2256
2257         pps_lock(intel_dp);
2258
2259         pp = ironlake_get_pp_control(intel_dp);
2260         pp &= ~EDP_BLC_ENABLE;
2261
2262         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2263
2264         I915_WRITE(pp_ctrl_reg, pp);
2265         POSTING_READ(pp_ctrl_reg);
2266
2267         pps_unlock(intel_dp);
2268
2269         intel_dp->last_backlight_off = jiffies;
2270         edp_wait_backlight_off(intel_dp);
2271 }
2272
2273 /* Disable backlight PP control and backlight PWM. */
2274 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2275 {
2276         if (!is_edp(intel_dp))
2277                 return;
2278
2279         DRM_DEBUG_KMS("\n");
2280
2281         _intel_edp_backlight_off(intel_dp);
2282         intel_panel_disable_backlight(intel_dp->attached_connector);
2283 }
2284
2285 /*
2286  * Hook for controlling the panel power control backlight through the bl_power
2287  * sysfs attribute. Take care to handle multiple calls.
2288  */
2289 static void intel_edp_backlight_power(struct intel_connector *connector,
2290                                       bool enable)
2291 {
2292         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2293         bool is_enabled;
2294
2295         pps_lock(intel_dp);
2296         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2297         pps_unlock(intel_dp);
2298
2299         if (is_enabled == enable)
2300                 return;
2301
2302         DRM_DEBUG_KMS("panel power control backlight %s\n",
2303                       enable ? "enable" : "disable");
2304
2305         if (enable)
2306                 _intel_edp_backlight_on(intel_dp);
2307         else
2308                 _intel_edp_backlight_off(intel_dp);
2309 }
2310
2311 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2312 {
2313         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2314         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2315         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2316
2317         I915_STATE_WARN(cur_state != state,
2318                         "DP port %c state assertion failure (expected %s, current %s)\n",
2319                         port_name(dig_port->port),
2320                         onoff(state), onoff(cur_state));
2321 }
2322 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2323
2324 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2325 {
2326         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2327
2328         I915_STATE_WARN(cur_state != state,
2329                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2330                         onoff(state), onoff(cur_state));
2331 }
2332 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2333 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2334
2335 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2336                                 struct intel_crtc_state *pipe_config)
2337 {
2338         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2339         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2340
2341         assert_pipe_disabled(dev_priv, crtc->pipe);
2342         assert_dp_port_disabled(intel_dp);
2343         assert_edp_pll_disabled(dev_priv);
2344
2345         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2346                       pipe_config->port_clock);
2347
2348         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2349
2350         if (pipe_config->port_clock == 162000)
2351                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2352         else
2353                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2354
2355         I915_WRITE(DP_A, intel_dp->DP);
2356         POSTING_READ(DP_A);
2357         udelay(500);
2358
2359         /*
2360          * [DevILK] Work around required when enabling DP PLL
2361          * while a pipe is enabled going to FDI:
2362          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2363          * 2. Program DP PLL enable
2364          */
2365         if (IS_GEN5(dev_priv))
2366                 intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe);
2367
2368         intel_dp->DP |= DP_PLL_ENABLE;
2369
2370         I915_WRITE(DP_A, intel_dp->DP);
2371         POSTING_READ(DP_A);
2372         udelay(200);
2373 }
2374
2375 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2376 {
2377         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2378         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2379         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2380
2381         assert_pipe_disabled(dev_priv, crtc->pipe);
2382         assert_dp_port_disabled(intel_dp);
2383         assert_edp_pll_enabled(dev_priv);
2384
2385         DRM_DEBUG_KMS("disabling eDP PLL\n");
2386
2387         intel_dp->DP &= ~DP_PLL_ENABLE;
2388
2389         I915_WRITE(DP_A, intel_dp->DP);
2390         POSTING_READ(DP_A);
2391         udelay(200);
2392 }
2393
2394 /* If the sink supports it, try to set the power state appropriately */
2395 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2396 {
2397         int ret, i;
2398
2399         /* Should have a valid DPCD by this point */
2400         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2401                 return;
2402
2403         if (mode != DRM_MODE_DPMS_ON) {
2404                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2405                                          DP_SET_POWER_D3);
2406         } else {
2407                 /*
2408                  * When turning on, we need to retry for 1ms to give the sink
2409                  * time to wake up.
2410                  */
2411                 for (i = 0; i < 3; i++) {
2412                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2413                                                  DP_SET_POWER_D0);
2414                         if (ret == 1)
2415                                 break;
2416                         msleep(1);
2417                 }
2418         }
2419
2420         if (ret != 1)
2421                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2422                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2423 }
2424
2425 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2426                                   enum pipe *pipe)
2427 {
2428         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2429         enum port port = dp_to_dig_port(intel_dp)->port;
2430         struct drm_device *dev = encoder->base.dev;
2431         struct drm_i915_private *dev_priv = to_i915(dev);
2432         enum intel_display_power_domain power_domain;
2433         u32 tmp;
2434         bool ret;
2435
2436         power_domain = intel_display_port_power_domain(encoder);
2437         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2438                 return false;
2439
2440         ret = false;
2441
2442         tmp = I915_READ(intel_dp->output_reg);
2443
2444         if (!(tmp & DP_PORT_EN))
2445                 goto out;
2446
2447         if (IS_GEN7(dev) && port == PORT_A) {
2448                 *pipe = PORT_TO_PIPE_CPT(tmp);
2449         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2450                 enum pipe p;
2451
2452                 for_each_pipe(dev_priv, p) {
2453                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2454                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2455                                 *pipe = p;
2456                                 ret = true;
2457
2458                                 goto out;
2459                         }
2460                 }
2461
2462                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2463                               i915_mmio_reg_offset(intel_dp->output_reg));
2464         } else if (IS_CHERRYVIEW(dev)) {
2465                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2466         } else {
2467                 *pipe = PORT_TO_PIPE(tmp);
2468         }
2469
2470         ret = true;
2471
2472 out:
2473         intel_display_power_put(dev_priv, power_domain);
2474
2475         return ret;
2476 }
2477
2478 static void intel_dp_get_config(struct intel_encoder *encoder,
2479                                 struct intel_crtc_state *pipe_config)
2480 {
2481         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2482         u32 tmp, flags = 0;
2483         struct drm_device *dev = encoder->base.dev;
2484         struct drm_i915_private *dev_priv = to_i915(dev);
2485         enum port port = dp_to_dig_port(intel_dp)->port;
2486         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2487
2488         tmp = I915_READ(intel_dp->output_reg);
2489
2490         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2491
2492         if (HAS_PCH_CPT(dev) && port != PORT_A) {
2493                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2494
2495                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2496                         flags |= DRM_MODE_FLAG_PHSYNC;
2497                 else
2498                         flags |= DRM_MODE_FLAG_NHSYNC;
2499
2500                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2501                         flags |= DRM_MODE_FLAG_PVSYNC;
2502                 else
2503                         flags |= DRM_MODE_FLAG_NVSYNC;
2504         } else {
2505                 if (tmp & DP_SYNC_HS_HIGH)
2506                         flags |= DRM_MODE_FLAG_PHSYNC;
2507                 else
2508                         flags |= DRM_MODE_FLAG_NHSYNC;
2509
2510                 if (tmp & DP_SYNC_VS_HIGH)
2511                         flags |= DRM_MODE_FLAG_PVSYNC;
2512                 else
2513                         flags |= DRM_MODE_FLAG_NVSYNC;
2514         }
2515
2516         pipe_config->base.adjusted_mode.flags |= flags;
2517
2518         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2519             !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
2520                 pipe_config->limited_color_range = true;
2521
2522         pipe_config->lane_count =
2523                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2524
2525         intel_dp_get_m_n(crtc, pipe_config);
2526
2527         if (port == PORT_A) {
2528                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2529                         pipe_config->port_clock = 162000;
2530                 else
2531                         pipe_config->port_clock = 270000;
2532         }
2533
2534         pipe_config->base.adjusted_mode.crtc_clock =
2535                 intel_dotclock_calculate(pipe_config->port_clock,
2536                                          &pipe_config->dp_m_n);
2537
2538         if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2539             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2540                 /*
2541                  * This is a big fat ugly hack.
2542                  *
2543                  * Some machines in UEFI boot mode provide us a VBT that has 18
2544                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2545                  * unknown we fail to light up. Yet the same BIOS boots up with
2546                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2547                  * max, not what it tells us to use.
2548                  *
2549                  * Note: This will still be broken if the eDP panel is not lit
2550                  * up by the BIOS, and thus we can't get the mode at module
2551                  * load.
2552                  */
2553                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2554                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2555                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2556         }
2557 }
2558
2559 static void intel_disable_dp(struct intel_encoder *encoder,
2560                              struct intel_crtc_state *old_crtc_state,
2561                              struct drm_connector_state *old_conn_state)
2562 {
2563         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2564         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2565
2566         if (old_crtc_state->has_audio)
2567                 intel_audio_codec_disable(encoder);
2568
2569         if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2570                 intel_psr_disable(intel_dp);
2571
2572         /* Make sure the panel is off before trying to change the mode. But also
2573          * ensure that we have vdd while we switch off the panel. */
2574         intel_edp_panel_vdd_on(intel_dp);
2575         intel_edp_backlight_off(intel_dp);
2576         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2577         intel_edp_panel_off(intel_dp);
2578
2579         /* disable the port before the pipe on g4x */
2580         if (INTEL_GEN(dev_priv) < 5)
2581                 intel_dp_link_down(intel_dp);
2582 }
2583
2584 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2585                                 struct intel_crtc_state *old_crtc_state,
2586                                 struct drm_connector_state *old_conn_state)
2587 {
2588         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2589         enum port port = dp_to_dig_port(intel_dp)->port;
2590
2591         intel_dp_link_down(intel_dp);
2592
2593         /* Only ilk+ has port A */
2594         if (port == PORT_A)
2595                 ironlake_edp_pll_off(intel_dp);
2596 }
2597
2598 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2599                                 struct intel_crtc_state *old_crtc_state,
2600                                 struct drm_connector_state *old_conn_state)
2601 {
2602         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2603
2604         intel_dp_link_down(intel_dp);
2605 }
2606
2607 static void chv_post_disable_dp(struct intel_encoder *encoder,
2608                                 struct intel_crtc_state *old_crtc_state,
2609                                 struct drm_connector_state *old_conn_state)
2610 {
2611         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2612         struct drm_device *dev = encoder->base.dev;
2613         struct drm_i915_private *dev_priv = to_i915(dev);
2614
2615         intel_dp_link_down(intel_dp);
2616
2617         mutex_lock(&dev_priv->sb_lock);
2618
2619         /* Assert data lane reset */
2620         chv_data_lane_soft_reset(encoder, true);
2621
2622         mutex_unlock(&dev_priv->sb_lock);
2623 }
2624
2625 static void
2626 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2627                          uint32_t *DP,
2628                          uint8_t dp_train_pat)
2629 {
2630         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2631         struct drm_device *dev = intel_dig_port->base.base.dev;
2632         struct drm_i915_private *dev_priv = to_i915(dev);
2633         enum port port = intel_dig_port->port;
2634
2635         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2636                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2637                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2638
2639         if (HAS_DDI(dev)) {
2640                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2641
2642                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2643                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2644                 else
2645                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2646
2647                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2648                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2649                 case DP_TRAINING_PATTERN_DISABLE:
2650                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2651
2652                         break;
2653                 case DP_TRAINING_PATTERN_1:
2654                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2655                         break;
2656                 case DP_TRAINING_PATTERN_2:
2657                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2658                         break;
2659                 case DP_TRAINING_PATTERN_3:
2660                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2661                         break;
2662                 }
2663                 I915_WRITE(DP_TP_CTL(port), temp);
2664
2665         } else if ((IS_GEN7(dev) && port == PORT_A) ||
2666                    (HAS_PCH_CPT(dev) && port != PORT_A)) {
2667                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2668
2669                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2670                 case DP_TRAINING_PATTERN_DISABLE:
2671                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2672                         break;
2673                 case DP_TRAINING_PATTERN_1:
2674                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2675                         break;
2676                 case DP_TRAINING_PATTERN_2:
2677                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2678                         break;
2679                 case DP_TRAINING_PATTERN_3:
2680                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2681                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2682                         break;
2683                 }
2684
2685         } else {
2686                 if (IS_CHERRYVIEW(dev))
2687                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2688                 else
2689                         *DP &= ~DP_LINK_TRAIN_MASK;
2690
2691                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2692                 case DP_TRAINING_PATTERN_DISABLE:
2693                         *DP |= DP_LINK_TRAIN_OFF;
2694                         break;
2695                 case DP_TRAINING_PATTERN_1:
2696                         *DP |= DP_LINK_TRAIN_PAT_1;
2697                         break;
2698                 case DP_TRAINING_PATTERN_2:
2699                         *DP |= DP_LINK_TRAIN_PAT_2;
2700                         break;
2701                 case DP_TRAINING_PATTERN_3:
2702                         if (IS_CHERRYVIEW(dev)) {
2703                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2704                         } else {
2705                                 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2706                                 *DP |= DP_LINK_TRAIN_PAT_2;
2707                         }
2708                         break;
2709                 }
2710         }
2711 }
2712
2713 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2714                                  struct intel_crtc_state *old_crtc_state)
2715 {
2716         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2717         struct drm_i915_private *dev_priv = to_i915(dev);
2718
2719         /* enable with pattern 1 (as per spec) */
2720
2721         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2722
2723         /*
2724          * Magic for VLV/CHV. We _must_ first set up the register
2725          * without actually enabling the port, and then do another
2726          * write to enable the port. Otherwise link training will
2727          * fail when the power sequencer is freshly used for this port.
2728          */
2729         intel_dp->DP |= DP_PORT_EN;
2730         if (old_crtc_state->has_audio)
2731                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2732
2733         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2734         POSTING_READ(intel_dp->output_reg);
2735 }
2736
2737 static void intel_enable_dp(struct intel_encoder *encoder,
2738                             struct intel_crtc_state *pipe_config)
2739 {
2740         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2741         struct drm_device *dev = encoder->base.dev;
2742         struct drm_i915_private *dev_priv = to_i915(dev);
2743         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2744         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2745         enum pipe pipe = crtc->pipe;
2746
2747         if (WARN_ON(dp_reg & DP_PORT_EN))
2748                 return;
2749
2750         pps_lock(intel_dp);
2751
2752         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2753                 vlv_init_panel_power_sequencer(intel_dp);
2754
2755         intel_dp_enable_port(intel_dp, pipe_config);
2756
2757         edp_panel_vdd_on(intel_dp);
2758         edp_panel_on(intel_dp);
2759         edp_panel_vdd_off(intel_dp, true);
2760
2761         pps_unlock(intel_dp);
2762
2763         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2764                 unsigned int lane_mask = 0x0;
2765
2766                 if (IS_CHERRYVIEW(dev))
2767                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2768
2769                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2770                                     lane_mask);
2771         }
2772
2773         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2774         intel_dp_start_link_train(intel_dp);
2775         intel_dp_stop_link_train(intel_dp);
2776
2777         if (pipe_config->has_audio) {
2778                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2779                                  pipe_name(pipe));
2780                 intel_audio_codec_enable(encoder);
2781         }
2782 }
2783
2784 static void g4x_enable_dp(struct intel_encoder *encoder,
2785                           struct intel_crtc_state *pipe_config,
2786                           struct drm_connector_state *conn_state)
2787 {
2788         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2789
2790         intel_enable_dp(encoder, pipe_config);
2791         intel_edp_backlight_on(intel_dp);
2792 }
2793
2794 static void vlv_enable_dp(struct intel_encoder *encoder,
2795                           struct intel_crtc_state *pipe_config,
2796                           struct drm_connector_state *conn_state)
2797 {
2798         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2799
2800         intel_edp_backlight_on(intel_dp);
2801         intel_psr_enable(intel_dp);
2802 }
2803
2804 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2805                               struct intel_crtc_state *pipe_config,
2806                               struct drm_connector_state *conn_state)
2807 {
2808         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2809         enum port port = dp_to_dig_port(intel_dp)->port;
2810
2811         intel_dp_prepare(encoder, pipe_config);
2812
2813         /* Only ilk+ has port A */
2814         if (port == PORT_A)
2815                 ironlake_edp_pll_on(intel_dp, pipe_config);
2816 }
2817
2818 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2819 {
2820         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2821         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2822         enum pipe pipe = intel_dp->pps_pipe;
2823         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2824
2825         edp_panel_vdd_off_sync(intel_dp);
2826
2827         /*
2828          * VLV seems to get confused when multiple power seqeuencers
2829          * have the same port selected (even if only one has power/vdd
2830          * enabled). The failure manifests as vlv_wait_port_ready() failing
2831          * CHV on the other hand doesn't seem to mind having the same port
2832          * selected in multiple power seqeuencers, but let's clear the
2833          * port select always when logically disconnecting a power sequencer
2834          * from a port.
2835          */
2836         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2837                       pipe_name(pipe), port_name(intel_dig_port->port));
2838         I915_WRITE(pp_on_reg, 0);
2839         POSTING_READ(pp_on_reg);
2840
2841         intel_dp->pps_pipe = INVALID_PIPE;
2842 }
2843
2844 static void vlv_steal_power_sequencer(struct drm_device *dev,
2845                                       enum pipe pipe)
2846 {
2847         struct drm_i915_private *dev_priv = to_i915(dev);
2848         struct intel_encoder *encoder;
2849
2850         lockdep_assert_held(&dev_priv->pps_mutex);
2851
2852         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2853                 return;
2854
2855         for_each_intel_encoder(dev, encoder) {
2856                 struct intel_dp *intel_dp;
2857                 enum port port;
2858
2859                 if (encoder->type != INTEL_OUTPUT_EDP)
2860                         continue;
2861
2862                 intel_dp = enc_to_intel_dp(&encoder->base);
2863                 port = dp_to_dig_port(intel_dp)->port;
2864
2865                 if (intel_dp->pps_pipe != pipe)
2866                         continue;
2867
2868                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2869                               pipe_name(pipe), port_name(port));
2870
2871                 WARN(encoder->base.crtc,
2872                      "stealing pipe %c power sequencer from active eDP port %c\n",
2873                      pipe_name(pipe), port_name(port));
2874
2875                 /* make sure vdd is off before we steal it */
2876                 vlv_detach_power_sequencer(intel_dp);
2877         }
2878 }
2879
2880 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2881 {
2882         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2883         struct intel_encoder *encoder = &intel_dig_port->base;
2884         struct drm_device *dev = encoder->base.dev;
2885         struct drm_i915_private *dev_priv = to_i915(dev);
2886         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2887
2888         lockdep_assert_held(&dev_priv->pps_mutex);
2889
2890         if (!is_edp(intel_dp))
2891                 return;
2892
2893         if (intel_dp->pps_pipe == crtc->pipe)
2894                 return;
2895
2896         /*
2897          * If another power sequencer was being used on this
2898          * port previously make sure to turn off vdd there while
2899          * we still have control of it.
2900          */
2901         if (intel_dp->pps_pipe != INVALID_PIPE)
2902                 vlv_detach_power_sequencer(intel_dp);
2903
2904         /*
2905          * We may be stealing the power
2906          * sequencer from another port.
2907          */
2908         vlv_steal_power_sequencer(dev, crtc->pipe);
2909
2910         /* now it's all ours */
2911         intel_dp->pps_pipe = crtc->pipe;
2912
2913         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2914                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2915
2916         /* init power sequencer on this pipe and port */
2917         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2918         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2919 }
2920
2921 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
2922                               struct intel_crtc_state *pipe_config,
2923                               struct drm_connector_state *conn_state)
2924 {
2925         vlv_phy_pre_encoder_enable(encoder);
2926
2927         intel_enable_dp(encoder, pipe_config);
2928 }
2929
2930 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
2931                                   struct intel_crtc_state *pipe_config,
2932                                   struct drm_connector_state *conn_state)
2933 {
2934         intel_dp_prepare(encoder, pipe_config);
2935
2936         vlv_phy_pre_pll_enable(encoder);
2937 }
2938
2939 static void chv_pre_enable_dp(struct intel_encoder *encoder,
2940                               struct intel_crtc_state *pipe_config,
2941                               struct drm_connector_state *conn_state)
2942 {
2943         chv_phy_pre_encoder_enable(encoder);
2944
2945         intel_enable_dp(encoder, pipe_config);
2946
2947         /* Second common lane will stay alive on its own now */
2948         chv_phy_release_cl2_override(encoder);
2949 }
2950
2951 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
2952                                   struct intel_crtc_state *pipe_config,
2953                                   struct drm_connector_state *conn_state)
2954 {
2955         intel_dp_prepare(encoder, pipe_config);
2956
2957         chv_phy_pre_pll_enable(encoder);
2958 }
2959
2960 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
2961                                     struct intel_crtc_state *pipe_config,
2962                                     struct drm_connector_state *conn_state)
2963 {
2964         chv_phy_post_pll_disable(encoder);
2965 }
2966
2967 /*
2968  * Fetch AUX CH registers 0x202 - 0x207 which contain
2969  * link status information
2970  */
2971 bool
2972 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2973 {
2974         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2975                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2976 }
2977
2978 /* These are source-specific values. */
2979 uint8_t
2980 intel_dp_voltage_max(struct intel_dp *intel_dp)
2981 {
2982         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2983         struct drm_i915_private *dev_priv = to_i915(dev);
2984         enum port port = dp_to_dig_port(intel_dp)->port;
2985
2986         if (IS_BROXTON(dev))
2987                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2988         else if (INTEL_INFO(dev)->gen >= 9) {
2989                 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
2990                         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2991                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2992         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2993                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2994         else if (IS_GEN7(dev) && port == PORT_A)
2995                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2996         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2997                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2998         else
2999                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3000 }
3001
3002 uint8_t
3003 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3004 {
3005         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3006         enum port port = dp_to_dig_port(intel_dp)->port;
3007
3008         if (INTEL_INFO(dev)->gen >= 9) {
3009                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3010                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3011                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3012                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3013                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3014                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3015                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3016                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3017                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3018                 default:
3019                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3020                 }
3021         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3022                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3023                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3024                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3025                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3026                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3027                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3028                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3029                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3030                 default:
3031                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3032                 }
3033         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
3034                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3035                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3036                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3037                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3038                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3039                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3040                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3041                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3042                 default:
3043                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3044                 }
3045         } else if (IS_GEN7(dev) && port == PORT_A) {
3046                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3047                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3048                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3049                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3050                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3051                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3052                 default:
3053                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3054                 }
3055         } else {
3056                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3057                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3058                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3059                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3060                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3061                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3062                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3063                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3064                 default:
3065                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3066                 }
3067         }
3068 }
3069
3070 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3071 {
3072         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3073         unsigned long demph_reg_value, preemph_reg_value,
3074                 uniqtranscale_reg_value;
3075         uint8_t train_set = intel_dp->train_set[0];
3076
3077         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3078         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3079                 preemph_reg_value = 0x0004000;
3080                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3081                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3082                         demph_reg_value = 0x2B405555;
3083                         uniqtranscale_reg_value = 0x552AB83A;
3084                         break;
3085                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3086                         demph_reg_value = 0x2B404040;
3087                         uniqtranscale_reg_value = 0x5548B83A;
3088                         break;
3089                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3090                         demph_reg_value = 0x2B245555;
3091                         uniqtranscale_reg_value = 0x5560B83A;
3092                         break;
3093                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3094                         demph_reg_value = 0x2B405555;
3095                         uniqtranscale_reg_value = 0x5598DA3A;
3096                         break;
3097                 default:
3098                         return 0;
3099                 }
3100                 break;
3101         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3102                 preemph_reg_value = 0x0002000;
3103                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3104                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3105                         demph_reg_value = 0x2B404040;
3106                         uniqtranscale_reg_value = 0x5552B83A;
3107                         break;
3108                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3109                         demph_reg_value = 0x2B404848;
3110                         uniqtranscale_reg_value = 0x5580B83A;
3111                         break;
3112                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3113                         demph_reg_value = 0x2B404040;
3114                         uniqtranscale_reg_value = 0x55ADDA3A;
3115                         break;
3116                 default:
3117                         return 0;
3118                 }
3119                 break;
3120         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3121                 preemph_reg_value = 0x0000000;
3122                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3123                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3124                         demph_reg_value = 0x2B305555;
3125                         uniqtranscale_reg_value = 0x5570B83A;
3126                         break;
3127                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3128                         demph_reg_value = 0x2B2B4040;
3129                         uniqtranscale_reg_value = 0x55ADDA3A;
3130                         break;
3131                 default:
3132                         return 0;
3133                 }
3134                 break;
3135         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3136                 preemph_reg_value = 0x0006000;
3137                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3138                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3139                         demph_reg_value = 0x1B405555;
3140                         uniqtranscale_reg_value = 0x55ADDA3A;
3141                         break;
3142                 default:
3143                         return 0;
3144                 }
3145                 break;
3146         default:
3147                 return 0;
3148         }
3149
3150         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3151                                  uniqtranscale_reg_value, 0);
3152
3153         return 0;
3154 }
3155
3156 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3157 {
3158         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3159         u32 deemph_reg_value, margin_reg_value;
3160         bool uniq_trans_scale = false;
3161         uint8_t train_set = intel_dp->train_set[0];
3162
3163         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3164         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3165                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3166                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3167                         deemph_reg_value = 128;
3168                         margin_reg_value = 52;
3169                         break;
3170                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3171                         deemph_reg_value = 128;
3172                         margin_reg_value = 77;
3173                         break;
3174                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3175                         deemph_reg_value = 128;
3176                         margin_reg_value = 102;
3177                         break;
3178                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3179                         deemph_reg_value = 128;
3180                         margin_reg_value = 154;
3181                         uniq_trans_scale = true;
3182                         break;
3183                 default:
3184                         return 0;
3185                 }
3186                 break;
3187         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3188                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3189                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3190                         deemph_reg_value = 85;
3191                         margin_reg_value = 78;
3192                         break;
3193                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3194                         deemph_reg_value = 85;
3195                         margin_reg_value = 116;
3196                         break;
3197                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3198                         deemph_reg_value = 85;
3199                         margin_reg_value = 154;
3200                         break;
3201                 default:
3202                         return 0;
3203                 }
3204                 break;
3205         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3206                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3207                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3208                         deemph_reg_value = 64;
3209                         margin_reg_value = 104;
3210                         break;
3211                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3212                         deemph_reg_value = 64;
3213                         margin_reg_value = 154;
3214                         break;
3215                 default:
3216                         return 0;
3217                 }
3218                 break;
3219         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3220                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3221                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3222                         deemph_reg_value = 43;
3223                         margin_reg_value = 154;
3224                         break;
3225                 default:
3226                         return 0;
3227                 }
3228                 break;
3229         default:
3230                 return 0;
3231         }
3232
3233         chv_set_phy_signal_level(encoder, deemph_reg_value,
3234                                  margin_reg_value, uniq_trans_scale);
3235
3236         return 0;
3237 }
3238
3239 static uint32_t
3240 gen4_signal_levels(uint8_t train_set)
3241 {
3242         uint32_t        signal_levels = 0;
3243
3244         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3245         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3246         default:
3247                 signal_levels |= DP_VOLTAGE_0_4;
3248                 break;
3249         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3250                 signal_levels |= DP_VOLTAGE_0_6;
3251                 break;
3252         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3253                 signal_levels |= DP_VOLTAGE_0_8;
3254                 break;
3255         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3256                 signal_levels |= DP_VOLTAGE_1_2;
3257                 break;
3258         }
3259         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3260         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3261         default:
3262                 signal_levels |= DP_PRE_EMPHASIS_0;
3263                 break;
3264         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3265                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3266                 break;
3267         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3268                 signal_levels |= DP_PRE_EMPHASIS_6;
3269                 break;
3270         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3271                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3272                 break;
3273         }
3274         return signal_levels;
3275 }
3276
3277 /* Gen6's DP voltage swing and pre-emphasis control */
3278 static uint32_t
3279 gen6_edp_signal_levels(uint8_t train_set)
3280 {
3281         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3282                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3283         switch (signal_levels) {
3284         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3285         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3286                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3287         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3288                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3289         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3290         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3291                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3292         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3293         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3294                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3295         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3296         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3297                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3298         default:
3299                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3300                               "0x%x\n", signal_levels);
3301                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3302         }
3303 }
3304
3305 /* Gen7's DP voltage swing and pre-emphasis control */
3306 static uint32_t
3307 gen7_edp_signal_levels(uint8_t train_set)
3308 {
3309         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3310                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3311         switch (signal_levels) {
3312         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3313                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3314         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3315                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3316         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3317                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3318
3319         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3320                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3321         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3322                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3323
3324         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3325                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3326         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3327                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3328
3329         default:
3330                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3331                               "0x%x\n", signal_levels);
3332                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3333         }
3334 }
3335
3336 void
3337 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3338 {
3339         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3340         enum port port = intel_dig_port->port;
3341         struct drm_device *dev = intel_dig_port->base.base.dev;
3342         struct drm_i915_private *dev_priv = to_i915(dev);
3343         uint32_t signal_levels, mask = 0;
3344         uint8_t train_set = intel_dp->train_set[0];
3345
3346         if (HAS_DDI(dev)) {
3347                 signal_levels = ddi_signal_levels(intel_dp);
3348
3349                 if (IS_BROXTON(dev))
3350                         signal_levels = 0;
3351                 else
3352                         mask = DDI_BUF_EMP_MASK;
3353         } else if (IS_CHERRYVIEW(dev)) {
3354                 signal_levels = chv_signal_levels(intel_dp);
3355         } else if (IS_VALLEYVIEW(dev)) {
3356                 signal_levels = vlv_signal_levels(intel_dp);
3357         } else if (IS_GEN7(dev) && port == PORT_A) {
3358                 signal_levels = gen7_edp_signal_levels(train_set);
3359                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3360         } else if (IS_GEN6(dev) && port == PORT_A) {
3361                 signal_levels = gen6_edp_signal_levels(train_set);
3362                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3363         } else {
3364                 signal_levels = gen4_signal_levels(train_set);
3365                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3366         }
3367
3368         if (mask)
3369                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3370
3371         DRM_DEBUG_KMS("Using vswing level %d\n",
3372                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3373         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3374                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3375                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3376
3377         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3378
3379         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3380         POSTING_READ(intel_dp->output_reg);
3381 }
3382
3383 void
3384 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3385                                        uint8_t dp_train_pat)
3386 {
3387         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3388         struct drm_i915_private *dev_priv =
3389                 to_i915(intel_dig_port->base.base.dev);
3390
3391         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3392
3393         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3394         POSTING_READ(intel_dp->output_reg);
3395 }
3396
3397 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3398 {
3399         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3400         struct drm_device *dev = intel_dig_port->base.base.dev;
3401         struct drm_i915_private *dev_priv = to_i915(dev);
3402         enum port port = intel_dig_port->port;
3403         uint32_t val;
3404
3405         if (!HAS_DDI(dev))
3406                 return;
3407
3408         val = I915_READ(DP_TP_CTL(port));
3409         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3410         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3411         I915_WRITE(DP_TP_CTL(port), val);
3412
3413         /*
3414          * On PORT_A we can have only eDP in SST mode. There the only reason
3415          * we need to set idle transmission mode is to work around a HW issue
3416          * where we enable the pipe while not in idle link-training mode.
3417          * In this case there is requirement to wait for a minimum number of
3418          * idle patterns to be sent.
3419          */
3420         if (port == PORT_A)
3421                 return;
3422
3423         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3424                                     DP_TP_STATUS_IDLE_DONE,
3425                                     DP_TP_STATUS_IDLE_DONE,
3426                                     1))
3427                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3428 }
3429
3430 static void
3431 intel_dp_link_down(struct intel_dp *intel_dp)
3432 {
3433         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3434         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3435         enum port port = intel_dig_port->port;
3436         struct drm_device *dev = intel_dig_port->base.base.dev;
3437         struct drm_i915_private *dev_priv = to_i915(dev);
3438         uint32_t DP = intel_dp->DP;
3439
3440         if (WARN_ON(HAS_DDI(dev)))
3441                 return;
3442
3443         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3444                 return;
3445
3446         DRM_DEBUG_KMS("\n");
3447
3448         if ((IS_GEN7(dev) && port == PORT_A) ||
3449             (HAS_PCH_CPT(dev) && port != PORT_A)) {
3450                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3451                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3452         } else {
3453                 if (IS_CHERRYVIEW(dev))
3454                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3455                 else
3456                         DP &= ~DP_LINK_TRAIN_MASK;
3457                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3458         }
3459         I915_WRITE(intel_dp->output_reg, DP);
3460         POSTING_READ(intel_dp->output_reg);
3461
3462         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3463         I915_WRITE(intel_dp->output_reg, DP);
3464         POSTING_READ(intel_dp->output_reg);
3465
3466         /*
3467          * HW workaround for IBX, we need to move the port
3468          * to transcoder A after disabling it to allow the
3469          * matching HDMI port to be enabled on transcoder A.
3470          */
3471         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3472                 /*
3473                  * We get CPU/PCH FIFO underruns on the other pipe when
3474                  * doing the workaround. Sweep them under the rug.
3475                  */
3476                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3477                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3478
3479                 /* always enable with pattern 1 (as per spec) */
3480                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3481                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3482                 I915_WRITE(intel_dp->output_reg, DP);
3483                 POSTING_READ(intel_dp->output_reg);
3484
3485                 DP &= ~DP_PORT_EN;
3486                 I915_WRITE(intel_dp->output_reg, DP);
3487                 POSTING_READ(intel_dp->output_reg);
3488
3489                 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
3490                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3491                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3492         }
3493
3494         msleep(intel_dp->panel_power_down_delay);
3495
3496         intel_dp->DP = DP;
3497 }
3498
3499 static bool
3500 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3501 {
3502         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3503                              sizeof(intel_dp->dpcd)) < 0)
3504                 return false; /* aux transfer failed */
3505
3506         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3507
3508         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3509 }
3510
3511 static bool
3512 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3513 {
3514         struct drm_i915_private *dev_priv =
3515                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3516
3517         /* this function is meant to be called only once */
3518         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3519
3520         if (!intel_dp_read_dpcd(intel_dp))
3521                 return false;
3522
3523         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3524                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3525                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3526
3527         /* Check if the panel supports PSR */
3528         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3529                          intel_dp->psr_dpcd,
3530                          sizeof(intel_dp->psr_dpcd));
3531         if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3532                 dev_priv->psr.sink_support = true;
3533                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3534         }
3535
3536         if (INTEL_GEN(dev_priv) >= 9 &&
3537             (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3538                 uint8_t frame_sync_cap;
3539
3540                 dev_priv->psr.sink_support = true;
3541                 drm_dp_dpcd_read(&intel_dp->aux,
3542                                  DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3543                                  &frame_sync_cap, 1);
3544                 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3545                 /* PSR2 needs frame sync as well */
3546                 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3547                 DRM_DEBUG_KMS("PSR2 %s on sink",
3548                               dev_priv->psr.psr2_support ? "supported" : "not supported");
3549         }
3550
3551         /* Read the eDP Display control capabilities registers */
3552         if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3553             drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3554                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd) ==
3555                              sizeof(intel_dp->edp_dpcd)))
3556                 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3557                               intel_dp->edp_dpcd);
3558
3559         /* Intermediate frequency support */
3560         if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3561                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3562                 int i;
3563
3564                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3565                                 sink_rates, sizeof(sink_rates));
3566
3567                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3568                         int val = le16_to_cpu(sink_rates[i]);
3569
3570                         if (val == 0)
3571                                 break;
3572
3573                         /* Value read is in kHz while drm clock is saved in deca-kHz */
3574                         intel_dp->sink_rates[i] = (val * 200) / 10;
3575                 }
3576                 intel_dp->num_sink_rates = i;
3577         }
3578
3579         return true;
3580 }
3581
3582
3583 static bool
3584 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3585 {
3586         if (!intel_dp_read_dpcd(intel_dp))
3587                 return false;
3588
3589         if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3590                              &intel_dp->sink_count, 1) < 0)
3591                 return false;
3592
3593         /*
3594          * Sink count can change between short pulse hpd hence
3595          * a member variable in intel_dp will track any changes
3596          * between short pulse interrupts.
3597          */
3598         intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3599
3600         /*
3601          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3602          * a dongle is present but no display. Unless we require to know
3603          * if a dongle is present or not, we don't need to update
3604          * downstream port information. So, an early return here saves
3605          * time from performing other operations which are not required.
3606          */
3607         if (!is_edp(intel_dp) && !intel_dp->sink_count)
3608                 return false;
3609
3610         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3611               DP_DWN_STRM_PORT_PRESENT))
3612                 return true; /* native DP sink */
3613
3614         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3615                 return true; /* no per-port downstream info */
3616
3617         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3618                              intel_dp->downstream_ports,
3619                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3620                 return false; /* downstream port status fetch failed */
3621
3622         return true;
3623 }
3624
3625 static void
3626 intel_dp_probe_oui(struct intel_dp *intel_dp)
3627 {
3628         u8 buf[3];
3629
3630         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3631                 return;
3632
3633         if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3634                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3635                               buf[0], buf[1], buf[2]);
3636
3637         if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3638                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3639                               buf[0], buf[1], buf[2]);
3640 }
3641
3642 static bool
3643 intel_dp_can_mst(struct intel_dp *intel_dp)
3644 {
3645         u8 buf[1];
3646
3647         if (!i915.enable_dp_mst)
3648                 return false;
3649
3650         if (!intel_dp->can_mst)
3651                 return false;
3652
3653         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3654                 return false;
3655
3656         if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3657                 return false;
3658
3659         return buf[0] & DP_MST_CAP;
3660 }
3661
3662 static void
3663 intel_dp_configure_mst(struct intel_dp *intel_dp)
3664 {
3665         if (!i915.enable_dp_mst)
3666                 return;
3667
3668         if (!intel_dp->can_mst)
3669                 return;
3670
3671         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3672
3673         if (intel_dp->is_mst)
3674                 DRM_DEBUG_KMS("Sink is MST capable\n");
3675         else
3676                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3677
3678         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3679                                         intel_dp->is_mst);
3680 }
3681
3682 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3683 {
3684         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3685         struct drm_device *dev = dig_port->base.base.dev;
3686         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3687         u8 buf;
3688         int ret = 0;
3689         int count = 0;
3690         int attempts = 10;
3691
3692         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3693                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3694                 ret = -EIO;
3695                 goto out;
3696         }
3697
3698         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3699                                buf & ~DP_TEST_SINK_START) < 0) {
3700                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3701                 ret = -EIO;
3702                 goto out;
3703         }
3704
3705         do {
3706                 intel_wait_for_vblank(dev, intel_crtc->pipe);
3707
3708                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3709                                       DP_TEST_SINK_MISC, &buf) < 0) {
3710                         ret = -EIO;
3711                         goto out;
3712                 }
3713                 count = buf & DP_TEST_COUNT_MASK;
3714         } while (--attempts && count);
3715
3716         if (attempts == 0) {
3717                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3718                 ret = -ETIMEDOUT;
3719         }
3720
3721  out:
3722         hsw_enable_ips(intel_crtc);
3723         return ret;
3724 }
3725
3726 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3727 {
3728         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3729         struct drm_device *dev = dig_port->base.base.dev;
3730         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3731         u8 buf;
3732         int ret;
3733
3734         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3735                 return -EIO;
3736
3737         if (!(buf & DP_TEST_CRC_SUPPORTED))
3738                 return -ENOTTY;
3739
3740         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3741                 return -EIO;
3742
3743         if (buf & DP_TEST_SINK_START) {
3744                 ret = intel_dp_sink_crc_stop(intel_dp);
3745                 if (ret)
3746                         return ret;
3747         }
3748
3749         hsw_disable_ips(intel_crtc);
3750
3751         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3752                                buf | DP_TEST_SINK_START) < 0) {
3753                 hsw_enable_ips(intel_crtc);
3754                 return -EIO;
3755         }
3756
3757         intel_wait_for_vblank(dev, intel_crtc->pipe);
3758         return 0;
3759 }
3760
3761 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3762 {
3763         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3764         struct drm_device *dev = dig_port->base.base.dev;
3765         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3766         u8 buf;
3767         int count, ret;
3768         int attempts = 6;
3769
3770         ret = intel_dp_sink_crc_start(intel_dp);
3771         if (ret)
3772                 return ret;
3773
3774         do {
3775                 intel_wait_for_vblank(dev, intel_crtc->pipe);
3776
3777                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3778                                       DP_TEST_SINK_MISC, &buf) < 0) {
3779                         ret = -EIO;
3780                         goto stop;
3781                 }
3782                 count = buf & DP_TEST_COUNT_MASK;
3783
3784         } while (--attempts && count == 0);
3785
3786         if (attempts == 0) {
3787                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3788                 ret = -ETIMEDOUT;
3789                 goto stop;
3790         }
3791
3792         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3793                 ret = -EIO;
3794                 goto stop;
3795         }
3796
3797 stop:
3798         intel_dp_sink_crc_stop(intel_dp);
3799         return ret;
3800 }
3801
3802 static bool
3803 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3804 {
3805         return drm_dp_dpcd_read(&intel_dp->aux,
3806                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3807                                        sink_irq_vector, 1) == 1;
3808 }
3809
3810 static bool
3811 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3812 {
3813         int ret;
3814
3815         ret = drm_dp_dpcd_read(&intel_dp->aux,
3816                                              DP_SINK_COUNT_ESI,
3817                                              sink_irq_vector, 14);
3818         if (ret != 14)
3819                 return false;
3820
3821         return true;
3822 }
3823
3824 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3825 {
3826         uint8_t test_result = DP_TEST_ACK;
3827         return test_result;
3828 }
3829
3830 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3831 {
3832         uint8_t test_result = DP_TEST_NAK;
3833         return test_result;
3834 }
3835
3836 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
3837 {
3838         uint8_t test_result = DP_TEST_NAK;
3839         struct intel_connector *intel_connector = intel_dp->attached_connector;
3840         struct drm_connector *connector = &intel_connector->base;
3841
3842         if (intel_connector->detect_edid == NULL ||
3843             connector->edid_corrupt ||
3844             intel_dp->aux.i2c_defer_count > 6) {
3845                 /* Check EDID read for NACKs, DEFERs and corruption
3846                  * (DP CTS 1.2 Core r1.1)
3847                  *    4.2.2.4 : Failed EDID read, I2C_NAK
3848                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
3849                  *    4.2.2.6 : EDID corruption detected
3850                  * Use failsafe mode for all cases
3851                  */
3852                 if (intel_dp->aux.i2c_nack_count > 0 ||
3853                         intel_dp->aux.i2c_defer_count > 0)
3854                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3855                                       intel_dp->aux.i2c_nack_count,
3856                                       intel_dp->aux.i2c_defer_count);
3857                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3858         } else {
3859                 struct edid *block = intel_connector->detect_edid;
3860
3861                 /* We have to write the checksum
3862                  * of the last block read
3863                  */
3864                 block += intel_connector->detect_edid->extensions;
3865
3866                 if (!drm_dp_dpcd_write(&intel_dp->aux,
3867                                         DP_TEST_EDID_CHECKSUM,
3868                                         &block->checksum,
3869                                         1))
3870                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3871
3872                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3873                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3874         }
3875
3876         /* Set test active flag here so userspace doesn't interrupt things */
3877         intel_dp->compliance_test_active = 1;
3878
3879         return test_result;
3880 }
3881
3882 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3883 {
3884         uint8_t test_result = DP_TEST_NAK;
3885         return test_result;
3886 }
3887
3888 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3889 {
3890         uint8_t response = DP_TEST_NAK;
3891         uint8_t rxdata = 0;
3892         int status = 0;
3893
3894         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3895         if (status <= 0) {
3896                 DRM_DEBUG_KMS("Could not read test request from sink\n");
3897                 goto update_status;
3898         }
3899
3900         switch (rxdata) {
3901         case DP_TEST_LINK_TRAINING:
3902                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3903                 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3904                 response = intel_dp_autotest_link_training(intel_dp);
3905                 break;
3906         case DP_TEST_LINK_VIDEO_PATTERN:
3907                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3908                 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3909                 response = intel_dp_autotest_video_pattern(intel_dp);
3910                 break;
3911         case DP_TEST_LINK_EDID_READ:
3912                 DRM_DEBUG_KMS("EDID test requested\n");
3913                 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3914                 response = intel_dp_autotest_edid(intel_dp);
3915                 break;
3916         case DP_TEST_LINK_PHY_TEST_PATTERN:
3917                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3918                 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3919                 response = intel_dp_autotest_phy_pattern(intel_dp);
3920                 break;
3921         default:
3922                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3923                 break;
3924         }
3925
3926 update_status:
3927         status = drm_dp_dpcd_write(&intel_dp->aux,
3928                                    DP_TEST_RESPONSE,
3929                                    &response, 1);
3930         if (status <= 0)
3931                 DRM_DEBUG_KMS("Could not write test response to sink\n");
3932 }
3933
3934 static int
3935 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3936 {
3937         bool bret;
3938
3939         if (intel_dp->is_mst) {
3940                 u8 esi[16] = { 0 };
3941                 int ret = 0;
3942                 int retry;
3943                 bool handled;
3944                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3945 go_again:
3946                 if (bret == true) {
3947
3948                         /* check link status - esi[10] = 0x200c */
3949                         if (intel_dp->active_mst_links &&
3950                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3951                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3952                                 intel_dp_start_link_train(intel_dp);
3953                                 intel_dp_stop_link_train(intel_dp);
3954                         }
3955
3956                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
3957                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3958
3959                         if (handled) {
3960                                 for (retry = 0; retry < 3; retry++) {
3961                                         int wret;
3962                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
3963                                                                  DP_SINK_COUNT_ESI+1,
3964                                                                  &esi[1], 3);
3965                                         if (wret == 3) {
3966                                                 break;
3967                                         }
3968                                 }
3969
3970                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3971                                 if (bret == true) {
3972                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
3973                                         goto go_again;
3974                                 }
3975                         } else
3976                                 ret = 0;
3977
3978                         return ret;
3979                 } else {
3980                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3981                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3982                         intel_dp->is_mst = false;
3983                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3984                         /* send a hotplug event */
3985                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3986                 }
3987         }
3988         return -EINVAL;
3989 }
3990
3991 static void
3992 intel_dp_check_link_status(struct intel_dp *intel_dp)
3993 {
3994         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3995         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3996         u8 link_status[DP_LINK_STATUS_SIZE];
3997
3998         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3999
4000         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4001                 DRM_ERROR("Failed to get link status\n");
4002                 return;
4003         }
4004
4005         if (!intel_encoder->base.crtc)
4006                 return;
4007
4008         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4009                 return;
4010
4011         /* if link training is requested we should perform it always */
4012         if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4013             (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4014                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4015                               intel_encoder->base.name);
4016                 intel_dp_start_link_train(intel_dp);
4017                 intel_dp_stop_link_train(intel_dp);
4018         }
4019 }
4020
4021 /*
4022  * According to DP spec
4023  * 5.1.2:
4024  *  1. Read DPCD
4025  *  2. Configure link according to Receiver Capabilities
4026  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4027  *  4. Check link status on receipt of hot-plug interrupt
4028  *
4029  * intel_dp_short_pulse -  handles short pulse interrupts
4030  * when full detection is not required.
4031  * Returns %true if short pulse is handled and full detection
4032  * is NOT required and %false otherwise.
4033  */
4034 static bool
4035 intel_dp_short_pulse(struct intel_dp *intel_dp)
4036 {
4037         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4038         u8 sink_irq_vector = 0;
4039         u8 old_sink_count = intel_dp->sink_count;
4040         bool ret;
4041
4042         /*
4043          * Clearing compliance test variables to allow capturing
4044          * of values for next automated test request.
4045          */
4046         intel_dp->compliance_test_active = 0;
4047         intel_dp->compliance_test_type = 0;
4048         intel_dp->compliance_test_data = 0;
4049
4050         /*
4051          * Now read the DPCD to see if it's actually running
4052          * If the current value of sink count doesn't match with
4053          * the value that was stored earlier or dpcd read failed
4054          * we need to do full detection
4055          */
4056         ret = intel_dp_get_dpcd(intel_dp);
4057
4058         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4059                 /* No need to proceed if we are going to do full detect */
4060                 return false;
4061         }
4062
4063         /* Try to read the source of the interrupt */
4064         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4065             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4066             sink_irq_vector != 0) {
4067                 /* Clear interrupt source */
4068                 drm_dp_dpcd_writeb(&intel_dp->aux,
4069                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4070                                    sink_irq_vector);
4071
4072                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4073                         DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4074                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4075                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4076         }
4077
4078         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4079         intel_dp_check_link_status(intel_dp);
4080         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4081
4082         return true;
4083 }
4084
4085 /* XXX this is probably wrong for multiple downstream ports */
4086 static enum drm_connector_status
4087 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4088 {
4089         uint8_t *dpcd = intel_dp->dpcd;
4090         uint8_t type;
4091
4092         if (!intel_dp_get_dpcd(intel_dp))
4093                 return connector_status_disconnected;
4094
4095         if (is_edp(intel_dp))
4096                 return connector_status_connected;
4097
4098         /* if there's no downstream port, we're done */
4099         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4100                 return connector_status_connected;
4101
4102         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4103         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4104             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4105
4106                 return intel_dp->sink_count ?
4107                 connector_status_connected : connector_status_disconnected;
4108         }
4109
4110         if (intel_dp_can_mst(intel_dp))
4111                 return connector_status_connected;
4112
4113         /* If no HPD, poke DDC gently */
4114         if (drm_probe_ddc(&intel_dp->aux.ddc))
4115                 return connector_status_connected;
4116
4117         /* Well we tried, say unknown for unreliable port types */
4118         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4119                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4120                 if (type == DP_DS_PORT_TYPE_VGA ||
4121                     type == DP_DS_PORT_TYPE_NON_EDID)
4122                         return connector_status_unknown;
4123         } else {
4124                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4125                         DP_DWN_STRM_PORT_TYPE_MASK;
4126                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4127                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4128                         return connector_status_unknown;
4129         }
4130
4131         /* Anything else is out of spec, warn and ignore */
4132         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4133         return connector_status_disconnected;
4134 }
4135
4136 static enum drm_connector_status
4137 edp_detect(struct intel_dp *intel_dp)
4138 {
4139         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4140         enum drm_connector_status status;
4141
4142         status = intel_panel_detect(dev);
4143         if (status == connector_status_unknown)
4144                 status = connector_status_connected;
4145
4146         return status;
4147 }
4148
4149 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4150                                        struct intel_digital_port *port)
4151 {
4152         u32 bit;
4153
4154         switch (port->port) {
4155         case PORT_A:
4156                 return true;
4157         case PORT_B:
4158                 bit = SDE_PORTB_HOTPLUG;
4159                 break;
4160         case PORT_C:
4161                 bit = SDE_PORTC_HOTPLUG;
4162                 break;
4163         case PORT_D:
4164                 bit = SDE_PORTD_HOTPLUG;
4165                 break;
4166         default:
4167                 MISSING_CASE(port->port);
4168                 return false;
4169         }
4170
4171         return I915_READ(SDEISR) & bit;
4172 }
4173
4174 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4175                                        struct intel_digital_port *port)
4176 {
4177         u32 bit;
4178
4179         switch (port->port) {
4180         case PORT_A:
4181                 return true;
4182         case PORT_B:
4183                 bit = SDE_PORTB_HOTPLUG_CPT;
4184                 break;
4185         case PORT_C:
4186                 bit = SDE_PORTC_HOTPLUG_CPT;
4187                 break;
4188         case PORT_D:
4189                 bit = SDE_PORTD_HOTPLUG_CPT;
4190                 break;
4191         case PORT_E:
4192                 bit = SDE_PORTE_HOTPLUG_SPT;
4193                 break;
4194         default:
4195                 MISSING_CASE(port->port);
4196                 return false;
4197         }
4198
4199         return I915_READ(SDEISR) & bit;
4200 }
4201
4202 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4203                                        struct intel_digital_port *port)
4204 {
4205         u32 bit;
4206
4207         switch (port->port) {
4208         case PORT_B:
4209                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4210                 break;
4211         case PORT_C:
4212                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4213                 break;
4214         case PORT_D:
4215                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4216                 break;
4217         default:
4218                 MISSING_CASE(port->port);
4219                 return false;
4220         }
4221
4222         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4223 }
4224
4225 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4226                                         struct intel_digital_port *port)
4227 {
4228         u32 bit;
4229
4230         switch (port->port) {
4231         case PORT_B:
4232                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4233                 break;
4234         case PORT_C:
4235                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4236                 break;
4237         case PORT_D:
4238                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4239                 break;
4240         default:
4241                 MISSING_CASE(port->port);
4242                 return false;
4243         }
4244
4245         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4246 }
4247
4248 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4249                                        struct intel_digital_port *intel_dig_port)
4250 {
4251         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4252         enum port port;
4253         u32 bit;
4254
4255         intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4256         switch (port) {
4257         case PORT_A:
4258                 bit = BXT_DE_PORT_HP_DDIA;
4259                 break;
4260         case PORT_B:
4261                 bit = BXT_DE_PORT_HP_DDIB;
4262                 break;
4263         case PORT_C:
4264                 bit = BXT_DE_PORT_HP_DDIC;
4265                 break;
4266         default:
4267                 MISSING_CASE(port);
4268                 return false;
4269         }
4270
4271         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4272 }
4273
4274 /*
4275  * intel_digital_port_connected - is the specified port connected?
4276  * @dev_priv: i915 private structure
4277  * @port: the port to test
4278  *
4279  * Return %true if @port is connected, %false otherwise.
4280  */
4281 static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4282                                          struct intel_digital_port *port)
4283 {
4284         if (HAS_PCH_IBX(dev_priv))
4285                 return ibx_digital_port_connected(dev_priv, port);
4286         else if (HAS_PCH_SPLIT(dev_priv))
4287                 return cpt_digital_port_connected(dev_priv, port);
4288         else if (IS_BROXTON(dev_priv))
4289                 return bxt_digital_port_connected(dev_priv, port);
4290         else if (IS_GM45(dev_priv))
4291                 return gm45_digital_port_connected(dev_priv, port);
4292         else
4293                 return g4x_digital_port_connected(dev_priv, port);
4294 }
4295
4296 static struct edid *
4297 intel_dp_get_edid(struct intel_dp *intel_dp)
4298 {
4299         struct intel_connector *intel_connector = intel_dp->attached_connector;
4300
4301         /* use cached edid if we have one */
4302         if (intel_connector->edid) {
4303                 /* invalid edid */
4304                 if (IS_ERR(intel_connector->edid))
4305                         return NULL;
4306
4307                 return drm_edid_duplicate(intel_connector->edid);
4308         } else
4309                 return drm_get_edid(&intel_connector->base,
4310                                     &intel_dp->aux.ddc);
4311 }
4312
4313 static void
4314 intel_dp_set_edid(struct intel_dp *intel_dp)
4315 {
4316         struct intel_connector *intel_connector = intel_dp->attached_connector;
4317         struct edid *edid;
4318
4319         intel_dp_unset_edid(intel_dp);
4320         edid = intel_dp_get_edid(intel_dp);
4321         intel_connector->detect_edid = edid;
4322
4323         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4324                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4325         else
4326                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4327 }
4328
4329 static void
4330 intel_dp_unset_edid(struct intel_dp *intel_dp)
4331 {
4332         struct intel_connector *intel_connector = intel_dp->attached_connector;
4333
4334         kfree(intel_connector->detect_edid);
4335         intel_connector->detect_edid = NULL;
4336
4337         intel_dp->has_audio = false;
4338 }
4339
4340 static void
4341 intel_dp_long_pulse(struct intel_connector *intel_connector)
4342 {
4343         struct drm_connector *connector = &intel_connector->base;
4344         struct intel_dp *intel_dp = intel_attached_dp(connector);
4345         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4346         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4347         struct drm_device *dev = connector->dev;
4348         enum drm_connector_status status;
4349         enum intel_display_power_domain power_domain;
4350         u8 sink_irq_vector = 0;
4351
4352         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4353         intel_display_power_get(to_i915(dev), power_domain);
4354
4355         /* Can't disconnect eDP, but you can close the lid... */
4356         if (is_edp(intel_dp))
4357                 status = edp_detect(intel_dp);
4358         else if (intel_digital_port_connected(to_i915(dev),
4359                                               dp_to_dig_port(intel_dp)))
4360                 status = intel_dp_detect_dpcd(intel_dp);
4361         else
4362                 status = connector_status_disconnected;
4363
4364         if (status != connector_status_connected) {
4365                 intel_dp->compliance_test_active = 0;
4366                 intel_dp->compliance_test_type = 0;
4367                 intel_dp->compliance_test_data = 0;
4368
4369                 if (intel_dp->is_mst) {
4370                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4371                                       intel_dp->is_mst,
4372                                       intel_dp->mst_mgr.mst_state);
4373                         intel_dp->is_mst = false;
4374                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4375                                                         intel_dp->is_mst);
4376                 }
4377
4378                 goto out;
4379         }
4380
4381         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4382                 intel_encoder->type = INTEL_OUTPUT_DP;
4383
4384         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4385                       yesno(intel_dp_source_supports_hbr2(intel_dp)),
4386                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4387
4388         intel_dp_print_rates(intel_dp);
4389
4390         intel_dp_probe_oui(intel_dp);
4391
4392         intel_dp_print_hw_revision(intel_dp);
4393         intel_dp_print_sw_revision(intel_dp);
4394
4395         intel_dp_configure_mst(intel_dp);
4396
4397         if (intel_dp->is_mst) {
4398                 /*
4399                  * If we are in MST mode then this connector
4400                  * won't appear connected or have anything
4401                  * with EDID on it
4402                  */
4403                 status = connector_status_disconnected;
4404                 goto out;
4405         } else if (connector->status == connector_status_connected) {
4406                 /*
4407                  * If display was connected already and is still connected
4408                  * check links status, there has been known issues of
4409                  * link loss triggerring long pulse!!!!
4410                  */
4411                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4412                 intel_dp_check_link_status(intel_dp);
4413                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4414                 goto out;
4415         }
4416
4417         /*
4418          * Clearing NACK and defer counts to get their exact values
4419          * while reading EDID which are required by Compliance tests
4420          * 4.2.2.4 and 4.2.2.5
4421          */
4422         intel_dp->aux.i2c_nack_count = 0;
4423         intel_dp->aux.i2c_defer_count = 0;
4424
4425         intel_dp_set_edid(intel_dp);
4426
4427         status = connector_status_connected;
4428         intel_dp->detect_done = true;
4429
4430         /* Try to read the source of the interrupt */
4431         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4432             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4433             sink_irq_vector != 0) {
4434                 /* Clear interrupt source */
4435                 drm_dp_dpcd_writeb(&intel_dp->aux,
4436                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4437                                    sink_irq_vector);
4438
4439                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4440                         intel_dp_handle_test_request(intel_dp);
4441                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4442                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4443         }
4444
4445 out:
4446         if ((status != connector_status_connected) &&
4447             (intel_dp->is_mst == false))
4448                 intel_dp_unset_edid(intel_dp);
4449
4450         intel_display_power_put(to_i915(dev), power_domain);
4451         return;
4452 }
4453
4454 static enum drm_connector_status
4455 intel_dp_detect(struct drm_connector *connector, bool force)
4456 {
4457         struct intel_dp *intel_dp = intel_attached_dp(connector);
4458         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4459         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4460         struct intel_connector *intel_connector = to_intel_connector(connector);
4461
4462         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4463                       connector->base.id, connector->name);
4464
4465         if (intel_dp->is_mst) {
4466                 /* MST devices are disconnected from a monitor POV */
4467                 intel_dp_unset_edid(intel_dp);
4468                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4469                         intel_encoder->type = INTEL_OUTPUT_DP;
4470                 return connector_status_disconnected;
4471         }
4472
4473         /* If full detect is not performed yet, do a full detect */
4474         if (!intel_dp->detect_done)
4475                 intel_dp_long_pulse(intel_dp->attached_connector);
4476
4477         intel_dp->detect_done = false;
4478
4479         if (is_edp(intel_dp) || intel_connector->detect_edid)
4480                 return connector_status_connected;
4481         else
4482                 return connector_status_disconnected;
4483 }
4484
4485 static void
4486 intel_dp_force(struct drm_connector *connector)
4487 {
4488         struct intel_dp *intel_dp = intel_attached_dp(connector);
4489         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4490         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4491         enum intel_display_power_domain power_domain;
4492
4493         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4494                       connector->base.id, connector->name);
4495         intel_dp_unset_edid(intel_dp);
4496
4497         if (connector->status != connector_status_connected)
4498                 return;
4499
4500         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4501         intel_display_power_get(dev_priv, power_domain);
4502
4503         intel_dp_set_edid(intel_dp);
4504
4505         intel_display_power_put(dev_priv, power_domain);
4506
4507         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4508                 intel_encoder->type = INTEL_OUTPUT_DP;
4509 }
4510
4511 static int intel_dp_get_modes(struct drm_connector *connector)
4512 {
4513         struct intel_connector *intel_connector = to_intel_connector(connector);
4514         struct edid *edid;
4515
4516         edid = intel_connector->detect_edid;
4517         if (edid) {
4518                 int ret = intel_connector_update_modes(connector, edid);
4519                 if (ret)
4520                         return ret;
4521         }
4522
4523         /* if eDP has no EDID, fall back to fixed mode */
4524         if (is_edp(intel_attached_dp(connector)) &&
4525             intel_connector->panel.fixed_mode) {
4526                 struct drm_display_mode *mode;
4527
4528                 mode = drm_mode_duplicate(connector->dev,
4529                                           intel_connector->panel.fixed_mode);
4530                 if (mode) {
4531                         drm_mode_probed_add(connector, mode);
4532                         return 1;
4533                 }
4534         }
4535
4536         return 0;
4537 }
4538
4539 static bool
4540 intel_dp_detect_audio(struct drm_connector *connector)
4541 {
4542         bool has_audio = false;
4543         struct edid *edid;
4544
4545         edid = to_intel_connector(connector)->detect_edid;
4546         if (edid)
4547                 has_audio = drm_detect_monitor_audio(edid);
4548
4549         return has_audio;
4550 }
4551
4552 static int
4553 intel_dp_set_property(struct drm_connector *connector,
4554                       struct drm_property *property,
4555                       uint64_t val)
4556 {
4557         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4558         struct intel_connector *intel_connector = to_intel_connector(connector);
4559         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4560         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4561         int ret;
4562
4563         ret = drm_object_property_set_value(&connector->base, property, val);
4564         if (ret)
4565                 return ret;
4566
4567         if (property == dev_priv->force_audio_property) {
4568                 int i = val;
4569                 bool has_audio;
4570
4571                 if (i == intel_dp->force_audio)
4572                         return 0;
4573
4574                 intel_dp->force_audio = i;
4575
4576                 if (i == HDMI_AUDIO_AUTO)
4577                         has_audio = intel_dp_detect_audio(connector);
4578                 else
4579                         has_audio = (i == HDMI_AUDIO_ON);
4580
4581                 if (has_audio == intel_dp->has_audio)
4582                         return 0;
4583
4584                 intel_dp->has_audio = has_audio;
4585                 goto done;
4586         }
4587
4588         if (property == dev_priv->broadcast_rgb_property) {
4589                 bool old_auto = intel_dp->color_range_auto;
4590                 bool old_range = intel_dp->limited_color_range;
4591
4592                 switch (val) {
4593                 case INTEL_BROADCAST_RGB_AUTO:
4594                         intel_dp->color_range_auto = true;
4595                         break;
4596                 case INTEL_BROADCAST_RGB_FULL:
4597                         intel_dp->color_range_auto = false;
4598                         intel_dp->limited_color_range = false;
4599                         break;
4600                 case INTEL_BROADCAST_RGB_LIMITED:
4601                         intel_dp->color_range_auto = false;
4602                         intel_dp->limited_color_range = true;
4603                         break;
4604                 default:
4605                         return -EINVAL;
4606                 }
4607
4608                 if (old_auto == intel_dp->color_range_auto &&
4609                     old_range == intel_dp->limited_color_range)
4610                         return 0;
4611
4612                 goto done;
4613         }
4614
4615         if (is_edp(intel_dp) &&
4616             property == connector->dev->mode_config.scaling_mode_property) {
4617                 if (val == DRM_MODE_SCALE_NONE) {
4618                         DRM_DEBUG_KMS("no scaling not supported\n");
4619                         return -EINVAL;
4620                 }
4621                 if (HAS_GMCH_DISPLAY(dev_priv) &&
4622                     val == DRM_MODE_SCALE_CENTER) {
4623                         DRM_DEBUG_KMS("centering not supported\n");
4624                         return -EINVAL;
4625                 }
4626
4627                 if (intel_connector->panel.fitting_mode == val) {
4628                         /* the eDP scaling property is not changed */
4629                         return 0;
4630                 }
4631                 intel_connector->panel.fitting_mode = val;
4632
4633                 goto done;
4634         }
4635
4636         return -EINVAL;
4637
4638 done:
4639         if (intel_encoder->base.crtc)
4640                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4641
4642         return 0;
4643 }
4644
4645 static int
4646 intel_dp_connector_register(struct drm_connector *connector)
4647 {
4648         struct intel_dp *intel_dp = intel_attached_dp(connector);
4649         int ret;
4650
4651         ret = intel_connector_register(connector);
4652         if (ret)
4653                 return ret;
4654
4655         i915_debugfs_connector_add(connector);
4656
4657         DRM_DEBUG_KMS("registering %s bus for %s\n",
4658                       intel_dp->aux.name, connector->kdev->kobj.name);
4659
4660         intel_dp->aux.dev = connector->kdev;
4661         return drm_dp_aux_register(&intel_dp->aux);
4662 }
4663
4664 static void
4665 intel_dp_connector_unregister(struct drm_connector *connector)
4666 {
4667         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4668         intel_connector_unregister(connector);
4669 }
4670
4671 static void
4672 intel_dp_connector_destroy(struct drm_connector *connector)
4673 {
4674         struct intel_connector *intel_connector = to_intel_connector(connector);
4675
4676         kfree(intel_connector->detect_edid);
4677
4678         if (!IS_ERR_OR_NULL(intel_connector->edid))
4679                 kfree(intel_connector->edid);
4680
4681         /* Can't call is_edp() since the encoder may have been destroyed
4682          * already. */
4683         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4684                 intel_panel_fini(&intel_connector->panel);
4685
4686         drm_connector_cleanup(connector);
4687         kfree(connector);
4688 }
4689
4690 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4691 {
4692         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4693         struct intel_dp *intel_dp = &intel_dig_port->dp;
4694
4695         intel_dp_mst_encoder_cleanup(intel_dig_port);
4696         if (is_edp(intel_dp)) {
4697                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4698                 /*
4699                  * vdd might still be enabled do to the delayed vdd off.
4700                  * Make sure vdd is actually turned off here.
4701                  */
4702                 pps_lock(intel_dp);
4703                 edp_panel_vdd_off_sync(intel_dp);
4704                 pps_unlock(intel_dp);
4705
4706                 if (intel_dp->edp_notifier.notifier_call) {
4707                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4708                         intel_dp->edp_notifier.notifier_call = NULL;
4709                 }
4710         }
4711
4712         intel_dp_aux_fini(intel_dp);
4713
4714         drm_encoder_cleanup(encoder);
4715         kfree(intel_dig_port);
4716 }
4717
4718 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4719 {
4720         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4721
4722         if (!is_edp(intel_dp))
4723                 return;
4724
4725         /*
4726          * vdd might still be enabled do to the delayed vdd off.
4727          * Make sure vdd is actually turned off here.
4728          */
4729         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4730         pps_lock(intel_dp);
4731         edp_panel_vdd_off_sync(intel_dp);
4732         pps_unlock(intel_dp);
4733 }
4734
4735 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4736 {
4737         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4738         struct drm_device *dev = intel_dig_port->base.base.dev;
4739         struct drm_i915_private *dev_priv = to_i915(dev);
4740         enum intel_display_power_domain power_domain;
4741
4742         lockdep_assert_held(&dev_priv->pps_mutex);
4743
4744         if (!edp_have_panel_vdd(intel_dp))
4745                 return;
4746
4747         /*
4748          * The VDD bit needs a power domain reference, so if the bit is
4749          * already enabled when we boot or resume, grab this reference and
4750          * schedule a vdd off, so we don't hold on to the reference
4751          * indefinitely.
4752          */
4753         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4754         power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4755         intel_display_power_get(dev_priv, power_domain);
4756
4757         edp_panel_vdd_schedule_off(intel_dp);
4758 }
4759
4760 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4761 {
4762         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4763         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4764
4765         if (!HAS_DDI(dev_priv))
4766                 intel_dp->DP = I915_READ(intel_dp->output_reg);
4767
4768         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4769                 return;
4770
4771         pps_lock(intel_dp);
4772
4773         /* Reinit the power sequencer, in case BIOS did something with it. */
4774         intel_dp_pps_init(encoder->dev, intel_dp);
4775         intel_edp_panel_vdd_sanitize(intel_dp);
4776
4777         pps_unlock(intel_dp);
4778 }
4779
4780 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4781         .dpms = drm_atomic_helper_connector_dpms,
4782         .detect = intel_dp_detect,
4783         .force = intel_dp_force,
4784         .fill_modes = drm_helper_probe_single_connector_modes,
4785         .set_property = intel_dp_set_property,
4786         .atomic_get_property = intel_connector_atomic_get_property,
4787         .late_register = intel_dp_connector_register,
4788         .early_unregister = intel_dp_connector_unregister,
4789         .destroy = intel_dp_connector_destroy,
4790         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4791         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4792 };
4793
4794 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4795         .get_modes = intel_dp_get_modes,
4796         .mode_valid = intel_dp_mode_valid,
4797 };
4798
4799 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4800         .reset = intel_dp_encoder_reset,
4801         .destroy = intel_dp_encoder_destroy,
4802 };
4803
4804 enum irqreturn
4805 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4806 {
4807         struct intel_dp *intel_dp = &intel_dig_port->dp;
4808         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4809         struct drm_device *dev = intel_dig_port->base.base.dev;
4810         struct drm_i915_private *dev_priv = to_i915(dev);
4811         enum intel_display_power_domain power_domain;
4812         enum irqreturn ret = IRQ_NONE;
4813
4814         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4815             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4816                 intel_dig_port->base.type = INTEL_OUTPUT_DP;
4817
4818         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4819                 /*
4820                  * vdd off can generate a long pulse on eDP which
4821                  * would require vdd on to handle it, and thus we
4822                  * would end up in an endless cycle of
4823                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4824                  */
4825                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4826                               port_name(intel_dig_port->port));
4827                 return IRQ_HANDLED;
4828         }
4829
4830         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4831                       port_name(intel_dig_port->port),
4832                       long_hpd ? "long" : "short");
4833
4834         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4835         intel_display_power_get(dev_priv, power_domain);
4836
4837         if (long_hpd) {
4838                 intel_dp_long_pulse(intel_dp->attached_connector);
4839                 if (intel_dp->is_mst)
4840                         ret = IRQ_HANDLED;
4841                 goto put_power;
4842
4843         } else {
4844                 if (intel_dp->is_mst) {
4845                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4846                                 /*
4847                                  * If we were in MST mode, and device is not
4848                                  * there, get out of MST mode
4849                                  */
4850                                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4851                                               intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4852                                 intel_dp->is_mst = false;
4853                                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4854                                                                 intel_dp->is_mst);
4855                                 goto put_power;
4856                         }
4857                 }
4858
4859                 if (!intel_dp->is_mst) {
4860                         if (!intel_dp_short_pulse(intel_dp)) {
4861                                 intel_dp_long_pulse(intel_dp->attached_connector);
4862                                 goto put_power;
4863                         }
4864                 }
4865         }
4866
4867         ret = IRQ_HANDLED;
4868
4869 put_power:
4870         intel_display_power_put(dev_priv, power_domain);
4871
4872         return ret;
4873 }
4874
4875 /* check the VBT to see whether the eDP is on another port */
4876 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4877 {
4878         struct drm_i915_private *dev_priv = to_i915(dev);
4879
4880         /*
4881          * eDP not supported on g4x. so bail out early just
4882          * for a bit extra safety in case the VBT is bonkers.
4883          */
4884         if (INTEL_INFO(dev)->gen < 5)
4885                 return false;
4886
4887         if (port == PORT_A)
4888                 return true;
4889
4890         return intel_bios_is_port_edp(dev_priv, port);
4891 }
4892
4893 void
4894 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4895 {
4896         struct intel_connector *intel_connector = to_intel_connector(connector);
4897
4898         intel_attach_force_audio_property(connector);
4899         intel_attach_broadcast_rgb_property(connector);
4900         intel_dp->color_range_auto = true;
4901
4902         if (is_edp(intel_dp)) {
4903                 drm_mode_create_scaling_mode_property(connector->dev);
4904                 drm_object_attach_property(
4905                         &connector->base,
4906                         connector->dev->mode_config.scaling_mode_property,
4907                         DRM_MODE_SCALE_ASPECT);
4908                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4909         }
4910 }
4911
4912 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4913 {
4914         intel_dp->panel_power_off_time = ktime_get_boottime();
4915         intel_dp->last_power_on = jiffies;
4916         intel_dp->last_backlight_off = jiffies;
4917 }
4918
4919 static void
4920 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
4921                            struct intel_dp *intel_dp, struct edp_power_seq *seq)
4922 {
4923         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
4924         struct pps_registers regs;
4925
4926         intel_pps_get_registers(dev_priv, intel_dp, &regs);
4927
4928         /* Workaround: Need to write PP_CONTROL with the unlock key as
4929          * the very first thing. */
4930         pp_ctl = ironlake_get_pp_control(intel_dp);
4931
4932         pp_on = I915_READ(regs.pp_on);
4933         pp_off = I915_READ(regs.pp_off);
4934         if (!IS_BROXTON(dev_priv)) {
4935                 I915_WRITE(regs.pp_ctrl, pp_ctl);
4936                 pp_div = I915_READ(regs.pp_div);
4937         }
4938
4939         /* Pull timing values out of registers */
4940         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4941                      PANEL_POWER_UP_DELAY_SHIFT;
4942
4943         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4944                   PANEL_LIGHT_ON_DELAY_SHIFT;
4945
4946         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4947                   PANEL_LIGHT_OFF_DELAY_SHIFT;
4948
4949         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4950                    PANEL_POWER_DOWN_DELAY_SHIFT;
4951
4952         if (IS_BROXTON(dev_priv)) {
4953                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4954                         BXT_POWER_CYCLE_DELAY_SHIFT;
4955                 if (tmp > 0)
4956                         seq->t11_t12 = (tmp - 1) * 1000;
4957                 else
4958                         seq->t11_t12 = 0;
4959         } else {
4960                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4961                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4962         }
4963 }
4964
4965 static void
4966 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
4967 {
4968         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4969                       state_name,
4970                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
4971 }
4972
4973 static void
4974 intel_pps_verify_state(struct drm_i915_private *dev_priv,
4975                        struct intel_dp *intel_dp)
4976 {
4977         struct edp_power_seq hw;
4978         struct edp_power_seq *sw = &intel_dp->pps_delays;
4979
4980         intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
4981
4982         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
4983             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
4984                 DRM_ERROR("PPS state mismatch\n");
4985                 intel_pps_dump_state("sw", sw);
4986                 intel_pps_dump_state("hw", &hw);
4987         }
4988 }
4989
4990 static void
4991 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4992                                     struct intel_dp *intel_dp)
4993 {
4994         struct drm_i915_private *dev_priv = to_i915(dev);
4995         struct edp_power_seq cur, vbt, spec,
4996                 *final = &intel_dp->pps_delays;
4997
4998         lockdep_assert_held(&dev_priv->pps_mutex);
4999
5000         /* already initialized? */
5001         if (final->t11_t12 != 0)
5002                 return;
5003
5004         intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5005
5006         intel_pps_dump_state("cur", &cur);
5007
5008         vbt = dev_priv->vbt.edp.pps;
5009
5010         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5011          * our hw here, which are all in 100usec. */
5012         spec.t1_t3 = 210 * 10;
5013         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5014         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5015         spec.t10 = 500 * 10;
5016         /* This one is special and actually in units of 100ms, but zero
5017          * based in the hw (so we need to add 100 ms). But the sw vbt
5018          * table multiplies it with 1000 to make it in units of 100usec,
5019          * too. */
5020         spec.t11_t12 = (510 + 100) * 10;
5021
5022         intel_pps_dump_state("vbt", &vbt);
5023
5024         /* Use the max of the register settings and vbt. If both are
5025          * unset, fall back to the spec limits. */
5026 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5027                                        spec.field : \
5028                                        max(cur.field, vbt.field))
5029         assign_final(t1_t3);
5030         assign_final(t8);
5031         assign_final(t9);
5032         assign_final(t10);
5033         assign_final(t11_t12);
5034 #undef assign_final
5035
5036 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5037         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5038         intel_dp->backlight_on_delay = get_delay(t8);
5039         intel_dp->backlight_off_delay = get_delay(t9);
5040         intel_dp->panel_power_down_delay = get_delay(t10);
5041         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5042 #undef get_delay
5043
5044         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5045                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5046                       intel_dp->panel_power_cycle_delay);
5047
5048         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5049                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5050
5051         /*
5052          * We override the HW backlight delays to 1 because we do manual waits
5053          * on them. For T8, even BSpec recommends doing it. For T9, if we
5054          * don't do this, we'll end up waiting for the backlight off delay
5055          * twice: once when we do the manual sleep, and once when we disable
5056          * the panel and wait for the PP_STATUS bit to become zero.
5057          */
5058         final->t8 = 1;
5059         final->t9 = 1;
5060 }
5061
5062 static void
5063 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5064                                               struct intel_dp *intel_dp)
5065 {
5066         struct drm_i915_private *dev_priv = to_i915(dev);
5067         u32 pp_on, pp_off, pp_div, port_sel = 0;
5068         int div = dev_priv->rawclk_freq / 1000;
5069         struct pps_registers regs;
5070         enum port port = dp_to_dig_port(intel_dp)->port;
5071         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5072
5073         lockdep_assert_held(&dev_priv->pps_mutex);
5074
5075         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5076
5077         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5078                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5079         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5080                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5081         /* Compute the divisor for the pp clock, simply match the Bspec
5082          * formula. */
5083         if (IS_BROXTON(dev)) {
5084                 pp_div = I915_READ(regs.pp_ctrl);
5085                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5086                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5087                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5088         } else {
5089                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5090                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5091                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5092         }
5093
5094         /* Haswell doesn't have any port selection bits for the panel
5095          * power sequencer any more. */
5096         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5097                 port_sel = PANEL_PORT_SELECT_VLV(port);
5098         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5099                 if (port == PORT_A)
5100                         port_sel = PANEL_PORT_SELECT_DPA;
5101                 else
5102                         port_sel = PANEL_PORT_SELECT_DPD;
5103         }
5104
5105         pp_on |= port_sel;
5106
5107         I915_WRITE(regs.pp_on, pp_on);
5108         I915_WRITE(regs.pp_off, pp_off);
5109         if (IS_BROXTON(dev))
5110                 I915_WRITE(regs.pp_ctrl, pp_div);
5111         else
5112                 I915_WRITE(regs.pp_div, pp_div);
5113
5114         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5115                       I915_READ(regs.pp_on),
5116                       I915_READ(regs.pp_off),
5117                       IS_BROXTON(dev) ?
5118                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5119                       I915_READ(regs.pp_div));
5120 }
5121
5122 static void intel_dp_pps_init(struct drm_device *dev,
5123                               struct intel_dp *intel_dp)
5124 {
5125         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5126                 vlv_initial_power_sequencer_setup(intel_dp);
5127         } else {
5128                 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5129                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5130         }
5131 }
5132
5133 /**
5134  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5135  * @dev_priv: i915 device
5136  * @crtc_state: a pointer to the active intel_crtc_state
5137  * @refresh_rate: RR to be programmed
5138  *
5139  * This function gets called when refresh rate (RR) has to be changed from
5140  * one frequency to another. Switches can be between high and low RR
5141  * supported by the panel or to any other RR based on media playback (in
5142  * this case, RR value needs to be passed from user space).
5143  *
5144  * The caller of this function needs to take a lock on dev_priv->drrs.
5145  */
5146 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5147                                     struct intel_crtc_state *crtc_state,
5148                                     int refresh_rate)
5149 {
5150         struct intel_encoder *encoder;
5151         struct intel_digital_port *dig_port = NULL;
5152         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5153         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5154         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5155
5156         if (refresh_rate <= 0) {
5157                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5158                 return;
5159         }
5160
5161         if (intel_dp == NULL) {
5162                 DRM_DEBUG_KMS("DRRS not supported.\n");
5163                 return;
5164         }
5165
5166         /*
5167          * FIXME: This needs proper synchronization with psr state for some
5168          * platforms that cannot have PSR and DRRS enabled at the same time.
5169          */
5170
5171         dig_port = dp_to_dig_port(intel_dp);
5172         encoder = &dig_port->base;
5173         intel_crtc = to_intel_crtc(encoder->base.crtc);
5174
5175         if (!intel_crtc) {
5176                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5177                 return;
5178         }
5179
5180         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5181                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5182                 return;
5183         }
5184
5185         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5186                         refresh_rate)
5187                 index = DRRS_LOW_RR;
5188
5189         if (index == dev_priv->drrs.refresh_rate_type) {
5190                 DRM_DEBUG_KMS(
5191                         "DRRS requested for previously set RR...ignoring\n");
5192                 return;
5193         }
5194
5195         if (!crtc_state->base.active) {
5196                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5197                 return;
5198         }
5199
5200         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5201                 switch (index) {
5202                 case DRRS_HIGH_RR:
5203                         intel_dp_set_m_n(intel_crtc, M1_N1);
5204                         break;
5205                 case DRRS_LOW_RR:
5206                         intel_dp_set_m_n(intel_crtc, M2_N2);
5207                         break;
5208                 case DRRS_MAX_RR:
5209                 default:
5210                         DRM_ERROR("Unsupported refreshrate type\n");
5211                 }
5212         } else if (INTEL_GEN(dev_priv) > 6) {
5213                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5214                 u32 val;
5215
5216                 val = I915_READ(reg);
5217                 if (index > DRRS_HIGH_RR) {
5218                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5219                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5220                         else
5221                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5222                 } else {
5223                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5224                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5225                         else
5226                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5227                 }
5228                 I915_WRITE(reg, val);
5229         }
5230
5231         dev_priv->drrs.refresh_rate_type = index;
5232
5233         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5234 }
5235
5236 /**
5237  * intel_edp_drrs_enable - init drrs struct if supported
5238  * @intel_dp: DP struct
5239  * @crtc_state: A pointer to the active crtc state.
5240  *
5241  * Initializes frontbuffer_bits and drrs.dp
5242  */
5243 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5244                            struct intel_crtc_state *crtc_state)
5245 {
5246         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5247         struct drm_i915_private *dev_priv = to_i915(dev);
5248
5249         if (!crtc_state->has_drrs) {
5250                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5251                 return;
5252         }
5253
5254         mutex_lock(&dev_priv->drrs.mutex);
5255         if (WARN_ON(dev_priv->drrs.dp)) {
5256                 DRM_ERROR("DRRS already enabled\n");
5257                 goto unlock;
5258         }
5259
5260         dev_priv->drrs.busy_frontbuffer_bits = 0;
5261
5262         dev_priv->drrs.dp = intel_dp;
5263
5264 unlock:
5265         mutex_unlock(&dev_priv->drrs.mutex);
5266 }
5267
5268 /**
5269  * intel_edp_drrs_disable - Disable DRRS
5270  * @intel_dp: DP struct
5271  * @old_crtc_state: Pointer to old crtc_state.
5272  *
5273  */
5274 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5275                             struct intel_crtc_state *old_crtc_state)
5276 {
5277         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5278         struct drm_i915_private *dev_priv = to_i915(dev);
5279
5280         if (!old_crtc_state->has_drrs)
5281                 return;
5282
5283         mutex_lock(&dev_priv->drrs.mutex);
5284         if (!dev_priv->drrs.dp) {
5285                 mutex_unlock(&dev_priv->drrs.mutex);
5286                 return;
5287         }
5288
5289         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5290                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5291                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5292
5293         dev_priv->drrs.dp = NULL;
5294         mutex_unlock(&dev_priv->drrs.mutex);
5295
5296         cancel_delayed_work_sync(&dev_priv->drrs.work);
5297 }
5298
5299 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5300 {
5301         struct drm_i915_private *dev_priv =
5302                 container_of(work, typeof(*dev_priv), drrs.work.work);
5303         struct intel_dp *intel_dp;
5304
5305         mutex_lock(&dev_priv->drrs.mutex);
5306
5307         intel_dp = dev_priv->drrs.dp;
5308
5309         if (!intel_dp)
5310                 goto unlock;
5311
5312         /*
5313          * The delayed work can race with an invalidate hence we need to
5314          * recheck.
5315          */
5316
5317         if (dev_priv->drrs.busy_frontbuffer_bits)
5318                 goto unlock;
5319
5320         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5321                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5322
5323                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5324                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5325         }
5326
5327 unlock:
5328         mutex_unlock(&dev_priv->drrs.mutex);
5329 }
5330
5331 /**
5332  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5333  * @dev_priv: i915 device
5334  * @frontbuffer_bits: frontbuffer plane tracking bits
5335  *
5336  * This function gets called everytime rendering on the given planes start.
5337  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5338  *
5339  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5340  */
5341 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5342                                unsigned int frontbuffer_bits)
5343 {
5344         struct drm_crtc *crtc;
5345         enum pipe pipe;
5346
5347         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5348                 return;
5349
5350         cancel_delayed_work(&dev_priv->drrs.work);
5351
5352         mutex_lock(&dev_priv->drrs.mutex);
5353         if (!dev_priv->drrs.dp) {
5354                 mutex_unlock(&dev_priv->drrs.mutex);
5355                 return;
5356         }
5357
5358         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5359         pipe = to_intel_crtc(crtc)->pipe;
5360
5361         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5362         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5363
5364         /* invalidate means busy screen hence upclock */
5365         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5366                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5367                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5368
5369         mutex_unlock(&dev_priv->drrs.mutex);
5370 }
5371
5372 /**
5373  * intel_edp_drrs_flush - Restart Idleness DRRS
5374  * @dev_priv: i915 device
5375  * @frontbuffer_bits: frontbuffer plane tracking bits
5376  *
5377  * This function gets called every time rendering on the given planes has
5378  * completed or flip on a crtc is completed. So DRRS should be upclocked
5379  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5380  * if no other planes are dirty.
5381  *
5382  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5383  */
5384 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5385                           unsigned int frontbuffer_bits)
5386 {
5387         struct drm_crtc *crtc;
5388         enum pipe pipe;
5389
5390         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5391                 return;
5392
5393         cancel_delayed_work(&dev_priv->drrs.work);
5394
5395         mutex_lock(&dev_priv->drrs.mutex);
5396         if (!dev_priv->drrs.dp) {
5397                 mutex_unlock(&dev_priv->drrs.mutex);
5398                 return;
5399         }
5400
5401         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5402         pipe = to_intel_crtc(crtc)->pipe;
5403
5404         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5405         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5406
5407         /* flush means busy screen hence upclock */
5408         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5409                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5410                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5411
5412         /*
5413          * flush also means no more activity hence schedule downclock, if all
5414          * other fbs are quiescent too
5415          */
5416         if (!dev_priv->drrs.busy_frontbuffer_bits)
5417                 schedule_delayed_work(&dev_priv->drrs.work,
5418                                 msecs_to_jiffies(1000));
5419         mutex_unlock(&dev_priv->drrs.mutex);
5420 }
5421
5422 /**
5423  * DOC: Display Refresh Rate Switching (DRRS)
5424  *
5425  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5426  * which enables swtching between low and high refresh rates,
5427  * dynamically, based on the usage scenario. This feature is applicable
5428  * for internal panels.
5429  *
5430  * Indication that the panel supports DRRS is given by the panel EDID, which
5431  * would list multiple refresh rates for one resolution.
5432  *
5433  * DRRS is of 2 types - static and seamless.
5434  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5435  * (may appear as a blink on screen) and is used in dock-undock scenario.
5436  * Seamless DRRS involves changing RR without any visual effect to the user
5437  * and can be used during normal system usage. This is done by programming
5438  * certain registers.
5439  *
5440  * Support for static/seamless DRRS may be indicated in the VBT based on
5441  * inputs from the panel spec.
5442  *
5443  * DRRS saves power by switching to low RR based on usage scenarios.
5444  *
5445  * The implementation is based on frontbuffer tracking implementation.  When
5446  * there is a disturbance on the screen triggered by user activity or a periodic
5447  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5448  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5449  * made.
5450  *
5451  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5452  * and intel_edp_drrs_flush() are called.
5453  *
5454  * DRRS can be further extended to support other internal panels and also
5455  * the scenario of video playback wherein RR is set based on the rate
5456  * requested by userspace.
5457  */
5458
5459 /**
5460  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5461  * @intel_connector: eDP connector
5462  * @fixed_mode: preferred mode of panel
5463  *
5464  * This function is  called only once at driver load to initialize basic
5465  * DRRS stuff.
5466  *
5467  * Returns:
5468  * Downclock mode if panel supports it, else return NULL.
5469  * DRRS support is determined by the presence of downclock mode (apart
5470  * from VBT setting).
5471  */
5472 static struct drm_display_mode *
5473 intel_dp_drrs_init(struct intel_connector *intel_connector,
5474                 struct drm_display_mode *fixed_mode)
5475 {
5476         struct drm_connector *connector = &intel_connector->base;
5477         struct drm_device *dev = connector->dev;
5478         struct drm_i915_private *dev_priv = to_i915(dev);
5479         struct drm_display_mode *downclock_mode = NULL;
5480
5481         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5482         mutex_init(&dev_priv->drrs.mutex);
5483
5484         if (INTEL_INFO(dev)->gen <= 6) {
5485                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5486                 return NULL;
5487         }
5488
5489         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5490                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5491                 return NULL;
5492         }
5493
5494         downclock_mode = intel_find_panel_downclock
5495                                         (dev, fixed_mode, connector);
5496
5497         if (!downclock_mode) {
5498                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5499                 return NULL;
5500         }
5501
5502         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5503
5504         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5505         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5506         return downclock_mode;
5507 }
5508
5509 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5510                                      struct intel_connector *intel_connector)
5511 {
5512         struct drm_connector *connector = &intel_connector->base;
5513         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5514         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5515         struct drm_device *dev = intel_encoder->base.dev;
5516         struct drm_i915_private *dev_priv = to_i915(dev);
5517         struct drm_display_mode *fixed_mode = NULL;
5518         struct drm_display_mode *downclock_mode = NULL;
5519         bool has_dpcd;
5520         struct drm_display_mode *scan;
5521         struct edid *edid;
5522         enum pipe pipe = INVALID_PIPE;
5523
5524         if (!is_edp(intel_dp))
5525                 return true;
5526
5527         /*
5528          * On IBX/CPT we may get here with LVDS already registered. Since the
5529          * driver uses the only internal power sequencer available for both
5530          * eDP and LVDS bail out early in this case to prevent interfering
5531          * with an already powered-on LVDS power sequencer.
5532          */
5533         if (intel_get_lvds_encoder(dev)) {
5534                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5535                 DRM_INFO("LVDS was detected, not registering eDP\n");
5536
5537                 return false;
5538         }
5539
5540         pps_lock(intel_dp);
5541
5542         intel_dp_init_panel_power_timestamps(intel_dp);
5543         intel_dp_pps_init(dev, intel_dp);
5544         intel_edp_panel_vdd_sanitize(intel_dp);
5545
5546         pps_unlock(intel_dp);
5547
5548         /* Cache DPCD and EDID for edp. */
5549         has_dpcd = intel_edp_init_dpcd(intel_dp);
5550
5551         if (!has_dpcd) {
5552                 /* if this fails, presume the device is a ghost */
5553                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5554                 goto out_vdd_off;
5555         }
5556
5557         mutex_lock(&dev->mode_config.mutex);
5558         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5559         if (edid) {
5560                 if (drm_add_edid_modes(connector, edid)) {
5561                         drm_mode_connector_update_edid_property(connector,
5562                                                                 edid);
5563                         drm_edid_to_eld(connector, edid);
5564                 } else {
5565                         kfree(edid);
5566                         edid = ERR_PTR(-EINVAL);
5567                 }
5568         } else {
5569                 edid = ERR_PTR(-ENOENT);
5570         }
5571         intel_connector->edid = edid;
5572
5573         /* prefer fixed mode from EDID if available */
5574         list_for_each_entry(scan, &connector->probed_modes, head) {
5575                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5576                         fixed_mode = drm_mode_duplicate(dev, scan);
5577                         downclock_mode = intel_dp_drrs_init(
5578                                                 intel_connector, fixed_mode);
5579                         break;
5580                 }
5581         }
5582
5583         /* fallback to VBT if available for eDP */
5584         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5585                 fixed_mode = drm_mode_duplicate(dev,
5586                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5587                 if (fixed_mode) {
5588                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5589                         connector->display_info.width_mm = fixed_mode->width_mm;
5590                         connector->display_info.height_mm = fixed_mode->height_mm;
5591                 }
5592         }
5593         mutex_unlock(&dev->mode_config.mutex);
5594
5595         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5596                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5597                 register_reboot_notifier(&intel_dp->edp_notifier);
5598
5599                 /*
5600                  * Figure out the current pipe for the initial backlight setup.
5601                  * If the current pipe isn't valid, try the PPS pipe, and if that
5602                  * fails just assume pipe A.
5603                  */
5604                 if (IS_CHERRYVIEW(dev))
5605                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5606                 else
5607                         pipe = PORT_TO_PIPE(intel_dp->DP);
5608
5609                 if (pipe != PIPE_A && pipe != PIPE_B)
5610                         pipe = intel_dp->pps_pipe;
5611
5612                 if (pipe != PIPE_A && pipe != PIPE_B)
5613                         pipe = PIPE_A;
5614
5615                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5616                               pipe_name(pipe));
5617         }
5618
5619         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5620         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5621         intel_panel_setup_backlight(connector, pipe);
5622
5623         return true;
5624
5625 out_vdd_off:
5626         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5627         /*
5628          * vdd might still be enabled do to the delayed vdd off.
5629          * Make sure vdd is actually turned off here.
5630          */
5631         pps_lock(intel_dp);
5632         edp_panel_vdd_off_sync(intel_dp);
5633         pps_unlock(intel_dp);
5634
5635         return false;
5636 }
5637
5638 bool
5639 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5640                         struct intel_connector *intel_connector)
5641 {
5642         struct drm_connector *connector = &intel_connector->base;
5643         struct intel_dp *intel_dp = &intel_dig_port->dp;
5644         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5645         struct drm_device *dev = intel_encoder->base.dev;
5646         struct drm_i915_private *dev_priv = to_i915(dev);
5647         enum port port = intel_dig_port->port;
5648         int type;
5649
5650         if (WARN(intel_dig_port->max_lanes < 1,
5651                  "Not enough lanes (%d) for DP on port %c\n",
5652                  intel_dig_port->max_lanes, port_name(port)))
5653                 return false;
5654
5655         intel_dp->pps_pipe = INVALID_PIPE;
5656
5657         /* intel_dp vfuncs */
5658         if (INTEL_INFO(dev)->gen >= 9)
5659                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5660         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5661                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5662         else if (HAS_PCH_SPLIT(dev))
5663                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5664         else
5665                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5666
5667         if (INTEL_INFO(dev)->gen >= 9)
5668                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5669         else
5670                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5671
5672         if (HAS_DDI(dev))
5673                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5674
5675         /* Preserve the current hw state. */
5676         intel_dp->DP = I915_READ(intel_dp->output_reg);
5677         intel_dp->attached_connector = intel_connector;
5678
5679         if (intel_dp_is_edp(dev, port))
5680                 type = DRM_MODE_CONNECTOR_eDP;
5681         else
5682                 type = DRM_MODE_CONNECTOR_DisplayPort;
5683
5684         /*
5685          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5686          * for DP the encoder type can be set by the caller to
5687          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5688          */
5689         if (type == DRM_MODE_CONNECTOR_eDP)
5690                 intel_encoder->type = INTEL_OUTPUT_EDP;
5691
5692         /* eDP only on port B and/or C on vlv/chv */
5693         if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5694                     is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5695                 return false;
5696
5697         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5698                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5699                         port_name(port));
5700
5701         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5702         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5703
5704         connector->interlace_allowed = true;
5705         connector->doublescan_allowed = 0;
5706
5707         intel_dp_aux_init(intel_dp);
5708
5709         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5710                           edp_panel_vdd_work);
5711
5712         intel_connector_attach_encoder(intel_connector, intel_encoder);
5713
5714         if (HAS_DDI(dev))
5715                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5716         else
5717                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5718
5719         /* Set up the hotplug pin. */
5720         switch (port) {
5721         case PORT_A:
5722                 intel_encoder->hpd_pin = HPD_PORT_A;
5723                 break;
5724         case PORT_B:
5725                 intel_encoder->hpd_pin = HPD_PORT_B;
5726                 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
5727                         intel_encoder->hpd_pin = HPD_PORT_A;
5728                 break;
5729         case PORT_C:
5730                 intel_encoder->hpd_pin = HPD_PORT_C;
5731                 break;
5732         case PORT_D:
5733                 intel_encoder->hpd_pin = HPD_PORT_D;
5734                 break;
5735         case PORT_E:
5736                 intel_encoder->hpd_pin = HPD_PORT_E;
5737                 break;
5738         default:
5739                 BUG();
5740         }
5741
5742         /* init MST on ports that can support it */
5743         if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
5744             (port == PORT_B || port == PORT_C || port == PORT_D))
5745                 intel_dp_mst_encoder_init(intel_dig_port,
5746                                           intel_connector->base.base.id);
5747
5748         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5749                 intel_dp_aux_fini(intel_dp);
5750                 intel_dp_mst_encoder_cleanup(intel_dig_port);
5751                 goto fail;
5752         }
5753
5754         intel_dp_add_properties(intel_dp, connector);
5755
5756         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5757          * 0xd.  Failure to do so will result in spurious interrupts being
5758          * generated on the port when a cable is not attached.
5759          */
5760         if (IS_G4X(dev) && !IS_GM45(dev)) {
5761                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5762                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5763         }
5764
5765         return true;
5766
5767 fail:
5768         drm_connector_cleanup(connector);
5769
5770         return false;
5771 }
5772
5773 bool intel_dp_init(struct drm_device *dev,
5774                    i915_reg_t output_reg,
5775                    enum port port)
5776 {
5777         struct drm_i915_private *dev_priv = to_i915(dev);
5778         struct intel_digital_port *intel_dig_port;
5779         struct intel_encoder *intel_encoder;
5780         struct drm_encoder *encoder;
5781         struct intel_connector *intel_connector;
5782
5783         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5784         if (!intel_dig_port)
5785                 return false;
5786
5787         intel_connector = intel_connector_alloc();
5788         if (!intel_connector)
5789                 goto err_connector_alloc;
5790
5791         intel_encoder = &intel_dig_port->base;
5792         encoder = &intel_encoder->base;
5793
5794         if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5795                              DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
5796                 goto err_encoder_init;
5797
5798         intel_encoder->compute_config = intel_dp_compute_config;
5799         intel_encoder->disable = intel_disable_dp;
5800         intel_encoder->get_hw_state = intel_dp_get_hw_state;
5801         intel_encoder->get_config = intel_dp_get_config;
5802         intel_encoder->suspend = intel_dp_encoder_suspend;
5803         if (IS_CHERRYVIEW(dev)) {
5804                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5805                 intel_encoder->pre_enable = chv_pre_enable_dp;
5806                 intel_encoder->enable = vlv_enable_dp;
5807                 intel_encoder->post_disable = chv_post_disable_dp;
5808                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
5809         } else if (IS_VALLEYVIEW(dev)) {
5810                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5811                 intel_encoder->pre_enable = vlv_pre_enable_dp;
5812                 intel_encoder->enable = vlv_enable_dp;
5813                 intel_encoder->post_disable = vlv_post_disable_dp;
5814         } else {
5815                 intel_encoder->pre_enable = g4x_pre_enable_dp;
5816                 intel_encoder->enable = g4x_enable_dp;
5817                 if (INTEL_INFO(dev)->gen >= 5)
5818                         intel_encoder->post_disable = ilk_post_disable_dp;
5819         }
5820
5821         intel_dig_port->port = port;
5822         intel_dig_port->dp.output_reg = output_reg;
5823         intel_dig_port->max_lanes = 4;
5824
5825         intel_encoder->type = INTEL_OUTPUT_DP;
5826         if (IS_CHERRYVIEW(dev)) {
5827                 if (port == PORT_D)
5828                         intel_encoder->crtc_mask = 1 << 2;
5829                 else
5830                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5831         } else {
5832                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5833         }
5834         intel_encoder->cloneable = 0;
5835
5836         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5837         dev_priv->hotplug.irq_port[port] = intel_dig_port;
5838
5839         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5840                 goto err_init_connector;
5841
5842         return true;
5843
5844 err_init_connector:
5845         drm_encoder_cleanup(encoder);
5846 err_encoder_init:
5847         kfree(intel_connector);
5848 err_connector_alloc:
5849         kfree(intel_dig_port);
5850         return false;
5851 }
5852
5853 void intel_dp_mst_suspend(struct drm_device *dev)
5854 {
5855         struct drm_i915_private *dev_priv = to_i915(dev);
5856         int i;
5857
5858         /* disable MST */
5859         for (i = 0; i < I915_MAX_PORTS; i++) {
5860                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5861
5862                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5863                         continue;
5864
5865                 if (intel_dig_port->dp.is_mst)
5866                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5867         }
5868 }
5869
5870 void intel_dp_mst_resume(struct drm_device *dev)
5871 {
5872         struct drm_i915_private *dev_priv = to_i915(dev);
5873         int i;
5874
5875         for (i = 0; i < I915_MAX_PORTS; i++) {
5876                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5877                 int ret;
5878
5879                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5880                         continue;
5881
5882                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5883                 if (ret)
5884                         intel_dp_check_mst_status(&intel_dig_port->dp);
5885         }
5886 }