2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/types.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <asm/byteorder.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_dp_helper.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_hdcp.h>
42 #include "intel_drv.h"
43 #include <drm/i915_drm.h>
46 #define DP_DPRX_ESI_LEN 14
48 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
49 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
50 #define DP_DSC_MIN_SUPPORTED_BPC 8
51 #define DP_DSC_MAX_SUPPORTED_BPC 10
53 /* DP DSC throughput values used for slice count calculations KPixels/s */
54 #define DP_DSC_PEAK_PIXEL_RATE 2720000
55 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
56 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
58 /* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
59 #define DP_DSC_FEC_OVERHEAD_FACTOR 976
61 /* Compliance test status bits */
62 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
63 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
64 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
65 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
72 static const struct dp_link_dpll g4x_dpll[] = {
74 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
76 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
79 static const struct dp_link_dpll pch_dpll[] = {
81 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
83 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
86 static const struct dp_link_dpll vlv_dpll[] = {
88 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
90 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
94 * CHV supports eDP 1.4 that have more link rates.
95 * Below only provides the fixed rate but exclude variable rate.
97 static const struct dp_link_dpll chv_dpll[] = {
99 * CHV requires to program fractional division for m2.
100 * m2 is stored in fixed point format using formula below
101 * (m2_int << 22) | m2_fraction
103 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
104 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
105 { 270000, /* m2_int = 27, m2_fraction = 0 */
106 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
109 /* Constants for DP DSC configurations */
110 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
112 /* With Single pipe configuration, HW is capable of supporting maximum
113 * of 4 slices per line.
115 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
118 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
119 * @intel_dp: DP struct
121 * If a CPU or PCH DP output is attached to an eDP panel, this function
122 * will return true, and false otherwise.
124 bool intel_dp_is_edp(struct intel_dp *intel_dp)
126 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
128 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
131 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
133 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
136 static void intel_dp_link_down(struct intel_encoder *encoder,
137 const struct intel_crtc_state *old_crtc_state);
138 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
139 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
140 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
141 const struct intel_crtc_state *crtc_state);
142 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
144 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
146 /* update sink rates from dpcd */
147 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
149 static const int dp_rates[] = {
150 162000, 270000, 540000, 810000
154 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
156 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
157 if (dp_rates[i] > max_rate)
159 intel_dp->sink_rates[i] = dp_rates[i];
162 intel_dp->num_sink_rates = i;
165 /* Get length of rates array potentially limited by max_rate. */
166 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
170 /* Limit results by potentially reduced max rate */
171 for (i = 0; i < len; i++) {
172 if (rates[len - i - 1] <= max_rate)
179 /* Get length of common rates array potentially limited by max_rate. */
180 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
183 return intel_dp_rate_limit_len(intel_dp->common_rates,
184 intel_dp->num_common_rates, max_rate);
187 /* Theoretical max between source and sink */
188 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
190 return intel_dp->common_rates[intel_dp->num_common_rates - 1];
193 static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
195 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
196 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
197 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
200 if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
203 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
204 DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
205 DP_LANE_ASSIGNMENT_SHIFT(tc_port);
209 MISSING_CASE(lane_info);
223 /* Theoretical max between source and sink */
224 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
226 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
227 int source_max = intel_dig_port->max_lanes;
228 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
229 int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
231 return min3(source_max, sink_max, fia_max);
234 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
236 return intel_dp->max_link_lane_count;
240 intel_dp_link_required(int pixel_clock, int bpp)
242 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
243 return DIV_ROUND_UP(pixel_clock * bpp, 8);
247 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
249 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
250 * link rate that is generally expressed in Gbps. Since, 8 bits of data
251 * is transmitted every LS_Clk per lane, there is no need to account for
252 * the channel encoding that is done in the PHY layer here.
255 return max_link_clock * max_lanes;
259 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
261 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
262 struct intel_encoder *encoder = &intel_dig_port->base;
263 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
264 int max_dotclk = dev_priv->max_dotclk_freq;
267 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
269 if (type != DP_DS_PORT_TYPE_VGA)
272 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
273 intel_dp->downstream_ports);
275 if (ds_max_dotclk != 0)
276 max_dotclk = min(max_dotclk, ds_max_dotclk);
281 static int cnl_max_source_rate(struct intel_dp *intel_dp)
283 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
284 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
285 enum port port = dig_port->base.port;
287 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
289 /* Low voltage SKUs are limited to max of 5.4G */
290 if (voltage == VOLTAGE_INFO_0_85V)
293 /* For this SKU 8.1G is supported in all ports */
294 if (IS_CNL_WITH_PORT_F(dev_priv))
297 /* For other SKUs, max rate on ports A and D is 5.4G */
298 if (port == PORT_A || port == PORT_D)
304 static int icl_max_source_rate(struct intel_dp *intel_dp)
306 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
307 enum port port = dig_port->base.port;
316 intel_dp_set_source_rates(struct intel_dp *intel_dp)
318 /* The values must be in increasing order */
319 static const int cnl_rates[] = {
320 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
322 static const int bxt_rates[] = {
323 162000, 216000, 243000, 270000, 324000, 432000, 540000
325 static const int skl_rates[] = {
326 162000, 216000, 270000, 324000, 432000, 540000
328 static const int hsw_rates[] = {
329 162000, 270000, 540000
331 static const int g4x_rates[] = {
334 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
335 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
336 const struct ddi_vbt_port_info *info =
337 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
338 const int *source_rates;
339 int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
341 /* This should only be done once */
342 WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
344 if (INTEL_GEN(dev_priv) >= 10) {
345 source_rates = cnl_rates;
346 size = ARRAY_SIZE(cnl_rates);
347 if (IS_GEN10(dev_priv))
348 max_rate = cnl_max_source_rate(intel_dp);
350 max_rate = icl_max_source_rate(intel_dp);
351 } else if (IS_GEN9_LP(dev_priv)) {
352 source_rates = bxt_rates;
353 size = ARRAY_SIZE(bxt_rates);
354 } else if (IS_GEN9_BC(dev_priv)) {
355 source_rates = skl_rates;
356 size = ARRAY_SIZE(skl_rates);
357 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
358 IS_BROADWELL(dev_priv)) {
359 source_rates = hsw_rates;
360 size = ARRAY_SIZE(hsw_rates);
362 source_rates = g4x_rates;
363 size = ARRAY_SIZE(g4x_rates);
366 if (max_rate && vbt_max_rate)
367 max_rate = min(max_rate, vbt_max_rate);
368 else if (vbt_max_rate)
369 max_rate = vbt_max_rate;
372 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
374 intel_dp->source_rates = source_rates;
375 intel_dp->num_source_rates = size;
378 static int intersect_rates(const int *source_rates, int source_len,
379 const int *sink_rates, int sink_len,
382 int i = 0, j = 0, k = 0;
384 while (i < source_len && j < sink_len) {
385 if (source_rates[i] == sink_rates[j]) {
386 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
388 common_rates[k] = source_rates[i];
392 } else if (source_rates[i] < sink_rates[j]) {
401 /* return index of rate in rates array, or -1 if not found */
402 static int intel_dp_rate_index(const int *rates, int len, int rate)
406 for (i = 0; i < len; i++)
407 if (rate == rates[i])
413 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
415 WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
417 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
418 intel_dp->num_source_rates,
419 intel_dp->sink_rates,
420 intel_dp->num_sink_rates,
421 intel_dp->common_rates);
423 /* Paranoia, there should always be something in common. */
424 if (WARN_ON(intel_dp->num_common_rates == 0)) {
425 intel_dp->common_rates[0] = 162000;
426 intel_dp->num_common_rates = 1;
430 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
434 * FIXME: we need to synchronize the current link parameters with
435 * hardware readout. Currently fast link training doesn't work on
438 if (link_rate == 0 ||
439 link_rate > intel_dp->max_link_rate)
442 if (lane_count == 0 ||
443 lane_count > intel_dp_max_lane_count(intel_dp))
449 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
453 const struct drm_display_mode *fixed_mode =
454 intel_dp->attached_connector->panel.fixed_mode;
455 int mode_rate, max_rate;
457 mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
458 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
459 if (mode_rate > max_rate)
465 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
466 int link_rate, uint8_t lane_count)
470 index = intel_dp_rate_index(intel_dp->common_rates,
471 intel_dp->num_common_rates,
474 if (intel_dp_is_edp(intel_dp) &&
475 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
476 intel_dp->common_rates[index - 1],
478 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
481 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
482 intel_dp->max_link_lane_count = lane_count;
483 } else if (lane_count > 1) {
484 if (intel_dp_is_edp(intel_dp) &&
485 !intel_dp_can_link_train_fallback_for_edp(intel_dp,
486 intel_dp_max_common_rate(intel_dp),
488 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
491 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
492 intel_dp->max_link_lane_count = lane_count >> 1;
494 DRM_ERROR("Link Training Unsuccessful\n");
501 static enum drm_mode_status
502 intel_dp_mode_valid(struct drm_connector *connector,
503 struct drm_display_mode *mode)
505 struct intel_dp *intel_dp = intel_attached_dp(connector);
506 struct intel_connector *intel_connector = to_intel_connector(connector);
507 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
508 struct drm_i915_private *dev_priv = to_i915(connector->dev);
509 int target_clock = mode->clock;
510 int max_rate, mode_rate, max_lanes, max_link_clock;
512 u16 dsc_max_output_bpp = 0;
513 u8 dsc_slice_count = 0;
515 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
516 return MODE_NO_DBLESCAN;
518 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
520 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
521 if (mode->hdisplay > fixed_mode->hdisplay)
524 if (mode->vdisplay > fixed_mode->vdisplay)
527 target_clock = fixed_mode->clock;
530 max_link_clock = intel_dp_max_link_rate(intel_dp);
531 max_lanes = intel_dp_max_lane_count(intel_dp);
533 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
534 mode_rate = intel_dp_link_required(target_clock, 18);
537 * Output bpp is stored in 6.4 format so right shift by 4 to get the
538 * integer value since we support only integer values of bpp.
540 if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
541 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
542 if (intel_dp_is_edp(intel_dp)) {
544 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
546 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
548 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
550 intel_dp_dsc_get_output_bpp(max_link_clock,
553 mode->hdisplay) >> 4;
555 intel_dp_dsc_get_slice_count(intel_dp,
561 if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
562 target_clock > max_dotclk)
563 return MODE_CLOCK_HIGH;
565 if (mode->clock < 10000)
566 return MODE_CLOCK_LOW;
568 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
569 return MODE_H_ILLEGAL;
574 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
581 for (i = 0; i < src_bytes; i++)
582 v |= ((uint32_t) src[i]) << ((3-i) * 8);
586 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
591 for (i = 0; i < dst_bytes; i++)
592 dst[i] = src >> ((3-i) * 8);
596 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
598 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
599 bool force_disable_vdd);
601 intel_dp_pps_init(struct intel_dp *intel_dp);
603 static void pps_lock(struct intel_dp *intel_dp)
605 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
608 * See intel_power_sequencer_reset() why we need
609 * a power domain reference here.
611 intel_display_power_get(dev_priv,
612 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
614 mutex_lock(&dev_priv->pps_mutex);
617 static void pps_unlock(struct intel_dp *intel_dp)
619 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
621 mutex_unlock(&dev_priv->pps_mutex);
623 intel_display_power_put(dev_priv,
624 intel_aux_power_domain(dp_to_dig_port(intel_dp)));
628 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
630 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
631 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
632 enum pipe pipe = intel_dp->pps_pipe;
633 bool pll_enabled, release_cl_override = false;
634 enum dpio_phy phy = DPIO_PHY(pipe);
635 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
638 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
639 "skipping pipe %c power sequencer kick due to port %c being active\n",
640 pipe_name(pipe), port_name(intel_dig_port->base.port)))
643 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
644 pipe_name(pipe), port_name(intel_dig_port->base.port));
646 /* Preserve the BIOS-computed detected bit. This is
647 * supposed to be read-only.
649 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
650 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
651 DP |= DP_PORT_WIDTH(1);
652 DP |= DP_LINK_TRAIN_PAT_1;
654 if (IS_CHERRYVIEW(dev_priv))
655 DP |= DP_PIPE_SEL_CHV(pipe);
657 DP |= DP_PIPE_SEL(pipe);
659 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
662 * The DPLL for the pipe must be enabled for this to work.
663 * So enable temporarily it if it's not already enabled.
666 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
667 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
669 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
670 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
671 DRM_ERROR("Failed to force on pll for pipe %c!\n",
678 * Similar magic as in intel_dp_enable_port().
679 * We _must_ do this port enable + disable trick
680 * to make this power sequencer lock onto the port.
681 * Otherwise even VDD force bit won't work.
683 I915_WRITE(intel_dp->output_reg, DP);
684 POSTING_READ(intel_dp->output_reg);
686 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
687 POSTING_READ(intel_dp->output_reg);
689 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
690 POSTING_READ(intel_dp->output_reg);
693 vlv_force_pll_off(dev_priv, pipe);
695 if (release_cl_override)
696 chv_phy_powergate_ch(dev_priv, phy, ch, false);
700 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
702 struct intel_encoder *encoder;
703 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
706 * We don't have power sequencer currently.
707 * Pick one that's not used by other ports.
709 for_each_intel_dp(&dev_priv->drm, encoder) {
710 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
712 if (encoder->type == INTEL_OUTPUT_EDP) {
713 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
714 intel_dp->active_pipe != intel_dp->pps_pipe);
716 if (intel_dp->pps_pipe != INVALID_PIPE)
717 pipes &= ~(1 << intel_dp->pps_pipe);
719 WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
721 if (intel_dp->active_pipe != INVALID_PIPE)
722 pipes &= ~(1 << intel_dp->active_pipe);
729 return ffs(pipes) - 1;
733 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
735 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
736 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
739 lockdep_assert_held(&dev_priv->pps_mutex);
741 /* We should never land here with regular DP ports */
742 WARN_ON(!intel_dp_is_edp(intel_dp));
744 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
745 intel_dp->active_pipe != intel_dp->pps_pipe);
747 if (intel_dp->pps_pipe != INVALID_PIPE)
748 return intel_dp->pps_pipe;
750 pipe = vlv_find_free_pps(dev_priv);
753 * Didn't find one. This should not happen since there
754 * are two power sequencers and up to two eDP ports.
756 if (WARN_ON(pipe == INVALID_PIPE))
759 vlv_steal_power_sequencer(dev_priv, pipe);
760 intel_dp->pps_pipe = pipe;
762 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
763 pipe_name(intel_dp->pps_pipe),
764 port_name(intel_dig_port->base.port));
766 /* init power sequencer on this pipe and port */
767 intel_dp_init_panel_power_sequencer(intel_dp);
768 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
771 * Even vdd force doesn't work until we've made
772 * the power sequencer lock in on the port.
774 vlv_power_sequencer_kick(intel_dp);
776 return intel_dp->pps_pipe;
780 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
782 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
783 int backlight_controller = dev_priv->vbt.backlight.controller;
785 lockdep_assert_held(&dev_priv->pps_mutex);
787 /* We should never land here with regular DP ports */
788 WARN_ON(!intel_dp_is_edp(intel_dp));
790 if (!intel_dp->pps_reset)
791 return backlight_controller;
793 intel_dp->pps_reset = false;
796 * Only the HW needs to be reprogrammed, the SW state is fixed and
797 * has been setup during connector init.
799 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
801 return backlight_controller;
804 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
807 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
810 return I915_READ(PP_STATUS(pipe)) & PP_ON;
813 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
816 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
819 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
826 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
828 vlv_pipe_check pipe_check)
832 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
833 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
834 PANEL_PORT_SELECT_MASK;
836 if (port_sel != PANEL_PORT_SELECT_VLV(port))
839 if (!pipe_check(dev_priv, pipe))
849 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
851 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
852 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
853 enum port port = intel_dig_port->base.port;
855 lockdep_assert_held(&dev_priv->pps_mutex);
857 /* try to find a pipe with this port selected */
858 /* first pick one where the panel is on */
859 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
861 /* didn't find one? pick one where vdd is on */
862 if (intel_dp->pps_pipe == INVALID_PIPE)
863 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
864 vlv_pipe_has_vdd_on);
865 /* didn't find one? pick one with just the correct port */
866 if (intel_dp->pps_pipe == INVALID_PIPE)
867 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
870 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
871 if (intel_dp->pps_pipe == INVALID_PIPE) {
872 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
877 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
878 port_name(port), pipe_name(intel_dp->pps_pipe));
880 intel_dp_init_panel_power_sequencer(intel_dp);
881 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
884 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
886 struct intel_encoder *encoder;
888 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
889 !IS_GEN9_LP(dev_priv)))
893 * We can't grab pps_mutex here due to deadlock with power_domain
894 * mutex when power_domain functions are called while holding pps_mutex.
895 * That also means that in order to use pps_pipe the code needs to
896 * hold both a power domain reference and pps_mutex, and the power domain
897 * reference get/put must be done while _not_ holding pps_mutex.
898 * pps_{lock,unlock}() do these steps in the correct order, so one
899 * should use them always.
902 for_each_intel_dp(&dev_priv->drm, encoder) {
903 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
905 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
907 if (encoder->type != INTEL_OUTPUT_EDP)
910 if (IS_GEN9_LP(dev_priv))
911 intel_dp->pps_reset = true;
913 intel_dp->pps_pipe = INVALID_PIPE;
917 struct pps_registers {
925 static void intel_pps_get_registers(struct intel_dp *intel_dp,
926 struct pps_registers *regs)
928 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
931 memset(regs, 0, sizeof(*regs));
933 if (IS_GEN9_LP(dev_priv))
934 pps_idx = bxt_power_sequencer_idx(intel_dp);
935 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
936 pps_idx = vlv_power_sequencer_pipe(intel_dp);
938 regs->pp_ctrl = PP_CONTROL(pps_idx);
939 regs->pp_stat = PP_STATUS(pps_idx);
940 regs->pp_on = PP_ON_DELAYS(pps_idx);
941 regs->pp_off = PP_OFF_DELAYS(pps_idx);
942 if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
943 !HAS_PCH_ICP(dev_priv))
944 regs->pp_div = PP_DIVISOR(pps_idx);
948 _pp_ctrl_reg(struct intel_dp *intel_dp)
950 struct pps_registers regs;
952 intel_pps_get_registers(intel_dp, ®s);
958 _pp_stat_reg(struct intel_dp *intel_dp)
960 struct pps_registers regs;
962 intel_pps_get_registers(intel_dp, ®s);
967 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
968 This function only applicable when panel PM state is not to be tracked */
969 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
972 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
974 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
976 if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
981 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
982 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
983 i915_reg_t pp_ctrl_reg, pp_div_reg;
986 pp_ctrl_reg = PP_CONTROL(pipe);
987 pp_div_reg = PP_DIVISOR(pipe);
988 pp_div = I915_READ(pp_div_reg);
989 pp_div &= PP_REFERENCE_DIVIDER_MASK;
991 /* 0x1F write to PP_DIV_REG sets max cycle delay */
992 I915_WRITE(pp_div_reg, pp_div | 0x1F);
993 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
994 msleep(intel_dp->panel_power_cycle_delay);
997 pps_unlock(intel_dp);
1002 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1004 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1006 lockdep_assert_held(&dev_priv->pps_mutex);
1008 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1009 intel_dp->pps_pipe == INVALID_PIPE)
1012 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1015 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1017 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1019 lockdep_assert_held(&dev_priv->pps_mutex);
1021 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1022 intel_dp->pps_pipe == INVALID_PIPE)
1025 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1029 intel_dp_check_edp(struct intel_dp *intel_dp)
1031 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1033 if (!intel_dp_is_edp(intel_dp))
1036 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1037 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1038 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1039 I915_READ(_pp_stat_reg(intel_dp)),
1040 I915_READ(_pp_ctrl_reg(intel_dp)));
1045 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1047 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1048 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1052 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1053 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
1054 msecs_to_jiffies_timeout(10));
1056 DRM_ERROR("dp aux hw did not signal timeout!\n");
1062 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1064 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1070 * The clock divider is based off the hrawclk, and would like to run at
1071 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
1073 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1076 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1078 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1079 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1085 * The clock divider is based off the cdclk or PCH rawclk, and would
1086 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
1087 * divide by 2000 and use that
1089 if (dig_port->aux_ch == AUX_CH_A)
1090 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1092 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1095 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1097 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1098 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1100 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1101 /* Workaround for non-ULT HSW */
1109 return ilk_get_aux_clock_divider(intel_dp, index);
1112 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1115 * SKL doesn't need us to program the AUX clock divider (Hardware will
1116 * derive the clock from CDCLK automatically). We still implement the
1117 * get_aux_clock_divider vfunc to plug-in into the existing code.
1119 return index ? 0 : 1;
1122 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1124 uint32_t aux_clock_divider)
1126 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1127 struct drm_i915_private *dev_priv =
1128 to_i915(intel_dig_port->base.base.dev);
1129 uint32_t precharge, timeout;
1131 if (IS_GEN6(dev_priv))
1136 if (IS_BROADWELL(dev_priv))
1137 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1139 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1141 return DP_AUX_CH_CTL_SEND_BUSY |
1142 DP_AUX_CH_CTL_DONE |
1143 DP_AUX_CH_CTL_INTERRUPT |
1144 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1146 DP_AUX_CH_CTL_RECEIVE_ERROR |
1147 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1148 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1149 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1152 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1156 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1159 ret = DP_AUX_CH_CTL_SEND_BUSY |
1160 DP_AUX_CH_CTL_DONE |
1161 DP_AUX_CH_CTL_INTERRUPT |
1162 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1163 DP_AUX_CH_CTL_TIME_OUT_MAX |
1164 DP_AUX_CH_CTL_RECEIVE_ERROR |
1165 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1166 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1167 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1169 if (intel_dig_port->tc_type == TC_PORT_TBT)
1170 ret |= DP_AUX_CH_CTL_TBT_IO;
1176 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1177 const uint8_t *send, int send_bytes,
1178 uint8_t *recv, int recv_size,
1179 u32 aux_send_ctl_flags)
1181 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1182 struct drm_i915_private *dev_priv =
1183 to_i915(intel_dig_port->base.base.dev);
1184 i915_reg_t ch_ctl, ch_data[5];
1185 uint32_t aux_clock_divider;
1186 int i, ret, recv_bytes;
1191 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1192 for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1193 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1198 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1199 * In such cases we want to leave VDD enabled and it's up to upper layers
1200 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1203 vdd = edp_panel_vdd_on(intel_dp);
1205 /* dp aux is extremely sensitive to irq latency, hence request the
1206 * lowest possible wakeup latency and so prevent the cpu from going into
1207 * deep sleep states.
1209 pm_qos_update_request(&dev_priv->pm_qos, 0);
1211 intel_dp_check_edp(intel_dp);
1213 /* Try to wait for any previous AUX channel activity */
1214 for (try = 0; try < 3; try++) {
1215 status = I915_READ_NOTRACE(ch_ctl);
1216 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1222 static u32 last_status = -1;
1223 const u32 status = I915_READ(ch_ctl);
1225 if (status != last_status) {
1226 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1228 last_status = status;
1235 /* Only 5 data registers! */
1236 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1241 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1242 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1246 send_ctl |= aux_send_ctl_flags;
1248 /* Must try at least 3 times according to DP spec */
1249 for (try = 0; try < 5; try++) {
1250 /* Load the send data into the aux channel data registers */
1251 for (i = 0; i < send_bytes; i += 4)
1252 I915_WRITE(ch_data[i >> 2],
1253 intel_dp_pack_aux(send + i,
1256 /* Send the command and wait for it to complete */
1257 I915_WRITE(ch_ctl, send_ctl);
1259 status = intel_dp_aux_wait_done(intel_dp);
1261 /* Clear done status and any errors */
1264 DP_AUX_CH_CTL_DONE |
1265 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1266 DP_AUX_CH_CTL_RECEIVE_ERROR);
1268 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1269 * 400us delay required for errors and timeouts
1270 * Timeout errors from the HW already meet this
1271 * requirement so skip to next iteration
1273 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1276 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1277 usleep_range(400, 500);
1280 if (status & DP_AUX_CH_CTL_DONE)
1285 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1286 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1292 /* Check for timeout or receive error.
1293 * Timeouts occur when the sink is not connected
1295 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1296 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1301 /* Timeouts occur when the device isn't connected, so they're
1302 * "normal" -- don't fill the kernel log with these */
1303 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1304 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1309 /* Unload any bytes sent back from the other side */
1310 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1311 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1314 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1315 * We have no idea of what happened so we return -EBUSY so
1316 * drm layer takes care for the necessary retries.
1318 if (recv_bytes == 0 || recv_bytes > 20) {
1319 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1325 if (recv_bytes > recv_size)
1326 recv_bytes = recv_size;
1328 for (i = 0; i < recv_bytes; i += 4)
1329 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1330 recv + i, recv_bytes - i);
1334 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1337 edp_panel_vdd_off(intel_dp, false);
1339 pps_unlock(intel_dp);
1344 #define BARE_ADDRESS_SIZE 3
1345 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1348 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1349 const struct drm_dp_aux_msg *msg)
1351 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1352 txbuf[1] = (msg->address >> 8) & 0xff;
1353 txbuf[2] = msg->address & 0xff;
1354 txbuf[3] = msg->size - 1;
1358 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1360 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1361 uint8_t txbuf[20], rxbuf[20];
1362 size_t txsize, rxsize;
1365 intel_dp_aux_header(txbuf, msg);
1367 switch (msg->request & ~DP_AUX_I2C_MOT) {
1368 case DP_AUX_NATIVE_WRITE:
1369 case DP_AUX_I2C_WRITE:
1370 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1371 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1372 rxsize = 2; /* 0 or 1 data bytes */
1374 if (WARN_ON(txsize > 20))
1377 WARN_ON(!msg->buffer != !msg->size);
1380 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1382 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1385 msg->reply = rxbuf[0] >> 4;
1388 /* Number of bytes written in a short write. */
1389 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1391 /* Return payload size. */
1397 case DP_AUX_NATIVE_READ:
1398 case DP_AUX_I2C_READ:
1399 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1400 rxsize = msg->size + 1;
1402 if (WARN_ON(rxsize > 20))
1405 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1408 msg->reply = rxbuf[0] >> 4;
1410 * Assume happy day, and copy the data. The caller is
1411 * expected to check msg->reply before touching it.
1413 * Return payload size.
1416 memcpy(msg->buffer, rxbuf + 1, ret);
1429 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1431 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1432 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1433 enum aux_ch aux_ch = dig_port->aux_ch;
1439 return DP_AUX_CH_CTL(aux_ch);
1441 MISSING_CASE(aux_ch);
1442 return DP_AUX_CH_CTL(AUX_CH_B);
1446 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1448 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1449 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1450 enum aux_ch aux_ch = dig_port->aux_ch;
1456 return DP_AUX_CH_DATA(aux_ch, index);
1458 MISSING_CASE(aux_ch);
1459 return DP_AUX_CH_DATA(AUX_CH_B, index);
1463 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1465 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1466 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1467 enum aux_ch aux_ch = dig_port->aux_ch;
1471 return DP_AUX_CH_CTL(aux_ch);
1475 return PCH_DP_AUX_CH_CTL(aux_ch);
1477 MISSING_CASE(aux_ch);
1478 return DP_AUX_CH_CTL(AUX_CH_A);
1482 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1484 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1485 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1486 enum aux_ch aux_ch = dig_port->aux_ch;
1490 return DP_AUX_CH_DATA(aux_ch, index);
1494 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1496 MISSING_CASE(aux_ch);
1497 return DP_AUX_CH_DATA(AUX_CH_A, index);
1501 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1503 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1504 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1505 enum aux_ch aux_ch = dig_port->aux_ch;
1514 return DP_AUX_CH_CTL(aux_ch);
1516 MISSING_CASE(aux_ch);
1517 return DP_AUX_CH_CTL(AUX_CH_A);
1521 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1523 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1524 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1525 enum aux_ch aux_ch = dig_port->aux_ch;
1534 return DP_AUX_CH_DATA(aux_ch, index);
1536 MISSING_CASE(aux_ch);
1537 return DP_AUX_CH_DATA(AUX_CH_A, index);
1542 intel_dp_aux_fini(struct intel_dp *intel_dp)
1544 kfree(intel_dp->aux.name);
1548 intel_dp_aux_init(struct intel_dp *intel_dp)
1550 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1551 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1552 struct intel_encoder *encoder = &dig_port->base;
1554 if (INTEL_GEN(dev_priv) >= 9) {
1555 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1556 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1557 } else if (HAS_PCH_SPLIT(dev_priv)) {
1558 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1559 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1561 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1562 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1565 if (INTEL_GEN(dev_priv) >= 9)
1566 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1567 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1568 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1569 else if (HAS_PCH_SPLIT(dev_priv))
1570 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1572 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1574 if (INTEL_GEN(dev_priv) >= 9)
1575 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1577 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1579 drm_dp_aux_init(&intel_dp->aux);
1581 /* Failure to allocate our preferred name is not critical */
1582 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1583 port_name(encoder->port));
1584 intel_dp->aux.transfer = intel_dp_aux_transfer;
1587 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1589 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1591 return max_rate >= 540000;
1594 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1596 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1598 return max_rate >= 810000;
1602 intel_dp_set_clock(struct intel_encoder *encoder,
1603 struct intel_crtc_state *pipe_config)
1605 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1606 const struct dp_link_dpll *divisor = NULL;
1609 if (IS_G4X(dev_priv)) {
1611 count = ARRAY_SIZE(g4x_dpll);
1612 } else if (HAS_PCH_SPLIT(dev_priv)) {
1614 count = ARRAY_SIZE(pch_dpll);
1615 } else if (IS_CHERRYVIEW(dev_priv)) {
1617 count = ARRAY_SIZE(chv_dpll);
1618 } else if (IS_VALLEYVIEW(dev_priv)) {
1620 count = ARRAY_SIZE(vlv_dpll);
1623 if (divisor && count) {
1624 for (i = 0; i < count; i++) {
1625 if (pipe_config->port_clock == divisor[i].clock) {
1626 pipe_config->dpll = divisor[i].dpll;
1627 pipe_config->clock_set = true;
1634 static void snprintf_int_array(char *str, size_t len,
1635 const int *array, int nelem)
1641 for (i = 0; i < nelem; i++) {
1642 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1650 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1652 char str[128]; /* FIXME: too big for stack? */
1654 if ((drm_debug & DRM_UT_KMS) == 0)
1657 snprintf_int_array(str, sizeof(str),
1658 intel_dp->source_rates, intel_dp->num_source_rates);
1659 DRM_DEBUG_KMS("source rates: %s\n", str);
1661 snprintf_int_array(str, sizeof(str),
1662 intel_dp->sink_rates, intel_dp->num_sink_rates);
1663 DRM_DEBUG_KMS("sink rates: %s\n", str);
1665 snprintf_int_array(str, sizeof(str),
1666 intel_dp->common_rates, intel_dp->num_common_rates);
1667 DRM_DEBUG_KMS("common rates: %s\n", str);
1671 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1675 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1676 if (WARN_ON(len <= 0))
1679 return intel_dp->common_rates[len - 1];
1682 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1684 int i = intel_dp_rate_index(intel_dp->sink_rates,
1685 intel_dp->num_sink_rates, rate);
1693 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1694 uint8_t *link_bw, uint8_t *rate_select)
1696 /* eDP 1.4 rate select method. */
1697 if (intel_dp->use_rate_select) {
1700 intel_dp_rate_select(intel_dp, port_clock);
1702 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1707 struct link_config_limits {
1708 int min_clock, max_clock;
1709 int min_lane_count, max_lane_count;
1710 int min_bpp, max_bpp;
1713 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1714 const struct intel_crtc_state *pipe_config)
1716 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1718 return INTEL_GEN(dev_priv) >= 11 &&
1719 pipe_config->cpu_transcoder != TRANSCODER_A;
1722 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1723 const struct intel_crtc_state *pipe_config)
1725 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1726 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1729 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1730 const struct intel_crtc_state *pipe_config)
1732 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1734 return INTEL_GEN(dev_priv) >= 10 &&
1735 pipe_config->cpu_transcoder != TRANSCODER_A;
1738 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1739 const struct intel_crtc_state *pipe_config)
1741 if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1744 return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1745 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1748 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1749 struct intel_crtc_state *pipe_config)
1751 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1752 struct intel_connector *intel_connector = intel_dp->attached_connector;
1755 bpp = pipe_config->pipe_bpp;
1756 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1759 bpp = min(bpp, 3*bpc);
1761 if (intel_dp_is_edp(intel_dp)) {
1762 /* Get bpp from vbt only for panels that dont have bpp in edid */
1763 if (intel_connector->base.display_info.bpc == 0 &&
1764 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1765 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1766 dev_priv->vbt.edp.bpp);
1767 bpp = dev_priv->vbt.edp.bpp;
1774 /* Adjust link config limits based on compliance test requests. */
1776 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1777 struct intel_crtc_state *pipe_config,
1778 struct link_config_limits *limits)
1780 /* For DP Compliance we override the computed bpp for the pipe */
1781 if (intel_dp->compliance.test_data.bpc != 0) {
1782 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1784 limits->min_bpp = limits->max_bpp = bpp;
1785 pipe_config->dither_force_disable = bpp == 6 * 3;
1787 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1790 /* Use values requested by Compliance Test Request */
1791 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1794 /* Validate the compliance test data since max values
1795 * might have changed due to link train fallback.
1797 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1798 intel_dp->compliance.test_lane_count)) {
1799 index = intel_dp_rate_index(intel_dp->common_rates,
1800 intel_dp->num_common_rates,
1801 intel_dp->compliance.test_link_rate);
1803 limits->min_clock = limits->max_clock = index;
1804 limits->min_lane_count = limits->max_lane_count =
1805 intel_dp->compliance.test_lane_count;
1810 /* Optimize link config in order: max bpp, min clock, min lanes */
1812 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1813 struct intel_crtc_state *pipe_config,
1814 const struct link_config_limits *limits)
1816 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1817 int bpp, clock, lane_count;
1818 int mode_rate, link_clock, link_avail;
1820 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1821 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1824 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1825 for (lane_count = limits->min_lane_count;
1826 lane_count <= limits->max_lane_count;
1828 link_clock = intel_dp->common_rates[clock];
1829 link_avail = intel_dp_max_data_rate(link_clock,
1832 if (mode_rate <= link_avail) {
1833 pipe_config->lane_count = lane_count;
1834 pipe_config->pipe_bpp = bpp;
1835 pipe_config->port_clock = link_clock;
1846 /* Optimize link config in order: max bpp, min lanes, min clock */
1848 intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
1849 struct intel_crtc_state *pipe_config,
1850 const struct link_config_limits *limits)
1852 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1853 int bpp, clock, lane_count;
1854 int mode_rate, link_clock, link_avail;
1856 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1857 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1860 for (lane_count = limits->min_lane_count;
1861 lane_count <= limits->max_lane_count;
1863 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1864 link_clock = intel_dp->common_rates[clock];
1865 link_avail = intel_dp_max_data_rate(link_clock,
1868 if (mode_rate <= link_avail) {
1869 pipe_config->lane_count = lane_count;
1870 pipe_config->pipe_bpp = bpp;
1871 pipe_config->port_clock = link_clock;
1882 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1885 u8 dsc_bpc[3] = {0};
1887 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1889 for (i = 0; i < num_bpc; i++) {
1890 if (dsc_max_bpc >= dsc_bpc[i])
1891 return dsc_bpc[i] * 3;
1897 static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1898 struct intel_crtc_state *pipe_config,
1899 struct drm_connector_state *conn_state,
1900 struct link_config_limits *limits)
1902 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1903 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1904 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1908 if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1911 dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
1912 conn_state->max_requested_bpc);
1914 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1915 if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
1916 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
1921 * For now enable DSC for max bpp, max link rate, max lane count.
1922 * Optimize this later for the minimum possible link rate/lane count
1923 * with DSC enabled for the requested mode.
1925 pipe_config->pipe_bpp = pipe_bpp;
1926 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1927 pipe_config->lane_count = limits->max_lane_count;
1929 if (intel_dp_is_edp(intel_dp)) {
1930 pipe_config->dsc_params.compressed_bpp =
1931 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1932 pipe_config->pipe_bpp);
1933 pipe_config->dsc_params.slice_count =
1934 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1937 u16 dsc_max_output_bpp;
1938 u8 dsc_dp_slice_count;
1940 dsc_max_output_bpp =
1941 intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
1942 pipe_config->lane_count,
1943 adjusted_mode->crtc_clock,
1944 adjusted_mode->crtc_hdisplay);
1945 dsc_dp_slice_count =
1946 intel_dp_dsc_get_slice_count(intel_dp,
1947 adjusted_mode->crtc_clock,
1948 adjusted_mode->crtc_hdisplay);
1949 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1950 DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
1953 pipe_config->dsc_params.compressed_bpp = min_t(u16,
1954 dsc_max_output_bpp >> 4,
1955 pipe_config->pipe_bpp);
1956 pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
1959 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1960 * is greater than the maximum Cdclock and if slice count is even
1961 * then we need to use 2 VDSC instances.
1963 if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
1964 if (pipe_config->dsc_params.slice_count > 1) {
1965 pipe_config->dsc_params.dsc_split = true;
1967 DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
1971 if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
1972 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
1973 "Compressed BPP = %d\n",
1974 pipe_config->pipe_bpp,
1975 pipe_config->dsc_params.compressed_bpp);
1978 pipe_config->dsc_params.compression_enable = true;
1979 DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
1980 "Compressed Bpp = %d Slice Count = %d\n",
1981 pipe_config->pipe_bpp,
1982 pipe_config->dsc_params.compressed_bpp,
1983 pipe_config->dsc_params.slice_count);
1989 intel_dp_compute_link_config(struct intel_encoder *encoder,
1990 struct intel_crtc_state *pipe_config,
1991 struct drm_connector_state *conn_state)
1993 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1994 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1995 struct link_config_limits limits;
1999 common_len = intel_dp_common_len_rate_limit(intel_dp,
2000 intel_dp->max_link_rate);
2002 /* No common link rates between source and sink */
2003 WARN_ON(common_len <= 0);
2005 limits.min_clock = 0;
2006 limits.max_clock = common_len - 1;
2008 limits.min_lane_count = 1;
2009 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2011 limits.min_bpp = 6 * 3;
2012 limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2014 if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
2016 * Use the maximum clock and number of lanes the eDP panel
2017 * advertizes being capable of. The eDP 1.3 and earlier panels
2018 * are generally designed to support only a single clock and
2019 * lane configuration, and typically these values correspond to
2020 * the native resolution of the panel. With eDP 1.4 rate select
2021 * and DSC, this is decreasingly the case, and we need to be
2022 * able to select less than maximum link config.
2024 limits.min_lane_count = limits.max_lane_count;
2025 limits.min_clock = limits.max_clock;
2028 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2030 DRM_DEBUG_KMS("DP link computation with max lane count %i "
2031 "max rate %d max bpp %d pixel clock %iKHz\n",
2032 limits.max_lane_count,
2033 intel_dp->common_rates[limits.max_clock],
2034 limits.max_bpp, adjusted_mode->crtc_clock);
2036 if (intel_dp_is_edp(intel_dp))
2038 * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
2039 * section A.1: "It is recommended that the minimum number of
2040 * lanes be used, using the minimum link rate allowed for that
2041 * lane configuration."
2043 * Note that we use the max clock and lane count for eDP 1.3 and
2044 * earlier, and fast vs. wide is irrelevant.
2046 ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config,
2049 /* Optimize for slow and wide. */
2050 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2053 /* enable compression if the mode doesn't fit available BW */
2055 if (!intel_dp_dsc_compute_config(intel_dp, pipe_config,
2056 conn_state, &limits))
2060 if (pipe_config->dsc_params.compression_enable) {
2061 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2062 pipe_config->lane_count, pipe_config->port_clock,
2063 pipe_config->pipe_bpp,
2064 pipe_config->dsc_params.compressed_bpp);
2066 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2067 intel_dp_link_required(adjusted_mode->crtc_clock,
2068 pipe_config->dsc_params.compressed_bpp),
2069 intel_dp_max_data_rate(pipe_config->port_clock,
2070 pipe_config->lane_count));
2072 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2073 pipe_config->lane_count, pipe_config->port_clock,
2074 pipe_config->pipe_bpp);
2076 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2077 intel_dp_link_required(adjusted_mode->crtc_clock,
2078 pipe_config->pipe_bpp),
2079 intel_dp_max_data_rate(pipe_config->port_clock,
2080 pipe_config->lane_count));
2086 intel_dp_compute_config(struct intel_encoder *encoder,
2087 struct intel_crtc_state *pipe_config,
2088 struct drm_connector_state *conn_state)
2090 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2091 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2092 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2093 struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2094 enum port port = encoder->port;
2095 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2096 struct intel_connector *intel_connector = intel_dp->attached_connector;
2097 struct intel_digital_connector_state *intel_conn_state =
2098 to_intel_digital_connector_state(conn_state);
2099 bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2100 DP_DPCD_QUIRK_CONSTANT_N);
2102 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2103 pipe_config->has_pch_encoder = true;
2105 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2107 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2109 pipe_config->has_drrs = false;
2110 if (IS_G4X(dev_priv) || port == PORT_A)
2111 pipe_config->has_audio = false;
2112 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2113 pipe_config->has_audio = intel_dp->has_audio;
2115 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2117 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2118 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2121 if (INTEL_GEN(dev_priv) >= 9) {
2124 ret = skl_update_scaler_crtc(pipe_config);
2129 if (HAS_GMCH_DISPLAY(dev_priv))
2130 intel_gmch_panel_fitting(intel_crtc, pipe_config,
2131 conn_state->scaling_mode);
2133 intel_pch_panel_fitting(intel_crtc, pipe_config,
2134 conn_state->scaling_mode);
2137 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2140 if (HAS_GMCH_DISPLAY(dev_priv) &&
2141 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2144 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2147 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2148 intel_dp_supports_fec(intel_dp, pipe_config);
2150 if (!intel_dp_compute_link_config(encoder, pipe_config, conn_state))
2153 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2156 * CEA-861-E - 5.1 Default Encoding Parameters
2157 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2159 pipe_config->limited_color_range =
2160 pipe_config->pipe_bpp != 18 &&
2161 drm_default_rgb_quant_range(adjusted_mode) ==
2162 HDMI_QUANTIZATION_RANGE_LIMITED;
2164 pipe_config->limited_color_range =
2165 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2168 if (!pipe_config->dsc_params.compression_enable)
2169 intel_link_compute_m_n(pipe_config->pipe_bpp,
2170 pipe_config->lane_count,
2171 adjusted_mode->crtc_clock,
2172 pipe_config->port_clock,
2173 &pipe_config->dp_m_n,
2176 intel_link_compute_m_n(pipe_config->dsc_params.compressed_bpp,
2177 pipe_config->lane_count,
2178 adjusted_mode->crtc_clock,
2179 pipe_config->port_clock,
2180 &pipe_config->dp_m_n,
2183 if (intel_connector->panel.downclock_mode != NULL &&
2184 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2185 pipe_config->has_drrs = true;
2186 intel_link_compute_m_n(pipe_config->pipe_bpp,
2187 pipe_config->lane_count,
2188 intel_connector->panel.downclock_mode->clock,
2189 pipe_config->port_clock,
2190 &pipe_config->dp_m2_n2,
2194 if (!HAS_DDI(dev_priv))
2195 intel_dp_set_clock(encoder, pipe_config);
2197 intel_psr_compute_config(intel_dp, pipe_config);
2202 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2203 int link_rate, uint8_t lane_count,
2206 intel_dp->link_trained = false;
2207 intel_dp->link_rate = link_rate;
2208 intel_dp->lane_count = lane_count;
2209 intel_dp->link_mst = link_mst;
2212 static void intel_dp_prepare(struct intel_encoder *encoder,
2213 const struct intel_crtc_state *pipe_config)
2215 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2216 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2217 enum port port = encoder->port;
2218 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2219 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2221 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2222 pipe_config->lane_count,
2223 intel_crtc_has_type(pipe_config,
2224 INTEL_OUTPUT_DP_MST));
2227 * There are four kinds of DP registers:
2234 * IBX PCH and CPU are the same for almost everything,
2235 * except that the CPU DP PLL is configured in this
2238 * CPT PCH is quite different, having many bits moved
2239 * to the TRANS_DP_CTL register instead. That
2240 * configuration happens (oddly) in ironlake_pch_enable
2243 /* Preserve the BIOS-computed detected bit. This is
2244 * supposed to be read-only.
2246 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2248 /* Handle DP bits in common between all three register formats */
2249 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2250 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2252 /* Split out the IBX/CPU vs CPT settings */
2254 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2255 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2256 intel_dp->DP |= DP_SYNC_HS_HIGH;
2257 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2258 intel_dp->DP |= DP_SYNC_VS_HIGH;
2259 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2261 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2262 intel_dp->DP |= DP_ENHANCED_FRAMING;
2264 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2265 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2268 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2270 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2271 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2272 trans_dp |= TRANS_DP_ENH_FRAMING;
2274 trans_dp &= ~TRANS_DP_ENH_FRAMING;
2275 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2277 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2278 intel_dp->DP |= DP_COLOR_RANGE_16_235;
2280 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2281 intel_dp->DP |= DP_SYNC_HS_HIGH;
2282 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2283 intel_dp->DP |= DP_SYNC_VS_HIGH;
2284 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2286 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2287 intel_dp->DP |= DP_ENHANCED_FRAMING;
2289 if (IS_CHERRYVIEW(dev_priv))
2290 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2292 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2296 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2297 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
2299 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2300 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
2302 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2303 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
2305 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2307 static void wait_panel_status(struct intel_dp *intel_dp,
2311 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2312 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2314 lockdep_assert_held(&dev_priv->pps_mutex);
2316 intel_pps_verify_state(intel_dp);
2318 pp_stat_reg = _pp_stat_reg(intel_dp);
2319 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2321 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2323 I915_READ(pp_stat_reg),
2324 I915_READ(pp_ctrl_reg));
2326 if (intel_wait_for_register(dev_priv,
2327 pp_stat_reg, mask, value,
2329 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2330 I915_READ(pp_stat_reg),
2331 I915_READ(pp_ctrl_reg));
2333 DRM_DEBUG_KMS("Wait complete\n");
2336 static void wait_panel_on(struct intel_dp *intel_dp)
2338 DRM_DEBUG_KMS("Wait for panel power on\n");
2339 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2342 static void wait_panel_off(struct intel_dp *intel_dp)
2344 DRM_DEBUG_KMS("Wait for panel power off time\n");
2345 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2348 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2350 ktime_t panel_power_on_time;
2351 s64 panel_power_off_duration;
2353 DRM_DEBUG_KMS("Wait for panel power cycle\n");
2355 /* take the difference of currrent time and panel power off time
2356 * and then make panel wait for t11_t12 if needed. */
2357 panel_power_on_time = ktime_get_boottime();
2358 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2360 /* When we disable the VDD override bit last we have to do the manual
2362 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2363 wait_remaining_ms_from_jiffies(jiffies,
2364 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2366 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2369 static void wait_backlight_on(struct intel_dp *intel_dp)
2371 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2372 intel_dp->backlight_on_delay);
2375 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2377 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2378 intel_dp->backlight_off_delay);
2381 /* Read the current pp_control value, unlocking the register if it
2385 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2387 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2390 lockdep_assert_held(&dev_priv->pps_mutex);
2392 control = I915_READ(_pp_ctrl_reg(intel_dp));
2393 if (WARN_ON(!HAS_DDI(dev_priv) &&
2394 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2395 control &= ~PANEL_UNLOCK_MASK;
2396 control |= PANEL_UNLOCK_REGS;
2402 * Must be paired with edp_panel_vdd_off().
2403 * Must hold pps_mutex around the whole on/off sequence.
2404 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2406 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2408 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2409 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2411 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2412 bool need_to_disable = !intel_dp->want_panel_vdd;
2414 lockdep_assert_held(&dev_priv->pps_mutex);
2416 if (!intel_dp_is_edp(intel_dp))
2419 cancel_delayed_work(&intel_dp->panel_vdd_work);
2420 intel_dp->want_panel_vdd = true;
2422 if (edp_have_panel_vdd(intel_dp))
2423 return need_to_disable;
2425 intel_display_power_get(dev_priv,
2426 intel_aux_power_domain(intel_dig_port));
2428 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2429 port_name(intel_dig_port->base.port));
2431 if (!edp_have_panel_power(intel_dp))
2432 wait_panel_power_cycle(intel_dp);
2434 pp = ironlake_get_pp_control(intel_dp);
2435 pp |= EDP_FORCE_VDD;
2437 pp_stat_reg = _pp_stat_reg(intel_dp);
2438 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2440 I915_WRITE(pp_ctrl_reg, pp);
2441 POSTING_READ(pp_ctrl_reg);
2442 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2443 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2445 * If the panel wasn't on, delay before accessing aux channel
2447 if (!edp_have_panel_power(intel_dp)) {
2448 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2449 port_name(intel_dig_port->base.port));
2450 msleep(intel_dp->panel_power_up_delay);
2453 return need_to_disable;
2457 * Must be paired with intel_edp_panel_vdd_off() or
2458 * intel_edp_panel_off().
2459 * Nested calls to these functions are not allowed since
2460 * we drop the lock. Caller must use some higher level
2461 * locking to prevent nested calls from other threads.
2463 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2467 if (!intel_dp_is_edp(intel_dp))
2471 vdd = edp_panel_vdd_on(intel_dp);
2472 pps_unlock(intel_dp);
2474 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2475 port_name(dp_to_dig_port(intel_dp)->base.port));
2478 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2480 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2481 struct intel_digital_port *intel_dig_port =
2482 dp_to_dig_port(intel_dp);
2484 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2486 lockdep_assert_held(&dev_priv->pps_mutex);
2488 WARN_ON(intel_dp->want_panel_vdd);
2490 if (!edp_have_panel_vdd(intel_dp))
2493 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2494 port_name(intel_dig_port->base.port));
2496 pp = ironlake_get_pp_control(intel_dp);
2497 pp &= ~EDP_FORCE_VDD;
2499 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2500 pp_stat_reg = _pp_stat_reg(intel_dp);
2502 I915_WRITE(pp_ctrl_reg, pp);
2503 POSTING_READ(pp_ctrl_reg);
2505 /* Make sure sequencer is idle before allowing subsequent activity */
2506 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2507 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2509 if ((pp & PANEL_POWER_ON) == 0)
2510 intel_dp->panel_power_off_time = ktime_get_boottime();
2512 intel_display_power_put(dev_priv,
2513 intel_aux_power_domain(intel_dig_port));
2516 static void edp_panel_vdd_work(struct work_struct *__work)
2518 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2519 struct intel_dp, panel_vdd_work);
2522 if (!intel_dp->want_panel_vdd)
2523 edp_panel_vdd_off_sync(intel_dp);
2524 pps_unlock(intel_dp);
2527 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2529 unsigned long delay;
2532 * Queue the timer to fire a long time from now (relative to the power
2533 * down delay) to keep the panel power up across a sequence of
2536 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2537 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2541 * Must be paired with edp_panel_vdd_on().
2542 * Must hold pps_mutex around the whole on/off sequence.
2543 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2545 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2547 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2549 lockdep_assert_held(&dev_priv->pps_mutex);
2551 if (!intel_dp_is_edp(intel_dp))
2554 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2555 port_name(dp_to_dig_port(intel_dp)->base.port));
2557 intel_dp->want_panel_vdd = false;
2560 edp_panel_vdd_off_sync(intel_dp);
2562 edp_panel_vdd_schedule_off(intel_dp);
2565 static void edp_panel_on(struct intel_dp *intel_dp)
2567 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2569 i915_reg_t pp_ctrl_reg;
2571 lockdep_assert_held(&dev_priv->pps_mutex);
2573 if (!intel_dp_is_edp(intel_dp))
2576 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2577 port_name(dp_to_dig_port(intel_dp)->base.port));
2579 if (WARN(edp_have_panel_power(intel_dp),
2580 "eDP port %c panel power already on\n",
2581 port_name(dp_to_dig_port(intel_dp)->base.port)))
2584 wait_panel_power_cycle(intel_dp);
2586 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2587 pp = ironlake_get_pp_control(intel_dp);
2588 if (IS_GEN5(dev_priv)) {
2589 /* ILK workaround: disable reset around power sequence */
2590 pp &= ~PANEL_POWER_RESET;
2591 I915_WRITE(pp_ctrl_reg, pp);
2592 POSTING_READ(pp_ctrl_reg);
2595 pp |= PANEL_POWER_ON;
2596 if (!IS_GEN5(dev_priv))
2597 pp |= PANEL_POWER_RESET;
2599 I915_WRITE(pp_ctrl_reg, pp);
2600 POSTING_READ(pp_ctrl_reg);
2602 wait_panel_on(intel_dp);
2603 intel_dp->last_power_on = jiffies;
2605 if (IS_GEN5(dev_priv)) {
2606 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2607 I915_WRITE(pp_ctrl_reg, pp);
2608 POSTING_READ(pp_ctrl_reg);
2612 void intel_edp_panel_on(struct intel_dp *intel_dp)
2614 if (!intel_dp_is_edp(intel_dp))
2618 edp_panel_on(intel_dp);
2619 pps_unlock(intel_dp);
2623 static void edp_panel_off(struct intel_dp *intel_dp)
2625 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2626 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2628 i915_reg_t pp_ctrl_reg;
2630 lockdep_assert_held(&dev_priv->pps_mutex);
2632 if (!intel_dp_is_edp(intel_dp))
2635 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2636 port_name(dig_port->base.port));
2638 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2639 port_name(dig_port->base.port));
2641 pp = ironlake_get_pp_control(intel_dp);
2642 /* We need to switch off panel power _and_ force vdd, for otherwise some
2643 * panels get very unhappy and cease to work. */
2644 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2647 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2649 intel_dp->want_panel_vdd = false;
2651 I915_WRITE(pp_ctrl_reg, pp);
2652 POSTING_READ(pp_ctrl_reg);
2654 wait_panel_off(intel_dp);
2655 intel_dp->panel_power_off_time = ktime_get_boottime();
2657 /* We got a reference when we enabled the VDD. */
2658 intel_display_power_put(dev_priv, intel_aux_power_domain(dig_port));
2661 void intel_edp_panel_off(struct intel_dp *intel_dp)
2663 if (!intel_dp_is_edp(intel_dp))
2667 edp_panel_off(intel_dp);
2668 pps_unlock(intel_dp);
2671 /* Enable backlight in the panel power control. */
2672 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2674 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2676 i915_reg_t pp_ctrl_reg;
2679 * If we enable the backlight right away following a panel power
2680 * on, we may see slight flicker as the panel syncs with the eDP
2681 * link. So delay a bit to make sure the image is solid before
2682 * allowing it to appear.
2684 wait_backlight_on(intel_dp);
2688 pp = ironlake_get_pp_control(intel_dp);
2689 pp |= EDP_BLC_ENABLE;
2691 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2693 I915_WRITE(pp_ctrl_reg, pp);
2694 POSTING_READ(pp_ctrl_reg);
2696 pps_unlock(intel_dp);
2699 /* Enable backlight PWM and backlight PP control. */
2700 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2701 const struct drm_connector_state *conn_state)
2703 struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2705 if (!intel_dp_is_edp(intel_dp))
2708 DRM_DEBUG_KMS("\n");
2710 intel_panel_enable_backlight(crtc_state, conn_state);
2711 _intel_edp_backlight_on(intel_dp);
2714 /* Disable backlight in the panel power control. */
2715 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2717 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2719 i915_reg_t pp_ctrl_reg;
2721 if (!intel_dp_is_edp(intel_dp))
2726 pp = ironlake_get_pp_control(intel_dp);
2727 pp &= ~EDP_BLC_ENABLE;
2729 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2731 I915_WRITE(pp_ctrl_reg, pp);
2732 POSTING_READ(pp_ctrl_reg);
2734 pps_unlock(intel_dp);
2736 intel_dp->last_backlight_off = jiffies;
2737 edp_wait_backlight_off(intel_dp);
2740 /* Disable backlight PP control and backlight PWM. */
2741 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2743 struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2745 if (!intel_dp_is_edp(intel_dp))
2748 DRM_DEBUG_KMS("\n");
2750 _intel_edp_backlight_off(intel_dp);
2751 intel_panel_disable_backlight(old_conn_state);
2755 * Hook for controlling the panel power control backlight through the bl_power
2756 * sysfs attribute. Take care to handle multiple calls.
2758 static void intel_edp_backlight_power(struct intel_connector *connector,
2761 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2765 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2766 pps_unlock(intel_dp);
2768 if (is_enabled == enable)
2771 DRM_DEBUG_KMS("panel power control backlight %s\n",
2772 enable ? "enable" : "disable");
2775 _intel_edp_backlight_on(intel_dp);
2777 _intel_edp_backlight_off(intel_dp);
2780 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2782 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2783 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2784 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2786 I915_STATE_WARN(cur_state != state,
2787 "DP port %c state assertion failure (expected %s, current %s)\n",
2788 port_name(dig_port->base.port),
2789 onoff(state), onoff(cur_state));
2791 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2793 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2795 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2797 I915_STATE_WARN(cur_state != state,
2798 "eDP PLL state assertion failure (expected %s, current %s)\n",
2799 onoff(state), onoff(cur_state));
2801 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2802 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2804 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2805 const struct intel_crtc_state *pipe_config)
2807 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2808 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2810 assert_pipe_disabled(dev_priv, crtc->pipe);
2811 assert_dp_port_disabled(intel_dp);
2812 assert_edp_pll_disabled(dev_priv);
2814 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2815 pipe_config->port_clock);
2817 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2819 if (pipe_config->port_clock == 162000)
2820 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2822 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2824 I915_WRITE(DP_A, intel_dp->DP);
2829 * [DevILK] Work around required when enabling DP PLL
2830 * while a pipe is enabled going to FDI:
2831 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2832 * 2. Program DP PLL enable
2834 if (IS_GEN5(dev_priv))
2835 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2837 intel_dp->DP |= DP_PLL_ENABLE;
2839 I915_WRITE(DP_A, intel_dp->DP);
2844 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2845 const struct intel_crtc_state *old_crtc_state)
2847 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2848 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2850 assert_pipe_disabled(dev_priv, crtc->pipe);
2851 assert_dp_port_disabled(intel_dp);
2852 assert_edp_pll_enabled(dev_priv);
2854 DRM_DEBUG_KMS("disabling eDP PLL\n");
2856 intel_dp->DP &= ~DP_PLL_ENABLE;
2858 I915_WRITE(DP_A, intel_dp->DP);
2863 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2866 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2867 * be capable of signalling downstream hpd with a long pulse.
2868 * Whether or not that means D3 is safe to use is not clear,
2869 * but let's assume so until proven otherwise.
2871 * FIXME should really check all downstream ports...
2873 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2874 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2875 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2878 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2879 const struct intel_crtc_state *crtc_state,
2884 if (!crtc_state->dsc_params.compression_enable)
2887 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2888 enable ? DP_DECOMPRESSION_EN : 0);
2890 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
2891 enable ? "enable" : "disable");
2894 /* If the sink supports it, try to set the power state appropriately */
2895 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2899 /* Should have a valid DPCD by this point */
2900 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2903 if (mode != DRM_MODE_DPMS_ON) {
2904 if (downstream_hpd_needs_d0(intel_dp))
2907 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2910 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2913 * When turning on, we need to retry for 1ms to give the sink
2916 for (i = 0; i < 3; i++) {
2917 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2924 if (ret == 1 && lspcon->active)
2925 lspcon_wait_pcon_mode(lspcon);
2929 DRM_DEBUG_KMS("failed to %s sink power state\n",
2930 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2933 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2934 enum port port, enum pipe *pipe)
2938 for_each_pipe(dev_priv, p) {
2939 u32 val = I915_READ(TRANS_DP_CTL(p));
2941 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2947 DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2949 /* must initialize pipe to something for the asserts */
2955 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2956 i915_reg_t dp_reg, enum port port,
2962 val = I915_READ(dp_reg);
2964 ret = val & DP_PORT_EN;
2966 /* asserts want to know the pipe even if the port is disabled */
2967 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2968 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2969 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2970 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2971 else if (IS_CHERRYVIEW(dev_priv))
2972 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2974 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2979 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2982 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2983 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2986 if (!intel_display_power_get_if_enabled(dev_priv,
2987 encoder->power_domain))
2990 ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
2991 encoder->port, pipe);
2993 intel_display_power_put(dev_priv, encoder->power_domain);
2998 static void intel_dp_get_config(struct intel_encoder *encoder,
2999 struct intel_crtc_state *pipe_config)
3001 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3002 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3004 enum port port = encoder->port;
3005 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3007 if (encoder->type == INTEL_OUTPUT_EDP)
3008 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3010 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3012 tmp = I915_READ(intel_dp->output_reg);
3014 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3016 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3017 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3019 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3020 flags |= DRM_MODE_FLAG_PHSYNC;
3022 flags |= DRM_MODE_FLAG_NHSYNC;
3024 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3025 flags |= DRM_MODE_FLAG_PVSYNC;
3027 flags |= DRM_MODE_FLAG_NVSYNC;
3029 if (tmp & DP_SYNC_HS_HIGH)
3030 flags |= DRM_MODE_FLAG_PHSYNC;
3032 flags |= DRM_MODE_FLAG_NHSYNC;
3034 if (tmp & DP_SYNC_VS_HIGH)
3035 flags |= DRM_MODE_FLAG_PVSYNC;
3037 flags |= DRM_MODE_FLAG_NVSYNC;
3040 pipe_config->base.adjusted_mode.flags |= flags;
3042 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3043 pipe_config->limited_color_range = true;
3045 pipe_config->lane_count =
3046 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3048 intel_dp_get_m_n(crtc, pipe_config);
3050 if (port == PORT_A) {
3051 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3052 pipe_config->port_clock = 162000;
3054 pipe_config->port_clock = 270000;
3057 pipe_config->base.adjusted_mode.crtc_clock =
3058 intel_dotclock_calculate(pipe_config->port_clock,
3059 &pipe_config->dp_m_n);
3061 if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3062 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3064 * This is a big fat ugly hack.
3066 * Some machines in UEFI boot mode provide us a VBT that has 18
3067 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3068 * unknown we fail to light up. Yet the same BIOS boots up with
3069 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3070 * max, not what it tells us to use.
3072 * Note: This will still be broken if the eDP panel is not lit
3073 * up by the BIOS, and thus we can't get the mode at module
3076 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3077 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3078 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3082 static void intel_disable_dp(struct intel_encoder *encoder,
3083 const struct intel_crtc_state *old_crtc_state,
3084 const struct drm_connector_state *old_conn_state)
3086 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3088 intel_dp->link_trained = false;
3090 if (old_crtc_state->has_audio)
3091 intel_audio_codec_disable(encoder,
3092 old_crtc_state, old_conn_state);
3094 /* Make sure the panel is off before trying to change the mode. But also
3095 * ensure that we have vdd while we switch off the panel. */
3096 intel_edp_panel_vdd_on(intel_dp);
3097 intel_edp_backlight_off(old_conn_state);
3098 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3099 intel_edp_panel_off(intel_dp);
3102 static void g4x_disable_dp(struct intel_encoder *encoder,
3103 const struct intel_crtc_state *old_crtc_state,
3104 const struct drm_connector_state *old_conn_state)
3106 intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3109 static void vlv_disable_dp(struct intel_encoder *encoder,
3110 const struct intel_crtc_state *old_crtc_state,
3111 const struct drm_connector_state *old_conn_state)
3113 intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3116 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3117 const struct intel_crtc_state *old_crtc_state,
3118 const struct drm_connector_state *old_conn_state)
3120 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3121 enum port port = encoder->port;
3124 * Bspec does not list a specific disable sequence for g4x DP.
3125 * Follow the ilk+ sequence (disable pipe before the port) for
3126 * g4x DP as it does not suffer from underruns like the normal
3127 * g4x modeset sequence (disable pipe after the port).
3129 intel_dp_link_down(encoder, old_crtc_state);
3131 /* Only ilk+ has port A */
3133 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3136 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3137 const struct intel_crtc_state *old_crtc_state,
3138 const struct drm_connector_state *old_conn_state)
3140 intel_dp_link_down(encoder, old_crtc_state);
3143 static void chv_post_disable_dp(struct intel_encoder *encoder,
3144 const struct intel_crtc_state *old_crtc_state,
3145 const struct drm_connector_state *old_conn_state)
3147 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3149 intel_dp_link_down(encoder, old_crtc_state);
3151 mutex_lock(&dev_priv->sb_lock);
3153 /* Assert data lane reset */
3154 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3156 mutex_unlock(&dev_priv->sb_lock);
3160 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3162 uint8_t dp_train_pat)
3164 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3165 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3166 enum port port = intel_dig_port->base.port;
3167 uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3169 if (dp_train_pat & train_pat_mask)
3170 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3171 dp_train_pat & train_pat_mask);
3173 if (HAS_DDI(dev_priv)) {
3174 uint32_t temp = I915_READ(DP_TP_CTL(port));
3176 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3177 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3179 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3181 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3182 switch (dp_train_pat & train_pat_mask) {
3183 case DP_TRAINING_PATTERN_DISABLE:
3184 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3187 case DP_TRAINING_PATTERN_1:
3188 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3190 case DP_TRAINING_PATTERN_2:
3191 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3193 case DP_TRAINING_PATTERN_3:
3194 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3196 case DP_TRAINING_PATTERN_4:
3197 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3200 I915_WRITE(DP_TP_CTL(port), temp);
3202 } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3203 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3204 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3206 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3207 case DP_TRAINING_PATTERN_DISABLE:
3208 *DP |= DP_LINK_TRAIN_OFF_CPT;
3210 case DP_TRAINING_PATTERN_1:
3211 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3213 case DP_TRAINING_PATTERN_2:
3214 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3216 case DP_TRAINING_PATTERN_3:
3217 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3218 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3223 *DP &= ~DP_LINK_TRAIN_MASK;
3225 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3226 case DP_TRAINING_PATTERN_DISABLE:
3227 *DP |= DP_LINK_TRAIN_OFF;
3229 case DP_TRAINING_PATTERN_1:
3230 *DP |= DP_LINK_TRAIN_PAT_1;
3232 case DP_TRAINING_PATTERN_2:
3233 *DP |= DP_LINK_TRAIN_PAT_2;
3235 case DP_TRAINING_PATTERN_3:
3236 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3237 *DP |= DP_LINK_TRAIN_PAT_2;
3243 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3244 const struct intel_crtc_state *old_crtc_state)
3246 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3248 /* enable with pattern 1 (as per spec) */
3250 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3253 * Magic for VLV/CHV. We _must_ first set up the register
3254 * without actually enabling the port, and then do another
3255 * write to enable the port. Otherwise link training will
3256 * fail when the power sequencer is freshly used for this port.
3258 intel_dp->DP |= DP_PORT_EN;
3259 if (old_crtc_state->has_audio)
3260 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3262 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3263 POSTING_READ(intel_dp->output_reg);
3266 static void intel_enable_dp(struct intel_encoder *encoder,
3267 const struct intel_crtc_state *pipe_config,
3268 const struct drm_connector_state *conn_state)
3270 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3271 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3272 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3273 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
3274 enum pipe pipe = crtc->pipe;
3276 if (WARN_ON(dp_reg & DP_PORT_EN))
3281 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3282 vlv_init_panel_power_sequencer(encoder, pipe_config);
3284 intel_dp_enable_port(intel_dp, pipe_config);
3286 edp_panel_vdd_on(intel_dp);
3287 edp_panel_on(intel_dp);
3288 edp_panel_vdd_off(intel_dp, true);
3290 pps_unlock(intel_dp);
3292 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3293 unsigned int lane_mask = 0x0;
3295 if (IS_CHERRYVIEW(dev_priv))
3296 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3298 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3302 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3303 intel_dp_start_link_train(intel_dp);
3304 intel_dp_stop_link_train(intel_dp);
3306 if (pipe_config->has_audio) {
3307 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3309 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3313 static void g4x_enable_dp(struct intel_encoder *encoder,
3314 const struct intel_crtc_state *pipe_config,
3315 const struct drm_connector_state *conn_state)
3317 intel_enable_dp(encoder, pipe_config, conn_state);
3318 intel_edp_backlight_on(pipe_config, conn_state);
3321 static void vlv_enable_dp(struct intel_encoder *encoder,
3322 const struct intel_crtc_state *pipe_config,
3323 const struct drm_connector_state *conn_state)
3325 intel_edp_backlight_on(pipe_config, conn_state);
3328 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3329 const struct intel_crtc_state *pipe_config,
3330 const struct drm_connector_state *conn_state)
3332 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3333 enum port port = encoder->port;
3335 intel_dp_prepare(encoder, pipe_config);
3337 /* Only ilk+ has port A */
3339 ironlake_edp_pll_on(intel_dp, pipe_config);
3342 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3344 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3345 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3346 enum pipe pipe = intel_dp->pps_pipe;
3347 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3349 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3351 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3354 edp_panel_vdd_off_sync(intel_dp);
3357 * VLV seems to get confused when multiple power sequencers
3358 * have the same port selected (even if only one has power/vdd
3359 * enabled). The failure manifests as vlv_wait_port_ready() failing
3360 * CHV on the other hand doesn't seem to mind having the same port
3361 * selected in multiple power sequencers, but let's clear the
3362 * port select always when logically disconnecting a power sequencer
3365 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3366 pipe_name(pipe), port_name(intel_dig_port->base.port));
3367 I915_WRITE(pp_on_reg, 0);
3368 POSTING_READ(pp_on_reg);
3370 intel_dp->pps_pipe = INVALID_PIPE;
3373 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3376 struct intel_encoder *encoder;
3378 lockdep_assert_held(&dev_priv->pps_mutex);
3380 for_each_intel_dp(&dev_priv->drm, encoder) {
3381 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3382 enum port port = encoder->port;
3384 WARN(intel_dp->active_pipe == pipe,
3385 "stealing pipe %c power sequencer from active (e)DP port %c\n",
3386 pipe_name(pipe), port_name(port));
3388 if (intel_dp->pps_pipe != pipe)
3391 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3392 pipe_name(pipe), port_name(port));
3394 /* make sure vdd is off before we steal it */
3395 vlv_detach_power_sequencer(intel_dp);
3399 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3400 const struct intel_crtc_state *crtc_state)
3402 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3403 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3404 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3406 lockdep_assert_held(&dev_priv->pps_mutex);
3408 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3410 if (intel_dp->pps_pipe != INVALID_PIPE &&
3411 intel_dp->pps_pipe != crtc->pipe) {
3413 * If another power sequencer was being used on this
3414 * port previously make sure to turn off vdd there while
3415 * we still have control of it.
3417 vlv_detach_power_sequencer(intel_dp);
3421 * We may be stealing the power
3422 * sequencer from another port.
3424 vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3426 intel_dp->active_pipe = crtc->pipe;
3428 if (!intel_dp_is_edp(intel_dp))
3431 /* now it's all ours */
3432 intel_dp->pps_pipe = crtc->pipe;
3434 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3435 pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3437 /* init power sequencer on this pipe and port */
3438 intel_dp_init_panel_power_sequencer(intel_dp);
3439 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3442 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3443 const struct intel_crtc_state *pipe_config,
3444 const struct drm_connector_state *conn_state)
3446 vlv_phy_pre_encoder_enable(encoder, pipe_config);
3448 intel_enable_dp(encoder, pipe_config, conn_state);
3451 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3452 const struct intel_crtc_state *pipe_config,
3453 const struct drm_connector_state *conn_state)
3455 intel_dp_prepare(encoder, pipe_config);
3457 vlv_phy_pre_pll_enable(encoder, pipe_config);
3460 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3461 const struct intel_crtc_state *pipe_config,
3462 const struct drm_connector_state *conn_state)
3464 chv_phy_pre_encoder_enable(encoder, pipe_config);
3466 intel_enable_dp(encoder, pipe_config, conn_state);
3468 /* Second common lane will stay alive on its own now */
3469 chv_phy_release_cl2_override(encoder);
3472 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3473 const struct intel_crtc_state *pipe_config,
3474 const struct drm_connector_state *conn_state)
3476 intel_dp_prepare(encoder, pipe_config);
3478 chv_phy_pre_pll_enable(encoder, pipe_config);
3481 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3482 const struct intel_crtc_state *old_crtc_state,
3483 const struct drm_connector_state *old_conn_state)
3485 chv_phy_post_pll_disable(encoder, old_crtc_state);
3489 * Fetch AUX CH registers 0x202 - 0x207 which contain
3490 * link status information
3493 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3495 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3496 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3499 /* These are source-specific values. */
3501 intel_dp_voltage_max(struct intel_dp *intel_dp)
3503 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3504 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3505 enum port port = encoder->port;
3507 if (HAS_DDI(dev_priv))
3508 return intel_ddi_dp_voltage_max(encoder);
3509 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3510 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3511 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3512 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3513 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3514 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3516 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3520 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3522 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3523 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3524 enum port port = encoder->port;
3526 if (HAS_DDI(dev_priv)) {
3527 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3528 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3529 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3530 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3531 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3532 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3533 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3534 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3535 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3536 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3538 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3540 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3541 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3542 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3543 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3544 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3545 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3546 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3548 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3551 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3552 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3553 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3554 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3555 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3556 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3557 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3558 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3560 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3565 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3567 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3568 unsigned long demph_reg_value, preemph_reg_value,
3569 uniqtranscale_reg_value;
3570 uint8_t train_set = intel_dp->train_set[0];
3572 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3573 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3574 preemph_reg_value = 0x0004000;
3575 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3576 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3577 demph_reg_value = 0x2B405555;
3578 uniqtranscale_reg_value = 0x552AB83A;
3580 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3581 demph_reg_value = 0x2B404040;
3582 uniqtranscale_reg_value = 0x5548B83A;
3584 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3585 demph_reg_value = 0x2B245555;
3586 uniqtranscale_reg_value = 0x5560B83A;
3588 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3589 demph_reg_value = 0x2B405555;
3590 uniqtranscale_reg_value = 0x5598DA3A;
3596 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3597 preemph_reg_value = 0x0002000;
3598 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3599 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3600 demph_reg_value = 0x2B404040;
3601 uniqtranscale_reg_value = 0x5552B83A;
3603 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3604 demph_reg_value = 0x2B404848;
3605 uniqtranscale_reg_value = 0x5580B83A;
3607 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3608 demph_reg_value = 0x2B404040;
3609 uniqtranscale_reg_value = 0x55ADDA3A;
3615 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3616 preemph_reg_value = 0x0000000;
3617 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3618 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3619 demph_reg_value = 0x2B305555;
3620 uniqtranscale_reg_value = 0x5570B83A;
3622 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3623 demph_reg_value = 0x2B2B4040;
3624 uniqtranscale_reg_value = 0x55ADDA3A;
3630 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3631 preemph_reg_value = 0x0006000;
3632 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3633 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3634 demph_reg_value = 0x1B405555;
3635 uniqtranscale_reg_value = 0x55ADDA3A;
3645 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3646 uniqtranscale_reg_value, 0);
3651 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3653 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3654 u32 deemph_reg_value, margin_reg_value;
3655 bool uniq_trans_scale = false;
3656 uint8_t train_set = intel_dp->train_set[0];
3658 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3659 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3660 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3661 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3662 deemph_reg_value = 128;
3663 margin_reg_value = 52;
3665 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3666 deemph_reg_value = 128;
3667 margin_reg_value = 77;
3669 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3670 deemph_reg_value = 128;
3671 margin_reg_value = 102;
3673 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3674 deemph_reg_value = 128;
3675 margin_reg_value = 154;
3676 uniq_trans_scale = true;
3682 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3683 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3684 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3685 deemph_reg_value = 85;
3686 margin_reg_value = 78;
3688 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3689 deemph_reg_value = 85;
3690 margin_reg_value = 116;
3692 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3693 deemph_reg_value = 85;
3694 margin_reg_value = 154;
3700 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3701 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3702 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3703 deemph_reg_value = 64;
3704 margin_reg_value = 104;
3706 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3707 deemph_reg_value = 64;
3708 margin_reg_value = 154;
3714 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3715 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3716 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3717 deemph_reg_value = 43;
3718 margin_reg_value = 154;
3728 chv_set_phy_signal_level(encoder, deemph_reg_value,
3729 margin_reg_value, uniq_trans_scale);
3735 g4x_signal_levels(uint8_t train_set)
3737 uint32_t signal_levels = 0;
3739 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3740 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3742 signal_levels |= DP_VOLTAGE_0_4;
3744 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3745 signal_levels |= DP_VOLTAGE_0_6;
3747 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3748 signal_levels |= DP_VOLTAGE_0_8;
3750 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3751 signal_levels |= DP_VOLTAGE_1_2;
3754 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3755 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3757 signal_levels |= DP_PRE_EMPHASIS_0;
3759 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3760 signal_levels |= DP_PRE_EMPHASIS_3_5;
3762 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3763 signal_levels |= DP_PRE_EMPHASIS_6;
3765 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3766 signal_levels |= DP_PRE_EMPHASIS_9_5;
3769 return signal_levels;
3772 /* SNB CPU eDP voltage swing and pre-emphasis control */
3774 snb_cpu_edp_signal_levels(uint8_t train_set)
3776 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3777 DP_TRAIN_PRE_EMPHASIS_MASK);
3778 switch (signal_levels) {
3779 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3780 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3781 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3782 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3783 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3784 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3785 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3786 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3787 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3788 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3789 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3790 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3791 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3792 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3794 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3795 "0x%x\n", signal_levels);
3796 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3800 /* IVB CPU eDP voltage swing and pre-emphasis control */
3802 ivb_cpu_edp_signal_levels(uint8_t train_set)
3804 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3805 DP_TRAIN_PRE_EMPHASIS_MASK);
3806 switch (signal_levels) {
3807 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3808 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3809 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3810 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3811 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3812 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3814 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3815 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3816 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3817 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3819 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3820 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3821 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3822 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3825 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3826 "0x%x\n", signal_levels);
3827 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3832 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3834 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3835 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3836 enum port port = intel_dig_port->base.port;
3837 uint32_t signal_levels, mask = 0;
3838 uint8_t train_set = intel_dp->train_set[0];
3840 if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
3841 signal_levels = bxt_signal_levels(intel_dp);
3842 } else if (HAS_DDI(dev_priv)) {
3843 signal_levels = ddi_signal_levels(intel_dp);
3844 mask = DDI_BUF_EMP_MASK;
3845 } else if (IS_CHERRYVIEW(dev_priv)) {
3846 signal_levels = chv_signal_levels(intel_dp);
3847 } else if (IS_VALLEYVIEW(dev_priv)) {
3848 signal_levels = vlv_signal_levels(intel_dp);
3849 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3850 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3851 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3852 } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3853 signal_levels = snb_cpu_edp_signal_levels(train_set);
3854 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3856 signal_levels = g4x_signal_levels(train_set);
3857 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3861 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3863 DRM_DEBUG_KMS("Using vswing level %d\n",
3864 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3865 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3866 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3867 DP_TRAIN_PRE_EMPHASIS_SHIFT);
3869 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3871 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3872 POSTING_READ(intel_dp->output_reg);
3876 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3877 uint8_t dp_train_pat)
3879 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3880 struct drm_i915_private *dev_priv =
3881 to_i915(intel_dig_port->base.base.dev);
3883 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3885 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3886 POSTING_READ(intel_dp->output_reg);
3889 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3891 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3892 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3893 enum port port = intel_dig_port->base.port;
3896 if (!HAS_DDI(dev_priv))
3899 val = I915_READ(DP_TP_CTL(port));
3900 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3901 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3902 I915_WRITE(DP_TP_CTL(port), val);
3905 * On PORT_A we can have only eDP in SST mode. There the only reason
3906 * we need to set idle transmission mode is to work around a HW issue
3907 * where we enable the pipe while not in idle link-training mode.
3908 * In this case there is requirement to wait for a minimum number of
3909 * idle patterns to be sent.
3914 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3915 DP_TP_STATUS_IDLE_DONE,
3916 DP_TP_STATUS_IDLE_DONE,
3918 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3922 intel_dp_link_down(struct intel_encoder *encoder,
3923 const struct intel_crtc_state *old_crtc_state)
3925 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3926 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3927 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3928 enum port port = encoder->port;
3929 uint32_t DP = intel_dp->DP;
3931 if (WARN_ON(HAS_DDI(dev_priv)))
3934 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3937 DRM_DEBUG_KMS("\n");
3939 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3940 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3941 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3942 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3944 DP &= ~DP_LINK_TRAIN_MASK;
3945 DP |= DP_LINK_TRAIN_PAT_IDLE;
3947 I915_WRITE(intel_dp->output_reg, DP);
3948 POSTING_READ(intel_dp->output_reg);
3950 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3951 I915_WRITE(intel_dp->output_reg, DP);
3952 POSTING_READ(intel_dp->output_reg);
3955 * HW workaround for IBX, we need to move the port
3956 * to transcoder A after disabling it to allow the
3957 * matching HDMI port to be enabled on transcoder A.
3959 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3961 * We get CPU/PCH FIFO underruns on the other pipe when
3962 * doing the workaround. Sweep them under the rug.
3964 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3965 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3967 /* always enable with pattern 1 (as per spec) */
3968 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
3969 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
3970 DP_LINK_TRAIN_PAT_1;
3971 I915_WRITE(intel_dp->output_reg, DP);
3972 POSTING_READ(intel_dp->output_reg);
3975 I915_WRITE(intel_dp->output_reg, DP);
3976 POSTING_READ(intel_dp->output_reg);
3978 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3979 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3980 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3983 msleep(intel_dp->panel_power_down_delay);
3987 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3989 intel_dp->active_pipe = INVALID_PIPE;
3990 pps_unlock(intel_dp);
3995 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3997 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3998 sizeof(intel_dp->dpcd)) < 0)
3999 return false; /* aux transfer failed */
4001 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4003 return intel_dp->dpcd[DP_DPCD_REV] != 0;
4006 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4009 * Clear the cached register set to avoid using stale values
4010 * for the sinks that do not support DSC.
4012 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4014 /* Clear fec_capable to avoid using stale values */
4015 intel_dp->fec_capable = 0;
4017 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4018 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4019 intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4020 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4022 sizeof(intel_dp->dsc_dpcd)) < 0)
4023 DRM_ERROR("Failed to read DPCD register 0x%x\n",
4026 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4027 (int)sizeof(intel_dp->dsc_dpcd),
4028 intel_dp->dsc_dpcd);
4030 /* FEC is supported only on DP 1.4 */
4031 if (!intel_dp_is_edp(intel_dp) &&
4032 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4033 &intel_dp->fec_capable) < 0)
4034 DRM_ERROR("Failed to read FEC DPCD register\n");
4036 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4041 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4043 struct drm_i915_private *dev_priv =
4044 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4046 /* this function is meant to be called only once */
4047 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4049 if (!intel_dp_read_dpcd(intel_dp))
4052 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4053 drm_dp_is_branch(intel_dp->dpcd));
4055 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4056 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4057 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4060 * Read the eDP display control registers.
4062 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4063 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4064 * set, but require eDP 1.4+ detection (e.g. for supported link rates
4065 * method). The display control registers should read zero if they're
4066 * not supported anyway.
4068 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4069 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4070 sizeof(intel_dp->edp_dpcd))
4071 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
4072 intel_dp->edp_dpcd);
4075 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4076 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4078 intel_psr_init_dpcd(intel_dp);
4080 /* Read the eDP 1.4+ supported link rates. */
4081 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4082 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4085 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4086 sink_rates, sizeof(sink_rates));
4088 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4089 int val = le16_to_cpu(sink_rates[i]);
4094 /* Value read multiplied by 200kHz gives the per-lane
4095 * link rate in kHz. The source rates are, however,
4096 * stored in terms of LS_Clk kHz. The full conversion
4097 * back to symbols is
4098 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4100 intel_dp->sink_rates[i] = (val * 200) / 10;
4102 intel_dp->num_sink_rates = i;
4106 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4107 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4109 if (intel_dp->num_sink_rates)
4110 intel_dp->use_rate_select = true;
4112 intel_dp_set_sink_rates(intel_dp);
4114 intel_dp_set_common_rates(intel_dp);
4116 /* Read the eDP DSC DPCD registers */
4117 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4118 intel_dp_get_dsc_sink_cap(intel_dp);
4125 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4127 if (!intel_dp_read_dpcd(intel_dp))
4130 /* Don't clobber cached eDP rates. */
4131 if (!intel_dp_is_edp(intel_dp)) {
4132 intel_dp_set_sink_rates(intel_dp);
4133 intel_dp_set_common_rates(intel_dp);
4137 * Some eDP panels do not set a valid value for sink count, that is why
4138 * it don't care about read it here and in intel_edp_init_dpcd().
4140 if (!intel_dp_is_edp(intel_dp)) {
4144 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4149 * Sink count can change between short pulse hpd hence
4150 * a member variable in intel_dp will track any changes
4151 * between short pulse interrupts.
4153 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4156 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4157 * a dongle is present but no display. Unless we require to know
4158 * if a dongle is present or not, we don't need to update
4159 * downstream port information. So, an early return here saves
4160 * time from performing other operations which are not required.
4162 if (!intel_dp->sink_count)
4166 if (!drm_dp_is_branch(intel_dp->dpcd))
4167 return true; /* native DP sink */
4169 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4170 return true; /* no per-port downstream info */
4172 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4173 intel_dp->downstream_ports,
4174 DP_MAX_DOWNSTREAM_PORTS) < 0)
4175 return false; /* downstream port status fetch failed */
4181 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4185 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4188 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4191 return mstm_cap & DP_MST_CAP;
4195 intel_dp_can_mst(struct intel_dp *intel_dp)
4197 return i915_modparams.enable_dp_mst &&
4198 intel_dp->can_mst &&
4199 intel_dp_sink_can_mst(intel_dp);
4203 intel_dp_configure_mst(struct intel_dp *intel_dp)
4205 struct intel_encoder *encoder =
4206 &dp_to_dig_port(intel_dp)->base;
4207 bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4209 DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
4210 port_name(encoder->port), yesno(intel_dp->can_mst),
4211 yesno(sink_can_mst), yesno(i915_modparams.enable_dp_mst));
4213 if (!intel_dp->can_mst)
4216 intel_dp->is_mst = sink_can_mst &&
4217 i915_modparams.enable_dp_mst;
4219 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4224 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4226 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4227 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4231 u16 intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
4232 int mode_clock, int mode_hdisplay)
4234 u16 bits_per_pixel, max_bpp_small_joiner_ram;
4238 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
4239 * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
4240 * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
4241 * for MST -> TimeSlotsPerMTP has to be calculated
4243 bits_per_pixel = (link_clock * lane_count * 8 *
4244 DP_DSC_FEC_OVERHEAD_FACTOR) /
4247 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
4248 max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
4252 * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
4253 * check, output bpp from small joiner RAM check)
4255 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
4257 /* Error out if the max bpp is less than smallest allowed valid bpp */
4258 if (bits_per_pixel < valid_dsc_bpp[0]) {
4259 DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
4263 /* Find the nearest match in the array of known BPPs from VESA */
4264 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
4265 if (bits_per_pixel < valid_dsc_bpp[i + 1])
4268 bits_per_pixel = valid_dsc_bpp[i];
4271 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
4272 * fractional part is 0
4274 return bits_per_pixel << 4;
4277 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
4281 u8 min_slice_count, i;
4282 int max_slice_width;
4284 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
4285 min_slice_count = DIV_ROUND_UP(mode_clock,
4286 DP_DSC_MAX_ENC_THROUGHPUT_0);
4288 min_slice_count = DIV_ROUND_UP(mode_clock,
4289 DP_DSC_MAX_ENC_THROUGHPUT_1);
4291 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
4292 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
4293 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
4297 /* Also take into account max slice width */
4298 min_slice_count = min_t(uint8_t, min_slice_count,
4299 DIV_ROUND_UP(mode_hdisplay,
4302 /* Find the closest match to the valid slice count values */
4303 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
4304 if (valid_dsc_slicecount[i] >
4305 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
4308 if (min_slice_count <= valid_dsc_slicecount[i])
4309 return valid_dsc_slicecount[i];
4312 DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
4316 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4320 uint8_t test_lane_count, test_link_bw;
4324 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4325 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4329 DRM_DEBUG_KMS("Lane count read failed\n");
4332 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4334 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4337 DRM_DEBUG_KMS("Link Rate read failed\n");
4340 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4342 /* Validate the requested link rate and lane count */
4343 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4347 intel_dp->compliance.test_lane_count = test_lane_count;
4348 intel_dp->compliance.test_link_rate = test_link_rate;
4353 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4355 uint8_t test_pattern;
4357 __be16 h_width, v_height;
4360 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4361 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4364 DRM_DEBUG_KMS("Test pattern read failed\n");
4367 if (test_pattern != DP_COLOR_RAMP)
4370 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4373 DRM_DEBUG_KMS("H Width read failed\n");
4377 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4380 DRM_DEBUG_KMS("V Height read failed\n");
4384 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4387 DRM_DEBUG_KMS("TEST MISC read failed\n");
4390 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4392 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4394 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4395 case DP_TEST_BIT_DEPTH_6:
4396 intel_dp->compliance.test_data.bpc = 6;
4398 case DP_TEST_BIT_DEPTH_8:
4399 intel_dp->compliance.test_data.bpc = 8;
4405 intel_dp->compliance.test_data.video_pattern = test_pattern;
4406 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4407 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4408 /* Set test active flag here so userspace doesn't interrupt things */
4409 intel_dp->compliance.test_active = 1;
4414 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4416 uint8_t test_result = DP_TEST_ACK;
4417 struct intel_connector *intel_connector = intel_dp->attached_connector;
4418 struct drm_connector *connector = &intel_connector->base;
4420 if (intel_connector->detect_edid == NULL ||
4421 connector->edid_corrupt ||
4422 intel_dp->aux.i2c_defer_count > 6) {
4423 /* Check EDID read for NACKs, DEFERs and corruption
4424 * (DP CTS 1.2 Core r1.1)
4425 * 4.2.2.4 : Failed EDID read, I2C_NAK
4426 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4427 * 4.2.2.6 : EDID corruption detected
4428 * Use failsafe mode for all cases
4430 if (intel_dp->aux.i2c_nack_count > 0 ||
4431 intel_dp->aux.i2c_defer_count > 0)
4432 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4433 intel_dp->aux.i2c_nack_count,
4434 intel_dp->aux.i2c_defer_count);
4435 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4437 struct edid *block = intel_connector->detect_edid;
4439 /* We have to write the checksum
4440 * of the last block read
4442 block += intel_connector->detect_edid->extensions;
4444 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4445 block->checksum) <= 0)
4446 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4448 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4449 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4452 /* Set test active flag here so userspace doesn't interrupt things */
4453 intel_dp->compliance.test_active = 1;
4458 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4460 uint8_t test_result = DP_TEST_NAK;
4464 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4466 uint8_t response = DP_TEST_NAK;
4467 uint8_t request = 0;
4470 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4472 DRM_DEBUG_KMS("Could not read test request from sink\n");
4477 case DP_TEST_LINK_TRAINING:
4478 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4479 response = intel_dp_autotest_link_training(intel_dp);
4481 case DP_TEST_LINK_VIDEO_PATTERN:
4482 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4483 response = intel_dp_autotest_video_pattern(intel_dp);
4485 case DP_TEST_LINK_EDID_READ:
4486 DRM_DEBUG_KMS("EDID test requested\n");
4487 response = intel_dp_autotest_edid(intel_dp);
4489 case DP_TEST_LINK_PHY_TEST_PATTERN:
4490 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4491 response = intel_dp_autotest_phy_pattern(intel_dp);
4494 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4498 if (response & DP_TEST_ACK)
4499 intel_dp->compliance.test_type = request;
4502 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4504 DRM_DEBUG_KMS("Could not write test response to sink\n");
4508 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4512 if (intel_dp->is_mst) {
4513 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4518 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4519 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4523 /* check link status - esi[10] = 0x200c */
4524 if (intel_dp->active_mst_links > 0 &&
4525 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4526 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4527 intel_dp_start_link_train(intel_dp);
4528 intel_dp_stop_link_train(intel_dp);
4531 DRM_DEBUG_KMS("got esi %3ph\n", esi);
4532 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4535 for (retry = 0; retry < 3; retry++) {
4537 wret = drm_dp_dpcd_write(&intel_dp->aux,
4538 DP_SINK_COUNT_ESI+1,
4545 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4547 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4555 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4556 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4557 intel_dp->is_mst = false;
4558 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4559 /* send a hotplug event */
4560 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4567 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4569 u8 link_status[DP_LINK_STATUS_SIZE];
4571 if (!intel_dp->link_trained)
4575 * While PSR source HW is enabled, it will control main-link sending
4576 * frames, enabling and disabling it so trying to do a retrain will fail
4577 * as the link would or not be on or it could mix training patterns
4578 * and frame data at the same time causing retrain to fail.
4579 * Also when exiting PSR, HW will retrain the link anyways fixing
4580 * any link status error.
4582 if (intel_psr_enabled(intel_dp))
4585 if (!intel_dp_get_link_status(intel_dp, link_status))
4589 * Validate the cached values of intel_dp->link_rate and
4590 * intel_dp->lane_count before attempting to retrain.
4592 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4593 intel_dp->lane_count))
4596 /* Retrain if Channel EQ or CR not ok */
4597 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4600 int intel_dp_retrain_link(struct intel_encoder *encoder,
4601 struct drm_modeset_acquire_ctx *ctx)
4603 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4604 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4605 struct intel_connector *connector = intel_dp->attached_connector;
4606 struct drm_connector_state *conn_state;
4607 struct intel_crtc_state *crtc_state;
4608 struct intel_crtc *crtc;
4611 /* FIXME handle the MST connectors as well */
4613 if (!connector || connector->base.status != connector_status_connected)
4616 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4621 conn_state = connector->base.state;
4623 crtc = to_intel_crtc(conn_state->crtc);
4627 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4631 crtc_state = to_intel_crtc_state(crtc->base.state);
4633 WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4635 if (!crtc_state->base.active)
4638 if (conn_state->commit &&
4639 !try_wait_for_completion(&conn_state->commit->hw_done))
4642 if (!intel_dp_needs_link_retrain(intel_dp))
4645 /* Suppress underruns caused by re-training */
4646 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4647 if (crtc_state->has_pch_encoder)
4648 intel_set_pch_fifo_underrun_reporting(dev_priv,
4649 intel_crtc_pch_transcoder(crtc), false);
4651 intel_dp_start_link_train(intel_dp);
4652 intel_dp_stop_link_train(intel_dp);
4654 /* Keep underrun reporting disabled until things are stable */
4655 intel_wait_for_vblank(dev_priv, crtc->pipe);
4657 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4658 if (crtc_state->has_pch_encoder)
4659 intel_set_pch_fifo_underrun_reporting(dev_priv,
4660 intel_crtc_pch_transcoder(crtc), true);
4666 * If display is now connected check links status,
4667 * there has been known issues of link loss triggering
4670 * Some sinks (eg. ASUS PB287Q) seem to perform some
4671 * weird HPD ping pong during modesets. So we can apparently
4672 * end up with HPD going low during a modeset, and then
4673 * going back up soon after. And once that happens we must
4674 * retrain the link to get a picture. That's in case no
4675 * userspace component reacted to intermittent HPD dip.
4677 static bool intel_dp_hotplug(struct intel_encoder *encoder,
4678 struct intel_connector *connector)
4680 struct drm_modeset_acquire_ctx ctx;
4684 changed = intel_encoder_hotplug(encoder, connector);
4686 drm_modeset_acquire_init(&ctx, 0);
4689 ret = intel_dp_retrain_link(encoder, &ctx);
4691 if (ret == -EDEADLK) {
4692 drm_modeset_backoff(&ctx);
4699 drm_modeset_drop_locks(&ctx);
4700 drm_modeset_acquire_fini(&ctx);
4701 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4706 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
4710 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4713 if (drm_dp_dpcd_readb(&intel_dp->aux,
4714 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4717 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4719 if (val & DP_AUTOMATED_TEST_REQUEST)
4720 intel_dp_handle_test_request(intel_dp);
4722 if (val & DP_CP_IRQ)
4723 intel_hdcp_check_link(intel_dp->attached_connector);
4725 if (val & DP_SINK_SPECIFIC_IRQ)
4726 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
4730 * According to DP spec
4733 * 2. Configure link according to Receiver Capabilities
4734 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4735 * 4. Check link status on receipt of hot-plug interrupt
4737 * intel_dp_short_pulse - handles short pulse interrupts
4738 * when full detection is not required.
4739 * Returns %true if short pulse is handled and full detection
4740 * is NOT required and %false otherwise.
4743 intel_dp_short_pulse(struct intel_dp *intel_dp)
4745 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4746 u8 old_sink_count = intel_dp->sink_count;
4750 * Clearing compliance test variables to allow capturing
4751 * of values for next automated test request.
4753 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4756 * Now read the DPCD to see if it's actually running
4757 * If the current value of sink count doesn't match with
4758 * the value that was stored earlier or dpcd read failed
4759 * we need to do full detection
4761 ret = intel_dp_get_dpcd(intel_dp);
4763 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4764 /* No need to proceed if we are going to do full detect */
4768 intel_dp_check_service_irq(intel_dp);
4770 /* Handle CEC interrupts, if any */
4771 drm_dp_cec_irq(&intel_dp->aux);
4773 /* defer to the hotplug work for link retraining if needed */
4774 if (intel_dp_needs_link_retrain(intel_dp))
4777 intel_psr_short_pulse(intel_dp);
4779 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4780 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4781 /* Send a Hotplug Uevent to userspace to start modeset */
4782 drm_kms_helper_hotplug_event(&dev_priv->drm);
4788 /* XXX this is probably wrong for multiple downstream ports */
4789 static enum drm_connector_status
4790 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4792 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4793 uint8_t *dpcd = intel_dp->dpcd;
4797 lspcon_resume(lspcon);
4799 if (!intel_dp_get_dpcd(intel_dp))
4800 return connector_status_disconnected;
4802 if (intel_dp_is_edp(intel_dp))
4803 return connector_status_connected;
4805 /* if there's no downstream port, we're done */
4806 if (!drm_dp_is_branch(dpcd))
4807 return connector_status_connected;
4809 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4810 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4811 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4813 return intel_dp->sink_count ?
4814 connector_status_connected : connector_status_disconnected;
4817 if (intel_dp_can_mst(intel_dp))
4818 return connector_status_connected;
4820 /* If no HPD, poke DDC gently */
4821 if (drm_probe_ddc(&intel_dp->aux.ddc))
4822 return connector_status_connected;
4824 /* Well we tried, say unknown for unreliable port types */
4825 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4826 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4827 if (type == DP_DS_PORT_TYPE_VGA ||
4828 type == DP_DS_PORT_TYPE_NON_EDID)
4829 return connector_status_unknown;
4831 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4832 DP_DWN_STRM_PORT_TYPE_MASK;
4833 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4834 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4835 return connector_status_unknown;
4838 /* Anything else is out of spec, warn and ignore */
4839 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4840 return connector_status_disconnected;
4843 static enum drm_connector_status
4844 edp_detect(struct intel_dp *intel_dp)
4846 return connector_status_connected;
4849 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4851 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4854 switch (encoder->hpd_pin) {
4856 bit = SDE_PORTB_HOTPLUG;
4859 bit = SDE_PORTC_HOTPLUG;
4862 bit = SDE_PORTD_HOTPLUG;
4865 MISSING_CASE(encoder->hpd_pin);
4869 return I915_READ(SDEISR) & bit;
4872 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4874 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4877 switch (encoder->hpd_pin) {
4879 bit = SDE_PORTB_HOTPLUG_CPT;
4882 bit = SDE_PORTC_HOTPLUG_CPT;
4885 bit = SDE_PORTD_HOTPLUG_CPT;
4888 MISSING_CASE(encoder->hpd_pin);
4892 return I915_READ(SDEISR) & bit;
4895 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4897 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4900 switch (encoder->hpd_pin) {
4902 bit = SDE_PORTA_HOTPLUG_SPT;
4905 bit = SDE_PORTE_HOTPLUG_SPT;
4908 return cpt_digital_port_connected(encoder);
4911 return I915_READ(SDEISR) & bit;
4914 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4916 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4919 switch (encoder->hpd_pin) {
4921 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4924 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4927 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4930 MISSING_CASE(encoder->hpd_pin);
4934 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4937 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4939 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4942 switch (encoder->hpd_pin) {
4944 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4947 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4950 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4953 MISSING_CASE(encoder->hpd_pin);
4957 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4960 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
4962 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4964 if (encoder->hpd_pin == HPD_PORT_A)
4965 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4967 return ibx_digital_port_connected(encoder);
4970 static bool snb_digital_port_connected(struct intel_encoder *encoder)
4972 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4974 if (encoder->hpd_pin == HPD_PORT_A)
4975 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4977 return cpt_digital_port_connected(encoder);
4980 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
4982 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4984 if (encoder->hpd_pin == HPD_PORT_A)
4985 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4987 return cpt_digital_port_connected(encoder);
4990 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4992 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4994 if (encoder->hpd_pin == HPD_PORT_A)
4995 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4997 return cpt_digital_port_connected(encoder);
5000 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5002 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5005 switch (encoder->hpd_pin) {
5007 bit = BXT_DE_PORT_HP_DDIA;
5010 bit = BXT_DE_PORT_HP_DDIB;
5013 bit = BXT_DE_PORT_HP_DDIC;
5016 MISSING_CASE(encoder->hpd_pin);
5020 return I915_READ(GEN8_DE_PORT_ISR) & bit;
5023 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
5024 struct intel_digital_port *intel_dig_port)
5026 enum port port = intel_dig_port->base.port;
5028 return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
5031 static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
5032 struct intel_digital_port *intel_dig_port,
5033 bool is_legacy, bool is_typec, bool is_tbt)
5035 enum port port = intel_dig_port->base.port;
5036 enum tc_port_type old_type = intel_dig_port->tc_type;
5037 const char *type_str;
5039 WARN_ON(is_legacy + is_typec + is_tbt != 1);
5042 intel_dig_port->tc_type = TC_PORT_LEGACY;
5043 type_str = "legacy";
5044 } else if (is_typec) {
5045 intel_dig_port->tc_type = TC_PORT_TYPEC;
5047 } else if (is_tbt) {
5048 intel_dig_port->tc_type = TC_PORT_TBT;
5054 /* Types are not supposed to be changed at runtime. */
5055 WARN_ON(old_type != TC_PORT_UNKNOWN &&
5056 old_type != intel_dig_port->tc_type);
5058 if (old_type != intel_dig_port->tc_type)
5059 DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
5063 static void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
5064 struct intel_digital_port *dig_port);
5067 * This function implements the first part of the Connect Flow described by our
5068 * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
5069 * lanes, EDID, etc) is done as needed in the typical places.
5071 * Unlike the other ports, type-C ports are not available to use as soon as we
5072 * get a hotplug. The type-C PHYs can be shared between multiple controllers:
5073 * display, USB, etc. As a result, handshaking through FIA is required around
5074 * connect and disconnect to cleanly transfer ownership with the controller and
5075 * set the type-C power state.
5077 * We could opt to only do the connect flow when we actually try to use the AUX
5078 * channels or do a modeset, then immediately run the disconnect flow after
5079 * usage, but there are some implications on this for a dynamic environment:
5080 * things may go away or change behind our backs. So for now our driver is
5081 * always trying to acquire ownership of the controller as soon as it gets an
5082 * interrupt (or polls state and sees a port is connected) and only gives it
5083 * back when it sees a disconnect. Implementation of a more fine-grained model
5084 * will require a lot of coordination with user space and thorough testing for
5085 * the extra possible cases.
5087 static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
5088 struct intel_digital_port *dig_port)
5090 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
5093 if (dig_port->tc_type != TC_PORT_LEGACY &&
5094 dig_port->tc_type != TC_PORT_TYPEC)
5097 val = I915_READ(PORT_TX_DFLEXDPPMS);
5098 if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
5099 DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
5104 * This function may be called many times in a row without an HPD event
5105 * in between, so try to avoid the write when we can.
5107 val = I915_READ(PORT_TX_DFLEXDPCSSS);
5108 if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
5109 val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
5110 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
5114 * Now we have to re-check the live state, in case the port recently
5115 * became disconnected. Not necessary for legacy mode.
5117 if (dig_port->tc_type == TC_PORT_TYPEC &&
5118 !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
5119 DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
5120 icl_tc_phy_disconnect(dev_priv, dig_port);
5128 * See the comment at the connect function. This implements the Disconnect
5131 static void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
5132 struct intel_digital_port *dig_port)
5134 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
5136 if (dig_port->tc_type == TC_PORT_UNKNOWN)
5140 * TBT disconnection flow is read the live status, what was done in
5143 if (dig_port->tc_type == TC_PORT_TYPEC ||
5144 dig_port->tc_type == TC_PORT_LEGACY) {
5147 val = I915_READ(PORT_TX_DFLEXDPCSSS);
5148 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
5149 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
5152 dig_port->tc_type = TC_PORT_UNKNOWN;
5156 * The type-C ports are different because even when they are connected, they may
5157 * not be available/usable by the graphics driver: see the comment on
5158 * icl_tc_phy_connect(). So in our driver instead of adding the additional
5159 * concept of "usable" and make everything check for "connected and usable" we
5160 * define a port as "connected" when it is not only connected, but also when it
5161 * is usable by the rest of the driver. That maintains the old assumption that
5162 * connected ports are usable, and avoids exposing to the users objects they
5165 static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
5166 struct intel_digital_port *intel_dig_port)
5168 enum port port = intel_dig_port->base.port;
5169 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
5170 bool is_legacy, is_typec, is_tbt;
5173 is_legacy = I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port);
5176 * The spec says we shouldn't be using the ISR bits for detecting
5177 * between TC and TBT. We should use DFLEXDPSP.
5179 dpsp = I915_READ(PORT_TX_DFLEXDPSP);
5180 is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
5181 is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
5183 if (!is_legacy && !is_typec && !is_tbt) {
5184 icl_tc_phy_disconnect(dev_priv, intel_dig_port);
5188 icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
5191 if (!icl_tc_phy_connect(dev_priv, intel_dig_port))
5197 static bool icl_digital_port_connected(struct intel_encoder *encoder)
5199 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5200 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
5202 if (intel_port_is_combophy(dev_priv, encoder->port))
5203 return icl_combo_port_connected(dev_priv, dig_port);
5204 else if (intel_port_is_tc(dev_priv, encoder->port))
5205 return icl_tc_port_connected(dev_priv, dig_port);
5207 MISSING_CASE(encoder->hpd_pin);
5213 * intel_digital_port_connected - is the specified port connected?
5214 * @encoder: intel_encoder
5216 * In cases where there's a connector physically connected but it can't be used
5217 * by our hardware we also return false, since the rest of the driver should
5218 * pretty much treat the port as disconnected. This is relevant for type-C
5219 * (starting on ICL) where there's ownership involved.
5221 * Return %true if port is connected, %false otherwise.
5223 bool intel_digital_port_connected(struct intel_encoder *encoder)
5225 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5227 if (HAS_GMCH_DISPLAY(dev_priv)) {
5228 if (IS_GM45(dev_priv))
5229 return gm45_digital_port_connected(encoder);
5231 return g4x_digital_port_connected(encoder);
5234 if (INTEL_GEN(dev_priv) >= 11)
5235 return icl_digital_port_connected(encoder);
5236 else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv))
5237 return spt_digital_port_connected(encoder);
5238 else if (IS_GEN9_LP(dev_priv))
5239 return bxt_digital_port_connected(encoder);
5240 else if (IS_GEN8(dev_priv))
5241 return bdw_digital_port_connected(encoder);
5242 else if (IS_GEN7(dev_priv))
5243 return ivb_digital_port_connected(encoder);
5244 else if (IS_GEN6(dev_priv))
5245 return snb_digital_port_connected(encoder);
5246 else if (IS_GEN5(dev_priv))
5247 return ilk_digital_port_connected(encoder);
5249 MISSING_CASE(INTEL_GEN(dev_priv));
5253 static struct edid *
5254 intel_dp_get_edid(struct intel_dp *intel_dp)
5256 struct intel_connector *intel_connector = intel_dp->attached_connector;
5258 /* use cached edid if we have one */
5259 if (intel_connector->edid) {
5261 if (IS_ERR(intel_connector->edid))
5264 return drm_edid_duplicate(intel_connector->edid);
5266 return drm_get_edid(&intel_connector->base,
5267 &intel_dp->aux.ddc);
5271 intel_dp_set_edid(struct intel_dp *intel_dp)
5273 struct intel_connector *intel_connector = intel_dp->attached_connector;
5276 intel_dp_unset_edid(intel_dp);
5277 edid = intel_dp_get_edid(intel_dp);
5278 intel_connector->detect_edid = edid;
5280 intel_dp->has_audio = drm_detect_monitor_audio(edid);
5281 drm_dp_cec_set_edid(&intel_dp->aux, edid);
5285 intel_dp_unset_edid(struct intel_dp *intel_dp)
5287 struct intel_connector *intel_connector = intel_dp->attached_connector;
5289 drm_dp_cec_unset_edid(&intel_dp->aux);
5290 kfree(intel_connector->detect_edid);
5291 intel_connector->detect_edid = NULL;
5293 intel_dp->has_audio = false;
5297 intel_dp_detect(struct drm_connector *connector,
5298 struct drm_modeset_acquire_ctx *ctx,
5301 struct drm_i915_private *dev_priv = to_i915(connector->dev);
5302 struct intel_dp *intel_dp = intel_attached_dp(connector);
5303 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5304 struct intel_encoder *encoder = &dig_port->base;
5305 enum drm_connector_status status;
5306 enum intel_display_power_domain aux_domain =
5307 intel_aux_power_domain(dig_port);
5309 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5310 connector->base.id, connector->name);
5311 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5313 intel_display_power_get(dev_priv, aux_domain);
5315 /* Can't disconnect eDP */
5316 if (intel_dp_is_edp(intel_dp))
5317 status = edp_detect(intel_dp);
5318 else if (intel_digital_port_connected(encoder))
5319 status = intel_dp_detect_dpcd(intel_dp);
5321 status = connector_status_disconnected;
5323 if (status == connector_status_disconnected) {
5324 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5325 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5327 if (intel_dp->is_mst) {
5328 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5330 intel_dp->mst_mgr.mst_state);
5331 intel_dp->is_mst = false;
5332 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5339 if (intel_dp->reset_link_params) {
5340 /* Initial max link lane count */
5341 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5343 /* Initial max link rate */
5344 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5346 intel_dp->reset_link_params = false;
5349 intel_dp_print_rates(intel_dp);
5351 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5352 if (INTEL_GEN(dev_priv) >= 11)
5353 intel_dp_get_dsc_sink_cap(intel_dp);
5355 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5356 drm_dp_is_branch(intel_dp->dpcd));
5358 intel_dp_configure_mst(intel_dp);
5360 if (intel_dp->is_mst) {
5362 * If we are in MST mode then this connector
5363 * won't appear connected or have anything
5366 status = connector_status_disconnected;
5371 * Some external monitors do not signal loss of link synchronization
5372 * with an IRQ_HPD, so force a link status check.
5374 if (!intel_dp_is_edp(intel_dp)) {
5377 ret = intel_dp_retrain_link(encoder, ctx);
5379 intel_display_power_put(dev_priv, aux_domain);
5385 * Clearing NACK and defer counts to get their exact values
5386 * while reading EDID which are required by Compliance tests
5387 * 4.2.2.4 and 4.2.2.5
5389 intel_dp->aux.i2c_nack_count = 0;
5390 intel_dp->aux.i2c_defer_count = 0;
5392 intel_dp_set_edid(intel_dp);
5393 if (intel_dp_is_edp(intel_dp) ||
5394 to_intel_connector(connector)->detect_edid)
5395 status = connector_status_connected;
5397 intel_dp_check_service_irq(intel_dp);
5400 if (status != connector_status_connected && !intel_dp->is_mst)
5401 intel_dp_unset_edid(intel_dp);
5403 intel_display_power_put(dev_priv, aux_domain);
5408 intel_dp_force(struct drm_connector *connector)
5410 struct intel_dp *intel_dp = intel_attached_dp(connector);
5411 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5412 struct intel_encoder *intel_encoder = &dig_port->base;
5413 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5414 enum intel_display_power_domain aux_domain =
5415 intel_aux_power_domain(dig_port);
5417 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5418 connector->base.id, connector->name);
5419 intel_dp_unset_edid(intel_dp);
5421 if (connector->status != connector_status_connected)
5424 intel_display_power_get(dev_priv, aux_domain);
5426 intel_dp_set_edid(intel_dp);
5428 intel_display_power_put(dev_priv, aux_domain);
5431 static int intel_dp_get_modes(struct drm_connector *connector)
5433 struct intel_connector *intel_connector = to_intel_connector(connector);
5436 edid = intel_connector->detect_edid;
5438 int ret = intel_connector_update_modes(connector, edid);
5443 /* if eDP has no EDID, fall back to fixed mode */
5444 if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5445 intel_connector->panel.fixed_mode) {
5446 struct drm_display_mode *mode;
5448 mode = drm_mode_duplicate(connector->dev,
5449 intel_connector->panel.fixed_mode);
5451 drm_mode_probed_add(connector, mode);
5460 intel_dp_connector_register(struct drm_connector *connector)
5462 struct intel_dp *intel_dp = intel_attached_dp(connector);
5463 struct drm_device *dev = connector->dev;
5466 ret = intel_connector_register(connector);
5470 i915_debugfs_connector_add(connector);
5472 DRM_DEBUG_KMS("registering %s bus for %s\n",
5473 intel_dp->aux.name, connector->kdev->kobj.name);
5475 intel_dp->aux.dev = connector->kdev;
5476 ret = drm_dp_aux_register(&intel_dp->aux);
5478 drm_dp_cec_register_connector(&intel_dp->aux,
5479 connector->name, dev->dev);
5484 intel_dp_connector_unregister(struct drm_connector *connector)
5486 struct intel_dp *intel_dp = intel_attached_dp(connector);
5488 drm_dp_cec_unregister_connector(&intel_dp->aux);
5489 drm_dp_aux_unregister(&intel_dp->aux);
5490 intel_connector_unregister(connector);
5493 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5495 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5496 struct intel_dp *intel_dp = &intel_dig_port->dp;
5498 intel_dp_mst_encoder_cleanup(intel_dig_port);
5499 if (intel_dp_is_edp(intel_dp)) {
5500 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5502 * vdd might still be enabled do to the delayed vdd off.
5503 * Make sure vdd is actually turned off here.
5506 edp_panel_vdd_off_sync(intel_dp);
5507 pps_unlock(intel_dp);
5509 if (intel_dp->edp_notifier.notifier_call) {
5510 unregister_reboot_notifier(&intel_dp->edp_notifier);
5511 intel_dp->edp_notifier.notifier_call = NULL;
5515 intel_dp_aux_fini(intel_dp);
5517 drm_encoder_cleanup(encoder);
5518 kfree(intel_dig_port);
5521 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5523 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5525 if (!intel_dp_is_edp(intel_dp))
5529 * vdd might still be enabled do to the delayed vdd off.
5530 * Make sure vdd is actually turned off here.
5532 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5534 edp_panel_vdd_off_sync(intel_dp);
5535 pps_unlock(intel_dp);
5539 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5542 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5543 static const struct drm_dp_aux_msg msg = {
5544 .request = DP_AUX_NATIVE_WRITE,
5545 .address = DP_AUX_HDCP_AKSV,
5546 .size = DRM_HDCP_KSV_LEN,
5548 uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5552 /* Output An first, that's easy */
5553 dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5554 an, DRM_HDCP_AN_LEN);
5555 if (dpcd_ret != DRM_HDCP_AN_LEN) {
5556 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5558 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5562 * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5563 * order to get it on the wire, we need to create the AUX header as if
5564 * we were writing the data, and then tickle the hardware to output the
5565 * data once the header is sent out.
5567 intel_dp_aux_header(txbuf, &msg);
5569 ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5570 rxbuf, sizeof(rxbuf),
5571 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5573 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5575 } else if (ret == 0) {
5576 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5580 reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5581 return reply == DP_AUX_NATIVE_REPLY_ACK ? 0 : -EIO;
5584 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5588 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5590 if (ret != DRM_HDCP_KSV_LEN) {
5591 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5592 return ret >= 0 ? -EIO : ret;
5597 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5602 * For some reason the HDMI and DP HDCP specs call this register
5603 * definition by different names. In the HDMI spec, it's called BSTATUS,
5604 * but in DP it's called BINFO.
5606 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5607 bstatus, DRM_HDCP_BSTATUS_LEN);
5608 if (ret != DRM_HDCP_BSTATUS_LEN) {
5609 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5610 return ret >= 0 ? -EIO : ret;
5616 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5621 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5624 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
5625 return ret >= 0 ? -EIO : ret;
5632 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5633 bool *repeater_present)
5638 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5642 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5647 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5651 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5652 ri_prime, DRM_HDCP_RI_LEN);
5653 if (ret != DRM_HDCP_RI_LEN) {
5654 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
5655 return ret >= 0 ? -EIO : ret;
5661 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5666 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5669 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5670 return ret >= 0 ? -EIO : ret;
5672 *ksv_ready = bstatus & DP_BSTATUS_READY;
5677 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5678 int num_downstream, u8 *ksv_fifo)
5683 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5684 for (i = 0; i < num_downstream; i += 3) {
5685 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5686 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5687 DP_AUX_HDCP_KSV_FIFO,
5688 ksv_fifo + i * DRM_HDCP_KSV_LEN,
5691 DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
5693 return ret >= 0 ? -EIO : ret;
5700 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5705 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5708 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5709 DP_AUX_HDCP_V_PRIME(i), part,
5710 DRM_HDCP_V_PRIME_PART_LEN);
5711 if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5712 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5713 return ret >= 0 ? -EIO : ret;
5719 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5722 /* Not used for single stream DisplayPort setups */
5727 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5732 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5735 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5739 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5743 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5749 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5753 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5757 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
5758 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
5759 .read_bksv = intel_dp_hdcp_read_bksv,
5760 .read_bstatus = intel_dp_hdcp_read_bstatus,
5761 .repeater_present = intel_dp_hdcp_repeater_present,
5762 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
5763 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
5764 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
5765 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
5766 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
5767 .check_link = intel_dp_hdcp_check_link,
5768 .hdcp_capable = intel_dp_hdcp_capable,
5771 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5773 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5774 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5776 lockdep_assert_held(&dev_priv->pps_mutex);
5778 if (!edp_have_panel_vdd(intel_dp))
5782 * The VDD bit needs a power domain reference, so if the bit is
5783 * already enabled when we boot or resume, grab this reference and
5784 * schedule a vdd off, so we don't hold on to the reference
5787 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5788 intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
5790 edp_panel_vdd_schedule_off(intel_dp);
5793 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5795 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5796 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5799 if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
5800 encoder->port, &pipe))
5803 return INVALID_PIPE;
5806 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5808 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5809 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5810 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5812 if (!HAS_DDI(dev_priv))
5813 intel_dp->DP = I915_READ(intel_dp->output_reg);
5816 lspcon_resume(lspcon);
5818 intel_dp->reset_link_params = true;
5822 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5823 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5825 if (intel_dp_is_edp(intel_dp)) {
5826 /* Reinit the power sequencer, in case BIOS did something with it. */
5827 intel_dp_pps_init(intel_dp);
5828 intel_edp_panel_vdd_sanitize(intel_dp);
5831 pps_unlock(intel_dp);
5834 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5835 .force = intel_dp_force,
5836 .fill_modes = drm_helper_probe_single_connector_modes,
5837 .atomic_get_property = intel_digital_connector_atomic_get_property,
5838 .atomic_set_property = intel_digital_connector_atomic_set_property,
5839 .late_register = intel_dp_connector_register,
5840 .early_unregister = intel_dp_connector_unregister,
5841 .destroy = intel_connector_destroy,
5842 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5843 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5846 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5847 .detect_ctx = intel_dp_detect,
5848 .get_modes = intel_dp_get_modes,
5849 .mode_valid = intel_dp_mode_valid,
5850 .atomic_check = intel_digital_connector_atomic_check,
5853 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5854 .reset = intel_dp_encoder_reset,
5855 .destroy = intel_dp_encoder_destroy,
5859 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5861 struct intel_dp *intel_dp = &intel_dig_port->dp;
5862 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5863 enum irqreturn ret = IRQ_NONE;
5865 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5867 * vdd off can generate a long pulse on eDP which
5868 * would require vdd on to handle it, and thus we
5869 * would end up in an endless cycle of
5870 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5872 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5873 port_name(intel_dig_port->base.port));
5877 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5878 port_name(intel_dig_port->base.port),
5879 long_hpd ? "long" : "short");
5882 intel_dp->reset_link_params = true;
5886 intel_display_power_get(dev_priv,
5887 intel_aux_power_domain(intel_dig_port));
5889 if (intel_dp->is_mst) {
5890 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5892 * If we were in MST mode, and device is not
5893 * there, get out of MST mode
5895 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5896 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5897 intel_dp->is_mst = false;
5898 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5904 if (!intel_dp->is_mst) {
5907 handled = intel_dp_short_pulse(intel_dp);
5916 intel_display_power_put(dev_priv,
5917 intel_aux_power_domain(intel_dig_port));
5922 /* check the VBT to see whether the eDP is on another port */
5923 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5926 * eDP not supported on g4x. so bail out early just
5927 * for a bit extra safety in case the VBT is bonkers.
5929 if (INTEL_GEN(dev_priv) < 5)
5932 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5935 return intel_bios_is_port_edp(dev_priv, port);
5939 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5941 struct drm_i915_private *dev_priv = to_i915(connector->dev);
5942 enum port port = dp_to_dig_port(intel_dp)->base.port;
5944 if (!IS_G4X(dev_priv) && port != PORT_A)
5945 intel_attach_force_audio_property(connector);
5947 intel_attach_broadcast_rgb_property(connector);
5948 if (HAS_GMCH_DISPLAY(dev_priv))
5949 drm_connector_attach_max_bpc_property(connector, 6, 10);
5950 else if (INTEL_GEN(dev_priv) >= 5)
5951 drm_connector_attach_max_bpc_property(connector, 6, 12);
5953 if (intel_dp_is_edp(intel_dp)) {
5954 u32 allowed_scalers;
5956 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5957 if (!HAS_GMCH_DISPLAY(dev_priv))
5958 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5960 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5962 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5967 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5969 intel_dp->panel_power_off_time = ktime_get_boottime();
5970 intel_dp->last_power_on = jiffies;
5971 intel_dp->last_backlight_off = jiffies;
5975 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
5977 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5978 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5979 struct pps_registers regs;
5981 intel_pps_get_registers(intel_dp, ®s);
5983 /* Workaround: Need to write PP_CONTROL with the unlock key as
5984 * the very first thing. */
5985 pp_ctl = ironlake_get_pp_control(intel_dp);
5987 pp_on = I915_READ(regs.pp_on);
5988 pp_off = I915_READ(regs.pp_off);
5989 if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
5990 !HAS_PCH_ICP(dev_priv)) {
5991 I915_WRITE(regs.pp_ctrl, pp_ctl);
5992 pp_div = I915_READ(regs.pp_div);
5995 /* Pull timing values out of registers */
5996 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5997 PANEL_POWER_UP_DELAY_SHIFT;
5999 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
6000 PANEL_LIGHT_ON_DELAY_SHIFT;
6002 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
6003 PANEL_LIGHT_OFF_DELAY_SHIFT;
6005 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
6006 PANEL_POWER_DOWN_DELAY_SHIFT;
6008 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
6009 HAS_PCH_ICP(dev_priv)) {
6010 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
6011 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
6013 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
6014 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
6019 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6021 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6023 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6027 intel_pps_verify_state(struct intel_dp *intel_dp)
6029 struct edp_power_seq hw;
6030 struct edp_power_seq *sw = &intel_dp->pps_delays;
6032 intel_pps_readout_hw_state(intel_dp, &hw);
6034 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6035 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6036 DRM_ERROR("PPS state mismatch\n");
6037 intel_pps_dump_state("sw", sw);
6038 intel_pps_dump_state("hw", &hw);
6043 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6045 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6046 struct edp_power_seq cur, vbt, spec,
6047 *final = &intel_dp->pps_delays;
6049 lockdep_assert_held(&dev_priv->pps_mutex);
6051 /* already initialized? */
6052 if (final->t11_t12 != 0)
6055 intel_pps_readout_hw_state(intel_dp, &cur);
6057 intel_pps_dump_state("cur", &cur);
6059 vbt = dev_priv->vbt.edp.pps;
6060 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6061 * of 500ms appears to be too short. Ocassionally the panel
6062 * just fails to power back on. Increasing the delay to 800ms
6063 * seems sufficient to avoid this problem.
6065 if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6066 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6067 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6070 /* T11_T12 delay is special and actually in units of 100ms, but zero
6071 * based in the hw (so we need to add 100 ms). But the sw vbt
6072 * table multiplies it with 1000 to make it in units of 100usec,
6074 vbt.t11_t12 += 100 * 10;
6076 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6077 * our hw here, which are all in 100usec. */
6078 spec.t1_t3 = 210 * 10;
6079 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6080 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6081 spec.t10 = 500 * 10;
6082 /* This one is special and actually in units of 100ms, but zero
6083 * based in the hw (so we need to add 100 ms). But the sw vbt
6084 * table multiplies it with 1000 to make it in units of 100usec,
6086 spec.t11_t12 = (510 + 100) * 10;
6088 intel_pps_dump_state("vbt", &vbt);
6090 /* Use the max of the register settings and vbt. If both are
6091 * unset, fall back to the spec limits. */
6092 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
6094 max(cur.field, vbt.field))
6095 assign_final(t1_t3);
6099 assign_final(t11_t12);
6102 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
6103 intel_dp->panel_power_up_delay = get_delay(t1_t3);
6104 intel_dp->backlight_on_delay = get_delay(t8);
6105 intel_dp->backlight_off_delay = get_delay(t9);
6106 intel_dp->panel_power_down_delay = get_delay(t10);
6107 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6110 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6111 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
6112 intel_dp->panel_power_cycle_delay);
6114 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6115 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
6118 * We override the HW backlight delays to 1 because we do manual waits
6119 * on them. For T8, even BSpec recommends doing it. For T9, if we
6120 * don't do this, we'll end up waiting for the backlight off delay
6121 * twice: once when we do the manual sleep, and once when we disable
6122 * the panel and wait for the PP_STATUS bit to become zero.
6128 * HW has only a 100msec granularity for t11_t12 so round it up
6131 final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6135 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6136 bool force_disable_vdd)
6138 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6139 u32 pp_on, pp_off, pp_div, port_sel = 0;
6140 int div = dev_priv->rawclk_freq / 1000;
6141 struct pps_registers regs;
6142 enum port port = dp_to_dig_port(intel_dp)->base.port;
6143 const struct edp_power_seq *seq = &intel_dp->pps_delays;
6145 lockdep_assert_held(&dev_priv->pps_mutex);
6147 intel_pps_get_registers(intel_dp, ®s);
6150 * On some VLV machines the BIOS can leave the VDD
6151 * enabled even on power sequencers which aren't
6152 * hooked up to any port. This would mess up the
6153 * power domain tracking the first time we pick
6154 * one of these power sequencers for use since
6155 * edp_panel_vdd_on() would notice that the VDD was
6156 * already on and therefore wouldn't grab the power
6157 * domain reference. Disable VDD first to avoid this.
6158 * This also avoids spuriously turning the VDD on as
6159 * soon as the new power sequencer gets initialized.
6161 if (force_disable_vdd) {
6162 u32 pp = ironlake_get_pp_control(intel_dp);
6164 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
6166 if (pp & EDP_FORCE_VDD)
6167 DRM_DEBUG_KMS("VDD already on, disabling first\n");
6169 pp &= ~EDP_FORCE_VDD;
6171 I915_WRITE(regs.pp_ctrl, pp);
6174 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
6175 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
6176 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
6177 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
6178 /* Compute the divisor for the pp clock, simply match the Bspec
6180 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
6181 HAS_PCH_ICP(dev_priv)) {
6182 pp_div = I915_READ(regs.pp_ctrl);
6183 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
6184 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
6185 << BXT_POWER_CYCLE_DELAY_SHIFT);
6187 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
6188 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
6189 << PANEL_POWER_CYCLE_DELAY_SHIFT);
6192 /* Haswell doesn't have any port selection bits for the panel
6193 * power sequencer any more. */
6194 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6195 port_sel = PANEL_PORT_SELECT_VLV(port);
6196 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6199 port_sel = PANEL_PORT_SELECT_DPA;
6202 port_sel = PANEL_PORT_SELECT_DPC;
6205 port_sel = PANEL_PORT_SELECT_DPD;
6215 I915_WRITE(regs.pp_on, pp_on);
6216 I915_WRITE(regs.pp_off, pp_off);
6217 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
6218 HAS_PCH_ICP(dev_priv))
6219 I915_WRITE(regs.pp_ctrl, pp_div);
6221 I915_WRITE(regs.pp_div, pp_div);
6223 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6224 I915_READ(regs.pp_on),
6225 I915_READ(regs.pp_off),
6226 (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
6227 HAS_PCH_ICP(dev_priv)) ?
6228 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
6229 I915_READ(regs.pp_div));
6232 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6234 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6236 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6237 vlv_initial_power_sequencer_setup(intel_dp);
6239 intel_dp_init_panel_power_sequencer(intel_dp);
6240 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6245 * intel_dp_set_drrs_state - program registers for RR switch to take effect
6246 * @dev_priv: i915 device
6247 * @crtc_state: a pointer to the active intel_crtc_state
6248 * @refresh_rate: RR to be programmed
6250 * This function gets called when refresh rate (RR) has to be changed from
6251 * one frequency to another. Switches can be between high and low RR
6252 * supported by the panel or to any other RR based on media playback (in
6253 * this case, RR value needs to be passed from user space).
6255 * The caller of this function needs to take a lock on dev_priv->drrs.
6257 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6258 const struct intel_crtc_state *crtc_state,
6261 struct intel_encoder *encoder;
6262 struct intel_digital_port *dig_port = NULL;
6263 struct intel_dp *intel_dp = dev_priv->drrs.dp;
6264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6265 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6267 if (refresh_rate <= 0) {
6268 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6272 if (intel_dp == NULL) {
6273 DRM_DEBUG_KMS("DRRS not supported.\n");
6277 dig_port = dp_to_dig_port(intel_dp);
6278 encoder = &dig_port->base;
6281 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6285 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6286 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6290 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6292 index = DRRS_LOW_RR;
6294 if (index == dev_priv->drrs.refresh_rate_type) {
6296 "DRRS requested for previously set RR...ignoring\n");
6300 if (!crtc_state->base.active) {
6301 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6305 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6308 intel_dp_set_m_n(crtc_state, M1_N1);
6311 intel_dp_set_m_n(crtc_state, M2_N2);
6315 DRM_ERROR("Unsupported refreshrate type\n");
6317 } else if (INTEL_GEN(dev_priv) > 6) {
6318 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6321 val = I915_READ(reg);
6322 if (index > DRRS_HIGH_RR) {
6323 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6324 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6326 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6328 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6329 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6331 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6333 I915_WRITE(reg, val);
6336 dev_priv->drrs.refresh_rate_type = index;
6338 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6342 * intel_edp_drrs_enable - init drrs struct if supported
6343 * @intel_dp: DP struct
6344 * @crtc_state: A pointer to the active crtc state.
6346 * Initializes frontbuffer_bits and drrs.dp
6348 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6349 const struct intel_crtc_state *crtc_state)
6351 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6353 if (!crtc_state->has_drrs) {
6354 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6358 if (dev_priv->psr.enabled) {
6359 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6363 mutex_lock(&dev_priv->drrs.mutex);
6364 if (WARN_ON(dev_priv->drrs.dp)) {
6365 DRM_ERROR("DRRS already enabled\n");
6369 dev_priv->drrs.busy_frontbuffer_bits = 0;
6371 dev_priv->drrs.dp = intel_dp;
6374 mutex_unlock(&dev_priv->drrs.mutex);
6378 * intel_edp_drrs_disable - Disable DRRS
6379 * @intel_dp: DP struct
6380 * @old_crtc_state: Pointer to old crtc_state.
6383 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6384 const struct intel_crtc_state *old_crtc_state)
6386 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6388 if (!old_crtc_state->has_drrs)
6391 mutex_lock(&dev_priv->drrs.mutex);
6392 if (!dev_priv->drrs.dp) {
6393 mutex_unlock(&dev_priv->drrs.mutex);
6397 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6398 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
6399 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
6401 dev_priv->drrs.dp = NULL;
6402 mutex_unlock(&dev_priv->drrs.mutex);
6404 cancel_delayed_work_sync(&dev_priv->drrs.work);
6407 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6409 struct drm_i915_private *dev_priv =
6410 container_of(work, typeof(*dev_priv), drrs.work.work);
6411 struct intel_dp *intel_dp;
6413 mutex_lock(&dev_priv->drrs.mutex);
6415 intel_dp = dev_priv->drrs.dp;
6421 * The delayed work can race with an invalidate hence we need to
6425 if (dev_priv->drrs.busy_frontbuffer_bits)
6428 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6429 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6431 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6432 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
6436 mutex_unlock(&dev_priv->drrs.mutex);
6440 * intel_edp_drrs_invalidate - Disable Idleness DRRS
6441 * @dev_priv: i915 device
6442 * @frontbuffer_bits: frontbuffer plane tracking bits
6444 * This function gets called everytime rendering on the given planes start.
6445 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6447 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6449 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6450 unsigned int frontbuffer_bits)
6452 struct drm_crtc *crtc;
6455 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6458 cancel_delayed_work(&dev_priv->drrs.work);
6460 mutex_lock(&dev_priv->drrs.mutex);
6461 if (!dev_priv->drrs.dp) {
6462 mutex_unlock(&dev_priv->drrs.mutex);
6466 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6467 pipe = to_intel_crtc(crtc)->pipe;
6469 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6470 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6472 /* invalidate means busy screen hence upclock */
6473 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6474 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6475 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6477 mutex_unlock(&dev_priv->drrs.mutex);
6481 * intel_edp_drrs_flush - Restart Idleness DRRS
6482 * @dev_priv: i915 device
6483 * @frontbuffer_bits: frontbuffer plane tracking bits
6485 * This function gets called every time rendering on the given planes has
6486 * completed or flip on a crtc is completed. So DRRS should be upclocked
6487 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6488 * if no other planes are dirty.
6490 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6492 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6493 unsigned int frontbuffer_bits)
6495 struct drm_crtc *crtc;
6498 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6501 cancel_delayed_work(&dev_priv->drrs.work);
6503 mutex_lock(&dev_priv->drrs.mutex);
6504 if (!dev_priv->drrs.dp) {
6505 mutex_unlock(&dev_priv->drrs.mutex);
6509 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6510 pipe = to_intel_crtc(crtc)->pipe;
6512 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6513 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6515 /* flush means busy screen hence upclock */
6516 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6517 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6518 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6521 * flush also means no more activity hence schedule downclock, if all
6522 * other fbs are quiescent too
6524 if (!dev_priv->drrs.busy_frontbuffer_bits)
6525 schedule_delayed_work(&dev_priv->drrs.work,
6526 msecs_to_jiffies(1000));
6527 mutex_unlock(&dev_priv->drrs.mutex);
6531 * DOC: Display Refresh Rate Switching (DRRS)
6533 * Display Refresh Rate Switching (DRRS) is a power conservation feature
6534 * which enables swtching between low and high refresh rates,
6535 * dynamically, based on the usage scenario. This feature is applicable
6536 * for internal panels.
6538 * Indication that the panel supports DRRS is given by the panel EDID, which
6539 * would list multiple refresh rates for one resolution.
6541 * DRRS is of 2 types - static and seamless.
6542 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6543 * (may appear as a blink on screen) and is used in dock-undock scenario.
6544 * Seamless DRRS involves changing RR without any visual effect to the user
6545 * and can be used during normal system usage. This is done by programming
6546 * certain registers.
6548 * Support for static/seamless DRRS may be indicated in the VBT based on
6549 * inputs from the panel spec.
6551 * DRRS saves power by switching to low RR based on usage scenarios.
6553 * The implementation is based on frontbuffer tracking implementation. When
6554 * there is a disturbance on the screen triggered by user activity or a periodic
6555 * system activity, DRRS is disabled (RR is changed to high RR). When there is
6556 * no movement on screen, after a timeout of 1 second, a switch to low RR is
6559 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6560 * and intel_edp_drrs_flush() are called.
6562 * DRRS can be further extended to support other internal panels and also
6563 * the scenario of video playback wherein RR is set based on the rate
6564 * requested by userspace.
6568 * intel_dp_drrs_init - Init basic DRRS work and mutex.
6569 * @connector: eDP connector
6570 * @fixed_mode: preferred mode of panel
6572 * This function is called only once at driver load to initialize basic
6576 * Downclock mode if panel supports it, else return NULL.
6577 * DRRS support is determined by the presence of downclock mode (apart
6578 * from VBT setting).
6580 static struct drm_display_mode *
6581 intel_dp_drrs_init(struct intel_connector *connector,
6582 struct drm_display_mode *fixed_mode)
6584 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6585 struct drm_display_mode *downclock_mode = NULL;
6587 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6588 mutex_init(&dev_priv->drrs.mutex);
6590 if (INTEL_GEN(dev_priv) <= 6) {
6591 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6595 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6596 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6600 downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
6603 if (!downclock_mode) {
6604 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6608 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6610 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6611 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6612 return downclock_mode;
6615 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6616 struct intel_connector *intel_connector)
6618 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6619 struct drm_device *dev = &dev_priv->drm;
6620 struct drm_connector *connector = &intel_connector->base;
6621 struct drm_display_mode *fixed_mode = NULL;
6622 struct drm_display_mode *downclock_mode = NULL;
6624 struct drm_display_mode *scan;
6626 enum pipe pipe = INVALID_PIPE;
6628 if (!intel_dp_is_edp(intel_dp))
6631 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
6634 * On IBX/CPT we may get here with LVDS already registered. Since the
6635 * driver uses the only internal power sequencer available for both
6636 * eDP and LVDS bail out early in this case to prevent interfering
6637 * with an already powered-on LVDS power sequencer.
6639 if (intel_get_lvds_encoder(&dev_priv->drm)) {
6640 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6641 DRM_INFO("LVDS was detected, not registering eDP\n");
6648 intel_dp_init_panel_power_timestamps(intel_dp);
6649 intel_dp_pps_init(intel_dp);
6650 intel_edp_panel_vdd_sanitize(intel_dp);
6652 pps_unlock(intel_dp);
6654 /* Cache DPCD and EDID for edp. */
6655 has_dpcd = intel_edp_init_dpcd(intel_dp);
6658 /* if this fails, presume the device is a ghost */
6659 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6663 mutex_lock(&dev->mode_config.mutex);
6664 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6666 if (drm_add_edid_modes(connector, edid)) {
6667 drm_connector_update_edid_property(connector,
6671 edid = ERR_PTR(-EINVAL);
6674 edid = ERR_PTR(-ENOENT);
6676 intel_connector->edid = edid;
6678 /* prefer fixed mode from EDID if available */
6679 list_for_each_entry(scan, &connector->probed_modes, head) {
6680 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
6681 fixed_mode = drm_mode_duplicate(dev, scan);
6682 downclock_mode = intel_dp_drrs_init(
6683 intel_connector, fixed_mode);
6688 /* fallback to VBT if available for eDP */
6689 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
6690 fixed_mode = drm_mode_duplicate(dev,
6691 dev_priv->vbt.lfp_lvds_vbt_mode);
6693 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
6694 connector->display_info.width_mm = fixed_mode->width_mm;
6695 connector->display_info.height_mm = fixed_mode->height_mm;
6698 mutex_unlock(&dev->mode_config.mutex);
6700 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6701 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
6702 register_reboot_notifier(&intel_dp->edp_notifier);
6705 * Figure out the current pipe for the initial backlight setup.
6706 * If the current pipe isn't valid, try the PPS pipe, and if that
6707 * fails just assume pipe A.
6709 pipe = vlv_active_pipe(intel_dp);
6711 if (pipe != PIPE_A && pipe != PIPE_B)
6712 pipe = intel_dp->pps_pipe;
6714 if (pipe != PIPE_A && pipe != PIPE_B)
6717 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6721 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6722 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6723 intel_panel_setup_backlight(connector, pipe);
6726 drm_connector_init_panel_orientation_property(
6727 connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
6732 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6734 * vdd might still be enabled do to the delayed vdd off.
6735 * Make sure vdd is actually turned off here.
6738 edp_panel_vdd_off_sync(intel_dp);
6739 pps_unlock(intel_dp);
6744 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6746 struct intel_connector *intel_connector;
6747 struct drm_connector *connector;
6749 intel_connector = container_of(work, typeof(*intel_connector),
6750 modeset_retry_work);
6751 connector = &intel_connector->base;
6752 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6755 /* Grab the locks before changing connector property*/
6756 mutex_lock(&connector->dev->mode_config.mutex);
6757 /* Set connector link status to BAD and send a Uevent to notify
6758 * userspace to do a modeset.
6760 drm_connector_set_link_status_property(connector,
6761 DRM_MODE_LINK_STATUS_BAD);
6762 mutex_unlock(&connector->dev->mode_config.mutex);
6763 /* Send Hotplug uevent so userspace can reprobe */
6764 drm_kms_helper_hotplug_event(connector->dev);
6768 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6769 struct intel_connector *intel_connector)
6771 struct drm_connector *connector = &intel_connector->base;
6772 struct intel_dp *intel_dp = &intel_dig_port->dp;
6773 struct intel_encoder *intel_encoder = &intel_dig_port->base;
6774 struct drm_device *dev = intel_encoder->base.dev;
6775 struct drm_i915_private *dev_priv = to_i915(dev);
6776 enum port port = intel_encoder->port;
6779 /* Initialize the work for modeset in case of link train failure */
6780 INIT_WORK(&intel_connector->modeset_retry_work,
6781 intel_dp_modeset_retry_work_fn);
6783 if (WARN(intel_dig_port->max_lanes < 1,
6784 "Not enough lanes (%d) for DP on port %c\n",
6785 intel_dig_port->max_lanes, port_name(port)))
6788 intel_dp_set_source_rates(intel_dp);
6790 intel_dp->reset_link_params = true;
6791 intel_dp->pps_pipe = INVALID_PIPE;
6792 intel_dp->active_pipe = INVALID_PIPE;
6794 /* intel_dp vfuncs */
6795 if (HAS_DDI(dev_priv))
6796 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6798 /* Preserve the current hw state. */
6799 intel_dp->DP = I915_READ(intel_dp->output_reg);
6800 intel_dp->attached_connector = intel_connector;
6802 if (intel_dp_is_port_edp(dev_priv, port))
6803 type = DRM_MODE_CONNECTOR_eDP;
6805 type = DRM_MODE_CONNECTOR_DisplayPort;
6807 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6808 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6811 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6812 * for DP the encoder type can be set by the caller to
6813 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6815 if (type == DRM_MODE_CONNECTOR_eDP)
6816 intel_encoder->type = INTEL_OUTPUT_EDP;
6818 /* eDP only on port B and/or C on vlv/chv */
6819 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6820 intel_dp_is_edp(intel_dp) &&
6821 port != PORT_B && port != PORT_C))
6824 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6825 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6828 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6829 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6831 if (!HAS_GMCH_DISPLAY(dev_priv))
6832 connector->interlace_allowed = true;
6833 connector->doublescan_allowed = 0;
6835 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
6837 intel_dp_aux_init(intel_dp);
6839 intel_connector_attach_encoder(intel_connector, intel_encoder);
6841 if (HAS_DDI(dev_priv))
6842 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6844 intel_connector->get_hw_state = intel_connector_get_hw_state;
6846 /* init MST on ports that can support it */
6847 if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6848 (port == PORT_B || port == PORT_C ||
6849 port == PORT_D || port == PORT_F))
6850 intel_dp_mst_encoder_init(intel_dig_port,
6851 intel_connector->base.base.id);
6853 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6854 intel_dp_aux_fini(intel_dp);
6855 intel_dp_mst_encoder_cleanup(intel_dig_port);
6859 intel_dp_add_properties(intel_dp, connector);
6861 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6862 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
6864 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6867 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6868 * 0xd. Failure to do so will result in spurious interrupts being
6869 * generated on the port when a cable is not attached.
6871 if (IS_G45(dev_priv)) {
6872 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6873 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6879 drm_connector_cleanup(connector);
6884 bool intel_dp_init(struct drm_i915_private *dev_priv,
6885 i915_reg_t output_reg,
6888 struct intel_digital_port *intel_dig_port;
6889 struct intel_encoder *intel_encoder;
6890 struct drm_encoder *encoder;
6891 struct intel_connector *intel_connector;
6893 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6894 if (!intel_dig_port)
6897 intel_connector = intel_connector_alloc();
6898 if (!intel_connector)
6899 goto err_connector_alloc;
6901 intel_encoder = &intel_dig_port->base;
6902 encoder = &intel_encoder->base;
6904 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6905 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6906 "DP %c", port_name(port)))
6907 goto err_encoder_init;
6909 intel_encoder->hotplug = intel_dp_hotplug;
6910 intel_encoder->compute_config = intel_dp_compute_config;
6911 intel_encoder->get_hw_state = intel_dp_get_hw_state;
6912 intel_encoder->get_config = intel_dp_get_config;
6913 intel_encoder->suspend = intel_dp_encoder_suspend;
6914 if (IS_CHERRYVIEW(dev_priv)) {
6915 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6916 intel_encoder->pre_enable = chv_pre_enable_dp;
6917 intel_encoder->enable = vlv_enable_dp;
6918 intel_encoder->disable = vlv_disable_dp;
6919 intel_encoder->post_disable = chv_post_disable_dp;
6920 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6921 } else if (IS_VALLEYVIEW(dev_priv)) {
6922 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6923 intel_encoder->pre_enable = vlv_pre_enable_dp;
6924 intel_encoder->enable = vlv_enable_dp;
6925 intel_encoder->disable = vlv_disable_dp;
6926 intel_encoder->post_disable = vlv_post_disable_dp;
6928 intel_encoder->pre_enable = g4x_pre_enable_dp;
6929 intel_encoder->enable = g4x_enable_dp;
6930 intel_encoder->disable = g4x_disable_dp;
6931 intel_encoder->post_disable = g4x_post_disable_dp;
6934 intel_dig_port->dp.output_reg = output_reg;
6935 intel_dig_port->max_lanes = 4;
6937 intel_encoder->type = INTEL_OUTPUT_DP;
6938 intel_encoder->power_domain = intel_port_to_power_domain(port);
6939 if (IS_CHERRYVIEW(dev_priv)) {
6941 intel_encoder->crtc_mask = 1 << 2;
6943 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6945 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6947 intel_encoder->cloneable = 0;
6948 intel_encoder->port = port;
6950 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6953 intel_infoframe_init(intel_dig_port);
6955 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
6956 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6957 goto err_init_connector;
6962 drm_encoder_cleanup(encoder);
6964 kfree(intel_connector);
6965 err_connector_alloc:
6966 kfree(intel_dig_port);
6970 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6972 struct intel_encoder *encoder;
6974 for_each_intel_encoder(&dev_priv->drm, encoder) {
6975 struct intel_dp *intel_dp;
6977 if (encoder->type != INTEL_OUTPUT_DDI)
6980 intel_dp = enc_to_intel_dp(&encoder->base);
6982 if (!intel_dp->can_mst)
6985 if (intel_dp->is_mst)
6986 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6990 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6992 struct intel_encoder *encoder;
6994 for_each_intel_encoder(&dev_priv->drm, encoder) {
6995 struct intel_dp *intel_dp;
6998 if (encoder->type != INTEL_OUTPUT_DDI)
7001 intel_dp = enc_to_intel_dp(&encoder->base);
7003 if (!intel_dp->can_mst)
7006 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
7008 intel_dp_check_mst_status(intel_dp);