drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/reboot.h>
  32 #include <linux/slab.h>
  33 #include <linux/types.h>
  34
  35 #include <asm/byteorder.h>
  36
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_crtc.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/i915_drm.h>
  44
  45 #include "i915_debugfs.h"
  46 #include "i915_drv.h"
  47 #include "intel_atomic.h"
  48 #include "intel_audio.h"
  49 #include "intel_connector.h"
  50 #include "intel_ddi.h"
  51 #include "intel_dp.h"
  52 #include "intel_dp_link_training.h"
  53 #include "intel_dp_mst.h"
  54 #include "intel_dpio_phy.h"
  55 #include "intel_drv.h"
  56 #include "intel_fifo_underrun.h"
  57 #include "intel_hdcp.h"
  58 #include "intel_hdmi.h"
  59 #include "intel_hotplug.h"
  60 #include "intel_lspcon.h"
  61 #include "intel_lvds.h"
  62 #include "intel_panel.h"
  63 #include "intel_psr.h"
  64 #include "intel_sideband.h"
  65 #include "intel_vdsc.h"
  66
  67 #define DP_DPRX_ESI_LEN 14
  68
  69 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
  70 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER      61440
  71 #define DP_DSC_MIN_SUPPORTED_BPC                8
  72 #define DP_DSC_MAX_SUPPORTED_BPC                10
  73
  74 /* DP DSC throughput values used for slice count calculations KPixels/s */
  75 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  76 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  77 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  78
  79 /* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
  80 #define DP_DSC_FEC_OVERHEAD_FACTOR              976
  81
  82 /* Compliance test status bits  */
  83 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  84 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  85 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  86 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  87
  88 struct dp_link_dpll {
  89         int clock;
  90         struct dpll dpll;
  91 };
  92
  93 static const struct dp_link_dpll g4x_dpll[] = {
  94         { 162000,
  95                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  96         { 270000,
  97                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  98 };
  99
 100 static const struct dp_link_dpll pch_dpll[] = {
 101         { 162000,
 102                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
 103         { 270000,
 104                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
 105 };
 106
 107 static const struct dp_link_dpll vlv_dpll[] = {
 108         { 162000,
 109                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 110         { 270000,
 111                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 112 };
 113
 114 /*
 115  * CHV supports eDP 1.4 that have  more link rates.
 116  * Below only provides the fixed rate but exclude variable rate.
 117  */
 118 static const struct dp_link_dpll chv_dpll[] = {
 119         /*
 120          * CHV requires to program fractional division for m2.
 121          * m2 is stored in fixed point format using formula below
 122          * (m2_int << 22) | m2_fraction
 123          */
 124         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 125                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 126         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 127                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 128 };
 129
 130 /* Constants for DP DSC configurations */
 131 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 132
 133 /* With Single pipe configuration, HW is capable of supporting maximum
 134  * of 4 slices per line.
 135  */
 136 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 137
 138 /**
 139  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 140  * @intel_dp: DP struct
 141  *
 142  * If a CPU or PCH DP output is attached to an eDP panel, this function
 143  * will return true, and false otherwise.
 144  */
 145 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 146 {
 147         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 148
 149         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 150 }
 151
 152 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 153 {
 154         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 155 }
 156
 157 static void intel_dp_link_down(struct intel_encoder *encoder,
 158                                const struct intel_crtc_state *old_crtc_state);
 159 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 160 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 161 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 162                                            const struct intel_crtc_state *crtc_state);
 163 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 164                                       enum pipe pipe);
 165 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 166
 167 /* update sink rates from dpcd */
 168 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 169 {
 170         static const int dp_rates[] = {
 171                 162000, 270000, 540000, 810000
 172         };
 173         int i, max_rate;
 174
 175         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 176
 177         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 178                 if (dp_rates[i] > max_rate)
 179                         break;
 180                 intel_dp->sink_rates[i] = dp_rates[i];
 181         }
 182
 183         intel_dp->num_sink_rates = i;
 184 }
 185
 186 /* Get length of rates array potentially limited by max_rate. */
 187 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 188 {
 189         int i;
 190
 191         /* Limit results by potentially reduced max rate */
 192         for (i = 0; i < len; i++) {
 193                 if (rates[len - i - 1] <= max_rate)
 194                         return len - i;
 195         }
 196
 197         return 0;
 198 }
 199
 200 /* Get length of common rates array potentially limited by max_rate. */
 201 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 202                                           int max_rate)
 203 {
 204         return intel_dp_rate_limit_len(intel_dp->common_rates,
 205                                        intel_dp->num_common_rates, max_rate);
 206 }
 207
 208 /* Theoretical max between source and sink */
 209 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 210 {
 211         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 212 }
 213
 214 static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
 215 {
 216         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 217         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 218         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
 219         intel_wakeref_t wakeref;
 220         u32 lane_info;
 221
 222         if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
 223                 return 4;
 224
 225         lane_info = 0;
 226         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
 227                 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
 228                              DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
 229                                 DP_LANE_ASSIGNMENT_SHIFT(tc_port);
 230
 231         switch (lane_info) {
 232         default:
 233                 MISSING_CASE(lane_info);
 234         case 1:
 235         case 2:
 236         case 4:
 237         case 8:
 238                 return 1;
 239         case 3:
 240         case 12:
 241                 return 2;
 242         case 15:
 243                 return 4;
 244         }
 245 }
 246
 247 /* Theoretical max between source and sink */
 248 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 249 {
 250         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 251         int source_max = intel_dig_port->max_lanes;
 252         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 253         int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
 254
 255         return min3(source_max, sink_max, fia_max);
 256 }
 257
 258 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 259 {
 260         return intel_dp->max_link_lane_count;
 261 }
 262
 263 int
 264 intel_dp_link_required(int pixel_clock, int bpp)
 265 {
 266         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 267         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 268 }
 269
 270 int
 271 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 272 {
 273         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 274          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 275          * is transmitted every LS_Clk per lane, there is no need to account for
 276          * the channel encoding that is done in the PHY layer here.
 277          */
 278
 279         return max_link_clock * max_lanes;
 280 }
 281
 282 static int
 283 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 284 {
 285         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 286         struct intel_encoder *encoder = &intel_dig_port->base;
 287         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 288         int max_dotclk = dev_priv->max_dotclk_freq;
 289         int ds_max_dotclk;
 290
 291         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 292
 293         if (type != DP_DS_PORT_TYPE_VGA)
 294                 return max_dotclk;
 295
 296         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 297                                                     intel_dp->downstream_ports);
 298
 299         if (ds_max_dotclk != 0)
 300                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 301
 302         return max_dotclk;
 303 }
 304
 305 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 306 {
 307         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 308         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 309         enum port port = dig_port->base.port;
 310
 311         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 312
 313         /* Low voltage SKUs are limited to max of 5.4G */
 314         if (voltage == VOLTAGE_INFO_0_85V)
 315                 return 540000;
 316
 317         /* For this SKU 8.1G is supported in all ports */
 318         if (IS_CNL_WITH_PORT_F(dev_priv))
 319                 return 810000;
 320
 321         /* For other SKUs, max rate on ports A and D is 5.4G */
 322         if (port == PORT_A || port == PORT_D)
 323                 return 540000;
 324
 325         return 810000;
 326 }
 327
 328 static int icl_max_source_rate(struct intel_dp *intel_dp)
 329 {
 330         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 331         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 332         enum port port = dig_port->base.port;
 333
 334         if (intel_port_is_combophy(dev_priv, port) &&
 335             !intel_dp_is_edp(intel_dp))
 336                 return 540000;
 337
 338         return 810000;
 339 }
 340
 341 static void
 342 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 343 {
 344         /* The values must be in increasing order */
 345         static const int cnl_rates[] = {
 346                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 347         };
 348         static const int bxt_rates[] = {
 349                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 350         };
 351         static const int skl_rates[] = {
 352                 162000, 216000, 270000, 324000, 432000, 540000
 353         };
 354         static const int hsw_rates[] = {
 355                 162000, 270000, 540000
 356         };
 357         static const int g4x_rates[] = {
 358                 162000, 270000
 359         };
 360         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 361         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 362         const struct ddi_vbt_port_info *info =
 363                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 364         const int *source_rates;
 365         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 366
 367         /* This should only be done once */
 368         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 369
 370         if (INTEL_GEN(dev_priv) >= 10) {
 371                 source_rates = cnl_rates;
 372                 size = ARRAY_SIZE(cnl_rates);
 373                 if (IS_GEN(dev_priv, 10))
 374                         max_rate = cnl_max_source_rate(intel_dp);
 375                 else
 376                         max_rate = icl_max_source_rate(intel_dp);
 377         } else if (IS_GEN9_LP(dev_priv)) {
 378                 source_rates = bxt_rates;
 379                 size = ARRAY_SIZE(bxt_rates);
 380         } else if (IS_GEN9_BC(dev_priv)) {
 381                 source_rates = skl_rates;
 382                 size = ARRAY_SIZE(skl_rates);
 383         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 384                    IS_BROADWELL(dev_priv)) {
 385                 source_rates = hsw_rates;
 386                 size = ARRAY_SIZE(hsw_rates);
 387         } else {
 388                 source_rates = g4x_rates;
 389                 size = ARRAY_SIZE(g4x_rates);
 390         }
 391
 392         if (max_rate && vbt_max_rate)
 393                 max_rate = min(max_rate, vbt_max_rate);
 394         else if (vbt_max_rate)
 395                 max_rate = vbt_max_rate;
 396
 397         if (max_rate)
 398                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 399
 400         intel_dp->source_rates = source_rates;
 401         intel_dp->num_source_rates = size;
 402 }
 403
 404 static int intersect_rates(const int *source_rates, int source_len,
 405                            const int *sink_rates, int sink_len,
 406                            int *common_rates)
 407 {
 408         int i = 0, j = 0, k = 0;
 409
 410         while (i < source_len && j < sink_len) {
 411                 if (source_rates[i] == sink_rates[j]) {
 412                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 413                                 return k;
 414                         common_rates[k] = source_rates[i];
 415                         ++k;
 416                         ++i;
 417                         ++j;
 418                 } else if (source_rates[i] < sink_rates[j]) {
 419                         ++i;
 420                 } else {
 421                         ++j;
 422                 }
 423         }
 424         return k;
 425 }
 426
 427 /* return index of rate in rates array, or -1 if not found */
 428 static int intel_dp_rate_index(const int *rates, int len, int rate)
 429 {
 430         int i;
 431
 432         for (i = 0; i < len; i++)
 433                 if (rate == rates[i])
 434                         return i;
 435
 436         return -1;
 437 }
 438
 439 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 440 {
 441         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 442
 443         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 444                                                      intel_dp->num_source_rates,
 445                                                      intel_dp->sink_rates,
 446                                                      intel_dp->num_sink_rates,
 447                                                      intel_dp->common_rates);
 448
 449         /* Paranoia, there should always be something in common. */
 450         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 451                 intel_dp->common_rates[0] = 162000;
 452                 intel_dp->num_common_rates = 1;
 453         }
 454 }
 455
 456 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 457                                        u8 lane_count)
 458 {
 459         /*
 460          * FIXME: we need to synchronize the current link parameters with
 461          * hardware readout. Currently fast link training doesn't work on
 462          * boot-up.
 463          */
 464         if (link_rate == 0 ||
 465             link_rate > intel_dp->max_link_rate)
 466                 return false;
 467
 468         if (lane_count == 0 ||
 469             lane_count > intel_dp_max_lane_count(intel_dp))
 470                 return false;
 471
 472         return true;
 473 }
 474
 475 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 476                                                      int link_rate,
 477                                                      u8 lane_count)
 478 {
 479         const struct drm_display_mode *fixed_mode =
 480                 intel_dp->attached_connector->panel.fixed_mode;
 481         int mode_rate, max_rate;
 482
 483         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 484         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 485         if (mode_rate > max_rate)
 486                 return false;
 487
 488         return true;
 489 }
 490
 491 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 492                                             int link_rate, u8 lane_count)
 493 {
 494         int index;
 495
 496         index = intel_dp_rate_index(intel_dp->common_rates,
 497                                     intel_dp->num_common_rates,
 498                                     link_rate);
 499         if (index > 0) {
 500                 if (intel_dp_is_edp(intel_dp) &&
 501                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 502                                                               intel_dp->common_rates[index - 1],
 503                                                               lane_count)) {
 504                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 505                         return 0;
 506                 }
 507                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 508                 intel_dp->max_link_lane_count = lane_count;
 509         } else if (lane_count > 1) {
 510                 if (intel_dp_is_edp(intel_dp) &&
 511                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 512                                                               intel_dp_max_common_rate(intel_dp),
 513                                                               lane_count >> 1)) {
 514                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 515                         return 0;
 516                 }
 517                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 518                 intel_dp->max_link_lane_count = lane_count >> 1;
 519         } else {
 520                 DRM_ERROR("Link Training Unsuccessful\n");
 521                 return -1;
 522         }
 523
 524         return 0;
 525 }
 526
 527 static enum drm_mode_status
 528 intel_dp_mode_valid(struct drm_connector *connector,
 529                     struct drm_display_mode *mode)
 530 {
 531         struct intel_dp *intel_dp = intel_attached_dp(connector);
 532         struct intel_connector *intel_connector = to_intel_connector(connector);
 533         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 534         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 535         int target_clock = mode->clock;
 536         int max_rate, mode_rate, max_lanes, max_link_clock;
 537         int max_dotclk;
 538         u16 dsc_max_output_bpp = 0;
 539         u8 dsc_slice_count = 0;
 540
 541         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 542                 return MODE_NO_DBLESCAN;
 543
 544         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 545
 546         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 547                 if (mode->hdisplay > fixed_mode->hdisplay)
 548                         return MODE_PANEL;
 549
 550                 if (mode->vdisplay > fixed_mode->vdisplay)
 551                         return MODE_PANEL;
 552
 553                 target_clock = fixed_mode->clock;
 554         }
 555
 556         max_link_clock = intel_dp_max_link_rate(intel_dp);
 557         max_lanes = intel_dp_max_lane_count(intel_dp);
 558
 559         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 560         mode_rate = intel_dp_link_required(target_clock, 18);
 561
 562         /*
 563          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 564          * integer value since we support only integer values of bpp.
 565          */
 566         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 567             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 568                 if (intel_dp_is_edp(intel_dp)) {
 569                         dsc_max_output_bpp =
 570                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 571                         dsc_slice_count =
 572                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 573                                                                 true);
 574                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 575                         dsc_max_output_bpp =
 576                                 intel_dp_dsc_get_output_bpp(max_link_clock,
 577                                                             max_lanes,
 578                                                             target_clock,
 579                                                             mode->hdisplay) >> 4;
 580                         dsc_slice_count =
 581                                 intel_dp_dsc_get_slice_count(intel_dp,
 582                                                              target_clock,
 583                                                              mode->hdisplay);
 584                 }
 585         }
 586
 587         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
 588             target_clock > max_dotclk)
 589                 return MODE_CLOCK_HIGH;
 590
 591         if (mode->clock < 10000)
 592                 return MODE_CLOCK_LOW;
 593
 594         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 595                 return MODE_H_ILLEGAL;
 596
 597         return MODE_OK;
 598 }
 599
 600 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 601 {
 602         int i;
 603         u32 v = 0;
 604
 605         if (src_bytes > 4)
 606                 src_bytes = 4;
 607         for (i = 0; i < src_bytes; i++)
 608                 v |= ((u32)src[i]) << ((3 - i) * 8);
 609         return v;
 610 }
 611
 612 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 613 {
 614         int i;
 615         if (dst_bytes > 4)
 616                 dst_bytes = 4;
 617         for (i = 0; i < dst_bytes; i++)
 618                 dst[i] = src >> ((3-i) * 8);
 619 }
 620
 621 static void
 622 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 623 static void
 624 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 625                                               bool force_disable_vdd);
 626 static void
 627 intel_dp_pps_init(struct intel_dp *intel_dp);
 628
 629 static intel_wakeref_t
 630 pps_lock(struct intel_dp *intel_dp)
 631 {
 632         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 633         intel_wakeref_t wakeref;
 634
 635         /*
 636          * See intel_power_sequencer_reset() why we need
 637          * a power domain reference here.
 638          */
 639         wakeref = intel_display_power_get(dev_priv,
 640                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 641
 642         mutex_lock(&dev_priv->pps_mutex);
 643
 644         return wakeref;
 645 }
 646
 647 static intel_wakeref_t
 648 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 649 {
 650         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 651
 652         mutex_unlock(&dev_priv->pps_mutex);
 653         intel_display_power_put(dev_priv,
 654                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 655                                 wakeref);
 656         return 0;
 657 }
 658
 659 #define with_pps_lock(dp, wf) \
 660         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 661
 662 static void
 663 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 664 {
 665         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 666         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 667         enum pipe pipe = intel_dp->pps_pipe;
 668         bool pll_enabled, release_cl_override = false;
 669         enum dpio_phy phy = DPIO_PHY(pipe);
 670         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 671         u32 DP;
 672
 673         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 674                  "skipping pipe %c power sequencer kick due to port %c being active\n",
 675                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 676                 return;
 677
 678         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 679                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 680
 681         /* Preserve the BIOS-computed detected bit. This is
 682          * supposed to be read-only.
 683          */
 684         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 685         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 686         DP |= DP_PORT_WIDTH(1);
 687         DP |= DP_LINK_TRAIN_PAT_1;
 688
 689         if (IS_CHERRYVIEW(dev_priv))
 690                 DP |= DP_PIPE_SEL_CHV(pipe);
 691         else
 692                 DP |= DP_PIPE_SEL(pipe);
 693
 694         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 695
 696         /*
 697          * The DPLL for the pipe must be enabled for this to work.
 698          * So enable temporarily it if it's not already enabled.
 699          */
 700         if (!pll_enabled) {
 701                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 702                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 703
 704                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 705                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 706                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 707                                   pipe_name(pipe));
 708                         return;
 709                 }
 710         }
 711
 712         /*
 713          * Similar magic as in intel_dp_enable_port().
 714          * We _must_ do this port enable + disable trick
 715          * to make this power sequencer lock onto the port.
 716          * Otherwise even VDD force bit won't work.
 717          */
 718         I915_WRITE(intel_dp->output_reg, DP);
 719         POSTING_READ(intel_dp->output_reg);
 720
 721         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 722         POSTING_READ(intel_dp->output_reg);
 723
 724         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 725         POSTING_READ(intel_dp->output_reg);
 726
 727         if (!pll_enabled) {
 728                 vlv_force_pll_off(dev_priv, pipe);
 729
 730                 if (release_cl_override)
 731                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 732         }
 733 }
 734
 735 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 736 {
 737         struct intel_encoder *encoder;
 738         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 739
 740         /*
 741          * We don't have power sequencer currently.
 742          * Pick one that's not used by other ports.
 743          */
 744         for_each_intel_dp(&dev_priv->drm, encoder) {
 745                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 746
 747                 if (encoder->type == INTEL_OUTPUT_EDP) {
 748                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 749                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 750
 751                         if (intel_dp->pps_pipe != INVALID_PIPE)
 752                                 pipes &= ~(1 << intel_dp->pps_pipe);
 753                 } else {
 754                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 755
 756                         if (intel_dp->active_pipe != INVALID_PIPE)
 757                                 pipes &= ~(1 << intel_dp->active_pipe);
 758                 }
 759         }
 760
 761         if (pipes == 0)
 762                 return INVALID_PIPE;
 763
 764         return ffs(pipes) - 1;
 765 }
 766
 767 static enum pipe
 768 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 769 {
 770         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 771         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 772         enum pipe pipe;
 773
 774         lockdep_assert_held(&dev_priv->pps_mutex);
 775
 776         /* We should never land here with regular DP ports */
 777         WARN_ON(!intel_dp_is_edp(intel_dp));
 778
 779         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 780                 intel_dp->active_pipe != intel_dp->pps_pipe);
 781
 782         if (intel_dp->pps_pipe != INVALID_PIPE)
 783                 return intel_dp->pps_pipe;
 784
 785         pipe = vlv_find_free_pps(dev_priv);
 786
 787         /*
 788          * Didn't find one. This should not happen since there
 789          * are two power sequencers and up to two eDP ports.
 790          */
 791         if (WARN_ON(pipe == INVALID_PIPE))
 792                 pipe = PIPE_A;
 793
 794         vlv_steal_power_sequencer(dev_priv, pipe);
 795         intel_dp->pps_pipe = pipe;
 796
 797         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 798                       pipe_name(intel_dp->pps_pipe),
 799                       port_name(intel_dig_port->base.port));
 800
 801         /* init power sequencer on this pipe and port */
 802         intel_dp_init_panel_power_sequencer(intel_dp);
 803         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 804
 805         /*
 806          * Even vdd force doesn't work until we've made
 807          * the power sequencer lock in on the port.
 808          */
 809         vlv_power_sequencer_kick(intel_dp);
 810
 811         return intel_dp->pps_pipe;
 812 }
 813
 814 static int
 815 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 816 {
 817         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 818         int backlight_controller = dev_priv->vbt.backlight.controller;
 819
 820         lockdep_assert_held(&dev_priv->pps_mutex);
 821
 822         /* We should never land here with regular DP ports */
 823         WARN_ON(!intel_dp_is_edp(intel_dp));
 824
 825         if (!intel_dp->pps_reset)
 826                 return backlight_controller;
 827
 828         intel_dp->pps_reset = false;
 829
 830         /*
 831          * Only the HW needs to be reprogrammed, the SW state is fixed and
 832          * has been setup during connector init.
 833          */
 834         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 835
 836         return backlight_controller;
 837 }
 838
 839 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 840                                enum pipe pipe);
 841
 842 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 843                                enum pipe pipe)
 844 {
 845         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 846 }
 847
 848 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 849                                 enum pipe pipe)
 850 {
 851         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 852 }
 853
 854 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 855                          enum pipe pipe)
 856 {
 857         return true;
 858 }
 859
 860 static enum pipe
 861 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 862                      enum port port,
 863                      vlv_pipe_check pipe_check)
 864 {
 865         enum pipe pipe;
 866
 867         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 868                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 869                         PANEL_PORT_SELECT_MASK;
 870
 871                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 872                         continue;
 873
 874                 if (!pipe_check(dev_priv, pipe))
 875                         continue;
 876
 877                 return pipe;
 878         }
 879
 880         return INVALID_PIPE;
 881 }
 882
 883 static void
 884 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 885 {
 886         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 887         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 888         enum port port = intel_dig_port->base.port;
 889
 890         lockdep_assert_held(&dev_priv->pps_mutex);
 891
 892         /* try to find a pipe with this port selected */
 893         /* first pick one where the panel is on */
 894         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 895                                                   vlv_pipe_has_pp_on);
 896         /* didn't find one? pick one where vdd is on */
 897         if (intel_dp->pps_pipe == INVALID_PIPE)
 898                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 899                                                           vlv_pipe_has_vdd_on);
 900         /* didn't find one? pick one with just the correct port */
 901         if (intel_dp->pps_pipe == INVALID_PIPE)
 902                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 903                                                           vlv_pipe_any);
 904
 905         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 906         if (intel_dp->pps_pipe == INVALID_PIPE) {
 907                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 908                               port_name(port));
 909                 return;
 910         }
 911
 912         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 913                       port_name(port), pipe_name(intel_dp->pps_pipe));
 914
 915         intel_dp_init_panel_power_sequencer(intel_dp);
 916         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 917 }
 918
 919 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 920 {
 921         struct intel_encoder *encoder;
 922
 923         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 924                     !IS_GEN9_LP(dev_priv)))
 925                 return;
 926
 927         /*
 928          * We can't grab pps_mutex here due to deadlock with power_domain
 929          * mutex when power_domain functions are called while holding pps_mutex.
 930          * That also means that in order to use pps_pipe the code needs to
 931          * hold both a power domain reference and pps_mutex, and the power domain
 932          * reference get/put must be done while _not_ holding pps_mutex.
 933          * pps_{lock,unlock}() do these steps in the correct order, so one
 934          * should use them always.
 935          */
 936
 937         for_each_intel_dp(&dev_priv->drm, encoder) {
 938                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 939
 940                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 941
 942                 if (encoder->type != INTEL_OUTPUT_EDP)
 943                         continue;
 944
 945                 if (IS_GEN9_LP(dev_priv))
 946                         intel_dp->pps_reset = true;
 947                 else
 948                         intel_dp->pps_pipe = INVALID_PIPE;
 949         }
 950 }
 951
 952 struct pps_registers {
 953         i915_reg_t pp_ctrl;
 954         i915_reg_t pp_stat;
 955         i915_reg_t pp_on;
 956         i915_reg_t pp_off;
 957         i915_reg_t pp_div;
 958 };
 959
 960 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 961                                     struct pps_registers *regs)
 962 {
 963         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 964         int pps_idx = 0;
 965
 966         memset(regs, 0, sizeof(*regs));
 967
 968         if (IS_GEN9_LP(dev_priv))
 969                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 970         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 971                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 972
 973         regs->pp_ctrl = PP_CONTROL(pps_idx);
 974         regs->pp_stat = PP_STATUS(pps_idx);
 975         regs->pp_on = PP_ON_DELAYS(pps_idx);
 976         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 977
 978         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
 979         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
 980                 regs->pp_div = INVALID_MMIO_REG;
 981         else
 982                 regs->pp_div = PP_DIVISOR(pps_idx);
 983 }
 984
 985 static i915_reg_t
 986 _pp_ctrl_reg(struct intel_dp *intel_dp)
 987 {
 988         struct pps_registers regs;
 989
 990         intel_pps_get_registers(intel_dp, &regs);
 991
 992         return regs.pp_ctrl;
 993 }
 994
 995 static i915_reg_t
 996 _pp_stat_reg(struct intel_dp *intel_dp)
 997 {
 998         struct pps_registers regs;
 999
1000         intel_pps_get_registers(intel_dp, &regs);
1001
1002         return regs.pp_stat;
1003 }
1004
1005 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1006    This function only applicable when panel PM state is not to be tracked */
1007 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1008                               void *unused)
1009 {
1010         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1011                                                  edp_notifier);
1012         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1013         intel_wakeref_t wakeref;
1014
1015         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1016                 return 0;
1017
1018         with_pps_lock(intel_dp, wakeref) {
1019                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1020                         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1021                         i915_reg_t pp_ctrl_reg, pp_div_reg;
1022                         u32 pp_div;
1023
1024                         pp_ctrl_reg = PP_CONTROL(pipe);
1025                         pp_div_reg  = PP_DIVISOR(pipe);
1026                         pp_div = I915_READ(pp_div_reg);
1027                         pp_div &= PP_REFERENCE_DIVIDER_MASK;
1028
1029                         /* 0x1F write to PP_DIV_REG sets max cycle delay */
1030                         I915_WRITE(pp_div_reg, pp_div | 0x1F);
1031                         I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS);
1032                         msleep(intel_dp->panel_power_cycle_delay);
1033                 }
1034         }
1035
1036         return 0;
1037 }
1038
1039 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1040 {
1041         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1042
1043         lockdep_assert_held(&dev_priv->pps_mutex);
1044
1045         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1046             intel_dp->pps_pipe == INVALID_PIPE)
1047                 return false;
1048
1049         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1050 }
1051
1052 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1053 {
1054         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1055
1056         lockdep_assert_held(&dev_priv->pps_mutex);
1057
1058         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1059             intel_dp->pps_pipe == INVALID_PIPE)
1060                 return false;
1061
1062         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1063 }
1064
1065 static void
1066 intel_dp_check_edp(struct intel_dp *intel_dp)
1067 {
1068         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1069
1070         if (!intel_dp_is_edp(intel_dp))
1071                 return;
1072
1073         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1074                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1075                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1076                               I915_READ(_pp_stat_reg(intel_dp)),
1077                               I915_READ(_pp_ctrl_reg(intel_dp)));
1078         }
1079 }
1080
1081 static u32
1082 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1083 {
1084         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1085         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1086         u32 status;
1087         bool done;
1088
1089 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1090         done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
1091                                   msecs_to_jiffies_timeout(10));
1092
1093         /* just trace the final value */
1094         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1095
1096         if (!done)
1097                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1098 #undef C
1099
1100         return status;
1101 }
1102
1103 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1104 {
1105         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1106
1107         if (index)
1108                 return 0;
1109
1110         /*
1111          * The clock divider is based off the hrawclk, and would like to run at
1112          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1113          */
1114         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1115 }
1116
1117 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1118 {
1119         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1120         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1121
1122         if (index)
1123                 return 0;
1124
1125         /*
1126          * The clock divider is based off the cdclk or PCH rawclk, and would
1127          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1128          * divide by 2000 and use that
1129          */
1130         if (dig_port->aux_ch == AUX_CH_A)
1131                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1132         else
1133                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1134 }
1135
1136 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1137 {
1138         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1139         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1140
1141         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1142                 /* Workaround for non-ULT HSW */
1143                 switch (index) {
1144                 case 0: return 63;
1145                 case 1: return 72;
1146                 default: return 0;
1147                 }
1148         }
1149
1150         return ilk_get_aux_clock_divider(intel_dp, index);
1151 }
1152
1153 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1154 {
1155         /*
1156          * SKL doesn't need us to program the AUX clock divider (Hardware will
1157          * derive the clock from CDCLK automatically). We still implement the
1158          * get_aux_clock_divider vfunc to plug-in into the existing code.
1159          */
1160         return index ? 0 : 1;
1161 }
1162
1163 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1164                                 int send_bytes,
1165                                 u32 aux_clock_divider)
1166 {
1167         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1168         struct drm_i915_private *dev_priv =
1169                         to_i915(intel_dig_port->base.base.dev);
1170         u32 precharge, timeout;
1171
1172         if (IS_GEN(dev_priv, 6))
1173                 precharge = 3;
1174         else
1175                 precharge = 5;
1176
1177         if (IS_BROADWELL(dev_priv))
1178                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1179         else
1180                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1181
1182         return DP_AUX_CH_CTL_SEND_BUSY |
1183                DP_AUX_CH_CTL_DONE |
1184                DP_AUX_CH_CTL_INTERRUPT |
1185                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1186                timeout |
1187                DP_AUX_CH_CTL_RECEIVE_ERROR |
1188                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1189                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1190                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1191 }
1192
1193 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1194                                 int send_bytes,
1195                                 u32 unused)
1196 {
1197         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1198         u32 ret;
1199
1200         ret = DP_AUX_CH_CTL_SEND_BUSY |
1201               DP_AUX_CH_CTL_DONE |
1202               DP_AUX_CH_CTL_INTERRUPT |
1203               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1204               DP_AUX_CH_CTL_TIME_OUT_MAX |
1205               DP_AUX_CH_CTL_RECEIVE_ERROR |
1206               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1207               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1208               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1209
1210         if (intel_dig_port->tc_type == TC_PORT_TBT)
1211                 ret |= DP_AUX_CH_CTL_TBT_IO;
1212
1213         return ret;
1214 }
1215
1216 static int
1217 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1218                   const u8 *send, int send_bytes,
1219                   u8 *recv, int recv_size,
1220                   u32 aux_send_ctl_flags)
1221 {
1222         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1223         struct drm_i915_private *dev_priv =
1224                         to_i915(intel_dig_port->base.base.dev);
1225         i915_reg_t ch_ctl, ch_data[5];
1226         u32 aux_clock_divider;
1227         enum intel_display_power_domain aux_domain =
1228                 intel_aux_power_domain(intel_dig_port);
1229         intel_wakeref_t aux_wakeref;
1230         intel_wakeref_t pps_wakeref;
1231         int i, ret, recv_bytes;
1232         int try, clock = 0;
1233         u32 status;
1234         bool vdd;
1235
1236         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1237         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1238                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1239
1240         aux_wakeref = intel_display_power_get(dev_priv, aux_domain);
1241         pps_wakeref = pps_lock(intel_dp);
1242
1243         /*
1244          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1245          * In such cases we want to leave VDD enabled and it's up to upper layers
1246          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1247          * ourselves.
1248          */
1249         vdd = edp_panel_vdd_on(intel_dp);
1250
1251         /* dp aux is extremely sensitive to irq latency, hence request the
1252          * lowest possible wakeup latency and so prevent the cpu from going into
1253          * deep sleep states.
1254          */
1255         pm_qos_update_request(&dev_priv->pm_qos, 0);
1256
1257         intel_dp_check_edp(intel_dp);
1258
1259         /* Try to wait for any previous AUX channel activity */
1260         for (try = 0; try < 3; try++) {
1261                 status = I915_READ_NOTRACE(ch_ctl);
1262                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1263                         break;
1264                 msleep(1);
1265         }
1266         /* just trace the final value */
1267         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1268
1269         if (try == 3) {
1270                 static u32 last_status = -1;
1271                 const u32 status = I915_READ(ch_ctl);
1272
1273                 if (status != last_status) {
1274                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1275                              status);
1276                         last_status = status;
1277                 }
1278
1279                 ret = -EBUSY;
1280                 goto out;
1281         }
1282
1283         /* Only 5 data registers! */
1284         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1285                 ret = -E2BIG;
1286                 goto out;
1287         }
1288
1289         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1290                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1291                                                           send_bytes,
1292                                                           aux_clock_divider);
1293
1294                 send_ctl |= aux_send_ctl_flags;
1295
1296                 /* Must try at least 3 times according to DP spec */
1297                 for (try = 0; try < 5; try++) {
1298                         /* Load the send data into the aux channel data registers */
1299                         for (i = 0; i < send_bytes; i += 4)
1300                                 I915_WRITE(ch_data[i >> 2],
1301                                            intel_dp_pack_aux(send + i,
1302                                                              send_bytes - i));
1303
1304                         /* Send the command and wait for it to complete */
1305                         I915_WRITE(ch_ctl, send_ctl);
1306
1307                         status = intel_dp_aux_wait_done(intel_dp);
1308
1309                         /* Clear done status and any errors */
1310                         I915_WRITE(ch_ctl,
1311                                    status |
1312                                    DP_AUX_CH_CTL_DONE |
1313                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1314                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1315
1316                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1317                          *   400us delay required for errors and timeouts
1318                          *   Timeout errors from the HW already meet this
1319                          *   requirement so skip to next iteration
1320                          */
1321                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1322                                 continue;
1323
1324                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1325                                 usleep_range(400, 500);
1326                                 continue;
1327                         }
1328                         if (status & DP_AUX_CH_CTL_DONE)
1329                                 goto done;
1330                 }
1331         }
1332
1333         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1334                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1335                 ret = -EBUSY;
1336                 goto out;
1337         }
1338
1339 done:
1340         /* Check for timeout or receive error.
1341          * Timeouts occur when the sink is not connected
1342          */
1343         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1344                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1345                 ret = -EIO;
1346                 goto out;
1347         }
1348
1349         /* Timeouts occur when the device isn't connected, so they're
1350          * "normal" -- don't fill the kernel log with these */
1351         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1352                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1353                 ret = -ETIMEDOUT;
1354                 goto out;
1355         }
1356
1357         /* Unload any bytes sent back from the other side */
1358         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1359                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1360
1361         /*
1362          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1363          * We have no idea of what happened so we return -EBUSY so
1364          * drm layer takes care for the necessary retries.
1365          */
1366         if (recv_bytes == 0 || recv_bytes > 20) {
1367                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1368                               recv_bytes);
1369                 ret = -EBUSY;
1370                 goto out;
1371         }
1372
1373         if (recv_bytes > recv_size)
1374                 recv_bytes = recv_size;
1375
1376         for (i = 0; i < recv_bytes; i += 4)
1377                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1378                                     recv + i, recv_bytes - i);
1379
1380         ret = recv_bytes;
1381 out:
1382         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1383
1384         if (vdd)
1385                 edp_panel_vdd_off(intel_dp, false);
1386
1387         pps_unlock(intel_dp, pps_wakeref);
1388         intel_display_power_put_async(dev_priv, aux_domain, aux_wakeref);
1389
1390         return ret;
1391 }
1392
1393 #define BARE_ADDRESS_SIZE       3
1394 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1395
1396 static void
1397 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1398                     const struct drm_dp_aux_msg *msg)
1399 {
1400         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1401         txbuf[1] = (msg->address >> 8) & 0xff;
1402         txbuf[2] = msg->address & 0xff;
1403         txbuf[3] = msg->size - 1;
1404 }
1405
1406 static ssize_t
1407 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1408 {
1409         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1410         u8 txbuf[20], rxbuf[20];
1411         size_t txsize, rxsize;
1412         int ret;
1413
1414         intel_dp_aux_header(txbuf, msg);
1415
1416         switch (msg->request & ~DP_AUX_I2C_MOT) {
1417         case DP_AUX_NATIVE_WRITE:
1418         case DP_AUX_I2C_WRITE:
1419         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1420                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1421                 rxsize = 2; /* 0 or 1 data bytes */
1422
1423                 if (WARN_ON(txsize > 20))
1424                         return -E2BIG;
1425
1426                 WARN_ON(!msg->buffer != !msg->size);
1427
1428                 if (msg->buffer)
1429                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1430
1431                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1432                                         rxbuf, rxsize, 0);
1433                 if (ret > 0) {
1434                         msg->reply = rxbuf[0] >> 4;
1435
1436                         if (ret > 1) {
1437                                 /* Number of bytes written in a short write. */
1438                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1439                         } else {
1440                                 /* Return payload size. */
1441                                 ret = msg->size;
1442                         }
1443                 }
1444                 break;
1445
1446         case DP_AUX_NATIVE_READ:
1447         case DP_AUX_I2C_READ:
1448                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1449                 rxsize = msg->size + 1;
1450
1451                 if (WARN_ON(rxsize > 20))
1452                         return -E2BIG;
1453
1454                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1455                                         rxbuf, rxsize, 0);
1456                 if (ret > 0) {
1457                         msg->reply = rxbuf[0] >> 4;
1458                         /*
1459                          * Assume happy day, and copy the data. The caller is
1460                          * expected to check msg->reply before touching it.
1461                          *
1462                          * Return payload size.
1463                          */
1464                         ret--;
1465                         memcpy(msg->buffer, rxbuf + 1, ret);
1466                 }
1467                 break;
1468
1469         default:
1470                 ret = -EINVAL;
1471                 break;
1472         }
1473
1474         return ret;
1475 }
1476
1477
1478 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1479 {
1480         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1481         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1482         enum aux_ch aux_ch = dig_port->aux_ch;
1483
1484         switch (aux_ch) {
1485         case AUX_CH_B:
1486         case AUX_CH_C:
1487         case AUX_CH_D:
1488                 return DP_AUX_CH_CTL(aux_ch);
1489         default:
1490                 MISSING_CASE(aux_ch);
1491                 return DP_AUX_CH_CTL(AUX_CH_B);
1492         }
1493 }
1494
1495 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1496 {
1497         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1498         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1499         enum aux_ch aux_ch = dig_port->aux_ch;
1500
1501         switch (aux_ch) {
1502         case AUX_CH_B:
1503         case AUX_CH_C:
1504         case AUX_CH_D:
1505                 return DP_AUX_CH_DATA(aux_ch, index);
1506         default:
1507                 MISSING_CASE(aux_ch);
1508                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1509         }
1510 }
1511
1512 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1513 {
1514         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1515         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1516         enum aux_ch aux_ch = dig_port->aux_ch;
1517
1518         switch (aux_ch) {
1519         case AUX_CH_A:
1520                 return DP_AUX_CH_CTL(aux_ch);
1521         case AUX_CH_B:
1522         case AUX_CH_C:
1523         case AUX_CH_D:
1524                 return PCH_DP_AUX_CH_CTL(aux_ch);
1525         default:
1526                 MISSING_CASE(aux_ch);
1527                 return DP_AUX_CH_CTL(AUX_CH_A);
1528         }
1529 }
1530
1531 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1532 {
1533         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1534         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1535         enum aux_ch aux_ch = dig_port->aux_ch;
1536
1537         switch (aux_ch) {
1538         case AUX_CH_A:
1539                 return DP_AUX_CH_DATA(aux_ch, index);
1540         case AUX_CH_B:
1541         case AUX_CH_C:
1542         case AUX_CH_D:
1543                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1544         default:
1545                 MISSING_CASE(aux_ch);
1546                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1547         }
1548 }
1549
1550 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1551 {
1552         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1553         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1554         enum aux_ch aux_ch = dig_port->aux_ch;
1555
1556         switch (aux_ch) {
1557         case AUX_CH_A:
1558         case AUX_CH_B:
1559         case AUX_CH_C:
1560         case AUX_CH_D:
1561         case AUX_CH_E:
1562         case AUX_CH_F:
1563                 return DP_AUX_CH_CTL(aux_ch);
1564         default:
1565                 MISSING_CASE(aux_ch);
1566                 return DP_AUX_CH_CTL(AUX_CH_A);
1567         }
1568 }
1569
1570 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1571 {
1572         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1573         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1574         enum aux_ch aux_ch = dig_port->aux_ch;
1575
1576         switch (aux_ch) {
1577         case AUX_CH_A:
1578         case AUX_CH_B:
1579         case AUX_CH_C:
1580         case AUX_CH_D:
1581         case AUX_CH_E:
1582         case AUX_CH_F:
1583                 return DP_AUX_CH_DATA(aux_ch, index);
1584         default:
1585                 MISSING_CASE(aux_ch);
1586                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1587         }
1588 }
1589
1590 static void
1591 intel_dp_aux_fini(struct intel_dp *intel_dp)
1592 {
1593         kfree(intel_dp->aux.name);
1594 }
1595
1596 static void
1597 intel_dp_aux_init(struct intel_dp *intel_dp)
1598 {
1599         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1600         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1601         struct intel_encoder *encoder = &dig_port->base;
1602
1603         if (INTEL_GEN(dev_priv) >= 9) {
1604                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1605                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1606         } else if (HAS_PCH_SPLIT(dev_priv)) {
1607                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1608                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1609         } else {
1610                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1611                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1612         }
1613
1614         if (INTEL_GEN(dev_priv) >= 9)
1615                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1616         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1617                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1618         else if (HAS_PCH_SPLIT(dev_priv))
1619                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1620         else
1621                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1622
1623         if (INTEL_GEN(dev_priv) >= 9)
1624                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1625         else
1626                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1627
1628         drm_dp_aux_init(&intel_dp->aux);
1629
1630         /* Failure to allocate our preferred name is not critical */
1631         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1632                                        port_name(encoder->port));
1633         intel_dp->aux.transfer = intel_dp_aux_transfer;
1634 }
1635
1636 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1637 {
1638         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1639
1640         return max_rate >= 540000;
1641 }
1642
1643 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1644 {
1645         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1646
1647         return max_rate >= 810000;
1648 }
1649
1650 static void
1651 intel_dp_set_clock(struct intel_encoder *encoder,
1652                    struct intel_crtc_state *pipe_config)
1653 {
1654         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1655         const struct dp_link_dpll *divisor = NULL;
1656         int i, count = 0;
1657
1658         if (IS_G4X(dev_priv)) {
1659                 divisor = g4x_dpll;
1660                 count = ARRAY_SIZE(g4x_dpll);
1661         } else if (HAS_PCH_SPLIT(dev_priv)) {
1662                 divisor = pch_dpll;
1663                 count = ARRAY_SIZE(pch_dpll);
1664         } else if (IS_CHERRYVIEW(dev_priv)) {
1665                 divisor = chv_dpll;
1666                 count = ARRAY_SIZE(chv_dpll);
1667         } else if (IS_VALLEYVIEW(dev_priv)) {
1668                 divisor = vlv_dpll;
1669                 count = ARRAY_SIZE(vlv_dpll);
1670         }
1671
1672         if (divisor && count) {
1673                 for (i = 0; i < count; i++) {
1674                         if (pipe_config->port_clock == divisor[i].clock) {
1675                                 pipe_config->dpll = divisor[i].dpll;
1676                                 pipe_config->clock_set = true;
1677                                 break;
1678                         }
1679                 }
1680         }
1681 }
1682
1683 static void snprintf_int_array(char *str, size_t len,
1684                                const int *array, int nelem)
1685 {
1686         int i;
1687
1688         str[0] = '\0';
1689
1690         for (i = 0; i < nelem; i++) {
1691                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1692                 if (r >= len)
1693                         return;
1694                 str += r;
1695                 len -= r;
1696         }
1697 }
1698
1699 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1700 {
1701         char str[128]; /* FIXME: too big for stack? */
1702
1703         if ((drm_debug & DRM_UT_KMS) == 0)
1704                 return;
1705
1706         snprintf_int_array(str, sizeof(str),
1707                            intel_dp->source_rates, intel_dp->num_source_rates);
1708         DRM_DEBUG_KMS("source rates: %s\n", str);
1709
1710         snprintf_int_array(str, sizeof(str),
1711                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1712         DRM_DEBUG_KMS("sink rates: %s\n", str);
1713
1714         snprintf_int_array(str, sizeof(str),
1715                            intel_dp->common_rates, intel_dp->num_common_rates);
1716         DRM_DEBUG_KMS("common rates: %s\n", str);
1717 }
1718
1719 int
1720 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1721 {
1722         int len;
1723
1724         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1725         if (WARN_ON(len <= 0))
1726                 return 162000;
1727
1728         return intel_dp->common_rates[len - 1];
1729 }
1730
1731 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1732 {
1733         int i = intel_dp_rate_index(intel_dp->sink_rates,
1734                                     intel_dp->num_sink_rates, rate);
1735
1736         if (WARN_ON(i < 0))
1737                 i = 0;
1738
1739         return i;
1740 }
1741
1742 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1743                            u8 *link_bw, u8 *rate_select)
1744 {
1745         /* eDP 1.4 rate select method. */
1746         if (intel_dp->use_rate_select) {
1747                 *link_bw = 0;
1748                 *rate_select =
1749                         intel_dp_rate_select(intel_dp, port_clock);
1750         } else {
1751                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1752                 *rate_select = 0;
1753         }
1754 }
1755
1756 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1757                                          const struct intel_crtc_state *pipe_config)
1758 {
1759         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1760
1761         return INTEL_GEN(dev_priv) >= 11 &&
1762                 pipe_config->cpu_transcoder != TRANSCODER_A;
1763 }
1764
1765 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1766                                   const struct intel_crtc_state *pipe_config)
1767 {
1768         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1769                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1770 }
1771
1772 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1773                                          const struct intel_crtc_state *pipe_config)
1774 {
1775         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1776
1777         return INTEL_GEN(dev_priv) >= 10 &&
1778                 pipe_config->cpu_transcoder != TRANSCODER_A;
1779 }
1780
1781 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1782                                   const struct intel_crtc_state *pipe_config)
1783 {
1784         if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1785                 return false;
1786
1787         return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1788                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1789 }
1790
1791 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1792                                 struct intel_crtc_state *pipe_config)
1793 {
1794         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1795         struct intel_connector *intel_connector = intel_dp->attached_connector;
1796         int bpp, bpc;
1797
1798         bpp = pipe_config->pipe_bpp;
1799         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1800
1801         if (bpc > 0)
1802                 bpp = min(bpp, 3*bpc);
1803
1804         if (intel_dp_is_edp(intel_dp)) {
1805                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1806                 if (intel_connector->base.display_info.bpc == 0 &&
1807                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1808                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1809                                       dev_priv->vbt.edp.bpp);
1810                         bpp = dev_priv->vbt.edp.bpp;
1811                 }
1812         }
1813
1814         return bpp;
1815 }
1816
1817 /* Adjust link config limits based on compliance test requests. */
1818 void
1819 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1820                                   struct intel_crtc_state *pipe_config,
1821                                   struct link_config_limits *limits)
1822 {
1823         /* For DP Compliance we override the computed bpp for the pipe */
1824         if (intel_dp->compliance.test_data.bpc != 0) {
1825                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1826
1827                 limits->min_bpp = limits->max_bpp = bpp;
1828                 pipe_config->dither_force_disable = bpp == 6 * 3;
1829
1830                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1831         }
1832
1833         /* Use values requested by Compliance Test Request */
1834         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1835                 int index;
1836
1837                 /* Validate the compliance test data since max values
1838                  * might have changed due to link train fallback.
1839                  */
1840                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1841                                                intel_dp->compliance.test_lane_count)) {
1842                         index = intel_dp_rate_index(intel_dp->common_rates,
1843                                                     intel_dp->num_common_rates,
1844                                                     intel_dp->compliance.test_link_rate);
1845                         if (index >= 0)
1846                                 limits->min_clock = limits->max_clock = index;
1847                         limits->min_lane_count = limits->max_lane_count =
1848                                 intel_dp->compliance.test_lane_count;
1849                 }
1850         }
1851 }
1852
1853 /* Optimize link config in order: max bpp, min clock, min lanes */
1854 static int
1855 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1856                                   struct intel_crtc_state *pipe_config,
1857                                   const struct link_config_limits *limits)
1858 {
1859         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1860         int bpp, clock, lane_count;
1861         int mode_rate, link_clock, link_avail;
1862
1863         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1864                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1865                                                    bpp);
1866
1867                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1868                         for (lane_count = limits->min_lane_count;
1869                              lane_count <= limits->max_lane_count;
1870                              lane_count <<= 1) {
1871                                 link_clock = intel_dp->common_rates[clock];
1872                                 link_avail = intel_dp_max_data_rate(link_clock,
1873                                                                     lane_count);
1874
1875                                 if (mode_rate <= link_avail) {
1876                                         pipe_config->lane_count = lane_count;
1877                                         pipe_config->pipe_bpp = bpp;
1878                                         pipe_config->port_clock = link_clock;
1879
1880                                         return 0;
1881                                 }
1882                         }
1883                 }
1884         }
1885
1886         return -EINVAL;
1887 }
1888
1889 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1890 {
1891         int i, num_bpc;
1892         u8 dsc_bpc[3] = {0};
1893
1894         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1895                                                        dsc_bpc);
1896         for (i = 0; i < num_bpc; i++) {
1897                 if (dsc_max_bpc >= dsc_bpc[i])
1898                         return dsc_bpc[i] * 3;
1899         }
1900
1901         return 0;
1902 }
1903
1904 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1905                                        struct intel_crtc_state *pipe_config,
1906                                        struct drm_connector_state *conn_state,
1907                                        struct link_config_limits *limits)
1908 {
1909         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1910         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1911         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1912         u8 dsc_max_bpc;
1913         int pipe_bpp;
1914         int ret;
1915
1916         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1917                 intel_dp_supports_fec(intel_dp, pipe_config);
1918
1919         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1920                 return -EINVAL;
1921
1922         dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
1923                             conn_state->max_requested_bpc);
1924
1925         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1926         if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
1927                 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
1928                 return -EINVAL;
1929         }
1930
1931         /*
1932          * For now enable DSC for max bpp, max link rate, max lane count.
1933          * Optimize this later for the minimum possible link rate/lane count
1934          * with DSC enabled for the requested mode.
1935          */
1936         pipe_config->pipe_bpp = pipe_bpp;
1937         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1938         pipe_config->lane_count = limits->max_lane_count;
1939
1940         if (intel_dp_is_edp(intel_dp)) {
1941                 pipe_config->dsc_params.compressed_bpp =
1942                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1943                               pipe_config->pipe_bpp);
1944                 pipe_config->dsc_params.slice_count =
1945                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1946                                                         true);
1947         } else {
1948                 u16 dsc_max_output_bpp;
1949                 u8 dsc_dp_slice_count;
1950
1951                 dsc_max_output_bpp =
1952                         intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
1953                                                     pipe_config->lane_count,
1954                                                     adjusted_mode->crtc_clock,
1955                                                     adjusted_mode->crtc_hdisplay);
1956                 dsc_dp_slice_count =
1957                         intel_dp_dsc_get_slice_count(intel_dp,
1958                                                      adjusted_mode->crtc_clock,
1959                                                      adjusted_mode->crtc_hdisplay);
1960                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1961                         DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
1962                         return -EINVAL;
1963                 }
1964                 pipe_config->dsc_params.compressed_bpp = min_t(u16,
1965                                                                dsc_max_output_bpp >> 4,
1966                                                                pipe_config->pipe_bpp);
1967                 pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
1968         }
1969         /*
1970          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1971          * is greater than the maximum Cdclock and if slice count is even
1972          * then we need to use 2 VDSC instances.
1973          */
1974         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
1975                 if (pipe_config->dsc_params.slice_count > 1) {
1976                         pipe_config->dsc_params.dsc_split = true;
1977                 } else {
1978                         DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
1979                         return -EINVAL;
1980                 }
1981         }
1982
1983         ret = intel_dp_compute_dsc_params(intel_dp, pipe_config);
1984         if (ret < 0) {
1985                 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
1986                               "Compressed BPP = %d\n",
1987                               pipe_config->pipe_bpp,
1988                               pipe_config->dsc_params.compressed_bpp);
1989                 return ret;
1990         }
1991
1992         pipe_config->dsc_params.compression_enable = true;
1993         DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
1994                       "Compressed Bpp = %d Slice Count = %d\n",
1995                       pipe_config->pipe_bpp,
1996                       pipe_config->dsc_params.compressed_bpp,
1997                       pipe_config->dsc_params.slice_count);
1998
1999         return 0;
2000 }
2001
2002 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
2003 {
2004         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2005                 return 6 * 3;
2006         else
2007                 return 8 * 3;
2008 }
2009
2010 static int
2011 intel_dp_compute_link_config(struct intel_encoder *encoder,
2012                              struct intel_crtc_state *pipe_config,
2013                              struct drm_connector_state *conn_state)
2014 {
2015         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2016         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2017         struct link_config_limits limits;
2018         int common_len;
2019         int ret;
2020
2021         common_len = intel_dp_common_len_rate_limit(intel_dp,
2022                                                     intel_dp->max_link_rate);
2023
2024         /* No common link rates between source and sink */
2025         WARN_ON(common_len <= 0);
2026
2027         limits.min_clock = 0;
2028         limits.max_clock = common_len - 1;
2029
2030         limits.min_lane_count = 1;
2031         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2032
2033         limits.min_bpp = intel_dp_min_bpp(pipe_config);
2034         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2035
2036         if (intel_dp_is_edp(intel_dp)) {
2037                 /*
2038                  * Use the maximum clock and number of lanes the eDP panel
2039                  * advertizes being capable of. The panels are generally
2040                  * designed to support only a single clock and lane
2041                  * configuration, and typically these values correspond to the
2042                  * native resolution of the panel.
2043                  */
2044                 limits.min_lane_count = limits.max_lane_count;
2045                 limits.min_clock = limits.max_clock;
2046         }
2047
2048         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2049
2050         DRM_DEBUG_KMS("DP link computation with max lane count %i "
2051                       "max rate %d max bpp %d pixel clock %iKHz\n",
2052                       limits.max_lane_count,
2053                       intel_dp->common_rates[limits.max_clock],
2054                       limits.max_bpp, adjusted_mode->crtc_clock);
2055
2056         /*
2057          * Optimize for slow and wide. This is the place to add alternative
2058          * optimization policy.
2059          */
2060         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2061
2062         /* enable compression if the mode doesn't fit available BW */
2063         DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
2064         if (ret || intel_dp->force_dsc_en) {
2065                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2066                                                   conn_state, &limits);
2067                 if (ret < 0)
2068                         return ret;
2069         }
2070
2071         if (pipe_config->dsc_params.compression_enable) {
2072                 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2073                               pipe_config->lane_count, pipe_config->port_clock,
2074                               pipe_config->pipe_bpp,
2075                               pipe_config->dsc_params.compressed_bpp);
2076
2077                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2078                               intel_dp_link_required(adjusted_mode->crtc_clock,
2079                                                      pipe_config->dsc_params.compressed_bpp),
2080                               intel_dp_max_data_rate(pipe_config->port_clock,
2081                                                      pipe_config->lane_count));
2082         } else {
2083                 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2084                               pipe_config->lane_count, pipe_config->port_clock,
2085                               pipe_config->pipe_bpp);
2086
2087                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2088                               intel_dp_link_required(adjusted_mode->crtc_clock,
2089                                                      pipe_config->pipe_bpp),
2090                               intel_dp_max_data_rate(pipe_config->port_clock,
2091                                                      pipe_config->lane_count));
2092         }
2093         return 0;
2094 }
2095
2096 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2097                                   const struct drm_connector_state *conn_state)
2098 {
2099         const struct intel_digital_connector_state *intel_conn_state =
2100                 to_intel_digital_connector_state(conn_state);
2101         const struct drm_display_mode *adjusted_mode =
2102                 &crtc_state->base.adjusted_mode;
2103
2104         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2105                 /*
2106                  * See:
2107                  * CEA-861-E - 5.1 Default Encoding Parameters
2108                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2109                  */
2110                 return crtc_state->pipe_bpp != 18 &&
2111                         drm_default_rgb_quant_range(adjusted_mode) ==
2112                         HDMI_QUANTIZATION_RANGE_LIMITED;
2113         } else {
2114                 return intel_conn_state->broadcast_rgb ==
2115                         INTEL_BROADCAST_RGB_LIMITED;
2116         }
2117 }
2118
2119 int
2120 intel_dp_compute_config(struct intel_encoder *encoder,
2121                         struct intel_crtc_state *pipe_config,
2122                         struct drm_connector_state *conn_state)
2123 {
2124         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2125         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2126         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2127         struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2128         enum port port = encoder->port;
2129         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2130         struct intel_connector *intel_connector = intel_dp->attached_connector;
2131         struct intel_digital_connector_state *intel_conn_state =
2132                 to_intel_digital_connector_state(conn_state);
2133         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2134                                            DP_DPCD_QUIRK_CONSTANT_N);
2135         int ret, output_bpp;
2136
2137         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2138                 pipe_config->has_pch_encoder = true;
2139
2140         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2141         if (lspcon->active)
2142                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2143
2144         pipe_config->has_drrs = false;
2145         if (IS_G4X(dev_priv) || port == PORT_A)
2146                 pipe_config->has_audio = false;
2147         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2148                 pipe_config->has_audio = intel_dp->has_audio;
2149         else
2150                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2151
2152         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2153                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2154                                        adjusted_mode);
2155
2156                 if (INTEL_GEN(dev_priv) >= 9) {
2157                         ret = skl_update_scaler_crtc(pipe_config);
2158                         if (ret)
2159                                 return ret;
2160                 }
2161
2162                 if (HAS_GMCH(dev_priv))
2163                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2164                                                  conn_state->scaling_mode);
2165                 else
2166                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2167                                                 conn_state->scaling_mode);
2168         }
2169
2170         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2171                 return -EINVAL;
2172
2173         if (HAS_GMCH(dev_priv) &&
2174             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2175                 return -EINVAL;
2176
2177         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2178                 return -EINVAL;
2179
2180         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2181         if (ret < 0)
2182                 return ret;
2183
2184         pipe_config->limited_color_range =
2185                 intel_dp_limited_color_range(pipe_config, conn_state);
2186
2187         if (pipe_config->dsc_params.compression_enable)
2188                 output_bpp = pipe_config->dsc_params.compressed_bpp;
2189         else
2190                 output_bpp = pipe_config->pipe_bpp;
2191
2192         intel_link_compute_m_n(output_bpp,
2193                                pipe_config->lane_count,
2194                                adjusted_mode->crtc_clock,
2195                                pipe_config->port_clock,
2196                                &pipe_config->dp_m_n,
2197                                constant_n);
2198
2199         if (intel_connector->panel.downclock_mode != NULL &&
2200                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2201                         pipe_config->has_drrs = true;
2202                         intel_link_compute_m_n(output_bpp,
2203                                                pipe_config->lane_count,
2204                                                intel_connector->panel.downclock_mode->clock,
2205                                                pipe_config->port_clock,
2206                                                &pipe_config->dp_m2_n2,
2207                                                constant_n);
2208         }
2209
2210         if (!HAS_DDI(dev_priv))
2211                 intel_dp_set_clock(encoder, pipe_config);
2212
2213         intel_psr_compute_config(intel_dp, pipe_config);
2214
2215         return 0;
2216 }
2217
2218 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2219                               int link_rate, u8 lane_count,
2220                               bool link_mst)
2221 {
2222         intel_dp->link_trained = false;
2223         intel_dp->link_rate = link_rate;
2224         intel_dp->lane_count = lane_count;
2225         intel_dp->link_mst = link_mst;
2226 }
2227
2228 static void intel_dp_prepare(struct intel_encoder *encoder,
2229                              const struct intel_crtc_state *pipe_config)
2230 {
2231         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2232         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2233         enum port port = encoder->port;
2234         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2235         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2236
2237         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2238                                  pipe_config->lane_count,
2239                                  intel_crtc_has_type(pipe_config,
2240                                                      INTEL_OUTPUT_DP_MST));
2241
2242         /*
2243          * There are four kinds of DP registers:
2244          *
2245          *      IBX PCH
2246          *      SNB CPU
2247          *      IVB CPU
2248          *      CPT PCH
2249          *
2250          * IBX PCH and CPU are the same for almost everything,
2251          * except that the CPU DP PLL is configured in this
2252          * register
2253          *
2254          * CPT PCH is quite different, having many bits moved
2255          * to the TRANS_DP_CTL register instead. That
2256          * configuration happens (oddly) in ironlake_pch_enable
2257          */
2258
2259         /* Preserve the BIOS-computed detected bit. This is
2260          * supposed to be read-only.
2261          */
2262         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2263
2264         /* Handle DP bits in common between all three register formats */
2265         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2266         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2267
2268         /* Split out the IBX/CPU vs CPT settings */
2269
2270         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2271                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2272                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2273                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2274                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2275                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2276
2277                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2278                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2279
2280                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2281         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2282                 u32 trans_dp;
2283
2284                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2285
2286                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2287                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2288                         trans_dp |= TRANS_DP_ENH_FRAMING;
2289                 else
2290                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2291                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2292         } else {
2293                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2294                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2295
2296                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2297                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2298                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2299                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2300                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2301
2302                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2303                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2304
2305                 if (IS_CHERRYVIEW(dev_priv))
2306                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2307                 else
2308                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2309         }
2310 }
2311
2312 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2313 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2314
2315 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2316 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2317
2318 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2319 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2320
2321 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2322
2323 static void wait_panel_status(struct intel_dp *intel_dp,
2324                                        u32 mask,
2325                                        u32 value)
2326 {
2327         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2328         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2329
2330         lockdep_assert_held(&dev_priv->pps_mutex);
2331
2332         intel_pps_verify_state(intel_dp);
2333
2334         pp_stat_reg = _pp_stat_reg(intel_dp);
2335         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2336
2337         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2338                         mask, value,
2339                         I915_READ(pp_stat_reg),
2340                         I915_READ(pp_ctrl_reg));
2341
2342         if (intel_wait_for_register(&dev_priv->uncore,
2343                                     pp_stat_reg, mask, value,
2344                                     5000))
2345                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2346                                 I915_READ(pp_stat_reg),
2347                                 I915_READ(pp_ctrl_reg));
2348
2349         DRM_DEBUG_KMS("Wait complete\n");
2350 }
2351
2352 static void wait_panel_on(struct intel_dp *intel_dp)
2353 {
2354         DRM_DEBUG_KMS("Wait for panel power on\n");
2355         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2356 }
2357
2358 static void wait_panel_off(struct intel_dp *intel_dp)
2359 {
2360         DRM_DEBUG_KMS("Wait for panel power off time\n");
2361         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2362 }
2363
2364 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2365 {
2366         ktime_t panel_power_on_time;
2367         s64 panel_power_off_duration;
2368
2369         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2370
2371         /* take the difference of currrent time and panel power off time
2372          * and then make panel wait for t11_t12 if needed. */
2373         panel_power_on_time = ktime_get_boottime();
2374         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2375
2376         /* When we disable the VDD override bit last we have to do the manual
2377          * wait. */
2378         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2379                 wait_remaining_ms_from_jiffies(jiffies,
2380                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2381
2382         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2383 }
2384
2385 static void wait_backlight_on(struct intel_dp *intel_dp)
2386 {
2387         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2388                                        intel_dp->backlight_on_delay);
2389 }
2390
2391 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2392 {
2393         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2394                                        intel_dp->backlight_off_delay);
2395 }
2396
2397 /* Read the current pp_control value, unlocking the register if it
2398  * is locked
2399  */
2400
2401 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2402 {
2403         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2404         u32 control;
2405
2406         lockdep_assert_held(&dev_priv->pps_mutex);
2407
2408         control = I915_READ(_pp_ctrl_reg(intel_dp));
2409         if (WARN_ON(!HAS_DDI(dev_priv) &&
2410                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2411                 control &= ~PANEL_UNLOCK_MASK;
2412                 control |= PANEL_UNLOCK_REGS;
2413         }
2414         return control;
2415 }
2416
2417 /*
2418  * Must be paired with edp_panel_vdd_off().
2419  * Must hold pps_mutex around the whole on/off sequence.
2420  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2421  */
2422 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2423 {
2424         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2425         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2426         u32 pp;
2427         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2428         bool need_to_disable = !intel_dp->want_panel_vdd;
2429
2430         lockdep_assert_held(&dev_priv->pps_mutex);
2431
2432         if (!intel_dp_is_edp(intel_dp))
2433                 return false;
2434
2435         cancel_delayed_work(&intel_dp->panel_vdd_work);
2436         intel_dp->want_panel_vdd = true;
2437
2438         if (edp_have_panel_vdd(intel_dp))
2439                 return need_to_disable;
2440
2441         intel_display_power_get(dev_priv,
2442                                 intel_aux_power_domain(intel_dig_port));
2443
2444         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2445                       port_name(intel_dig_port->base.port));
2446
2447         if (!edp_have_panel_power(intel_dp))
2448                 wait_panel_power_cycle(intel_dp);
2449
2450         pp = ironlake_get_pp_control(intel_dp);
2451         pp |= EDP_FORCE_VDD;
2452
2453         pp_stat_reg = _pp_stat_reg(intel_dp);
2454         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2455
2456         I915_WRITE(pp_ctrl_reg, pp);
2457         POSTING_READ(pp_ctrl_reg);
2458         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2459                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2460         /*
2461          * If the panel wasn't on, delay before accessing aux channel
2462          */
2463         if (!edp_have_panel_power(intel_dp)) {
2464                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2465                               port_name(intel_dig_port->base.port));
2466                 msleep(intel_dp->panel_power_up_delay);
2467         }
2468
2469         return need_to_disable;
2470 }
2471
2472 /*
2473  * Must be paired with intel_edp_panel_vdd_off() or
2474  * intel_edp_panel_off().
2475  * Nested calls to these functions are not allowed since
2476  * we drop the lock. Caller must use some higher level
2477  * locking to prevent nested calls from other threads.
2478  */
2479 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2480 {
2481         intel_wakeref_t wakeref;
2482         bool vdd;
2483
2484         if (!intel_dp_is_edp(intel_dp))
2485                 return;
2486
2487         vdd = false;
2488         with_pps_lock(intel_dp, wakeref)
2489                 vdd = edp_panel_vdd_on(intel_dp);
2490         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2491              port_name(dp_to_dig_port(intel_dp)->base.port));
2492 }
2493
2494 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2495 {
2496         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2497         struct intel_digital_port *intel_dig_port =
2498                 dp_to_dig_port(intel_dp);
2499         u32 pp;
2500         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2501
2502         lockdep_assert_held(&dev_priv->pps_mutex);
2503
2504         WARN_ON(intel_dp->want_panel_vdd);
2505
2506         if (!edp_have_panel_vdd(intel_dp))
2507                 return;
2508
2509         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2510                       port_name(intel_dig_port->base.port));
2511
2512         pp = ironlake_get_pp_control(intel_dp);
2513         pp &= ~EDP_FORCE_VDD;
2514
2515         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2516         pp_stat_reg = _pp_stat_reg(intel_dp);
2517
2518         I915_WRITE(pp_ctrl_reg, pp);
2519         POSTING_READ(pp_ctrl_reg);
2520
2521         /* Make sure sequencer is idle before allowing subsequent activity */
2522         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2523         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2524
2525         if ((pp & PANEL_POWER_ON) == 0)
2526                 intel_dp->panel_power_off_time = ktime_get_boottime();
2527
2528         intel_display_power_put_unchecked(dev_priv,
2529                                           intel_aux_power_domain(intel_dig_port));
2530 }
2531
2532 static void edp_panel_vdd_work(struct work_struct *__work)
2533 {
2534         struct intel_dp *intel_dp =
2535                 container_of(to_delayed_work(__work),
2536                              struct intel_dp, panel_vdd_work);
2537         intel_wakeref_t wakeref;
2538
2539         with_pps_lock(intel_dp, wakeref) {
2540                 if (!intel_dp->want_panel_vdd)
2541                         edp_panel_vdd_off_sync(intel_dp);
2542         }
2543 }
2544
2545 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2546 {
2547         unsigned long delay;
2548
2549         /*
2550          * Queue the timer to fire a long time from now (relative to the power
2551          * down delay) to keep the panel power up across a sequence of
2552          * operations.
2553          */
2554         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2555         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2556 }
2557
2558 /*
2559  * Must be paired with edp_panel_vdd_on().
2560  * Must hold pps_mutex around the whole on/off sequence.
2561  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2562  */
2563 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2564 {
2565         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2566
2567         lockdep_assert_held(&dev_priv->pps_mutex);
2568
2569         if (!intel_dp_is_edp(intel_dp))
2570                 return;
2571
2572         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2573              port_name(dp_to_dig_port(intel_dp)->base.port));
2574
2575         intel_dp->want_panel_vdd = false;
2576
2577         if (sync)
2578                 edp_panel_vdd_off_sync(intel_dp);
2579         else
2580                 edp_panel_vdd_schedule_off(intel_dp);
2581 }
2582
2583 static void edp_panel_on(struct intel_dp *intel_dp)
2584 {
2585         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2586         u32 pp;
2587         i915_reg_t pp_ctrl_reg;
2588
2589         lockdep_assert_held(&dev_priv->pps_mutex);
2590
2591         if (!intel_dp_is_edp(intel_dp))
2592                 return;
2593
2594         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2595                       port_name(dp_to_dig_port(intel_dp)->base.port));
2596
2597         if (WARN(edp_have_panel_power(intel_dp),
2598                  "eDP port %c panel power already on\n",
2599                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2600                 return;
2601
2602         wait_panel_power_cycle(intel_dp);
2603
2604         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2605         pp = ironlake_get_pp_control(intel_dp);
2606         if (IS_GEN(dev_priv, 5)) {
2607                 /* ILK workaround: disable reset around power sequence */
2608                 pp &= ~PANEL_POWER_RESET;
2609                 I915_WRITE(pp_ctrl_reg, pp);
2610                 POSTING_READ(pp_ctrl_reg);
2611         }
2612
2613         pp |= PANEL_POWER_ON;
2614         if (!IS_GEN(dev_priv, 5))
2615                 pp |= PANEL_POWER_RESET;
2616
2617         I915_WRITE(pp_ctrl_reg, pp);
2618         POSTING_READ(pp_ctrl_reg);
2619
2620         wait_panel_on(intel_dp);
2621         intel_dp->last_power_on = jiffies;
2622
2623         if (IS_GEN(dev_priv, 5)) {
2624                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2625                 I915_WRITE(pp_ctrl_reg, pp);
2626                 POSTING_READ(pp_ctrl_reg);
2627         }
2628 }
2629
2630 void intel_edp_panel_on(struct intel_dp *intel_dp)
2631 {
2632         intel_wakeref_t wakeref;
2633
2634         if (!intel_dp_is_edp(intel_dp))
2635                 return;
2636
2637         with_pps_lock(intel_dp, wakeref)
2638                 edp_panel_on(intel_dp);
2639 }
2640
2641
2642 static void edp_panel_off(struct intel_dp *intel_dp)
2643 {
2644         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2645         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2646         u32 pp;
2647         i915_reg_t pp_ctrl_reg;
2648
2649         lockdep_assert_held(&dev_priv->pps_mutex);
2650
2651         if (!intel_dp_is_edp(intel_dp))
2652                 return;
2653
2654         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2655                       port_name(dig_port->base.port));
2656
2657         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2658              port_name(dig_port->base.port));
2659
2660         pp = ironlake_get_pp_control(intel_dp);
2661         /* We need to switch off panel power _and_ force vdd, for otherwise some
2662          * panels get very unhappy and cease to work. */
2663         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2664                 EDP_BLC_ENABLE);
2665
2666         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2667
2668         intel_dp->want_panel_vdd = false;
2669
2670         I915_WRITE(pp_ctrl_reg, pp);
2671         POSTING_READ(pp_ctrl_reg);
2672
2673         wait_panel_off(intel_dp);
2674         intel_dp->panel_power_off_time = ktime_get_boottime();
2675
2676         /* We got a reference when we enabled the VDD. */
2677         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
2678 }
2679
2680 void intel_edp_panel_off(struct intel_dp *intel_dp)
2681 {
2682         intel_wakeref_t wakeref;
2683
2684         if (!intel_dp_is_edp(intel_dp))
2685                 return;
2686
2687         with_pps_lock(intel_dp, wakeref)
2688                 edp_panel_off(intel_dp);
2689 }
2690
2691 /* Enable backlight in the panel power control. */
2692 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2693 {
2694         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2695         intel_wakeref_t wakeref;
2696
2697         /*
2698          * If we enable the backlight right away following a panel power
2699          * on, we may see slight flicker as the panel syncs with the eDP
2700          * link.  So delay a bit to make sure the image is solid before
2701          * allowing it to appear.
2702          */
2703         wait_backlight_on(intel_dp);
2704
2705         with_pps_lock(intel_dp, wakeref) {
2706                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2707                 u32 pp;
2708
2709                 pp = ironlake_get_pp_control(intel_dp);
2710                 pp |= EDP_BLC_ENABLE;
2711
2712                 I915_WRITE(pp_ctrl_reg, pp);
2713                 POSTING_READ(pp_ctrl_reg);
2714         }
2715 }
2716
2717 /* Enable backlight PWM and backlight PP control. */
2718 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2719                             const struct drm_connector_state *conn_state)
2720 {
2721         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2722
2723         if (!intel_dp_is_edp(intel_dp))
2724                 return;
2725
2726         DRM_DEBUG_KMS("\n");
2727
2728         intel_panel_enable_backlight(crtc_state, conn_state);
2729         _intel_edp_backlight_on(intel_dp);
2730 }
2731
2732 /* Disable backlight in the panel power control. */
2733 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2734 {
2735         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2736         intel_wakeref_t wakeref;
2737
2738         if (!intel_dp_is_edp(intel_dp))
2739                 return;
2740
2741         with_pps_lock(intel_dp, wakeref) {
2742                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2743                 u32 pp;
2744
2745                 pp = ironlake_get_pp_control(intel_dp);
2746                 pp &= ~EDP_BLC_ENABLE;
2747
2748                 I915_WRITE(pp_ctrl_reg, pp);
2749                 POSTING_READ(pp_ctrl_reg);
2750         }
2751
2752         intel_dp->last_backlight_off = jiffies;
2753         edp_wait_backlight_off(intel_dp);
2754 }
2755
2756 /* Disable backlight PP control and backlight PWM. */
2757 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2758 {
2759         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2760
2761         if (!intel_dp_is_edp(intel_dp))
2762                 return;
2763
2764         DRM_DEBUG_KMS("\n");
2765
2766         _intel_edp_backlight_off(intel_dp);
2767         intel_panel_disable_backlight(old_conn_state);
2768 }
2769
2770 /*
2771  * Hook for controlling the panel power control backlight through the bl_power
2772  * sysfs attribute. Take care to handle multiple calls.
2773  */
2774 static void intel_edp_backlight_power(struct intel_connector *connector,
2775                                       bool enable)
2776 {
2777         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2778         intel_wakeref_t wakeref;
2779         bool is_enabled;
2780
2781         is_enabled = false;
2782         with_pps_lock(intel_dp, wakeref)
2783                 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2784         if (is_enabled == enable)
2785                 return;
2786
2787         DRM_DEBUG_KMS("panel power control backlight %s\n",
2788                       enable ? "enable" : "disable");
2789
2790         if (enable)
2791                 _intel_edp_backlight_on(intel_dp);
2792         else
2793                 _intel_edp_backlight_off(intel_dp);
2794 }
2795
2796 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2797 {
2798         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2799         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2800         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2801
2802         I915_STATE_WARN(cur_state != state,
2803                         "DP port %c state assertion failure (expected %s, current %s)\n",
2804                         port_name(dig_port->base.port),
2805                         onoff(state), onoff(cur_state));
2806 }
2807 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2808
2809 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2810 {
2811         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2812
2813         I915_STATE_WARN(cur_state != state,
2814                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2815                         onoff(state), onoff(cur_state));
2816 }
2817 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2818 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2819
2820 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2821                                 const struct intel_crtc_state *pipe_config)
2822 {
2823         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2824         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2825
2826         assert_pipe_disabled(dev_priv, crtc->pipe);
2827         assert_dp_port_disabled(intel_dp);
2828         assert_edp_pll_disabled(dev_priv);
2829
2830         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2831                       pipe_config->port_clock);
2832
2833         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2834
2835         if (pipe_config->port_clock == 162000)
2836                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2837         else
2838                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2839
2840         I915_WRITE(DP_A, intel_dp->DP);
2841         POSTING_READ(DP_A);
2842         udelay(500);
2843
2844         /*
2845          * [DevILK] Work around required when enabling DP PLL
2846          * while a pipe is enabled going to FDI:
2847          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2848          * 2. Program DP PLL enable
2849          */
2850         if (IS_GEN(dev_priv, 5))
2851                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2852
2853         intel_dp->DP |= DP_PLL_ENABLE;
2854
2855         I915_WRITE(DP_A, intel_dp->DP);
2856         POSTING_READ(DP_A);
2857         udelay(200);
2858 }
2859
2860 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2861                                  const struct intel_crtc_state *old_crtc_state)
2862 {
2863         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2864         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2865
2866         assert_pipe_disabled(dev_priv, crtc->pipe);
2867         assert_dp_port_disabled(intel_dp);
2868         assert_edp_pll_enabled(dev_priv);
2869
2870         DRM_DEBUG_KMS("disabling eDP PLL\n");
2871
2872         intel_dp->DP &= ~DP_PLL_ENABLE;
2873
2874         I915_WRITE(DP_A, intel_dp->DP);
2875         POSTING_READ(DP_A);
2876         udelay(200);
2877 }
2878
2879 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2880 {
2881         /*
2882          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2883          * be capable of signalling downstream hpd with a long pulse.
2884          * Whether or not that means D3 is safe to use is not clear,
2885          * but let's assume so until proven otherwise.
2886          *
2887          * FIXME should really check all downstream ports...
2888          */
2889         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2890                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2891                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2892 }
2893
2894 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2895                                            const struct intel_crtc_state *crtc_state,
2896                                            bool enable)
2897 {
2898         int ret;
2899
2900         if (!crtc_state->dsc_params.compression_enable)
2901                 return;
2902
2903         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2904                                  enable ? DP_DECOMPRESSION_EN : 0);
2905         if (ret < 0)
2906                 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
2907                               enable ? "enable" : "disable");
2908 }
2909
2910 /* If the sink supports it, try to set the power state appropriately */
2911 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2912 {
2913         int ret, i;
2914
2915         /* Should have a valid DPCD by this point */
2916         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2917                 return;
2918
2919         if (mode != DRM_MODE_DPMS_ON) {
2920                 if (downstream_hpd_needs_d0(intel_dp))
2921                         return;
2922
2923                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2924                                          DP_SET_POWER_D3);
2925         } else {
2926                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2927
2928                 /*
2929                  * When turning on, we need to retry for 1ms to give the sink
2930                  * time to wake up.
2931                  */
2932                 for (i = 0; i < 3; i++) {
2933                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2934                                                  DP_SET_POWER_D0);
2935                         if (ret == 1)
2936                                 break;
2937                         msleep(1);
2938                 }
2939
2940                 if (ret == 1 && lspcon->active)
2941                         lspcon_wait_pcon_mode(lspcon);
2942         }
2943
2944         if (ret != 1)
2945                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2946                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2947 }
2948
2949 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2950                                  enum port port, enum pipe *pipe)
2951 {
2952         enum pipe p;
2953
2954         for_each_pipe(dev_priv, p) {
2955                 u32 val = I915_READ(TRANS_DP_CTL(p));
2956
2957                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2958                         *pipe = p;
2959                         return true;
2960                 }
2961         }
2962
2963         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2964
2965         /* must initialize pipe to something for the asserts */
2966         *pipe = PIPE_A;
2967
2968         return false;
2969 }
2970
2971 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2972                            i915_reg_t dp_reg, enum port port,
2973                            enum pipe *pipe)
2974 {
2975         bool ret;
2976         u32 val;
2977
2978         val = I915_READ(dp_reg);
2979
2980         ret = val & DP_PORT_EN;
2981
2982         /* asserts want to know the pipe even if the port is disabled */
2983         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2984                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2985         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2986                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2987         else if (IS_CHERRYVIEW(dev_priv))
2988                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2989         else
2990                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2991
2992         return ret;
2993 }
2994
2995 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2996                                   enum pipe *pipe)
2997 {
2998         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2999         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3000         intel_wakeref_t wakeref;
3001         bool ret;
3002
3003         wakeref = intel_display_power_get_if_enabled(dev_priv,
3004                                                      encoder->power_domain);
3005         if (!wakeref)
3006                 return false;
3007
3008         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3009                                     encoder->port, pipe);
3010
3011         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3012
3013         return ret;
3014 }
3015
3016 static void intel_dp_get_config(struct intel_encoder *encoder,
3017                                 struct intel_crtc_state *pipe_config)
3018 {
3019         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3020         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3021         u32 tmp, flags = 0;
3022         enum port port = encoder->port;
3023         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3024
3025         if (encoder->type == INTEL_OUTPUT_EDP)
3026                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3027         else
3028                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3029
3030         tmp = I915_READ(intel_dp->output_reg);
3031
3032         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3033
3034         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3035                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3036
3037                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3038                         flags |= DRM_MODE_FLAG_PHSYNC;
3039                 else
3040                         flags |= DRM_MODE_FLAG_NHSYNC;
3041
3042                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3043                         flags |= DRM_MODE_FLAG_PVSYNC;
3044                 else
3045                         flags |= DRM_MODE_FLAG_NVSYNC;
3046         } else {
3047                 if (tmp & DP_SYNC_HS_HIGH)
3048                         flags |= DRM_MODE_FLAG_PHSYNC;
3049                 else
3050                         flags |= DRM_MODE_FLAG_NHSYNC;
3051
3052                 if (tmp & DP_SYNC_VS_HIGH)
3053                         flags |= DRM_MODE_FLAG_PVSYNC;
3054                 else
3055                         flags |= DRM_MODE_FLAG_NVSYNC;
3056         }
3057
3058         pipe_config->base.adjusted_mode.flags |= flags;
3059
3060         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3061                 pipe_config->limited_color_range = true;
3062
3063         pipe_config->lane_count =
3064                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3065
3066         intel_dp_get_m_n(crtc, pipe_config);
3067
3068         if (port == PORT_A) {
3069                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3070                         pipe_config->port_clock = 162000;
3071                 else
3072                         pipe_config->port_clock = 270000;
3073         }
3074
3075         pipe_config->base.adjusted_mode.crtc_clock =
3076                 intel_dotclock_calculate(pipe_config->port_clock,
3077                                          &pipe_config->dp_m_n);
3078
3079         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3080             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3081                 /*
3082                  * This is a big fat ugly hack.
3083                  *
3084                  * Some machines in UEFI boot mode provide us a VBT that has 18
3085                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3086                  * unknown we fail to light up. Yet the same BIOS boots up with
3087                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3088                  * max, not what it tells us to use.
3089                  *
3090                  * Note: This will still be broken if the eDP panel is not lit
3091                  * up by the BIOS, and thus we can't get the mode at module
3092                  * load.
3093                  */
3094                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3095                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3096                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3097         }
3098 }
3099
3100 static void intel_disable_dp(struct intel_encoder *encoder,
3101                              const struct intel_crtc_state *old_crtc_state,
3102                              const struct drm_connector_state *old_conn_state)
3103 {
3104         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3105
3106         intel_dp->link_trained = false;
3107
3108         if (old_crtc_state->has_audio)
3109                 intel_audio_codec_disable(encoder,
3110                                           old_crtc_state, old_conn_state);
3111
3112         /* Make sure the panel is off before trying to change the mode. But also
3113          * ensure that we have vdd while we switch off the panel. */
3114         intel_edp_panel_vdd_on(intel_dp);
3115         intel_edp_backlight_off(old_conn_state);
3116         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3117         intel_edp_panel_off(intel_dp);
3118 }
3119
3120 static void g4x_disable_dp(struct intel_encoder *encoder,
3121                            const struct intel_crtc_state *old_crtc_state,
3122                            const struct drm_connector_state *old_conn_state)
3123 {
3124         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3125 }
3126
3127 static void vlv_disable_dp(struct intel_encoder *encoder,
3128                            const struct intel_crtc_state *old_crtc_state,
3129                            const struct drm_connector_state *old_conn_state)
3130 {
3131         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3132 }
3133
3134 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3135                                 const struct intel_crtc_state *old_crtc_state,
3136                                 const struct drm_connector_state *old_conn_state)
3137 {
3138         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3139         enum port port = encoder->port;
3140
3141         /*
3142          * Bspec does not list a specific disable sequence for g4x DP.
3143          * Follow the ilk+ sequence (disable pipe before the port) for
3144          * g4x DP as it does not suffer from underruns like the normal
3145          * g4x modeset sequence (disable pipe after the port).
3146          */
3147         intel_dp_link_down(encoder, old_crtc_state);
3148
3149         /* Only ilk+ has port A */
3150         if (port == PORT_A)
3151                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3152 }
3153
3154 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3155                                 const struct intel_crtc_state *old_crtc_state,
3156                                 const struct drm_connector_state *old_conn_state)
3157 {
3158         intel_dp_link_down(encoder, old_crtc_state);
3159 }
3160
3161 static void chv_post_disable_dp(struct intel_encoder *encoder,
3162                                 const struct intel_crtc_state *old_crtc_state,
3163                                 const struct drm_connector_state *old_conn_state)
3164 {
3165         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3166
3167         intel_dp_link_down(encoder, old_crtc_state);
3168
3169         vlv_dpio_get(dev_priv);
3170
3171         /* Assert data lane reset */
3172         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3173
3174         vlv_dpio_put(dev_priv);
3175 }
3176
3177 static void
3178 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3179                          u32 *DP,
3180                          u8 dp_train_pat)
3181 {
3182         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3183         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3184         enum port port = intel_dig_port->base.port;
3185         u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3186
3187         if (dp_train_pat & train_pat_mask)
3188                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3189                               dp_train_pat & train_pat_mask);
3190
3191         if (HAS_DDI(dev_priv)) {
3192                 u32 temp = I915_READ(DP_TP_CTL(port));
3193
3194                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3195                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3196                 else
3197                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3198
3199                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3200                 switch (dp_train_pat & train_pat_mask) {
3201                 case DP_TRAINING_PATTERN_DISABLE:
3202                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3203
3204                         break;
3205                 case DP_TRAINING_PATTERN_1:
3206                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3207                         break;
3208                 case DP_TRAINING_PATTERN_2:
3209                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3210                         break;
3211                 case DP_TRAINING_PATTERN_3:
3212                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3213                         break;
3214                 case DP_TRAINING_PATTERN_4:
3215                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3216                         break;
3217                 }
3218                 I915_WRITE(DP_TP_CTL(port), temp);
3219
3220         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3221                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3222                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3223
3224                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3225                 case DP_TRAINING_PATTERN_DISABLE:
3226                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3227                         break;
3228                 case DP_TRAINING_PATTERN_1:
3229                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3230                         break;
3231                 case DP_TRAINING_PATTERN_2:
3232                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3233                         break;
3234                 case DP_TRAINING_PATTERN_3:
3235                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3236                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3237                         break;
3238                 }
3239
3240         } else {
3241                 *DP &= ~DP_LINK_TRAIN_MASK;
3242
3243                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3244                 case DP_TRAINING_PATTERN_DISABLE:
3245                         *DP |= DP_LINK_TRAIN_OFF;
3246                         break;
3247                 case DP_TRAINING_PATTERN_1:
3248                         *DP |= DP_LINK_TRAIN_PAT_1;
3249                         break;
3250                 case DP_TRAINING_PATTERN_2:
3251                         *DP |= DP_LINK_TRAIN_PAT_2;
3252                         break;
3253                 case DP_TRAINING_PATTERN_3:
3254                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3255                         *DP |= DP_LINK_TRAIN_PAT_2;
3256                         break;
3257                 }
3258         }
3259 }
3260
3261 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3262                                  const struct intel_crtc_state *old_crtc_state)
3263 {
3264         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3265
3266         /* enable with pattern 1 (as per spec) */
3267
3268         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3269
3270         /*
3271          * Magic for VLV/CHV. We _must_ first set up the register
3272          * without actually enabling the port, and then do another
3273          * write to enable the port. Otherwise link training will
3274          * fail when the power sequencer is freshly used for this port.
3275          */
3276         intel_dp->DP |= DP_PORT_EN;
3277         if (old_crtc_state->has_audio)
3278                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3279
3280         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3281         POSTING_READ(intel_dp->output_reg);
3282 }
3283
3284 static void intel_enable_dp(struct intel_encoder *encoder,
3285                             const struct intel_crtc_state *pipe_config,
3286                             const struct drm_connector_state *conn_state)
3287 {
3288         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3289         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3290         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3291         u32 dp_reg = I915_READ(intel_dp->output_reg);
3292         enum pipe pipe = crtc->pipe;
3293         intel_wakeref_t wakeref;
3294
3295         if (WARN_ON(dp_reg & DP_PORT_EN))
3296                 return;
3297
3298         with_pps_lock(intel_dp, wakeref) {
3299                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3300                         vlv_init_panel_power_sequencer(encoder, pipe_config);
3301
3302                 intel_dp_enable_port(intel_dp, pipe_config);
3303
3304                 edp_panel_vdd_on(intel_dp);
3305                 edp_panel_on(intel_dp);
3306                 edp_panel_vdd_off(intel_dp, true);
3307         }
3308
3309         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3310                 unsigned int lane_mask = 0x0;
3311
3312                 if (IS_CHERRYVIEW(dev_priv))
3313                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3314
3315                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3316                                     lane_mask);
3317         }
3318
3319         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3320         intel_dp_start_link_train(intel_dp);
3321         intel_dp_stop_link_train(intel_dp);
3322
3323         if (pipe_config->has_audio) {
3324                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3325                                  pipe_name(pipe));
3326                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3327         }
3328 }
3329
3330 static void g4x_enable_dp(struct intel_encoder *encoder,
3331                           const struct intel_crtc_state *pipe_config,
3332                           const struct drm_connector_state *conn_state)
3333 {
3334         intel_enable_dp(encoder, pipe_config, conn_state);
3335         intel_edp_backlight_on(pipe_config, conn_state);
3336 }
3337
3338 static void vlv_enable_dp(struct intel_encoder *encoder,
3339                           const struct intel_crtc_state *pipe_config,
3340                           const struct drm_connector_state *conn_state)
3341 {
3342         intel_edp_backlight_on(pipe_config, conn_state);
3343 }
3344
3345 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3346                               const struct intel_crtc_state *pipe_config,
3347                               const struct drm_connector_state *conn_state)
3348 {
3349         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3350         enum port port = encoder->port;
3351
3352         intel_dp_prepare(encoder, pipe_config);
3353
3354         /* Only ilk+ has port A */
3355         if (port == PORT_A)
3356                 ironlake_edp_pll_on(intel_dp, pipe_config);
3357 }
3358
3359 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3360 {
3361         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3362         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3363         enum pipe pipe = intel_dp->pps_pipe;
3364         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3365
3366         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3367
3368         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3369                 return;
3370
3371         edp_panel_vdd_off_sync(intel_dp);
3372
3373         /*
3374          * VLV seems to get confused when multiple power sequencers
3375          * have the same port selected (even if only one has power/vdd
3376          * enabled). The failure manifests as vlv_wait_port_ready() failing
3377          * CHV on the other hand doesn't seem to mind having the same port
3378          * selected in multiple power sequencers, but let's clear the
3379          * port select always when logically disconnecting a power sequencer
3380          * from a port.
3381          */
3382         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3383                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3384         I915_WRITE(pp_on_reg, 0);
3385         POSTING_READ(pp_on_reg);
3386
3387         intel_dp->pps_pipe = INVALID_PIPE;
3388 }
3389
3390 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3391                                       enum pipe pipe)
3392 {
3393         struct intel_encoder *encoder;
3394
3395         lockdep_assert_held(&dev_priv->pps_mutex);
3396
3397         for_each_intel_dp(&dev_priv->drm, encoder) {
3398                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3399                 enum port port = encoder->port;
3400
3401                 WARN(intel_dp->active_pipe == pipe,
3402                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3403                      pipe_name(pipe), port_name(port));
3404
3405                 if (intel_dp->pps_pipe != pipe)
3406                         continue;
3407
3408                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3409                               pipe_name(pipe), port_name(port));
3410
3411                 /* make sure vdd is off before we steal it */
3412                 vlv_detach_power_sequencer(intel_dp);
3413         }
3414 }
3415
3416 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3417                                            const struct intel_crtc_state *crtc_state)
3418 {
3419         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3420         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3421         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3422
3423         lockdep_assert_held(&dev_priv->pps_mutex);
3424
3425         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3426
3427         if (intel_dp->pps_pipe != INVALID_PIPE &&
3428             intel_dp->pps_pipe != crtc->pipe) {
3429                 /*
3430                  * If another power sequencer was being used on this
3431                  * port previously make sure to turn off vdd there while
3432                  * we still have control of it.
3433                  */
3434                 vlv_detach_power_sequencer(intel_dp);
3435         }
3436
3437         /*
3438          * We may be stealing the power
3439          * sequencer from another port.
3440          */
3441         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3442
3443         intel_dp->active_pipe = crtc->pipe;
3444
3445         if (!intel_dp_is_edp(intel_dp))
3446                 return;
3447
3448         /* now it's all ours */
3449         intel_dp->pps_pipe = crtc->pipe;
3450
3451         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3452                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3453
3454         /* init power sequencer on this pipe and port */
3455         intel_dp_init_panel_power_sequencer(intel_dp);
3456         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3457 }
3458
3459 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3460                               const struct intel_crtc_state *pipe_config,
3461                               const struct drm_connector_state *conn_state)
3462 {
3463         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3464
3465         intel_enable_dp(encoder, pipe_config, conn_state);
3466 }
3467
3468 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3469                                   const struct intel_crtc_state *pipe_config,
3470                                   const struct drm_connector_state *conn_state)
3471 {
3472         intel_dp_prepare(encoder, pipe_config);
3473
3474         vlv_phy_pre_pll_enable(encoder, pipe_config);
3475 }
3476
3477 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3478                               const struct intel_crtc_state *pipe_config,
3479                               const struct drm_connector_state *conn_state)
3480 {
3481         chv_phy_pre_encoder_enable(encoder, pipe_config);
3482
3483         intel_enable_dp(encoder, pipe_config, conn_state);
3484
3485         /* Second common lane will stay alive on its own now */
3486         chv_phy_release_cl2_override(encoder);
3487 }
3488
3489 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3490                                   const struct intel_crtc_state *pipe_config,
3491                                   const struct drm_connector_state *conn_state)
3492 {
3493         intel_dp_prepare(encoder, pipe_config);
3494
3495         chv_phy_pre_pll_enable(encoder, pipe_config);
3496 }
3497
3498 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3499                                     const struct intel_crtc_state *old_crtc_state,
3500                                     const struct drm_connector_state *old_conn_state)
3501 {
3502         chv_phy_post_pll_disable(encoder, old_crtc_state);
3503 }
3504
3505 /*
3506  * Fetch AUX CH registers 0x202 - 0x207 which contain
3507  * link status information
3508  */
3509 bool
3510 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3511 {
3512         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3513                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3514 }
3515
3516 /* These are source-specific values. */
3517 u8
3518 intel_dp_voltage_max(struct intel_dp *intel_dp)
3519 {
3520         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3521         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3522         enum port port = encoder->port;
3523
3524         if (HAS_DDI(dev_priv))
3525                 return intel_ddi_dp_voltage_max(encoder);
3526         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3527                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3528         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3529                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3530         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3531                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3532         else
3533                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3534 }
3535
3536 u8
3537 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
3538 {
3539         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3540         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3541         enum port port = encoder->port;
3542
3543         if (HAS_DDI(dev_priv)) {
3544                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3545         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3546                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3547                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3548                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3549                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3550                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3551                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3552                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3553                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3554                 default:
3555                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3556                 }
3557         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3558                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3559                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3560                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3561                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3562                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3563                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3564                 default:
3565                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3566                 }
3567         } else {
3568                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3569                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3570                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3571                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3572                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3573                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3574                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3575                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3576                 default:
3577                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3578                 }
3579         }
3580 }
3581
3582 static u32 vlv_signal_levels(struct intel_dp *intel_dp)
3583 {
3584         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3585         unsigned long demph_reg_value, preemph_reg_value,
3586                 uniqtranscale_reg_value;
3587         u8 train_set = intel_dp->train_set[0];
3588
3589         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3590         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3591                 preemph_reg_value = 0x0004000;
3592                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3593                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3594                         demph_reg_value = 0x2B405555;
3595                         uniqtranscale_reg_value = 0x552AB83A;
3596                         break;
3597                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3598                         demph_reg_value = 0x2B404040;
3599                         uniqtranscale_reg_value = 0x5548B83A;
3600                         break;
3601                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3602                         demph_reg_value = 0x2B245555;
3603                         uniqtranscale_reg_value = 0x5560B83A;
3604                         break;
3605                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3606                         demph_reg_value = 0x2B405555;
3607                         uniqtranscale_reg_value = 0x5598DA3A;
3608                         break;
3609                 default:
3610                         return 0;
3611                 }
3612                 break;
3613         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3614                 preemph_reg_value = 0x0002000;
3615                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3616                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3617                         demph_reg_value = 0x2B404040;
3618                         uniqtranscale_reg_value = 0x5552B83A;
3619                         break;
3620                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3621                         demph_reg_value = 0x2B404848;
3622                         uniqtranscale_reg_value = 0x5580B83A;
3623                         break;
3624                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3625                         demph_reg_value = 0x2B404040;
3626                         uniqtranscale_reg_value = 0x55ADDA3A;
3627                         break;
3628                 default:
3629                         return 0;
3630                 }
3631                 break;
3632         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3633                 preemph_reg_value = 0x0000000;
3634                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3635                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3636                         demph_reg_value = 0x2B305555;
3637                         uniqtranscale_reg_value = 0x5570B83A;
3638                         break;
3639                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3640                         demph_reg_value = 0x2B2B4040;
3641                         uniqtranscale_reg_value = 0x55ADDA3A;
3642                         break;
3643                 default:
3644                         return 0;
3645                 }
3646                 break;
3647         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3648                 preemph_reg_value = 0x0006000;
3649                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3650                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3651                         demph_reg_value = 0x1B405555;
3652                         uniqtranscale_reg_value = 0x55ADDA3A;
3653                         break;
3654                 default:
3655                         return 0;
3656                 }
3657                 break;
3658         default:
3659                 return 0;
3660         }
3661
3662         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3663                                  uniqtranscale_reg_value, 0);
3664
3665         return 0;
3666 }
3667
3668 static u32 chv_signal_levels(struct intel_dp *intel_dp)
3669 {
3670         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3671         u32 deemph_reg_value, margin_reg_value;
3672         bool uniq_trans_scale = false;
3673         u8 train_set = intel_dp->train_set[0];
3674
3675         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3676         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3677                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3678                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3679                         deemph_reg_value = 128;
3680                         margin_reg_value = 52;
3681                         break;
3682                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3683                         deemph_reg_value = 128;
3684                         margin_reg_value = 77;
3685                         break;
3686                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3687                         deemph_reg_value = 128;
3688                         margin_reg_value = 102;
3689                         break;
3690                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3691                         deemph_reg_value = 128;
3692                         margin_reg_value = 154;
3693                         uniq_trans_scale = true;
3694                         break;
3695                 default:
3696                         return 0;
3697                 }
3698                 break;
3699         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3700                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3701                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3702                         deemph_reg_value = 85;
3703                         margin_reg_value = 78;
3704                         break;
3705                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3706                         deemph_reg_value = 85;
3707                         margin_reg_value = 116;
3708                         break;
3709                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3710                         deemph_reg_value = 85;
3711                         margin_reg_value = 154;
3712                         break;
3713                 default:
3714                         return 0;
3715                 }
3716                 break;
3717         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3718                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3719                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3720                         deemph_reg_value = 64;
3721                         margin_reg_value = 104;
3722                         break;
3723                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3724                         deemph_reg_value = 64;
3725                         margin_reg_value = 154;
3726                         break;
3727                 default:
3728                         return 0;
3729                 }
3730                 break;
3731         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3732                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3733                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3734                         deemph_reg_value = 43;
3735                         margin_reg_value = 154;
3736                         break;
3737                 default:
3738                         return 0;
3739                 }
3740                 break;
3741         default:
3742                 return 0;
3743         }
3744
3745         chv_set_phy_signal_level(encoder, deemph_reg_value,
3746                                  margin_reg_value, uniq_trans_scale);
3747
3748         return 0;
3749 }
3750
3751 static u32
3752 g4x_signal_levels(u8 train_set)
3753 {
3754         u32 signal_levels = 0;
3755
3756         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3757         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3758         default:
3759                 signal_levels |= DP_VOLTAGE_0_4;
3760                 break;
3761         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3762                 signal_levels |= DP_VOLTAGE_0_6;
3763                 break;
3764         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3765                 signal_levels |= DP_VOLTAGE_0_8;
3766                 break;
3767         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3768                 signal_levels |= DP_VOLTAGE_1_2;
3769                 break;
3770         }
3771         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3772         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3773         default:
3774                 signal_levels |= DP_PRE_EMPHASIS_0;
3775                 break;
3776         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3777                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3778                 break;
3779         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3780                 signal_levels |= DP_PRE_EMPHASIS_6;
3781                 break;
3782         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3783                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3784                 break;
3785         }
3786         return signal_levels;
3787 }
3788
3789 /* SNB CPU eDP voltage swing and pre-emphasis control */
3790 static u32
3791 snb_cpu_edp_signal_levels(u8 train_set)
3792 {
3793         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3794                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3795         switch (signal_levels) {
3796         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3797         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3798                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3799         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3800                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3801         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3802         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3803                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3804         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3805         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3806                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3807         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3808         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3809                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3810         default:
3811                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3812                               "0x%x\n", signal_levels);
3813                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3814         }
3815 }
3816
3817 /* IVB CPU eDP voltage swing and pre-emphasis control */
3818 static u32
3819 ivb_cpu_edp_signal_levels(u8 train_set)
3820 {
3821         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3822                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3823         switch (signal_levels) {
3824         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3825                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3826         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3827                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3828         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3829                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3830
3831         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3832                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3833         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3834                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3835
3836         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3837                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3838         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3839                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3840
3841         default:
3842                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3843                               "0x%x\n", signal_levels);
3844                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3845         }
3846 }
3847
3848 void
3849 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3850 {
3851         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3852         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3853         enum port port = intel_dig_port->base.port;
3854         u32 signal_levels, mask = 0;
3855         u8 train_set = intel_dp->train_set[0];
3856
3857         if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
3858                 signal_levels = bxt_signal_levels(intel_dp);
3859         } else if (HAS_DDI(dev_priv)) {
3860                 signal_levels = ddi_signal_levels(intel_dp);
3861                 mask = DDI_BUF_EMP_MASK;
3862         } else if (IS_CHERRYVIEW(dev_priv)) {
3863                 signal_levels = chv_signal_levels(intel_dp);
3864         } else if (IS_VALLEYVIEW(dev_priv)) {
3865                 signal_levels = vlv_signal_levels(intel_dp);
3866         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3867                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3868                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3869         } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
3870                 signal_levels = snb_cpu_edp_signal_levels(train_set);
3871                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3872         } else {
3873                 signal_levels = g4x_signal_levels(train_set);
3874                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3875         }
3876
3877         if (mask)
3878                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3879
3880         DRM_DEBUG_KMS("Using vswing level %d\n",
3881                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3882         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3883                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3884                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3885
3886         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3887
3888         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3889         POSTING_READ(intel_dp->output_reg);
3890 }
3891
3892 void
3893 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3894                                        u8 dp_train_pat)
3895 {
3896         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3897         struct drm_i915_private *dev_priv =
3898                 to_i915(intel_dig_port->base.base.dev);
3899
3900         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3901
3902         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3903         POSTING_READ(intel_dp->output_reg);
3904 }
3905
3906 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3907 {
3908         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3909         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3910         enum port port = intel_dig_port->base.port;
3911         u32 val;
3912
3913         if (!HAS_DDI(dev_priv))
3914                 return;
3915
3916         val = I915_READ(DP_TP_CTL(port));
3917         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3918         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3919         I915_WRITE(DP_TP_CTL(port), val);
3920
3921         /*
3922          * On PORT_A we can have only eDP in SST mode. There the only reason
3923          * we need to set idle transmission mode is to work around a HW issue
3924          * where we enable the pipe while not in idle link-training mode.
3925          * In this case there is requirement to wait for a minimum number of
3926          * idle patterns to be sent.
3927          */
3928         if (port == PORT_A)
3929                 return;
3930
3931         if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
3932                                     DP_TP_STATUS_IDLE_DONE,
3933                                     DP_TP_STATUS_IDLE_DONE,
3934                                     1))
3935                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3936 }
3937
3938 static void
3939 intel_dp_link_down(struct intel_encoder *encoder,
3940                    const struct intel_crtc_state *old_crtc_state)
3941 {
3942         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3943         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3944         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3945         enum port port = encoder->port;
3946         u32 DP = intel_dp->DP;
3947
3948         if (WARN_ON(HAS_DDI(dev_priv)))
3949                 return;
3950
3951         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3952                 return;
3953
3954         DRM_DEBUG_KMS("\n");
3955
3956         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3957             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3958                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3959                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3960         } else {
3961                 DP &= ~DP_LINK_TRAIN_MASK;
3962                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3963         }
3964         I915_WRITE(intel_dp->output_reg, DP);
3965         POSTING_READ(intel_dp->output_reg);
3966
3967         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3968         I915_WRITE(intel_dp->output_reg, DP);
3969         POSTING_READ(intel_dp->output_reg);
3970
3971         /*
3972          * HW workaround for IBX, we need to move the port
3973          * to transcoder A after disabling it to allow the
3974          * matching HDMI port to be enabled on transcoder A.
3975          */
3976         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3977                 /*
3978                  * We get CPU/PCH FIFO underruns on the other pipe when
3979                  * doing the workaround. Sweep them under the rug.
3980                  */
3981                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3982                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3983
3984                 /* always enable with pattern 1 (as per spec) */
3985                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
3986                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
3987                         DP_LINK_TRAIN_PAT_1;
3988                 I915_WRITE(intel_dp->output_reg, DP);
3989                 POSTING_READ(intel_dp->output_reg);
3990
3991                 DP &= ~DP_PORT_EN;
3992                 I915_WRITE(intel_dp->output_reg, DP);
3993                 POSTING_READ(intel_dp->output_reg);
3994
3995                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3996                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3997                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3998         }
3999
4000         msleep(intel_dp->panel_power_down_delay);
4001
4002         intel_dp->DP = DP;
4003
4004         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4005                 intel_wakeref_t wakeref;
4006
4007                 with_pps_lock(intel_dp, wakeref)
4008                         intel_dp->active_pipe = INVALID_PIPE;
4009         }
4010 }
4011
4012 static void
4013 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4014 {
4015         u8 dpcd_ext[6];
4016
4017         /*
4018          * Prior to DP1.3 the bit represented by
4019          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4020          * if it is set DP_DPCD_REV at 0000h could be at a value less than
4021          * the true capability of the panel. The only way to check is to
4022          * then compare 0000h and 2200h.
4023          */
4024         if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4025               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4026                 return;
4027
4028         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4029                              &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4030                 DRM_ERROR("DPCD failed read at extended capabilities\n");
4031                 return;
4032         }
4033
4034         if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4035                 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n");
4036                 return;
4037         }
4038
4039         if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4040                 return;
4041
4042         DRM_DEBUG_KMS("Base DPCD: %*ph\n",
4043                       (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4044
4045         memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4046 }
4047
4048 bool
4049 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4050 {
4051         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4052                              sizeof(intel_dp->dpcd)) < 0)
4053                 return false; /* aux transfer failed */
4054
4055         intel_dp_extended_receiver_capabilities(intel_dp);
4056
4057         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4058
4059         return intel_dp->dpcd[DP_DPCD_REV] != 0;
4060 }
4061
4062 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4063 {
4064         /*
4065          * Clear the cached register set to avoid using stale values
4066          * for the sinks that do not support DSC.
4067          */
4068         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4069
4070         /* Clear fec_capable to avoid using stale values */
4071         intel_dp->fec_capable = 0;
4072
4073         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4074         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4075             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4076                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4077                                      intel_dp->dsc_dpcd,
4078                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4079                         DRM_ERROR("Failed to read DPCD register 0x%x\n",
4080                                   DP_DSC_SUPPORT);
4081
4082                 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4083                               (int)sizeof(intel_dp->dsc_dpcd),
4084                               intel_dp->dsc_dpcd);
4085
4086                 /* FEC is supported only on DP 1.4 */
4087                 if (!intel_dp_is_edp(intel_dp) &&
4088                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4089                                       &intel_dp->fec_capable) < 0)
4090                         DRM_ERROR("Failed to read FEC DPCD register\n");
4091
4092                 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4093         }
4094 }
4095
4096 static bool
4097 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4098 {
4099         struct drm_i915_private *dev_priv =
4100                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4101
4102         /* this function is meant to be called only once */
4103         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4104
4105         if (!intel_dp_read_dpcd(intel_dp))
4106                 return false;
4107
4108         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4109                          drm_dp_is_branch(intel_dp->dpcd));
4110
4111         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4112                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4113                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4114
4115         /*
4116          * Read the eDP display control registers.
4117          *
4118          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4119          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4120          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4121          * method). The display control registers should read zero if they're
4122          * not supported anyway.
4123          */
4124         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4125                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4126                              sizeof(intel_dp->edp_dpcd))
4127                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
4128                               intel_dp->edp_dpcd);
4129
4130         /*
4131          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4132          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4133          */
4134         intel_psr_init_dpcd(intel_dp);
4135
4136         /* Read the eDP 1.4+ supported link rates. */
4137         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4138                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4139                 int i;
4140
4141                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4142                                 sink_rates, sizeof(sink_rates));
4143
4144                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4145                         int val = le16_to_cpu(sink_rates[i]);
4146
4147                         if (val == 0)
4148                                 break;
4149
4150                         /* Value read multiplied by 200kHz gives the per-lane
4151                          * link rate in kHz. The source rates are, however,
4152                          * stored in terms of LS_Clk kHz. The full conversion
4153                          * back to symbols is
4154                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4155                          */
4156                         intel_dp->sink_rates[i] = (val * 200) / 10;
4157                 }
4158                 intel_dp->num_sink_rates = i;
4159         }
4160
4161         /*
4162          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4163          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4164          */
4165         if (intel_dp->num_sink_rates)
4166                 intel_dp->use_rate_select = true;
4167         else
4168                 intel_dp_set_sink_rates(intel_dp);
4169
4170         intel_dp_set_common_rates(intel_dp);
4171
4172         /* Read the eDP DSC DPCD registers */
4173         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4174                 intel_dp_get_dsc_sink_cap(intel_dp);
4175
4176         return true;
4177 }
4178
4179
4180 static bool
4181 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4182 {
4183         if (!intel_dp_read_dpcd(intel_dp))
4184                 return false;
4185
4186         /* Don't clobber cached eDP rates. */
4187         if (!intel_dp_is_edp(intel_dp)) {
4188                 intel_dp_set_sink_rates(intel_dp);
4189                 intel_dp_set_common_rates(intel_dp);
4190         }
4191
4192         /*
4193          * Some eDP panels do not set a valid value for sink count, that is why
4194          * it don't care about read it here and in intel_edp_init_dpcd().
4195          */
4196         if (!intel_dp_is_edp(intel_dp)) {
4197                 u8 count;
4198                 ssize_t r;
4199
4200                 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4201                 if (r < 1)
4202                         return false;
4203
4204                 /*
4205                  * Sink count can change between short pulse hpd hence
4206                  * a member variable in intel_dp will track any changes
4207                  * between short pulse interrupts.
4208                  */
4209                 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4210
4211                 /*
4212                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4213                  * a dongle is present but no display. Unless we require to know
4214                  * if a dongle is present or not, we don't need to update
4215                  * downstream port information. So, an early return here saves
4216                  * time from performing other operations which are not required.
4217                  */
4218                 if (!intel_dp->sink_count)
4219                         return false;
4220         }
4221
4222         if (!drm_dp_is_branch(intel_dp->dpcd))
4223                 return true; /* native DP sink */
4224
4225         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4226                 return true; /* no per-port downstream info */
4227
4228         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4229                              intel_dp->downstream_ports,
4230                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4231                 return false; /* downstream port status fetch failed */
4232
4233         return true;
4234 }
4235
4236 static bool
4237 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4238 {
4239         u8 mstm_cap;
4240
4241         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4242                 return false;
4243
4244         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4245                 return false;
4246
4247         return mstm_cap & DP_MST_CAP;
4248 }
4249
4250 static bool
4251 intel_dp_can_mst(struct intel_dp *intel_dp)
4252 {
4253         return i915_modparams.enable_dp_mst &&
4254                 intel_dp->can_mst &&
4255                 intel_dp_sink_can_mst(intel_dp);
4256 }
4257
4258 static void
4259 intel_dp_configure_mst(struct intel_dp *intel_dp)
4260 {
4261         struct intel_encoder *encoder =
4262                 &dp_to_dig_port(intel_dp)->base;
4263         bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4264
4265         DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
4266                       port_name(encoder->port), yesno(intel_dp->can_mst),
4267                       yesno(sink_can_mst), yesno(i915_modparams.enable_dp_mst));
4268
4269         if (!intel_dp->can_mst)
4270                 return;
4271
4272         intel_dp->is_mst = sink_can_mst &&
4273                 i915_modparams.enable_dp_mst;
4274
4275         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4276                                         intel_dp->is_mst);
4277 }
4278
4279 static bool
4280 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4281 {
4282         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4283                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4284                 DP_DPRX_ESI_LEN;
4285 }
4286
4287 u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
4288                                 int mode_clock, int mode_hdisplay)
4289 {
4290         u16 bits_per_pixel, max_bpp_small_joiner_ram;
4291         int i;
4292
4293         /*
4294          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
4295          * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
4296          * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
4297          * for MST -> TimeSlotsPerMTP has to be calculated
4298          */
4299         bits_per_pixel = (link_clock * lane_count * 8 *
4300                           DP_DSC_FEC_OVERHEAD_FACTOR) /
4301                 mode_clock;
4302
4303         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
4304         max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
4305                 mode_hdisplay;
4306
4307         /*
4308          * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
4309          * check, output bpp from small joiner RAM check)
4310          */
4311         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
4312
4313         /* Error out if the max bpp is less than smallest allowed valid bpp */
4314         if (bits_per_pixel < valid_dsc_bpp[0]) {
4315                 DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
4316                 return 0;
4317         }
4318
4319         /* Find the nearest match in the array of known BPPs from VESA */
4320         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
4321                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
4322                         break;
4323         }
4324         bits_per_pixel = valid_dsc_bpp[i];
4325
4326         /*
4327          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
4328          * fractional part is 0
4329          */
4330         return bits_per_pixel << 4;
4331 }
4332
4333 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
4334                                 int mode_clock,
4335                                 int mode_hdisplay)
4336 {
4337         u8 min_slice_count, i;
4338         int max_slice_width;
4339
4340         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
4341                 min_slice_count = DIV_ROUND_UP(mode_clock,
4342                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
4343         else
4344                 min_slice_count = DIV_ROUND_UP(mode_clock,
4345                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
4346
4347         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
4348         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
4349                 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
4350                               max_slice_width);
4351                 return 0;
4352         }
4353         /* Also take into account max slice width */
4354         min_slice_count = min_t(u8, min_slice_count,
4355                                 DIV_ROUND_UP(mode_hdisplay,
4356                                              max_slice_width));
4357
4358         /* Find the closest match to the valid slice count values */
4359         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
4360                 if (valid_dsc_slicecount[i] >
4361                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
4362                                                     false))
4363                         break;
4364                 if (min_slice_count  <= valid_dsc_slicecount[i])
4365                         return valid_dsc_slicecount[i];
4366         }
4367
4368         DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
4369         return 0;
4370 }
4371
4372 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4373 {
4374         int status = 0;
4375         int test_link_rate;
4376         u8 test_lane_count, test_link_bw;
4377         /* (DP CTS 1.2)
4378          * 4.3.1.11
4379          */
4380         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4381         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4382                                    &test_lane_count);
4383
4384         if (status <= 0) {
4385                 DRM_DEBUG_KMS("Lane count read failed\n");
4386                 return DP_TEST_NAK;
4387         }
4388         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4389
4390         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4391                                    &test_link_bw);
4392         if (status <= 0) {
4393                 DRM_DEBUG_KMS("Link Rate read failed\n");
4394                 return DP_TEST_NAK;
4395         }
4396         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4397
4398         /* Validate the requested link rate and lane count */
4399         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4400                                         test_lane_count))
4401                 return DP_TEST_NAK;
4402
4403         intel_dp->compliance.test_lane_count = test_lane_count;
4404         intel_dp->compliance.test_link_rate = test_link_rate;
4405
4406         return DP_TEST_ACK;
4407 }
4408
4409 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4410 {
4411         u8 test_pattern;
4412         u8 test_misc;
4413         __be16 h_width, v_height;
4414         int status = 0;
4415
4416         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4417         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4418                                    &test_pattern);
4419         if (status <= 0) {
4420                 DRM_DEBUG_KMS("Test pattern read failed\n");
4421                 return DP_TEST_NAK;
4422         }
4423         if (test_pattern != DP_COLOR_RAMP)
4424                 return DP_TEST_NAK;
4425
4426         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4427                                   &h_width, 2);
4428         if (status <= 0) {
4429                 DRM_DEBUG_KMS("H Width read failed\n");
4430                 return DP_TEST_NAK;
4431         }
4432
4433         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4434                                   &v_height, 2);
4435         if (status <= 0) {
4436                 DRM_DEBUG_KMS("V Height read failed\n");
4437                 return DP_TEST_NAK;
4438         }
4439
4440         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4441                                    &test_misc);
4442         if (status <= 0) {
4443                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4444                 return DP_TEST_NAK;
4445         }
4446         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4447                 return DP_TEST_NAK;
4448         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4449                 return DP_TEST_NAK;
4450         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4451         case DP_TEST_BIT_DEPTH_6:
4452                 intel_dp->compliance.test_data.bpc = 6;
4453                 break;
4454         case DP_TEST_BIT_DEPTH_8:
4455                 intel_dp->compliance.test_data.bpc = 8;
4456                 break;
4457         default:
4458                 return DP_TEST_NAK;
4459         }
4460
4461         intel_dp->compliance.test_data.video_pattern = test_pattern;
4462         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4463         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4464         /* Set test active flag here so userspace doesn't interrupt things */
4465         intel_dp->compliance.test_active = 1;
4466
4467         return DP_TEST_ACK;
4468 }
4469
4470 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4471 {
4472         u8 test_result = DP_TEST_ACK;
4473         struct intel_connector *intel_connector = intel_dp->attached_connector;
4474         struct drm_connector *connector = &intel_connector->base;
4475
4476         if (intel_connector->detect_edid == NULL ||
4477             connector->edid_corrupt ||
4478             intel_dp->aux.i2c_defer_count > 6) {
4479                 /* Check EDID read for NACKs, DEFERs and corruption
4480                  * (DP CTS 1.2 Core r1.1)
4481                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4482                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4483                  *    4.2.2.6 : EDID corruption detected
4484                  * Use failsafe mode for all cases
4485                  */
4486                 if (intel_dp->aux.i2c_nack_count > 0 ||
4487                         intel_dp->aux.i2c_defer_count > 0)
4488                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4489                                       intel_dp->aux.i2c_nack_count,
4490                                       intel_dp->aux.i2c_defer_count);
4491                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4492         } else {
4493                 struct edid *block = intel_connector->detect_edid;
4494
4495                 /* We have to write the checksum
4496                  * of the last block read
4497                  */
4498                 block += intel_connector->detect_edid->extensions;
4499
4500                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4501                                        block->checksum) <= 0)
4502                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4503
4504                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4505                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4506         }
4507
4508         /* Set test active flag here so userspace doesn't interrupt things */
4509         intel_dp->compliance.test_active = 1;
4510
4511         return test_result;
4512 }
4513
4514 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4515 {
4516         u8 test_result = DP_TEST_NAK;
4517         return test_result;
4518 }
4519
4520 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4521 {
4522         u8 response = DP_TEST_NAK;
4523         u8 request = 0;
4524         int status;
4525
4526         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4527         if (status <= 0) {
4528                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4529                 goto update_status;
4530         }
4531
4532         switch (request) {
4533         case DP_TEST_LINK_TRAINING:
4534                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4535                 response = intel_dp_autotest_link_training(intel_dp);
4536                 break;
4537         case DP_TEST_LINK_VIDEO_PATTERN:
4538                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4539                 response = intel_dp_autotest_video_pattern(intel_dp);
4540                 break;
4541         case DP_TEST_LINK_EDID_READ:
4542                 DRM_DEBUG_KMS("EDID test requested\n");
4543                 response = intel_dp_autotest_edid(intel_dp);
4544                 break;
4545         case DP_TEST_LINK_PHY_TEST_PATTERN:
4546                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4547                 response = intel_dp_autotest_phy_pattern(intel_dp);
4548                 break;
4549         default:
4550                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4551                 break;
4552         }
4553
4554         if (response & DP_TEST_ACK)
4555                 intel_dp->compliance.test_type = request;
4556
4557 update_status:
4558         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4559         if (status <= 0)
4560                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4561 }
4562
4563 static int
4564 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4565 {
4566         bool bret;
4567
4568         if (intel_dp->is_mst) {
4569                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4570                 int ret = 0;
4571                 int retry;
4572                 bool handled;
4573
4574                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4575                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4576 go_again:
4577                 if (bret == true) {
4578
4579                         /* check link status - esi[10] = 0x200c */
4580                         if (intel_dp->active_mst_links > 0 &&
4581                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4582                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4583                                 intel_dp_start_link_train(intel_dp);
4584                                 intel_dp_stop_link_train(intel_dp);
4585                         }
4586
4587                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4588                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4589
4590                         if (handled) {
4591                                 for (retry = 0; retry < 3; retry++) {
4592                                         int wret;
4593                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4594                                                                  DP_SINK_COUNT_ESI+1,
4595                                                                  &esi[1], 3);
4596                                         if (wret == 3) {
4597                                                 break;
4598                                         }
4599                                 }
4600
4601                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4602                                 if (bret == true) {
4603                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4604                                         goto go_again;
4605                                 }
4606                         } else
4607                                 ret = 0;
4608
4609                         return ret;
4610                 } else {
4611                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4612                         intel_dp->is_mst = false;
4613                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4614                                                         intel_dp->is_mst);
4615                 }
4616         }
4617         return -EINVAL;
4618 }
4619
4620 static bool
4621 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4622 {
4623         u8 link_status[DP_LINK_STATUS_SIZE];
4624
4625         if (!intel_dp->link_trained)
4626                 return false;
4627
4628         /*
4629          * While PSR source HW is enabled, it will control main-link sending
4630          * frames, enabling and disabling it so trying to do a retrain will fail
4631          * as the link would or not be on or it could mix training patterns
4632          * and frame data at the same time causing retrain to fail.
4633          * Also when exiting PSR, HW will retrain the link anyways fixing
4634          * any link status error.
4635          */
4636         if (intel_psr_enabled(intel_dp))
4637                 return false;
4638
4639         if (!intel_dp_get_link_status(intel_dp, link_status))
4640                 return false;
4641
4642         /*
4643          * Validate the cached values of intel_dp->link_rate and
4644          * intel_dp->lane_count before attempting to retrain.
4645          */
4646         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4647                                         intel_dp->lane_count))
4648                 return false;
4649
4650         /* Retrain if Channel EQ or CR not ok */
4651         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4652 }
4653
4654 int intel_dp_retrain_link(struct intel_encoder *encoder,
4655                           struct drm_modeset_acquire_ctx *ctx)
4656 {
4657         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4658         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4659         struct intel_connector *connector = intel_dp->attached_connector;
4660         struct drm_connector_state *conn_state;
4661         struct intel_crtc_state *crtc_state;
4662         struct intel_crtc *crtc;
4663         int ret;
4664
4665         /* FIXME handle the MST connectors as well */
4666
4667         if (!connector || connector->base.status != connector_status_connected)
4668                 return 0;
4669
4670         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4671                                ctx);
4672         if (ret)
4673                 return ret;
4674
4675         conn_state = connector->base.state;
4676
4677         crtc = to_intel_crtc(conn_state->crtc);
4678         if (!crtc)
4679                 return 0;
4680
4681         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4682         if (ret)
4683                 return ret;
4684
4685         crtc_state = to_intel_crtc_state(crtc->base.state);
4686
4687         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4688
4689         if (!crtc_state->base.active)
4690                 return 0;
4691
4692         if (conn_state->commit &&
4693             !try_wait_for_completion(&conn_state->commit->hw_done))
4694                 return 0;
4695
4696         if (!intel_dp_needs_link_retrain(intel_dp))
4697                 return 0;
4698
4699         /* Suppress underruns caused by re-training */
4700         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4701         if (crtc_state->has_pch_encoder)
4702                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4703                                                       intel_crtc_pch_transcoder(crtc), false);
4704
4705         intel_dp_start_link_train(intel_dp);
4706         intel_dp_stop_link_train(intel_dp);
4707
4708         /* Keep underrun reporting disabled until things are stable */
4709         intel_wait_for_vblank(dev_priv, crtc->pipe);
4710
4711         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4712         if (crtc_state->has_pch_encoder)
4713                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4714                                                       intel_crtc_pch_transcoder(crtc), true);
4715
4716         return 0;
4717 }
4718
4719 /*
4720  * If display is now connected check links status,
4721  * there has been known issues of link loss triggering
4722  * long pulse.
4723  *
4724  * Some sinks (eg. ASUS PB287Q) seem to perform some
4725  * weird HPD ping pong during modesets. So we can apparently
4726  * end up with HPD going low during a modeset, and then
4727  * going back up soon after. And once that happens we must
4728  * retrain the link to get a picture. That's in case no
4729  * userspace component reacted to intermittent HPD dip.
4730  */
4731 static bool intel_dp_hotplug(struct intel_encoder *encoder,
4732                              struct intel_connector *connector)
4733 {
4734         struct drm_modeset_acquire_ctx ctx;
4735         bool changed;
4736         int ret;
4737
4738         changed = intel_encoder_hotplug(encoder, connector);
4739
4740         drm_modeset_acquire_init(&ctx, 0);
4741
4742         for (;;) {
4743                 ret = intel_dp_retrain_link(encoder, &ctx);
4744
4745                 if (ret == -EDEADLK) {
4746                         drm_modeset_backoff(&ctx);
4747                         continue;
4748                 }
4749
4750                 break;
4751         }
4752
4753         drm_modeset_drop_locks(&ctx);
4754         drm_modeset_acquire_fini(&ctx);
4755         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4756
4757         return changed;
4758 }
4759
4760 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
4761 {
4762         u8 val;
4763
4764         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4765                 return;
4766
4767         if (drm_dp_dpcd_readb(&intel_dp->aux,
4768                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4769                 return;
4770
4771         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4772
4773         if (val & DP_AUTOMATED_TEST_REQUEST)
4774                 intel_dp_handle_test_request(intel_dp);
4775
4776         if (val & DP_CP_IRQ)
4777                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4778
4779         if (val & DP_SINK_SPECIFIC_IRQ)
4780                 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
4781 }
4782
4783 /*
4784  * According to DP spec
4785  * 5.1.2:
4786  *  1. Read DPCD
4787  *  2. Configure link according to Receiver Capabilities
4788  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4789  *  4. Check link status on receipt of hot-plug interrupt
4790  *
4791  * intel_dp_short_pulse -  handles short pulse interrupts
4792  * when full detection is not required.
4793  * Returns %true if short pulse is handled and full detection
4794  * is NOT required and %false otherwise.
4795  */
4796 static bool
4797 intel_dp_short_pulse(struct intel_dp *intel_dp)
4798 {
4799         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4800         u8 old_sink_count = intel_dp->sink_count;
4801         bool ret;
4802
4803         /*
4804          * Clearing compliance test variables to allow capturing
4805          * of values for next automated test request.
4806          */
4807         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4808
4809         /*
4810          * Now read the DPCD to see if it's actually running
4811          * If the current value of sink count doesn't match with
4812          * the value that was stored earlier or dpcd read failed
4813          * we need to do full detection
4814          */
4815         ret = intel_dp_get_dpcd(intel_dp);
4816
4817         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4818                 /* No need to proceed if we are going to do full detect */
4819                 return false;
4820         }
4821
4822         intel_dp_check_service_irq(intel_dp);
4823
4824         /* Handle CEC interrupts, if any */
4825         drm_dp_cec_irq(&intel_dp->aux);
4826
4827         /* defer to the hotplug work for link retraining if needed */
4828         if (intel_dp_needs_link_retrain(intel_dp))
4829                 return false;
4830
4831         intel_psr_short_pulse(intel_dp);
4832
4833         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4834                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4835                 /* Send a Hotplug Uevent to userspace to start modeset */
4836                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4837         }
4838
4839         return true;
4840 }
4841
4842 /* XXX this is probably wrong for multiple downstream ports */
4843 static enum drm_connector_status
4844 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4845 {
4846         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4847         u8 *dpcd = intel_dp->dpcd;
4848         u8 type;
4849
4850         if (WARN_ON(intel_dp_is_edp(intel_dp)))
4851                 return connector_status_connected;
4852
4853         if (lspcon->active)
4854                 lspcon_resume(lspcon);
4855
4856         if (!intel_dp_get_dpcd(intel_dp))
4857                 return connector_status_disconnected;
4858
4859         /* if there's no downstream port, we're done */
4860         if (!drm_dp_is_branch(dpcd))
4861                 return connector_status_connected;
4862
4863         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4864         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4865             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4866
4867                 return intel_dp->sink_count ?
4868                 connector_status_connected : connector_status_disconnected;
4869         }
4870
4871         if (intel_dp_can_mst(intel_dp))
4872                 return connector_status_connected;
4873
4874         /* If no HPD, poke DDC gently */
4875         if (drm_probe_ddc(&intel_dp->aux.ddc))
4876                 return connector_status_connected;
4877
4878         /* Well we tried, say unknown for unreliable port types */
4879         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4880                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4881                 if (type == DP_DS_PORT_TYPE_VGA ||
4882                     type == DP_DS_PORT_TYPE_NON_EDID)
4883                         return connector_status_unknown;
4884         } else {
4885                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4886                         DP_DWN_STRM_PORT_TYPE_MASK;
4887                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4888                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4889                         return connector_status_unknown;
4890         }
4891
4892         /* Anything else is out of spec, warn and ignore */
4893         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4894         return connector_status_disconnected;
4895 }
4896
4897 static enum drm_connector_status
4898 edp_detect(struct intel_dp *intel_dp)
4899 {
4900         return connector_status_connected;
4901 }
4902
4903 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4904 {
4905         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4906         u32 bit;
4907
4908         switch (encoder->hpd_pin) {
4909         case HPD_PORT_B:
4910                 bit = SDE_PORTB_HOTPLUG;
4911                 break;
4912         case HPD_PORT_C:
4913                 bit = SDE_PORTC_HOTPLUG;
4914                 break;
4915         case HPD_PORT_D:
4916                 bit = SDE_PORTD_HOTPLUG;
4917                 break;
4918         default:
4919                 MISSING_CASE(encoder->hpd_pin);
4920                 return false;
4921         }
4922
4923         return I915_READ(SDEISR) & bit;
4924 }
4925
4926 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4927 {
4928         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4929         u32 bit;
4930
4931         switch (encoder->hpd_pin) {
4932         case HPD_PORT_B:
4933                 bit = SDE_PORTB_HOTPLUG_CPT;
4934                 break;
4935         case HPD_PORT_C:
4936                 bit = SDE_PORTC_HOTPLUG_CPT;
4937                 break;
4938         case HPD_PORT_D:
4939                 bit = SDE_PORTD_HOTPLUG_CPT;
4940                 break;
4941         default:
4942                 MISSING_CASE(encoder->hpd_pin);
4943                 return false;
4944         }
4945
4946         return I915_READ(SDEISR) & bit;
4947 }
4948
4949 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4950 {
4951         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4952         u32 bit;
4953
4954         switch (encoder->hpd_pin) {
4955         case HPD_PORT_A:
4956                 bit = SDE_PORTA_HOTPLUG_SPT;
4957                 break;
4958         case HPD_PORT_E:
4959                 bit = SDE_PORTE_HOTPLUG_SPT;
4960                 break;
4961         default:
4962                 return cpt_digital_port_connected(encoder);
4963         }
4964
4965         return I915_READ(SDEISR) & bit;
4966 }
4967
4968 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4969 {
4970         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4971         u32 bit;
4972
4973         switch (encoder->hpd_pin) {
4974         case HPD_PORT_B:
4975                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4976                 break;
4977         case HPD_PORT_C:
4978                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4979                 break;
4980         case HPD_PORT_D:
4981                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4982                 break;
4983         default:
4984                 MISSING_CASE(encoder->hpd_pin);
4985                 return false;
4986         }
4987
4988         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4989 }
4990
4991 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4992 {
4993         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4994         u32 bit;
4995
4996         switch (encoder->hpd_pin) {
4997         case HPD_PORT_B:
4998                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4999                 break;
5000         case HPD_PORT_C:
5001                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
5002                 break;
5003         case HPD_PORT_D:
5004                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
5005                 break;
5006         default:
5007                 MISSING_CASE(encoder->hpd_pin);
5008                 return false;
5009         }
5010
5011         return I915_READ(PORT_HOTPLUG_STAT) & bit;
5012 }
5013
5014 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
5015 {
5016         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5017
5018         if (encoder->hpd_pin == HPD_PORT_A)
5019                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5020         else
5021                 return ibx_digital_port_connected(encoder);
5022 }
5023
5024 static bool snb_digital_port_connected(struct intel_encoder *encoder)
5025 {
5026         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5027
5028         if (encoder->hpd_pin == HPD_PORT_A)
5029                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5030         else
5031                 return cpt_digital_port_connected(encoder);
5032 }
5033
5034 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
5035 {
5036         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5037
5038         if (encoder->hpd_pin == HPD_PORT_A)
5039                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
5040         else
5041                 return cpt_digital_port_connected(encoder);
5042 }
5043
5044 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5045 {
5046         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5047
5048         if (encoder->hpd_pin == HPD_PORT_A)
5049                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
5050         else
5051                 return cpt_digital_port_connected(encoder);
5052 }
5053
5054 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5055 {
5056         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5057         u32 bit;
5058
5059         switch (encoder->hpd_pin) {
5060         case HPD_PORT_A:
5061                 bit = BXT_DE_PORT_HP_DDIA;
5062                 break;
5063         case HPD_PORT_B:
5064                 bit = BXT_DE_PORT_HP_DDIB;
5065                 break;
5066         case HPD_PORT_C:
5067                 bit = BXT_DE_PORT_HP_DDIC;
5068                 break;
5069         default:
5070                 MISSING_CASE(encoder->hpd_pin);
5071                 return false;
5072         }
5073
5074         return I915_READ(GEN8_DE_PORT_ISR) & bit;
5075 }
5076
5077 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
5078                                      struct intel_digital_port *intel_dig_port)
5079 {
5080         enum port port = intel_dig_port->base.port;
5081
5082         return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
5083 }
5084
5085 static const char *tc_type_name(enum tc_port_type type)
5086 {
5087         static const char * const names[] = {
5088                 [TC_PORT_UNKNOWN] = "unknown",
5089                 [TC_PORT_LEGACY] = "legacy",
5090                 [TC_PORT_TYPEC] = "typec",
5091                 [TC_PORT_TBT] = "tbt",
5092         };
5093
5094         if (WARN_ON(type >= ARRAY_SIZE(names)))
5095                 type = TC_PORT_UNKNOWN;
5096
5097         return names[type];
5098 }
5099
5100 static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
5101                                     struct intel_digital_port *intel_dig_port,
5102                                     bool is_legacy, bool is_typec, bool is_tbt)
5103 {
5104         enum port port = intel_dig_port->base.port;
5105         enum tc_port_type old_type = intel_dig_port->tc_type;
5106
5107         WARN_ON(is_legacy + is_typec + is_tbt != 1);
5108
5109         if (is_legacy)
5110                 intel_dig_port->tc_type = TC_PORT_LEGACY;
5111         else if (is_typec)
5112                 intel_dig_port->tc_type = TC_PORT_TYPEC;
5113         else if (is_tbt)
5114                 intel_dig_port->tc_type = TC_PORT_TBT;
5115         else
5116                 return;
5117
5118         /* Types are not supposed to be changed at runtime. */
5119         WARN_ON(old_type != TC_PORT_UNKNOWN &&
5120                 old_type != intel_dig_port->tc_type);
5121
5122         if (old_type != intel_dig_port->tc_type)
5123                 DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
5124                               tc_type_name(intel_dig_port->tc_type));
5125 }
5126
5127 /*
5128  * This function implements the first part of the Connect Flow described by our
5129  * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
5130  * lanes, EDID, etc) is done as needed in the typical places.
5131  *
5132  * Unlike the other ports, type-C ports are not available to use as soon as we
5133  * get a hotplug. The type-C PHYs can be shared between multiple controllers:
5134  * display, USB, etc. As a result, handshaking through FIA is required around
5135  * connect and disconnect to cleanly transfer ownership with the controller and
5136  * set the type-C power state.
5137  *
5138  * We could opt to only do the connect flow when we actually try to use the AUX
5139  * channels or do a modeset, then immediately run the disconnect flow after
5140  * usage, but there are some implications on this for a dynamic environment:
5141  * things may go away or change behind our backs. So for now our driver is
5142  * always trying to acquire ownership of the controller as soon as it gets an
5143  * interrupt (or polls state and sees a port is connected) and only gives it
5144  * back when it sees a disconnect. Implementation of a more fine-grained model
5145  * will require a lot of coordination with user space and thorough testing for
5146  * the extra possible cases.
5147  */
5148 static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
5149                                struct intel_digital_port *dig_port)
5150 {
5151         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
5152         u32 val;
5153
5154         if (dig_port->tc_type != TC_PORT_LEGACY &&
5155             dig_port->tc_type != TC_PORT_TYPEC)
5156                 return true;
5157
5158         val = I915_READ(PORT_TX_DFLEXDPPMS);
5159         if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
5160                 DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
5161                 WARN_ON(dig_port->tc_legacy_port);
5162                 return false;
5163         }
5164
5165         /*
5166          * This function may be called many times in a row without an HPD event
5167          * in between, so try to avoid the write when we can.
5168          */
5169         val = I915_READ(PORT_TX_DFLEXDPCSSS);
5170         if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
5171                 val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
5172                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
5173         }
5174
5175         /*
5176          * Now we have to re-check the live state, in case the port recently
5177          * became disconnected. Not necessary for legacy mode.
5178          */
5179         if (dig_port->tc_type == TC_PORT_TYPEC &&
5180             !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
5181                 DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
5182                 icl_tc_phy_disconnect(dev_priv, dig_port);
5183                 return false;
5184         }
5185
5186         return true;
5187 }
5188
5189 /*
5190  * See the comment at the connect function. This implements the Disconnect
5191  * Flow.
5192  */
5193 void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
5194                            struct intel_digital_port *dig_port)
5195 {
5196         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
5197
5198         if (dig_port->tc_type == TC_PORT_UNKNOWN)
5199                 return;
5200
5201         /*
5202          * TBT disconnection flow is read the live status, what was done in
5203          * caller.
5204          */
5205         if (dig_port->tc_type == TC_PORT_TYPEC ||
5206             dig_port->tc_type == TC_PORT_LEGACY) {
5207                 u32 val;
5208
5209                 val = I915_READ(PORT_TX_DFLEXDPCSSS);
5210                 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
5211                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
5212         }
5213
5214         DRM_DEBUG_KMS("Port %c TC type %s disconnected\n",
5215                       port_name(dig_port->base.port),
5216                       tc_type_name(dig_port->tc_type));
5217
5218         dig_port->tc_type = TC_PORT_UNKNOWN;
5219 }
5220
5221 /*
5222  * The type-C ports are different because even when they are connected, they may
5223  * not be available/usable by the graphics driver: see the comment on
5224  * icl_tc_phy_connect(). So in our driver instead of adding the additional
5225  * concept of "usable" and make everything check for "connected and usable" we
5226  * define a port as "connected" when it is not only connected, but also when it
5227  * is usable by the rest of the driver. That maintains the old assumption that
5228  * connected ports are usable, and avoids exposing to the users objects they
5229  * can't really use.
5230  */
5231 static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
5232                                   struct intel_digital_port *intel_dig_port)
5233 {
5234         enum port port = intel_dig_port->base.port;
5235         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
5236         bool is_legacy, is_typec, is_tbt;
5237         u32 dpsp;
5238
5239         /*
5240          * Complain if we got a legacy port HPD, but VBT didn't mark the port as
5241          * legacy. Treat the port as legacy from now on.
5242          */
5243         if (!intel_dig_port->tc_legacy_port &&
5244             I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port)) {
5245                 DRM_ERROR("VBT incorrectly claims port %c is not TypeC legacy\n",
5246                           port_name(port));
5247                 intel_dig_port->tc_legacy_port = true;
5248         }
5249         is_legacy = intel_dig_port->tc_legacy_port;
5250
5251         /*
5252          * The spec says we shouldn't be using the ISR bits for detecting
5253          * between TC and TBT. We should use DFLEXDPSP.
5254          */
5255         dpsp = I915_READ(PORT_TX_DFLEXDPSP);
5256         is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
5257         is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
5258
5259         if (!is_legacy && !is_typec && !is_tbt) {
5260                 icl_tc_phy_disconnect(dev_priv, intel_dig_port);
5261
5262                 return false;
5263         }
5264
5265         icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
5266                                 is_tbt);
5267
5268         if (!icl_tc_phy_connect(dev_priv, intel_dig_port))
5269                 return false;
5270
5271         return true;
5272 }
5273
5274 static bool icl_digital_port_connected(struct intel_encoder *encoder)
5275 {
5276         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5277         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
5278
5279         if (intel_port_is_combophy(dev_priv, encoder->port))
5280                 return icl_combo_port_connected(dev_priv, dig_port);
5281         else if (intel_port_is_tc(dev_priv, encoder->port))
5282                 return icl_tc_port_connected(dev_priv, dig_port);
5283         else
5284                 MISSING_CASE(encoder->hpd_pin);
5285
5286         return false;
5287 }
5288
5289 /*
5290  * intel_digital_port_connected - is the specified port connected?
5291  * @encoder: intel_encoder
5292  *
5293  * In cases where there's a connector physically connected but it can't be used
5294  * by our hardware we also return false, since the rest of the driver should
5295  * pretty much treat the port as disconnected. This is relevant for type-C
5296  * (starting on ICL) where there's ownership involved.
5297  *
5298  * Return %true if port is connected, %false otherwise.
5299  */
5300 static bool __intel_digital_port_connected(struct intel_encoder *encoder)
5301 {
5302         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5303
5304         if (HAS_GMCH(dev_priv)) {
5305                 if (IS_GM45(dev_priv))
5306                         return gm45_digital_port_connected(encoder);
5307                 else
5308                         return g4x_digital_port_connected(encoder);
5309         }
5310
5311         if (INTEL_GEN(dev_priv) >= 11)
5312                 return icl_digital_port_connected(encoder);
5313         else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv))
5314                 return spt_digital_port_connected(encoder);
5315         else if (IS_GEN9_LP(dev_priv))
5316                 return bxt_digital_port_connected(encoder);
5317         else if (IS_GEN(dev_priv, 8))
5318                 return bdw_digital_port_connected(encoder);
5319         else if (IS_GEN(dev_priv, 7))
5320                 return ivb_digital_port_connected(encoder);
5321         else if (IS_GEN(dev_priv, 6))
5322                 return snb_digital_port_connected(encoder);
5323         else if (IS_GEN(dev_priv, 5))
5324                 return ilk_digital_port_connected(encoder);
5325
5326         MISSING_CASE(INTEL_GEN(dev_priv));
5327         return false;
5328 }
5329
5330 bool intel_digital_port_connected(struct intel_encoder *encoder)
5331 {
5332         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5333         bool is_connected = false;
5334         intel_wakeref_t wakeref;
5335
5336         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
5337                 is_connected = __intel_digital_port_connected(encoder);
5338
5339         return is_connected;
5340 }
5341
5342 static struct edid *
5343 intel_dp_get_edid(struct intel_dp *intel_dp)
5344 {
5345         struct intel_connector *intel_connector = intel_dp->attached_connector;
5346
5347         /* use cached edid if we have one */
5348         if (intel_connector->edid) {
5349                 /* invalid edid */
5350                 if (IS_ERR(intel_connector->edid))
5351                         return NULL;
5352
5353                 return drm_edid_duplicate(intel_connector->edid);
5354         } else
5355                 return drm_get_edid(&intel_connector->base,
5356                                     &intel_dp->aux.ddc);
5357 }
5358
5359 static void
5360 intel_dp_set_edid(struct intel_dp *intel_dp)
5361 {
5362         struct intel_connector *intel_connector = intel_dp->attached_connector;
5363         struct edid *edid;
5364
5365         intel_dp_unset_edid(intel_dp);
5366         edid = intel_dp_get_edid(intel_dp);
5367         intel_connector->detect_edid = edid;
5368
5369         intel_dp->has_audio = drm_detect_monitor_audio(edid);
5370         drm_dp_cec_set_edid(&intel_dp->aux, edid);
5371 }
5372
5373 static void
5374 intel_dp_unset_edid(struct intel_dp *intel_dp)
5375 {
5376         struct intel_connector *intel_connector = intel_dp->attached_connector;
5377
5378         drm_dp_cec_unset_edid(&intel_dp->aux);
5379         kfree(intel_connector->detect_edid);
5380         intel_connector->detect_edid = NULL;
5381
5382         intel_dp->has_audio = false;
5383 }
5384
5385 static int
5386 intel_dp_detect(struct drm_connector *connector,
5387                 struct drm_modeset_acquire_ctx *ctx,
5388                 bool force)
5389 {
5390         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5391         struct intel_dp *intel_dp = intel_attached_dp(connector);
5392         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5393         struct intel_encoder *encoder = &dig_port->base;
5394         enum drm_connector_status status;
5395
5396         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5397                       connector->base.id, connector->name);
5398         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5399
5400         /* Can't disconnect eDP */
5401         if (intel_dp_is_edp(intel_dp))
5402                 status = edp_detect(intel_dp);
5403         else if (intel_digital_port_connected(encoder))
5404                 status = intel_dp_detect_dpcd(intel_dp);
5405         else
5406                 status = connector_status_disconnected;
5407
5408         if (status == connector_status_disconnected) {
5409                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5410                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5411
5412                 if (intel_dp->is_mst) {
5413                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5414                                       intel_dp->is_mst,
5415                                       intel_dp->mst_mgr.mst_state);
5416                         intel_dp->is_mst = false;
5417                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5418                                                         intel_dp->is_mst);
5419                 }
5420
5421                 goto out;
5422         }
5423
5424         if (intel_dp->reset_link_params) {
5425                 /* Initial max link lane count */
5426                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5427
5428                 /* Initial max link rate */
5429                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5430
5431                 intel_dp->reset_link_params = false;
5432         }
5433
5434         intel_dp_print_rates(intel_dp);
5435
5436         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5437         if (INTEL_GEN(dev_priv) >= 11)
5438                 intel_dp_get_dsc_sink_cap(intel_dp);
5439
5440         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5441                          drm_dp_is_branch(intel_dp->dpcd));
5442
5443         intel_dp_configure_mst(intel_dp);
5444
5445         if (intel_dp->is_mst) {
5446                 /*
5447                  * If we are in MST mode then this connector
5448                  * won't appear connected or have anything
5449                  * with EDID on it
5450                  */
5451                 status = connector_status_disconnected;
5452                 goto out;
5453         }
5454
5455         /*
5456          * Some external monitors do not signal loss of link synchronization
5457          * with an IRQ_HPD, so force a link status check.
5458          */
5459         if (!intel_dp_is_edp(intel_dp)) {
5460                 int ret;
5461
5462                 ret = intel_dp_retrain_link(encoder, ctx);
5463                 if (ret)
5464                         return ret;
5465         }
5466
5467         /*
5468          * Clearing NACK and defer counts to get their exact values
5469          * while reading EDID which are required by Compliance tests
5470          * 4.2.2.4 and 4.2.2.5
5471          */
5472         intel_dp->aux.i2c_nack_count = 0;
5473         intel_dp->aux.i2c_defer_count = 0;
5474
5475         intel_dp_set_edid(intel_dp);
5476         if (intel_dp_is_edp(intel_dp) ||
5477             to_intel_connector(connector)->detect_edid)
5478                 status = connector_status_connected;
5479
5480         intel_dp_check_service_irq(intel_dp);
5481
5482 out:
5483         if (status != connector_status_connected && !intel_dp->is_mst)
5484                 intel_dp_unset_edid(intel_dp);
5485
5486         return status;
5487 }
5488
5489 static void
5490 intel_dp_force(struct drm_connector *connector)
5491 {
5492         struct intel_dp *intel_dp = intel_attached_dp(connector);
5493         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5494         struct intel_encoder *intel_encoder = &dig_port->base;
5495         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5496         enum intel_display_power_domain aux_domain =
5497                 intel_aux_power_domain(dig_port);
5498         intel_wakeref_t wakeref;
5499
5500         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5501                       connector->base.id, connector->name);
5502         intel_dp_unset_edid(intel_dp);
5503
5504         if (connector->status != connector_status_connected)
5505                 return;
5506
5507         wakeref = intel_display_power_get(dev_priv, aux_domain);
5508
5509         intel_dp_set_edid(intel_dp);
5510
5511         intel_display_power_put(dev_priv, aux_domain, wakeref);
5512 }
5513
5514 static int intel_dp_get_modes(struct drm_connector *connector)
5515 {
5516         struct intel_connector *intel_connector = to_intel_connector(connector);
5517         struct edid *edid;
5518
5519         edid = intel_connector->detect_edid;
5520         if (edid) {
5521                 int ret = intel_connector_update_modes(connector, edid);
5522                 if (ret)
5523                         return ret;
5524         }
5525
5526         /* if eDP has no EDID, fall back to fixed mode */
5527         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5528             intel_connector->panel.fixed_mode) {
5529                 struct drm_display_mode *mode;
5530
5531                 mode = drm_mode_duplicate(connector->dev,
5532                                           intel_connector->panel.fixed_mode);
5533                 if (mode) {
5534                         drm_mode_probed_add(connector, mode);
5535                         return 1;
5536                 }
5537         }
5538
5539         return 0;
5540 }
5541
5542 static int
5543 intel_dp_connector_register(struct drm_connector *connector)
5544 {
5545         struct intel_dp *intel_dp = intel_attached_dp(connector);
5546         struct drm_device *dev = connector->dev;
5547         int ret;
5548
5549         ret = intel_connector_register(connector);
5550         if (ret)
5551                 return ret;
5552
5553         i915_debugfs_connector_add(connector);
5554
5555         DRM_DEBUG_KMS("registering %s bus for %s\n",
5556                       intel_dp->aux.name, connector->kdev->kobj.name);
5557
5558         intel_dp->aux.dev = connector->kdev;
5559         ret = drm_dp_aux_register(&intel_dp->aux);
5560         if (!ret)
5561                 drm_dp_cec_register_connector(&intel_dp->aux,
5562                                               connector->name, dev->dev);
5563         return ret;
5564 }
5565
5566 static void
5567 intel_dp_connector_unregister(struct drm_connector *connector)
5568 {
5569         struct intel_dp *intel_dp = intel_attached_dp(connector);
5570
5571         drm_dp_cec_unregister_connector(&intel_dp->aux);
5572         drm_dp_aux_unregister(&intel_dp->aux);
5573         intel_connector_unregister(connector);
5574 }
5575
5576 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5577 {
5578         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5579         struct intel_dp *intel_dp = &intel_dig_port->dp;
5580
5581         intel_dp_mst_encoder_cleanup(intel_dig_port);
5582         if (intel_dp_is_edp(intel_dp)) {
5583                 intel_wakeref_t wakeref;
5584
5585                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5586                 /*
5587                  * vdd might still be enabled do to the delayed vdd off.
5588                  * Make sure vdd is actually turned off here.
5589                  */
5590                 with_pps_lock(intel_dp, wakeref)
5591                         edp_panel_vdd_off_sync(intel_dp);
5592
5593                 if (intel_dp->edp_notifier.notifier_call) {
5594                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5595                         intel_dp->edp_notifier.notifier_call = NULL;
5596                 }
5597         }
5598
5599         intel_dp_aux_fini(intel_dp);
5600 }
5601
5602 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5603 {
5604         intel_dp_encoder_flush_work(encoder);
5605
5606         drm_encoder_cleanup(encoder);
5607         kfree(enc_to_dig_port(encoder));
5608 }
5609
5610 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5611 {
5612         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5613         intel_wakeref_t wakeref;
5614
5615         if (!intel_dp_is_edp(intel_dp))
5616                 return;
5617
5618         /*
5619          * vdd might still be enabled do to the delayed vdd off.
5620          * Make sure vdd is actually turned off here.
5621          */
5622         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5623         with_pps_lock(intel_dp, wakeref)
5624                 edp_panel_vdd_off_sync(intel_dp);
5625 }
5626
5627 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
5628 {
5629         long ret;
5630
5631 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
5632         ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
5633                                                msecs_to_jiffies(timeout));
5634
5635         if (!ret)
5636                 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
5637 }
5638
5639 static
5640 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5641                                 u8 *an)
5642 {
5643         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5644         static const struct drm_dp_aux_msg msg = {
5645                 .request = DP_AUX_NATIVE_WRITE,
5646                 .address = DP_AUX_HDCP_AKSV,
5647                 .size = DRM_HDCP_KSV_LEN,
5648         };
5649         u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5650         ssize_t dpcd_ret;
5651         int ret;
5652
5653         /* Output An first, that's easy */
5654         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5655                                      an, DRM_HDCP_AN_LEN);
5656         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5657                 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5658                               dpcd_ret);
5659                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5660         }
5661
5662         /*
5663          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5664          * order to get it on the wire, we need to create the AUX header as if
5665          * we were writing the data, and then tickle the hardware to output the
5666          * data once the header is sent out.
5667          */
5668         intel_dp_aux_header(txbuf, &msg);
5669
5670         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5671                                 rxbuf, sizeof(rxbuf),
5672                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5673         if (ret < 0) {
5674                 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5675                 return ret;
5676         } else if (ret == 0) {
5677                 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5678                 return -EIO;
5679         }
5680
5681         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5682         if (reply != DP_AUX_NATIVE_REPLY_ACK) {
5683                 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
5684                               reply);
5685                 return -EIO;
5686         }
5687         return 0;
5688 }
5689
5690 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5691                                    u8 *bksv)
5692 {
5693         ssize_t ret;
5694         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5695                                DRM_HDCP_KSV_LEN);
5696         if (ret != DRM_HDCP_KSV_LEN) {
5697                 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5698                 return ret >= 0 ? -EIO : ret;
5699         }
5700         return 0;
5701 }
5702
5703 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5704                                       u8 *bstatus)
5705 {
5706         ssize_t ret;
5707         /*
5708          * For some reason the HDMI and DP HDCP specs call this register
5709          * definition by different names. In the HDMI spec, it's called BSTATUS,
5710          * but in DP it's called BINFO.
5711          */
5712         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5713                                bstatus, DRM_HDCP_BSTATUS_LEN);
5714         if (ret != DRM_HDCP_BSTATUS_LEN) {
5715                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5716                 return ret >= 0 ? -EIO : ret;
5717         }
5718         return 0;
5719 }
5720
5721 static
5722 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5723                              u8 *bcaps)
5724 {
5725         ssize_t ret;
5726
5727         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5728                                bcaps, 1);
5729         if (ret != 1) {
5730                 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
5731                 return ret >= 0 ? -EIO : ret;
5732         }
5733
5734         return 0;
5735 }
5736
5737 static
5738 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5739                                    bool *repeater_present)
5740 {
5741         ssize_t ret;
5742         u8 bcaps;
5743
5744         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5745         if (ret)
5746                 return ret;
5747
5748         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5749         return 0;
5750 }
5751
5752 static
5753 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5754                                 u8 *ri_prime)
5755 {
5756         ssize_t ret;
5757         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5758                                ri_prime, DRM_HDCP_RI_LEN);
5759         if (ret != DRM_HDCP_RI_LEN) {
5760                 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
5761                 return ret >= 0 ? -EIO : ret;
5762         }
5763         return 0;
5764 }
5765
5766 static
5767 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5768                                  bool *ksv_ready)
5769 {
5770         ssize_t ret;
5771         u8 bstatus;
5772         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5773                                &bstatus, 1);
5774         if (ret != 1) {
5775                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5776                 return ret >= 0 ? -EIO : ret;
5777         }
5778         *ksv_ready = bstatus & DP_BSTATUS_READY;
5779         return 0;
5780 }
5781
5782 static
5783 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5784                                 int num_downstream, u8 *ksv_fifo)
5785 {
5786         ssize_t ret;
5787         int i;
5788
5789         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5790         for (i = 0; i < num_downstream; i += 3) {
5791                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5792                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5793                                        DP_AUX_HDCP_KSV_FIFO,
5794                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5795                                        len);
5796                 if (ret != len) {
5797                         DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
5798                                       i, ret);
5799                         return ret >= 0 ? -EIO : ret;
5800                 }
5801         }
5802         return 0;
5803 }
5804
5805 static
5806 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5807                                     int i, u32 *part)
5808 {
5809         ssize_t ret;
5810
5811         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5812                 return -EINVAL;
5813
5814         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5815                                DP_AUX_HDCP_V_PRIME(i), part,
5816                                DRM_HDCP_V_PRIME_PART_LEN);
5817         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5818                 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5819                 return ret >= 0 ? -EIO : ret;
5820         }
5821         return 0;
5822 }
5823
5824 static
5825 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5826                                     bool enable)
5827 {
5828         /* Not used for single stream DisplayPort setups */
5829         return 0;
5830 }
5831
5832 static
5833 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5834 {
5835         ssize_t ret;
5836         u8 bstatus;
5837
5838         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5839                                &bstatus, 1);
5840         if (ret != 1) {
5841                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5842                 return false;
5843         }
5844
5845         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5846 }
5847
5848 static
5849 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5850                           bool *hdcp_capable)
5851 {
5852         ssize_t ret;
5853         u8 bcaps;
5854
5855         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5856         if (ret)
5857                 return ret;
5858
5859         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5860         return 0;
5861 }
5862
5863 struct hdcp2_dp_errata_stream_type {
5864         u8      msg_id;
5865         u8      stream_type;
5866 } __packed;
5867
5868 static struct hdcp2_dp_msg_data {
5869         u8 msg_id;
5870         u32 offset;
5871         bool msg_detectable;
5872         u32 timeout;
5873         u32 timeout2; /* Added for non_paired situation */
5874         } hdcp2_msg_data[] = {
5875                 {HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0},
5876                 {HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
5877                                 false, HDCP_2_2_CERT_TIMEOUT_MS, 0},
5878                 {HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
5879                                 false, 0, 0},
5880                 {HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
5881                                 false, 0, 0},
5882                 {HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
5883                                 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
5884                                 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS},
5885                 {HDCP_2_2_AKE_SEND_PAIRING_INFO,
5886                                 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
5887                                 HDCP_2_2_PAIRING_TIMEOUT_MS, 0},
5888                 {HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0},
5889                 {HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
5890                                 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0},
5891                 {HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
5892                                 0, 0},
5893                 {HDCP_2_2_REP_SEND_RECVID_LIST,
5894                                 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
5895                                 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0},
5896                 {HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
5897                                 0, 0},
5898                 {HDCP_2_2_REP_STREAM_MANAGE,
5899                                 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
5900                                 0, 0},
5901                 {HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
5902                                 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0},
5903 /* local define to shovel this through the write_2_2 interface */
5904 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE  50
5905                 {HDCP_2_2_ERRATA_DP_STREAM_TYPE,
5906                                 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
5907                                 0, 0},
5908                 };
5909
5910 static inline
5911 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
5912                                   u8 *rx_status)
5913 {
5914         ssize_t ret;
5915
5916         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5917                                DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
5918                                HDCP_2_2_DP_RXSTATUS_LEN);
5919         if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
5920                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5921                 return ret >= 0 ? -EIO : ret;
5922         }
5923
5924         return 0;
5925 }
5926
5927 static
5928 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
5929                                   u8 msg_id, bool *msg_ready)
5930 {
5931         u8 rx_status;
5932         int ret;
5933
5934         *msg_ready = false;
5935         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
5936         if (ret < 0)
5937                 return ret;
5938
5939         switch (msg_id) {
5940         case HDCP_2_2_AKE_SEND_HPRIME:
5941                 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
5942                         *msg_ready = true;
5943                 break;
5944         case HDCP_2_2_AKE_SEND_PAIRING_INFO:
5945                 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
5946                         *msg_ready = true;
5947                 break;
5948         case HDCP_2_2_REP_SEND_RECVID_LIST:
5949                 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
5950                         *msg_ready = true;
5951                 break;
5952         default:
5953                 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
5954                 return -EINVAL;
5955         }
5956
5957         return 0;
5958 }
5959
5960 static ssize_t
5961 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
5962                             struct hdcp2_dp_msg_data *hdcp2_msg_data)
5963 {
5964         struct intel_dp *dp = &intel_dig_port->dp;
5965         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
5966         u8 msg_id = hdcp2_msg_data->msg_id;
5967         int ret, timeout;
5968         bool msg_ready = false;
5969
5970         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
5971                 timeout = hdcp2_msg_data->timeout2;
5972         else
5973                 timeout = hdcp2_msg_data->timeout;
5974
5975         /*
5976          * There is no way to detect the CERT, LPRIME and STREAM_READY
5977          * availability. So Wait for timeout and read the msg.
5978          */
5979         if (!hdcp2_msg_data->msg_detectable) {
5980                 mdelay(timeout);
5981                 ret = 0;
5982         } else {
5983                 /*
5984                  * As we want to check the msg availability at timeout, Ignoring
5985                  * the timeout at wait for CP_IRQ.
5986                  */
5987                 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
5988                 ret = hdcp2_detect_msg_availability(intel_dig_port,
5989                                                     msg_id, &msg_ready);
5990                 if (!msg_ready)
5991                         ret = -ETIMEDOUT;
5992         }
5993
5994         if (ret)
5995                 DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n",
5996                               hdcp2_msg_data->msg_id, ret, timeout);
5997
5998         return ret;
5999 }
6000
6001 static struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
6002 {
6003         int i;
6004
6005         for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++)
6006                 if (hdcp2_msg_data[i].msg_id == msg_id)
6007                         return &hdcp2_msg_data[i];
6008
6009         return NULL;
6010 }
6011
6012 static
6013 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
6014                              void *buf, size_t size)
6015 {
6016         struct intel_dp *dp = &intel_dig_port->dp;
6017         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6018         unsigned int offset;
6019         u8 *byte = buf;
6020         ssize_t ret, bytes_to_write, len;
6021         struct hdcp2_dp_msg_data *hdcp2_msg_data;
6022
6023         hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
6024         if (!hdcp2_msg_data)
6025                 return -EINVAL;
6026
6027         offset = hdcp2_msg_data->offset;
6028
6029         /* No msg_id in DP HDCP2.2 msgs */
6030         bytes_to_write = size - 1;
6031         byte++;
6032
6033         hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
6034
6035         while (bytes_to_write) {
6036                 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
6037                                 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
6038
6039                 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
6040                                         offset, (void *)byte, len);
6041                 if (ret < 0)
6042                         return ret;
6043
6044                 bytes_to_write -= ret;
6045                 byte += ret;
6046                 offset += ret;
6047         }
6048
6049         return size;
6050 }
6051
6052 static
6053 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6054 {
6055         u8 rx_info[HDCP_2_2_RXINFO_LEN];
6056         u32 dev_cnt;
6057         ssize_t ret;
6058
6059         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6060                                DP_HDCP_2_2_REG_RXINFO_OFFSET,
6061                                (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6062         if (ret != HDCP_2_2_RXINFO_LEN)
6063                 return ret >= 0 ? -EIO : ret;
6064
6065         dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6066                    HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6067
6068         if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6069                 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
6070
6071         ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
6072                 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
6073                 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
6074
6075         return ret;
6076 }
6077
6078 static
6079 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
6080                             u8 msg_id, void *buf, size_t size)
6081 {
6082         unsigned int offset;
6083         u8 *byte = buf;
6084         ssize_t ret, bytes_to_recv, len;
6085         struct hdcp2_dp_msg_data *hdcp2_msg_data;
6086
6087         hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
6088         if (!hdcp2_msg_data)
6089                 return -EINVAL;
6090         offset = hdcp2_msg_data->offset;
6091
6092         ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
6093         if (ret < 0)
6094                 return ret;
6095
6096         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
6097                 ret = get_receiver_id_list_size(intel_dig_port);
6098                 if (ret < 0)
6099                         return ret;
6100
6101                 size = ret;
6102         }
6103         bytes_to_recv = size - 1;
6104
6105         /* DP adaptation msgs has no msg_id */
6106         byte++;
6107
6108         while (bytes_to_recv) {
6109                 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
6110                       DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
6111
6112                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
6113                                        (void *)byte, len);
6114                 if (ret < 0) {
6115                         DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret);
6116                         return ret;
6117                 }
6118
6119                 bytes_to_recv -= ret;
6120                 byte += ret;
6121                 offset += ret;
6122         }
6123         byte = buf;
6124         *byte = msg_id;
6125
6126         return size;
6127 }
6128
6129 static
6130 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
6131                                       bool is_repeater, u8 content_type)
6132 {
6133         struct hdcp2_dp_errata_stream_type stream_type_msg;
6134
6135         if (is_repeater)
6136                 return 0;
6137
6138         /*
6139          * Errata for DP: As Stream type is used for encryption, Receiver
6140          * should be communicated with stream type for the decryption of the
6141          * content.
6142          * Repeater will be communicated with stream type as a part of it's
6143          * auth later in time.
6144          */
6145         stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
6146         stream_type_msg.stream_type = content_type;
6147
6148         return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
6149                                         sizeof(stream_type_msg));
6150 }
6151
6152 static
6153 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
6154 {
6155         u8 rx_status;
6156         int ret;
6157
6158         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6159         if (ret)
6160                 return ret;
6161
6162         if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
6163                 ret = HDCP_REAUTH_REQUEST;
6164         else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
6165                 ret = HDCP_LINK_INTEGRITY_FAILURE;
6166         else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6167                 ret = HDCP_TOPOLOGY_CHANGE;
6168
6169         return ret;
6170 }
6171
6172 static
6173 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
6174                            bool *capable)
6175 {
6176         u8 rx_caps[3];
6177         int ret;
6178
6179         *capable = false;
6180         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6181                                DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
6182                                rx_caps, HDCP_2_2_RXCAPS_LEN);
6183         if (ret != HDCP_2_2_RXCAPS_LEN)
6184                 return ret >= 0 ? -EIO : ret;
6185
6186         if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
6187             HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
6188                 *capable = true;
6189
6190         return 0;
6191 }
6192
6193 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
6194         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
6195         .read_bksv = intel_dp_hdcp_read_bksv,
6196         .read_bstatus = intel_dp_hdcp_read_bstatus,
6197         .repeater_present = intel_dp_hdcp_repeater_present,
6198         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
6199         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
6200         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
6201         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
6202         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
6203         .check_link = intel_dp_hdcp_check_link,
6204         .hdcp_capable = intel_dp_hdcp_capable,
6205         .write_2_2_msg = intel_dp_hdcp2_write_msg,
6206         .read_2_2_msg = intel_dp_hdcp2_read_msg,
6207         .config_stream_type = intel_dp_hdcp2_config_stream_type,
6208         .check_2_2_link = intel_dp_hdcp2_check_link,
6209         .hdcp_2_2_capable = intel_dp_hdcp2_capable,
6210         .protocol = HDCP_PROTOCOL_DP,
6211 };
6212
6213 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
6214 {
6215         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6216         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6217
6218         lockdep_assert_held(&dev_priv->pps_mutex);
6219
6220         if (!edp_have_panel_vdd(intel_dp))
6221                 return;
6222
6223         /*
6224          * The VDD bit needs a power domain reference, so if the bit is
6225          * already enabled when we boot or resume, grab this reference and
6226          * schedule a vdd off, so we don't hold on to the reference
6227          * indefinitely.
6228          */
6229         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
6230         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
6231
6232         edp_panel_vdd_schedule_off(intel_dp);
6233 }
6234
6235 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
6236 {
6237         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6238         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6239         enum pipe pipe;
6240
6241         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
6242                                   encoder->port, &pipe))
6243                 return pipe;
6244
6245         return INVALID_PIPE;
6246 }
6247
6248 void intel_dp_encoder_reset(struct drm_encoder *encoder)
6249 {
6250         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6251         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6252         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
6253         intel_wakeref_t wakeref;
6254
6255         if (!HAS_DDI(dev_priv))
6256                 intel_dp->DP = I915_READ(intel_dp->output_reg);
6257
6258         if (lspcon->active)
6259                 lspcon_resume(lspcon);
6260
6261         intel_dp->reset_link_params = true;
6262
6263         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
6264             !intel_dp_is_edp(intel_dp))
6265                 return;
6266
6267         with_pps_lock(intel_dp, wakeref) {
6268                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6269                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6270
6271                 if (intel_dp_is_edp(intel_dp)) {
6272                         /*
6273                          * Reinit the power sequencer, in case BIOS did
6274                          * something nasty with it.
6275                          */
6276                         intel_dp_pps_init(intel_dp);
6277                         intel_edp_panel_vdd_sanitize(intel_dp);
6278                 }
6279         }
6280 }
6281
6282 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6283         .force = intel_dp_force,
6284         .fill_modes = drm_helper_probe_single_connector_modes,
6285         .atomic_get_property = intel_digital_connector_atomic_get_property,
6286         .atomic_set_property = intel_digital_connector_atomic_set_property,
6287         .late_register = intel_dp_connector_register,
6288         .early_unregister = intel_dp_connector_unregister,
6289         .destroy = intel_connector_destroy,
6290         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6291         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6292 };
6293
6294 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6295         .detect_ctx = intel_dp_detect,
6296         .get_modes = intel_dp_get_modes,
6297         .mode_valid = intel_dp_mode_valid,
6298         .atomic_check = intel_digital_connector_atomic_check,
6299 };
6300
6301 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6302         .reset = intel_dp_encoder_reset,
6303         .destroy = intel_dp_encoder_destroy,
6304 };
6305
6306 enum irqreturn
6307 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
6308 {
6309         struct intel_dp *intel_dp = &intel_dig_port->dp;
6310
6311         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
6312                 /*
6313                  * vdd off can generate a long pulse on eDP which
6314                  * would require vdd on to handle it, and thus we
6315                  * would end up in an endless cycle of
6316                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
6317                  */
6318                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
6319                               port_name(intel_dig_port->base.port));
6320                 return IRQ_HANDLED;
6321         }
6322
6323         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
6324                       port_name(intel_dig_port->base.port),
6325                       long_hpd ? "long" : "short");
6326
6327         if (long_hpd) {
6328                 intel_dp->reset_link_params = true;
6329                 return IRQ_NONE;
6330         }
6331
6332         if (intel_dp->is_mst) {
6333                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
6334                         /*
6335                          * If we were in MST mode, and device is not
6336                          * there, get out of MST mode
6337                          */
6338                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
6339                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
6340                         intel_dp->is_mst = false;
6341                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6342                                                         intel_dp->is_mst);
6343
6344                         return IRQ_NONE;
6345                 }
6346         }
6347
6348         if (!intel_dp->is_mst) {
6349                 bool handled;
6350
6351                 handled = intel_dp_short_pulse(intel_dp);
6352
6353                 if (!handled)
6354                         return IRQ_NONE;
6355         }
6356
6357         return IRQ_HANDLED;
6358 }
6359
6360 /* check the VBT to see whether the eDP is on another port */
6361 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
6362 {
6363         /*
6364          * eDP not supported on g4x. so bail out early just
6365          * for a bit extra safety in case the VBT is bonkers.
6366          */
6367         if (INTEL_GEN(dev_priv) < 5)
6368                 return false;
6369
6370         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
6371                 return true;
6372
6373         return intel_bios_is_port_edp(dev_priv, port);
6374 }
6375
6376 static void
6377 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6378 {
6379         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6380         enum port port = dp_to_dig_port(intel_dp)->base.port;
6381
6382         if (!IS_G4X(dev_priv) && port != PORT_A)
6383                 intel_attach_force_audio_property(connector);
6384
6385         intel_attach_broadcast_rgb_property(connector);
6386         if (HAS_GMCH(dev_priv))
6387                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6388         else if (INTEL_GEN(dev_priv) >= 5)
6389                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6390
6391         if (intel_dp_is_edp(intel_dp)) {
6392                 u32 allowed_scalers;
6393
6394                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
6395                 if (!HAS_GMCH(dev_priv))
6396                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
6397
6398                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
6399
6400                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
6401
6402         }
6403 }
6404
6405 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
6406 {
6407         intel_dp->panel_power_off_time = ktime_get_boottime();
6408         intel_dp->last_power_on = jiffies;
6409         intel_dp->last_backlight_off = jiffies;
6410 }
6411
6412 static void
6413 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
6414 {
6415         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6416         u32 pp_on, pp_off, pp_ctl;
6417         struct pps_registers regs;
6418
6419         intel_pps_get_registers(intel_dp, &regs);
6420
6421         pp_ctl = ironlake_get_pp_control(intel_dp);
6422
6423         /* Ensure PPS is unlocked */
6424         if (!HAS_DDI(dev_priv))
6425                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6426
6427         pp_on = I915_READ(regs.pp_on);
6428         pp_off = I915_READ(regs.pp_off);
6429
6430         /* Pull timing values out of registers */
6431         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
6432         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
6433         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
6434         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
6435
6436         if (i915_mmio_reg_valid(regs.pp_div)) {
6437                 u32 pp_div;
6438
6439                 pp_div = I915_READ(regs.pp_div);
6440
6441                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
6442         } else {
6443                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
6444         }
6445 }
6446
6447 static void
6448 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6449 {
6450         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6451                       state_name,
6452                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6453 }
6454
6455 static void
6456 intel_pps_verify_state(struct intel_dp *intel_dp)
6457 {
6458         struct edp_power_seq hw;
6459         struct edp_power_seq *sw = &intel_dp->pps_delays;
6460
6461         intel_pps_readout_hw_state(intel_dp, &hw);
6462
6463         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6464             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6465                 DRM_ERROR("PPS state mismatch\n");
6466                 intel_pps_dump_state("sw", sw);
6467                 intel_pps_dump_state("hw", &hw);
6468         }
6469 }
6470
6471 static void
6472 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6473 {
6474         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6475         struct edp_power_seq cur, vbt, spec,
6476                 *final = &intel_dp->pps_delays;
6477
6478         lockdep_assert_held(&dev_priv->pps_mutex);
6479
6480         /* already initialized? */
6481         if (final->t11_t12 != 0)
6482                 return;
6483
6484         intel_pps_readout_hw_state(intel_dp, &cur);
6485
6486         intel_pps_dump_state("cur", &cur);
6487
6488         vbt = dev_priv->vbt.edp.pps;
6489         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6490          * of 500ms appears to be too short. Ocassionally the panel
6491          * just fails to power back on. Increasing the delay to 800ms
6492          * seems sufficient to avoid this problem.
6493          */
6494         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6495                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6496                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6497                               vbt.t11_t12);
6498         }
6499         /* T11_T12 delay is special and actually in units of 100ms, but zero
6500          * based in the hw (so we need to add 100 ms). But the sw vbt
6501          * table multiplies it with 1000 to make it in units of 100usec,
6502          * too. */
6503         vbt.t11_t12 += 100 * 10;
6504
6505         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6506          * our hw here, which are all in 100usec. */
6507         spec.t1_t3 = 210 * 10;
6508         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6509         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6510         spec.t10 = 500 * 10;
6511         /* This one is special and actually in units of 100ms, but zero
6512          * based in the hw (so we need to add 100 ms). But the sw vbt
6513          * table multiplies it with 1000 to make it in units of 100usec,
6514          * too. */
6515         spec.t11_t12 = (510 + 100) * 10;
6516
6517         intel_pps_dump_state("vbt", &vbt);
6518
6519         /* Use the max of the register settings and vbt. If both are
6520          * unset, fall back to the spec limits. */
6521 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
6522                                        spec.field : \
6523                                        max(cur.field, vbt.field))
6524         assign_final(t1_t3);
6525         assign_final(t8);
6526         assign_final(t9);
6527         assign_final(t10);
6528         assign_final(t11_t12);
6529 #undef assign_final
6530
6531 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
6532         intel_dp->panel_power_up_delay = get_delay(t1_t3);
6533         intel_dp->backlight_on_delay = get_delay(t8);
6534         intel_dp->backlight_off_delay = get_delay(t9);
6535         intel_dp->panel_power_down_delay = get_delay(t10);
6536         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6537 #undef get_delay
6538
6539         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6540                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
6541                       intel_dp->panel_power_cycle_delay);
6542
6543         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6544                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
6545
6546         /*
6547          * We override the HW backlight delays to 1 because we do manual waits
6548          * on them. For T8, even BSpec recommends doing it. For T9, if we
6549          * don't do this, we'll end up waiting for the backlight off delay
6550          * twice: once when we do the manual sleep, and once when we disable
6551          * the panel and wait for the PP_STATUS bit to become zero.
6552          */
6553         final->t8 = 1;
6554         final->t9 = 1;
6555
6556         /*
6557          * HW has only a 100msec granularity for t11_t12 so round it up
6558          * accordingly.
6559          */
6560         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6561 }
6562
6563 static void
6564 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6565                                               bool force_disable_vdd)
6566 {
6567         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6568         u32 pp_on, pp_off, port_sel = 0;
6569         int div = dev_priv->rawclk_freq / 1000;
6570         struct pps_registers regs;
6571         enum port port = dp_to_dig_port(intel_dp)->base.port;
6572         const struct edp_power_seq *seq = &intel_dp->pps_delays;
6573
6574         lockdep_assert_held(&dev_priv->pps_mutex);
6575
6576         intel_pps_get_registers(intel_dp, &regs);
6577
6578         /*
6579          * On some VLV machines the BIOS can leave the VDD
6580          * enabled even on power sequencers which aren't
6581          * hooked up to any port. This would mess up the
6582          * power domain tracking the first time we pick
6583          * one of these power sequencers for use since
6584          * edp_panel_vdd_on() would notice that the VDD was
6585          * already on and therefore wouldn't grab the power
6586          * domain reference. Disable VDD first to avoid this.
6587          * This also avoids spuriously turning the VDD on as
6588          * soon as the new power sequencer gets initialized.
6589          */
6590         if (force_disable_vdd) {
6591                 u32 pp = ironlake_get_pp_control(intel_dp);
6592
6593                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
6594
6595                 if (pp & EDP_FORCE_VDD)
6596                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
6597
6598                 pp &= ~EDP_FORCE_VDD;
6599
6600                 I915_WRITE(regs.pp_ctrl, pp);
6601         }
6602
6603         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
6604                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
6605         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
6606                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
6607
6608         /* Haswell doesn't have any port selection bits for the panel
6609          * power sequencer any more. */
6610         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6611                 port_sel = PANEL_PORT_SELECT_VLV(port);
6612         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6613                 switch (port) {
6614                 case PORT_A:
6615                         port_sel = PANEL_PORT_SELECT_DPA;
6616                         break;
6617                 case PORT_C:
6618                         port_sel = PANEL_PORT_SELECT_DPC;
6619                         break;
6620                 case PORT_D:
6621                         port_sel = PANEL_PORT_SELECT_DPD;
6622                         break;
6623                 default:
6624                         MISSING_CASE(port);
6625                         break;
6626                 }
6627         }
6628
6629         pp_on |= port_sel;
6630
6631         I915_WRITE(regs.pp_on, pp_on);
6632         I915_WRITE(regs.pp_off, pp_off);
6633
6634         /*
6635          * Compute the divisor for the pp clock, simply match the Bspec formula.
6636          */
6637         if (i915_mmio_reg_valid(regs.pp_div)) {
6638                 I915_WRITE(regs.pp_div,
6639                            REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) |
6640                            REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
6641         } else {
6642                 u32 pp_ctl;
6643
6644                 pp_ctl = I915_READ(regs.pp_ctrl);
6645                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
6646                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
6647                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6648         }
6649
6650         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6651                       I915_READ(regs.pp_on),
6652                       I915_READ(regs.pp_off),
6653                       i915_mmio_reg_valid(regs.pp_div) ?
6654                       I915_READ(regs.pp_div) :
6655                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
6656 }
6657
6658 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6659 {
6660         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6661
6662         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6663                 vlv_initial_power_sequencer_setup(intel_dp);
6664         } else {
6665                 intel_dp_init_panel_power_sequencer(intel_dp);
6666                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6667         }
6668 }
6669
6670 /**
6671  * intel_dp_set_drrs_state - program registers for RR switch to take effect
6672  * @dev_priv: i915 device
6673  * @crtc_state: a pointer to the active intel_crtc_state
6674  * @refresh_rate: RR to be programmed
6675  *
6676  * This function gets called when refresh rate (RR) has to be changed from
6677  * one frequency to another. Switches can be between high and low RR
6678  * supported by the panel or to any other RR based on media playback (in
6679  * this case, RR value needs to be passed from user space).
6680  *
6681  * The caller of this function needs to take a lock on dev_priv->drrs.
6682  */
6683 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6684                                     const struct intel_crtc_state *crtc_state,
6685                                     int refresh_rate)
6686 {
6687         struct intel_encoder *encoder;
6688         struct intel_digital_port *dig_port = NULL;
6689         struct intel_dp *intel_dp = dev_priv->drrs.dp;
6690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6691         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6692
6693         if (refresh_rate <= 0) {
6694                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6695                 return;
6696         }
6697
6698         if (intel_dp == NULL) {
6699                 DRM_DEBUG_KMS("DRRS not supported.\n");
6700                 return;
6701         }
6702
6703         dig_port = dp_to_dig_port(intel_dp);
6704         encoder = &dig_port->base;
6705
6706         if (!intel_crtc) {
6707                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6708                 return;
6709         }
6710
6711         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6712                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6713                 return;
6714         }
6715
6716         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6717                         refresh_rate)
6718                 index = DRRS_LOW_RR;
6719
6720         if (index == dev_priv->drrs.refresh_rate_type) {
6721                 DRM_DEBUG_KMS(
6722                         "DRRS requested for previously set RR...ignoring\n");
6723                 return;
6724         }
6725
6726         if (!crtc_state->base.active) {
6727                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6728                 return;
6729         }
6730
6731         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6732                 switch (index) {
6733                 case DRRS_HIGH_RR:
6734                         intel_dp_set_m_n(crtc_state, M1_N1);
6735                         break;
6736                 case DRRS_LOW_RR:
6737                         intel_dp_set_m_n(crtc_state, M2_N2);
6738                         break;
6739                 case DRRS_MAX_RR:
6740                 default:
6741                         DRM_ERROR("Unsupported refreshrate type\n");
6742                 }
6743         } else if (INTEL_GEN(dev_priv) > 6) {
6744                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6745                 u32 val;
6746
6747                 val = I915_READ(reg);
6748                 if (index > DRRS_HIGH_RR) {
6749                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6750                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6751                         else
6752                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6753                 } else {
6754                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6755                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6756                         else
6757                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6758                 }
6759                 I915_WRITE(reg, val);
6760         }
6761
6762         dev_priv->drrs.refresh_rate_type = index;
6763
6764         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6765 }
6766
6767 /**
6768  * intel_edp_drrs_enable - init drrs struct if supported
6769  * @intel_dp: DP struct
6770  * @crtc_state: A pointer to the active crtc state.
6771  *
6772  * Initializes frontbuffer_bits and drrs.dp
6773  */
6774 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6775                            const struct intel_crtc_state *crtc_state)
6776 {
6777         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6778
6779         if (!crtc_state->has_drrs) {
6780                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6781                 return;
6782         }
6783
6784         if (dev_priv->psr.enabled) {
6785                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6786                 return;
6787         }
6788
6789         mutex_lock(&dev_priv->drrs.mutex);
6790         if (dev_priv->drrs.dp) {
6791                 DRM_DEBUG_KMS("DRRS already enabled\n");
6792                 goto unlock;
6793         }
6794
6795         dev_priv->drrs.busy_frontbuffer_bits = 0;
6796
6797         dev_priv->drrs.dp = intel_dp;
6798
6799 unlock:
6800         mutex_unlock(&dev_priv->drrs.mutex);
6801 }
6802
6803 /**
6804  * intel_edp_drrs_disable - Disable DRRS
6805  * @intel_dp: DP struct
6806  * @old_crtc_state: Pointer to old crtc_state.
6807  *
6808  */
6809 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6810                             const struct intel_crtc_state *old_crtc_state)
6811 {
6812         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6813
6814         if (!old_crtc_state->has_drrs)
6815                 return;
6816
6817         mutex_lock(&dev_priv->drrs.mutex);
6818         if (!dev_priv->drrs.dp) {
6819                 mutex_unlock(&dev_priv->drrs.mutex);
6820                 return;
6821         }
6822
6823         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6824                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
6825                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
6826
6827         dev_priv->drrs.dp = NULL;
6828         mutex_unlock(&dev_priv->drrs.mutex);
6829
6830         cancel_delayed_work_sync(&dev_priv->drrs.work);
6831 }
6832
6833 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6834 {
6835         struct drm_i915_private *dev_priv =
6836                 container_of(work, typeof(*dev_priv), drrs.work.work);
6837         struct intel_dp *intel_dp;
6838
6839         mutex_lock(&dev_priv->drrs.mutex);
6840
6841         intel_dp = dev_priv->drrs.dp;
6842
6843         if (!intel_dp)
6844                 goto unlock;
6845
6846         /*
6847          * The delayed work can race with an invalidate hence we need to
6848          * recheck.
6849          */
6850
6851         if (dev_priv->drrs.busy_frontbuffer_bits)
6852                 goto unlock;
6853
6854         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6855                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6856
6857                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6858                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
6859         }
6860
6861 unlock:
6862         mutex_unlock(&dev_priv->drrs.mutex);
6863 }
6864
6865 /**
6866  * intel_edp_drrs_invalidate - Disable Idleness DRRS
6867  * @dev_priv: i915 device
6868  * @frontbuffer_bits: frontbuffer plane tracking bits
6869  *
6870  * This function gets called everytime rendering on the given planes start.
6871  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6872  *
6873  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6874  */
6875 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6876                                unsigned int frontbuffer_bits)
6877 {
6878         struct drm_crtc *crtc;
6879         enum pipe pipe;
6880
6881         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6882                 return;
6883
6884         cancel_delayed_work(&dev_priv->drrs.work);
6885
6886         mutex_lock(&dev_priv->drrs.mutex);
6887         if (!dev_priv->drrs.dp) {
6888                 mutex_unlock(&dev_priv->drrs.mutex);
6889                 return;
6890         }
6891
6892         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6893         pipe = to_intel_crtc(crtc)->pipe;
6894
6895         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6896         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6897
6898         /* invalidate means busy screen hence upclock */
6899         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6900                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6901                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6902
6903         mutex_unlock(&dev_priv->drrs.mutex);
6904 }
6905
6906 /**
6907  * intel_edp_drrs_flush - Restart Idleness DRRS
6908  * @dev_priv: i915 device
6909  * @frontbuffer_bits: frontbuffer plane tracking bits
6910  *
6911  * This function gets called every time rendering on the given planes has
6912  * completed or flip on a crtc is completed. So DRRS should be upclocked
6913  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6914  * if no other planes are dirty.
6915  *
6916  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6917  */
6918 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6919                           unsigned int frontbuffer_bits)
6920 {
6921         struct drm_crtc *crtc;
6922         enum pipe pipe;
6923
6924         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6925                 return;
6926
6927         cancel_delayed_work(&dev_priv->drrs.work);
6928
6929         mutex_lock(&dev_priv->drrs.mutex);
6930         if (!dev_priv->drrs.dp) {
6931                 mutex_unlock(&dev_priv->drrs.mutex);
6932                 return;
6933         }
6934
6935         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6936         pipe = to_intel_crtc(crtc)->pipe;
6937
6938         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6939         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6940
6941         /* flush means busy screen hence upclock */
6942         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6943                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6944                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6945
6946         /*
6947          * flush also means no more activity hence schedule downclock, if all
6948          * other fbs are quiescent too
6949          */
6950         if (!dev_priv->drrs.busy_frontbuffer_bits)
6951                 schedule_delayed_work(&dev_priv->drrs.work,
6952                                 msecs_to_jiffies(1000));
6953         mutex_unlock(&dev_priv->drrs.mutex);
6954 }
6955
6956 /**
6957  * DOC: Display Refresh Rate Switching (DRRS)
6958  *
6959  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6960  * which enables swtching between low and high refresh rates,
6961  * dynamically, based on the usage scenario. This feature is applicable
6962  * for internal panels.
6963  *
6964  * Indication that the panel supports DRRS is given by the panel EDID, which
6965  * would list multiple refresh rates for one resolution.
6966  *
6967  * DRRS is of 2 types - static and seamless.
6968  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6969  * (may appear as a blink on screen) and is used in dock-undock scenario.
6970  * Seamless DRRS involves changing RR without any visual effect to the user
6971  * and can be used during normal system usage. This is done by programming
6972  * certain registers.
6973  *
6974  * Support for static/seamless DRRS may be indicated in the VBT based on
6975  * inputs from the panel spec.
6976  *
6977  * DRRS saves power by switching to low RR based on usage scenarios.
6978  *
6979  * The implementation is based on frontbuffer tracking implementation.  When
6980  * there is a disturbance on the screen triggered by user activity or a periodic
6981  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6982  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6983  * made.
6984  *
6985  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6986  * and intel_edp_drrs_flush() are called.
6987  *
6988  * DRRS can be further extended to support other internal panels and also
6989  * the scenario of video playback wherein RR is set based on the rate
6990  * requested by userspace.
6991  */
6992
6993 /**
6994  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6995  * @connector: eDP connector
6996  * @fixed_mode: preferred mode of panel
6997  *
6998  * This function is  called only once at driver load to initialize basic
6999  * DRRS stuff.
7000  *
7001  * Returns:
7002  * Downclock mode if panel supports it, else return NULL.
7003  * DRRS support is determined by the presence of downclock mode (apart
7004  * from VBT setting).
7005  */
7006 static struct drm_display_mode *
7007 intel_dp_drrs_init(struct intel_connector *connector,
7008                    struct drm_display_mode *fixed_mode)
7009 {
7010         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7011         struct drm_display_mode *downclock_mode = NULL;
7012
7013         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
7014         mutex_init(&dev_priv->drrs.mutex);
7015
7016         if (INTEL_GEN(dev_priv) <= 6) {
7017                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
7018                 return NULL;
7019         }
7020
7021         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
7022                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
7023                 return NULL;
7024         }
7025
7026         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
7027         if (!downclock_mode) {
7028                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
7029                 return NULL;
7030         }
7031
7032         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
7033
7034         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
7035         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
7036         return downclock_mode;
7037 }
7038
7039 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
7040                                      struct intel_connector *intel_connector)
7041 {
7042         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7043         struct drm_device *dev = &dev_priv->drm;
7044         struct drm_connector *connector = &intel_connector->base;
7045         struct drm_display_mode *fixed_mode = NULL;
7046         struct drm_display_mode *downclock_mode = NULL;
7047         bool has_dpcd;
7048         enum pipe pipe = INVALID_PIPE;
7049         intel_wakeref_t wakeref;
7050         struct edid *edid;
7051
7052         if (!intel_dp_is_edp(intel_dp))
7053                 return true;
7054
7055         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
7056
7057         /*
7058          * On IBX/CPT we may get here with LVDS already registered. Since the
7059          * driver uses the only internal power sequencer available for both
7060          * eDP and LVDS bail out early in this case to prevent interfering
7061          * with an already powered-on LVDS power sequencer.
7062          */
7063         if (intel_get_lvds_encoder(dev_priv)) {
7064                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7065                 DRM_INFO("LVDS was detected, not registering eDP\n");
7066
7067                 return false;
7068         }
7069
7070         with_pps_lock(intel_dp, wakeref) {
7071                 intel_dp_init_panel_power_timestamps(intel_dp);
7072                 intel_dp_pps_init(intel_dp);
7073                 intel_edp_panel_vdd_sanitize(intel_dp);
7074         }
7075
7076         /* Cache DPCD and EDID for edp. */
7077         has_dpcd = intel_edp_init_dpcd(intel_dp);
7078
7079         if (!has_dpcd) {
7080                 /* if this fails, presume the device is a ghost */
7081                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
7082                 goto out_vdd_off;
7083         }
7084
7085         mutex_lock(&dev->mode_config.mutex);
7086         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
7087         if (edid) {
7088                 if (drm_add_edid_modes(connector, edid)) {
7089                         drm_connector_update_edid_property(connector,
7090                                                                 edid);
7091                 } else {
7092                         kfree(edid);
7093                         edid = ERR_PTR(-EINVAL);
7094                 }
7095         } else {
7096                 edid = ERR_PTR(-ENOENT);
7097         }
7098         intel_connector->edid = edid;
7099
7100         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
7101         if (fixed_mode)
7102                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
7103
7104         /* fallback to VBT if available for eDP */
7105         if (!fixed_mode)
7106                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
7107         mutex_unlock(&dev->mode_config.mutex);
7108
7109         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7110                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
7111                 register_reboot_notifier(&intel_dp->edp_notifier);
7112
7113                 /*
7114                  * Figure out the current pipe for the initial backlight setup.
7115                  * If the current pipe isn't valid, try the PPS pipe, and if that
7116                  * fails just assume pipe A.
7117                  */
7118                 pipe = vlv_active_pipe(intel_dp);
7119
7120                 if (pipe != PIPE_A && pipe != PIPE_B)
7121                         pipe = intel_dp->pps_pipe;
7122
7123                 if (pipe != PIPE_A && pipe != PIPE_B)
7124                         pipe = PIPE_A;
7125
7126                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
7127                               pipe_name(pipe));
7128         }
7129
7130         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
7131         intel_connector->panel.backlight.power = intel_edp_backlight_power;
7132         intel_panel_setup_backlight(connector, pipe);
7133
7134         if (fixed_mode)
7135                 drm_connector_init_panel_orientation_property(
7136                         connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
7137
7138         return true;
7139
7140 out_vdd_off:
7141         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7142         /*
7143          * vdd might still be enabled do to the delayed vdd off.
7144          * Make sure vdd is actually turned off here.
7145          */
7146         with_pps_lock(intel_dp, wakeref)
7147                 edp_panel_vdd_off_sync(intel_dp);
7148
7149         return false;
7150 }
7151
7152 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
7153 {
7154         struct intel_connector *intel_connector;
7155         struct drm_connector *connector;
7156
7157         intel_connector = container_of(work, typeof(*intel_connector),
7158                                        modeset_retry_work);
7159         connector = &intel_connector->base;
7160         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
7161                       connector->name);
7162
7163         /* Grab the locks before changing connector property*/
7164         mutex_lock(&connector->dev->mode_config.mutex);
7165         /* Set connector link status to BAD and send a Uevent to notify
7166          * userspace to do a modeset.
7167          */
7168         drm_connector_set_link_status_property(connector,
7169                                                DRM_MODE_LINK_STATUS_BAD);
7170         mutex_unlock(&connector->dev->mode_config.mutex);
7171         /* Send Hotplug uevent so userspace can reprobe */
7172         drm_kms_helper_hotplug_event(connector->dev);
7173 }
7174
7175 bool
7176 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
7177                         struct intel_connector *intel_connector)
7178 {
7179         struct drm_connector *connector = &intel_connector->base;
7180         struct intel_dp *intel_dp = &intel_dig_port->dp;
7181         struct intel_encoder *intel_encoder = &intel_dig_port->base;
7182         struct drm_device *dev = intel_encoder->base.dev;
7183         struct drm_i915_private *dev_priv = to_i915(dev);
7184         enum port port = intel_encoder->port;
7185         int type;
7186
7187         /* Initialize the work for modeset in case of link train failure */
7188         INIT_WORK(&intel_connector->modeset_retry_work,
7189                   intel_dp_modeset_retry_work_fn);
7190
7191         if (WARN(intel_dig_port->max_lanes < 1,
7192                  "Not enough lanes (%d) for DP on port %c\n",
7193                  intel_dig_port->max_lanes, port_name(port)))
7194                 return false;
7195
7196         intel_dp_set_source_rates(intel_dp);
7197
7198         intel_dp->reset_link_params = true;
7199         intel_dp->pps_pipe = INVALID_PIPE;
7200         intel_dp->active_pipe = INVALID_PIPE;
7201
7202         /* intel_dp vfuncs */
7203         if (HAS_DDI(dev_priv))
7204                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
7205
7206         /* Preserve the current hw state. */
7207         intel_dp->DP = I915_READ(intel_dp->output_reg);
7208         intel_dp->attached_connector = intel_connector;
7209
7210         if (intel_dp_is_port_edp(dev_priv, port)) {
7211                 /*
7212                  * Currently we don't support eDP on TypeC ports, although in
7213                  * theory it could work on TypeC legacy ports.
7214                  */
7215                 WARN_ON(intel_port_is_tc(dev_priv, port));
7216                 type = DRM_MODE_CONNECTOR_eDP;
7217         } else {
7218                 type = DRM_MODE_CONNECTOR_DisplayPort;
7219         }
7220
7221         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7222                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7223
7224         /*
7225          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
7226          * for DP the encoder type can be set by the caller to
7227          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
7228          */
7229         if (type == DRM_MODE_CONNECTOR_eDP)
7230                 intel_encoder->type = INTEL_OUTPUT_EDP;
7231
7232         /* eDP only on port B and/or C on vlv/chv */
7233         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7234                     intel_dp_is_edp(intel_dp) &&
7235                     port != PORT_B && port != PORT_C))
7236                 return false;
7237
7238         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
7239                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
7240                         port_name(port));
7241
7242         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
7243         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
7244
7245         if (!HAS_GMCH(dev_priv))
7246                 connector->interlace_allowed = true;
7247         connector->doublescan_allowed = 0;
7248
7249         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
7250
7251         intel_dp_aux_init(intel_dp);
7252
7253         intel_connector_attach_encoder(intel_connector, intel_encoder);
7254
7255         if (HAS_DDI(dev_priv))
7256                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
7257         else
7258                 intel_connector->get_hw_state = intel_connector_get_hw_state;
7259
7260         /* init MST on ports that can support it */
7261         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
7262             (port == PORT_B || port == PORT_C ||
7263              port == PORT_D || port == PORT_F))
7264                 intel_dp_mst_encoder_init(intel_dig_port,
7265                                           intel_connector->base.base.id);
7266
7267         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
7268                 intel_dp_aux_fini(intel_dp);
7269                 intel_dp_mst_encoder_cleanup(intel_dig_port);
7270                 goto fail;
7271         }
7272
7273         intel_dp_add_properties(intel_dp, connector);
7274
7275         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
7276                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
7277                 if (ret)
7278                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
7279         }
7280
7281         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
7282          * 0xd.  Failure to do so will result in spurious interrupts being
7283          * generated on the port when a cable is not attached.
7284          */
7285         if (IS_G45(dev_priv)) {
7286                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
7287                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
7288         }
7289
7290         return true;
7291
7292 fail:
7293         drm_connector_cleanup(connector);
7294
7295         return false;
7296 }
7297
7298 bool intel_dp_init(struct drm_i915_private *dev_priv,
7299                    i915_reg_t output_reg,
7300                    enum port port)
7301 {
7302         struct intel_digital_port *intel_dig_port;
7303         struct intel_encoder *intel_encoder;
7304         struct drm_encoder *encoder;
7305         struct intel_connector *intel_connector;
7306
7307         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
7308         if (!intel_dig_port)
7309                 return false;
7310
7311         intel_connector = intel_connector_alloc();
7312         if (!intel_connector)
7313                 goto err_connector_alloc;
7314
7315         intel_encoder = &intel_dig_port->base;
7316         encoder = &intel_encoder->base;
7317
7318         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
7319                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
7320                              "DP %c", port_name(port)))
7321                 goto err_encoder_init;
7322
7323         intel_encoder->hotplug = intel_dp_hotplug;
7324         intel_encoder->compute_config = intel_dp_compute_config;
7325         intel_encoder->get_hw_state = intel_dp_get_hw_state;
7326         intel_encoder->get_config = intel_dp_get_config;
7327         intel_encoder->update_pipe = intel_panel_update_backlight;
7328         intel_encoder->suspend = intel_dp_encoder_suspend;
7329         if (IS_CHERRYVIEW(dev_priv)) {
7330                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
7331                 intel_encoder->pre_enable = chv_pre_enable_dp;
7332                 intel_encoder->enable = vlv_enable_dp;
7333                 intel_encoder->disable = vlv_disable_dp;
7334                 intel_encoder->post_disable = chv_post_disable_dp;
7335                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
7336         } else if (IS_VALLEYVIEW(dev_priv)) {
7337                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
7338                 intel_encoder->pre_enable = vlv_pre_enable_dp;
7339                 intel_encoder->enable = vlv_enable_dp;
7340                 intel_encoder->disable = vlv_disable_dp;
7341                 intel_encoder->post_disable = vlv_post_disable_dp;
7342         } else {
7343                 intel_encoder->pre_enable = g4x_pre_enable_dp;
7344                 intel_encoder->enable = g4x_enable_dp;
7345                 intel_encoder->disable = g4x_disable_dp;
7346                 intel_encoder->post_disable = g4x_post_disable_dp;
7347         }
7348
7349         intel_dig_port->dp.output_reg = output_reg;
7350         intel_dig_port->max_lanes = 4;
7351
7352         intel_encoder->type = INTEL_OUTPUT_DP;
7353         intel_encoder->power_domain = intel_port_to_power_domain(port);
7354         if (IS_CHERRYVIEW(dev_priv)) {
7355                 if (port == PORT_D)
7356                         intel_encoder->crtc_mask = 1 << 2;
7357                 else
7358                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
7359         } else {
7360                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
7361         }
7362         intel_encoder->cloneable = 0;
7363         intel_encoder->port = port;
7364
7365         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
7366
7367         if (port != PORT_A)
7368                 intel_infoframe_init(intel_dig_port);
7369
7370         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
7371         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
7372                 goto err_init_connector;
7373
7374         return true;
7375
7376 err_init_connector:
7377         drm_encoder_cleanup(encoder);
7378 err_encoder_init:
7379         kfree(intel_connector);
7380 err_connector_alloc:
7381         kfree(intel_dig_port);
7382         return false;
7383 }
7384
7385 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
7386 {
7387         struct intel_encoder *encoder;
7388
7389         for_each_intel_encoder(&dev_priv->drm, encoder) {
7390                 struct intel_dp *intel_dp;
7391
7392                 if (encoder->type != INTEL_OUTPUT_DDI)
7393                         continue;
7394
7395                 intel_dp = enc_to_intel_dp(&encoder->base);
7396
7397                 if (!intel_dp->can_mst)
7398                         continue;
7399
7400                 if (intel_dp->is_mst)
7401                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
7402         }
7403 }
7404
7405 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
7406 {
7407         struct intel_encoder *encoder;
7408
7409         for_each_intel_encoder(&dev_priv->drm, encoder) {
7410                 struct intel_dp *intel_dp;
7411                 int ret;
7412
7413                 if (encoder->type != INTEL_OUTPUT_DDI)
7414                         continue;
7415
7416                 intel_dp = enc_to_intel_dp(&encoder->base);
7417
7418                 if (!intel_dp->can_mst)
7419                         continue;
7420
7421                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
7422                 if (ret) {
7423                         intel_dp->is_mst = false;
7424                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7425                                                         false);
7426                 }
7427         }
7428 }