2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_crtc_helper.h>
37 #include <drm/drm_edid.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
42 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44 /* Compliance test status bits */
45 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
55 static const struct dp_link_dpll gen4_dpll[] = {
57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
62 static const struct dp_link_dpll pch_dpll[] = {
64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
69 static const struct dp_link_dpll vlv_dpll[] = {
71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
80 static const struct dp_link_dpll chv_dpll[] = {
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96 static const int skl_rates[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98 static const int default_rates[] = { 162000, 270000, 540000 };
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
107 static bool is_edp(struct intel_dp *intel_dp)
109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
118 return intel_dig_port->base.base.dev;
121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
126 static void intel_dp_link_down(struct intel_dp *intel_dp);
127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
130 static void vlv_steal_power_sequencer(struct drm_device *dev,
132 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
135 intel_dp_max_link_bw(struct intel_dp *intel_dp)
137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
147 max_link_bw = DP_LINK_BW_1_62;
153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
156 u8 source_max, sink_max;
158 source_max = intel_dig_port->max_lanes;
159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
161 return min(source_max, sink_max);
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
170 * 270000 * 1 * 8 / 10 == 216000
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
182 intel_dp_link_required(int pixel_clock, int bpp)
184 return (pixel_clock * bpp + 9) / 10;
188 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
190 return (max_link_clock * max_lanes * 8) / 10;
194 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
196 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
197 struct intel_encoder *encoder = &intel_dig_port->base;
198 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
199 int max_dotclk = dev_priv->max_dotclk_freq;
202 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
204 if (type != DP_DS_PORT_TYPE_VGA)
207 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
208 intel_dp->downstream_ports);
210 if (ds_max_dotclk != 0)
211 max_dotclk = min(max_dotclk, ds_max_dotclk);
216 static enum drm_mode_status
217 intel_dp_mode_valid(struct drm_connector *connector,
218 struct drm_display_mode *mode)
220 struct intel_dp *intel_dp = intel_attached_dp(connector);
221 struct intel_connector *intel_connector = to_intel_connector(connector);
222 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
223 int target_clock = mode->clock;
224 int max_rate, mode_rate, max_lanes, max_link_clock;
227 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
229 if (is_edp(intel_dp) && fixed_mode) {
230 if (mode->hdisplay > fixed_mode->hdisplay)
233 if (mode->vdisplay > fixed_mode->vdisplay)
236 target_clock = fixed_mode->clock;
239 max_link_clock = intel_dp_max_link_rate(intel_dp);
240 max_lanes = intel_dp_max_lane_count(intel_dp);
242 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
243 mode_rate = intel_dp_link_required(target_clock, 18);
245 if (mode_rate > max_rate || target_clock > max_dotclk)
246 return MODE_CLOCK_HIGH;
248 if (mode->clock < 10000)
249 return MODE_CLOCK_LOW;
251 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
252 return MODE_H_ILLEGAL;
257 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
264 for (i = 0; i < src_bytes; i++)
265 v |= ((uint32_t) src[i]) << ((3-i) * 8);
269 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
274 for (i = 0; i < dst_bytes; i++)
275 dst[i] = src >> ((3-i) * 8);
279 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
280 struct intel_dp *intel_dp);
282 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
283 struct intel_dp *intel_dp);
285 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
287 static void pps_lock(struct intel_dp *intel_dp)
289 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
290 struct intel_encoder *encoder = &intel_dig_port->base;
291 struct drm_device *dev = encoder->base.dev;
292 struct drm_i915_private *dev_priv = to_i915(dev);
293 enum intel_display_power_domain power_domain;
296 * See vlv_power_sequencer_reset() why we need
297 * a power domain reference here.
299 power_domain = intel_display_port_aux_power_domain(encoder);
300 intel_display_power_get(dev_priv, power_domain);
302 mutex_lock(&dev_priv->pps_mutex);
305 static void pps_unlock(struct intel_dp *intel_dp)
307 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
308 struct intel_encoder *encoder = &intel_dig_port->base;
309 struct drm_device *dev = encoder->base.dev;
310 struct drm_i915_private *dev_priv = to_i915(dev);
311 enum intel_display_power_domain power_domain;
313 mutex_unlock(&dev_priv->pps_mutex);
315 power_domain = intel_display_port_aux_power_domain(encoder);
316 intel_display_power_put(dev_priv, power_domain);
320 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
323 struct drm_device *dev = intel_dig_port->base.base.dev;
324 struct drm_i915_private *dev_priv = to_i915(dev);
325 enum pipe pipe = intel_dp->pps_pipe;
326 bool pll_enabled, release_cl_override = false;
327 enum dpio_phy phy = DPIO_PHY(pipe);
328 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
331 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
332 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
333 pipe_name(pipe), port_name(intel_dig_port->port)))
336 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
337 pipe_name(pipe), port_name(intel_dig_port->port));
339 /* Preserve the BIOS-computed detected bit. This is
340 * supposed to be read-only.
342 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
343 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
344 DP |= DP_PORT_WIDTH(1);
345 DP |= DP_LINK_TRAIN_PAT_1;
347 if (IS_CHERRYVIEW(dev_priv))
348 DP |= DP_PIPE_SELECT_CHV(pipe);
349 else if (pipe == PIPE_B)
350 DP |= DP_PIPEB_SELECT;
352 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
355 * The DPLL for the pipe must be enabled for this to work.
356 * So enable temporarily it if it's not already enabled.
359 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
360 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
362 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev_priv) ?
363 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
364 DRM_ERROR("Failed to force on pll for pipe %c!\n",
371 * Similar magic as in intel_dp_enable_port().
372 * We _must_ do this port enable + disable trick
373 * to make this power seqeuencer lock onto the port.
374 * Otherwise even VDD force bit won't work.
376 I915_WRITE(intel_dp->output_reg, DP);
377 POSTING_READ(intel_dp->output_reg);
379 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
380 POSTING_READ(intel_dp->output_reg);
382 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
383 POSTING_READ(intel_dp->output_reg);
386 vlv_force_pll_off(dev, pipe);
388 if (release_cl_override)
389 chv_phy_powergate_ch(dev_priv, phy, ch, false);
394 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
396 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
397 struct drm_device *dev = intel_dig_port->base.base.dev;
398 struct drm_i915_private *dev_priv = to_i915(dev);
399 struct intel_encoder *encoder;
400 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
403 lockdep_assert_held(&dev_priv->pps_mutex);
405 /* We should never land here with regular DP ports */
406 WARN_ON(!is_edp(intel_dp));
408 if (intel_dp->pps_pipe != INVALID_PIPE)
409 return intel_dp->pps_pipe;
412 * We don't have power sequencer currently.
413 * Pick one that's not used by other ports.
415 for_each_intel_encoder(dev, encoder) {
416 struct intel_dp *tmp;
418 if (encoder->type != INTEL_OUTPUT_EDP)
421 tmp = enc_to_intel_dp(&encoder->base);
423 if (tmp->pps_pipe != INVALID_PIPE)
424 pipes &= ~(1 << tmp->pps_pipe);
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
431 if (WARN_ON(pipes == 0))
434 pipe = ffs(pipes) - 1;
436 vlv_steal_power_sequencer(dev, pipe);
437 intel_dp->pps_pipe = pipe;
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp->pps_pipe),
441 port_name(intel_dig_port->port));
443 /* init power sequencer on this pipe and port */
444 intel_dp_init_panel_power_sequencer(dev, intel_dp);
445 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
451 vlv_power_sequencer_kick(intel_dp);
453 return intel_dp->pps_pipe;
457 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
459 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
460 struct drm_device *dev = intel_dig_port->base.base.dev;
461 struct drm_i915_private *dev_priv = to_i915(dev);
463 lockdep_assert_held(&dev_priv->pps_mutex);
465 /* We should never land here with regular DP ports */
466 WARN_ON(!is_edp(intel_dp));
469 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
470 * mapping needs to be retrieved from VBT, for now just hard-code to
471 * use instance #0 always.
473 if (!intel_dp->pps_reset)
476 intel_dp->pps_reset = false;
479 * Only the HW needs to be reprogrammed, the SW state is fixed and
480 * has been setup during connector init.
482 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
487 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
490 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
493 return I915_READ(PP_STATUS(pipe)) & PP_ON;
496 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
499 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
502 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
509 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
511 vlv_pipe_check pipe_check)
515 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
516 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
517 PANEL_PORT_SELECT_MASK;
519 if (port_sel != PANEL_PORT_SELECT_VLV(port))
522 if (!pipe_check(dev_priv, pipe))
532 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
534 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
535 struct drm_device *dev = intel_dig_port->base.base.dev;
536 struct drm_i915_private *dev_priv = to_i915(dev);
537 enum port port = intel_dig_port->port;
539 lockdep_assert_held(&dev_priv->pps_mutex);
541 /* try to find a pipe with this port selected */
542 /* first pick one where the panel is on */
543 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
545 /* didn't find one? pick one where vdd is on */
546 if (intel_dp->pps_pipe == INVALID_PIPE)
547 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
548 vlv_pipe_has_vdd_on);
549 /* didn't find one? pick one with just the correct port */
550 if (intel_dp->pps_pipe == INVALID_PIPE)
551 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
554 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
555 if (intel_dp->pps_pipe == INVALID_PIPE) {
556 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
561 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
562 port_name(port), pipe_name(intel_dp->pps_pipe));
564 intel_dp_init_panel_power_sequencer(dev, intel_dp);
565 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
568 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
570 struct drm_device *dev = &dev_priv->drm;
571 struct intel_encoder *encoder;
573 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
574 !IS_BROXTON(dev_priv)))
578 * We can't grab pps_mutex here due to deadlock with power_domain
579 * mutex when power_domain functions are called while holding pps_mutex.
580 * That also means that in order to use pps_pipe the code needs to
581 * hold both a power domain reference and pps_mutex, and the power domain
582 * reference get/put must be done while _not_ holding pps_mutex.
583 * pps_{lock,unlock}() do these steps in the correct order, so one
584 * should use them always.
587 for_each_intel_encoder(dev, encoder) {
588 struct intel_dp *intel_dp;
590 if (encoder->type != INTEL_OUTPUT_EDP)
593 intel_dp = enc_to_intel_dp(&encoder->base);
594 if (IS_BROXTON(dev_priv))
595 intel_dp->pps_reset = true;
597 intel_dp->pps_pipe = INVALID_PIPE;
601 struct pps_registers {
609 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
610 struct intel_dp *intel_dp,
611 struct pps_registers *regs)
615 memset(regs, 0, sizeof(*regs));
617 if (IS_BROXTON(dev_priv))
618 pps_idx = bxt_power_sequencer_idx(intel_dp);
619 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
620 pps_idx = vlv_power_sequencer_pipe(intel_dp);
622 regs->pp_ctrl = PP_CONTROL(pps_idx);
623 regs->pp_stat = PP_STATUS(pps_idx);
624 regs->pp_on = PP_ON_DELAYS(pps_idx);
625 regs->pp_off = PP_OFF_DELAYS(pps_idx);
626 if (!IS_BROXTON(dev_priv))
627 regs->pp_div = PP_DIVISOR(pps_idx);
631 _pp_ctrl_reg(struct intel_dp *intel_dp)
633 struct pps_registers regs;
635 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
642 _pp_stat_reg(struct intel_dp *intel_dp)
644 struct pps_registers regs;
646 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
652 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
653 This function only applicable when panel PM state is not to be tracked */
654 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
657 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
659 struct drm_device *dev = intel_dp_to_dev(intel_dp);
660 struct drm_i915_private *dev_priv = to_i915(dev);
662 if (!is_edp(intel_dp) || code != SYS_RESTART)
667 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
668 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
669 i915_reg_t pp_ctrl_reg, pp_div_reg;
672 pp_ctrl_reg = PP_CONTROL(pipe);
673 pp_div_reg = PP_DIVISOR(pipe);
674 pp_div = I915_READ(pp_div_reg);
675 pp_div &= PP_REFERENCE_DIVIDER_MASK;
677 /* 0x1F write to PP_DIV_REG sets max cycle delay */
678 I915_WRITE(pp_div_reg, pp_div | 0x1F);
679 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
680 msleep(intel_dp->panel_power_cycle_delay);
683 pps_unlock(intel_dp);
688 static bool edp_have_panel_power(struct intel_dp *intel_dp)
690 struct drm_device *dev = intel_dp_to_dev(intel_dp);
691 struct drm_i915_private *dev_priv = to_i915(dev);
693 lockdep_assert_held(&dev_priv->pps_mutex);
695 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
696 intel_dp->pps_pipe == INVALID_PIPE)
699 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
702 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
704 struct drm_device *dev = intel_dp_to_dev(intel_dp);
705 struct drm_i915_private *dev_priv = to_i915(dev);
707 lockdep_assert_held(&dev_priv->pps_mutex);
709 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
710 intel_dp->pps_pipe == INVALID_PIPE)
713 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
717 intel_dp_check_edp(struct intel_dp *intel_dp)
719 struct drm_device *dev = intel_dp_to_dev(intel_dp);
720 struct drm_i915_private *dev_priv = to_i915(dev);
722 if (!is_edp(intel_dp))
725 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
726 WARN(1, "eDP powered off while attempting aux channel communication.\n");
727 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
728 I915_READ(_pp_stat_reg(intel_dp)),
729 I915_READ(_pp_ctrl_reg(intel_dp)));
734 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
736 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
737 struct drm_device *dev = intel_dig_port->base.base.dev;
738 struct drm_i915_private *dev_priv = to_i915(dev);
739 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
743 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
745 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
746 msecs_to_jiffies_timeout(10));
748 done = wait_for(C, 10) == 0;
750 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
757 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
759 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
760 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
766 * The clock divider is based off the hrawclk, and would like to run at
767 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
769 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
772 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
774 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
775 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
781 * The clock divider is based off the cdclk or PCH rawclk, and would
782 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
783 * divide by 2000 and use that
785 if (intel_dig_port->port == PORT_A)
786 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
788 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
791 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
793 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
794 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
796 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
797 /* Workaround for non-ULT HSW */
805 return ilk_get_aux_clock_divider(intel_dp, index);
808 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
811 * SKL doesn't need us to program the AUX clock divider (Hardware will
812 * derive the clock from CDCLK automatically). We still implement the
813 * get_aux_clock_divider vfunc to plug-in into the existing code.
815 return index ? 0 : 1;
818 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
821 uint32_t aux_clock_divider)
823 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
824 struct drm_i915_private *dev_priv =
825 to_i915(intel_dig_port->base.base.dev);
826 uint32_t precharge, timeout;
828 if (IS_GEN6(dev_priv))
833 if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
834 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
836 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
838 return DP_AUX_CH_CTL_SEND_BUSY |
840 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
841 DP_AUX_CH_CTL_TIME_OUT_ERROR |
843 DP_AUX_CH_CTL_RECEIVE_ERROR |
844 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
845 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
846 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
849 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
854 return DP_AUX_CH_CTL_SEND_BUSY |
856 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
857 DP_AUX_CH_CTL_TIME_OUT_ERROR |
858 DP_AUX_CH_CTL_TIME_OUT_1600us |
859 DP_AUX_CH_CTL_RECEIVE_ERROR |
860 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
861 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
862 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
866 intel_dp_aux_ch(struct intel_dp *intel_dp,
867 const uint8_t *send, int send_bytes,
868 uint8_t *recv, int recv_size)
870 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
871 struct drm_device *dev = intel_dig_port->base.base.dev;
872 struct drm_i915_private *dev_priv = to_i915(dev);
873 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
874 uint32_t aux_clock_divider;
875 int i, ret, recv_bytes;
878 bool has_aux_irq = HAS_AUX_IRQ(dev);
884 * We will be called with VDD already enabled for dpcd/edid/oui reads.
885 * In such cases we want to leave VDD enabled and it's up to upper layers
886 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
889 vdd = edp_panel_vdd_on(intel_dp);
891 /* dp aux is extremely sensitive to irq latency, hence request the
892 * lowest possible wakeup latency and so prevent the cpu from going into
895 pm_qos_update_request(&dev_priv->pm_qos, 0);
897 intel_dp_check_edp(intel_dp);
899 /* Try to wait for any previous AUX channel activity */
900 for (try = 0; try < 3; try++) {
901 status = I915_READ_NOTRACE(ch_ctl);
902 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
908 static u32 last_status = -1;
909 const u32 status = I915_READ(ch_ctl);
911 if (status != last_status) {
912 WARN(1, "dp_aux_ch not started status 0x%08x\n",
914 last_status = status;
921 /* Only 5 data registers! */
922 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
927 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
928 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
933 /* Must try at least 3 times according to DP spec */
934 for (try = 0; try < 5; try++) {
935 /* Load the send data into the aux channel data registers */
936 for (i = 0; i < send_bytes; i += 4)
937 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
938 intel_dp_pack_aux(send + i,
941 /* Send the command and wait for it to complete */
942 I915_WRITE(ch_ctl, send_ctl);
944 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
946 /* Clear done status and any errors */
950 DP_AUX_CH_CTL_TIME_OUT_ERROR |
951 DP_AUX_CH_CTL_RECEIVE_ERROR);
953 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
956 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
957 * 400us delay required for errors and timeouts
958 * Timeout errors from the HW already meet this
959 * requirement so skip to next iteration
961 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
962 usleep_range(400, 500);
965 if (status & DP_AUX_CH_CTL_DONE)
970 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
971 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
977 /* Check for timeout or receive error.
978 * Timeouts occur when the sink is not connected
980 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
981 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
986 /* Timeouts occur when the device isn't connected, so they're
987 * "normal" -- don't fill the kernel log with these */
988 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
989 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
994 /* Unload any bytes sent back from the other side */
995 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
996 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
999 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1000 * We have no idea of what happened so we return -EBUSY so
1001 * drm layer takes care for the necessary retries.
1003 if (recv_bytes == 0 || recv_bytes > 20) {
1004 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1007 * FIXME: This patch was created on top of a series that
1008 * organize the retries at drm level. There EBUSY should
1009 * also take care for 1ms wait before retrying.
1010 * That aux retries re-org is still needed and after that is
1011 * merged we remove this sleep from here.
1013 usleep_range(1000, 1500);
1018 if (recv_bytes > recv_size)
1019 recv_bytes = recv_size;
1021 for (i = 0; i < recv_bytes; i += 4)
1022 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1023 recv + i, recv_bytes - i);
1027 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1030 edp_panel_vdd_off(intel_dp, false);
1032 pps_unlock(intel_dp);
1037 #define BARE_ADDRESS_SIZE 3
1038 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1040 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1042 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1043 uint8_t txbuf[20], rxbuf[20];
1044 size_t txsize, rxsize;
1047 txbuf[0] = (msg->request << 4) |
1048 ((msg->address >> 16) & 0xf);
1049 txbuf[1] = (msg->address >> 8) & 0xff;
1050 txbuf[2] = msg->address & 0xff;
1051 txbuf[3] = msg->size - 1;
1053 switch (msg->request & ~DP_AUX_I2C_MOT) {
1054 case DP_AUX_NATIVE_WRITE:
1055 case DP_AUX_I2C_WRITE:
1056 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1057 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1058 rxsize = 2; /* 0 or 1 data bytes */
1060 if (WARN_ON(txsize > 20))
1063 WARN_ON(!msg->buffer != !msg->size);
1066 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1068 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1070 msg->reply = rxbuf[0] >> 4;
1073 /* Number of bytes written in a short write. */
1074 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1076 /* Return payload size. */
1082 case DP_AUX_NATIVE_READ:
1083 case DP_AUX_I2C_READ:
1084 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1085 rxsize = msg->size + 1;
1087 if (WARN_ON(rxsize > 20))
1090 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1092 msg->reply = rxbuf[0] >> 4;
1094 * Assume happy day, and copy the data. The caller is
1095 * expected to check msg->reply before touching it.
1097 * Return payload size.
1100 memcpy(msg->buffer, rxbuf + 1, ret);
1112 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1119 return DP_AUX_CH_CTL(port);
1122 return DP_AUX_CH_CTL(PORT_B);
1126 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1127 enum port port, int index)
1133 return DP_AUX_CH_DATA(port, index);
1136 return DP_AUX_CH_DATA(PORT_B, index);
1140 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1145 return DP_AUX_CH_CTL(port);
1149 return PCH_DP_AUX_CH_CTL(port);
1152 return DP_AUX_CH_CTL(PORT_A);
1156 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1157 enum port port, int index)
1161 return DP_AUX_CH_DATA(port, index);
1165 return PCH_DP_AUX_CH_DATA(port, index);
1168 return DP_AUX_CH_DATA(PORT_A, index);
1173 * On SKL we don't have Aux for port E so we rely
1174 * on VBT to set a proper alternate aux channel.
1176 static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1178 const struct ddi_vbt_port_info *info =
1179 &dev_priv->vbt.ddi_port_info[PORT_E];
1181 switch (info->alternate_aux_channel) {
1191 MISSING_CASE(info->alternate_aux_channel);
1196 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1200 port = skl_porte_aux_port(dev_priv);
1207 return DP_AUX_CH_CTL(port);
1210 return DP_AUX_CH_CTL(PORT_A);
1214 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1215 enum port port, int index)
1218 port = skl_porte_aux_port(dev_priv);
1225 return DP_AUX_CH_DATA(port, index);
1228 return DP_AUX_CH_DATA(PORT_A, index);
1232 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1235 if (INTEL_INFO(dev_priv)->gen >= 9)
1236 return skl_aux_ctl_reg(dev_priv, port);
1237 else if (HAS_PCH_SPLIT(dev_priv))
1238 return ilk_aux_ctl_reg(dev_priv, port);
1240 return g4x_aux_ctl_reg(dev_priv, port);
1243 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1244 enum port port, int index)
1246 if (INTEL_INFO(dev_priv)->gen >= 9)
1247 return skl_aux_data_reg(dev_priv, port, index);
1248 else if (HAS_PCH_SPLIT(dev_priv))
1249 return ilk_aux_data_reg(dev_priv, port, index);
1251 return g4x_aux_data_reg(dev_priv, port, index);
1254 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1256 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1257 enum port port = dp_to_dig_port(intel_dp)->port;
1260 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1261 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1262 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1266 intel_dp_aux_fini(struct intel_dp *intel_dp)
1268 kfree(intel_dp->aux.name);
1272 intel_dp_aux_init(struct intel_dp *intel_dp)
1274 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1275 enum port port = intel_dig_port->port;
1277 intel_aux_reg_init(intel_dp);
1278 drm_dp_aux_init(&intel_dp->aux);
1280 /* Failure to allocate our preferred name is not critical */
1281 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1282 intel_dp->aux.transfer = intel_dp_aux_transfer;
1286 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1288 if (intel_dp->num_sink_rates) {
1289 *sink_rates = intel_dp->sink_rates;
1290 return intel_dp->num_sink_rates;
1293 *sink_rates = default_rates;
1295 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1298 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1300 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1301 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1303 if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1304 IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
1311 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
1313 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1314 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1317 if (IS_BROXTON(dev_priv)) {
1318 *source_rates = bxt_rates;
1319 size = ARRAY_SIZE(bxt_rates);
1320 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1321 *source_rates = skl_rates;
1322 size = ARRAY_SIZE(skl_rates);
1324 *source_rates = default_rates;
1325 size = ARRAY_SIZE(default_rates);
1328 /* This depends on the fact that 5.4 is last value in the array */
1329 if (!intel_dp_source_supports_hbr2(intel_dp))
1336 intel_dp_set_clock(struct intel_encoder *encoder,
1337 struct intel_crtc_state *pipe_config)
1339 struct drm_device *dev = encoder->base.dev;
1340 struct drm_i915_private *dev_priv = to_i915(dev);
1341 const struct dp_link_dpll *divisor = NULL;
1344 if (IS_G4X(dev_priv)) {
1345 divisor = gen4_dpll;
1346 count = ARRAY_SIZE(gen4_dpll);
1347 } else if (HAS_PCH_SPLIT(dev_priv)) {
1349 count = ARRAY_SIZE(pch_dpll);
1350 } else if (IS_CHERRYVIEW(dev_priv)) {
1352 count = ARRAY_SIZE(chv_dpll);
1353 } else if (IS_VALLEYVIEW(dev_priv)) {
1355 count = ARRAY_SIZE(vlv_dpll);
1358 if (divisor && count) {
1359 for (i = 0; i < count; i++) {
1360 if (pipe_config->port_clock == divisor[i].clock) {
1361 pipe_config->dpll = divisor[i].dpll;
1362 pipe_config->clock_set = true;
1369 static int intersect_rates(const int *source_rates, int source_len,
1370 const int *sink_rates, int sink_len,
1373 int i = 0, j = 0, k = 0;
1375 while (i < source_len && j < sink_len) {
1376 if (source_rates[i] == sink_rates[j]) {
1377 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1379 common_rates[k] = source_rates[i];
1383 } else if (source_rates[i] < sink_rates[j]) {
1392 static int intel_dp_common_rates(struct intel_dp *intel_dp,
1395 const int *source_rates, *sink_rates;
1396 int source_len, sink_len;
1398 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1399 source_len = intel_dp_source_rates(intel_dp, &source_rates);
1401 return intersect_rates(source_rates, source_len,
1402 sink_rates, sink_len,
1406 static void snprintf_int_array(char *str, size_t len,
1407 const int *array, int nelem)
1413 for (i = 0; i < nelem; i++) {
1414 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1422 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1424 const int *source_rates, *sink_rates;
1425 int source_len, sink_len, common_len;
1426 int common_rates[DP_MAX_SUPPORTED_RATES];
1427 char str[128]; /* FIXME: too big for stack? */
1429 if ((drm_debug & DRM_UT_KMS) == 0)
1432 source_len = intel_dp_source_rates(intel_dp, &source_rates);
1433 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1434 DRM_DEBUG_KMS("source rates: %s\n", str);
1436 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1437 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1438 DRM_DEBUG_KMS("sink rates: %s\n", str);
1440 common_len = intel_dp_common_rates(intel_dp, common_rates);
1441 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1442 DRM_DEBUG_KMS("common rates: %s\n", str);
1445 static void intel_dp_print_hw_revision(struct intel_dp *intel_dp)
1450 if ((drm_debug & DRM_UT_KMS) == 0)
1453 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1454 DP_DWN_STRM_PORT_PRESENT))
1457 len = drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_HW_REV, &rev, 1);
1461 DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev & 0xf0) >> 4, rev & 0xf);
1464 static void intel_dp_print_sw_revision(struct intel_dp *intel_dp)
1469 if ((drm_debug & DRM_UT_KMS) == 0)
1472 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1473 DP_DWN_STRM_PORT_PRESENT))
1476 len = drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_SW_REV, &rev, 2);
1480 DRM_DEBUG_KMS("sink sw revision: %d.%d\n", rev[0], rev[1]);
1483 static int rate_to_index(int find, const int *rates)
1487 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1488 if (find == rates[i])
1495 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1497 int rates[DP_MAX_SUPPORTED_RATES] = {};
1500 len = intel_dp_common_rates(intel_dp, rates);
1501 if (WARN_ON(len <= 0))
1504 return rates[len - 1];
1507 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1509 return rate_to_index(rate, intel_dp->sink_rates);
1512 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1513 uint8_t *link_bw, uint8_t *rate_select)
1515 if (intel_dp->num_sink_rates) {
1518 intel_dp_rate_select(intel_dp, port_clock);
1520 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1525 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1526 struct intel_crtc_state *pipe_config)
1530 bpp = pipe_config->pipe_bpp;
1531 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1534 bpp = min(bpp, 3*bpc);
1540 intel_dp_compute_config(struct intel_encoder *encoder,
1541 struct intel_crtc_state *pipe_config,
1542 struct drm_connector_state *conn_state)
1544 struct drm_device *dev = encoder->base.dev;
1545 struct drm_i915_private *dev_priv = to_i915(dev);
1546 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1547 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1548 enum port port = dp_to_dig_port(intel_dp)->port;
1549 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1550 struct intel_connector *intel_connector = intel_dp->attached_connector;
1551 int lane_count, clock;
1552 int min_lane_count = 1;
1553 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1554 /* Conveniently, the link BW constants become indices with a shift...*/
1558 int link_avail, link_clock;
1559 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1561 uint8_t link_bw, rate_select;
1563 common_len = intel_dp_common_rates(intel_dp, common_rates);
1565 /* No common link rates between source and sink */
1566 WARN_ON(common_len <= 0);
1568 max_clock = common_len - 1;
1570 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1571 pipe_config->has_pch_encoder = true;
1573 pipe_config->has_drrs = false;
1574 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1576 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1577 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1580 if (INTEL_INFO(dev)->gen >= 9) {
1582 ret = skl_update_scaler_crtc(pipe_config);
1587 if (HAS_GMCH_DISPLAY(dev_priv))
1588 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1589 intel_connector->panel.fitting_mode);
1591 intel_pch_panel_fitting(intel_crtc, pipe_config,
1592 intel_connector->panel.fitting_mode);
1595 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1598 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1599 "max bw %d pixel clock %iKHz\n",
1600 max_lane_count, common_rates[max_clock],
1601 adjusted_mode->crtc_clock);
1603 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1604 * bpc in between. */
1605 bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1606 if (is_edp(intel_dp)) {
1608 /* Get bpp from vbt only for panels that dont have bpp in edid */
1609 if (intel_connector->base.display_info.bpc == 0 &&
1610 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1611 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1612 dev_priv->vbt.edp.bpp);
1613 bpp = dev_priv->vbt.edp.bpp;
1617 * Use the maximum clock and number of lanes the eDP panel
1618 * advertizes being capable of. The panels are generally
1619 * designed to support only a single clock and lane
1620 * configuration, and typically these values correspond to the
1621 * native resolution of the panel.
1623 min_lane_count = max_lane_count;
1624 min_clock = max_clock;
1627 for (; bpp >= 6*3; bpp -= 2*3) {
1628 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1631 for (clock = min_clock; clock <= max_clock; clock++) {
1632 for (lane_count = min_lane_count;
1633 lane_count <= max_lane_count;
1636 link_clock = common_rates[clock];
1637 link_avail = intel_dp_max_data_rate(link_clock,
1640 if (mode_rate <= link_avail) {
1650 if (intel_dp->color_range_auto) {
1653 * CEA-861-E - 5.1 Default Encoding Parameters
1654 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1656 pipe_config->limited_color_range =
1657 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1659 pipe_config->limited_color_range =
1660 intel_dp->limited_color_range;
1663 pipe_config->lane_count = lane_count;
1665 pipe_config->pipe_bpp = bpp;
1666 pipe_config->port_clock = common_rates[clock];
1668 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1669 &link_bw, &rate_select);
1671 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1672 link_bw, rate_select, pipe_config->lane_count,
1673 pipe_config->port_clock, bpp);
1674 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1675 mode_rate, link_avail);
1677 intel_link_compute_m_n(bpp, lane_count,
1678 adjusted_mode->crtc_clock,
1679 pipe_config->port_clock,
1680 &pipe_config->dp_m_n);
1682 if (intel_connector->panel.downclock_mode != NULL &&
1683 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1684 pipe_config->has_drrs = true;
1685 intel_link_compute_m_n(bpp, lane_count,
1686 intel_connector->panel.downclock_mode->clock,
1687 pipe_config->port_clock,
1688 &pipe_config->dp_m2_n2);
1692 * DPLL0 VCO may need to be adjusted to get the correct
1693 * clock for eDP. This will affect cdclk as well.
1695 if (is_edp(intel_dp) &&
1696 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1699 switch (pipe_config->port_clock / 2) {
1709 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1712 if (!HAS_DDI(dev_priv))
1713 intel_dp_set_clock(encoder, pipe_config);
1718 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1719 int link_rate, uint8_t lane_count,
1722 intel_dp->link_rate = link_rate;
1723 intel_dp->lane_count = lane_count;
1724 intel_dp->link_mst = link_mst;
1727 static void intel_dp_prepare(struct intel_encoder *encoder,
1728 struct intel_crtc_state *pipe_config)
1730 struct drm_device *dev = encoder->base.dev;
1731 struct drm_i915_private *dev_priv = to_i915(dev);
1732 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1733 enum port port = dp_to_dig_port(intel_dp)->port;
1734 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1735 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1737 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1738 pipe_config->lane_count,
1739 intel_crtc_has_type(pipe_config,
1740 INTEL_OUTPUT_DP_MST));
1743 * There are four kinds of DP registers:
1750 * IBX PCH and CPU are the same for almost everything,
1751 * except that the CPU DP PLL is configured in this
1754 * CPT PCH is quite different, having many bits moved
1755 * to the TRANS_DP_CTL register instead. That
1756 * configuration happens (oddly) in ironlake_pch_enable
1759 /* Preserve the BIOS-computed detected bit. This is
1760 * supposed to be read-only.
1762 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1764 /* Handle DP bits in common between all three register formats */
1765 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1766 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1768 /* Split out the IBX/CPU vs CPT settings */
1770 if (IS_GEN7(dev_priv) && port == PORT_A) {
1771 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1772 intel_dp->DP |= DP_SYNC_HS_HIGH;
1773 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1774 intel_dp->DP |= DP_SYNC_VS_HIGH;
1775 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1777 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1778 intel_dp->DP |= DP_ENHANCED_FRAMING;
1780 intel_dp->DP |= crtc->pipe << 29;
1781 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1784 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1786 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1787 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1788 trans_dp |= TRANS_DP_ENH_FRAMING;
1790 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1791 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1793 if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
1794 !IS_CHERRYVIEW(dev_priv) &&
1795 pipe_config->limited_color_range)
1796 intel_dp->DP |= DP_COLOR_RANGE_16_235;
1798 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1799 intel_dp->DP |= DP_SYNC_HS_HIGH;
1800 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1801 intel_dp->DP |= DP_SYNC_VS_HIGH;
1802 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1804 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1805 intel_dp->DP |= DP_ENHANCED_FRAMING;
1807 if (IS_CHERRYVIEW(dev_priv))
1808 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1809 else if (crtc->pipe == PIPE_B)
1810 intel_dp->DP |= DP_PIPEB_SELECT;
1814 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1815 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1817 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1818 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1820 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1821 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1823 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1824 struct intel_dp *intel_dp);
1826 static void wait_panel_status(struct intel_dp *intel_dp,
1830 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1831 struct drm_i915_private *dev_priv = to_i915(dev);
1832 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1834 lockdep_assert_held(&dev_priv->pps_mutex);
1836 intel_pps_verify_state(dev_priv, intel_dp);
1838 pp_stat_reg = _pp_stat_reg(intel_dp);
1839 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1841 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1843 I915_READ(pp_stat_reg),
1844 I915_READ(pp_ctrl_reg));
1846 if (intel_wait_for_register(dev_priv,
1847 pp_stat_reg, mask, value,
1849 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1850 I915_READ(pp_stat_reg),
1851 I915_READ(pp_ctrl_reg));
1853 DRM_DEBUG_KMS("Wait complete\n");
1856 static void wait_panel_on(struct intel_dp *intel_dp)
1858 DRM_DEBUG_KMS("Wait for panel power on\n");
1859 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1862 static void wait_panel_off(struct intel_dp *intel_dp)
1864 DRM_DEBUG_KMS("Wait for panel power off time\n");
1865 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1868 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1870 ktime_t panel_power_on_time;
1871 s64 panel_power_off_duration;
1873 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1875 /* take the difference of currrent time and panel power off time
1876 * and then make panel wait for t11_t12 if needed. */
1877 panel_power_on_time = ktime_get_boottime();
1878 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1880 /* When we disable the VDD override bit last we have to do the manual
1882 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1883 wait_remaining_ms_from_jiffies(jiffies,
1884 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1886 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1889 static void wait_backlight_on(struct intel_dp *intel_dp)
1891 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1892 intel_dp->backlight_on_delay);
1895 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1897 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1898 intel_dp->backlight_off_delay);
1901 /* Read the current pp_control value, unlocking the register if it
1905 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1907 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1908 struct drm_i915_private *dev_priv = to_i915(dev);
1911 lockdep_assert_held(&dev_priv->pps_mutex);
1913 control = I915_READ(_pp_ctrl_reg(intel_dp));
1914 if (WARN_ON(!HAS_DDI(dev_priv) &&
1915 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
1916 control &= ~PANEL_UNLOCK_MASK;
1917 control |= PANEL_UNLOCK_REGS;
1923 * Must be paired with edp_panel_vdd_off().
1924 * Must hold pps_mutex around the whole on/off sequence.
1925 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1927 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1929 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1930 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1931 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1932 struct drm_i915_private *dev_priv = to_i915(dev);
1933 enum intel_display_power_domain power_domain;
1935 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1936 bool need_to_disable = !intel_dp->want_panel_vdd;
1938 lockdep_assert_held(&dev_priv->pps_mutex);
1940 if (!is_edp(intel_dp))
1943 cancel_delayed_work(&intel_dp->panel_vdd_work);
1944 intel_dp->want_panel_vdd = true;
1946 if (edp_have_panel_vdd(intel_dp))
1947 return need_to_disable;
1949 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1950 intel_display_power_get(dev_priv, power_domain);
1952 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1953 port_name(intel_dig_port->port));
1955 if (!edp_have_panel_power(intel_dp))
1956 wait_panel_power_cycle(intel_dp);
1958 pp = ironlake_get_pp_control(intel_dp);
1959 pp |= EDP_FORCE_VDD;
1961 pp_stat_reg = _pp_stat_reg(intel_dp);
1962 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1964 I915_WRITE(pp_ctrl_reg, pp);
1965 POSTING_READ(pp_ctrl_reg);
1966 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1967 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1969 * If the panel wasn't on, delay before accessing aux channel
1971 if (!edp_have_panel_power(intel_dp)) {
1972 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1973 port_name(intel_dig_port->port));
1974 msleep(intel_dp->panel_power_up_delay);
1977 return need_to_disable;
1981 * Must be paired with intel_edp_panel_vdd_off() or
1982 * intel_edp_panel_off().
1983 * Nested calls to these functions are not allowed since
1984 * we drop the lock. Caller must use some higher level
1985 * locking to prevent nested calls from other threads.
1987 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1991 if (!is_edp(intel_dp))
1995 vdd = edp_panel_vdd_on(intel_dp);
1996 pps_unlock(intel_dp);
1998 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1999 port_name(dp_to_dig_port(intel_dp)->port));
2002 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2004 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2005 struct drm_i915_private *dev_priv = to_i915(dev);
2006 struct intel_digital_port *intel_dig_port =
2007 dp_to_dig_port(intel_dp);
2008 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2009 enum intel_display_power_domain power_domain;
2011 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2013 lockdep_assert_held(&dev_priv->pps_mutex);
2015 WARN_ON(intel_dp->want_panel_vdd);
2017 if (!edp_have_panel_vdd(intel_dp))
2020 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2021 port_name(intel_dig_port->port));
2023 pp = ironlake_get_pp_control(intel_dp);
2024 pp &= ~EDP_FORCE_VDD;
2026 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2027 pp_stat_reg = _pp_stat_reg(intel_dp);
2029 I915_WRITE(pp_ctrl_reg, pp);
2030 POSTING_READ(pp_ctrl_reg);
2032 /* Make sure sequencer is idle before allowing subsequent activity */
2033 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2034 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2036 if ((pp & PANEL_POWER_ON) == 0)
2037 intel_dp->panel_power_off_time = ktime_get_boottime();
2039 power_domain = intel_display_port_aux_power_domain(intel_encoder);
2040 intel_display_power_put(dev_priv, power_domain);
2043 static void edp_panel_vdd_work(struct work_struct *__work)
2045 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2046 struct intel_dp, panel_vdd_work);
2049 if (!intel_dp->want_panel_vdd)
2050 edp_panel_vdd_off_sync(intel_dp);
2051 pps_unlock(intel_dp);
2054 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2056 unsigned long delay;
2059 * Queue the timer to fire a long time from now (relative to the power
2060 * down delay) to keep the panel power up across a sequence of
2063 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2064 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2068 * Must be paired with edp_panel_vdd_on().
2069 * Must hold pps_mutex around the whole on/off sequence.
2070 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2072 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2074 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2076 lockdep_assert_held(&dev_priv->pps_mutex);
2078 if (!is_edp(intel_dp))
2081 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2082 port_name(dp_to_dig_port(intel_dp)->port));
2084 intel_dp->want_panel_vdd = false;
2087 edp_panel_vdd_off_sync(intel_dp);
2089 edp_panel_vdd_schedule_off(intel_dp);
2092 static void edp_panel_on(struct intel_dp *intel_dp)
2094 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2095 struct drm_i915_private *dev_priv = to_i915(dev);
2097 i915_reg_t pp_ctrl_reg;
2099 lockdep_assert_held(&dev_priv->pps_mutex);
2101 if (!is_edp(intel_dp))
2104 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2105 port_name(dp_to_dig_port(intel_dp)->port));
2107 if (WARN(edp_have_panel_power(intel_dp),
2108 "eDP port %c panel power already on\n",
2109 port_name(dp_to_dig_port(intel_dp)->port)))
2112 wait_panel_power_cycle(intel_dp);
2114 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2115 pp = ironlake_get_pp_control(intel_dp);
2116 if (IS_GEN5(dev_priv)) {
2117 /* ILK workaround: disable reset around power sequence */
2118 pp &= ~PANEL_POWER_RESET;
2119 I915_WRITE(pp_ctrl_reg, pp);
2120 POSTING_READ(pp_ctrl_reg);
2123 pp |= PANEL_POWER_ON;
2124 if (!IS_GEN5(dev_priv))
2125 pp |= PANEL_POWER_RESET;
2127 I915_WRITE(pp_ctrl_reg, pp);
2128 POSTING_READ(pp_ctrl_reg);
2130 wait_panel_on(intel_dp);
2131 intel_dp->last_power_on = jiffies;
2133 if (IS_GEN5(dev_priv)) {
2134 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2135 I915_WRITE(pp_ctrl_reg, pp);
2136 POSTING_READ(pp_ctrl_reg);
2140 void intel_edp_panel_on(struct intel_dp *intel_dp)
2142 if (!is_edp(intel_dp))
2146 edp_panel_on(intel_dp);
2147 pps_unlock(intel_dp);
2151 static void edp_panel_off(struct intel_dp *intel_dp)
2153 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2154 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2155 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2156 struct drm_i915_private *dev_priv = to_i915(dev);
2157 enum intel_display_power_domain power_domain;
2159 i915_reg_t pp_ctrl_reg;
2161 lockdep_assert_held(&dev_priv->pps_mutex);
2163 if (!is_edp(intel_dp))
2166 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2167 port_name(dp_to_dig_port(intel_dp)->port));
2169 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2170 port_name(dp_to_dig_port(intel_dp)->port));
2172 pp = ironlake_get_pp_control(intel_dp);
2173 /* We need to switch off panel power _and_ force vdd, for otherwise some
2174 * panels get very unhappy and cease to work. */
2175 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2178 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2180 intel_dp->want_panel_vdd = false;
2182 I915_WRITE(pp_ctrl_reg, pp);
2183 POSTING_READ(pp_ctrl_reg);
2185 intel_dp->panel_power_off_time = ktime_get_boottime();
2186 wait_panel_off(intel_dp);
2188 /* We got a reference when we enabled the VDD. */
2189 power_domain = intel_display_port_aux_power_domain(intel_encoder);
2190 intel_display_power_put(dev_priv, power_domain);
2193 void intel_edp_panel_off(struct intel_dp *intel_dp)
2195 if (!is_edp(intel_dp))
2199 edp_panel_off(intel_dp);
2200 pps_unlock(intel_dp);
2203 /* Enable backlight in the panel power control. */
2204 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2206 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2207 struct drm_device *dev = intel_dig_port->base.base.dev;
2208 struct drm_i915_private *dev_priv = to_i915(dev);
2210 i915_reg_t pp_ctrl_reg;
2213 * If we enable the backlight right away following a panel power
2214 * on, we may see slight flicker as the panel syncs with the eDP
2215 * link. So delay a bit to make sure the image is solid before
2216 * allowing it to appear.
2218 wait_backlight_on(intel_dp);
2222 pp = ironlake_get_pp_control(intel_dp);
2223 pp |= EDP_BLC_ENABLE;
2225 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2227 I915_WRITE(pp_ctrl_reg, pp);
2228 POSTING_READ(pp_ctrl_reg);
2230 pps_unlock(intel_dp);
2233 /* Enable backlight PWM and backlight PP control. */
2234 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2236 if (!is_edp(intel_dp))
2239 DRM_DEBUG_KMS("\n");
2241 intel_panel_enable_backlight(intel_dp->attached_connector);
2242 _intel_edp_backlight_on(intel_dp);
2245 /* Disable backlight in the panel power control. */
2246 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2248 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2249 struct drm_i915_private *dev_priv = to_i915(dev);
2251 i915_reg_t pp_ctrl_reg;
2253 if (!is_edp(intel_dp))
2258 pp = ironlake_get_pp_control(intel_dp);
2259 pp &= ~EDP_BLC_ENABLE;
2261 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2263 I915_WRITE(pp_ctrl_reg, pp);
2264 POSTING_READ(pp_ctrl_reg);
2266 pps_unlock(intel_dp);
2268 intel_dp->last_backlight_off = jiffies;
2269 edp_wait_backlight_off(intel_dp);
2272 /* Disable backlight PP control and backlight PWM. */
2273 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2275 if (!is_edp(intel_dp))
2278 DRM_DEBUG_KMS("\n");
2280 _intel_edp_backlight_off(intel_dp);
2281 intel_panel_disable_backlight(intel_dp->attached_connector);
2285 * Hook for controlling the panel power control backlight through the bl_power
2286 * sysfs attribute. Take care to handle multiple calls.
2288 static void intel_edp_backlight_power(struct intel_connector *connector,
2291 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2295 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2296 pps_unlock(intel_dp);
2298 if (is_enabled == enable)
2301 DRM_DEBUG_KMS("panel power control backlight %s\n",
2302 enable ? "enable" : "disable");
2305 _intel_edp_backlight_on(intel_dp);
2307 _intel_edp_backlight_off(intel_dp);
2310 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2312 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2313 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2314 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2316 I915_STATE_WARN(cur_state != state,
2317 "DP port %c state assertion failure (expected %s, current %s)\n",
2318 port_name(dig_port->port),
2319 onoff(state), onoff(cur_state));
2321 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2323 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2325 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2327 I915_STATE_WARN(cur_state != state,
2328 "eDP PLL state assertion failure (expected %s, current %s)\n",
2329 onoff(state), onoff(cur_state));
2331 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2332 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2334 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2335 struct intel_crtc_state *pipe_config)
2337 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2338 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2340 assert_pipe_disabled(dev_priv, crtc->pipe);
2341 assert_dp_port_disabled(intel_dp);
2342 assert_edp_pll_disabled(dev_priv);
2344 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2345 pipe_config->port_clock);
2347 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2349 if (pipe_config->port_clock == 162000)
2350 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2352 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2354 I915_WRITE(DP_A, intel_dp->DP);
2359 * [DevILK] Work around required when enabling DP PLL
2360 * while a pipe is enabled going to FDI:
2361 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2362 * 2. Program DP PLL enable
2364 if (IS_GEN5(dev_priv))
2365 intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe);
2367 intel_dp->DP |= DP_PLL_ENABLE;
2369 I915_WRITE(DP_A, intel_dp->DP);
2374 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2377 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2378 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2380 assert_pipe_disabled(dev_priv, crtc->pipe);
2381 assert_dp_port_disabled(intel_dp);
2382 assert_edp_pll_enabled(dev_priv);
2384 DRM_DEBUG_KMS("disabling eDP PLL\n");
2386 intel_dp->DP &= ~DP_PLL_ENABLE;
2388 I915_WRITE(DP_A, intel_dp->DP);
2393 /* If the sink supports it, try to set the power state appropriately */
2394 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2398 /* Should have a valid DPCD by this point */
2399 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2402 if (mode != DRM_MODE_DPMS_ON) {
2403 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2407 * When turning on, we need to retry for 1ms to give the sink
2410 for (i = 0; i < 3; i++) {
2411 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2420 DRM_DEBUG_KMS("failed to %s sink power state\n",
2421 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2424 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2427 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2428 enum port port = dp_to_dig_port(intel_dp)->port;
2429 struct drm_device *dev = encoder->base.dev;
2430 struct drm_i915_private *dev_priv = to_i915(dev);
2431 enum intel_display_power_domain power_domain;
2435 power_domain = intel_display_port_power_domain(encoder);
2436 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2441 tmp = I915_READ(intel_dp->output_reg);
2443 if (!(tmp & DP_PORT_EN))
2446 if (IS_GEN7(dev_priv) && port == PORT_A) {
2447 *pipe = PORT_TO_PIPE_CPT(tmp);
2448 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2451 for_each_pipe(dev_priv, p) {
2452 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2453 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2461 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2462 i915_mmio_reg_offset(intel_dp->output_reg));
2463 } else if (IS_CHERRYVIEW(dev_priv)) {
2464 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2466 *pipe = PORT_TO_PIPE(tmp);
2472 intel_display_power_put(dev_priv, power_domain);
2477 static void intel_dp_get_config(struct intel_encoder *encoder,
2478 struct intel_crtc_state *pipe_config)
2480 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2482 struct drm_device *dev = encoder->base.dev;
2483 struct drm_i915_private *dev_priv = to_i915(dev);
2484 enum port port = dp_to_dig_port(intel_dp)->port;
2485 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2487 tmp = I915_READ(intel_dp->output_reg);
2489 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2491 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2492 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2494 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2495 flags |= DRM_MODE_FLAG_PHSYNC;
2497 flags |= DRM_MODE_FLAG_NHSYNC;
2499 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2500 flags |= DRM_MODE_FLAG_PVSYNC;
2502 flags |= DRM_MODE_FLAG_NVSYNC;
2504 if (tmp & DP_SYNC_HS_HIGH)
2505 flags |= DRM_MODE_FLAG_PHSYNC;
2507 flags |= DRM_MODE_FLAG_NHSYNC;
2509 if (tmp & DP_SYNC_VS_HIGH)
2510 flags |= DRM_MODE_FLAG_PVSYNC;
2512 flags |= DRM_MODE_FLAG_NVSYNC;
2515 pipe_config->base.adjusted_mode.flags |= flags;
2517 if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
2518 !IS_CHERRYVIEW(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2519 pipe_config->limited_color_range = true;
2521 pipe_config->lane_count =
2522 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2524 intel_dp_get_m_n(crtc, pipe_config);
2526 if (port == PORT_A) {
2527 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2528 pipe_config->port_clock = 162000;
2530 pipe_config->port_clock = 270000;
2533 pipe_config->base.adjusted_mode.crtc_clock =
2534 intel_dotclock_calculate(pipe_config->port_clock,
2535 &pipe_config->dp_m_n);
2537 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2538 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2540 * This is a big fat ugly hack.
2542 * Some machines in UEFI boot mode provide us a VBT that has 18
2543 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2544 * unknown we fail to light up. Yet the same BIOS boots up with
2545 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2546 * max, not what it tells us to use.
2548 * Note: This will still be broken if the eDP panel is not lit
2549 * up by the BIOS, and thus we can't get the mode at module
2552 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2553 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2554 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2558 static void intel_disable_dp(struct intel_encoder *encoder,
2559 struct intel_crtc_state *old_crtc_state,
2560 struct drm_connector_state *old_conn_state)
2562 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2563 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2565 if (old_crtc_state->has_audio)
2566 intel_audio_codec_disable(encoder);
2568 if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2569 intel_psr_disable(intel_dp);
2571 /* Make sure the panel is off before trying to change the mode. But also
2572 * ensure that we have vdd while we switch off the panel. */
2573 intel_edp_panel_vdd_on(intel_dp);
2574 intel_edp_backlight_off(intel_dp);
2575 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2576 intel_edp_panel_off(intel_dp);
2578 /* disable the port before the pipe on g4x */
2579 if (INTEL_GEN(dev_priv) < 5)
2580 intel_dp_link_down(intel_dp);
2583 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2584 struct intel_crtc_state *old_crtc_state,
2585 struct drm_connector_state *old_conn_state)
2587 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2588 enum port port = dp_to_dig_port(intel_dp)->port;
2590 intel_dp_link_down(intel_dp);
2592 /* Only ilk+ has port A */
2594 ironlake_edp_pll_off(intel_dp);
2597 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2598 struct intel_crtc_state *old_crtc_state,
2599 struct drm_connector_state *old_conn_state)
2601 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2603 intel_dp_link_down(intel_dp);
2606 static void chv_post_disable_dp(struct intel_encoder *encoder,
2607 struct intel_crtc_state *old_crtc_state,
2608 struct drm_connector_state *old_conn_state)
2610 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2611 struct drm_device *dev = encoder->base.dev;
2612 struct drm_i915_private *dev_priv = to_i915(dev);
2614 intel_dp_link_down(intel_dp);
2616 mutex_lock(&dev_priv->sb_lock);
2618 /* Assert data lane reset */
2619 chv_data_lane_soft_reset(encoder, true);
2621 mutex_unlock(&dev_priv->sb_lock);
2625 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2627 uint8_t dp_train_pat)
2629 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2630 struct drm_device *dev = intel_dig_port->base.base.dev;
2631 struct drm_i915_private *dev_priv = to_i915(dev);
2632 enum port port = intel_dig_port->port;
2634 if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2635 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2636 dp_train_pat & DP_TRAINING_PATTERN_MASK);
2638 if (HAS_DDI(dev_priv)) {
2639 uint32_t temp = I915_READ(DP_TP_CTL(port));
2641 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2642 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2644 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2646 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2647 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2648 case DP_TRAINING_PATTERN_DISABLE:
2649 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2652 case DP_TRAINING_PATTERN_1:
2653 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2655 case DP_TRAINING_PATTERN_2:
2656 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2658 case DP_TRAINING_PATTERN_3:
2659 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2662 I915_WRITE(DP_TP_CTL(port), temp);
2664 } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2665 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2666 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2668 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2669 case DP_TRAINING_PATTERN_DISABLE:
2670 *DP |= DP_LINK_TRAIN_OFF_CPT;
2672 case DP_TRAINING_PATTERN_1:
2673 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2675 case DP_TRAINING_PATTERN_2:
2676 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2678 case DP_TRAINING_PATTERN_3:
2679 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2680 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2685 if (IS_CHERRYVIEW(dev_priv))
2686 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2688 *DP &= ~DP_LINK_TRAIN_MASK;
2690 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2691 case DP_TRAINING_PATTERN_DISABLE:
2692 *DP |= DP_LINK_TRAIN_OFF;
2694 case DP_TRAINING_PATTERN_1:
2695 *DP |= DP_LINK_TRAIN_PAT_1;
2697 case DP_TRAINING_PATTERN_2:
2698 *DP |= DP_LINK_TRAIN_PAT_2;
2700 case DP_TRAINING_PATTERN_3:
2701 if (IS_CHERRYVIEW(dev_priv)) {
2702 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2704 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2705 *DP |= DP_LINK_TRAIN_PAT_2;
2712 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2713 struct intel_crtc_state *old_crtc_state)
2715 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2716 struct drm_i915_private *dev_priv = to_i915(dev);
2718 /* enable with pattern 1 (as per spec) */
2720 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2723 * Magic for VLV/CHV. We _must_ first set up the register
2724 * without actually enabling the port, and then do another
2725 * write to enable the port. Otherwise link training will
2726 * fail when the power sequencer is freshly used for this port.
2728 intel_dp->DP |= DP_PORT_EN;
2729 if (old_crtc_state->has_audio)
2730 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2732 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2733 POSTING_READ(intel_dp->output_reg);
2736 static void intel_enable_dp(struct intel_encoder *encoder,
2737 struct intel_crtc_state *pipe_config)
2739 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2740 struct drm_device *dev = encoder->base.dev;
2741 struct drm_i915_private *dev_priv = to_i915(dev);
2742 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2743 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2744 enum pipe pipe = crtc->pipe;
2746 if (WARN_ON(dp_reg & DP_PORT_EN))
2751 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2752 vlv_init_panel_power_sequencer(intel_dp);
2754 intel_dp_enable_port(intel_dp, pipe_config);
2756 edp_panel_vdd_on(intel_dp);
2757 edp_panel_on(intel_dp);
2758 edp_panel_vdd_off(intel_dp, true);
2760 pps_unlock(intel_dp);
2762 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2763 unsigned int lane_mask = 0x0;
2765 if (IS_CHERRYVIEW(dev_priv))
2766 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2768 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2772 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2773 intel_dp_start_link_train(intel_dp);
2774 intel_dp_stop_link_train(intel_dp);
2776 if (pipe_config->has_audio) {
2777 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2779 intel_audio_codec_enable(encoder);
2783 static void g4x_enable_dp(struct intel_encoder *encoder,
2784 struct intel_crtc_state *pipe_config,
2785 struct drm_connector_state *conn_state)
2787 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2789 intel_enable_dp(encoder, pipe_config);
2790 intel_edp_backlight_on(intel_dp);
2793 static void vlv_enable_dp(struct intel_encoder *encoder,
2794 struct intel_crtc_state *pipe_config,
2795 struct drm_connector_state *conn_state)
2797 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2799 intel_edp_backlight_on(intel_dp);
2800 intel_psr_enable(intel_dp);
2803 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2804 struct intel_crtc_state *pipe_config,
2805 struct drm_connector_state *conn_state)
2807 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2808 enum port port = dp_to_dig_port(intel_dp)->port;
2810 intel_dp_prepare(encoder, pipe_config);
2812 /* Only ilk+ has port A */
2814 ironlake_edp_pll_on(intel_dp, pipe_config);
2817 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2819 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2820 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2821 enum pipe pipe = intel_dp->pps_pipe;
2822 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2824 edp_panel_vdd_off_sync(intel_dp);
2827 * VLV seems to get confused when multiple power seqeuencers
2828 * have the same port selected (even if only one has power/vdd
2829 * enabled). The failure manifests as vlv_wait_port_ready() failing
2830 * CHV on the other hand doesn't seem to mind having the same port
2831 * selected in multiple power seqeuencers, but let's clear the
2832 * port select always when logically disconnecting a power sequencer
2835 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2836 pipe_name(pipe), port_name(intel_dig_port->port));
2837 I915_WRITE(pp_on_reg, 0);
2838 POSTING_READ(pp_on_reg);
2840 intel_dp->pps_pipe = INVALID_PIPE;
2843 static void vlv_steal_power_sequencer(struct drm_device *dev,
2846 struct drm_i915_private *dev_priv = to_i915(dev);
2847 struct intel_encoder *encoder;
2849 lockdep_assert_held(&dev_priv->pps_mutex);
2851 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2854 for_each_intel_encoder(dev, encoder) {
2855 struct intel_dp *intel_dp;
2858 if (encoder->type != INTEL_OUTPUT_EDP)
2861 intel_dp = enc_to_intel_dp(&encoder->base);
2862 port = dp_to_dig_port(intel_dp)->port;
2864 if (intel_dp->pps_pipe != pipe)
2867 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2868 pipe_name(pipe), port_name(port));
2870 WARN(encoder->base.crtc,
2871 "stealing pipe %c power sequencer from active eDP port %c\n",
2872 pipe_name(pipe), port_name(port));
2874 /* make sure vdd is off before we steal it */
2875 vlv_detach_power_sequencer(intel_dp);
2879 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2881 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2882 struct intel_encoder *encoder = &intel_dig_port->base;
2883 struct drm_device *dev = encoder->base.dev;
2884 struct drm_i915_private *dev_priv = to_i915(dev);
2885 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2887 lockdep_assert_held(&dev_priv->pps_mutex);
2889 if (!is_edp(intel_dp))
2892 if (intel_dp->pps_pipe == crtc->pipe)
2896 * If another power sequencer was being used on this
2897 * port previously make sure to turn off vdd there while
2898 * we still have control of it.
2900 if (intel_dp->pps_pipe != INVALID_PIPE)
2901 vlv_detach_power_sequencer(intel_dp);
2904 * We may be stealing the power
2905 * sequencer from another port.
2907 vlv_steal_power_sequencer(dev, crtc->pipe);
2909 /* now it's all ours */
2910 intel_dp->pps_pipe = crtc->pipe;
2912 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2913 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2915 /* init power sequencer on this pipe and port */
2916 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2917 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2920 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
2921 struct intel_crtc_state *pipe_config,
2922 struct drm_connector_state *conn_state)
2924 vlv_phy_pre_encoder_enable(encoder);
2926 intel_enable_dp(encoder, pipe_config);
2929 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
2930 struct intel_crtc_state *pipe_config,
2931 struct drm_connector_state *conn_state)
2933 intel_dp_prepare(encoder, pipe_config);
2935 vlv_phy_pre_pll_enable(encoder);
2938 static void chv_pre_enable_dp(struct intel_encoder *encoder,
2939 struct intel_crtc_state *pipe_config,
2940 struct drm_connector_state *conn_state)
2942 chv_phy_pre_encoder_enable(encoder);
2944 intel_enable_dp(encoder, pipe_config);
2946 /* Second common lane will stay alive on its own now */
2947 chv_phy_release_cl2_override(encoder);
2950 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
2951 struct intel_crtc_state *pipe_config,
2952 struct drm_connector_state *conn_state)
2954 intel_dp_prepare(encoder, pipe_config);
2956 chv_phy_pre_pll_enable(encoder);
2959 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
2960 struct intel_crtc_state *pipe_config,
2961 struct drm_connector_state *conn_state)
2963 chv_phy_post_pll_disable(encoder);
2967 * Fetch AUX CH registers 0x202 - 0x207 which contain
2968 * link status information
2971 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2973 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2974 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2977 /* These are source-specific values. */
2979 intel_dp_voltage_max(struct intel_dp *intel_dp)
2981 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2982 struct drm_i915_private *dev_priv = to_i915(dev);
2983 enum port port = dp_to_dig_port(intel_dp)->port;
2985 if (IS_BROXTON(dev_priv))
2986 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2987 else if (INTEL_INFO(dev)->gen >= 9) {
2988 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
2989 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2990 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2991 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2992 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2993 else if (IS_GEN7(dev_priv) && port == PORT_A)
2994 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2995 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2996 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2998 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3002 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3004 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3005 enum port port = dp_to_dig_port(intel_dp)->port;
3007 if (INTEL_GEN(dev_priv) >= 9) {
3008 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3009 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3010 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3011 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3012 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3014 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3015 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3016 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3018 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3020 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3021 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3023 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3024 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3025 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3026 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3027 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3028 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3030 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3032 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3033 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3034 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3035 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3036 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3037 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3038 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3039 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3040 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3042 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3044 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3045 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3047 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3048 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3049 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3050 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3052 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3055 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3056 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3057 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3058 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3059 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3060 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3061 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3062 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3064 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3069 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3071 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3072 unsigned long demph_reg_value, preemph_reg_value,
3073 uniqtranscale_reg_value;
3074 uint8_t train_set = intel_dp->train_set[0];
3076 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3077 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3078 preemph_reg_value = 0x0004000;
3079 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3080 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3081 demph_reg_value = 0x2B405555;
3082 uniqtranscale_reg_value = 0x552AB83A;
3084 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3085 demph_reg_value = 0x2B404040;
3086 uniqtranscale_reg_value = 0x5548B83A;
3088 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3089 demph_reg_value = 0x2B245555;
3090 uniqtranscale_reg_value = 0x5560B83A;
3092 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3093 demph_reg_value = 0x2B405555;
3094 uniqtranscale_reg_value = 0x5598DA3A;
3100 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3101 preemph_reg_value = 0x0002000;
3102 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3103 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3104 demph_reg_value = 0x2B404040;
3105 uniqtranscale_reg_value = 0x5552B83A;
3107 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3108 demph_reg_value = 0x2B404848;
3109 uniqtranscale_reg_value = 0x5580B83A;
3111 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3112 demph_reg_value = 0x2B404040;
3113 uniqtranscale_reg_value = 0x55ADDA3A;
3119 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3120 preemph_reg_value = 0x0000000;
3121 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3122 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3123 demph_reg_value = 0x2B305555;
3124 uniqtranscale_reg_value = 0x5570B83A;
3126 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3127 demph_reg_value = 0x2B2B4040;
3128 uniqtranscale_reg_value = 0x55ADDA3A;
3134 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3135 preemph_reg_value = 0x0006000;
3136 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3137 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3138 demph_reg_value = 0x1B405555;
3139 uniqtranscale_reg_value = 0x55ADDA3A;
3149 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3150 uniqtranscale_reg_value, 0);
3155 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3157 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3158 u32 deemph_reg_value, margin_reg_value;
3159 bool uniq_trans_scale = false;
3160 uint8_t train_set = intel_dp->train_set[0];
3162 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3163 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3164 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3165 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3166 deemph_reg_value = 128;
3167 margin_reg_value = 52;
3169 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3170 deemph_reg_value = 128;
3171 margin_reg_value = 77;
3173 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3174 deemph_reg_value = 128;
3175 margin_reg_value = 102;
3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3178 deemph_reg_value = 128;
3179 margin_reg_value = 154;
3180 uniq_trans_scale = true;
3186 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3187 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3188 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3189 deemph_reg_value = 85;
3190 margin_reg_value = 78;
3192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3193 deemph_reg_value = 85;
3194 margin_reg_value = 116;
3196 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3197 deemph_reg_value = 85;
3198 margin_reg_value = 154;
3204 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3205 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3207 deemph_reg_value = 64;
3208 margin_reg_value = 104;
3210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3211 deemph_reg_value = 64;
3212 margin_reg_value = 154;
3218 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3219 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3220 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3221 deemph_reg_value = 43;
3222 margin_reg_value = 154;
3232 chv_set_phy_signal_level(encoder, deemph_reg_value,
3233 margin_reg_value, uniq_trans_scale);
3239 gen4_signal_levels(uint8_t train_set)
3241 uint32_t signal_levels = 0;
3243 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3244 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3246 signal_levels |= DP_VOLTAGE_0_4;
3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3249 signal_levels |= DP_VOLTAGE_0_6;
3251 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3252 signal_levels |= DP_VOLTAGE_0_8;
3254 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3255 signal_levels |= DP_VOLTAGE_1_2;
3258 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3259 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3261 signal_levels |= DP_PRE_EMPHASIS_0;
3263 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3264 signal_levels |= DP_PRE_EMPHASIS_3_5;
3266 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3267 signal_levels |= DP_PRE_EMPHASIS_6;
3269 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3270 signal_levels |= DP_PRE_EMPHASIS_9_5;
3273 return signal_levels;
3276 /* Gen6's DP voltage swing and pre-emphasis control */
3278 gen6_edp_signal_levels(uint8_t train_set)
3280 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3281 DP_TRAIN_PRE_EMPHASIS_MASK);
3282 switch (signal_levels) {
3283 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3284 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3285 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3287 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3288 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3290 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3291 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3292 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3293 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3294 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3295 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3296 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3298 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3299 "0x%x\n", signal_levels);
3300 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3304 /* Gen7's DP voltage swing and pre-emphasis control */
3306 gen7_edp_signal_levels(uint8_t train_set)
3308 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3309 DP_TRAIN_PRE_EMPHASIS_MASK);
3310 switch (signal_levels) {
3311 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3312 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3314 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3315 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3316 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3318 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3319 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3321 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3323 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3324 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3326 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3329 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3330 "0x%x\n", signal_levels);
3331 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3336 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3338 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3339 enum port port = intel_dig_port->port;
3340 struct drm_device *dev = intel_dig_port->base.base.dev;
3341 struct drm_i915_private *dev_priv = to_i915(dev);
3342 uint32_t signal_levels, mask = 0;
3343 uint8_t train_set = intel_dp->train_set[0];
3345 if (HAS_DDI(dev_priv)) {
3346 signal_levels = ddi_signal_levels(intel_dp);
3348 if (IS_BROXTON(dev_priv))
3351 mask = DDI_BUF_EMP_MASK;
3352 } else if (IS_CHERRYVIEW(dev_priv)) {
3353 signal_levels = chv_signal_levels(intel_dp);
3354 } else if (IS_VALLEYVIEW(dev_priv)) {
3355 signal_levels = vlv_signal_levels(intel_dp);
3356 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3357 signal_levels = gen7_edp_signal_levels(train_set);
3358 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3359 } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3360 signal_levels = gen6_edp_signal_levels(train_set);
3361 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3363 signal_levels = gen4_signal_levels(train_set);
3364 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3368 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3370 DRM_DEBUG_KMS("Using vswing level %d\n",
3371 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3372 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3373 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3374 DP_TRAIN_PRE_EMPHASIS_SHIFT);
3376 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3378 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3379 POSTING_READ(intel_dp->output_reg);
3383 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3384 uint8_t dp_train_pat)
3386 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3387 struct drm_i915_private *dev_priv =
3388 to_i915(intel_dig_port->base.base.dev);
3390 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3392 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3393 POSTING_READ(intel_dp->output_reg);
3396 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3399 struct drm_device *dev = intel_dig_port->base.base.dev;
3400 struct drm_i915_private *dev_priv = to_i915(dev);
3401 enum port port = intel_dig_port->port;
3404 if (!HAS_DDI(dev_priv))
3407 val = I915_READ(DP_TP_CTL(port));
3408 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3409 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3410 I915_WRITE(DP_TP_CTL(port), val);
3413 * On PORT_A we can have only eDP in SST mode. There the only reason
3414 * we need to set idle transmission mode is to work around a HW issue
3415 * where we enable the pipe while not in idle link-training mode.
3416 * In this case there is requirement to wait for a minimum number of
3417 * idle patterns to be sent.
3422 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3423 DP_TP_STATUS_IDLE_DONE,
3424 DP_TP_STATUS_IDLE_DONE,
3426 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3430 intel_dp_link_down(struct intel_dp *intel_dp)
3432 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3433 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3434 enum port port = intel_dig_port->port;
3435 struct drm_device *dev = intel_dig_port->base.base.dev;
3436 struct drm_i915_private *dev_priv = to_i915(dev);
3437 uint32_t DP = intel_dp->DP;
3439 if (WARN_ON(HAS_DDI(dev_priv)))
3442 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3445 DRM_DEBUG_KMS("\n");
3447 if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3448 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3449 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3450 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3452 if (IS_CHERRYVIEW(dev_priv))
3453 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3455 DP &= ~DP_LINK_TRAIN_MASK;
3456 DP |= DP_LINK_TRAIN_PAT_IDLE;
3458 I915_WRITE(intel_dp->output_reg, DP);
3459 POSTING_READ(intel_dp->output_reg);
3461 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3462 I915_WRITE(intel_dp->output_reg, DP);
3463 POSTING_READ(intel_dp->output_reg);
3466 * HW workaround for IBX, we need to move the port
3467 * to transcoder A after disabling it to allow the
3468 * matching HDMI port to be enabled on transcoder A.
3470 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3472 * We get CPU/PCH FIFO underruns on the other pipe when
3473 * doing the workaround. Sweep them under the rug.
3475 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3476 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3478 /* always enable with pattern 1 (as per spec) */
3479 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3480 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3481 I915_WRITE(intel_dp->output_reg, DP);
3482 POSTING_READ(intel_dp->output_reg);
3485 I915_WRITE(intel_dp->output_reg, DP);
3486 POSTING_READ(intel_dp->output_reg);
3488 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
3489 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3490 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3493 msleep(intel_dp->panel_power_down_delay);
3499 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3501 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3502 sizeof(intel_dp->dpcd)) < 0)
3503 return false; /* aux transfer failed */
3505 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3507 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3511 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3513 struct drm_i915_private *dev_priv =
3514 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3516 /* this function is meant to be called only once */
3517 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3519 if (!intel_dp_read_dpcd(intel_dp))
3522 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3523 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3524 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3526 /* Check if the panel supports PSR */
3527 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3529 sizeof(intel_dp->psr_dpcd));
3530 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3531 dev_priv->psr.sink_support = true;
3532 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3535 if (INTEL_GEN(dev_priv) >= 9 &&
3536 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3537 uint8_t frame_sync_cap;
3539 dev_priv->psr.sink_support = true;
3540 drm_dp_dpcd_read(&intel_dp->aux,
3541 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3542 &frame_sync_cap, 1);
3543 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3544 /* PSR2 needs frame sync as well */
3545 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3546 DRM_DEBUG_KMS("PSR2 %s on sink",
3547 dev_priv->psr.psr2_support ? "supported" : "not supported");
3550 /* Read the eDP Display control capabilities registers */
3551 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3552 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3553 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3554 sizeof(intel_dp->edp_dpcd))
3555 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3556 intel_dp->edp_dpcd);
3558 /* Intermediate frequency support */
3559 if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3560 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3563 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3564 sink_rates, sizeof(sink_rates));
3566 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3567 int val = le16_to_cpu(sink_rates[i]);
3572 /* Value read is in kHz while drm clock is saved in deca-kHz */
3573 intel_dp->sink_rates[i] = (val * 200) / 10;
3575 intel_dp->num_sink_rates = i;
3583 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3585 if (!intel_dp_read_dpcd(intel_dp))
3588 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3589 &intel_dp->sink_count, 1) < 0)
3593 * Sink count can change between short pulse hpd hence
3594 * a member variable in intel_dp will track any changes
3595 * between short pulse interrupts.
3597 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3600 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3601 * a dongle is present but no display. Unless we require to know
3602 * if a dongle is present or not, we don't need to update
3603 * downstream port information. So, an early return here saves
3604 * time from performing other operations which are not required.
3606 if (!is_edp(intel_dp) && !intel_dp->sink_count)
3609 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3610 DP_DWN_STRM_PORT_PRESENT))
3611 return true; /* native DP sink */
3613 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3614 return true; /* no per-port downstream info */
3616 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3617 intel_dp->downstream_ports,
3618 DP_MAX_DOWNSTREAM_PORTS) < 0)
3619 return false; /* downstream port status fetch failed */
3625 intel_dp_probe_oui(struct intel_dp *intel_dp)
3629 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3632 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3633 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3634 buf[0], buf[1], buf[2]);
3636 if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3637 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3638 buf[0], buf[1], buf[2]);
3642 intel_dp_can_mst(struct intel_dp *intel_dp)
3646 if (!i915.enable_dp_mst)
3649 if (!intel_dp->can_mst)
3652 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3655 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3658 return buf[0] & DP_MST_CAP;
3662 intel_dp_configure_mst(struct intel_dp *intel_dp)
3664 if (!i915.enable_dp_mst)
3667 if (!intel_dp->can_mst)
3670 intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3672 if (intel_dp->is_mst)
3673 DRM_DEBUG_KMS("Sink is MST capable\n");
3675 DRM_DEBUG_KMS("Sink is not MST capable\n");
3677 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3681 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3683 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3684 struct drm_device *dev = dig_port->base.base.dev;
3685 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3691 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3692 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3697 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3698 buf & ~DP_TEST_SINK_START) < 0) {
3699 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3705 intel_wait_for_vblank(dev, intel_crtc->pipe);
3707 if (drm_dp_dpcd_readb(&intel_dp->aux,
3708 DP_TEST_SINK_MISC, &buf) < 0) {
3712 count = buf & DP_TEST_COUNT_MASK;
3713 } while (--attempts && count);
3715 if (attempts == 0) {
3716 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3721 hsw_enable_ips(intel_crtc);
3725 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3727 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3728 struct drm_device *dev = dig_port->base.base.dev;
3729 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3733 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3736 if (!(buf & DP_TEST_CRC_SUPPORTED))
3739 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3742 if (buf & DP_TEST_SINK_START) {
3743 ret = intel_dp_sink_crc_stop(intel_dp);
3748 hsw_disable_ips(intel_crtc);
3750 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3751 buf | DP_TEST_SINK_START) < 0) {
3752 hsw_enable_ips(intel_crtc);
3756 intel_wait_for_vblank(dev, intel_crtc->pipe);
3760 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3762 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3763 struct drm_device *dev = dig_port->base.base.dev;
3764 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3769 ret = intel_dp_sink_crc_start(intel_dp);
3774 intel_wait_for_vblank(dev, intel_crtc->pipe);
3776 if (drm_dp_dpcd_readb(&intel_dp->aux,
3777 DP_TEST_SINK_MISC, &buf) < 0) {
3781 count = buf & DP_TEST_COUNT_MASK;
3783 } while (--attempts && count == 0);
3785 if (attempts == 0) {
3786 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3791 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3797 intel_dp_sink_crc_stop(intel_dp);
3802 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3804 return drm_dp_dpcd_read(&intel_dp->aux,
3805 DP_DEVICE_SERVICE_IRQ_VECTOR,
3806 sink_irq_vector, 1) == 1;
3810 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3814 ret = drm_dp_dpcd_read(&intel_dp->aux,
3816 sink_irq_vector, 14);
3823 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3825 uint8_t test_result = DP_TEST_ACK;
3829 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3831 uint8_t test_result = DP_TEST_NAK;
3835 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
3837 uint8_t test_result = DP_TEST_NAK;
3838 struct intel_connector *intel_connector = intel_dp->attached_connector;
3839 struct drm_connector *connector = &intel_connector->base;
3841 if (intel_connector->detect_edid == NULL ||
3842 connector->edid_corrupt ||
3843 intel_dp->aux.i2c_defer_count > 6) {
3844 /* Check EDID read for NACKs, DEFERs and corruption
3845 * (DP CTS 1.2 Core r1.1)
3846 * 4.2.2.4 : Failed EDID read, I2C_NAK
3847 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3848 * 4.2.2.6 : EDID corruption detected
3849 * Use failsafe mode for all cases
3851 if (intel_dp->aux.i2c_nack_count > 0 ||
3852 intel_dp->aux.i2c_defer_count > 0)
3853 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3854 intel_dp->aux.i2c_nack_count,
3855 intel_dp->aux.i2c_defer_count);
3856 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3858 struct edid *block = intel_connector->detect_edid;
3860 /* We have to write the checksum
3861 * of the last block read
3863 block += intel_connector->detect_edid->extensions;
3865 if (!drm_dp_dpcd_write(&intel_dp->aux,
3866 DP_TEST_EDID_CHECKSUM,
3869 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3871 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3872 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3875 /* Set test active flag here so userspace doesn't interrupt things */
3876 intel_dp->compliance_test_active = 1;
3881 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3883 uint8_t test_result = DP_TEST_NAK;
3887 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3889 uint8_t response = DP_TEST_NAK;
3893 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3895 DRM_DEBUG_KMS("Could not read test request from sink\n");
3900 case DP_TEST_LINK_TRAINING:
3901 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3902 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3903 response = intel_dp_autotest_link_training(intel_dp);
3905 case DP_TEST_LINK_VIDEO_PATTERN:
3906 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3907 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3908 response = intel_dp_autotest_video_pattern(intel_dp);
3910 case DP_TEST_LINK_EDID_READ:
3911 DRM_DEBUG_KMS("EDID test requested\n");
3912 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3913 response = intel_dp_autotest_edid(intel_dp);
3915 case DP_TEST_LINK_PHY_TEST_PATTERN:
3916 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3917 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3918 response = intel_dp_autotest_phy_pattern(intel_dp);
3921 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3926 status = drm_dp_dpcd_write(&intel_dp->aux,
3930 DRM_DEBUG_KMS("Could not write test response to sink\n");
3934 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3938 if (intel_dp->is_mst) {
3943 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3947 /* check link status - esi[10] = 0x200c */
3948 if (intel_dp->active_mst_links &&
3949 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3950 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3951 intel_dp_start_link_train(intel_dp);
3952 intel_dp_stop_link_train(intel_dp);
3955 DRM_DEBUG_KMS("got esi %3ph\n", esi);
3956 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3959 for (retry = 0; retry < 3; retry++) {
3961 wret = drm_dp_dpcd_write(&intel_dp->aux,
3962 DP_SINK_COUNT_ESI+1,
3969 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3971 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
3979 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3980 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3981 intel_dp->is_mst = false;
3982 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3983 /* send a hotplug event */
3984 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3991 intel_dp_check_link_status(struct intel_dp *intel_dp)
3993 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3994 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3995 u8 link_status[DP_LINK_STATUS_SIZE];
3997 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3999 if (!intel_dp_get_link_status(intel_dp, link_status)) {
4000 DRM_ERROR("Failed to get link status\n");
4004 if (!intel_encoder->base.crtc)
4007 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4010 /* if link training is requested we should perform it always */
4011 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4012 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4013 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4014 intel_encoder->base.name);
4015 intel_dp_start_link_train(intel_dp);
4016 intel_dp_stop_link_train(intel_dp);
4021 * According to DP spec
4024 * 2. Configure link according to Receiver Capabilities
4025 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4026 * 4. Check link status on receipt of hot-plug interrupt
4028 * intel_dp_short_pulse - handles short pulse interrupts
4029 * when full detection is not required.
4030 * Returns %true if short pulse is handled and full detection
4031 * is NOT required and %false otherwise.
4034 intel_dp_short_pulse(struct intel_dp *intel_dp)
4036 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4037 u8 sink_irq_vector = 0;
4038 u8 old_sink_count = intel_dp->sink_count;
4042 * Clearing compliance test variables to allow capturing
4043 * of values for next automated test request.
4045 intel_dp->compliance_test_active = 0;
4046 intel_dp->compliance_test_type = 0;
4047 intel_dp->compliance_test_data = 0;
4050 * Now read the DPCD to see if it's actually running
4051 * If the current value of sink count doesn't match with
4052 * the value that was stored earlier or dpcd read failed
4053 * we need to do full detection
4055 ret = intel_dp_get_dpcd(intel_dp);
4057 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4058 /* No need to proceed if we are going to do full detect */
4062 /* Try to read the source of the interrupt */
4063 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4064 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4065 sink_irq_vector != 0) {
4066 /* Clear interrupt source */
4067 drm_dp_dpcd_writeb(&intel_dp->aux,
4068 DP_DEVICE_SERVICE_IRQ_VECTOR,
4071 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4072 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4073 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4074 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4077 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4078 intel_dp_check_link_status(intel_dp);
4079 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4084 /* XXX this is probably wrong for multiple downstream ports */
4085 static enum drm_connector_status
4086 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4088 uint8_t *dpcd = intel_dp->dpcd;
4091 if (!intel_dp_get_dpcd(intel_dp))
4092 return connector_status_disconnected;
4094 if (is_edp(intel_dp))
4095 return connector_status_connected;
4097 /* if there's no downstream port, we're done */
4098 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4099 return connector_status_connected;
4101 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4102 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4103 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4105 return intel_dp->sink_count ?
4106 connector_status_connected : connector_status_disconnected;
4109 if (intel_dp_can_mst(intel_dp))
4110 return connector_status_connected;
4112 /* If no HPD, poke DDC gently */
4113 if (drm_probe_ddc(&intel_dp->aux.ddc))
4114 return connector_status_connected;
4116 /* Well we tried, say unknown for unreliable port types */
4117 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4118 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4119 if (type == DP_DS_PORT_TYPE_VGA ||
4120 type == DP_DS_PORT_TYPE_NON_EDID)
4121 return connector_status_unknown;
4123 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4124 DP_DWN_STRM_PORT_TYPE_MASK;
4125 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4126 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4127 return connector_status_unknown;
4130 /* Anything else is out of spec, warn and ignore */
4131 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4132 return connector_status_disconnected;
4135 static enum drm_connector_status
4136 edp_detect(struct intel_dp *intel_dp)
4138 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4139 enum drm_connector_status status;
4141 status = intel_panel_detect(dev);
4142 if (status == connector_status_unknown)
4143 status = connector_status_connected;
4148 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4149 struct intel_digital_port *port)
4153 switch (port->port) {
4157 bit = SDE_PORTB_HOTPLUG;
4160 bit = SDE_PORTC_HOTPLUG;
4163 bit = SDE_PORTD_HOTPLUG;
4166 MISSING_CASE(port->port);
4170 return I915_READ(SDEISR) & bit;
4173 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4174 struct intel_digital_port *port)
4178 switch (port->port) {
4182 bit = SDE_PORTB_HOTPLUG_CPT;
4185 bit = SDE_PORTC_HOTPLUG_CPT;
4188 bit = SDE_PORTD_HOTPLUG_CPT;
4191 bit = SDE_PORTE_HOTPLUG_SPT;
4194 MISSING_CASE(port->port);
4198 return I915_READ(SDEISR) & bit;
4201 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4202 struct intel_digital_port *port)
4206 switch (port->port) {
4208 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4211 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4214 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4217 MISSING_CASE(port->port);
4221 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4224 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4225 struct intel_digital_port *port)
4229 switch (port->port) {
4231 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4234 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4237 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4240 MISSING_CASE(port->port);
4244 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4247 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4248 struct intel_digital_port *intel_dig_port)
4250 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4254 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4257 bit = BXT_DE_PORT_HP_DDIA;
4260 bit = BXT_DE_PORT_HP_DDIB;
4263 bit = BXT_DE_PORT_HP_DDIC;
4270 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4274 * intel_digital_port_connected - is the specified port connected?
4275 * @dev_priv: i915 private structure
4276 * @port: the port to test
4278 * Return %true if @port is connected, %false otherwise.
4280 static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4281 struct intel_digital_port *port)
4283 if (HAS_PCH_IBX(dev_priv))
4284 return ibx_digital_port_connected(dev_priv, port);
4285 else if (HAS_PCH_SPLIT(dev_priv))
4286 return cpt_digital_port_connected(dev_priv, port);
4287 else if (IS_BROXTON(dev_priv))
4288 return bxt_digital_port_connected(dev_priv, port);
4289 else if (IS_GM45(dev_priv))
4290 return gm45_digital_port_connected(dev_priv, port);
4292 return g4x_digital_port_connected(dev_priv, port);
4295 static struct edid *
4296 intel_dp_get_edid(struct intel_dp *intel_dp)
4298 struct intel_connector *intel_connector = intel_dp->attached_connector;
4300 /* use cached edid if we have one */
4301 if (intel_connector->edid) {
4303 if (IS_ERR(intel_connector->edid))
4306 return drm_edid_duplicate(intel_connector->edid);
4308 return drm_get_edid(&intel_connector->base,
4309 &intel_dp->aux.ddc);
4313 intel_dp_set_edid(struct intel_dp *intel_dp)
4315 struct intel_connector *intel_connector = intel_dp->attached_connector;
4318 intel_dp_unset_edid(intel_dp);
4319 edid = intel_dp_get_edid(intel_dp);
4320 intel_connector->detect_edid = edid;
4322 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4323 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4325 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4329 intel_dp_unset_edid(struct intel_dp *intel_dp)
4331 struct intel_connector *intel_connector = intel_dp->attached_connector;
4333 kfree(intel_connector->detect_edid);
4334 intel_connector->detect_edid = NULL;
4336 intel_dp->has_audio = false;
4339 static enum drm_connector_status
4340 intel_dp_long_pulse(struct intel_connector *intel_connector)
4342 struct drm_connector *connector = &intel_connector->base;
4343 struct intel_dp *intel_dp = intel_attached_dp(connector);
4344 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4345 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4346 struct drm_device *dev = connector->dev;
4347 enum drm_connector_status status;
4348 enum intel_display_power_domain power_domain;
4349 u8 sink_irq_vector = 0;
4351 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4352 intel_display_power_get(to_i915(dev), power_domain);
4354 /* Can't disconnect eDP, but you can close the lid... */
4355 if (is_edp(intel_dp))
4356 status = edp_detect(intel_dp);
4357 else if (intel_digital_port_connected(to_i915(dev),
4358 dp_to_dig_port(intel_dp)))
4359 status = intel_dp_detect_dpcd(intel_dp);
4361 status = connector_status_disconnected;
4363 if (status == connector_status_disconnected) {
4364 intel_dp->compliance_test_active = 0;
4365 intel_dp->compliance_test_type = 0;
4366 intel_dp->compliance_test_data = 0;
4368 if (intel_dp->is_mst) {
4369 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4371 intel_dp->mst_mgr.mst_state);
4372 intel_dp->is_mst = false;
4373 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4380 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4381 intel_encoder->type = INTEL_OUTPUT_DP;
4383 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4384 yesno(intel_dp_source_supports_hbr2(intel_dp)),
4385 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4387 intel_dp_print_rates(intel_dp);
4389 intel_dp_probe_oui(intel_dp);
4391 intel_dp_print_hw_revision(intel_dp);
4392 intel_dp_print_sw_revision(intel_dp);
4394 intel_dp_configure_mst(intel_dp);
4396 if (intel_dp->is_mst) {
4398 * If we are in MST mode then this connector
4399 * won't appear connected or have anything
4402 status = connector_status_disconnected;
4404 } else if (connector->status == connector_status_connected) {
4406 * If display was connected already and is still connected
4407 * check links status, there has been known issues of
4408 * link loss triggerring long pulse!!!!
4410 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4411 intel_dp_check_link_status(intel_dp);
4412 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4417 * Clearing NACK and defer counts to get their exact values
4418 * while reading EDID which are required by Compliance tests
4419 * 4.2.2.4 and 4.2.2.5
4421 intel_dp->aux.i2c_nack_count = 0;
4422 intel_dp->aux.i2c_defer_count = 0;
4424 intel_dp_set_edid(intel_dp);
4425 if (is_edp(intel_dp) || intel_connector->detect_edid)
4426 status = connector_status_connected;
4427 intel_dp->detect_done = true;
4429 /* Try to read the source of the interrupt */
4430 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4431 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4432 sink_irq_vector != 0) {
4433 /* Clear interrupt source */
4434 drm_dp_dpcd_writeb(&intel_dp->aux,
4435 DP_DEVICE_SERVICE_IRQ_VECTOR,
4438 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4439 intel_dp_handle_test_request(intel_dp);
4440 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4441 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4445 if (status != connector_status_connected && !intel_dp->is_mst)
4446 intel_dp_unset_edid(intel_dp);
4448 intel_display_power_put(to_i915(dev), power_domain);
4452 static enum drm_connector_status
4453 intel_dp_detect(struct drm_connector *connector, bool force)
4455 struct intel_dp *intel_dp = intel_attached_dp(connector);
4456 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4457 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4458 enum drm_connector_status status = connector->status;
4460 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4461 connector->base.id, connector->name);
4463 if (intel_dp->is_mst) {
4464 /* MST devices are disconnected from a monitor POV */
4465 intel_dp_unset_edid(intel_dp);
4466 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4467 intel_encoder->type = INTEL_OUTPUT_DP;
4468 return connector_status_disconnected;
4471 /* If full detect is not performed yet, do a full detect */
4472 if (!intel_dp->detect_done)
4473 status = intel_dp_long_pulse(intel_dp->attached_connector);
4475 intel_dp->detect_done = false;
4481 intel_dp_force(struct drm_connector *connector)
4483 struct intel_dp *intel_dp = intel_attached_dp(connector);
4484 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4485 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4486 enum intel_display_power_domain power_domain;
4488 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4489 connector->base.id, connector->name);
4490 intel_dp_unset_edid(intel_dp);
4492 if (connector->status != connector_status_connected)
4495 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4496 intel_display_power_get(dev_priv, power_domain);
4498 intel_dp_set_edid(intel_dp);
4500 intel_display_power_put(dev_priv, power_domain);
4502 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4503 intel_encoder->type = INTEL_OUTPUT_DP;
4506 static int intel_dp_get_modes(struct drm_connector *connector)
4508 struct intel_connector *intel_connector = to_intel_connector(connector);
4511 edid = intel_connector->detect_edid;
4513 int ret = intel_connector_update_modes(connector, edid);
4518 /* if eDP has no EDID, fall back to fixed mode */
4519 if (is_edp(intel_attached_dp(connector)) &&
4520 intel_connector->panel.fixed_mode) {
4521 struct drm_display_mode *mode;
4523 mode = drm_mode_duplicate(connector->dev,
4524 intel_connector->panel.fixed_mode);
4526 drm_mode_probed_add(connector, mode);
4535 intel_dp_detect_audio(struct drm_connector *connector)
4537 bool has_audio = false;
4540 edid = to_intel_connector(connector)->detect_edid;
4542 has_audio = drm_detect_monitor_audio(edid);
4548 intel_dp_set_property(struct drm_connector *connector,
4549 struct drm_property *property,
4552 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4553 struct intel_connector *intel_connector = to_intel_connector(connector);
4554 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4555 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4558 ret = drm_object_property_set_value(&connector->base, property, val);
4562 if (property == dev_priv->force_audio_property) {
4566 if (i == intel_dp->force_audio)
4569 intel_dp->force_audio = i;
4571 if (i == HDMI_AUDIO_AUTO)
4572 has_audio = intel_dp_detect_audio(connector);
4574 has_audio = (i == HDMI_AUDIO_ON);
4576 if (has_audio == intel_dp->has_audio)
4579 intel_dp->has_audio = has_audio;
4583 if (property == dev_priv->broadcast_rgb_property) {
4584 bool old_auto = intel_dp->color_range_auto;
4585 bool old_range = intel_dp->limited_color_range;
4588 case INTEL_BROADCAST_RGB_AUTO:
4589 intel_dp->color_range_auto = true;
4591 case INTEL_BROADCAST_RGB_FULL:
4592 intel_dp->color_range_auto = false;
4593 intel_dp->limited_color_range = false;
4595 case INTEL_BROADCAST_RGB_LIMITED:
4596 intel_dp->color_range_auto = false;
4597 intel_dp->limited_color_range = true;
4603 if (old_auto == intel_dp->color_range_auto &&
4604 old_range == intel_dp->limited_color_range)
4610 if (is_edp(intel_dp) &&
4611 property == connector->dev->mode_config.scaling_mode_property) {
4612 if (val == DRM_MODE_SCALE_NONE) {
4613 DRM_DEBUG_KMS("no scaling not supported\n");
4616 if (HAS_GMCH_DISPLAY(dev_priv) &&
4617 val == DRM_MODE_SCALE_CENTER) {
4618 DRM_DEBUG_KMS("centering not supported\n");
4622 if (intel_connector->panel.fitting_mode == val) {
4623 /* the eDP scaling property is not changed */
4626 intel_connector->panel.fitting_mode = val;
4634 if (intel_encoder->base.crtc)
4635 intel_crtc_restore_mode(intel_encoder->base.crtc);
4641 intel_dp_connector_register(struct drm_connector *connector)
4643 struct intel_dp *intel_dp = intel_attached_dp(connector);
4646 ret = intel_connector_register(connector);
4650 i915_debugfs_connector_add(connector);
4652 DRM_DEBUG_KMS("registering %s bus for %s\n",
4653 intel_dp->aux.name, connector->kdev->kobj.name);
4655 intel_dp->aux.dev = connector->kdev;
4656 return drm_dp_aux_register(&intel_dp->aux);
4660 intel_dp_connector_unregister(struct drm_connector *connector)
4662 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4663 intel_connector_unregister(connector);
4667 intel_dp_connector_destroy(struct drm_connector *connector)
4669 struct intel_connector *intel_connector = to_intel_connector(connector);
4671 kfree(intel_connector->detect_edid);
4673 if (!IS_ERR_OR_NULL(intel_connector->edid))
4674 kfree(intel_connector->edid);
4676 /* Can't call is_edp() since the encoder may have been destroyed
4678 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4679 intel_panel_fini(&intel_connector->panel);
4681 drm_connector_cleanup(connector);
4685 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4687 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4688 struct intel_dp *intel_dp = &intel_dig_port->dp;
4690 intel_dp_mst_encoder_cleanup(intel_dig_port);
4691 if (is_edp(intel_dp)) {
4692 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4694 * vdd might still be enabled do to the delayed vdd off.
4695 * Make sure vdd is actually turned off here.
4698 edp_panel_vdd_off_sync(intel_dp);
4699 pps_unlock(intel_dp);
4701 if (intel_dp->edp_notifier.notifier_call) {
4702 unregister_reboot_notifier(&intel_dp->edp_notifier);
4703 intel_dp->edp_notifier.notifier_call = NULL;
4707 intel_dp_aux_fini(intel_dp);
4709 drm_encoder_cleanup(encoder);
4710 kfree(intel_dig_port);
4713 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4715 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4717 if (!is_edp(intel_dp))
4721 * vdd might still be enabled do to the delayed vdd off.
4722 * Make sure vdd is actually turned off here.
4724 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4726 edp_panel_vdd_off_sync(intel_dp);
4727 pps_unlock(intel_dp);
4730 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4732 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4733 struct drm_device *dev = intel_dig_port->base.base.dev;
4734 struct drm_i915_private *dev_priv = to_i915(dev);
4735 enum intel_display_power_domain power_domain;
4737 lockdep_assert_held(&dev_priv->pps_mutex);
4739 if (!edp_have_panel_vdd(intel_dp))
4743 * The VDD bit needs a power domain reference, so if the bit is
4744 * already enabled when we boot or resume, grab this reference and
4745 * schedule a vdd off, so we don't hold on to the reference
4748 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4749 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4750 intel_display_power_get(dev_priv, power_domain);
4752 edp_panel_vdd_schedule_off(intel_dp);
4755 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4757 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4758 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4760 if (!HAS_DDI(dev_priv))
4761 intel_dp->DP = I915_READ(intel_dp->output_reg);
4763 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4768 /* Reinit the power sequencer, in case BIOS did something with it. */
4769 intel_dp_pps_init(encoder->dev, intel_dp);
4770 intel_edp_panel_vdd_sanitize(intel_dp);
4772 pps_unlock(intel_dp);
4775 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4776 .dpms = drm_atomic_helper_connector_dpms,
4777 .detect = intel_dp_detect,
4778 .force = intel_dp_force,
4779 .fill_modes = drm_helper_probe_single_connector_modes,
4780 .set_property = intel_dp_set_property,
4781 .atomic_get_property = intel_connector_atomic_get_property,
4782 .late_register = intel_dp_connector_register,
4783 .early_unregister = intel_dp_connector_unregister,
4784 .destroy = intel_dp_connector_destroy,
4785 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4786 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4789 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4790 .get_modes = intel_dp_get_modes,
4791 .mode_valid = intel_dp_mode_valid,
4794 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4795 .reset = intel_dp_encoder_reset,
4796 .destroy = intel_dp_encoder_destroy,
4800 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4802 struct intel_dp *intel_dp = &intel_dig_port->dp;
4803 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4804 struct drm_device *dev = intel_dig_port->base.base.dev;
4805 struct drm_i915_private *dev_priv = to_i915(dev);
4806 enum intel_display_power_domain power_domain;
4807 enum irqreturn ret = IRQ_NONE;
4809 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4810 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4811 intel_dig_port->base.type = INTEL_OUTPUT_DP;
4813 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4815 * vdd off can generate a long pulse on eDP which
4816 * would require vdd on to handle it, and thus we
4817 * would end up in an endless cycle of
4818 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4820 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4821 port_name(intel_dig_port->port));
4825 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4826 port_name(intel_dig_port->port),
4827 long_hpd ? "long" : "short");
4830 intel_dp->detect_done = false;
4834 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4835 intel_display_power_get(dev_priv, power_domain);
4837 if (intel_dp->is_mst) {
4838 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4840 * If we were in MST mode, and device is not
4841 * there, get out of MST mode
4843 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4844 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4845 intel_dp->is_mst = false;
4846 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4848 intel_dp->detect_done = false;
4853 if (!intel_dp->is_mst) {
4854 if (!intel_dp_short_pulse(intel_dp)) {
4855 intel_dp->detect_done = false;
4863 intel_display_power_put(dev_priv, power_domain);
4868 /* check the VBT to see whether the eDP is on another port */
4869 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4871 struct drm_i915_private *dev_priv = to_i915(dev);
4874 * eDP not supported on g4x. so bail out early just
4875 * for a bit extra safety in case the VBT is bonkers.
4877 if (INTEL_INFO(dev)->gen < 5)
4883 return intel_bios_is_port_edp(dev_priv, port);
4887 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4889 struct intel_connector *intel_connector = to_intel_connector(connector);
4891 intel_attach_force_audio_property(connector);
4892 intel_attach_broadcast_rgb_property(connector);
4893 intel_dp->color_range_auto = true;
4895 if (is_edp(intel_dp)) {
4896 drm_mode_create_scaling_mode_property(connector->dev);
4897 drm_object_attach_property(
4899 connector->dev->mode_config.scaling_mode_property,
4900 DRM_MODE_SCALE_ASPECT);
4901 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4905 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4907 intel_dp->panel_power_off_time = ktime_get_boottime();
4908 intel_dp->last_power_on = jiffies;
4909 intel_dp->last_backlight_off = jiffies;
4913 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
4914 struct intel_dp *intel_dp, struct edp_power_seq *seq)
4916 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
4917 struct pps_registers regs;
4919 intel_pps_get_registers(dev_priv, intel_dp, ®s);
4921 /* Workaround: Need to write PP_CONTROL with the unlock key as
4922 * the very first thing. */
4923 pp_ctl = ironlake_get_pp_control(intel_dp);
4925 pp_on = I915_READ(regs.pp_on);
4926 pp_off = I915_READ(regs.pp_off);
4927 if (!IS_BROXTON(dev_priv)) {
4928 I915_WRITE(regs.pp_ctrl, pp_ctl);
4929 pp_div = I915_READ(regs.pp_div);
4932 /* Pull timing values out of registers */
4933 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4934 PANEL_POWER_UP_DELAY_SHIFT;
4936 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4937 PANEL_LIGHT_ON_DELAY_SHIFT;
4939 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4940 PANEL_LIGHT_OFF_DELAY_SHIFT;
4942 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4943 PANEL_POWER_DOWN_DELAY_SHIFT;
4945 if (IS_BROXTON(dev_priv)) {
4946 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4947 BXT_POWER_CYCLE_DELAY_SHIFT;
4949 seq->t11_t12 = (tmp - 1) * 1000;
4953 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4954 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4959 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
4961 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4963 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
4967 intel_pps_verify_state(struct drm_i915_private *dev_priv,
4968 struct intel_dp *intel_dp)
4970 struct edp_power_seq hw;
4971 struct edp_power_seq *sw = &intel_dp->pps_delays;
4973 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
4975 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
4976 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
4977 DRM_ERROR("PPS state mismatch\n");
4978 intel_pps_dump_state("sw", sw);
4979 intel_pps_dump_state("hw", &hw);
4984 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4985 struct intel_dp *intel_dp)
4987 struct drm_i915_private *dev_priv = to_i915(dev);
4988 struct edp_power_seq cur, vbt, spec,
4989 *final = &intel_dp->pps_delays;
4991 lockdep_assert_held(&dev_priv->pps_mutex);
4993 /* already initialized? */
4994 if (final->t11_t12 != 0)
4997 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
4999 intel_pps_dump_state("cur", &cur);
5001 vbt = dev_priv->vbt.edp.pps;
5003 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5004 * our hw here, which are all in 100usec. */
5005 spec.t1_t3 = 210 * 10;
5006 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5007 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5008 spec.t10 = 500 * 10;
5009 /* This one is special and actually in units of 100ms, but zero
5010 * based in the hw (so we need to add 100 ms). But the sw vbt
5011 * table multiplies it with 1000 to make it in units of 100usec,
5013 spec.t11_t12 = (510 + 100) * 10;
5015 intel_pps_dump_state("vbt", &vbt);
5017 /* Use the max of the register settings and vbt. If both are
5018 * unset, fall back to the spec limits. */
5019 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5021 max(cur.field, vbt.field))
5022 assign_final(t1_t3);
5026 assign_final(t11_t12);
5029 #define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5030 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5031 intel_dp->backlight_on_delay = get_delay(t8);
5032 intel_dp->backlight_off_delay = get_delay(t9);
5033 intel_dp->panel_power_down_delay = get_delay(t10);
5034 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5037 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5038 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5039 intel_dp->panel_power_cycle_delay);
5041 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5042 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5045 * We override the HW backlight delays to 1 because we do manual waits
5046 * on them. For T8, even BSpec recommends doing it. For T9, if we
5047 * don't do this, we'll end up waiting for the backlight off delay
5048 * twice: once when we do the manual sleep, and once when we disable
5049 * the panel and wait for the PP_STATUS bit to become zero.
5056 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5057 struct intel_dp *intel_dp)
5059 struct drm_i915_private *dev_priv = to_i915(dev);
5060 u32 pp_on, pp_off, pp_div, port_sel = 0;
5061 int div = dev_priv->rawclk_freq / 1000;
5062 struct pps_registers regs;
5063 enum port port = dp_to_dig_port(intel_dp)->port;
5064 const struct edp_power_seq *seq = &intel_dp->pps_delays;
5066 lockdep_assert_held(&dev_priv->pps_mutex);
5068 intel_pps_get_registers(dev_priv, intel_dp, ®s);
5070 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5071 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5072 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5073 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5074 /* Compute the divisor for the pp clock, simply match the Bspec
5076 if (IS_BROXTON(dev_priv)) {
5077 pp_div = I915_READ(regs.pp_ctrl);
5078 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5079 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5080 << BXT_POWER_CYCLE_DELAY_SHIFT);
5082 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5083 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5084 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5087 /* Haswell doesn't have any port selection bits for the panel
5088 * power sequencer any more. */
5089 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5090 port_sel = PANEL_PORT_SELECT_VLV(port);
5091 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5093 port_sel = PANEL_PORT_SELECT_DPA;
5095 port_sel = PANEL_PORT_SELECT_DPD;
5100 I915_WRITE(regs.pp_on, pp_on);
5101 I915_WRITE(regs.pp_off, pp_off);
5102 if (IS_BROXTON(dev_priv))
5103 I915_WRITE(regs.pp_ctrl, pp_div);
5105 I915_WRITE(regs.pp_div, pp_div);
5107 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5108 I915_READ(regs.pp_on),
5109 I915_READ(regs.pp_off),
5110 IS_BROXTON(dev_priv) ?
5111 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5112 I915_READ(regs.pp_div));
5115 static void intel_dp_pps_init(struct drm_device *dev,
5116 struct intel_dp *intel_dp)
5118 struct drm_i915_private *dev_priv = to_i915(dev);
5120 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5121 vlv_initial_power_sequencer_setup(intel_dp);
5123 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5124 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5129 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5130 * @dev_priv: i915 device
5131 * @crtc_state: a pointer to the active intel_crtc_state
5132 * @refresh_rate: RR to be programmed
5134 * This function gets called when refresh rate (RR) has to be changed from
5135 * one frequency to another. Switches can be between high and low RR
5136 * supported by the panel or to any other RR based on media playback (in
5137 * this case, RR value needs to be passed from user space).
5139 * The caller of this function needs to take a lock on dev_priv->drrs.
5141 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5142 struct intel_crtc_state *crtc_state,
5145 struct intel_encoder *encoder;
5146 struct intel_digital_port *dig_port = NULL;
5147 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5149 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5151 if (refresh_rate <= 0) {
5152 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5156 if (intel_dp == NULL) {
5157 DRM_DEBUG_KMS("DRRS not supported.\n");
5162 * FIXME: This needs proper synchronization with psr state for some
5163 * platforms that cannot have PSR and DRRS enabled at the same time.
5166 dig_port = dp_to_dig_port(intel_dp);
5167 encoder = &dig_port->base;
5168 intel_crtc = to_intel_crtc(encoder->base.crtc);
5171 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5175 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5176 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5180 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5182 index = DRRS_LOW_RR;
5184 if (index == dev_priv->drrs.refresh_rate_type) {
5186 "DRRS requested for previously set RR...ignoring\n");
5190 if (!crtc_state->base.active) {
5191 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5195 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5198 intel_dp_set_m_n(intel_crtc, M1_N1);
5201 intel_dp_set_m_n(intel_crtc, M2_N2);
5205 DRM_ERROR("Unsupported refreshrate type\n");
5207 } else if (INTEL_GEN(dev_priv) > 6) {
5208 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5211 val = I915_READ(reg);
5212 if (index > DRRS_HIGH_RR) {
5213 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5214 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5216 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5218 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5219 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5221 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5223 I915_WRITE(reg, val);
5226 dev_priv->drrs.refresh_rate_type = index;
5228 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5232 * intel_edp_drrs_enable - init drrs struct if supported
5233 * @intel_dp: DP struct
5234 * @crtc_state: A pointer to the active crtc state.
5236 * Initializes frontbuffer_bits and drrs.dp
5238 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5239 struct intel_crtc_state *crtc_state)
5241 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5242 struct drm_i915_private *dev_priv = to_i915(dev);
5244 if (!crtc_state->has_drrs) {
5245 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5249 mutex_lock(&dev_priv->drrs.mutex);
5250 if (WARN_ON(dev_priv->drrs.dp)) {
5251 DRM_ERROR("DRRS already enabled\n");
5255 dev_priv->drrs.busy_frontbuffer_bits = 0;
5257 dev_priv->drrs.dp = intel_dp;
5260 mutex_unlock(&dev_priv->drrs.mutex);
5264 * intel_edp_drrs_disable - Disable DRRS
5265 * @intel_dp: DP struct
5266 * @old_crtc_state: Pointer to old crtc_state.
5269 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5270 struct intel_crtc_state *old_crtc_state)
5272 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5273 struct drm_i915_private *dev_priv = to_i915(dev);
5275 if (!old_crtc_state->has_drrs)
5278 mutex_lock(&dev_priv->drrs.mutex);
5279 if (!dev_priv->drrs.dp) {
5280 mutex_unlock(&dev_priv->drrs.mutex);
5284 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5285 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5286 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5288 dev_priv->drrs.dp = NULL;
5289 mutex_unlock(&dev_priv->drrs.mutex);
5291 cancel_delayed_work_sync(&dev_priv->drrs.work);
5294 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5296 struct drm_i915_private *dev_priv =
5297 container_of(work, typeof(*dev_priv), drrs.work.work);
5298 struct intel_dp *intel_dp;
5300 mutex_lock(&dev_priv->drrs.mutex);
5302 intel_dp = dev_priv->drrs.dp;
5308 * The delayed work can race with an invalidate hence we need to
5312 if (dev_priv->drrs.busy_frontbuffer_bits)
5315 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5316 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5318 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5319 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5323 mutex_unlock(&dev_priv->drrs.mutex);
5327 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5328 * @dev_priv: i915 device
5329 * @frontbuffer_bits: frontbuffer plane tracking bits
5331 * This function gets called everytime rendering on the given planes start.
5332 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5334 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5336 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5337 unsigned int frontbuffer_bits)
5339 struct drm_crtc *crtc;
5342 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5345 cancel_delayed_work(&dev_priv->drrs.work);
5347 mutex_lock(&dev_priv->drrs.mutex);
5348 if (!dev_priv->drrs.dp) {
5349 mutex_unlock(&dev_priv->drrs.mutex);
5353 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5354 pipe = to_intel_crtc(crtc)->pipe;
5356 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5357 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5359 /* invalidate means busy screen hence upclock */
5360 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5361 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5362 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5364 mutex_unlock(&dev_priv->drrs.mutex);
5368 * intel_edp_drrs_flush - Restart Idleness DRRS
5369 * @dev_priv: i915 device
5370 * @frontbuffer_bits: frontbuffer plane tracking bits
5372 * This function gets called every time rendering on the given planes has
5373 * completed or flip on a crtc is completed. So DRRS should be upclocked
5374 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5375 * if no other planes are dirty.
5377 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5379 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5380 unsigned int frontbuffer_bits)
5382 struct drm_crtc *crtc;
5385 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5388 cancel_delayed_work(&dev_priv->drrs.work);
5390 mutex_lock(&dev_priv->drrs.mutex);
5391 if (!dev_priv->drrs.dp) {
5392 mutex_unlock(&dev_priv->drrs.mutex);
5396 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5397 pipe = to_intel_crtc(crtc)->pipe;
5399 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5400 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5402 /* flush means busy screen hence upclock */
5403 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5404 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5405 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5408 * flush also means no more activity hence schedule downclock, if all
5409 * other fbs are quiescent too
5411 if (!dev_priv->drrs.busy_frontbuffer_bits)
5412 schedule_delayed_work(&dev_priv->drrs.work,
5413 msecs_to_jiffies(1000));
5414 mutex_unlock(&dev_priv->drrs.mutex);
5418 * DOC: Display Refresh Rate Switching (DRRS)
5420 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5421 * which enables swtching between low and high refresh rates,
5422 * dynamically, based on the usage scenario. This feature is applicable
5423 * for internal panels.
5425 * Indication that the panel supports DRRS is given by the panel EDID, which
5426 * would list multiple refresh rates for one resolution.
5428 * DRRS is of 2 types - static and seamless.
5429 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5430 * (may appear as a blink on screen) and is used in dock-undock scenario.
5431 * Seamless DRRS involves changing RR without any visual effect to the user
5432 * and can be used during normal system usage. This is done by programming
5433 * certain registers.
5435 * Support for static/seamless DRRS may be indicated in the VBT based on
5436 * inputs from the panel spec.
5438 * DRRS saves power by switching to low RR based on usage scenarios.
5440 * The implementation is based on frontbuffer tracking implementation. When
5441 * there is a disturbance on the screen triggered by user activity or a periodic
5442 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5443 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5446 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5447 * and intel_edp_drrs_flush() are called.
5449 * DRRS can be further extended to support other internal panels and also
5450 * the scenario of video playback wherein RR is set based on the rate
5451 * requested by userspace.
5455 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5456 * @intel_connector: eDP connector
5457 * @fixed_mode: preferred mode of panel
5459 * This function is called only once at driver load to initialize basic
5463 * Downclock mode if panel supports it, else return NULL.
5464 * DRRS support is determined by the presence of downclock mode (apart
5465 * from VBT setting).
5467 static struct drm_display_mode *
5468 intel_dp_drrs_init(struct intel_connector *intel_connector,
5469 struct drm_display_mode *fixed_mode)
5471 struct drm_connector *connector = &intel_connector->base;
5472 struct drm_device *dev = connector->dev;
5473 struct drm_i915_private *dev_priv = to_i915(dev);
5474 struct drm_display_mode *downclock_mode = NULL;
5476 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5477 mutex_init(&dev_priv->drrs.mutex);
5479 if (INTEL_INFO(dev)->gen <= 6) {
5480 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5484 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5485 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5489 downclock_mode = intel_find_panel_downclock
5490 (dev, fixed_mode, connector);
5492 if (!downclock_mode) {
5493 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5497 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5499 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5500 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5501 return downclock_mode;
5504 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5505 struct intel_connector *intel_connector)
5507 struct drm_connector *connector = &intel_connector->base;
5508 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5509 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5510 struct drm_device *dev = intel_encoder->base.dev;
5511 struct drm_i915_private *dev_priv = to_i915(dev);
5512 struct drm_display_mode *fixed_mode = NULL;
5513 struct drm_display_mode *downclock_mode = NULL;
5515 struct drm_display_mode *scan;
5517 enum pipe pipe = INVALID_PIPE;
5519 if (!is_edp(intel_dp))
5523 * On IBX/CPT we may get here with LVDS already registered. Since the
5524 * driver uses the only internal power sequencer available for both
5525 * eDP and LVDS bail out early in this case to prevent interfering
5526 * with an already powered-on LVDS power sequencer.
5528 if (intel_get_lvds_encoder(dev)) {
5529 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5530 DRM_INFO("LVDS was detected, not registering eDP\n");
5537 intel_dp_init_panel_power_timestamps(intel_dp);
5538 intel_dp_pps_init(dev, intel_dp);
5539 intel_edp_panel_vdd_sanitize(intel_dp);
5541 pps_unlock(intel_dp);
5543 /* Cache DPCD and EDID for edp. */
5544 has_dpcd = intel_edp_init_dpcd(intel_dp);
5547 /* if this fails, presume the device is a ghost */
5548 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5552 mutex_lock(&dev->mode_config.mutex);
5553 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5555 if (drm_add_edid_modes(connector, edid)) {
5556 drm_mode_connector_update_edid_property(connector,
5558 drm_edid_to_eld(connector, edid);
5561 edid = ERR_PTR(-EINVAL);
5564 edid = ERR_PTR(-ENOENT);
5566 intel_connector->edid = edid;
5568 /* prefer fixed mode from EDID if available */
5569 list_for_each_entry(scan, &connector->probed_modes, head) {
5570 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5571 fixed_mode = drm_mode_duplicate(dev, scan);
5572 downclock_mode = intel_dp_drrs_init(
5573 intel_connector, fixed_mode);
5578 /* fallback to VBT if available for eDP */
5579 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5580 fixed_mode = drm_mode_duplicate(dev,
5581 dev_priv->vbt.lfp_lvds_vbt_mode);
5583 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5584 connector->display_info.width_mm = fixed_mode->width_mm;
5585 connector->display_info.height_mm = fixed_mode->height_mm;
5588 mutex_unlock(&dev->mode_config.mutex);
5590 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5591 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5592 register_reboot_notifier(&intel_dp->edp_notifier);
5595 * Figure out the current pipe for the initial backlight setup.
5596 * If the current pipe isn't valid, try the PPS pipe, and if that
5597 * fails just assume pipe A.
5599 if (IS_CHERRYVIEW(dev_priv))
5600 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5602 pipe = PORT_TO_PIPE(intel_dp->DP);
5604 if (pipe != PIPE_A && pipe != PIPE_B)
5605 pipe = intel_dp->pps_pipe;
5607 if (pipe != PIPE_A && pipe != PIPE_B)
5610 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5614 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5615 intel_connector->panel.backlight.power = intel_edp_backlight_power;
5616 intel_panel_setup_backlight(connector, pipe);
5621 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5623 * vdd might still be enabled do to the delayed vdd off.
5624 * Make sure vdd is actually turned off here.
5627 edp_panel_vdd_off_sync(intel_dp);
5628 pps_unlock(intel_dp);
5634 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5635 struct intel_connector *intel_connector)
5637 struct drm_connector *connector = &intel_connector->base;
5638 struct intel_dp *intel_dp = &intel_dig_port->dp;
5639 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5640 struct drm_device *dev = intel_encoder->base.dev;
5641 struct drm_i915_private *dev_priv = to_i915(dev);
5642 enum port port = intel_dig_port->port;
5645 if (WARN(intel_dig_port->max_lanes < 1,
5646 "Not enough lanes (%d) for DP on port %c\n",
5647 intel_dig_port->max_lanes, port_name(port)))
5650 intel_dp->pps_pipe = INVALID_PIPE;
5652 /* intel_dp vfuncs */
5653 if (INTEL_INFO(dev)->gen >= 9)
5654 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5655 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5656 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5657 else if (HAS_PCH_SPLIT(dev_priv))
5658 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5660 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5662 if (INTEL_INFO(dev)->gen >= 9)
5663 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5665 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5667 if (HAS_DDI(dev_priv))
5668 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5670 /* Preserve the current hw state. */
5671 intel_dp->DP = I915_READ(intel_dp->output_reg);
5672 intel_dp->attached_connector = intel_connector;
5674 if (intel_dp_is_edp(dev, port))
5675 type = DRM_MODE_CONNECTOR_eDP;
5677 type = DRM_MODE_CONNECTOR_DisplayPort;
5680 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5681 * for DP the encoder type can be set by the caller to
5682 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5684 if (type == DRM_MODE_CONNECTOR_eDP)
5685 intel_encoder->type = INTEL_OUTPUT_EDP;
5687 /* eDP only on port B and/or C on vlv/chv */
5688 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
5689 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5692 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5693 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5696 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5697 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5699 connector->interlace_allowed = true;
5700 connector->doublescan_allowed = 0;
5702 intel_dp_aux_init(intel_dp);
5704 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5705 edp_panel_vdd_work);
5707 intel_connector_attach_encoder(intel_connector, intel_encoder);
5709 if (HAS_DDI(dev_priv))
5710 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5712 intel_connector->get_hw_state = intel_connector_get_hw_state;
5714 /* Set up the hotplug pin. */
5717 intel_encoder->hpd_pin = HPD_PORT_A;
5720 intel_encoder->hpd_pin = HPD_PORT_B;
5721 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
5722 intel_encoder->hpd_pin = HPD_PORT_A;
5725 intel_encoder->hpd_pin = HPD_PORT_C;
5728 intel_encoder->hpd_pin = HPD_PORT_D;
5731 intel_encoder->hpd_pin = HPD_PORT_E;
5737 /* init MST on ports that can support it */
5738 if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
5739 (port == PORT_B || port == PORT_C || port == PORT_D))
5740 intel_dp_mst_encoder_init(intel_dig_port,
5741 intel_connector->base.base.id);
5743 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5744 intel_dp_aux_fini(intel_dp);
5745 intel_dp_mst_encoder_cleanup(intel_dig_port);
5749 intel_dp_add_properties(intel_dp, connector);
5751 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5752 * 0xd. Failure to do so will result in spurious interrupts being
5753 * generated on the port when a cable is not attached.
5755 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
5756 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5757 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5763 drm_connector_cleanup(connector);
5768 bool intel_dp_init(struct drm_device *dev,
5769 i915_reg_t output_reg,
5772 struct drm_i915_private *dev_priv = to_i915(dev);
5773 struct intel_digital_port *intel_dig_port;
5774 struct intel_encoder *intel_encoder;
5775 struct drm_encoder *encoder;
5776 struct intel_connector *intel_connector;
5778 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5779 if (!intel_dig_port)
5782 intel_connector = intel_connector_alloc();
5783 if (!intel_connector)
5784 goto err_connector_alloc;
5786 intel_encoder = &intel_dig_port->base;
5787 encoder = &intel_encoder->base;
5789 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5790 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
5791 goto err_encoder_init;
5793 intel_encoder->compute_config = intel_dp_compute_config;
5794 intel_encoder->disable = intel_disable_dp;
5795 intel_encoder->get_hw_state = intel_dp_get_hw_state;
5796 intel_encoder->get_config = intel_dp_get_config;
5797 intel_encoder->suspend = intel_dp_encoder_suspend;
5798 if (IS_CHERRYVIEW(dev_priv)) {
5799 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5800 intel_encoder->pre_enable = chv_pre_enable_dp;
5801 intel_encoder->enable = vlv_enable_dp;
5802 intel_encoder->post_disable = chv_post_disable_dp;
5803 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
5804 } else if (IS_VALLEYVIEW(dev_priv)) {
5805 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5806 intel_encoder->pre_enable = vlv_pre_enable_dp;
5807 intel_encoder->enable = vlv_enable_dp;
5808 intel_encoder->post_disable = vlv_post_disable_dp;
5810 intel_encoder->pre_enable = g4x_pre_enable_dp;
5811 intel_encoder->enable = g4x_enable_dp;
5812 if (INTEL_INFO(dev)->gen >= 5)
5813 intel_encoder->post_disable = ilk_post_disable_dp;
5816 intel_dig_port->port = port;
5817 intel_dig_port->dp.output_reg = output_reg;
5818 intel_dig_port->max_lanes = 4;
5820 intel_encoder->type = INTEL_OUTPUT_DP;
5821 if (IS_CHERRYVIEW(dev_priv)) {
5823 intel_encoder->crtc_mask = 1 << 2;
5825 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5827 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5829 intel_encoder->cloneable = 0;
5830 intel_encoder->port = port;
5832 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5833 dev_priv->hotplug.irq_port[port] = intel_dig_port;
5835 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5836 goto err_init_connector;
5841 drm_encoder_cleanup(encoder);
5843 kfree(intel_connector);
5844 err_connector_alloc:
5845 kfree(intel_dig_port);
5849 void intel_dp_mst_suspend(struct drm_device *dev)
5851 struct drm_i915_private *dev_priv = to_i915(dev);
5855 for (i = 0; i < I915_MAX_PORTS; i++) {
5856 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5858 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5861 if (intel_dig_port->dp.is_mst)
5862 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5866 void intel_dp_mst_resume(struct drm_device *dev)
5868 struct drm_i915_private *dev_priv = to_i915(dev);
5871 for (i = 0; i < I915_MAX_PORTS; i++) {
5872 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5875 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5878 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5880 intel_dp_check_mst_status(&intel_dig_port->dp);