drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/reboot.h>
  32 #include <linux/slab.h>
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_hdcp.h>
  41 #include <drm/drm_probe_helper.h>
  42 #include <drm/i915_drm.h>
  43
  44 #include "i915_drv.h"
  45 #include "intel_audio.h"
  46 #include "intel_connector.h"
  47 #include "intel_ddi.h"
  48 #include "intel_dp.h"
  49 #include "intel_drv.h"
  50 #include "intel_hdcp.h"
  51 #include "intel_hdmi.h"
  52 #include "intel_lspcon.h"
  53 #include "intel_lvds.h"
  54 #include "intel_panel.h"
  55 #include "intel_psr.h"
  56
  57 #define DP_DPRX_ESI_LEN 14
  58
  59 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
  60 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER      61440
  61 #define DP_DSC_MIN_SUPPORTED_BPC                8
  62 #define DP_DSC_MAX_SUPPORTED_BPC                10
  63
  64 /* DP DSC throughput values used for slice count calculations KPixels/s */
  65 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  66 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  67 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  68
  69 /* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
  70 #define DP_DSC_FEC_OVERHEAD_FACTOR              976
  71
  72 /* Compliance test status bits  */
  73 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  74 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  75 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  76 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  77
  78 struct dp_link_dpll {
  79         int clock;
  80         struct dpll dpll;
  81 };
  82
  83 static const struct dp_link_dpll g4x_dpll[] = {
  84         { 162000,
  85                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  86         { 270000,
  87                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  88 };
  89
  90 static const struct dp_link_dpll pch_dpll[] = {
  91         { 162000,
  92                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  93         { 270000,
  94                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  95 };
  96
  97 static const struct dp_link_dpll vlv_dpll[] = {
  98         { 162000,
  99                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 100         { 270000,
 101                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 102 };
 103
 104 /*
 105  * CHV supports eDP 1.4 that have  more link rates.
 106  * Below only provides the fixed rate but exclude variable rate.
 107  */
 108 static const struct dp_link_dpll chv_dpll[] = {
 109         /*
 110          * CHV requires to program fractional division for m2.
 111          * m2 is stored in fixed point format using formula below
 112          * (m2_int << 22) | m2_fraction
 113          */
 114         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 115                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 116         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 117                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 118 };
 119
 120 /* Constants for DP DSC configurations */
 121 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 122
 123 /* With Single pipe configuration, HW is capable of supporting maximum
 124  * of 4 slices per line.
 125  */
 126 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 127
 128 /**
 129  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 130  * @intel_dp: DP struct
 131  *
 132  * If a CPU or PCH DP output is attached to an eDP panel, this function
 133  * will return true, and false otherwise.
 134  */
 135 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 136 {
 137         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 138
 139         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 140 }
 141
 142 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 143 {
 144         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 145 }
 146
 147 static void intel_dp_link_down(struct intel_encoder *encoder,
 148                                const struct intel_crtc_state *old_crtc_state);
 149 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 150 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 151 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 152                                            const struct intel_crtc_state *crtc_state);
 153 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 154                                       enum pipe pipe);
 155 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 156
 157 /* update sink rates from dpcd */
 158 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 159 {
 160         static const int dp_rates[] = {
 161                 162000, 270000, 540000, 810000
 162         };
 163         int i, max_rate;
 164
 165         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 166
 167         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 168                 if (dp_rates[i] > max_rate)
 169                         break;
 170                 intel_dp->sink_rates[i] = dp_rates[i];
 171         }
 172
 173         intel_dp->num_sink_rates = i;
 174 }
 175
 176 /* Get length of rates array potentially limited by max_rate. */
 177 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 178 {
 179         int i;
 180
 181         /* Limit results by potentially reduced max rate */
 182         for (i = 0; i < len; i++) {
 183                 if (rates[len - i - 1] <= max_rate)
 184                         return len - i;
 185         }
 186
 187         return 0;
 188 }
 189
 190 /* Get length of common rates array potentially limited by max_rate. */
 191 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 192                                           int max_rate)
 193 {
 194         return intel_dp_rate_limit_len(intel_dp->common_rates,
 195                                        intel_dp->num_common_rates, max_rate);
 196 }
 197
 198 /* Theoretical max between source and sink */
 199 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 200 {
 201         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 202 }
 203
 204 static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
 205 {
 206         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 207         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 208         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
 209         u32 lane_info;
 210
 211         if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
 212                 return 4;
 213
 214         lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
 215                      DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
 216                     DP_LANE_ASSIGNMENT_SHIFT(tc_port);
 217
 218         switch (lane_info) {
 219         default:
 220                 MISSING_CASE(lane_info);
 221         case 1:
 222         case 2:
 223         case 4:
 224         case 8:
 225                 return 1;
 226         case 3:
 227         case 12:
 228                 return 2;
 229         case 15:
 230                 return 4;
 231         }
 232 }
 233
 234 /* Theoretical max between source and sink */
 235 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 236 {
 237         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 238         int source_max = intel_dig_port->max_lanes;
 239         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 240         int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
 241
 242         return min3(source_max, sink_max, fia_max);
 243 }
 244
 245 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 246 {
 247         return intel_dp->max_link_lane_count;
 248 }
 249
 250 int
 251 intel_dp_link_required(int pixel_clock, int bpp)
 252 {
 253         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 254         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 255 }
 256
 257 int
 258 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 259 {
 260         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 261          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 262          * is transmitted every LS_Clk per lane, there is no need to account for
 263          * the channel encoding that is done in the PHY layer here.
 264          */
 265
 266         return max_link_clock * max_lanes;
 267 }
 268
 269 static int
 270 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 271 {
 272         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 273         struct intel_encoder *encoder = &intel_dig_port->base;
 274         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 275         int max_dotclk = dev_priv->max_dotclk_freq;
 276         int ds_max_dotclk;
 277
 278         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 279
 280         if (type != DP_DS_PORT_TYPE_VGA)
 281                 return max_dotclk;
 282
 283         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 284                                                     intel_dp->downstream_ports);
 285
 286         if (ds_max_dotclk != 0)
 287                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 288
 289         return max_dotclk;
 290 }
 291
 292 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 293 {
 294         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 295         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 296         enum port port = dig_port->base.port;
 297
 298         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 299
 300         /* Low voltage SKUs are limited to max of 5.4G */
 301         if (voltage == VOLTAGE_INFO_0_85V)
 302                 return 540000;
 303
 304         /* For this SKU 8.1G is supported in all ports */
 305         if (IS_CNL_WITH_PORT_F(dev_priv))
 306                 return 810000;
 307
 308         /* For other SKUs, max rate on ports A and D is 5.4G */
 309         if (port == PORT_A || port == PORT_D)
 310                 return 540000;
 311
 312         return 810000;
 313 }
 314
 315 static int icl_max_source_rate(struct intel_dp *intel_dp)
 316 {
 317         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 318         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 319         enum port port = dig_port->base.port;
 320
 321         if (intel_port_is_combophy(dev_priv, port) &&
 322             !intel_dp_is_edp(intel_dp))
 323                 return 540000;
 324
 325         return 810000;
 326 }
 327
 328 static void
 329 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 330 {
 331         /* The values must be in increasing order */
 332         static const int cnl_rates[] = {
 333                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 334         };
 335         static const int bxt_rates[] = {
 336                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 337         };
 338         static const int skl_rates[] = {
 339                 162000, 216000, 270000, 324000, 432000, 540000
 340         };
 341         static const int hsw_rates[] = {
 342                 162000, 270000, 540000
 343         };
 344         static const int g4x_rates[] = {
 345                 162000, 270000
 346         };
 347         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 348         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 349         const struct ddi_vbt_port_info *info =
 350                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 351         const int *source_rates;
 352         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 353
 354         /* This should only be done once */
 355         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 356
 357         if (INTEL_GEN(dev_priv) >= 10) {
 358                 source_rates = cnl_rates;
 359                 size = ARRAY_SIZE(cnl_rates);
 360                 if (IS_GEN(dev_priv, 10))
 361                         max_rate = cnl_max_source_rate(intel_dp);
 362                 else
 363                         max_rate = icl_max_source_rate(intel_dp);
 364         } else if (IS_GEN9_LP(dev_priv)) {
 365                 source_rates = bxt_rates;
 366                 size = ARRAY_SIZE(bxt_rates);
 367         } else if (IS_GEN9_BC(dev_priv)) {
 368                 source_rates = skl_rates;
 369                 size = ARRAY_SIZE(skl_rates);
 370         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 371                    IS_BROADWELL(dev_priv)) {
 372                 source_rates = hsw_rates;
 373                 size = ARRAY_SIZE(hsw_rates);
 374         } else {
 375                 source_rates = g4x_rates;
 376                 size = ARRAY_SIZE(g4x_rates);
 377         }
 378
 379         if (max_rate && vbt_max_rate)
 380                 max_rate = min(max_rate, vbt_max_rate);
 381         else if (vbt_max_rate)
 382                 max_rate = vbt_max_rate;
 383
 384         if (max_rate)
 385                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 386
 387         intel_dp->source_rates = source_rates;
 388         intel_dp->num_source_rates = size;
 389 }
 390
 391 static int intersect_rates(const int *source_rates, int source_len,
 392                            const int *sink_rates, int sink_len,
 393                            int *common_rates)
 394 {
 395         int i = 0, j = 0, k = 0;
 396
 397         while (i < source_len && j < sink_len) {
 398                 if (source_rates[i] == sink_rates[j]) {
 399                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 400                                 return k;
 401                         common_rates[k] = source_rates[i];
 402                         ++k;
 403                         ++i;
 404                         ++j;
 405                 } else if (source_rates[i] < sink_rates[j]) {
 406                         ++i;
 407                 } else {
 408                         ++j;
 409                 }
 410         }
 411         return k;
 412 }
 413
 414 /* return index of rate in rates array, or -1 if not found */
 415 static int intel_dp_rate_index(const int *rates, int len, int rate)
 416 {
 417         int i;
 418
 419         for (i = 0; i < len; i++)
 420                 if (rate == rates[i])
 421                         return i;
 422
 423         return -1;
 424 }
 425
 426 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 427 {
 428         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 429
 430         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 431                                                      intel_dp->num_source_rates,
 432                                                      intel_dp->sink_rates,
 433                                                      intel_dp->num_sink_rates,
 434                                                      intel_dp->common_rates);
 435
 436         /* Paranoia, there should always be something in common. */
 437         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 438                 intel_dp->common_rates[0] = 162000;
 439                 intel_dp->num_common_rates = 1;
 440         }
 441 }
 442
 443 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 444                                        u8 lane_count)
 445 {
 446         /*
 447          * FIXME: we need to synchronize the current link parameters with
 448          * hardware readout. Currently fast link training doesn't work on
 449          * boot-up.
 450          */
 451         if (link_rate == 0 ||
 452             link_rate > intel_dp->max_link_rate)
 453                 return false;
 454
 455         if (lane_count == 0 ||
 456             lane_count > intel_dp_max_lane_count(intel_dp))
 457                 return false;
 458
 459         return true;
 460 }
 461
 462 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 463                                                      int link_rate,
 464                                                      u8 lane_count)
 465 {
 466         const struct drm_display_mode *fixed_mode =
 467                 intel_dp->attached_connector->panel.fixed_mode;
 468         int mode_rate, max_rate;
 469
 470         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 471         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 472         if (mode_rate > max_rate)
 473                 return false;
 474
 475         return true;
 476 }
 477
 478 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 479                                             int link_rate, u8 lane_count)
 480 {
 481         int index;
 482
 483         index = intel_dp_rate_index(intel_dp->common_rates,
 484                                     intel_dp->num_common_rates,
 485                                     link_rate);
 486         if (index > 0) {
 487                 if (intel_dp_is_edp(intel_dp) &&
 488                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 489                                                               intel_dp->common_rates[index - 1],
 490                                                               lane_count)) {
 491                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 492                         return 0;
 493                 }
 494                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 495                 intel_dp->max_link_lane_count = lane_count;
 496         } else if (lane_count > 1) {
 497                 if (intel_dp_is_edp(intel_dp) &&
 498                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 499                                                               intel_dp_max_common_rate(intel_dp),
 500                                                               lane_count >> 1)) {
 501                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 502                         return 0;
 503                 }
 504                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 505                 intel_dp->max_link_lane_count = lane_count >> 1;
 506         } else {
 507                 DRM_ERROR("Link Training Unsuccessful\n");
 508                 return -1;
 509         }
 510
 511         return 0;
 512 }
 513
 514 static enum drm_mode_status
 515 intel_dp_mode_valid(struct drm_connector *connector,
 516                     struct drm_display_mode *mode)
 517 {
 518         struct intel_dp *intel_dp = intel_attached_dp(connector);
 519         struct intel_connector *intel_connector = to_intel_connector(connector);
 520         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 521         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 522         int target_clock = mode->clock;
 523         int max_rate, mode_rate, max_lanes, max_link_clock;
 524         int max_dotclk;
 525         u16 dsc_max_output_bpp = 0;
 526         u8 dsc_slice_count = 0;
 527
 528         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 529                 return MODE_NO_DBLESCAN;
 530
 531         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 532
 533         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 534                 if (mode->hdisplay > fixed_mode->hdisplay)
 535                         return MODE_PANEL;
 536
 537                 if (mode->vdisplay > fixed_mode->vdisplay)
 538                         return MODE_PANEL;
 539
 540                 target_clock = fixed_mode->clock;
 541         }
 542
 543         max_link_clock = intel_dp_max_link_rate(intel_dp);
 544         max_lanes = intel_dp_max_lane_count(intel_dp);
 545
 546         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 547         mode_rate = intel_dp_link_required(target_clock, 18);
 548
 549         /*
 550          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 551          * integer value since we support only integer values of bpp.
 552          */
 553         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 554             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 555                 if (intel_dp_is_edp(intel_dp)) {
 556                         dsc_max_output_bpp =
 557                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 558                         dsc_slice_count =
 559                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 560                                                                 true);
 561                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 562                         dsc_max_output_bpp =
 563                                 intel_dp_dsc_get_output_bpp(max_link_clock,
 564                                                             max_lanes,
 565                                                             target_clock,
 566                                                             mode->hdisplay) >> 4;
 567                         dsc_slice_count =
 568                                 intel_dp_dsc_get_slice_count(intel_dp,
 569                                                              target_clock,
 570                                                              mode->hdisplay);
 571                 }
 572         }
 573
 574         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
 575             target_clock > max_dotclk)
 576                 return MODE_CLOCK_HIGH;
 577
 578         if (mode->clock < 10000)
 579                 return MODE_CLOCK_LOW;
 580
 581         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 582                 return MODE_H_ILLEGAL;
 583
 584         return MODE_OK;
 585 }
 586
 587 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 588 {
 589         int i;
 590         u32 v = 0;
 591
 592         if (src_bytes > 4)
 593                 src_bytes = 4;
 594         for (i = 0; i < src_bytes; i++)
 595                 v |= ((u32)src[i]) << ((3 - i) * 8);
 596         return v;
 597 }
 598
 599 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 600 {
 601         int i;
 602         if (dst_bytes > 4)
 603                 dst_bytes = 4;
 604         for (i = 0; i < dst_bytes; i++)
 605                 dst[i] = src >> ((3-i) * 8);
 606 }
 607
 608 static void
 609 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 610 static void
 611 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 612                                               bool force_disable_vdd);
 613 static void
 614 intel_dp_pps_init(struct intel_dp *intel_dp);
 615
 616 static intel_wakeref_t
 617 pps_lock(struct intel_dp *intel_dp)
 618 {
 619         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 620         intel_wakeref_t wakeref;
 621
 622         /*
 623          * See intel_power_sequencer_reset() why we need
 624          * a power domain reference here.
 625          */
 626         wakeref = intel_display_power_get(dev_priv,
 627                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 628
 629         mutex_lock(&dev_priv->pps_mutex);
 630
 631         return wakeref;
 632 }
 633
 634 static intel_wakeref_t
 635 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 636 {
 637         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 638
 639         mutex_unlock(&dev_priv->pps_mutex);
 640         intel_display_power_put(dev_priv,
 641                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 642                                 wakeref);
 643         return 0;
 644 }
 645
 646 #define with_pps_lock(dp, wf) \
 647         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 648
 649 static void
 650 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 651 {
 652         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 653         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 654         enum pipe pipe = intel_dp->pps_pipe;
 655         bool pll_enabled, release_cl_override = false;
 656         enum dpio_phy phy = DPIO_PHY(pipe);
 657         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 658         u32 DP;
 659
 660         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 661                  "skipping pipe %c power sequencer kick due to port %c being active\n",
 662                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 663                 return;
 664
 665         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 666                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 667
 668         /* Preserve the BIOS-computed detected bit. This is
 669          * supposed to be read-only.
 670          */
 671         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 672         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 673         DP |= DP_PORT_WIDTH(1);
 674         DP |= DP_LINK_TRAIN_PAT_1;
 675
 676         if (IS_CHERRYVIEW(dev_priv))
 677                 DP |= DP_PIPE_SEL_CHV(pipe);
 678         else
 679                 DP |= DP_PIPE_SEL(pipe);
 680
 681         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 682
 683         /*
 684          * The DPLL for the pipe must be enabled for this to work.
 685          * So enable temporarily it if it's not already enabled.
 686          */
 687         if (!pll_enabled) {
 688                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 689                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 690
 691                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 692                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 693                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 694                                   pipe_name(pipe));
 695                         return;
 696                 }
 697         }
 698
 699         /*
 700          * Similar magic as in intel_dp_enable_port().
 701          * We _must_ do this port enable + disable trick
 702          * to make this power sequencer lock onto the port.
 703          * Otherwise even VDD force bit won't work.
 704          */
 705         I915_WRITE(intel_dp->output_reg, DP);
 706         POSTING_READ(intel_dp->output_reg);
 707
 708         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 709         POSTING_READ(intel_dp->output_reg);
 710
 711         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 712         POSTING_READ(intel_dp->output_reg);
 713
 714         if (!pll_enabled) {
 715                 vlv_force_pll_off(dev_priv, pipe);
 716
 717                 if (release_cl_override)
 718                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 719         }
 720 }
 721
 722 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 723 {
 724         struct intel_encoder *encoder;
 725         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 726
 727         /*
 728          * We don't have power sequencer currently.
 729          * Pick one that's not used by other ports.
 730          */
 731         for_each_intel_dp(&dev_priv->drm, encoder) {
 732                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 733
 734                 if (encoder->type == INTEL_OUTPUT_EDP) {
 735                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 736                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 737
 738                         if (intel_dp->pps_pipe != INVALID_PIPE)
 739                                 pipes &= ~(1 << intel_dp->pps_pipe);
 740                 } else {
 741                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 742
 743                         if (intel_dp->active_pipe != INVALID_PIPE)
 744                                 pipes &= ~(1 << intel_dp->active_pipe);
 745                 }
 746         }
 747
 748         if (pipes == 0)
 749                 return INVALID_PIPE;
 750
 751         return ffs(pipes) - 1;
 752 }
 753
 754 static enum pipe
 755 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 756 {
 757         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 758         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 759         enum pipe pipe;
 760
 761         lockdep_assert_held(&dev_priv->pps_mutex);
 762
 763         /* We should never land here with regular DP ports */
 764         WARN_ON(!intel_dp_is_edp(intel_dp));
 765
 766         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 767                 intel_dp->active_pipe != intel_dp->pps_pipe);
 768
 769         if (intel_dp->pps_pipe != INVALID_PIPE)
 770                 return intel_dp->pps_pipe;
 771
 772         pipe = vlv_find_free_pps(dev_priv);
 773
 774         /*
 775          * Didn't find one. This should not happen since there
 776          * are two power sequencers and up to two eDP ports.
 777          */
 778         if (WARN_ON(pipe == INVALID_PIPE))
 779                 pipe = PIPE_A;
 780
 781         vlv_steal_power_sequencer(dev_priv, pipe);
 782         intel_dp->pps_pipe = pipe;
 783
 784         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 785                       pipe_name(intel_dp->pps_pipe),
 786                       port_name(intel_dig_port->base.port));
 787
 788         /* init power sequencer on this pipe and port */
 789         intel_dp_init_panel_power_sequencer(intel_dp);
 790         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 791
 792         /*
 793          * Even vdd force doesn't work until we've made
 794          * the power sequencer lock in on the port.
 795          */
 796         vlv_power_sequencer_kick(intel_dp);
 797
 798         return intel_dp->pps_pipe;
 799 }
 800
 801 static int
 802 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 803 {
 804         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 805         int backlight_controller = dev_priv->vbt.backlight.controller;
 806
 807         lockdep_assert_held(&dev_priv->pps_mutex);
 808
 809         /* We should never land here with regular DP ports */
 810         WARN_ON(!intel_dp_is_edp(intel_dp));
 811
 812         if (!intel_dp->pps_reset)
 813                 return backlight_controller;
 814
 815         intel_dp->pps_reset = false;
 816
 817         /*
 818          * Only the HW needs to be reprogrammed, the SW state is fixed and
 819          * has been setup during connector init.
 820          */
 821         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 822
 823         return backlight_controller;
 824 }
 825
 826 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 827                                enum pipe pipe);
 828
 829 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 830                                enum pipe pipe)
 831 {
 832         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 833 }
 834
 835 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 836                                 enum pipe pipe)
 837 {
 838         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 839 }
 840
 841 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 842                          enum pipe pipe)
 843 {
 844         return true;
 845 }
 846
 847 static enum pipe
 848 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 849                      enum port port,
 850                      vlv_pipe_check pipe_check)
 851 {
 852         enum pipe pipe;
 853
 854         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 855                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 856                         PANEL_PORT_SELECT_MASK;
 857
 858                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 859                         continue;
 860
 861                 if (!pipe_check(dev_priv, pipe))
 862                         continue;
 863
 864                 return pipe;
 865         }
 866
 867         return INVALID_PIPE;
 868 }
 869
 870 static void
 871 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 872 {
 873         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 874         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 875         enum port port = intel_dig_port->base.port;
 876
 877         lockdep_assert_held(&dev_priv->pps_mutex);
 878
 879         /* try to find a pipe with this port selected */
 880         /* first pick one where the panel is on */
 881         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 882                                                   vlv_pipe_has_pp_on);
 883         /* didn't find one? pick one where vdd is on */
 884         if (intel_dp->pps_pipe == INVALID_PIPE)
 885                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 886                                                           vlv_pipe_has_vdd_on);
 887         /* didn't find one? pick one with just the correct port */
 888         if (intel_dp->pps_pipe == INVALID_PIPE)
 889                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 890                                                           vlv_pipe_any);
 891
 892         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 893         if (intel_dp->pps_pipe == INVALID_PIPE) {
 894                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 895                               port_name(port));
 896                 return;
 897         }
 898
 899         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 900                       port_name(port), pipe_name(intel_dp->pps_pipe));
 901
 902         intel_dp_init_panel_power_sequencer(intel_dp);
 903         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 904 }
 905
 906 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 907 {
 908         struct intel_encoder *encoder;
 909
 910         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 911                     !IS_GEN9_LP(dev_priv)))
 912                 return;
 913
 914         /*
 915          * We can't grab pps_mutex here due to deadlock with power_domain
 916          * mutex when power_domain functions are called while holding pps_mutex.
 917          * That also means that in order to use pps_pipe the code needs to
 918          * hold both a power domain reference and pps_mutex, and the power domain
 919          * reference get/put must be done while _not_ holding pps_mutex.
 920          * pps_{lock,unlock}() do these steps in the correct order, so one
 921          * should use them always.
 922          */
 923
 924         for_each_intel_dp(&dev_priv->drm, encoder) {
 925                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 926
 927                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 928
 929                 if (encoder->type != INTEL_OUTPUT_EDP)
 930                         continue;
 931
 932                 if (IS_GEN9_LP(dev_priv))
 933                         intel_dp->pps_reset = true;
 934                 else
 935                         intel_dp->pps_pipe = INVALID_PIPE;
 936         }
 937 }
 938
 939 struct pps_registers {
 940         i915_reg_t pp_ctrl;
 941         i915_reg_t pp_stat;
 942         i915_reg_t pp_on;
 943         i915_reg_t pp_off;
 944         i915_reg_t pp_div;
 945 };
 946
 947 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 948                                     struct pps_registers *regs)
 949 {
 950         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 951         int pps_idx = 0;
 952
 953         memset(regs, 0, sizeof(*regs));
 954
 955         if (IS_GEN9_LP(dev_priv))
 956                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 957         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 958                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 959
 960         regs->pp_ctrl = PP_CONTROL(pps_idx);
 961         regs->pp_stat = PP_STATUS(pps_idx);
 962         regs->pp_on = PP_ON_DELAYS(pps_idx);
 963         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 964
 965         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
 966         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
 967                 regs->pp_div = INVALID_MMIO_REG;
 968         else
 969                 regs->pp_div = PP_DIVISOR(pps_idx);
 970 }
 971
 972 static i915_reg_t
 973 _pp_ctrl_reg(struct intel_dp *intel_dp)
 974 {
 975         struct pps_registers regs;
 976
 977         intel_pps_get_registers(intel_dp, &regs);
 978
 979         return regs.pp_ctrl;
 980 }
 981
 982 static i915_reg_t
 983 _pp_stat_reg(struct intel_dp *intel_dp)
 984 {
 985         struct pps_registers regs;
 986
 987         intel_pps_get_registers(intel_dp, &regs);
 988
 989         return regs.pp_stat;
 990 }
 991
 992 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 993    This function only applicable when panel PM state is not to be tracked */
 994 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 995                               void *unused)
 996 {
 997         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 998                                                  edp_notifier);
 999         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1000         intel_wakeref_t wakeref;
1001
1002         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1003                 return 0;
1004
1005         with_pps_lock(intel_dp, wakeref) {
1006                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1007                         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1008                         i915_reg_t pp_ctrl_reg, pp_div_reg;
1009                         u32 pp_div;
1010
1011                         pp_ctrl_reg = PP_CONTROL(pipe);
1012                         pp_div_reg  = PP_DIVISOR(pipe);
1013                         pp_div = I915_READ(pp_div_reg);
1014                         pp_div &= PP_REFERENCE_DIVIDER_MASK;
1015
1016                         /* 0x1F write to PP_DIV_REG sets max cycle delay */
1017                         I915_WRITE(pp_div_reg, pp_div | 0x1F);
1018                         I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS);
1019                         msleep(intel_dp->panel_power_cycle_delay);
1020                 }
1021         }
1022
1023         return 0;
1024 }
1025
1026 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1027 {
1028         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1029
1030         lockdep_assert_held(&dev_priv->pps_mutex);
1031
1032         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1033             intel_dp->pps_pipe == INVALID_PIPE)
1034                 return false;
1035
1036         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1037 }
1038
1039 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1040 {
1041         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1042
1043         lockdep_assert_held(&dev_priv->pps_mutex);
1044
1045         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1046             intel_dp->pps_pipe == INVALID_PIPE)
1047                 return false;
1048
1049         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1050 }
1051
1052 static void
1053 intel_dp_check_edp(struct intel_dp *intel_dp)
1054 {
1055         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1056
1057         if (!intel_dp_is_edp(intel_dp))
1058                 return;
1059
1060         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1061                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1062                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1063                               I915_READ(_pp_stat_reg(intel_dp)),
1064                               I915_READ(_pp_ctrl_reg(intel_dp)));
1065         }
1066 }
1067
1068 static u32
1069 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1070 {
1071         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1072         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1073         u32 status;
1074         bool done;
1075
1076 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1077         done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
1078                                   msecs_to_jiffies_timeout(10));
1079
1080         /* just trace the final value */
1081         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1082
1083         if (!done)
1084                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1085 #undef C
1086
1087         return status;
1088 }
1089
1090 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1091 {
1092         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1093
1094         if (index)
1095                 return 0;
1096
1097         /*
1098          * The clock divider is based off the hrawclk, and would like to run at
1099          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1100          */
1101         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1102 }
1103
1104 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1105 {
1106         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1107         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1108
1109         if (index)
1110                 return 0;
1111
1112         /*
1113          * The clock divider is based off the cdclk or PCH rawclk, and would
1114          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1115          * divide by 2000 and use that
1116          */
1117         if (dig_port->aux_ch == AUX_CH_A)
1118                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1119         else
1120                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1121 }
1122
1123 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1124 {
1125         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1126         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1127
1128         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1129                 /* Workaround for non-ULT HSW */
1130                 switch (index) {
1131                 case 0: return 63;
1132                 case 1: return 72;
1133                 default: return 0;
1134                 }
1135         }
1136
1137         return ilk_get_aux_clock_divider(intel_dp, index);
1138 }
1139
1140 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1141 {
1142         /*
1143          * SKL doesn't need us to program the AUX clock divider (Hardware will
1144          * derive the clock from CDCLK automatically). We still implement the
1145          * get_aux_clock_divider vfunc to plug-in into the existing code.
1146          */
1147         return index ? 0 : 1;
1148 }
1149
1150 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1151                                 int send_bytes,
1152                                 u32 aux_clock_divider)
1153 {
1154         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1155         struct drm_i915_private *dev_priv =
1156                         to_i915(intel_dig_port->base.base.dev);
1157         u32 precharge, timeout;
1158
1159         if (IS_GEN(dev_priv, 6))
1160                 precharge = 3;
1161         else
1162                 precharge = 5;
1163
1164         if (IS_BROADWELL(dev_priv))
1165                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1166         else
1167                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1168
1169         return DP_AUX_CH_CTL_SEND_BUSY |
1170                DP_AUX_CH_CTL_DONE |
1171                DP_AUX_CH_CTL_INTERRUPT |
1172                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1173                timeout |
1174                DP_AUX_CH_CTL_RECEIVE_ERROR |
1175                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1176                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1177                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1178 }
1179
1180 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1181                                 int send_bytes,
1182                                 u32 unused)
1183 {
1184         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1185         u32 ret;
1186
1187         ret = DP_AUX_CH_CTL_SEND_BUSY |
1188               DP_AUX_CH_CTL_DONE |
1189               DP_AUX_CH_CTL_INTERRUPT |
1190               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1191               DP_AUX_CH_CTL_TIME_OUT_MAX |
1192               DP_AUX_CH_CTL_RECEIVE_ERROR |
1193               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1194               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1195               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1196
1197         if (intel_dig_port->tc_type == TC_PORT_TBT)
1198                 ret |= DP_AUX_CH_CTL_TBT_IO;
1199
1200         return ret;
1201 }
1202
1203 static int
1204 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1205                   const u8 *send, int send_bytes,
1206                   u8 *recv, int recv_size,
1207                   u32 aux_send_ctl_flags)
1208 {
1209         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1210         struct drm_i915_private *dev_priv =
1211                         to_i915(intel_dig_port->base.base.dev);
1212         i915_reg_t ch_ctl, ch_data[5];
1213         u32 aux_clock_divider;
1214         intel_wakeref_t wakeref;
1215         int i, ret, recv_bytes;
1216         int try, clock = 0;
1217         u32 status;
1218         bool vdd;
1219
1220         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1221         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1222                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1223
1224         wakeref = pps_lock(intel_dp);
1225
1226         /*
1227          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1228          * In such cases we want to leave VDD enabled and it's up to upper layers
1229          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1230          * ourselves.
1231          */
1232         vdd = edp_panel_vdd_on(intel_dp);
1233
1234         /* dp aux is extremely sensitive to irq latency, hence request the
1235          * lowest possible wakeup latency and so prevent the cpu from going into
1236          * deep sleep states.
1237          */
1238         pm_qos_update_request(&dev_priv->pm_qos, 0);
1239
1240         intel_dp_check_edp(intel_dp);
1241
1242         /* Try to wait for any previous AUX channel activity */
1243         for (try = 0; try < 3; try++) {
1244                 status = I915_READ_NOTRACE(ch_ctl);
1245                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1246                         break;
1247                 msleep(1);
1248         }
1249         /* just trace the final value */
1250         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1251
1252         if (try == 3) {
1253                 static u32 last_status = -1;
1254                 const u32 status = I915_READ(ch_ctl);
1255
1256                 if (status != last_status) {
1257                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1258                              status);
1259                         last_status = status;
1260                 }
1261
1262                 ret = -EBUSY;
1263                 goto out;
1264         }
1265
1266         /* Only 5 data registers! */
1267         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1268                 ret = -E2BIG;
1269                 goto out;
1270         }
1271
1272         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1273                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1274                                                           send_bytes,
1275                                                           aux_clock_divider);
1276
1277                 send_ctl |= aux_send_ctl_flags;
1278
1279                 /* Must try at least 3 times according to DP spec */
1280                 for (try = 0; try < 5; try++) {
1281                         /* Load the send data into the aux channel data registers */
1282                         for (i = 0; i < send_bytes; i += 4)
1283                                 I915_WRITE(ch_data[i >> 2],
1284                                            intel_dp_pack_aux(send + i,
1285                                                              send_bytes - i));
1286
1287                         /* Send the command and wait for it to complete */
1288                         I915_WRITE(ch_ctl, send_ctl);
1289
1290                         status = intel_dp_aux_wait_done(intel_dp);
1291
1292                         /* Clear done status and any errors */
1293                         I915_WRITE(ch_ctl,
1294                                    status |
1295                                    DP_AUX_CH_CTL_DONE |
1296                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1297                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1298
1299                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1300                          *   400us delay required for errors and timeouts
1301                          *   Timeout errors from the HW already meet this
1302                          *   requirement so skip to next iteration
1303                          */
1304                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1305                                 continue;
1306
1307                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1308                                 usleep_range(400, 500);
1309                                 continue;
1310                         }
1311                         if (status & DP_AUX_CH_CTL_DONE)
1312                                 goto done;
1313                 }
1314         }
1315
1316         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1317                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1318                 ret = -EBUSY;
1319                 goto out;
1320         }
1321
1322 done:
1323         /* Check for timeout or receive error.
1324          * Timeouts occur when the sink is not connected
1325          */
1326         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1327                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1328                 ret = -EIO;
1329                 goto out;
1330         }
1331
1332         /* Timeouts occur when the device isn't connected, so they're
1333          * "normal" -- don't fill the kernel log with these */
1334         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1335                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1336                 ret = -ETIMEDOUT;
1337                 goto out;
1338         }
1339
1340         /* Unload any bytes sent back from the other side */
1341         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1342                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1343
1344         /*
1345          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1346          * We have no idea of what happened so we return -EBUSY so
1347          * drm layer takes care for the necessary retries.
1348          */
1349         if (recv_bytes == 0 || recv_bytes > 20) {
1350                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1351                               recv_bytes);
1352                 ret = -EBUSY;
1353                 goto out;
1354         }
1355
1356         if (recv_bytes > recv_size)
1357                 recv_bytes = recv_size;
1358
1359         for (i = 0; i < recv_bytes; i += 4)
1360                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1361                                     recv + i, recv_bytes - i);
1362
1363         ret = recv_bytes;
1364 out:
1365         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1366
1367         if (vdd)
1368                 edp_panel_vdd_off(intel_dp, false);
1369
1370         pps_unlock(intel_dp, wakeref);
1371
1372         return ret;
1373 }
1374
1375 #define BARE_ADDRESS_SIZE       3
1376 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1377
1378 static void
1379 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1380                     const struct drm_dp_aux_msg *msg)
1381 {
1382         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1383         txbuf[1] = (msg->address >> 8) & 0xff;
1384         txbuf[2] = msg->address & 0xff;
1385         txbuf[3] = msg->size - 1;
1386 }
1387
1388 static ssize_t
1389 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1390 {
1391         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1392         u8 txbuf[20], rxbuf[20];
1393         size_t txsize, rxsize;
1394         int ret;
1395
1396         intel_dp_aux_header(txbuf, msg);
1397
1398         switch (msg->request & ~DP_AUX_I2C_MOT) {
1399         case DP_AUX_NATIVE_WRITE:
1400         case DP_AUX_I2C_WRITE:
1401         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1402                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1403                 rxsize = 2; /* 0 or 1 data bytes */
1404
1405                 if (WARN_ON(txsize > 20))
1406                         return -E2BIG;
1407
1408                 WARN_ON(!msg->buffer != !msg->size);
1409
1410                 if (msg->buffer)
1411                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1412
1413                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1414                                         rxbuf, rxsize, 0);
1415                 if (ret > 0) {
1416                         msg->reply = rxbuf[0] >> 4;
1417
1418                         if (ret > 1) {
1419                                 /* Number of bytes written in a short write. */
1420                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1421                         } else {
1422                                 /* Return payload size. */
1423                                 ret = msg->size;
1424                         }
1425                 }
1426                 break;
1427
1428         case DP_AUX_NATIVE_READ:
1429         case DP_AUX_I2C_READ:
1430                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1431                 rxsize = msg->size + 1;
1432
1433                 if (WARN_ON(rxsize > 20))
1434                         return -E2BIG;
1435
1436                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1437                                         rxbuf, rxsize, 0);
1438                 if (ret > 0) {
1439                         msg->reply = rxbuf[0] >> 4;
1440                         /*
1441                          * Assume happy day, and copy the data. The caller is
1442                          * expected to check msg->reply before touching it.
1443                          *
1444                          * Return payload size.
1445                          */
1446                         ret--;
1447                         memcpy(msg->buffer, rxbuf + 1, ret);
1448                 }
1449                 break;
1450
1451         default:
1452                 ret = -EINVAL;
1453                 break;
1454         }
1455
1456         return ret;
1457 }
1458
1459
1460 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1461 {
1462         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1463         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1464         enum aux_ch aux_ch = dig_port->aux_ch;
1465
1466         switch (aux_ch) {
1467         case AUX_CH_B:
1468         case AUX_CH_C:
1469         case AUX_CH_D:
1470                 return DP_AUX_CH_CTL(aux_ch);
1471         default:
1472                 MISSING_CASE(aux_ch);
1473                 return DP_AUX_CH_CTL(AUX_CH_B);
1474         }
1475 }
1476
1477 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1478 {
1479         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1480         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1481         enum aux_ch aux_ch = dig_port->aux_ch;
1482
1483         switch (aux_ch) {
1484         case AUX_CH_B:
1485         case AUX_CH_C:
1486         case AUX_CH_D:
1487                 return DP_AUX_CH_DATA(aux_ch, index);
1488         default:
1489                 MISSING_CASE(aux_ch);
1490                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1491         }
1492 }
1493
1494 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1495 {
1496         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1497         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1498         enum aux_ch aux_ch = dig_port->aux_ch;
1499
1500         switch (aux_ch) {
1501         case AUX_CH_A:
1502                 return DP_AUX_CH_CTL(aux_ch);
1503         case AUX_CH_B:
1504         case AUX_CH_C:
1505         case AUX_CH_D:
1506                 return PCH_DP_AUX_CH_CTL(aux_ch);
1507         default:
1508                 MISSING_CASE(aux_ch);
1509                 return DP_AUX_CH_CTL(AUX_CH_A);
1510         }
1511 }
1512
1513 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1514 {
1515         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1516         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1517         enum aux_ch aux_ch = dig_port->aux_ch;
1518
1519         switch (aux_ch) {
1520         case AUX_CH_A:
1521                 return DP_AUX_CH_DATA(aux_ch, index);
1522         case AUX_CH_B:
1523         case AUX_CH_C:
1524         case AUX_CH_D:
1525                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1526         default:
1527                 MISSING_CASE(aux_ch);
1528                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1529         }
1530 }
1531
1532 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1533 {
1534         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1535         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1536         enum aux_ch aux_ch = dig_port->aux_ch;
1537
1538         switch (aux_ch) {
1539         case AUX_CH_A:
1540         case AUX_CH_B:
1541         case AUX_CH_C:
1542         case AUX_CH_D:
1543         case AUX_CH_E:
1544         case AUX_CH_F:
1545                 return DP_AUX_CH_CTL(aux_ch);
1546         default:
1547                 MISSING_CASE(aux_ch);
1548                 return DP_AUX_CH_CTL(AUX_CH_A);
1549         }
1550 }
1551
1552 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1553 {
1554         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1555         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1556         enum aux_ch aux_ch = dig_port->aux_ch;
1557
1558         switch (aux_ch) {
1559         case AUX_CH_A:
1560         case AUX_CH_B:
1561         case AUX_CH_C:
1562         case AUX_CH_D:
1563         case AUX_CH_E:
1564         case AUX_CH_F:
1565                 return DP_AUX_CH_DATA(aux_ch, index);
1566         default:
1567                 MISSING_CASE(aux_ch);
1568                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1569         }
1570 }
1571
1572 static void
1573 intel_dp_aux_fini(struct intel_dp *intel_dp)
1574 {
1575         kfree(intel_dp->aux.name);
1576 }
1577
1578 static void
1579 intel_dp_aux_init(struct intel_dp *intel_dp)
1580 {
1581         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1582         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1583         struct intel_encoder *encoder = &dig_port->base;
1584
1585         if (INTEL_GEN(dev_priv) >= 9) {
1586                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1587                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1588         } else if (HAS_PCH_SPLIT(dev_priv)) {
1589                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1590                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1591         } else {
1592                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1593                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1594         }
1595
1596         if (INTEL_GEN(dev_priv) >= 9)
1597                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1598         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1599                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1600         else if (HAS_PCH_SPLIT(dev_priv))
1601                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1602         else
1603                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1604
1605         if (INTEL_GEN(dev_priv) >= 9)
1606                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1607         else
1608                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1609
1610         drm_dp_aux_init(&intel_dp->aux);
1611
1612         /* Failure to allocate our preferred name is not critical */
1613         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1614                                        port_name(encoder->port));
1615         intel_dp->aux.transfer = intel_dp_aux_transfer;
1616 }
1617
1618 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1619 {
1620         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1621
1622         return max_rate >= 540000;
1623 }
1624
1625 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1626 {
1627         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1628
1629         return max_rate >= 810000;
1630 }
1631
1632 static void
1633 intel_dp_set_clock(struct intel_encoder *encoder,
1634                    struct intel_crtc_state *pipe_config)
1635 {
1636         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1637         const struct dp_link_dpll *divisor = NULL;
1638         int i, count = 0;
1639
1640         if (IS_G4X(dev_priv)) {
1641                 divisor = g4x_dpll;
1642                 count = ARRAY_SIZE(g4x_dpll);
1643         } else if (HAS_PCH_SPLIT(dev_priv)) {
1644                 divisor = pch_dpll;
1645                 count = ARRAY_SIZE(pch_dpll);
1646         } else if (IS_CHERRYVIEW(dev_priv)) {
1647                 divisor = chv_dpll;
1648                 count = ARRAY_SIZE(chv_dpll);
1649         } else if (IS_VALLEYVIEW(dev_priv)) {
1650                 divisor = vlv_dpll;
1651                 count = ARRAY_SIZE(vlv_dpll);
1652         }
1653
1654         if (divisor && count) {
1655                 for (i = 0; i < count; i++) {
1656                         if (pipe_config->port_clock == divisor[i].clock) {
1657                                 pipe_config->dpll = divisor[i].dpll;
1658                                 pipe_config->clock_set = true;
1659                                 break;
1660                         }
1661                 }
1662         }
1663 }
1664
1665 static void snprintf_int_array(char *str, size_t len,
1666                                const int *array, int nelem)
1667 {
1668         int i;
1669
1670         str[0] = '\0';
1671
1672         for (i = 0; i < nelem; i++) {
1673                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1674                 if (r >= len)
1675                         return;
1676                 str += r;
1677                 len -= r;
1678         }
1679 }
1680
1681 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1682 {
1683         char str[128]; /* FIXME: too big for stack? */
1684
1685         if ((drm_debug & DRM_UT_KMS) == 0)
1686                 return;
1687
1688         snprintf_int_array(str, sizeof(str),
1689                            intel_dp->source_rates, intel_dp->num_source_rates);
1690         DRM_DEBUG_KMS("source rates: %s\n", str);
1691
1692         snprintf_int_array(str, sizeof(str),
1693                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1694         DRM_DEBUG_KMS("sink rates: %s\n", str);
1695
1696         snprintf_int_array(str, sizeof(str),
1697                            intel_dp->common_rates, intel_dp->num_common_rates);
1698         DRM_DEBUG_KMS("common rates: %s\n", str);
1699 }
1700
1701 int
1702 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1703 {
1704         int len;
1705
1706         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1707         if (WARN_ON(len <= 0))
1708                 return 162000;
1709
1710         return intel_dp->common_rates[len - 1];
1711 }
1712
1713 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1714 {
1715         int i = intel_dp_rate_index(intel_dp->sink_rates,
1716                                     intel_dp->num_sink_rates, rate);
1717
1718         if (WARN_ON(i < 0))
1719                 i = 0;
1720
1721         return i;
1722 }
1723
1724 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1725                            u8 *link_bw, u8 *rate_select)
1726 {
1727         /* eDP 1.4 rate select method. */
1728         if (intel_dp->use_rate_select) {
1729                 *link_bw = 0;
1730                 *rate_select =
1731                         intel_dp_rate_select(intel_dp, port_clock);
1732         } else {
1733                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1734                 *rate_select = 0;
1735         }
1736 }
1737
1738 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1739                                          const struct intel_crtc_state *pipe_config)
1740 {
1741         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1742
1743         return INTEL_GEN(dev_priv) >= 11 &&
1744                 pipe_config->cpu_transcoder != TRANSCODER_A;
1745 }
1746
1747 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1748                                   const struct intel_crtc_state *pipe_config)
1749 {
1750         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1751                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1752 }
1753
1754 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1755                                          const struct intel_crtc_state *pipe_config)
1756 {
1757         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1758
1759         return INTEL_GEN(dev_priv) >= 10 &&
1760                 pipe_config->cpu_transcoder != TRANSCODER_A;
1761 }
1762
1763 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1764                                   const struct intel_crtc_state *pipe_config)
1765 {
1766         if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1767                 return false;
1768
1769         return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1770                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1771 }
1772
1773 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1774                                 struct intel_crtc_state *pipe_config)
1775 {
1776         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1777         struct intel_connector *intel_connector = intel_dp->attached_connector;
1778         int bpp, bpc;
1779
1780         bpp = pipe_config->pipe_bpp;
1781         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1782
1783         if (bpc > 0)
1784                 bpp = min(bpp, 3*bpc);
1785
1786         if (intel_dp_is_edp(intel_dp)) {
1787                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1788                 if (intel_connector->base.display_info.bpc == 0 &&
1789                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1790                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1791                                       dev_priv->vbt.edp.bpp);
1792                         bpp = dev_priv->vbt.edp.bpp;
1793                 }
1794         }
1795
1796         return bpp;
1797 }
1798
1799 /* Adjust link config limits based on compliance test requests. */
1800 void
1801 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1802                                   struct intel_crtc_state *pipe_config,
1803                                   struct link_config_limits *limits)
1804 {
1805         /* For DP Compliance we override the computed bpp for the pipe */
1806         if (intel_dp->compliance.test_data.bpc != 0) {
1807                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1808
1809                 limits->min_bpp = limits->max_bpp = bpp;
1810                 pipe_config->dither_force_disable = bpp == 6 * 3;
1811
1812                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1813         }
1814
1815         /* Use values requested by Compliance Test Request */
1816         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1817                 int index;
1818
1819                 /* Validate the compliance test data since max values
1820                  * might have changed due to link train fallback.
1821                  */
1822                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1823                                                intel_dp->compliance.test_lane_count)) {
1824                         index = intel_dp_rate_index(intel_dp->common_rates,
1825                                                     intel_dp->num_common_rates,
1826                                                     intel_dp->compliance.test_link_rate);
1827                         if (index >= 0)
1828                                 limits->min_clock = limits->max_clock = index;
1829                         limits->min_lane_count = limits->max_lane_count =
1830                                 intel_dp->compliance.test_lane_count;
1831                 }
1832         }
1833 }
1834
1835 /* Optimize link config in order: max bpp, min clock, min lanes */
1836 static int
1837 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1838                                   struct intel_crtc_state *pipe_config,
1839                                   const struct link_config_limits *limits)
1840 {
1841         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1842         int bpp, clock, lane_count;
1843         int mode_rate, link_clock, link_avail;
1844
1845         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1846                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1847                                                    bpp);
1848
1849                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1850                         for (lane_count = limits->min_lane_count;
1851                              lane_count <= limits->max_lane_count;
1852                              lane_count <<= 1) {
1853                                 link_clock = intel_dp->common_rates[clock];
1854                                 link_avail = intel_dp_max_data_rate(link_clock,
1855                                                                     lane_count);
1856
1857                                 if (mode_rate <= link_avail) {
1858                                         pipe_config->lane_count = lane_count;
1859                                         pipe_config->pipe_bpp = bpp;
1860                                         pipe_config->port_clock = link_clock;
1861
1862                                         return 0;
1863                                 }
1864                         }
1865                 }
1866         }
1867
1868         return -EINVAL;
1869 }
1870
1871 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1872 {
1873         int i, num_bpc;
1874         u8 dsc_bpc[3] = {0};
1875
1876         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1877                                                        dsc_bpc);
1878         for (i = 0; i < num_bpc; i++) {
1879                 if (dsc_max_bpc >= dsc_bpc[i])
1880                         return dsc_bpc[i] * 3;
1881         }
1882
1883         return 0;
1884 }
1885
1886 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1887                                        struct intel_crtc_state *pipe_config,
1888                                        struct drm_connector_state *conn_state,
1889                                        struct link_config_limits *limits)
1890 {
1891         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1892         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1893         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1894         u8 dsc_max_bpc;
1895         int pipe_bpp;
1896         int ret;
1897
1898         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
1899                 intel_dp_supports_fec(intel_dp, pipe_config);
1900
1901         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1902                 return -EINVAL;
1903
1904         dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
1905                             conn_state->max_requested_bpc);
1906
1907         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1908         if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
1909                 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
1910                 return -EINVAL;
1911         }
1912
1913         /*
1914          * For now enable DSC for max bpp, max link rate, max lane count.
1915          * Optimize this later for the minimum possible link rate/lane count
1916          * with DSC enabled for the requested mode.
1917          */
1918         pipe_config->pipe_bpp = pipe_bpp;
1919         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1920         pipe_config->lane_count = limits->max_lane_count;
1921
1922         if (intel_dp_is_edp(intel_dp)) {
1923                 pipe_config->dsc_params.compressed_bpp =
1924                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1925                               pipe_config->pipe_bpp);
1926                 pipe_config->dsc_params.slice_count =
1927                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1928                                                         true);
1929         } else {
1930                 u16 dsc_max_output_bpp;
1931                 u8 dsc_dp_slice_count;
1932
1933                 dsc_max_output_bpp =
1934                         intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
1935                                                     pipe_config->lane_count,
1936                                                     adjusted_mode->crtc_clock,
1937                                                     adjusted_mode->crtc_hdisplay);
1938                 dsc_dp_slice_count =
1939                         intel_dp_dsc_get_slice_count(intel_dp,
1940                                                      adjusted_mode->crtc_clock,
1941                                                      adjusted_mode->crtc_hdisplay);
1942                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1943                         DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
1944                         return -EINVAL;
1945                 }
1946                 pipe_config->dsc_params.compressed_bpp = min_t(u16,
1947                                                                dsc_max_output_bpp >> 4,
1948                                                                pipe_config->pipe_bpp);
1949                 pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
1950         }
1951         /*
1952          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1953          * is greater than the maximum Cdclock and if slice count is even
1954          * then we need to use 2 VDSC instances.
1955          */
1956         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
1957                 if (pipe_config->dsc_params.slice_count > 1) {
1958                         pipe_config->dsc_params.dsc_split = true;
1959                 } else {
1960                         DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
1961                         return -EINVAL;
1962                 }
1963         }
1964
1965         ret = intel_dp_compute_dsc_params(intel_dp, pipe_config);
1966         if (ret < 0) {
1967                 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
1968                               "Compressed BPP = %d\n",
1969                               pipe_config->pipe_bpp,
1970                               pipe_config->dsc_params.compressed_bpp);
1971                 return ret;
1972         }
1973
1974         pipe_config->dsc_params.compression_enable = true;
1975         DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
1976                       "Compressed Bpp = %d Slice Count = %d\n",
1977                       pipe_config->pipe_bpp,
1978                       pipe_config->dsc_params.compressed_bpp,
1979                       pipe_config->dsc_params.slice_count);
1980
1981         return 0;
1982 }
1983
1984 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
1985 {
1986         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
1987                 return 6 * 3;
1988         else
1989                 return 8 * 3;
1990 }
1991
1992 static int
1993 intel_dp_compute_link_config(struct intel_encoder *encoder,
1994                              struct intel_crtc_state *pipe_config,
1995                              struct drm_connector_state *conn_state)
1996 {
1997         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1998         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1999         struct link_config_limits limits;
2000         int common_len;
2001         int ret;
2002
2003         common_len = intel_dp_common_len_rate_limit(intel_dp,
2004                                                     intel_dp->max_link_rate);
2005
2006         /* No common link rates between source and sink */
2007         WARN_ON(common_len <= 0);
2008
2009         limits.min_clock = 0;
2010         limits.max_clock = common_len - 1;
2011
2012         limits.min_lane_count = 1;
2013         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2014
2015         limits.min_bpp = intel_dp_min_bpp(pipe_config);
2016         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2017
2018         if (intel_dp_is_edp(intel_dp)) {
2019                 /*
2020                  * Use the maximum clock and number of lanes the eDP panel
2021                  * advertizes being capable of. The panels are generally
2022                  * designed to support only a single clock and lane
2023                  * configuration, and typically these values correspond to the
2024                  * native resolution of the panel.
2025                  */
2026                 limits.min_lane_count = limits.max_lane_count;
2027                 limits.min_clock = limits.max_clock;
2028         }
2029
2030         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2031
2032         DRM_DEBUG_KMS("DP link computation with max lane count %i "
2033                       "max rate %d max bpp %d pixel clock %iKHz\n",
2034                       limits.max_lane_count,
2035                       intel_dp->common_rates[limits.max_clock],
2036                       limits.max_bpp, adjusted_mode->crtc_clock);
2037
2038         /*
2039          * Optimize for slow and wide. This is the place to add alternative
2040          * optimization policy.
2041          */
2042         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2043
2044         /* enable compression if the mode doesn't fit available BW */
2045         DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
2046         if (ret || intel_dp->force_dsc_en) {
2047                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2048                                                   conn_state, &limits);
2049                 if (ret < 0)
2050                         return ret;
2051         }
2052
2053         if (pipe_config->dsc_params.compression_enable) {
2054                 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2055                               pipe_config->lane_count, pipe_config->port_clock,
2056                               pipe_config->pipe_bpp,
2057                               pipe_config->dsc_params.compressed_bpp);
2058
2059                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2060                               intel_dp_link_required(adjusted_mode->crtc_clock,
2061                                                      pipe_config->dsc_params.compressed_bpp),
2062                               intel_dp_max_data_rate(pipe_config->port_clock,
2063                                                      pipe_config->lane_count));
2064         } else {
2065                 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2066                               pipe_config->lane_count, pipe_config->port_clock,
2067                               pipe_config->pipe_bpp);
2068
2069                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2070                               intel_dp_link_required(adjusted_mode->crtc_clock,
2071                                                      pipe_config->pipe_bpp),
2072                               intel_dp_max_data_rate(pipe_config->port_clock,
2073                                                      pipe_config->lane_count));
2074         }
2075         return 0;
2076 }
2077
2078 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2079                                   const struct drm_connector_state *conn_state)
2080 {
2081         const struct intel_digital_connector_state *intel_conn_state =
2082                 to_intel_digital_connector_state(conn_state);
2083         const struct drm_display_mode *adjusted_mode =
2084                 &crtc_state->base.adjusted_mode;
2085
2086         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2087                 /*
2088                  * See:
2089                  * CEA-861-E - 5.1 Default Encoding Parameters
2090                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2091                  */
2092                 return crtc_state->pipe_bpp != 18 &&
2093                         drm_default_rgb_quant_range(adjusted_mode) ==
2094                         HDMI_QUANTIZATION_RANGE_LIMITED;
2095         } else {
2096                 return intel_conn_state->broadcast_rgb ==
2097                         INTEL_BROADCAST_RGB_LIMITED;
2098         }
2099 }
2100
2101 int
2102 intel_dp_compute_config(struct intel_encoder *encoder,
2103                         struct intel_crtc_state *pipe_config,
2104                         struct drm_connector_state *conn_state)
2105 {
2106         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2107         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2108         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2109         struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2110         enum port port = encoder->port;
2111         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2112         struct intel_connector *intel_connector = intel_dp->attached_connector;
2113         struct intel_digital_connector_state *intel_conn_state =
2114                 to_intel_digital_connector_state(conn_state);
2115         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2116                                            DP_DPCD_QUIRK_CONSTANT_N);
2117         int ret, output_bpp;
2118
2119         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2120                 pipe_config->has_pch_encoder = true;
2121
2122         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2123         if (lspcon->active)
2124                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2125
2126         pipe_config->has_drrs = false;
2127         if (IS_G4X(dev_priv) || port == PORT_A)
2128                 pipe_config->has_audio = false;
2129         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2130                 pipe_config->has_audio = intel_dp->has_audio;
2131         else
2132                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2133
2134         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2135                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2136                                        adjusted_mode);
2137
2138                 if (INTEL_GEN(dev_priv) >= 9) {
2139                         ret = skl_update_scaler_crtc(pipe_config);
2140                         if (ret)
2141                                 return ret;
2142                 }
2143
2144                 if (HAS_GMCH(dev_priv))
2145                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2146                                                  conn_state->scaling_mode);
2147                 else
2148                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2149                                                 conn_state->scaling_mode);
2150         }
2151
2152         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2153                 return -EINVAL;
2154
2155         if (HAS_GMCH(dev_priv) &&
2156             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2157                 return -EINVAL;
2158
2159         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2160                 return -EINVAL;
2161
2162         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2163         if (ret < 0)
2164                 return ret;
2165
2166         pipe_config->limited_color_range =
2167                 intel_dp_limited_color_range(pipe_config, conn_state);
2168
2169         if (pipe_config->dsc_params.compression_enable)
2170                 output_bpp = pipe_config->dsc_params.compressed_bpp;
2171         else
2172                 output_bpp = pipe_config->pipe_bpp;
2173
2174         intel_link_compute_m_n(output_bpp,
2175                                pipe_config->lane_count,
2176                                adjusted_mode->crtc_clock,
2177                                pipe_config->port_clock,
2178                                &pipe_config->dp_m_n,
2179                                constant_n);
2180
2181         if (intel_connector->panel.downclock_mode != NULL &&
2182                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2183                         pipe_config->has_drrs = true;
2184                         intel_link_compute_m_n(output_bpp,
2185                                                pipe_config->lane_count,
2186                                                intel_connector->panel.downclock_mode->clock,
2187                                                pipe_config->port_clock,
2188                                                &pipe_config->dp_m2_n2,
2189                                                constant_n);
2190         }
2191
2192         if (!HAS_DDI(dev_priv))
2193                 intel_dp_set_clock(encoder, pipe_config);
2194
2195         intel_psr_compute_config(intel_dp, pipe_config);
2196
2197         return 0;
2198 }
2199
2200 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2201                               int link_rate, u8 lane_count,
2202                               bool link_mst)
2203 {
2204         intel_dp->link_trained = false;
2205         intel_dp->link_rate = link_rate;
2206         intel_dp->lane_count = lane_count;
2207         intel_dp->link_mst = link_mst;
2208 }
2209
2210 static void intel_dp_prepare(struct intel_encoder *encoder,
2211                              const struct intel_crtc_state *pipe_config)
2212 {
2213         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2214         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2215         enum port port = encoder->port;
2216         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2217         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2218
2219         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2220                                  pipe_config->lane_count,
2221                                  intel_crtc_has_type(pipe_config,
2222                                                      INTEL_OUTPUT_DP_MST));
2223
2224         /*
2225          * There are four kinds of DP registers:
2226          *
2227          *      IBX PCH
2228          *      SNB CPU
2229          *      IVB CPU
2230          *      CPT PCH
2231          *
2232          * IBX PCH and CPU are the same for almost everything,
2233          * except that the CPU DP PLL is configured in this
2234          * register
2235          *
2236          * CPT PCH is quite different, having many bits moved
2237          * to the TRANS_DP_CTL register instead. That
2238          * configuration happens (oddly) in ironlake_pch_enable
2239          */
2240
2241         /* Preserve the BIOS-computed detected bit. This is
2242          * supposed to be read-only.
2243          */
2244         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2245
2246         /* Handle DP bits in common between all three register formats */
2247         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2248         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2249
2250         /* Split out the IBX/CPU vs CPT settings */
2251
2252         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2253                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2254                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2255                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2256                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2257                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2258
2259                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2260                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2261
2262                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2263         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2264                 u32 trans_dp;
2265
2266                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2267
2268                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2269                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2270                         trans_dp |= TRANS_DP_ENH_FRAMING;
2271                 else
2272                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2273                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2274         } else {
2275                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2276                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2277
2278                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2279                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2280                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2281                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2282                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2283
2284                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2285                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2286
2287                 if (IS_CHERRYVIEW(dev_priv))
2288                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2289                 else
2290                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2291         }
2292 }
2293
2294 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2295 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2296
2297 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2298 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2299
2300 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2301 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2302
2303 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2304
2305 static void wait_panel_status(struct intel_dp *intel_dp,
2306                                        u32 mask,
2307                                        u32 value)
2308 {
2309         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2310         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2311
2312         lockdep_assert_held(&dev_priv->pps_mutex);
2313
2314         intel_pps_verify_state(intel_dp);
2315
2316         pp_stat_reg = _pp_stat_reg(intel_dp);
2317         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2318
2319         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2320                         mask, value,
2321                         I915_READ(pp_stat_reg),
2322                         I915_READ(pp_ctrl_reg));
2323
2324         if (intel_wait_for_register(&dev_priv->uncore,
2325                                     pp_stat_reg, mask, value,
2326                                     5000))
2327                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2328                                 I915_READ(pp_stat_reg),
2329                                 I915_READ(pp_ctrl_reg));
2330
2331         DRM_DEBUG_KMS("Wait complete\n");
2332 }
2333
2334 static void wait_panel_on(struct intel_dp *intel_dp)
2335 {
2336         DRM_DEBUG_KMS("Wait for panel power on\n");
2337         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2338 }
2339
2340 static void wait_panel_off(struct intel_dp *intel_dp)
2341 {
2342         DRM_DEBUG_KMS("Wait for panel power off time\n");
2343         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2344 }
2345
2346 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2347 {
2348         ktime_t panel_power_on_time;
2349         s64 panel_power_off_duration;
2350
2351         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2352
2353         /* take the difference of currrent time and panel power off time
2354          * and then make panel wait for t11_t12 if needed. */
2355         panel_power_on_time = ktime_get_boottime();
2356         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2357
2358         /* When we disable the VDD override bit last we have to do the manual
2359          * wait. */
2360         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2361                 wait_remaining_ms_from_jiffies(jiffies,
2362                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2363
2364         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2365 }
2366
2367 static void wait_backlight_on(struct intel_dp *intel_dp)
2368 {
2369         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2370                                        intel_dp->backlight_on_delay);
2371 }
2372
2373 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2374 {
2375         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2376                                        intel_dp->backlight_off_delay);
2377 }
2378
2379 /* Read the current pp_control value, unlocking the register if it
2380  * is locked
2381  */
2382
2383 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2384 {
2385         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2386         u32 control;
2387
2388         lockdep_assert_held(&dev_priv->pps_mutex);
2389
2390         control = I915_READ(_pp_ctrl_reg(intel_dp));
2391         if (WARN_ON(!HAS_DDI(dev_priv) &&
2392                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2393                 control &= ~PANEL_UNLOCK_MASK;
2394                 control |= PANEL_UNLOCK_REGS;
2395         }
2396         return control;
2397 }
2398
2399 /*
2400  * Must be paired with edp_panel_vdd_off().
2401  * Must hold pps_mutex around the whole on/off sequence.
2402  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2403  */
2404 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2405 {
2406         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2407         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2408         u32 pp;
2409         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2410         bool need_to_disable = !intel_dp->want_panel_vdd;
2411
2412         lockdep_assert_held(&dev_priv->pps_mutex);
2413
2414         if (!intel_dp_is_edp(intel_dp))
2415                 return false;
2416
2417         cancel_delayed_work(&intel_dp->panel_vdd_work);
2418         intel_dp->want_panel_vdd = true;
2419
2420         if (edp_have_panel_vdd(intel_dp))
2421                 return need_to_disable;
2422
2423         intel_display_power_get(dev_priv,
2424                                 intel_aux_power_domain(intel_dig_port));
2425
2426         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2427                       port_name(intel_dig_port->base.port));
2428
2429         if (!edp_have_panel_power(intel_dp))
2430                 wait_panel_power_cycle(intel_dp);
2431
2432         pp = ironlake_get_pp_control(intel_dp);
2433         pp |= EDP_FORCE_VDD;
2434
2435         pp_stat_reg = _pp_stat_reg(intel_dp);
2436         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2437
2438         I915_WRITE(pp_ctrl_reg, pp);
2439         POSTING_READ(pp_ctrl_reg);
2440         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2441                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2442         /*
2443          * If the panel wasn't on, delay before accessing aux channel
2444          */
2445         if (!edp_have_panel_power(intel_dp)) {
2446                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2447                               port_name(intel_dig_port->base.port));
2448                 msleep(intel_dp->panel_power_up_delay);
2449         }
2450
2451         return need_to_disable;
2452 }
2453
2454 /*
2455  * Must be paired with intel_edp_panel_vdd_off() or
2456  * intel_edp_panel_off().
2457  * Nested calls to these functions are not allowed since
2458  * we drop the lock. Caller must use some higher level
2459  * locking to prevent nested calls from other threads.
2460  */
2461 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2462 {
2463         intel_wakeref_t wakeref;
2464         bool vdd;
2465
2466         if (!intel_dp_is_edp(intel_dp))
2467                 return;
2468
2469         vdd = false;
2470         with_pps_lock(intel_dp, wakeref)
2471                 vdd = edp_panel_vdd_on(intel_dp);
2472         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2473              port_name(dp_to_dig_port(intel_dp)->base.port));
2474 }
2475
2476 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2477 {
2478         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2479         struct intel_digital_port *intel_dig_port =
2480                 dp_to_dig_port(intel_dp);
2481         u32 pp;
2482         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2483
2484         lockdep_assert_held(&dev_priv->pps_mutex);
2485
2486         WARN_ON(intel_dp->want_panel_vdd);
2487
2488         if (!edp_have_panel_vdd(intel_dp))
2489                 return;
2490
2491         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2492                       port_name(intel_dig_port->base.port));
2493
2494         pp = ironlake_get_pp_control(intel_dp);
2495         pp &= ~EDP_FORCE_VDD;
2496
2497         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2498         pp_stat_reg = _pp_stat_reg(intel_dp);
2499
2500         I915_WRITE(pp_ctrl_reg, pp);
2501         POSTING_READ(pp_ctrl_reg);
2502
2503         /* Make sure sequencer is idle before allowing subsequent activity */
2504         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2505         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2506
2507         if ((pp & PANEL_POWER_ON) == 0)
2508                 intel_dp->panel_power_off_time = ktime_get_boottime();
2509
2510         intel_display_power_put_unchecked(dev_priv,
2511                                           intel_aux_power_domain(intel_dig_port));
2512 }
2513
2514 static void edp_panel_vdd_work(struct work_struct *__work)
2515 {
2516         struct intel_dp *intel_dp =
2517                 container_of(to_delayed_work(__work),
2518                              struct intel_dp, panel_vdd_work);
2519         intel_wakeref_t wakeref;
2520
2521         with_pps_lock(intel_dp, wakeref) {
2522                 if (!intel_dp->want_panel_vdd)
2523                         edp_panel_vdd_off_sync(intel_dp);
2524         }
2525 }
2526
2527 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2528 {
2529         unsigned long delay;
2530
2531         /*
2532          * Queue the timer to fire a long time from now (relative to the power
2533          * down delay) to keep the panel power up across a sequence of
2534          * operations.
2535          */
2536         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2537         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2538 }
2539
2540 /*
2541  * Must be paired with edp_panel_vdd_on().
2542  * Must hold pps_mutex around the whole on/off sequence.
2543  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2544  */
2545 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2546 {
2547         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2548
2549         lockdep_assert_held(&dev_priv->pps_mutex);
2550
2551         if (!intel_dp_is_edp(intel_dp))
2552                 return;
2553
2554         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2555              port_name(dp_to_dig_port(intel_dp)->base.port));
2556
2557         intel_dp->want_panel_vdd = false;
2558
2559         if (sync)
2560                 edp_panel_vdd_off_sync(intel_dp);
2561         else
2562                 edp_panel_vdd_schedule_off(intel_dp);
2563 }
2564
2565 static void edp_panel_on(struct intel_dp *intel_dp)
2566 {
2567         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2568         u32 pp;
2569         i915_reg_t pp_ctrl_reg;
2570
2571         lockdep_assert_held(&dev_priv->pps_mutex);
2572
2573         if (!intel_dp_is_edp(intel_dp))
2574                 return;
2575
2576         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2577                       port_name(dp_to_dig_port(intel_dp)->base.port));
2578
2579         if (WARN(edp_have_panel_power(intel_dp),
2580                  "eDP port %c panel power already on\n",
2581                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2582                 return;
2583
2584         wait_panel_power_cycle(intel_dp);
2585
2586         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2587         pp = ironlake_get_pp_control(intel_dp);
2588         if (IS_GEN(dev_priv, 5)) {
2589                 /* ILK workaround: disable reset around power sequence */
2590                 pp &= ~PANEL_POWER_RESET;
2591                 I915_WRITE(pp_ctrl_reg, pp);
2592                 POSTING_READ(pp_ctrl_reg);
2593         }
2594
2595         pp |= PANEL_POWER_ON;
2596         if (!IS_GEN(dev_priv, 5))
2597                 pp |= PANEL_POWER_RESET;
2598
2599         I915_WRITE(pp_ctrl_reg, pp);
2600         POSTING_READ(pp_ctrl_reg);
2601
2602         wait_panel_on(intel_dp);
2603         intel_dp->last_power_on = jiffies;
2604
2605         if (IS_GEN(dev_priv, 5)) {
2606                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2607                 I915_WRITE(pp_ctrl_reg, pp);
2608                 POSTING_READ(pp_ctrl_reg);
2609         }
2610 }
2611
2612 void intel_edp_panel_on(struct intel_dp *intel_dp)
2613 {
2614         intel_wakeref_t wakeref;
2615
2616         if (!intel_dp_is_edp(intel_dp))
2617                 return;
2618
2619         with_pps_lock(intel_dp, wakeref)
2620                 edp_panel_on(intel_dp);
2621 }
2622
2623
2624 static void edp_panel_off(struct intel_dp *intel_dp)
2625 {
2626         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2627         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2628         u32 pp;
2629         i915_reg_t pp_ctrl_reg;
2630
2631         lockdep_assert_held(&dev_priv->pps_mutex);
2632
2633         if (!intel_dp_is_edp(intel_dp))
2634                 return;
2635
2636         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2637                       port_name(dig_port->base.port));
2638
2639         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2640              port_name(dig_port->base.port));
2641
2642         pp = ironlake_get_pp_control(intel_dp);
2643         /* We need to switch off panel power _and_ force vdd, for otherwise some
2644          * panels get very unhappy and cease to work. */
2645         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2646                 EDP_BLC_ENABLE);
2647
2648         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2649
2650         intel_dp->want_panel_vdd = false;
2651
2652         I915_WRITE(pp_ctrl_reg, pp);
2653         POSTING_READ(pp_ctrl_reg);
2654
2655         wait_panel_off(intel_dp);
2656         intel_dp->panel_power_off_time = ktime_get_boottime();
2657
2658         /* We got a reference when we enabled the VDD. */
2659         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
2660 }
2661
2662 void intel_edp_panel_off(struct intel_dp *intel_dp)
2663 {
2664         intel_wakeref_t wakeref;
2665
2666         if (!intel_dp_is_edp(intel_dp))
2667                 return;
2668
2669         with_pps_lock(intel_dp, wakeref)
2670                 edp_panel_off(intel_dp);
2671 }
2672
2673 /* Enable backlight in the panel power control. */
2674 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2675 {
2676         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2677         intel_wakeref_t wakeref;
2678
2679         /*
2680          * If we enable the backlight right away following a panel power
2681          * on, we may see slight flicker as the panel syncs with the eDP
2682          * link.  So delay a bit to make sure the image is solid before
2683          * allowing it to appear.
2684          */
2685         wait_backlight_on(intel_dp);
2686
2687         with_pps_lock(intel_dp, wakeref) {
2688                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2689                 u32 pp;
2690
2691                 pp = ironlake_get_pp_control(intel_dp);
2692                 pp |= EDP_BLC_ENABLE;
2693
2694                 I915_WRITE(pp_ctrl_reg, pp);
2695                 POSTING_READ(pp_ctrl_reg);
2696         }
2697 }
2698
2699 /* Enable backlight PWM and backlight PP control. */
2700 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2701                             const struct drm_connector_state *conn_state)
2702 {
2703         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2704
2705         if (!intel_dp_is_edp(intel_dp))
2706                 return;
2707
2708         DRM_DEBUG_KMS("\n");
2709
2710         intel_panel_enable_backlight(crtc_state, conn_state);
2711         _intel_edp_backlight_on(intel_dp);
2712 }
2713
2714 /* Disable backlight in the panel power control. */
2715 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2716 {
2717         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2718         intel_wakeref_t wakeref;
2719
2720         if (!intel_dp_is_edp(intel_dp))
2721                 return;
2722
2723         with_pps_lock(intel_dp, wakeref) {
2724                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2725                 u32 pp;
2726
2727                 pp = ironlake_get_pp_control(intel_dp);
2728                 pp &= ~EDP_BLC_ENABLE;
2729
2730                 I915_WRITE(pp_ctrl_reg, pp);
2731                 POSTING_READ(pp_ctrl_reg);
2732         }
2733
2734         intel_dp->last_backlight_off = jiffies;
2735         edp_wait_backlight_off(intel_dp);
2736 }
2737
2738 /* Disable backlight PP control and backlight PWM. */
2739 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2740 {
2741         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2742
2743         if (!intel_dp_is_edp(intel_dp))
2744                 return;
2745
2746         DRM_DEBUG_KMS("\n");
2747
2748         _intel_edp_backlight_off(intel_dp);
2749         intel_panel_disable_backlight(old_conn_state);
2750 }
2751
2752 /*
2753  * Hook for controlling the panel power control backlight through the bl_power
2754  * sysfs attribute. Take care to handle multiple calls.
2755  */
2756 static void intel_edp_backlight_power(struct intel_connector *connector,
2757                                       bool enable)
2758 {
2759         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2760         intel_wakeref_t wakeref;
2761         bool is_enabled;
2762
2763         is_enabled = false;
2764         with_pps_lock(intel_dp, wakeref)
2765                 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2766         if (is_enabled == enable)
2767                 return;
2768
2769         DRM_DEBUG_KMS("panel power control backlight %s\n",
2770                       enable ? "enable" : "disable");
2771
2772         if (enable)
2773                 _intel_edp_backlight_on(intel_dp);
2774         else
2775                 _intel_edp_backlight_off(intel_dp);
2776 }
2777
2778 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2779 {
2780         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2781         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2782         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2783
2784         I915_STATE_WARN(cur_state != state,
2785                         "DP port %c state assertion failure (expected %s, current %s)\n",
2786                         port_name(dig_port->base.port),
2787                         onoff(state), onoff(cur_state));
2788 }
2789 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2790
2791 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2792 {
2793         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2794
2795         I915_STATE_WARN(cur_state != state,
2796                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2797                         onoff(state), onoff(cur_state));
2798 }
2799 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2800 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2801
2802 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2803                                 const struct intel_crtc_state *pipe_config)
2804 {
2805         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2806         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2807
2808         assert_pipe_disabled(dev_priv, crtc->pipe);
2809         assert_dp_port_disabled(intel_dp);
2810         assert_edp_pll_disabled(dev_priv);
2811
2812         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2813                       pipe_config->port_clock);
2814
2815         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2816
2817         if (pipe_config->port_clock == 162000)
2818                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2819         else
2820                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2821
2822         I915_WRITE(DP_A, intel_dp->DP);
2823         POSTING_READ(DP_A);
2824         udelay(500);
2825
2826         /*
2827          * [DevILK] Work around required when enabling DP PLL
2828          * while a pipe is enabled going to FDI:
2829          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2830          * 2. Program DP PLL enable
2831          */
2832         if (IS_GEN(dev_priv, 5))
2833                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2834
2835         intel_dp->DP |= DP_PLL_ENABLE;
2836
2837         I915_WRITE(DP_A, intel_dp->DP);
2838         POSTING_READ(DP_A);
2839         udelay(200);
2840 }
2841
2842 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2843                                  const struct intel_crtc_state *old_crtc_state)
2844 {
2845         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2846         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2847
2848         assert_pipe_disabled(dev_priv, crtc->pipe);
2849         assert_dp_port_disabled(intel_dp);
2850         assert_edp_pll_enabled(dev_priv);
2851
2852         DRM_DEBUG_KMS("disabling eDP PLL\n");
2853
2854         intel_dp->DP &= ~DP_PLL_ENABLE;
2855
2856         I915_WRITE(DP_A, intel_dp->DP);
2857         POSTING_READ(DP_A);
2858         udelay(200);
2859 }
2860
2861 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2862 {
2863         /*
2864          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2865          * be capable of signalling downstream hpd with a long pulse.
2866          * Whether or not that means D3 is safe to use is not clear,
2867          * but let's assume so until proven otherwise.
2868          *
2869          * FIXME should really check all downstream ports...
2870          */
2871         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2872                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2873                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2874 }
2875
2876 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2877                                            const struct intel_crtc_state *crtc_state,
2878                                            bool enable)
2879 {
2880         int ret;
2881
2882         if (!crtc_state->dsc_params.compression_enable)
2883                 return;
2884
2885         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2886                                  enable ? DP_DECOMPRESSION_EN : 0);
2887         if (ret < 0)
2888                 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
2889                               enable ? "enable" : "disable");
2890 }
2891
2892 /* If the sink supports it, try to set the power state appropriately */
2893 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2894 {
2895         int ret, i;
2896
2897         /* Should have a valid DPCD by this point */
2898         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2899                 return;
2900
2901         if (mode != DRM_MODE_DPMS_ON) {
2902                 if (downstream_hpd_needs_d0(intel_dp))
2903                         return;
2904
2905                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2906                                          DP_SET_POWER_D3);
2907         } else {
2908                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2909
2910                 /*
2911                  * When turning on, we need to retry for 1ms to give the sink
2912                  * time to wake up.
2913                  */
2914                 for (i = 0; i < 3; i++) {
2915                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2916                                                  DP_SET_POWER_D0);
2917                         if (ret == 1)
2918                                 break;
2919                         msleep(1);
2920                 }
2921
2922                 if (ret == 1 && lspcon->active)
2923                         lspcon_wait_pcon_mode(lspcon);
2924         }
2925
2926         if (ret != 1)
2927                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2928                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2929 }
2930
2931 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2932                                  enum port port, enum pipe *pipe)
2933 {
2934         enum pipe p;
2935
2936         for_each_pipe(dev_priv, p) {
2937                 u32 val = I915_READ(TRANS_DP_CTL(p));
2938
2939                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2940                         *pipe = p;
2941                         return true;
2942                 }
2943         }
2944
2945         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2946
2947         /* must initialize pipe to something for the asserts */
2948         *pipe = PIPE_A;
2949
2950         return false;
2951 }
2952
2953 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2954                            i915_reg_t dp_reg, enum port port,
2955                            enum pipe *pipe)
2956 {
2957         bool ret;
2958         u32 val;
2959
2960         val = I915_READ(dp_reg);
2961
2962         ret = val & DP_PORT_EN;
2963
2964         /* asserts want to know the pipe even if the port is disabled */
2965         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2966                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2967         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2968                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2969         else if (IS_CHERRYVIEW(dev_priv))
2970                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2971         else
2972                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2973
2974         return ret;
2975 }
2976
2977 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2978                                   enum pipe *pipe)
2979 {
2980         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2981         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2982         intel_wakeref_t wakeref;
2983         bool ret;
2984
2985         wakeref = intel_display_power_get_if_enabled(dev_priv,
2986                                                      encoder->power_domain);
2987         if (!wakeref)
2988                 return false;
2989
2990         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
2991                                     encoder->port, pipe);
2992
2993         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2994
2995         return ret;
2996 }
2997
2998 static void intel_dp_get_config(struct intel_encoder *encoder,
2999                                 struct intel_crtc_state *pipe_config)
3000 {
3001         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3002         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3003         u32 tmp, flags = 0;
3004         enum port port = encoder->port;
3005         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3006
3007         if (encoder->type == INTEL_OUTPUT_EDP)
3008                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3009         else
3010                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3011
3012         tmp = I915_READ(intel_dp->output_reg);
3013
3014         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3015
3016         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3017                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3018
3019                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3020                         flags |= DRM_MODE_FLAG_PHSYNC;
3021                 else
3022                         flags |= DRM_MODE_FLAG_NHSYNC;
3023
3024                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3025                         flags |= DRM_MODE_FLAG_PVSYNC;
3026                 else
3027                         flags |= DRM_MODE_FLAG_NVSYNC;
3028         } else {
3029                 if (tmp & DP_SYNC_HS_HIGH)
3030                         flags |= DRM_MODE_FLAG_PHSYNC;
3031                 else
3032                         flags |= DRM_MODE_FLAG_NHSYNC;
3033
3034                 if (tmp & DP_SYNC_VS_HIGH)
3035                         flags |= DRM_MODE_FLAG_PVSYNC;
3036                 else
3037                         flags |= DRM_MODE_FLAG_NVSYNC;
3038         }
3039
3040         pipe_config->base.adjusted_mode.flags |= flags;
3041
3042         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3043                 pipe_config->limited_color_range = true;
3044
3045         pipe_config->lane_count =
3046                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3047
3048         intel_dp_get_m_n(crtc, pipe_config);
3049
3050         if (port == PORT_A) {
3051                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3052                         pipe_config->port_clock = 162000;
3053                 else
3054                         pipe_config->port_clock = 270000;
3055         }
3056
3057         pipe_config->base.adjusted_mode.crtc_clock =
3058                 intel_dotclock_calculate(pipe_config->port_clock,
3059                                          &pipe_config->dp_m_n);
3060
3061         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3062             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3063                 /*
3064                  * This is a big fat ugly hack.
3065                  *
3066                  * Some machines in UEFI boot mode provide us a VBT that has 18
3067                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3068                  * unknown we fail to light up. Yet the same BIOS boots up with
3069                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3070                  * max, not what it tells us to use.
3071                  *
3072                  * Note: This will still be broken if the eDP panel is not lit
3073                  * up by the BIOS, and thus we can't get the mode at module
3074                  * load.
3075                  */
3076                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3077                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3078                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3079         }
3080 }
3081
3082 static void intel_disable_dp(struct intel_encoder *encoder,
3083                              const struct intel_crtc_state *old_crtc_state,
3084                              const struct drm_connector_state *old_conn_state)
3085 {
3086         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3087
3088         intel_dp->link_trained = false;
3089
3090         if (old_crtc_state->has_audio)
3091                 intel_audio_codec_disable(encoder,
3092                                           old_crtc_state, old_conn_state);
3093
3094         /* Make sure the panel is off before trying to change the mode. But also
3095          * ensure that we have vdd while we switch off the panel. */
3096         intel_edp_panel_vdd_on(intel_dp);
3097         intel_edp_backlight_off(old_conn_state);
3098         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3099         intel_edp_panel_off(intel_dp);
3100 }
3101
3102 static void g4x_disable_dp(struct intel_encoder *encoder,
3103                            const struct intel_crtc_state *old_crtc_state,
3104                            const struct drm_connector_state *old_conn_state)
3105 {
3106         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3107 }
3108
3109 static void vlv_disable_dp(struct intel_encoder *encoder,
3110                            const struct intel_crtc_state *old_crtc_state,
3111                            const struct drm_connector_state *old_conn_state)
3112 {
3113         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3114 }
3115
3116 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3117                                 const struct intel_crtc_state *old_crtc_state,
3118                                 const struct drm_connector_state *old_conn_state)
3119 {
3120         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3121         enum port port = encoder->port;
3122
3123         /*
3124          * Bspec does not list a specific disable sequence for g4x DP.
3125          * Follow the ilk+ sequence (disable pipe before the port) for
3126          * g4x DP as it does not suffer from underruns like the normal
3127          * g4x modeset sequence (disable pipe after the port).
3128          */
3129         intel_dp_link_down(encoder, old_crtc_state);
3130
3131         /* Only ilk+ has port A */
3132         if (port == PORT_A)
3133                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3134 }
3135
3136 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3137                                 const struct intel_crtc_state *old_crtc_state,
3138                                 const struct drm_connector_state *old_conn_state)
3139 {
3140         intel_dp_link_down(encoder, old_crtc_state);
3141 }
3142
3143 static void chv_post_disable_dp(struct intel_encoder *encoder,
3144                                 const struct intel_crtc_state *old_crtc_state,
3145                                 const struct drm_connector_state *old_conn_state)
3146 {
3147         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3148
3149         intel_dp_link_down(encoder, old_crtc_state);
3150
3151         mutex_lock(&dev_priv->sb_lock);
3152
3153         /* Assert data lane reset */
3154         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3155
3156         mutex_unlock(&dev_priv->sb_lock);
3157 }
3158
3159 static void
3160 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3161                          u32 *DP,
3162                          u8 dp_train_pat)
3163 {
3164         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3165         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3166         enum port port = intel_dig_port->base.port;
3167         u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3168
3169         if (dp_train_pat & train_pat_mask)
3170                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3171                               dp_train_pat & train_pat_mask);
3172
3173         if (HAS_DDI(dev_priv)) {
3174                 u32 temp = I915_READ(DP_TP_CTL(port));
3175
3176                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3177                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3178                 else
3179                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3180
3181                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3182                 switch (dp_train_pat & train_pat_mask) {
3183                 case DP_TRAINING_PATTERN_DISABLE:
3184                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3185
3186                         break;
3187                 case DP_TRAINING_PATTERN_1:
3188                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3189                         break;
3190                 case DP_TRAINING_PATTERN_2:
3191                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3192                         break;
3193                 case DP_TRAINING_PATTERN_3:
3194                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3195                         break;
3196                 case DP_TRAINING_PATTERN_4:
3197                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3198                         break;
3199                 }
3200                 I915_WRITE(DP_TP_CTL(port), temp);
3201
3202         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3203                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3204                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3205
3206                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3207                 case DP_TRAINING_PATTERN_DISABLE:
3208                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3209                         break;
3210                 case DP_TRAINING_PATTERN_1:
3211                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3212                         break;
3213                 case DP_TRAINING_PATTERN_2:
3214                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3215                         break;
3216                 case DP_TRAINING_PATTERN_3:
3217                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3218                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3219                         break;
3220                 }
3221
3222         } else {
3223                 *DP &= ~DP_LINK_TRAIN_MASK;
3224
3225                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3226                 case DP_TRAINING_PATTERN_DISABLE:
3227                         *DP |= DP_LINK_TRAIN_OFF;
3228                         break;
3229                 case DP_TRAINING_PATTERN_1:
3230                         *DP |= DP_LINK_TRAIN_PAT_1;
3231                         break;
3232                 case DP_TRAINING_PATTERN_2:
3233                         *DP |= DP_LINK_TRAIN_PAT_2;
3234                         break;
3235                 case DP_TRAINING_PATTERN_3:
3236                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3237                         *DP |= DP_LINK_TRAIN_PAT_2;
3238                         break;
3239                 }
3240         }
3241 }
3242
3243 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3244                                  const struct intel_crtc_state *old_crtc_state)
3245 {
3246         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3247
3248         /* enable with pattern 1 (as per spec) */
3249
3250         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3251
3252         /*
3253          * Magic for VLV/CHV. We _must_ first set up the register
3254          * without actually enabling the port, and then do another
3255          * write to enable the port. Otherwise link training will
3256          * fail when the power sequencer is freshly used for this port.
3257          */
3258         intel_dp->DP |= DP_PORT_EN;
3259         if (old_crtc_state->has_audio)
3260                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3261
3262         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3263         POSTING_READ(intel_dp->output_reg);
3264 }
3265
3266 static void intel_enable_dp(struct intel_encoder *encoder,
3267                             const struct intel_crtc_state *pipe_config,
3268                             const struct drm_connector_state *conn_state)
3269 {
3270         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3271         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3272         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3273         u32 dp_reg = I915_READ(intel_dp->output_reg);
3274         enum pipe pipe = crtc->pipe;
3275         intel_wakeref_t wakeref;
3276
3277         if (WARN_ON(dp_reg & DP_PORT_EN))
3278                 return;
3279
3280         with_pps_lock(intel_dp, wakeref) {
3281                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3282                         vlv_init_panel_power_sequencer(encoder, pipe_config);
3283
3284                 intel_dp_enable_port(intel_dp, pipe_config);
3285
3286                 edp_panel_vdd_on(intel_dp);
3287                 edp_panel_on(intel_dp);
3288                 edp_panel_vdd_off(intel_dp, true);
3289         }
3290
3291         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3292                 unsigned int lane_mask = 0x0;
3293
3294                 if (IS_CHERRYVIEW(dev_priv))
3295                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3296
3297                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3298                                     lane_mask);
3299         }
3300
3301         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3302         intel_dp_start_link_train(intel_dp);
3303         intel_dp_stop_link_train(intel_dp);
3304
3305         if (pipe_config->has_audio) {
3306                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3307                                  pipe_name(pipe));
3308                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3309         }
3310 }
3311
3312 static void g4x_enable_dp(struct intel_encoder *encoder,
3313                           const struct intel_crtc_state *pipe_config,
3314                           const struct drm_connector_state *conn_state)
3315 {
3316         intel_enable_dp(encoder, pipe_config, conn_state);
3317         intel_edp_backlight_on(pipe_config, conn_state);
3318 }
3319
3320 static void vlv_enable_dp(struct intel_encoder *encoder,
3321                           const struct intel_crtc_state *pipe_config,
3322                           const struct drm_connector_state *conn_state)
3323 {
3324         intel_edp_backlight_on(pipe_config, conn_state);
3325 }
3326
3327 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3328                               const struct intel_crtc_state *pipe_config,
3329                               const struct drm_connector_state *conn_state)
3330 {
3331         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3332         enum port port = encoder->port;
3333
3334         intel_dp_prepare(encoder, pipe_config);
3335
3336         /* Only ilk+ has port A */
3337         if (port == PORT_A)
3338                 ironlake_edp_pll_on(intel_dp, pipe_config);
3339 }
3340
3341 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3342 {
3343         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3344         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3345         enum pipe pipe = intel_dp->pps_pipe;
3346         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3347
3348         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3349
3350         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3351                 return;
3352
3353         edp_panel_vdd_off_sync(intel_dp);
3354
3355         /*
3356          * VLV seems to get confused when multiple power sequencers
3357          * have the same port selected (even if only one has power/vdd
3358          * enabled). The failure manifests as vlv_wait_port_ready() failing
3359          * CHV on the other hand doesn't seem to mind having the same port
3360          * selected in multiple power sequencers, but let's clear the
3361          * port select always when logically disconnecting a power sequencer
3362          * from a port.
3363          */
3364         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3365                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3366         I915_WRITE(pp_on_reg, 0);
3367         POSTING_READ(pp_on_reg);
3368
3369         intel_dp->pps_pipe = INVALID_PIPE;
3370 }
3371
3372 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3373                                       enum pipe pipe)
3374 {
3375         struct intel_encoder *encoder;
3376
3377         lockdep_assert_held(&dev_priv->pps_mutex);
3378
3379         for_each_intel_dp(&dev_priv->drm, encoder) {
3380                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3381                 enum port port = encoder->port;
3382
3383                 WARN(intel_dp->active_pipe == pipe,
3384                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3385                      pipe_name(pipe), port_name(port));
3386
3387                 if (intel_dp->pps_pipe != pipe)
3388                         continue;
3389
3390                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3391                               pipe_name(pipe), port_name(port));
3392
3393                 /* make sure vdd is off before we steal it */
3394                 vlv_detach_power_sequencer(intel_dp);
3395         }
3396 }
3397
3398 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3399                                            const struct intel_crtc_state *crtc_state)
3400 {
3401         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3402         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3403         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3404
3405         lockdep_assert_held(&dev_priv->pps_mutex);
3406
3407         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3408
3409         if (intel_dp->pps_pipe != INVALID_PIPE &&
3410             intel_dp->pps_pipe != crtc->pipe) {
3411                 /*
3412                  * If another power sequencer was being used on this
3413                  * port previously make sure to turn off vdd there while
3414                  * we still have control of it.
3415                  */
3416                 vlv_detach_power_sequencer(intel_dp);
3417         }
3418
3419         /*
3420          * We may be stealing the power
3421          * sequencer from another port.
3422          */
3423         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3424
3425         intel_dp->active_pipe = crtc->pipe;
3426
3427         if (!intel_dp_is_edp(intel_dp))
3428                 return;
3429
3430         /* now it's all ours */
3431         intel_dp->pps_pipe = crtc->pipe;
3432
3433         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3434                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3435
3436         /* init power sequencer on this pipe and port */
3437         intel_dp_init_panel_power_sequencer(intel_dp);
3438         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3439 }
3440
3441 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3442                               const struct intel_crtc_state *pipe_config,
3443                               const struct drm_connector_state *conn_state)
3444 {
3445         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3446
3447         intel_enable_dp(encoder, pipe_config, conn_state);
3448 }
3449
3450 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3451                                   const struct intel_crtc_state *pipe_config,
3452                                   const struct drm_connector_state *conn_state)
3453 {
3454         intel_dp_prepare(encoder, pipe_config);
3455
3456         vlv_phy_pre_pll_enable(encoder, pipe_config);
3457 }
3458
3459 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3460                               const struct intel_crtc_state *pipe_config,
3461                               const struct drm_connector_state *conn_state)
3462 {
3463         chv_phy_pre_encoder_enable(encoder, pipe_config);
3464
3465         intel_enable_dp(encoder, pipe_config, conn_state);
3466
3467         /* Second common lane will stay alive on its own now */
3468         chv_phy_release_cl2_override(encoder);
3469 }
3470
3471 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3472                                   const struct intel_crtc_state *pipe_config,
3473                                   const struct drm_connector_state *conn_state)
3474 {
3475         intel_dp_prepare(encoder, pipe_config);
3476
3477         chv_phy_pre_pll_enable(encoder, pipe_config);
3478 }
3479
3480 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3481                                     const struct intel_crtc_state *old_crtc_state,
3482                                     const struct drm_connector_state *old_conn_state)
3483 {
3484         chv_phy_post_pll_disable(encoder, old_crtc_state);
3485 }
3486
3487 /*
3488  * Fetch AUX CH registers 0x202 - 0x207 which contain
3489  * link status information
3490  */
3491 bool
3492 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3493 {
3494         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3495                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3496 }
3497
3498 /* These are source-specific values. */
3499 u8
3500 intel_dp_voltage_max(struct intel_dp *intel_dp)
3501 {
3502         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3503         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3504         enum port port = encoder->port;
3505
3506         if (HAS_DDI(dev_priv))
3507                 return intel_ddi_dp_voltage_max(encoder);
3508         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3509                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3510         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3511                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3512         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3513                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3514         else
3515                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3516 }
3517
3518 u8
3519 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
3520 {
3521         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3522         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3523         enum port port = encoder->port;
3524
3525         if (HAS_DDI(dev_priv)) {
3526                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3527         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3528                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3529                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3530                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3531                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3532                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3533                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3534                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3535                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3536                 default:
3537                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3538                 }
3539         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3540                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3541                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3542                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3543                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3544                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3545                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3546                 default:
3547                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3548                 }
3549         } else {
3550                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3551                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3552                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3553                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3554                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3555                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3556                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3557                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3558                 default:
3559                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3560                 }
3561         }
3562 }
3563
3564 static u32 vlv_signal_levels(struct intel_dp *intel_dp)
3565 {
3566         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3567         unsigned long demph_reg_value, preemph_reg_value,
3568                 uniqtranscale_reg_value;
3569         u8 train_set = intel_dp->train_set[0];
3570
3571         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3572         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3573                 preemph_reg_value = 0x0004000;
3574                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3575                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3576                         demph_reg_value = 0x2B405555;
3577                         uniqtranscale_reg_value = 0x552AB83A;
3578                         break;
3579                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3580                         demph_reg_value = 0x2B404040;
3581                         uniqtranscale_reg_value = 0x5548B83A;
3582                         break;
3583                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3584                         demph_reg_value = 0x2B245555;
3585                         uniqtranscale_reg_value = 0x5560B83A;
3586                         break;
3587                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3588                         demph_reg_value = 0x2B405555;
3589                         uniqtranscale_reg_value = 0x5598DA3A;
3590                         break;
3591                 default:
3592                         return 0;
3593                 }
3594                 break;
3595         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3596                 preemph_reg_value = 0x0002000;
3597                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3598                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3599                         demph_reg_value = 0x2B404040;
3600                         uniqtranscale_reg_value = 0x5552B83A;
3601                         break;
3602                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3603                         demph_reg_value = 0x2B404848;
3604                         uniqtranscale_reg_value = 0x5580B83A;
3605                         break;
3606                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3607                         demph_reg_value = 0x2B404040;
3608                         uniqtranscale_reg_value = 0x55ADDA3A;
3609                         break;
3610                 default:
3611                         return 0;
3612                 }
3613                 break;
3614         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3615                 preemph_reg_value = 0x0000000;
3616                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3617                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3618                         demph_reg_value = 0x2B305555;
3619                         uniqtranscale_reg_value = 0x5570B83A;
3620                         break;
3621                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3622                         demph_reg_value = 0x2B2B4040;
3623                         uniqtranscale_reg_value = 0x55ADDA3A;
3624                         break;
3625                 default:
3626                         return 0;
3627                 }
3628                 break;
3629         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3630                 preemph_reg_value = 0x0006000;
3631                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3632                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3633                         demph_reg_value = 0x1B405555;
3634                         uniqtranscale_reg_value = 0x55ADDA3A;
3635                         break;
3636                 default:
3637                         return 0;
3638                 }
3639                 break;
3640         default:
3641                 return 0;
3642         }
3643
3644         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3645                                  uniqtranscale_reg_value, 0);
3646
3647         return 0;
3648 }
3649
3650 static u32 chv_signal_levels(struct intel_dp *intel_dp)
3651 {
3652         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3653         u32 deemph_reg_value, margin_reg_value;
3654         bool uniq_trans_scale = false;
3655         u8 train_set = intel_dp->train_set[0];
3656
3657         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3658         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3659                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3660                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3661                         deemph_reg_value = 128;
3662                         margin_reg_value = 52;
3663                         break;
3664                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3665                         deemph_reg_value = 128;
3666                         margin_reg_value = 77;
3667                         break;
3668                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3669                         deemph_reg_value = 128;
3670                         margin_reg_value = 102;
3671                         break;
3672                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3673                         deemph_reg_value = 128;
3674                         margin_reg_value = 154;
3675                         uniq_trans_scale = true;
3676                         break;
3677                 default:
3678                         return 0;
3679                 }
3680                 break;
3681         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3682                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3683                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3684                         deemph_reg_value = 85;
3685                         margin_reg_value = 78;
3686                         break;
3687                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3688                         deemph_reg_value = 85;
3689                         margin_reg_value = 116;
3690                         break;
3691                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3692                         deemph_reg_value = 85;
3693                         margin_reg_value = 154;
3694                         break;
3695                 default:
3696                         return 0;
3697                 }
3698                 break;
3699         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3700                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3701                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3702                         deemph_reg_value = 64;
3703                         margin_reg_value = 104;
3704                         break;
3705                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3706                         deemph_reg_value = 64;
3707                         margin_reg_value = 154;
3708                         break;
3709                 default:
3710                         return 0;
3711                 }
3712                 break;
3713         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3714                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3715                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3716                         deemph_reg_value = 43;
3717                         margin_reg_value = 154;
3718                         break;
3719                 default:
3720                         return 0;
3721                 }
3722                 break;
3723         default:
3724                 return 0;
3725         }
3726
3727         chv_set_phy_signal_level(encoder, deemph_reg_value,
3728                                  margin_reg_value, uniq_trans_scale);
3729
3730         return 0;
3731 }
3732
3733 static u32
3734 g4x_signal_levels(u8 train_set)
3735 {
3736         u32 signal_levels = 0;
3737
3738         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3739         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3740         default:
3741                 signal_levels |= DP_VOLTAGE_0_4;
3742                 break;
3743         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3744                 signal_levels |= DP_VOLTAGE_0_6;
3745                 break;
3746         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3747                 signal_levels |= DP_VOLTAGE_0_8;
3748                 break;
3749         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3750                 signal_levels |= DP_VOLTAGE_1_2;
3751                 break;
3752         }
3753         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3754         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3755         default:
3756                 signal_levels |= DP_PRE_EMPHASIS_0;
3757                 break;
3758         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3759                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3760                 break;
3761         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3762                 signal_levels |= DP_PRE_EMPHASIS_6;
3763                 break;
3764         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3765                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3766                 break;
3767         }
3768         return signal_levels;
3769 }
3770
3771 /* SNB CPU eDP voltage swing and pre-emphasis control */
3772 static u32
3773 snb_cpu_edp_signal_levels(u8 train_set)
3774 {
3775         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3776                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3777         switch (signal_levels) {
3778         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3779         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3780                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3781         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3782                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3783         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3784         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3785                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3786         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3787         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3788                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3789         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3790         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3791                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3792         default:
3793                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3794                               "0x%x\n", signal_levels);
3795                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3796         }
3797 }
3798
3799 /* IVB CPU eDP voltage swing and pre-emphasis control */
3800 static u32
3801 ivb_cpu_edp_signal_levels(u8 train_set)
3802 {
3803         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3804                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3805         switch (signal_levels) {
3806         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3807                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3808         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3809                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3810         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3811                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3812
3813         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3814                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3815         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3816                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3817
3818         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3819                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3820         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3821                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3822
3823         default:
3824                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3825                               "0x%x\n", signal_levels);
3826                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3827         }
3828 }
3829
3830 void
3831 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3832 {
3833         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3834         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3835         enum port port = intel_dig_port->base.port;
3836         u32 signal_levels, mask = 0;
3837         u8 train_set = intel_dp->train_set[0];
3838
3839         if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
3840                 signal_levels = bxt_signal_levels(intel_dp);
3841         } else if (HAS_DDI(dev_priv)) {
3842                 signal_levels = ddi_signal_levels(intel_dp);
3843                 mask = DDI_BUF_EMP_MASK;
3844         } else if (IS_CHERRYVIEW(dev_priv)) {
3845                 signal_levels = chv_signal_levels(intel_dp);
3846         } else if (IS_VALLEYVIEW(dev_priv)) {
3847                 signal_levels = vlv_signal_levels(intel_dp);
3848         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3849                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3850                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3851         } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
3852                 signal_levels = snb_cpu_edp_signal_levels(train_set);
3853                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3854         } else {
3855                 signal_levels = g4x_signal_levels(train_set);
3856                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3857         }
3858
3859         if (mask)
3860                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3861
3862         DRM_DEBUG_KMS("Using vswing level %d\n",
3863                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3864         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3865                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3866                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3867
3868         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3869
3870         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3871         POSTING_READ(intel_dp->output_reg);
3872 }
3873
3874 void
3875 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3876                                        u8 dp_train_pat)
3877 {
3878         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3879         struct drm_i915_private *dev_priv =
3880                 to_i915(intel_dig_port->base.base.dev);
3881
3882         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3883
3884         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3885         POSTING_READ(intel_dp->output_reg);
3886 }
3887
3888 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3889 {
3890         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3891         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3892         enum port port = intel_dig_port->base.port;
3893         u32 val;
3894
3895         if (!HAS_DDI(dev_priv))
3896                 return;
3897
3898         val = I915_READ(DP_TP_CTL(port));
3899         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3900         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3901         I915_WRITE(DP_TP_CTL(port), val);
3902
3903         /*
3904          * On PORT_A we can have only eDP in SST mode. There the only reason
3905          * we need to set idle transmission mode is to work around a HW issue
3906          * where we enable the pipe while not in idle link-training mode.
3907          * In this case there is requirement to wait for a minimum number of
3908          * idle patterns to be sent.
3909          */
3910         if (port == PORT_A)
3911                 return;
3912
3913         if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
3914                                     DP_TP_STATUS_IDLE_DONE,
3915                                     DP_TP_STATUS_IDLE_DONE,
3916                                     1))
3917                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3918 }
3919
3920 static void
3921 intel_dp_link_down(struct intel_encoder *encoder,
3922                    const struct intel_crtc_state *old_crtc_state)
3923 {
3924         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3925         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3926         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3927         enum port port = encoder->port;
3928         u32 DP = intel_dp->DP;
3929
3930         if (WARN_ON(HAS_DDI(dev_priv)))
3931                 return;
3932
3933         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3934                 return;
3935
3936         DRM_DEBUG_KMS("\n");
3937
3938         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3939             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3940                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3941                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3942         } else {
3943                 DP &= ~DP_LINK_TRAIN_MASK;
3944                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3945         }
3946         I915_WRITE(intel_dp->output_reg, DP);
3947         POSTING_READ(intel_dp->output_reg);
3948
3949         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3950         I915_WRITE(intel_dp->output_reg, DP);
3951         POSTING_READ(intel_dp->output_reg);
3952
3953         /*
3954          * HW workaround for IBX, we need to move the port
3955          * to transcoder A after disabling it to allow the
3956          * matching HDMI port to be enabled on transcoder A.
3957          */
3958         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3959                 /*
3960                  * We get CPU/PCH FIFO underruns on the other pipe when
3961                  * doing the workaround. Sweep them under the rug.
3962                  */
3963                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3964                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3965
3966                 /* always enable with pattern 1 (as per spec) */
3967                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
3968                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
3969                         DP_LINK_TRAIN_PAT_1;
3970                 I915_WRITE(intel_dp->output_reg, DP);
3971                 POSTING_READ(intel_dp->output_reg);
3972
3973                 DP &= ~DP_PORT_EN;
3974                 I915_WRITE(intel_dp->output_reg, DP);
3975                 POSTING_READ(intel_dp->output_reg);
3976
3977                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3978                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3979                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3980         }
3981
3982         msleep(intel_dp->panel_power_down_delay);
3983
3984         intel_dp->DP = DP;
3985
3986         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3987                 intel_wakeref_t wakeref;
3988
3989                 with_pps_lock(intel_dp, wakeref)
3990                         intel_dp->active_pipe = INVALID_PIPE;
3991         }
3992 }
3993
3994 static void
3995 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
3996 {
3997         u8 dpcd_ext[6];
3998
3999         /*
4000          * Prior to DP1.3 the bit represented by
4001          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4002          * if it is set DP_DPCD_REV at 0000h could be at a value less than
4003          * the true capability of the panel. The only way to check is to
4004          * then compare 0000h and 2200h.
4005          */
4006         if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4007               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4008                 return;
4009
4010         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4011                              &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4012                 DRM_ERROR("DPCD failed read at extended capabilities\n");
4013                 return;
4014         }
4015
4016         if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4017                 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n");
4018                 return;
4019         }
4020
4021         if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4022                 return;
4023
4024         DRM_DEBUG_KMS("Base DPCD: %*ph\n",
4025                       (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4026
4027         memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4028 }
4029
4030 bool
4031 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4032 {
4033         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4034                              sizeof(intel_dp->dpcd)) < 0)
4035                 return false; /* aux transfer failed */
4036
4037         intel_dp_extended_receiver_capabilities(intel_dp);
4038
4039         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4040
4041         return intel_dp->dpcd[DP_DPCD_REV] != 0;
4042 }
4043
4044 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4045 {
4046         /*
4047          * Clear the cached register set to avoid using stale values
4048          * for the sinks that do not support DSC.
4049          */
4050         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4051
4052         /* Clear fec_capable to avoid using stale values */
4053         intel_dp->fec_capable = 0;
4054
4055         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4056         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4057             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4058                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4059                                      intel_dp->dsc_dpcd,
4060                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4061                         DRM_ERROR("Failed to read DPCD register 0x%x\n",
4062                                   DP_DSC_SUPPORT);
4063
4064                 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4065                               (int)sizeof(intel_dp->dsc_dpcd),
4066                               intel_dp->dsc_dpcd);
4067
4068                 /* FEC is supported only on DP 1.4 */
4069                 if (!intel_dp_is_edp(intel_dp) &&
4070                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4071                                       &intel_dp->fec_capable) < 0)
4072                         DRM_ERROR("Failed to read FEC DPCD register\n");
4073
4074                 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4075         }
4076 }
4077
4078 static bool
4079 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4080 {
4081         struct drm_i915_private *dev_priv =
4082                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4083
4084         /* this function is meant to be called only once */
4085         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4086
4087         if (!intel_dp_read_dpcd(intel_dp))
4088                 return false;
4089
4090         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4091                          drm_dp_is_branch(intel_dp->dpcd));
4092
4093         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4094                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4095                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4096
4097         /*
4098          * Read the eDP display control registers.
4099          *
4100          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4101          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4102          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4103          * method). The display control registers should read zero if they're
4104          * not supported anyway.
4105          */
4106         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4107                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4108                              sizeof(intel_dp->edp_dpcd))
4109                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
4110                               intel_dp->edp_dpcd);
4111
4112         /*
4113          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4114          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4115          */
4116         intel_psr_init_dpcd(intel_dp);
4117
4118         /* Read the eDP 1.4+ supported link rates. */
4119         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4120                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4121                 int i;
4122
4123                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4124                                 sink_rates, sizeof(sink_rates));
4125
4126                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4127                         int val = le16_to_cpu(sink_rates[i]);
4128
4129                         if (val == 0)
4130                                 break;
4131
4132                         /* Value read multiplied by 200kHz gives the per-lane
4133                          * link rate in kHz. The source rates are, however,
4134                          * stored in terms of LS_Clk kHz. The full conversion
4135                          * back to symbols is
4136                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4137                          */
4138                         intel_dp->sink_rates[i] = (val * 200) / 10;
4139                 }
4140                 intel_dp->num_sink_rates = i;
4141         }
4142
4143         /*
4144          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4145          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4146          */
4147         if (intel_dp->num_sink_rates)
4148                 intel_dp->use_rate_select = true;
4149         else
4150                 intel_dp_set_sink_rates(intel_dp);
4151
4152         intel_dp_set_common_rates(intel_dp);
4153
4154         /* Read the eDP DSC DPCD registers */
4155         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4156                 intel_dp_get_dsc_sink_cap(intel_dp);
4157
4158         return true;
4159 }
4160
4161
4162 static bool
4163 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4164 {
4165         if (!intel_dp_read_dpcd(intel_dp))
4166                 return false;
4167
4168         /* Don't clobber cached eDP rates. */
4169         if (!intel_dp_is_edp(intel_dp)) {
4170                 intel_dp_set_sink_rates(intel_dp);
4171                 intel_dp_set_common_rates(intel_dp);
4172         }
4173
4174         /*
4175          * Some eDP panels do not set a valid value for sink count, that is why
4176          * it don't care about read it here and in intel_edp_init_dpcd().
4177          */
4178         if (!intel_dp_is_edp(intel_dp)) {
4179                 u8 count;
4180                 ssize_t r;
4181
4182                 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4183                 if (r < 1)
4184                         return false;
4185
4186                 /*
4187                  * Sink count can change between short pulse hpd hence
4188                  * a member variable in intel_dp will track any changes
4189                  * between short pulse interrupts.
4190                  */
4191                 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4192
4193                 /*
4194                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4195                  * a dongle is present but no display. Unless we require to know
4196                  * if a dongle is present or not, we don't need to update
4197                  * downstream port information. So, an early return here saves
4198                  * time from performing other operations which are not required.
4199                  */
4200                 if (!intel_dp->sink_count)
4201                         return false;
4202         }
4203
4204         if (!drm_dp_is_branch(intel_dp->dpcd))
4205                 return true; /* native DP sink */
4206
4207         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4208                 return true; /* no per-port downstream info */
4209
4210         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4211                              intel_dp->downstream_ports,
4212                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4213                 return false; /* downstream port status fetch failed */
4214
4215         return true;
4216 }
4217
4218 static bool
4219 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4220 {
4221         u8 mstm_cap;
4222
4223         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4224                 return false;
4225
4226         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4227                 return false;
4228
4229         return mstm_cap & DP_MST_CAP;
4230 }
4231
4232 static bool
4233 intel_dp_can_mst(struct intel_dp *intel_dp)
4234 {
4235         return i915_modparams.enable_dp_mst &&
4236                 intel_dp->can_mst &&
4237                 intel_dp_sink_can_mst(intel_dp);
4238 }
4239
4240 static void
4241 intel_dp_configure_mst(struct intel_dp *intel_dp)
4242 {
4243         struct intel_encoder *encoder =
4244                 &dp_to_dig_port(intel_dp)->base;
4245         bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4246
4247         DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
4248                       port_name(encoder->port), yesno(intel_dp->can_mst),
4249                       yesno(sink_can_mst), yesno(i915_modparams.enable_dp_mst));
4250
4251         if (!intel_dp->can_mst)
4252                 return;
4253
4254         intel_dp->is_mst = sink_can_mst &&
4255                 i915_modparams.enable_dp_mst;
4256
4257         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4258                                         intel_dp->is_mst);
4259 }
4260
4261 static bool
4262 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4263 {
4264         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4265                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4266                 DP_DPRX_ESI_LEN;
4267 }
4268
4269 u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
4270                                 int mode_clock, int mode_hdisplay)
4271 {
4272         u16 bits_per_pixel, max_bpp_small_joiner_ram;
4273         int i;
4274
4275         /*
4276          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
4277          * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
4278          * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
4279          * for MST -> TimeSlotsPerMTP has to be calculated
4280          */
4281         bits_per_pixel = (link_clock * lane_count * 8 *
4282                           DP_DSC_FEC_OVERHEAD_FACTOR) /
4283                 mode_clock;
4284
4285         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
4286         max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
4287                 mode_hdisplay;
4288
4289         /*
4290          * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
4291          * check, output bpp from small joiner RAM check)
4292          */
4293         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
4294
4295         /* Error out if the max bpp is less than smallest allowed valid bpp */
4296         if (bits_per_pixel < valid_dsc_bpp[0]) {
4297                 DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
4298                 return 0;
4299         }
4300
4301         /* Find the nearest match in the array of known BPPs from VESA */
4302         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
4303                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
4304                         break;
4305         }
4306         bits_per_pixel = valid_dsc_bpp[i];
4307
4308         /*
4309          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
4310          * fractional part is 0
4311          */
4312         return bits_per_pixel << 4;
4313 }
4314
4315 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
4316                                 int mode_clock,
4317                                 int mode_hdisplay)
4318 {
4319         u8 min_slice_count, i;
4320         int max_slice_width;
4321
4322         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
4323                 min_slice_count = DIV_ROUND_UP(mode_clock,
4324                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
4325         else
4326                 min_slice_count = DIV_ROUND_UP(mode_clock,
4327                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
4328
4329         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
4330         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
4331                 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
4332                               max_slice_width);
4333                 return 0;
4334         }
4335         /* Also take into account max slice width */
4336         min_slice_count = min_t(u8, min_slice_count,
4337                                 DIV_ROUND_UP(mode_hdisplay,
4338                                              max_slice_width));
4339
4340         /* Find the closest match to the valid slice count values */
4341         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
4342                 if (valid_dsc_slicecount[i] >
4343                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
4344                                                     false))
4345                         break;
4346                 if (min_slice_count  <= valid_dsc_slicecount[i])
4347                         return valid_dsc_slicecount[i];
4348         }
4349
4350         DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
4351         return 0;
4352 }
4353
4354 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4355 {
4356         int status = 0;
4357         int test_link_rate;
4358         u8 test_lane_count, test_link_bw;
4359         /* (DP CTS 1.2)
4360          * 4.3.1.11
4361          */
4362         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4363         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4364                                    &test_lane_count);
4365
4366         if (status <= 0) {
4367                 DRM_DEBUG_KMS("Lane count read failed\n");
4368                 return DP_TEST_NAK;
4369         }
4370         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4371
4372         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4373                                    &test_link_bw);
4374         if (status <= 0) {
4375                 DRM_DEBUG_KMS("Link Rate read failed\n");
4376                 return DP_TEST_NAK;
4377         }
4378         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4379
4380         /* Validate the requested link rate and lane count */
4381         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4382                                         test_lane_count))
4383                 return DP_TEST_NAK;
4384
4385         intel_dp->compliance.test_lane_count = test_lane_count;
4386         intel_dp->compliance.test_link_rate = test_link_rate;
4387
4388         return DP_TEST_ACK;
4389 }
4390
4391 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4392 {
4393         u8 test_pattern;
4394         u8 test_misc;
4395         __be16 h_width, v_height;
4396         int status = 0;
4397
4398         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4399         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4400                                    &test_pattern);
4401         if (status <= 0) {
4402                 DRM_DEBUG_KMS("Test pattern read failed\n");
4403                 return DP_TEST_NAK;
4404         }
4405         if (test_pattern != DP_COLOR_RAMP)
4406                 return DP_TEST_NAK;
4407
4408         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4409                                   &h_width, 2);
4410         if (status <= 0) {
4411                 DRM_DEBUG_KMS("H Width read failed\n");
4412                 return DP_TEST_NAK;
4413         }
4414
4415         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4416                                   &v_height, 2);
4417         if (status <= 0) {
4418                 DRM_DEBUG_KMS("V Height read failed\n");
4419                 return DP_TEST_NAK;
4420         }
4421
4422         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4423                                    &test_misc);
4424         if (status <= 0) {
4425                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4426                 return DP_TEST_NAK;
4427         }
4428         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4429                 return DP_TEST_NAK;
4430         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4431                 return DP_TEST_NAK;
4432         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4433         case DP_TEST_BIT_DEPTH_6:
4434                 intel_dp->compliance.test_data.bpc = 6;
4435                 break;
4436         case DP_TEST_BIT_DEPTH_8:
4437                 intel_dp->compliance.test_data.bpc = 8;
4438                 break;
4439         default:
4440                 return DP_TEST_NAK;
4441         }
4442
4443         intel_dp->compliance.test_data.video_pattern = test_pattern;
4444         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4445         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4446         /* Set test active flag here so userspace doesn't interrupt things */
4447         intel_dp->compliance.test_active = 1;
4448
4449         return DP_TEST_ACK;
4450 }
4451
4452 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4453 {
4454         u8 test_result = DP_TEST_ACK;
4455         struct intel_connector *intel_connector = intel_dp->attached_connector;
4456         struct drm_connector *connector = &intel_connector->base;
4457
4458         if (intel_connector->detect_edid == NULL ||
4459             connector->edid_corrupt ||
4460             intel_dp->aux.i2c_defer_count > 6) {
4461                 /* Check EDID read for NACKs, DEFERs and corruption
4462                  * (DP CTS 1.2 Core r1.1)
4463                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4464                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4465                  *    4.2.2.6 : EDID corruption detected
4466                  * Use failsafe mode for all cases
4467                  */
4468                 if (intel_dp->aux.i2c_nack_count > 0 ||
4469                         intel_dp->aux.i2c_defer_count > 0)
4470                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4471                                       intel_dp->aux.i2c_nack_count,
4472                                       intel_dp->aux.i2c_defer_count);
4473                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4474         } else {
4475                 struct edid *block = intel_connector->detect_edid;
4476
4477                 /* We have to write the checksum
4478                  * of the last block read
4479                  */
4480                 block += intel_connector->detect_edid->extensions;
4481
4482                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4483                                        block->checksum) <= 0)
4484                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4485
4486                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4487                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4488         }
4489
4490         /* Set test active flag here so userspace doesn't interrupt things */
4491         intel_dp->compliance.test_active = 1;
4492
4493         return test_result;
4494 }
4495
4496 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4497 {
4498         u8 test_result = DP_TEST_NAK;
4499         return test_result;
4500 }
4501
4502 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4503 {
4504         u8 response = DP_TEST_NAK;
4505         u8 request = 0;
4506         int status;
4507
4508         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4509         if (status <= 0) {
4510                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4511                 goto update_status;
4512         }
4513
4514         switch (request) {
4515         case DP_TEST_LINK_TRAINING:
4516                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4517                 response = intel_dp_autotest_link_training(intel_dp);
4518                 break;
4519         case DP_TEST_LINK_VIDEO_PATTERN:
4520                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4521                 response = intel_dp_autotest_video_pattern(intel_dp);
4522                 break;
4523         case DP_TEST_LINK_EDID_READ:
4524                 DRM_DEBUG_KMS("EDID test requested\n");
4525                 response = intel_dp_autotest_edid(intel_dp);
4526                 break;
4527         case DP_TEST_LINK_PHY_TEST_PATTERN:
4528                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4529                 response = intel_dp_autotest_phy_pattern(intel_dp);
4530                 break;
4531         default:
4532                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4533                 break;
4534         }
4535
4536         if (response & DP_TEST_ACK)
4537                 intel_dp->compliance.test_type = request;
4538
4539 update_status:
4540         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4541         if (status <= 0)
4542                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4543 }
4544
4545 static int
4546 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4547 {
4548         bool bret;
4549
4550         if (intel_dp->is_mst) {
4551                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4552                 int ret = 0;
4553                 int retry;
4554                 bool handled;
4555
4556                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4557                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4558 go_again:
4559                 if (bret == true) {
4560
4561                         /* check link status - esi[10] = 0x200c */
4562                         if (intel_dp->active_mst_links > 0 &&
4563                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4564                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4565                                 intel_dp_start_link_train(intel_dp);
4566                                 intel_dp_stop_link_train(intel_dp);
4567                         }
4568
4569                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4570                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4571
4572                         if (handled) {
4573                                 for (retry = 0; retry < 3; retry++) {
4574                                         int wret;
4575                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4576                                                                  DP_SINK_COUNT_ESI+1,
4577                                                                  &esi[1], 3);
4578                                         if (wret == 3) {
4579                                                 break;
4580                                         }
4581                                 }
4582
4583                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4584                                 if (bret == true) {
4585                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4586                                         goto go_again;
4587                                 }
4588                         } else
4589                                 ret = 0;
4590
4591                         return ret;
4592                 } else {
4593                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4594                         intel_dp->is_mst = false;
4595                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4596                                                         intel_dp->is_mst);
4597                 }
4598         }
4599         return -EINVAL;
4600 }
4601
4602 static bool
4603 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4604 {
4605         u8 link_status[DP_LINK_STATUS_SIZE];
4606
4607         if (!intel_dp->link_trained)
4608                 return false;
4609
4610         /*
4611          * While PSR source HW is enabled, it will control main-link sending
4612          * frames, enabling and disabling it so trying to do a retrain will fail
4613          * as the link would or not be on or it could mix training patterns
4614          * and frame data at the same time causing retrain to fail.
4615          * Also when exiting PSR, HW will retrain the link anyways fixing
4616          * any link status error.
4617          */
4618         if (intel_psr_enabled(intel_dp))
4619                 return false;
4620
4621         if (!intel_dp_get_link_status(intel_dp, link_status))
4622                 return false;
4623
4624         /*
4625          * Validate the cached values of intel_dp->link_rate and
4626          * intel_dp->lane_count before attempting to retrain.
4627          */
4628         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4629                                         intel_dp->lane_count))
4630                 return false;
4631
4632         /* Retrain if Channel EQ or CR not ok */
4633         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4634 }
4635
4636 int intel_dp_retrain_link(struct intel_encoder *encoder,
4637                           struct drm_modeset_acquire_ctx *ctx)
4638 {
4639         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4640         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4641         struct intel_connector *connector = intel_dp->attached_connector;
4642         struct drm_connector_state *conn_state;
4643         struct intel_crtc_state *crtc_state;
4644         struct intel_crtc *crtc;
4645         int ret;
4646
4647         /* FIXME handle the MST connectors as well */
4648
4649         if (!connector || connector->base.status != connector_status_connected)
4650                 return 0;
4651
4652         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4653                                ctx);
4654         if (ret)
4655                 return ret;
4656
4657         conn_state = connector->base.state;
4658
4659         crtc = to_intel_crtc(conn_state->crtc);
4660         if (!crtc)
4661                 return 0;
4662
4663         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4664         if (ret)
4665                 return ret;
4666
4667         crtc_state = to_intel_crtc_state(crtc->base.state);
4668
4669         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4670
4671         if (!crtc_state->base.active)
4672                 return 0;
4673
4674         if (conn_state->commit &&
4675             !try_wait_for_completion(&conn_state->commit->hw_done))
4676                 return 0;
4677
4678         if (!intel_dp_needs_link_retrain(intel_dp))
4679                 return 0;
4680
4681         /* Suppress underruns caused by re-training */
4682         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4683         if (crtc_state->has_pch_encoder)
4684                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4685                                                       intel_crtc_pch_transcoder(crtc), false);
4686
4687         intel_dp_start_link_train(intel_dp);
4688         intel_dp_stop_link_train(intel_dp);
4689
4690         /* Keep underrun reporting disabled until things are stable */
4691         intel_wait_for_vblank(dev_priv, crtc->pipe);
4692
4693         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4694         if (crtc_state->has_pch_encoder)
4695                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4696                                                       intel_crtc_pch_transcoder(crtc), true);
4697
4698         return 0;
4699 }
4700
4701 /*
4702  * If display is now connected check links status,
4703  * there has been known issues of link loss triggering
4704  * long pulse.
4705  *
4706  * Some sinks (eg. ASUS PB287Q) seem to perform some
4707  * weird HPD ping pong during modesets. So we can apparently
4708  * end up with HPD going low during a modeset, and then
4709  * going back up soon after. And once that happens we must
4710  * retrain the link to get a picture. That's in case no
4711  * userspace component reacted to intermittent HPD dip.
4712  */
4713 static bool intel_dp_hotplug(struct intel_encoder *encoder,
4714                              struct intel_connector *connector)
4715 {
4716         struct drm_modeset_acquire_ctx ctx;
4717         bool changed;
4718         int ret;
4719
4720         changed = intel_encoder_hotplug(encoder, connector);
4721
4722         drm_modeset_acquire_init(&ctx, 0);
4723
4724         for (;;) {
4725                 ret = intel_dp_retrain_link(encoder, &ctx);
4726
4727                 if (ret == -EDEADLK) {
4728                         drm_modeset_backoff(&ctx);
4729                         continue;
4730                 }
4731
4732                 break;
4733         }
4734
4735         drm_modeset_drop_locks(&ctx);
4736         drm_modeset_acquire_fini(&ctx);
4737         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4738
4739         return changed;
4740 }
4741
4742 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
4743 {
4744         u8 val;
4745
4746         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4747                 return;
4748
4749         if (drm_dp_dpcd_readb(&intel_dp->aux,
4750                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4751                 return;
4752
4753         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4754
4755         if (val & DP_AUTOMATED_TEST_REQUEST)
4756                 intel_dp_handle_test_request(intel_dp);
4757
4758         if (val & DP_CP_IRQ)
4759                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4760
4761         if (val & DP_SINK_SPECIFIC_IRQ)
4762                 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
4763 }
4764
4765 /*
4766  * According to DP spec
4767  * 5.1.2:
4768  *  1. Read DPCD
4769  *  2. Configure link according to Receiver Capabilities
4770  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4771  *  4. Check link status on receipt of hot-plug interrupt
4772  *
4773  * intel_dp_short_pulse -  handles short pulse interrupts
4774  * when full detection is not required.
4775  * Returns %true if short pulse is handled and full detection
4776  * is NOT required and %false otherwise.
4777  */
4778 static bool
4779 intel_dp_short_pulse(struct intel_dp *intel_dp)
4780 {
4781         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4782         u8 old_sink_count = intel_dp->sink_count;
4783         bool ret;
4784
4785         /*
4786          * Clearing compliance test variables to allow capturing
4787          * of values for next automated test request.
4788          */
4789         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4790
4791         /*
4792          * Now read the DPCD to see if it's actually running
4793          * If the current value of sink count doesn't match with
4794          * the value that was stored earlier or dpcd read failed
4795          * we need to do full detection
4796          */
4797         ret = intel_dp_get_dpcd(intel_dp);
4798
4799         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4800                 /* No need to proceed if we are going to do full detect */
4801                 return false;
4802         }
4803
4804         intel_dp_check_service_irq(intel_dp);
4805
4806         /* Handle CEC interrupts, if any */
4807         drm_dp_cec_irq(&intel_dp->aux);
4808
4809         /* defer to the hotplug work for link retraining if needed */
4810         if (intel_dp_needs_link_retrain(intel_dp))
4811                 return false;
4812
4813         intel_psr_short_pulse(intel_dp);
4814
4815         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4816                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4817                 /* Send a Hotplug Uevent to userspace to start modeset */
4818                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4819         }
4820
4821         return true;
4822 }
4823
4824 /* XXX this is probably wrong for multiple downstream ports */
4825 static enum drm_connector_status
4826 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4827 {
4828         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4829         u8 *dpcd = intel_dp->dpcd;
4830         u8 type;
4831
4832         if (lspcon->active)
4833                 lspcon_resume(lspcon);
4834
4835         if (!intel_dp_get_dpcd(intel_dp))
4836                 return connector_status_disconnected;
4837
4838         if (intel_dp_is_edp(intel_dp))
4839                 return connector_status_connected;
4840
4841         /* if there's no downstream port, we're done */
4842         if (!drm_dp_is_branch(dpcd))
4843                 return connector_status_connected;
4844
4845         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4846         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4847             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4848
4849                 return intel_dp->sink_count ?
4850                 connector_status_connected : connector_status_disconnected;
4851         }
4852
4853         if (intel_dp_can_mst(intel_dp))
4854                 return connector_status_connected;
4855
4856         /* If no HPD, poke DDC gently */
4857         if (drm_probe_ddc(&intel_dp->aux.ddc))
4858                 return connector_status_connected;
4859
4860         /* Well we tried, say unknown for unreliable port types */
4861         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4862                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4863                 if (type == DP_DS_PORT_TYPE_VGA ||
4864                     type == DP_DS_PORT_TYPE_NON_EDID)
4865                         return connector_status_unknown;
4866         } else {
4867                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4868                         DP_DWN_STRM_PORT_TYPE_MASK;
4869                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4870                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4871                         return connector_status_unknown;
4872         }
4873
4874         /* Anything else is out of spec, warn and ignore */
4875         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4876         return connector_status_disconnected;
4877 }
4878
4879 static enum drm_connector_status
4880 edp_detect(struct intel_dp *intel_dp)
4881 {
4882         return connector_status_connected;
4883 }
4884
4885 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4886 {
4887         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4888         u32 bit;
4889
4890         switch (encoder->hpd_pin) {
4891         case HPD_PORT_B:
4892                 bit = SDE_PORTB_HOTPLUG;
4893                 break;
4894         case HPD_PORT_C:
4895                 bit = SDE_PORTC_HOTPLUG;
4896                 break;
4897         case HPD_PORT_D:
4898                 bit = SDE_PORTD_HOTPLUG;
4899                 break;
4900         default:
4901                 MISSING_CASE(encoder->hpd_pin);
4902                 return false;
4903         }
4904
4905         return I915_READ(SDEISR) & bit;
4906 }
4907
4908 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4909 {
4910         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4911         u32 bit;
4912
4913         switch (encoder->hpd_pin) {
4914         case HPD_PORT_B:
4915                 bit = SDE_PORTB_HOTPLUG_CPT;
4916                 break;
4917         case HPD_PORT_C:
4918                 bit = SDE_PORTC_HOTPLUG_CPT;
4919                 break;
4920         case HPD_PORT_D:
4921                 bit = SDE_PORTD_HOTPLUG_CPT;
4922                 break;
4923         default:
4924                 MISSING_CASE(encoder->hpd_pin);
4925                 return false;
4926         }
4927
4928         return I915_READ(SDEISR) & bit;
4929 }
4930
4931 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4932 {
4933         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4934         u32 bit;
4935
4936         switch (encoder->hpd_pin) {
4937         case HPD_PORT_A:
4938                 bit = SDE_PORTA_HOTPLUG_SPT;
4939                 break;
4940         case HPD_PORT_E:
4941                 bit = SDE_PORTE_HOTPLUG_SPT;
4942                 break;
4943         default:
4944                 return cpt_digital_port_connected(encoder);
4945         }
4946
4947         return I915_READ(SDEISR) & bit;
4948 }
4949
4950 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4951 {
4952         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4953         u32 bit;
4954
4955         switch (encoder->hpd_pin) {
4956         case HPD_PORT_B:
4957                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4958                 break;
4959         case HPD_PORT_C:
4960                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4961                 break;
4962         case HPD_PORT_D:
4963                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4964                 break;
4965         default:
4966                 MISSING_CASE(encoder->hpd_pin);
4967                 return false;
4968         }
4969
4970         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4971 }
4972
4973 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4974 {
4975         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4976         u32 bit;
4977
4978         switch (encoder->hpd_pin) {
4979         case HPD_PORT_B:
4980                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4981                 break;
4982         case HPD_PORT_C:
4983                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4984                 break;
4985         case HPD_PORT_D:
4986                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4987                 break;
4988         default:
4989                 MISSING_CASE(encoder->hpd_pin);
4990                 return false;
4991         }
4992
4993         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4994 }
4995
4996 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
4997 {
4998         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4999
5000         if (encoder->hpd_pin == HPD_PORT_A)
5001                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5002         else
5003                 return ibx_digital_port_connected(encoder);
5004 }
5005
5006 static bool snb_digital_port_connected(struct intel_encoder *encoder)
5007 {
5008         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5009
5010         if (encoder->hpd_pin == HPD_PORT_A)
5011                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5012         else
5013                 return cpt_digital_port_connected(encoder);
5014 }
5015
5016 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
5017 {
5018         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5019
5020         if (encoder->hpd_pin == HPD_PORT_A)
5021                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
5022         else
5023                 return cpt_digital_port_connected(encoder);
5024 }
5025
5026 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5027 {
5028         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5029
5030         if (encoder->hpd_pin == HPD_PORT_A)
5031                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
5032         else
5033                 return cpt_digital_port_connected(encoder);
5034 }
5035
5036 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5037 {
5038         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5039         u32 bit;
5040
5041         switch (encoder->hpd_pin) {
5042         case HPD_PORT_A:
5043                 bit = BXT_DE_PORT_HP_DDIA;
5044                 break;
5045         case HPD_PORT_B:
5046                 bit = BXT_DE_PORT_HP_DDIB;
5047                 break;
5048         case HPD_PORT_C:
5049                 bit = BXT_DE_PORT_HP_DDIC;
5050                 break;
5051         default:
5052                 MISSING_CASE(encoder->hpd_pin);
5053                 return false;
5054         }
5055
5056         return I915_READ(GEN8_DE_PORT_ISR) & bit;
5057 }
5058
5059 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
5060                                      struct intel_digital_port *intel_dig_port)
5061 {
5062         enum port port = intel_dig_port->base.port;
5063
5064         return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
5065 }
5066
5067 static const char *tc_type_name(enum tc_port_type type)
5068 {
5069         static const char * const names[] = {
5070                 [TC_PORT_UNKNOWN] = "unknown",
5071                 [TC_PORT_LEGACY] = "legacy",
5072                 [TC_PORT_TYPEC] = "typec",
5073                 [TC_PORT_TBT] = "tbt",
5074         };
5075
5076         if (WARN_ON(type >= ARRAY_SIZE(names)))
5077                 type = TC_PORT_UNKNOWN;
5078
5079         return names[type];
5080 }
5081
5082 static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
5083                                     struct intel_digital_port *intel_dig_port,
5084                                     bool is_legacy, bool is_typec, bool is_tbt)
5085 {
5086         enum port port = intel_dig_port->base.port;
5087         enum tc_port_type old_type = intel_dig_port->tc_type;
5088
5089         WARN_ON(is_legacy + is_typec + is_tbt != 1);
5090
5091         if (is_legacy)
5092                 intel_dig_port->tc_type = TC_PORT_LEGACY;
5093         else if (is_typec)
5094                 intel_dig_port->tc_type = TC_PORT_TYPEC;
5095         else if (is_tbt)
5096                 intel_dig_port->tc_type = TC_PORT_TBT;
5097         else
5098                 return;
5099
5100         /* Types are not supposed to be changed at runtime. */
5101         WARN_ON(old_type != TC_PORT_UNKNOWN &&
5102                 old_type != intel_dig_port->tc_type);
5103
5104         if (old_type != intel_dig_port->tc_type)
5105                 DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
5106                               tc_type_name(intel_dig_port->tc_type));
5107 }
5108
5109 /*
5110  * This function implements the first part of the Connect Flow described by our
5111  * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
5112  * lanes, EDID, etc) is done as needed in the typical places.
5113  *
5114  * Unlike the other ports, type-C ports are not available to use as soon as we
5115  * get a hotplug. The type-C PHYs can be shared between multiple controllers:
5116  * display, USB, etc. As a result, handshaking through FIA is required around
5117  * connect and disconnect to cleanly transfer ownership with the controller and
5118  * set the type-C power state.
5119  *
5120  * We could opt to only do the connect flow when we actually try to use the AUX
5121  * channels or do a modeset, then immediately run the disconnect flow after
5122  * usage, but there are some implications on this for a dynamic environment:
5123  * things may go away or change behind our backs. So for now our driver is
5124  * always trying to acquire ownership of the controller as soon as it gets an
5125  * interrupt (or polls state and sees a port is connected) and only gives it
5126  * back when it sees a disconnect. Implementation of a more fine-grained model
5127  * will require a lot of coordination with user space and thorough testing for
5128  * the extra possible cases.
5129  */
5130 static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
5131                                struct intel_digital_port *dig_port)
5132 {
5133         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
5134         u32 val;
5135
5136         if (dig_port->tc_type != TC_PORT_LEGACY &&
5137             dig_port->tc_type != TC_PORT_TYPEC)
5138                 return true;
5139
5140         val = I915_READ(PORT_TX_DFLEXDPPMS);
5141         if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
5142                 DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
5143                 WARN_ON(dig_port->tc_legacy_port);
5144                 return false;
5145         }
5146
5147         /*
5148          * This function may be called many times in a row without an HPD event
5149          * in between, so try to avoid the write when we can.
5150          */
5151         val = I915_READ(PORT_TX_DFLEXDPCSSS);
5152         if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
5153                 val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
5154                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
5155         }
5156
5157         /*
5158          * Now we have to re-check the live state, in case the port recently
5159          * became disconnected. Not necessary for legacy mode.
5160          */
5161         if (dig_port->tc_type == TC_PORT_TYPEC &&
5162             !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
5163                 DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
5164                 icl_tc_phy_disconnect(dev_priv, dig_port);
5165                 return false;
5166         }
5167
5168         return true;
5169 }
5170
5171 /*
5172  * See the comment at the connect function. This implements the Disconnect
5173  * Flow.
5174  */
5175 void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
5176                            struct intel_digital_port *dig_port)
5177 {
5178         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
5179
5180         if (dig_port->tc_type == TC_PORT_UNKNOWN)
5181                 return;
5182
5183         /*
5184          * TBT disconnection flow is read the live status, what was done in
5185          * caller.
5186          */
5187         if (dig_port->tc_type == TC_PORT_TYPEC ||
5188             dig_port->tc_type == TC_PORT_LEGACY) {
5189                 u32 val;
5190
5191                 val = I915_READ(PORT_TX_DFLEXDPCSSS);
5192                 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
5193                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
5194         }
5195
5196         DRM_DEBUG_KMS("Port %c TC type %s disconnected\n",
5197                       port_name(dig_port->base.port),
5198                       tc_type_name(dig_port->tc_type));
5199
5200         dig_port->tc_type = TC_PORT_UNKNOWN;
5201 }
5202
5203 /*
5204  * The type-C ports are different because even when they are connected, they may
5205  * not be available/usable by the graphics driver: see the comment on
5206  * icl_tc_phy_connect(). So in our driver instead of adding the additional
5207  * concept of "usable" and make everything check for "connected and usable" we
5208  * define a port as "connected" when it is not only connected, but also when it
5209  * is usable by the rest of the driver. That maintains the old assumption that
5210  * connected ports are usable, and avoids exposing to the users objects they
5211  * can't really use.
5212  */
5213 static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
5214                                   struct intel_digital_port *intel_dig_port)
5215 {
5216         enum port port = intel_dig_port->base.port;
5217         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
5218         bool is_legacy, is_typec, is_tbt;
5219         u32 dpsp;
5220
5221         /*
5222          * WARN if we got a legacy port HPD, but VBT didn't mark the port as
5223          * legacy. Treat the port as legacy from now on.
5224          */
5225         if (WARN_ON(!intel_dig_port->tc_legacy_port &&
5226                     I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port)))
5227                 intel_dig_port->tc_legacy_port = true;
5228         is_legacy = intel_dig_port->tc_legacy_port;
5229
5230         /*
5231          * The spec says we shouldn't be using the ISR bits for detecting
5232          * between TC and TBT. We should use DFLEXDPSP.
5233          */
5234         dpsp = I915_READ(PORT_TX_DFLEXDPSP);
5235         is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
5236         is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
5237
5238         if (!is_legacy && !is_typec && !is_tbt) {
5239                 icl_tc_phy_disconnect(dev_priv, intel_dig_port);
5240
5241                 return false;
5242         }
5243
5244         icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
5245                                 is_tbt);
5246
5247         if (!icl_tc_phy_connect(dev_priv, intel_dig_port))
5248                 return false;
5249
5250         return true;
5251 }
5252
5253 static bool icl_digital_port_connected(struct intel_encoder *encoder)
5254 {
5255         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5256         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
5257
5258         if (intel_port_is_combophy(dev_priv, encoder->port))
5259                 return icl_combo_port_connected(dev_priv, dig_port);
5260         else if (intel_port_is_tc(dev_priv, encoder->port))
5261                 return icl_tc_port_connected(dev_priv, dig_port);
5262         else
5263                 MISSING_CASE(encoder->hpd_pin);
5264
5265         return false;
5266 }
5267
5268 /*
5269  * intel_digital_port_connected - is the specified port connected?
5270  * @encoder: intel_encoder
5271  *
5272  * In cases where there's a connector physically connected but it can't be used
5273  * by our hardware we also return false, since the rest of the driver should
5274  * pretty much treat the port as disconnected. This is relevant for type-C
5275  * (starting on ICL) where there's ownership involved.
5276  *
5277  * Return %true if port is connected, %false otherwise.
5278  */
5279 bool intel_digital_port_connected(struct intel_encoder *encoder)
5280 {
5281         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5282
5283         if (HAS_GMCH(dev_priv)) {
5284                 if (IS_GM45(dev_priv))
5285                         return gm45_digital_port_connected(encoder);
5286                 else
5287                         return g4x_digital_port_connected(encoder);
5288         }
5289
5290         if (INTEL_GEN(dev_priv) >= 11)
5291                 return icl_digital_port_connected(encoder);
5292         else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv))
5293                 return spt_digital_port_connected(encoder);
5294         else if (IS_GEN9_LP(dev_priv))
5295                 return bxt_digital_port_connected(encoder);
5296         else if (IS_GEN(dev_priv, 8))
5297                 return bdw_digital_port_connected(encoder);
5298         else if (IS_GEN(dev_priv, 7))
5299                 return ivb_digital_port_connected(encoder);
5300         else if (IS_GEN(dev_priv, 6))
5301                 return snb_digital_port_connected(encoder);
5302         else if (IS_GEN(dev_priv, 5))
5303                 return ilk_digital_port_connected(encoder);
5304
5305         MISSING_CASE(INTEL_GEN(dev_priv));
5306         return false;
5307 }
5308
5309 static struct edid *
5310 intel_dp_get_edid(struct intel_dp *intel_dp)
5311 {
5312         struct intel_connector *intel_connector = intel_dp->attached_connector;
5313
5314         /* use cached edid if we have one */
5315         if (intel_connector->edid) {
5316                 /* invalid edid */
5317                 if (IS_ERR(intel_connector->edid))
5318                         return NULL;
5319
5320                 return drm_edid_duplicate(intel_connector->edid);
5321         } else
5322                 return drm_get_edid(&intel_connector->base,
5323                                     &intel_dp->aux.ddc);
5324 }
5325
5326 static void
5327 intel_dp_set_edid(struct intel_dp *intel_dp)
5328 {
5329         struct intel_connector *intel_connector = intel_dp->attached_connector;
5330         struct edid *edid;
5331
5332         intel_dp_unset_edid(intel_dp);
5333         edid = intel_dp_get_edid(intel_dp);
5334         intel_connector->detect_edid = edid;
5335
5336         intel_dp->has_audio = drm_detect_monitor_audio(edid);
5337         drm_dp_cec_set_edid(&intel_dp->aux, edid);
5338 }
5339
5340 static void
5341 intel_dp_unset_edid(struct intel_dp *intel_dp)
5342 {
5343         struct intel_connector *intel_connector = intel_dp->attached_connector;
5344
5345         drm_dp_cec_unset_edid(&intel_dp->aux);
5346         kfree(intel_connector->detect_edid);
5347         intel_connector->detect_edid = NULL;
5348
5349         intel_dp->has_audio = false;
5350 }
5351
5352 static int
5353 intel_dp_detect(struct drm_connector *connector,
5354                 struct drm_modeset_acquire_ctx *ctx,
5355                 bool force)
5356 {
5357         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5358         struct intel_dp *intel_dp = intel_attached_dp(connector);
5359         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5360         struct intel_encoder *encoder = &dig_port->base;
5361         enum drm_connector_status status;
5362         enum intel_display_power_domain aux_domain =
5363                 intel_aux_power_domain(dig_port);
5364         intel_wakeref_t wakeref;
5365
5366         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5367                       connector->base.id, connector->name);
5368         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5369
5370         wakeref = intel_display_power_get(dev_priv, aux_domain);
5371
5372         /* Can't disconnect eDP */
5373         if (intel_dp_is_edp(intel_dp))
5374                 status = edp_detect(intel_dp);
5375         else if (intel_digital_port_connected(encoder))
5376                 status = intel_dp_detect_dpcd(intel_dp);
5377         else
5378                 status = connector_status_disconnected;
5379
5380         if (status == connector_status_disconnected) {
5381                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5382                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5383
5384                 if (intel_dp->is_mst) {
5385                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5386                                       intel_dp->is_mst,
5387                                       intel_dp->mst_mgr.mst_state);
5388                         intel_dp->is_mst = false;
5389                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5390                                                         intel_dp->is_mst);
5391                 }
5392
5393                 goto out;
5394         }
5395
5396         if (intel_dp->reset_link_params) {
5397                 /* Initial max link lane count */
5398                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5399
5400                 /* Initial max link rate */
5401                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5402
5403                 intel_dp->reset_link_params = false;
5404         }
5405
5406         intel_dp_print_rates(intel_dp);
5407
5408         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5409         if (INTEL_GEN(dev_priv) >= 11)
5410                 intel_dp_get_dsc_sink_cap(intel_dp);
5411
5412         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5413                          drm_dp_is_branch(intel_dp->dpcd));
5414
5415         intel_dp_configure_mst(intel_dp);
5416
5417         if (intel_dp->is_mst) {
5418                 /*
5419                  * If we are in MST mode then this connector
5420                  * won't appear connected or have anything
5421                  * with EDID on it
5422                  */
5423                 status = connector_status_disconnected;
5424                 goto out;
5425         }
5426
5427         /*
5428          * Some external monitors do not signal loss of link synchronization
5429          * with an IRQ_HPD, so force a link status check.
5430          */
5431         if (!intel_dp_is_edp(intel_dp)) {
5432                 int ret;
5433
5434                 ret = intel_dp_retrain_link(encoder, ctx);
5435                 if (ret) {
5436                         intel_display_power_put(dev_priv, aux_domain, wakeref);
5437                         return ret;
5438                 }
5439         }
5440
5441         /*
5442          * Clearing NACK and defer counts to get their exact values
5443          * while reading EDID which are required by Compliance tests
5444          * 4.2.2.4 and 4.2.2.5
5445          */
5446         intel_dp->aux.i2c_nack_count = 0;
5447         intel_dp->aux.i2c_defer_count = 0;
5448
5449         intel_dp_set_edid(intel_dp);
5450         if (intel_dp_is_edp(intel_dp) ||
5451             to_intel_connector(connector)->detect_edid)
5452                 status = connector_status_connected;
5453
5454         intel_dp_check_service_irq(intel_dp);
5455
5456 out:
5457         if (status != connector_status_connected && !intel_dp->is_mst)
5458                 intel_dp_unset_edid(intel_dp);
5459
5460         intel_display_power_put(dev_priv, aux_domain, wakeref);
5461         return status;
5462 }
5463
5464 static void
5465 intel_dp_force(struct drm_connector *connector)
5466 {
5467         struct intel_dp *intel_dp = intel_attached_dp(connector);
5468         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5469         struct intel_encoder *intel_encoder = &dig_port->base;
5470         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5471         enum intel_display_power_domain aux_domain =
5472                 intel_aux_power_domain(dig_port);
5473         intel_wakeref_t wakeref;
5474
5475         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5476                       connector->base.id, connector->name);
5477         intel_dp_unset_edid(intel_dp);
5478
5479         if (connector->status != connector_status_connected)
5480                 return;
5481
5482         wakeref = intel_display_power_get(dev_priv, aux_domain);
5483
5484         intel_dp_set_edid(intel_dp);
5485
5486         intel_display_power_put(dev_priv, aux_domain, wakeref);
5487 }
5488
5489 static int intel_dp_get_modes(struct drm_connector *connector)
5490 {
5491         struct intel_connector *intel_connector = to_intel_connector(connector);
5492         struct edid *edid;
5493
5494         edid = intel_connector->detect_edid;
5495         if (edid) {
5496                 int ret = intel_connector_update_modes(connector, edid);
5497                 if (ret)
5498                         return ret;
5499         }
5500
5501         /* if eDP has no EDID, fall back to fixed mode */
5502         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5503             intel_connector->panel.fixed_mode) {
5504                 struct drm_display_mode *mode;
5505
5506                 mode = drm_mode_duplicate(connector->dev,
5507                                           intel_connector->panel.fixed_mode);
5508                 if (mode) {
5509                         drm_mode_probed_add(connector, mode);
5510                         return 1;
5511                 }
5512         }
5513
5514         return 0;
5515 }
5516
5517 static int
5518 intel_dp_connector_register(struct drm_connector *connector)
5519 {
5520         struct intel_dp *intel_dp = intel_attached_dp(connector);
5521         struct drm_device *dev = connector->dev;
5522         int ret;
5523
5524         ret = intel_connector_register(connector);
5525         if (ret)
5526                 return ret;
5527
5528         i915_debugfs_connector_add(connector);
5529
5530         DRM_DEBUG_KMS("registering %s bus for %s\n",
5531                       intel_dp->aux.name, connector->kdev->kobj.name);
5532
5533         intel_dp->aux.dev = connector->kdev;
5534         ret = drm_dp_aux_register(&intel_dp->aux);
5535         if (!ret)
5536                 drm_dp_cec_register_connector(&intel_dp->aux,
5537                                               connector->name, dev->dev);
5538         return ret;
5539 }
5540
5541 static void
5542 intel_dp_connector_unregister(struct drm_connector *connector)
5543 {
5544         struct intel_dp *intel_dp = intel_attached_dp(connector);
5545
5546         drm_dp_cec_unregister_connector(&intel_dp->aux);
5547         drm_dp_aux_unregister(&intel_dp->aux);
5548         intel_connector_unregister(connector);
5549 }
5550
5551 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5552 {
5553         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5554         struct intel_dp *intel_dp = &intel_dig_port->dp;
5555
5556         intel_dp_mst_encoder_cleanup(intel_dig_port);
5557         if (intel_dp_is_edp(intel_dp)) {
5558                 intel_wakeref_t wakeref;
5559
5560                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5561                 /*
5562                  * vdd might still be enabled do to the delayed vdd off.
5563                  * Make sure vdd is actually turned off here.
5564                  */
5565                 with_pps_lock(intel_dp, wakeref)
5566                         edp_panel_vdd_off_sync(intel_dp);
5567
5568                 if (intel_dp->edp_notifier.notifier_call) {
5569                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5570                         intel_dp->edp_notifier.notifier_call = NULL;
5571                 }
5572         }
5573
5574         intel_dp_aux_fini(intel_dp);
5575 }
5576
5577 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5578 {
5579         intel_dp_encoder_flush_work(encoder);
5580
5581         drm_encoder_cleanup(encoder);
5582         kfree(enc_to_dig_port(encoder));
5583 }
5584
5585 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5586 {
5587         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5588         intel_wakeref_t wakeref;
5589
5590         if (!intel_dp_is_edp(intel_dp))
5591                 return;
5592
5593         /*
5594          * vdd might still be enabled do to the delayed vdd off.
5595          * Make sure vdd is actually turned off here.
5596          */
5597         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5598         with_pps_lock(intel_dp, wakeref)
5599                 edp_panel_vdd_off_sync(intel_dp);
5600 }
5601
5602 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
5603 {
5604         long ret;
5605
5606 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
5607         ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
5608                                                msecs_to_jiffies(timeout));
5609
5610         if (!ret)
5611                 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
5612 }
5613
5614 static
5615 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5616                                 u8 *an)
5617 {
5618         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5619         static const struct drm_dp_aux_msg msg = {
5620                 .request = DP_AUX_NATIVE_WRITE,
5621                 .address = DP_AUX_HDCP_AKSV,
5622                 .size = DRM_HDCP_KSV_LEN,
5623         };
5624         u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5625         ssize_t dpcd_ret;
5626         int ret;
5627
5628         /* Output An first, that's easy */
5629         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5630                                      an, DRM_HDCP_AN_LEN);
5631         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5632                 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5633                               dpcd_ret);
5634                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5635         }
5636
5637         /*
5638          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5639          * order to get it on the wire, we need to create the AUX header as if
5640          * we were writing the data, and then tickle the hardware to output the
5641          * data once the header is sent out.
5642          */
5643         intel_dp_aux_header(txbuf, &msg);
5644
5645         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5646                                 rxbuf, sizeof(rxbuf),
5647                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5648         if (ret < 0) {
5649                 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5650                 return ret;
5651         } else if (ret == 0) {
5652                 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5653                 return -EIO;
5654         }
5655
5656         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5657         if (reply != DP_AUX_NATIVE_REPLY_ACK) {
5658                 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
5659                               reply);
5660                 return -EIO;
5661         }
5662         return 0;
5663 }
5664
5665 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5666                                    u8 *bksv)
5667 {
5668         ssize_t ret;
5669         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5670                                DRM_HDCP_KSV_LEN);
5671         if (ret != DRM_HDCP_KSV_LEN) {
5672                 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5673                 return ret >= 0 ? -EIO : ret;
5674         }
5675         return 0;
5676 }
5677
5678 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5679                                       u8 *bstatus)
5680 {
5681         ssize_t ret;
5682         /*
5683          * For some reason the HDMI and DP HDCP specs call this register
5684          * definition by different names. In the HDMI spec, it's called BSTATUS,
5685          * but in DP it's called BINFO.
5686          */
5687         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5688                                bstatus, DRM_HDCP_BSTATUS_LEN);
5689         if (ret != DRM_HDCP_BSTATUS_LEN) {
5690                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5691                 return ret >= 0 ? -EIO : ret;
5692         }
5693         return 0;
5694 }
5695
5696 static
5697 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5698                              u8 *bcaps)
5699 {
5700         ssize_t ret;
5701
5702         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5703                                bcaps, 1);
5704         if (ret != 1) {
5705                 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
5706                 return ret >= 0 ? -EIO : ret;
5707         }
5708
5709         return 0;
5710 }
5711
5712 static
5713 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5714                                    bool *repeater_present)
5715 {
5716         ssize_t ret;
5717         u8 bcaps;
5718
5719         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5720         if (ret)
5721                 return ret;
5722
5723         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5724         return 0;
5725 }
5726
5727 static
5728 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5729                                 u8 *ri_prime)
5730 {
5731         ssize_t ret;
5732         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5733                                ri_prime, DRM_HDCP_RI_LEN);
5734         if (ret != DRM_HDCP_RI_LEN) {
5735                 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
5736                 return ret >= 0 ? -EIO : ret;
5737         }
5738         return 0;
5739 }
5740
5741 static
5742 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5743                                  bool *ksv_ready)
5744 {
5745         ssize_t ret;
5746         u8 bstatus;
5747         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5748                                &bstatus, 1);
5749         if (ret != 1) {
5750                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5751                 return ret >= 0 ? -EIO : ret;
5752         }
5753         *ksv_ready = bstatus & DP_BSTATUS_READY;
5754         return 0;
5755 }
5756
5757 static
5758 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5759                                 int num_downstream, u8 *ksv_fifo)
5760 {
5761         ssize_t ret;
5762         int i;
5763
5764         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5765         for (i = 0; i < num_downstream; i += 3) {
5766                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5767                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5768                                        DP_AUX_HDCP_KSV_FIFO,
5769                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5770                                        len);
5771                 if (ret != len) {
5772                         DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
5773                                       i, ret);
5774                         return ret >= 0 ? -EIO : ret;
5775                 }
5776         }
5777         return 0;
5778 }
5779
5780 static
5781 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5782                                     int i, u32 *part)
5783 {
5784         ssize_t ret;
5785
5786         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5787                 return -EINVAL;
5788
5789         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5790                                DP_AUX_HDCP_V_PRIME(i), part,
5791                                DRM_HDCP_V_PRIME_PART_LEN);
5792         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5793                 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5794                 return ret >= 0 ? -EIO : ret;
5795         }
5796         return 0;
5797 }
5798
5799 static
5800 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5801                                     bool enable)
5802 {
5803         /* Not used for single stream DisplayPort setups */
5804         return 0;
5805 }
5806
5807 static
5808 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5809 {
5810         ssize_t ret;
5811         u8 bstatus;
5812
5813         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5814                                &bstatus, 1);
5815         if (ret != 1) {
5816                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5817                 return false;
5818         }
5819
5820         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5821 }
5822
5823 static
5824 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5825                           bool *hdcp_capable)
5826 {
5827         ssize_t ret;
5828         u8 bcaps;
5829
5830         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5831         if (ret)
5832                 return ret;
5833
5834         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5835         return 0;
5836 }
5837
5838 struct hdcp2_dp_errata_stream_type {
5839         u8      msg_id;
5840         u8      stream_type;
5841 } __packed;
5842
5843 static struct hdcp2_dp_msg_data {
5844         u8 msg_id;
5845         u32 offset;
5846         bool msg_detectable;
5847         u32 timeout;
5848         u32 timeout2; /* Added for non_paired situation */
5849         } hdcp2_msg_data[] = {
5850                 {HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0},
5851                 {HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
5852                                 false, HDCP_2_2_CERT_TIMEOUT_MS, 0},
5853                 {HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
5854                                 false, 0, 0},
5855                 {HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
5856                                 false, 0, 0},
5857                 {HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
5858                                 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
5859                                 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS},
5860                 {HDCP_2_2_AKE_SEND_PAIRING_INFO,
5861                                 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
5862                                 HDCP_2_2_PAIRING_TIMEOUT_MS, 0},
5863                 {HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0},
5864                 {HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
5865                                 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0},
5866                 {HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
5867                                 0, 0},
5868                 {HDCP_2_2_REP_SEND_RECVID_LIST,
5869                                 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
5870                                 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0},
5871                 {HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
5872                                 0, 0},
5873                 {HDCP_2_2_REP_STREAM_MANAGE,
5874                                 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
5875                                 0, 0},
5876                 {HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
5877                                 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0},
5878 /* local define to shovel this through the write_2_2 interface */
5879 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE  50
5880                 {HDCP_2_2_ERRATA_DP_STREAM_TYPE,
5881                                 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
5882                                 0, 0},
5883                 };
5884
5885 static inline
5886 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
5887                                   u8 *rx_status)
5888 {
5889         ssize_t ret;
5890
5891         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5892                                DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
5893                                HDCP_2_2_DP_RXSTATUS_LEN);
5894         if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
5895                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5896                 return ret >= 0 ? -EIO : ret;
5897         }
5898
5899         return 0;
5900 }
5901
5902 static
5903 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
5904                                   u8 msg_id, bool *msg_ready)
5905 {
5906         u8 rx_status;
5907         int ret;
5908
5909         *msg_ready = false;
5910         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
5911         if (ret < 0)
5912                 return ret;
5913
5914         switch (msg_id) {
5915         case HDCP_2_2_AKE_SEND_HPRIME:
5916                 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
5917                         *msg_ready = true;
5918                 break;
5919         case HDCP_2_2_AKE_SEND_PAIRING_INFO:
5920                 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
5921                         *msg_ready = true;
5922                 break;
5923         case HDCP_2_2_REP_SEND_RECVID_LIST:
5924                 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
5925                         *msg_ready = true;
5926                 break;
5927         default:
5928                 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
5929                 return -EINVAL;
5930         }
5931
5932         return 0;
5933 }
5934
5935 static ssize_t
5936 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
5937                             struct hdcp2_dp_msg_data *hdcp2_msg_data)
5938 {
5939         struct intel_dp *dp = &intel_dig_port->dp;
5940         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
5941         u8 msg_id = hdcp2_msg_data->msg_id;
5942         int ret, timeout;
5943         bool msg_ready = false;
5944
5945         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
5946                 timeout = hdcp2_msg_data->timeout2;
5947         else
5948                 timeout = hdcp2_msg_data->timeout;
5949
5950         /*
5951          * There is no way to detect the CERT, LPRIME and STREAM_READY
5952          * availability. So Wait for timeout and read the msg.
5953          */
5954         if (!hdcp2_msg_data->msg_detectable) {
5955                 mdelay(timeout);
5956                 ret = 0;
5957         } else {
5958                 /*
5959                  * As we want to check the msg availability at timeout, Ignoring
5960                  * the timeout at wait for CP_IRQ.
5961                  */
5962                 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
5963                 ret = hdcp2_detect_msg_availability(intel_dig_port,
5964                                                     msg_id, &msg_ready);
5965                 if (!msg_ready)
5966                         ret = -ETIMEDOUT;
5967         }
5968
5969         if (ret)
5970                 DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n",
5971                               hdcp2_msg_data->msg_id, ret, timeout);
5972
5973         return ret;
5974 }
5975
5976 static struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
5977 {
5978         int i;
5979
5980         for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++)
5981                 if (hdcp2_msg_data[i].msg_id == msg_id)
5982                         return &hdcp2_msg_data[i];
5983
5984         return NULL;
5985 }
5986
5987 static
5988 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
5989                              void *buf, size_t size)
5990 {
5991         struct intel_dp *dp = &intel_dig_port->dp;
5992         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
5993         unsigned int offset;
5994         u8 *byte = buf;
5995         ssize_t ret, bytes_to_write, len;
5996         struct hdcp2_dp_msg_data *hdcp2_msg_data;
5997
5998         hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
5999         if (!hdcp2_msg_data)
6000                 return -EINVAL;
6001
6002         offset = hdcp2_msg_data->offset;
6003
6004         /* No msg_id in DP HDCP2.2 msgs */
6005         bytes_to_write = size - 1;
6006         byte++;
6007
6008         hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
6009
6010         while (bytes_to_write) {
6011                 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
6012                                 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
6013
6014                 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
6015                                         offset, (void *)byte, len);
6016                 if (ret < 0)
6017                         return ret;
6018
6019                 bytes_to_write -= ret;
6020                 byte += ret;
6021                 offset += ret;
6022         }
6023
6024         return size;
6025 }
6026
6027 static
6028 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6029 {
6030         u8 rx_info[HDCP_2_2_RXINFO_LEN];
6031         u32 dev_cnt;
6032         ssize_t ret;
6033
6034         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6035                                DP_HDCP_2_2_REG_RXINFO_OFFSET,
6036                                (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6037         if (ret != HDCP_2_2_RXINFO_LEN)
6038                 return ret >= 0 ? -EIO : ret;
6039
6040         dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6041                    HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6042
6043         if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6044                 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
6045
6046         ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
6047                 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
6048                 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
6049
6050         return ret;
6051 }
6052
6053 static
6054 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
6055                             u8 msg_id, void *buf, size_t size)
6056 {
6057         unsigned int offset;
6058         u8 *byte = buf;
6059         ssize_t ret, bytes_to_recv, len;
6060         struct hdcp2_dp_msg_data *hdcp2_msg_data;
6061
6062         hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
6063         if (!hdcp2_msg_data)
6064                 return -EINVAL;
6065         offset = hdcp2_msg_data->offset;
6066
6067         ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
6068         if (ret < 0)
6069                 return ret;
6070
6071         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
6072                 ret = get_receiver_id_list_size(intel_dig_port);
6073                 if (ret < 0)
6074                         return ret;
6075
6076                 size = ret;
6077         }
6078         bytes_to_recv = size - 1;
6079
6080         /* DP adaptation msgs has no msg_id */
6081         byte++;
6082
6083         while (bytes_to_recv) {
6084                 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
6085                       DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
6086
6087                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
6088                                        (void *)byte, len);
6089                 if (ret < 0) {
6090                         DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret);
6091                         return ret;
6092                 }
6093
6094                 bytes_to_recv -= ret;
6095                 byte += ret;
6096                 offset += ret;
6097         }
6098         byte = buf;
6099         *byte = msg_id;
6100
6101         return size;
6102 }
6103
6104 static
6105 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
6106                                       bool is_repeater, u8 content_type)
6107 {
6108         struct hdcp2_dp_errata_stream_type stream_type_msg;
6109
6110         if (is_repeater)
6111                 return 0;
6112
6113         /*
6114          * Errata for DP: As Stream type is used for encryption, Receiver
6115          * should be communicated with stream type for the decryption of the
6116          * content.
6117          * Repeater will be communicated with stream type as a part of it's
6118          * auth later in time.
6119          */
6120         stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
6121         stream_type_msg.stream_type = content_type;
6122
6123         return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
6124                                         sizeof(stream_type_msg));
6125 }
6126
6127 static
6128 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
6129 {
6130         u8 rx_status;
6131         int ret;
6132
6133         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6134         if (ret)
6135                 return ret;
6136
6137         if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
6138                 ret = HDCP_REAUTH_REQUEST;
6139         else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
6140                 ret = HDCP_LINK_INTEGRITY_FAILURE;
6141         else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6142                 ret = HDCP_TOPOLOGY_CHANGE;
6143
6144         return ret;
6145 }
6146
6147 static
6148 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
6149                            bool *capable)
6150 {
6151         u8 rx_caps[3];
6152         int ret;
6153
6154         *capable = false;
6155         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6156                                DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
6157                                rx_caps, HDCP_2_2_RXCAPS_LEN);
6158         if (ret != HDCP_2_2_RXCAPS_LEN)
6159                 return ret >= 0 ? -EIO : ret;
6160
6161         if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
6162             HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
6163                 *capable = true;
6164
6165         return 0;
6166 }
6167
6168 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
6169         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
6170         .read_bksv = intel_dp_hdcp_read_bksv,
6171         .read_bstatus = intel_dp_hdcp_read_bstatus,
6172         .repeater_present = intel_dp_hdcp_repeater_present,
6173         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
6174         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
6175         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
6176         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
6177         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
6178         .check_link = intel_dp_hdcp_check_link,
6179         .hdcp_capable = intel_dp_hdcp_capable,
6180         .write_2_2_msg = intel_dp_hdcp2_write_msg,
6181         .read_2_2_msg = intel_dp_hdcp2_read_msg,
6182         .config_stream_type = intel_dp_hdcp2_config_stream_type,
6183         .check_2_2_link = intel_dp_hdcp2_check_link,
6184         .hdcp_2_2_capable = intel_dp_hdcp2_capable,
6185         .protocol = HDCP_PROTOCOL_DP,
6186 };
6187
6188 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
6189 {
6190         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6191         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6192
6193         lockdep_assert_held(&dev_priv->pps_mutex);
6194
6195         if (!edp_have_panel_vdd(intel_dp))
6196                 return;
6197
6198         /*
6199          * The VDD bit needs a power domain reference, so if the bit is
6200          * already enabled when we boot or resume, grab this reference and
6201          * schedule a vdd off, so we don't hold on to the reference
6202          * indefinitely.
6203          */
6204         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
6205         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
6206
6207         edp_panel_vdd_schedule_off(intel_dp);
6208 }
6209
6210 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
6211 {
6212         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6213         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6214         enum pipe pipe;
6215
6216         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
6217                                   encoder->port, &pipe))
6218                 return pipe;
6219
6220         return INVALID_PIPE;
6221 }
6222
6223 void intel_dp_encoder_reset(struct drm_encoder *encoder)
6224 {
6225         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6226         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6227         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
6228         intel_wakeref_t wakeref;
6229
6230         if (!HAS_DDI(dev_priv))
6231                 intel_dp->DP = I915_READ(intel_dp->output_reg);
6232
6233         if (lspcon->active)
6234                 lspcon_resume(lspcon);
6235
6236         intel_dp->reset_link_params = true;
6237
6238         with_pps_lock(intel_dp, wakeref) {
6239                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6240                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6241
6242                 if (intel_dp_is_edp(intel_dp)) {
6243                         /*
6244                          * Reinit the power sequencer, in case BIOS did
6245                          * something nasty with it.
6246                          */
6247                         intel_dp_pps_init(intel_dp);
6248                         intel_edp_panel_vdd_sanitize(intel_dp);
6249                 }
6250         }
6251 }
6252
6253 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6254         .force = intel_dp_force,
6255         .fill_modes = drm_helper_probe_single_connector_modes,
6256         .atomic_get_property = intel_digital_connector_atomic_get_property,
6257         .atomic_set_property = intel_digital_connector_atomic_set_property,
6258         .late_register = intel_dp_connector_register,
6259         .early_unregister = intel_dp_connector_unregister,
6260         .destroy = intel_connector_destroy,
6261         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6262         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6263 };
6264
6265 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6266         .detect_ctx = intel_dp_detect,
6267         .get_modes = intel_dp_get_modes,
6268         .mode_valid = intel_dp_mode_valid,
6269         .atomic_check = intel_digital_connector_atomic_check,
6270 };
6271
6272 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6273         .reset = intel_dp_encoder_reset,
6274         .destroy = intel_dp_encoder_destroy,
6275 };
6276
6277 enum irqreturn
6278 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
6279 {
6280         struct intel_dp *intel_dp = &intel_dig_port->dp;
6281         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6282         enum irqreturn ret = IRQ_NONE;
6283         intel_wakeref_t wakeref;
6284
6285         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
6286                 /*
6287                  * vdd off can generate a long pulse on eDP which
6288                  * would require vdd on to handle it, and thus we
6289                  * would end up in an endless cycle of
6290                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
6291                  */
6292                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
6293                               port_name(intel_dig_port->base.port));
6294                 return IRQ_HANDLED;
6295         }
6296
6297         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
6298                       port_name(intel_dig_port->base.port),
6299                       long_hpd ? "long" : "short");
6300
6301         if (long_hpd) {
6302                 intel_dp->reset_link_params = true;
6303                 return IRQ_NONE;
6304         }
6305
6306         wakeref = intel_display_power_get(dev_priv,
6307                                           intel_aux_power_domain(intel_dig_port));
6308
6309         if (intel_dp->is_mst) {
6310                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
6311                         /*
6312                          * If we were in MST mode, and device is not
6313                          * there, get out of MST mode
6314                          */
6315                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
6316                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
6317                         intel_dp->is_mst = false;
6318                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6319                                                         intel_dp->is_mst);
6320                         goto put_power;
6321                 }
6322         }
6323
6324         if (!intel_dp->is_mst) {
6325                 bool handled;
6326
6327                 handled = intel_dp_short_pulse(intel_dp);
6328
6329                 if (!handled)
6330                         goto put_power;
6331         }
6332
6333         ret = IRQ_HANDLED;
6334
6335 put_power:
6336         intel_display_power_put(dev_priv,
6337                                 intel_aux_power_domain(intel_dig_port),
6338                                 wakeref);
6339
6340         return ret;
6341 }
6342
6343 /* check the VBT to see whether the eDP is on another port */
6344 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
6345 {
6346         /*
6347          * eDP not supported on g4x. so bail out early just
6348          * for a bit extra safety in case the VBT is bonkers.
6349          */
6350         if (INTEL_GEN(dev_priv) < 5)
6351                 return false;
6352
6353         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
6354                 return true;
6355
6356         return intel_bios_is_port_edp(dev_priv, port);
6357 }
6358
6359 static void
6360 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6361 {
6362         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6363         enum port port = dp_to_dig_port(intel_dp)->base.port;
6364
6365         if (!IS_G4X(dev_priv) && port != PORT_A)
6366                 intel_attach_force_audio_property(connector);
6367
6368         intel_attach_broadcast_rgb_property(connector);
6369         if (HAS_GMCH(dev_priv))
6370                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6371         else if (INTEL_GEN(dev_priv) >= 5)
6372                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6373
6374         if (intel_dp_is_edp(intel_dp)) {
6375                 u32 allowed_scalers;
6376
6377                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
6378                 if (!HAS_GMCH(dev_priv))
6379                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
6380
6381                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
6382
6383                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
6384
6385         }
6386 }
6387
6388 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
6389 {
6390         intel_dp->panel_power_off_time = ktime_get_boottime();
6391         intel_dp->last_power_on = jiffies;
6392         intel_dp->last_backlight_off = jiffies;
6393 }
6394
6395 static void
6396 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
6397 {
6398         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6399         u32 pp_on, pp_off, pp_ctl;
6400         struct pps_registers regs;
6401
6402         intel_pps_get_registers(intel_dp, &regs);
6403
6404         pp_ctl = ironlake_get_pp_control(intel_dp);
6405
6406         /* Ensure PPS is unlocked */
6407         if (!HAS_DDI(dev_priv))
6408                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6409
6410         pp_on = I915_READ(regs.pp_on);
6411         pp_off = I915_READ(regs.pp_off);
6412
6413         /* Pull timing values out of registers */
6414         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
6415         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
6416         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
6417         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
6418
6419         if (i915_mmio_reg_valid(regs.pp_div)) {
6420                 u32 pp_div;
6421
6422                 pp_div = I915_READ(regs.pp_div);
6423
6424                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
6425         } else {
6426                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
6427         }
6428 }
6429
6430 static void
6431 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6432 {
6433         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6434                       state_name,
6435                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6436 }
6437
6438 static void
6439 intel_pps_verify_state(struct intel_dp *intel_dp)
6440 {
6441         struct edp_power_seq hw;
6442         struct edp_power_seq *sw = &intel_dp->pps_delays;
6443
6444         intel_pps_readout_hw_state(intel_dp, &hw);
6445
6446         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6447             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6448                 DRM_ERROR("PPS state mismatch\n");
6449                 intel_pps_dump_state("sw", sw);
6450                 intel_pps_dump_state("hw", &hw);
6451         }
6452 }
6453
6454 static void
6455 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6456 {
6457         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6458         struct edp_power_seq cur, vbt, spec,
6459                 *final = &intel_dp->pps_delays;
6460
6461         lockdep_assert_held(&dev_priv->pps_mutex);
6462
6463         /* already initialized? */
6464         if (final->t11_t12 != 0)
6465                 return;
6466
6467         intel_pps_readout_hw_state(intel_dp, &cur);
6468
6469         intel_pps_dump_state("cur", &cur);
6470
6471         vbt = dev_priv->vbt.edp.pps;
6472         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6473          * of 500ms appears to be too short. Ocassionally the panel
6474          * just fails to power back on. Increasing the delay to 800ms
6475          * seems sufficient to avoid this problem.
6476          */
6477         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6478                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6479                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6480                               vbt.t11_t12);
6481         }
6482         /* T11_T12 delay is special and actually in units of 100ms, but zero
6483          * based in the hw (so we need to add 100 ms). But the sw vbt
6484          * table multiplies it with 1000 to make it in units of 100usec,
6485          * too. */
6486         vbt.t11_t12 += 100 * 10;
6487
6488         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6489          * our hw here, which are all in 100usec. */
6490         spec.t1_t3 = 210 * 10;
6491         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6492         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6493         spec.t10 = 500 * 10;
6494         /* This one is special and actually in units of 100ms, but zero
6495          * based in the hw (so we need to add 100 ms). But the sw vbt
6496          * table multiplies it with 1000 to make it in units of 100usec,
6497          * too. */
6498         spec.t11_t12 = (510 + 100) * 10;
6499
6500         intel_pps_dump_state("vbt", &vbt);
6501
6502         /* Use the max of the register settings and vbt. If both are
6503          * unset, fall back to the spec limits. */
6504 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
6505                                        spec.field : \
6506                                        max(cur.field, vbt.field))
6507         assign_final(t1_t3);
6508         assign_final(t8);
6509         assign_final(t9);
6510         assign_final(t10);
6511         assign_final(t11_t12);
6512 #undef assign_final
6513
6514 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
6515         intel_dp->panel_power_up_delay = get_delay(t1_t3);
6516         intel_dp->backlight_on_delay = get_delay(t8);
6517         intel_dp->backlight_off_delay = get_delay(t9);
6518         intel_dp->panel_power_down_delay = get_delay(t10);
6519         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6520 #undef get_delay
6521
6522         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6523                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
6524                       intel_dp->panel_power_cycle_delay);
6525
6526         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6527                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
6528
6529         /*
6530          * We override the HW backlight delays to 1 because we do manual waits
6531          * on them. For T8, even BSpec recommends doing it. For T9, if we
6532          * don't do this, we'll end up waiting for the backlight off delay
6533          * twice: once when we do the manual sleep, and once when we disable
6534          * the panel and wait for the PP_STATUS bit to become zero.
6535          */
6536         final->t8 = 1;
6537         final->t9 = 1;
6538
6539         /*
6540          * HW has only a 100msec granularity for t11_t12 so round it up
6541          * accordingly.
6542          */
6543         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6544 }
6545
6546 static void
6547 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6548                                               bool force_disable_vdd)
6549 {
6550         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6551         u32 pp_on, pp_off, port_sel = 0;
6552         int div = dev_priv->rawclk_freq / 1000;
6553         struct pps_registers regs;
6554         enum port port = dp_to_dig_port(intel_dp)->base.port;
6555         const struct edp_power_seq *seq = &intel_dp->pps_delays;
6556
6557         lockdep_assert_held(&dev_priv->pps_mutex);
6558
6559         intel_pps_get_registers(intel_dp, &regs);
6560
6561         /*
6562          * On some VLV machines the BIOS can leave the VDD
6563          * enabled even on power sequencers which aren't
6564          * hooked up to any port. This would mess up the
6565          * power domain tracking the first time we pick
6566          * one of these power sequencers for use since
6567          * edp_panel_vdd_on() would notice that the VDD was
6568          * already on and therefore wouldn't grab the power
6569          * domain reference. Disable VDD first to avoid this.
6570          * This also avoids spuriously turning the VDD on as
6571          * soon as the new power sequencer gets initialized.
6572          */
6573         if (force_disable_vdd) {
6574                 u32 pp = ironlake_get_pp_control(intel_dp);
6575
6576                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
6577
6578                 if (pp & EDP_FORCE_VDD)
6579                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
6580
6581                 pp &= ~EDP_FORCE_VDD;
6582
6583                 I915_WRITE(regs.pp_ctrl, pp);
6584         }
6585
6586         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
6587                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
6588         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
6589                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
6590
6591         /* Haswell doesn't have any port selection bits for the panel
6592          * power sequencer any more. */
6593         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6594                 port_sel = PANEL_PORT_SELECT_VLV(port);
6595         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6596                 switch (port) {
6597                 case PORT_A:
6598                         port_sel = PANEL_PORT_SELECT_DPA;
6599                         break;
6600                 case PORT_C:
6601                         port_sel = PANEL_PORT_SELECT_DPC;
6602                         break;
6603                 case PORT_D:
6604                         port_sel = PANEL_PORT_SELECT_DPD;
6605                         break;
6606                 default:
6607                         MISSING_CASE(port);
6608                         break;
6609                 }
6610         }
6611
6612         pp_on |= port_sel;
6613
6614         I915_WRITE(regs.pp_on, pp_on);
6615         I915_WRITE(regs.pp_off, pp_off);
6616
6617         /*
6618          * Compute the divisor for the pp clock, simply match the Bspec formula.
6619          */
6620         if (i915_mmio_reg_valid(regs.pp_div)) {
6621                 I915_WRITE(regs.pp_div,
6622                            REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) |
6623                            REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
6624         } else {
6625                 u32 pp_ctl;
6626
6627                 pp_ctl = I915_READ(regs.pp_ctrl);
6628                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
6629                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
6630                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6631         }
6632
6633         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6634                       I915_READ(regs.pp_on),
6635                       I915_READ(regs.pp_off),
6636                       i915_mmio_reg_valid(regs.pp_div) ?
6637                       I915_READ(regs.pp_div) :
6638                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
6639 }
6640
6641 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6642 {
6643         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6644
6645         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6646                 vlv_initial_power_sequencer_setup(intel_dp);
6647         } else {
6648                 intel_dp_init_panel_power_sequencer(intel_dp);
6649                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6650         }
6651 }
6652
6653 /**
6654  * intel_dp_set_drrs_state - program registers for RR switch to take effect
6655  * @dev_priv: i915 device
6656  * @crtc_state: a pointer to the active intel_crtc_state
6657  * @refresh_rate: RR to be programmed
6658  *
6659  * This function gets called when refresh rate (RR) has to be changed from
6660  * one frequency to another. Switches can be between high and low RR
6661  * supported by the panel or to any other RR based on media playback (in
6662  * this case, RR value needs to be passed from user space).
6663  *
6664  * The caller of this function needs to take a lock on dev_priv->drrs.
6665  */
6666 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6667                                     const struct intel_crtc_state *crtc_state,
6668                                     int refresh_rate)
6669 {
6670         struct intel_encoder *encoder;
6671         struct intel_digital_port *dig_port = NULL;
6672         struct intel_dp *intel_dp = dev_priv->drrs.dp;
6673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6674         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6675
6676         if (refresh_rate <= 0) {
6677                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6678                 return;
6679         }
6680
6681         if (intel_dp == NULL) {
6682                 DRM_DEBUG_KMS("DRRS not supported.\n");
6683                 return;
6684         }
6685
6686         dig_port = dp_to_dig_port(intel_dp);
6687         encoder = &dig_port->base;
6688
6689         if (!intel_crtc) {
6690                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6691                 return;
6692         }
6693
6694         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6695                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6696                 return;
6697         }
6698
6699         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6700                         refresh_rate)
6701                 index = DRRS_LOW_RR;
6702
6703         if (index == dev_priv->drrs.refresh_rate_type) {
6704                 DRM_DEBUG_KMS(
6705                         "DRRS requested for previously set RR...ignoring\n");
6706                 return;
6707         }
6708
6709         if (!crtc_state->base.active) {
6710                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6711                 return;
6712         }
6713
6714         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6715                 switch (index) {
6716                 case DRRS_HIGH_RR:
6717                         intel_dp_set_m_n(crtc_state, M1_N1);
6718                         break;
6719                 case DRRS_LOW_RR:
6720                         intel_dp_set_m_n(crtc_state, M2_N2);
6721                         break;
6722                 case DRRS_MAX_RR:
6723                 default:
6724                         DRM_ERROR("Unsupported refreshrate type\n");
6725                 }
6726         } else if (INTEL_GEN(dev_priv) > 6) {
6727                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6728                 u32 val;
6729
6730                 val = I915_READ(reg);
6731                 if (index > DRRS_HIGH_RR) {
6732                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6733                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6734                         else
6735                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6736                 } else {
6737                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6738                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6739                         else
6740                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6741                 }
6742                 I915_WRITE(reg, val);
6743         }
6744
6745         dev_priv->drrs.refresh_rate_type = index;
6746
6747         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6748 }
6749
6750 /**
6751  * intel_edp_drrs_enable - init drrs struct if supported
6752  * @intel_dp: DP struct
6753  * @crtc_state: A pointer to the active crtc state.
6754  *
6755  * Initializes frontbuffer_bits and drrs.dp
6756  */
6757 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6758                            const struct intel_crtc_state *crtc_state)
6759 {
6760         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6761
6762         if (!crtc_state->has_drrs) {
6763                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6764                 return;
6765         }
6766
6767         if (dev_priv->psr.enabled) {
6768                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6769                 return;
6770         }
6771
6772         mutex_lock(&dev_priv->drrs.mutex);
6773         if (dev_priv->drrs.dp) {
6774                 DRM_DEBUG_KMS("DRRS already enabled\n");
6775                 goto unlock;
6776         }
6777
6778         dev_priv->drrs.busy_frontbuffer_bits = 0;
6779
6780         dev_priv->drrs.dp = intel_dp;
6781
6782 unlock:
6783         mutex_unlock(&dev_priv->drrs.mutex);
6784 }
6785
6786 /**
6787  * intel_edp_drrs_disable - Disable DRRS
6788  * @intel_dp: DP struct
6789  * @old_crtc_state: Pointer to old crtc_state.
6790  *
6791  */
6792 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6793                             const struct intel_crtc_state *old_crtc_state)
6794 {
6795         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6796
6797         if (!old_crtc_state->has_drrs)
6798                 return;
6799
6800         mutex_lock(&dev_priv->drrs.mutex);
6801         if (!dev_priv->drrs.dp) {
6802                 mutex_unlock(&dev_priv->drrs.mutex);
6803                 return;
6804         }
6805
6806         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6807                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
6808                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
6809
6810         dev_priv->drrs.dp = NULL;
6811         mutex_unlock(&dev_priv->drrs.mutex);
6812
6813         cancel_delayed_work_sync(&dev_priv->drrs.work);
6814 }
6815
6816 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6817 {
6818         struct drm_i915_private *dev_priv =
6819                 container_of(work, typeof(*dev_priv), drrs.work.work);
6820         struct intel_dp *intel_dp;
6821
6822         mutex_lock(&dev_priv->drrs.mutex);
6823
6824         intel_dp = dev_priv->drrs.dp;
6825
6826         if (!intel_dp)
6827                 goto unlock;
6828
6829         /*
6830          * The delayed work can race with an invalidate hence we need to
6831          * recheck.
6832          */
6833
6834         if (dev_priv->drrs.busy_frontbuffer_bits)
6835                 goto unlock;
6836
6837         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6838                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6839
6840                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6841                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
6842         }
6843
6844 unlock:
6845         mutex_unlock(&dev_priv->drrs.mutex);
6846 }
6847
6848 /**
6849  * intel_edp_drrs_invalidate - Disable Idleness DRRS
6850  * @dev_priv: i915 device
6851  * @frontbuffer_bits: frontbuffer plane tracking bits
6852  *
6853  * This function gets called everytime rendering on the given planes start.
6854  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6855  *
6856  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6857  */
6858 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6859                                unsigned int frontbuffer_bits)
6860 {
6861         struct drm_crtc *crtc;
6862         enum pipe pipe;
6863
6864         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6865                 return;
6866
6867         cancel_delayed_work(&dev_priv->drrs.work);
6868
6869         mutex_lock(&dev_priv->drrs.mutex);
6870         if (!dev_priv->drrs.dp) {
6871                 mutex_unlock(&dev_priv->drrs.mutex);
6872                 return;
6873         }
6874
6875         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6876         pipe = to_intel_crtc(crtc)->pipe;
6877
6878         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6879         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6880
6881         /* invalidate means busy screen hence upclock */
6882         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6883                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6884                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6885
6886         mutex_unlock(&dev_priv->drrs.mutex);
6887 }
6888
6889 /**
6890  * intel_edp_drrs_flush - Restart Idleness DRRS
6891  * @dev_priv: i915 device
6892  * @frontbuffer_bits: frontbuffer plane tracking bits
6893  *
6894  * This function gets called every time rendering on the given planes has
6895  * completed or flip on a crtc is completed. So DRRS should be upclocked
6896  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6897  * if no other planes are dirty.
6898  *
6899  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6900  */
6901 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6902                           unsigned int frontbuffer_bits)
6903 {
6904         struct drm_crtc *crtc;
6905         enum pipe pipe;
6906
6907         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6908                 return;
6909
6910         cancel_delayed_work(&dev_priv->drrs.work);
6911
6912         mutex_lock(&dev_priv->drrs.mutex);
6913         if (!dev_priv->drrs.dp) {
6914                 mutex_unlock(&dev_priv->drrs.mutex);
6915                 return;
6916         }
6917
6918         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6919         pipe = to_intel_crtc(crtc)->pipe;
6920
6921         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6922         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6923
6924         /* flush means busy screen hence upclock */
6925         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6926                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6927                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6928
6929         /*
6930          * flush also means no more activity hence schedule downclock, if all
6931          * other fbs are quiescent too
6932          */
6933         if (!dev_priv->drrs.busy_frontbuffer_bits)
6934                 schedule_delayed_work(&dev_priv->drrs.work,
6935                                 msecs_to_jiffies(1000));
6936         mutex_unlock(&dev_priv->drrs.mutex);
6937 }
6938
6939 /**
6940  * DOC: Display Refresh Rate Switching (DRRS)
6941  *
6942  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6943  * which enables swtching between low and high refresh rates,
6944  * dynamically, based on the usage scenario. This feature is applicable
6945  * for internal panels.
6946  *
6947  * Indication that the panel supports DRRS is given by the panel EDID, which
6948  * would list multiple refresh rates for one resolution.
6949  *
6950  * DRRS is of 2 types - static and seamless.
6951  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6952  * (may appear as a blink on screen) and is used in dock-undock scenario.
6953  * Seamless DRRS involves changing RR without any visual effect to the user
6954  * and can be used during normal system usage. This is done by programming
6955  * certain registers.
6956  *
6957  * Support for static/seamless DRRS may be indicated in the VBT based on
6958  * inputs from the panel spec.
6959  *
6960  * DRRS saves power by switching to low RR based on usage scenarios.
6961  *
6962  * The implementation is based on frontbuffer tracking implementation.  When
6963  * there is a disturbance on the screen triggered by user activity or a periodic
6964  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6965  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6966  * made.
6967  *
6968  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6969  * and intel_edp_drrs_flush() are called.
6970  *
6971  * DRRS can be further extended to support other internal panels and also
6972  * the scenario of video playback wherein RR is set based on the rate
6973  * requested by userspace.
6974  */
6975
6976 /**
6977  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6978  * @connector: eDP connector
6979  * @fixed_mode: preferred mode of panel
6980  *
6981  * This function is  called only once at driver load to initialize basic
6982  * DRRS stuff.
6983  *
6984  * Returns:
6985  * Downclock mode if panel supports it, else return NULL.
6986  * DRRS support is determined by the presence of downclock mode (apart
6987  * from VBT setting).
6988  */
6989 static struct drm_display_mode *
6990 intel_dp_drrs_init(struct intel_connector *connector,
6991                    struct drm_display_mode *fixed_mode)
6992 {
6993         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6994         struct drm_display_mode *downclock_mode = NULL;
6995
6996         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6997         mutex_init(&dev_priv->drrs.mutex);
6998
6999         if (INTEL_GEN(dev_priv) <= 6) {
7000                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
7001                 return NULL;
7002         }
7003
7004         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
7005                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
7006                 return NULL;
7007         }
7008
7009         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
7010         if (!downclock_mode) {
7011                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
7012                 return NULL;
7013         }
7014
7015         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
7016
7017         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
7018         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
7019         return downclock_mode;
7020 }
7021
7022 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
7023                                      struct intel_connector *intel_connector)
7024 {
7025         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7026         struct drm_device *dev = &dev_priv->drm;
7027         struct drm_connector *connector = &intel_connector->base;
7028         struct drm_display_mode *fixed_mode = NULL;
7029         struct drm_display_mode *downclock_mode = NULL;
7030         bool has_dpcd;
7031         enum pipe pipe = INVALID_PIPE;
7032         intel_wakeref_t wakeref;
7033         struct edid *edid;
7034
7035         if (!intel_dp_is_edp(intel_dp))
7036                 return true;
7037
7038         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
7039
7040         /*
7041          * On IBX/CPT we may get here with LVDS already registered. Since the
7042          * driver uses the only internal power sequencer available for both
7043          * eDP and LVDS bail out early in this case to prevent interfering
7044          * with an already powered-on LVDS power sequencer.
7045          */
7046         if (intel_get_lvds_encoder(dev_priv)) {
7047                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7048                 DRM_INFO("LVDS was detected, not registering eDP\n");
7049
7050                 return false;
7051         }
7052
7053         with_pps_lock(intel_dp, wakeref) {
7054                 intel_dp_init_panel_power_timestamps(intel_dp);
7055                 intel_dp_pps_init(intel_dp);
7056                 intel_edp_panel_vdd_sanitize(intel_dp);
7057         }
7058
7059         /* Cache DPCD and EDID for edp. */
7060         has_dpcd = intel_edp_init_dpcd(intel_dp);
7061
7062         if (!has_dpcd) {
7063                 /* if this fails, presume the device is a ghost */
7064                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
7065                 goto out_vdd_off;
7066         }
7067
7068         mutex_lock(&dev->mode_config.mutex);
7069         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
7070         if (edid) {
7071                 if (drm_add_edid_modes(connector, edid)) {
7072                         drm_connector_update_edid_property(connector,
7073                                                                 edid);
7074                 } else {
7075                         kfree(edid);
7076                         edid = ERR_PTR(-EINVAL);
7077                 }
7078         } else {
7079                 edid = ERR_PTR(-ENOENT);
7080         }
7081         intel_connector->edid = edid;
7082
7083         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
7084         if (fixed_mode)
7085                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
7086
7087         /* fallback to VBT if available for eDP */
7088         if (!fixed_mode)
7089                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
7090         mutex_unlock(&dev->mode_config.mutex);
7091
7092         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7093                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
7094                 register_reboot_notifier(&intel_dp->edp_notifier);
7095
7096                 /*
7097                  * Figure out the current pipe for the initial backlight setup.
7098                  * If the current pipe isn't valid, try the PPS pipe, and if that
7099                  * fails just assume pipe A.
7100                  */
7101                 pipe = vlv_active_pipe(intel_dp);
7102
7103                 if (pipe != PIPE_A && pipe != PIPE_B)
7104                         pipe = intel_dp->pps_pipe;
7105
7106                 if (pipe != PIPE_A && pipe != PIPE_B)
7107                         pipe = PIPE_A;
7108
7109                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
7110                               pipe_name(pipe));
7111         }
7112
7113         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
7114         intel_connector->panel.backlight.power = intel_edp_backlight_power;
7115         intel_panel_setup_backlight(connector, pipe);
7116
7117         if (fixed_mode)
7118                 drm_connector_init_panel_orientation_property(
7119                         connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
7120
7121         return true;
7122
7123 out_vdd_off:
7124         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7125         /*
7126          * vdd might still be enabled do to the delayed vdd off.
7127          * Make sure vdd is actually turned off here.
7128          */
7129         with_pps_lock(intel_dp, wakeref)
7130                 edp_panel_vdd_off_sync(intel_dp);
7131
7132         return false;
7133 }
7134
7135 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
7136 {
7137         struct intel_connector *intel_connector;
7138         struct drm_connector *connector;
7139
7140         intel_connector = container_of(work, typeof(*intel_connector),
7141                                        modeset_retry_work);
7142         connector = &intel_connector->base;
7143         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
7144                       connector->name);
7145
7146         /* Grab the locks before changing connector property*/
7147         mutex_lock(&connector->dev->mode_config.mutex);
7148         /* Set connector link status to BAD and send a Uevent to notify
7149          * userspace to do a modeset.
7150          */
7151         drm_connector_set_link_status_property(connector,
7152                                                DRM_MODE_LINK_STATUS_BAD);
7153         mutex_unlock(&connector->dev->mode_config.mutex);
7154         /* Send Hotplug uevent so userspace can reprobe */
7155         drm_kms_helper_hotplug_event(connector->dev);
7156 }
7157
7158 bool
7159 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
7160                         struct intel_connector *intel_connector)
7161 {
7162         struct drm_connector *connector = &intel_connector->base;
7163         struct intel_dp *intel_dp = &intel_dig_port->dp;
7164         struct intel_encoder *intel_encoder = &intel_dig_port->base;
7165         struct drm_device *dev = intel_encoder->base.dev;
7166         struct drm_i915_private *dev_priv = to_i915(dev);
7167         enum port port = intel_encoder->port;
7168         int type;
7169
7170         /* Initialize the work for modeset in case of link train failure */
7171         INIT_WORK(&intel_connector->modeset_retry_work,
7172                   intel_dp_modeset_retry_work_fn);
7173
7174         if (WARN(intel_dig_port->max_lanes < 1,
7175                  "Not enough lanes (%d) for DP on port %c\n",
7176                  intel_dig_port->max_lanes, port_name(port)))
7177                 return false;
7178
7179         intel_dp_set_source_rates(intel_dp);
7180
7181         intel_dp->reset_link_params = true;
7182         intel_dp->pps_pipe = INVALID_PIPE;
7183         intel_dp->active_pipe = INVALID_PIPE;
7184
7185         /* intel_dp vfuncs */
7186         if (HAS_DDI(dev_priv))
7187                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
7188
7189         /* Preserve the current hw state. */
7190         intel_dp->DP = I915_READ(intel_dp->output_reg);
7191         intel_dp->attached_connector = intel_connector;
7192
7193         if (intel_dp_is_port_edp(dev_priv, port))
7194                 type = DRM_MODE_CONNECTOR_eDP;
7195         else
7196                 type = DRM_MODE_CONNECTOR_DisplayPort;
7197
7198         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7199                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7200
7201         /*
7202          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
7203          * for DP the encoder type can be set by the caller to
7204          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
7205          */
7206         if (type == DRM_MODE_CONNECTOR_eDP)
7207                 intel_encoder->type = INTEL_OUTPUT_EDP;
7208
7209         /* eDP only on port B and/or C on vlv/chv */
7210         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7211                     intel_dp_is_edp(intel_dp) &&
7212                     port != PORT_B && port != PORT_C))
7213                 return false;
7214
7215         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
7216                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
7217                         port_name(port));
7218
7219         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
7220         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
7221
7222         if (!HAS_GMCH(dev_priv))
7223                 connector->interlace_allowed = true;
7224         connector->doublescan_allowed = 0;
7225
7226         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
7227
7228         intel_dp_aux_init(intel_dp);
7229
7230         intel_connector_attach_encoder(intel_connector, intel_encoder);
7231
7232         if (HAS_DDI(dev_priv))
7233                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
7234         else
7235                 intel_connector->get_hw_state = intel_connector_get_hw_state;
7236
7237         /* init MST on ports that can support it */
7238         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
7239             (port == PORT_B || port == PORT_C ||
7240              port == PORT_D || port == PORT_F))
7241                 intel_dp_mst_encoder_init(intel_dig_port,
7242                                           intel_connector->base.base.id);
7243
7244         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
7245                 intel_dp_aux_fini(intel_dp);
7246                 intel_dp_mst_encoder_cleanup(intel_dig_port);
7247                 goto fail;
7248         }
7249
7250         intel_dp_add_properties(intel_dp, connector);
7251
7252         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
7253                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
7254                 if (ret)
7255                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
7256         }
7257
7258         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
7259          * 0xd.  Failure to do so will result in spurious interrupts being
7260          * generated on the port when a cable is not attached.
7261          */
7262         if (IS_G45(dev_priv)) {
7263                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
7264                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
7265         }
7266
7267         return true;
7268
7269 fail:
7270         drm_connector_cleanup(connector);
7271
7272         return false;
7273 }
7274
7275 bool intel_dp_init(struct drm_i915_private *dev_priv,
7276                    i915_reg_t output_reg,
7277                    enum port port)
7278 {
7279         struct intel_digital_port *intel_dig_port;
7280         struct intel_encoder *intel_encoder;
7281         struct drm_encoder *encoder;
7282         struct intel_connector *intel_connector;
7283
7284         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
7285         if (!intel_dig_port)
7286                 return false;
7287
7288         intel_connector = intel_connector_alloc();
7289         if (!intel_connector)
7290                 goto err_connector_alloc;
7291
7292         intel_encoder = &intel_dig_port->base;
7293         encoder = &intel_encoder->base;
7294
7295         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
7296                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
7297                              "DP %c", port_name(port)))
7298                 goto err_encoder_init;
7299
7300         intel_encoder->hotplug = intel_dp_hotplug;
7301         intel_encoder->compute_config = intel_dp_compute_config;
7302         intel_encoder->get_hw_state = intel_dp_get_hw_state;
7303         intel_encoder->get_config = intel_dp_get_config;
7304         intel_encoder->update_pipe = intel_panel_update_backlight;
7305         intel_encoder->suspend = intel_dp_encoder_suspend;
7306         if (IS_CHERRYVIEW(dev_priv)) {
7307                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
7308                 intel_encoder->pre_enable = chv_pre_enable_dp;
7309                 intel_encoder->enable = vlv_enable_dp;
7310                 intel_encoder->disable = vlv_disable_dp;
7311                 intel_encoder->post_disable = chv_post_disable_dp;
7312                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
7313         } else if (IS_VALLEYVIEW(dev_priv)) {
7314                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
7315                 intel_encoder->pre_enable = vlv_pre_enable_dp;
7316                 intel_encoder->enable = vlv_enable_dp;
7317                 intel_encoder->disable = vlv_disable_dp;
7318                 intel_encoder->post_disable = vlv_post_disable_dp;
7319         } else {
7320                 intel_encoder->pre_enable = g4x_pre_enable_dp;
7321                 intel_encoder->enable = g4x_enable_dp;
7322                 intel_encoder->disable = g4x_disable_dp;
7323                 intel_encoder->post_disable = g4x_post_disable_dp;
7324         }
7325
7326         intel_dig_port->dp.output_reg = output_reg;
7327         intel_dig_port->max_lanes = 4;
7328
7329         intel_encoder->type = INTEL_OUTPUT_DP;
7330         intel_encoder->power_domain = intel_port_to_power_domain(port);
7331         if (IS_CHERRYVIEW(dev_priv)) {
7332                 if (port == PORT_D)
7333                         intel_encoder->crtc_mask = 1 << 2;
7334                 else
7335                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
7336         } else {
7337                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
7338         }
7339         intel_encoder->cloneable = 0;
7340         intel_encoder->port = port;
7341
7342         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
7343
7344         if (port != PORT_A)
7345                 intel_infoframe_init(intel_dig_port);
7346
7347         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
7348         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
7349                 goto err_init_connector;
7350
7351         return true;
7352
7353 err_init_connector:
7354         drm_encoder_cleanup(encoder);
7355 err_encoder_init:
7356         kfree(intel_connector);
7357 err_connector_alloc:
7358         kfree(intel_dig_port);
7359         return false;
7360 }
7361
7362 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
7363 {
7364         struct intel_encoder *encoder;
7365
7366         for_each_intel_encoder(&dev_priv->drm, encoder) {
7367                 struct intel_dp *intel_dp;
7368
7369                 if (encoder->type != INTEL_OUTPUT_DDI)
7370                         continue;
7371
7372                 intel_dp = enc_to_intel_dp(&encoder->base);
7373
7374                 if (!intel_dp->can_mst)
7375                         continue;
7376
7377                 if (intel_dp->is_mst)
7378                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
7379         }
7380 }
7381
7382 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
7383 {
7384         struct intel_encoder *encoder;
7385
7386         for_each_intel_encoder(&dev_priv->drm, encoder) {
7387                 struct intel_dp *intel_dp;
7388                 int ret;
7389
7390                 if (encoder->type != INTEL_OUTPUT_DDI)
7391                         continue;
7392
7393                 intel_dp = enc_to_intel_dp(&encoder->base);
7394
7395                 if (!intel_dp->can_mst)
7396                         continue;
7397
7398                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
7399                 if (ret) {
7400                         intel_dp->is_mst = false;
7401                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7402                                                         false);
7403                 }
7404         }
7405 }