drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drm_atomic_helper.h>
  36 #include <drm/drm_crtc.h>
  37 #include <drm/drm_crtc_helper.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_hdcp.h>
  41 #include "intel_drv.h"
  42 #include <drm/i915_drm.h>
  43 #include "i915_drv.h"
  44
  45 #define DP_DPRX_ESI_LEN 14
  46
  47 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
  48 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER      61440
  49 #define DP_DSC_MIN_SUPPORTED_BPC                8
  50 #define DP_DSC_MAX_SUPPORTED_BPC                10
  51
  52 /* DP DSC throughput values used for slice count calculations KPixels/s */
  53 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  54 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  55 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  56
  57 /* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
  58 #define DP_DSC_FEC_OVERHEAD_FACTOR              976
  59
  60 /* Compliance test status bits  */
  61 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  62 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  63 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  64 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  65
  66 struct dp_link_dpll {
  67         int clock;
  68         struct dpll dpll;
  69 };
  70
  71 static const struct dp_link_dpll g4x_dpll[] = {
  72         { 162000,
  73                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  74         { 270000,
  75                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  76 };
  77
  78 static const struct dp_link_dpll pch_dpll[] = {
  79         { 162000,
  80                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  81         { 270000,
  82                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  83 };
  84
  85 static const struct dp_link_dpll vlv_dpll[] = {
  86         { 162000,
  87                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  88         { 270000,
  89                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  90 };
  91
  92 /*
  93  * CHV supports eDP 1.4 that have  more link rates.
  94  * Below only provides the fixed rate but exclude variable rate.
  95  */
  96 static const struct dp_link_dpll chv_dpll[] = {
  97         /*
  98          * CHV requires to program fractional division for m2.
  99          * m2 is stored in fixed point format using formula below
 100          * (m2_int << 22) | m2_fraction
 101          */
 102         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 103                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 104         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 105                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 106 };
 107
 108 /* Constants for DP DSC configurations */
 109 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 110
 111 /* With Single pipe configuration, HW is capable of supporting maximum
 112  * of 4 slices per line.
 113  */
 114 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 115
 116 /**
 117  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 118  * @intel_dp: DP struct
 119  *
 120  * If a CPU or PCH DP output is attached to an eDP panel, this function
 121  * will return true, and false otherwise.
 122  */
 123 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 124 {
 125         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 126
 127         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 128 }
 129
 130 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 131 {
 132         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 133 }
 134
 135 static void intel_dp_link_down(struct intel_encoder *encoder,
 136                                const struct intel_crtc_state *old_crtc_state);
 137 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 138 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 139 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 140                                            const struct intel_crtc_state *crtc_state);
 141 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 142                                       enum pipe pipe);
 143 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 144
 145 /* update sink rates from dpcd */
 146 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 147 {
 148         static const int dp_rates[] = {
 149                 162000, 270000, 540000, 810000
 150         };
 151         int i, max_rate;
 152
 153         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 154
 155         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 156                 if (dp_rates[i] > max_rate)
 157                         break;
 158                 intel_dp->sink_rates[i] = dp_rates[i];
 159         }
 160
 161         intel_dp->num_sink_rates = i;
 162 }
 163
 164 /* Get length of rates array potentially limited by max_rate. */
 165 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 166 {
 167         int i;
 168
 169         /* Limit results by potentially reduced max rate */
 170         for (i = 0; i < len; i++) {
 171                 if (rates[len - i - 1] <= max_rate)
 172                         return len - i;
 173         }
 174
 175         return 0;
 176 }
 177
 178 /* Get length of common rates array potentially limited by max_rate. */
 179 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 180                                           int max_rate)
 181 {
 182         return intel_dp_rate_limit_len(intel_dp->common_rates,
 183                                        intel_dp->num_common_rates, max_rate);
 184 }
 185
 186 /* Theoretical max between source and sink */
 187 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 188 {
 189         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 190 }
 191
 192 static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
 193 {
 194         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 195         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 196         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
 197         u32 lane_info;
 198
 199         if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
 200                 return 4;
 201
 202         lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
 203                      DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
 204                     DP_LANE_ASSIGNMENT_SHIFT(tc_port);
 205
 206         switch (lane_info) {
 207         default:
 208                 MISSING_CASE(lane_info);
 209         case 1:
 210         case 2:
 211         case 4:
 212         case 8:
 213                 return 1;
 214         case 3:
 215         case 12:
 216                 return 2;
 217         case 15:
 218                 return 4;
 219         }
 220 }
 221
 222 /* Theoretical max between source and sink */
 223 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 224 {
 225         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 226         int source_max = intel_dig_port->max_lanes;
 227         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 228         int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
 229
 230         return min3(source_max, sink_max, fia_max);
 231 }
 232
 233 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 234 {
 235         return intel_dp->max_link_lane_count;
 236 }
 237
 238 int
 239 intel_dp_link_required(int pixel_clock, int bpp)
 240 {
 241         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 242         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 243 }
 244
 245 int
 246 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 247 {
 248         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 249          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 250          * is transmitted every LS_Clk per lane, there is no need to account for
 251          * the channel encoding that is done in the PHY layer here.
 252          */
 253
 254         return max_link_clock * max_lanes;
 255 }
 256
 257 static int
 258 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 259 {
 260         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 261         struct intel_encoder *encoder = &intel_dig_port->base;
 262         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 263         int max_dotclk = dev_priv->max_dotclk_freq;
 264         int ds_max_dotclk;
 265
 266         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 267
 268         if (type != DP_DS_PORT_TYPE_VGA)
 269                 return max_dotclk;
 270
 271         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 272                                                     intel_dp->downstream_ports);
 273
 274         if (ds_max_dotclk != 0)
 275                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 276
 277         return max_dotclk;
 278 }
 279
 280 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 281 {
 282         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 283         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 284         enum port port = dig_port->base.port;
 285
 286         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 287
 288         /* Low voltage SKUs are limited to max of 5.4G */
 289         if (voltage == VOLTAGE_INFO_0_85V)
 290                 return 540000;
 291
 292         /* For this SKU 8.1G is supported in all ports */
 293         if (IS_CNL_WITH_PORT_F(dev_priv))
 294                 return 810000;
 295
 296         /* For other SKUs, max rate on ports A and D is 5.4G */
 297         if (port == PORT_A || port == PORT_D)
 298                 return 540000;
 299
 300         return 810000;
 301 }
 302
 303 static int icl_max_source_rate(struct intel_dp *intel_dp)
 304 {
 305         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 306         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 307         enum port port = dig_port->base.port;
 308
 309         if (intel_port_is_combophy(dev_priv, port) &&
 310             !intel_dp_is_edp(intel_dp))
 311                 return 540000;
 312
 313         return 810000;
 314 }
 315
 316 static void
 317 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 318 {
 319         /* The values must be in increasing order */
 320         static const int cnl_rates[] = {
 321                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 322         };
 323         static const int bxt_rates[] = {
 324                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 325         };
 326         static const int skl_rates[] = {
 327                 162000, 216000, 270000, 324000, 432000, 540000
 328         };
 329         static const int hsw_rates[] = {
 330                 162000, 270000, 540000
 331         };
 332         static const int g4x_rates[] = {
 333                 162000, 270000
 334         };
 335         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 336         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 337         const struct ddi_vbt_port_info *info =
 338                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 339         const int *source_rates;
 340         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 341
 342         /* This should only be done once */
 343         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 344
 345         if (INTEL_GEN(dev_priv) >= 10) {
 346                 source_rates = cnl_rates;
 347                 size = ARRAY_SIZE(cnl_rates);
 348                 if (IS_GEN(dev_priv, 10))
 349                         max_rate = cnl_max_source_rate(intel_dp);
 350                 else
 351                         max_rate = icl_max_source_rate(intel_dp);
 352         } else if (IS_GEN9_LP(dev_priv)) {
 353                 source_rates = bxt_rates;
 354                 size = ARRAY_SIZE(bxt_rates);
 355         } else if (IS_GEN9_BC(dev_priv)) {
 356                 source_rates = skl_rates;
 357                 size = ARRAY_SIZE(skl_rates);
 358         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 359                    IS_BROADWELL(dev_priv)) {
 360                 source_rates = hsw_rates;
 361                 size = ARRAY_SIZE(hsw_rates);
 362         } else {
 363                 source_rates = g4x_rates;
 364                 size = ARRAY_SIZE(g4x_rates);
 365         }
 366
 367         if (max_rate && vbt_max_rate)
 368                 max_rate = min(max_rate, vbt_max_rate);
 369         else if (vbt_max_rate)
 370                 max_rate = vbt_max_rate;
 371
 372         if (max_rate)
 373                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 374
 375         intel_dp->source_rates = source_rates;
 376         intel_dp->num_source_rates = size;
 377 }
 378
 379 static int intersect_rates(const int *source_rates, int source_len,
 380                            const int *sink_rates, int sink_len,
 381                            int *common_rates)
 382 {
 383         int i = 0, j = 0, k = 0;
 384
 385         while (i < source_len && j < sink_len) {
 386                 if (source_rates[i] == sink_rates[j]) {
 387                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 388                                 return k;
 389                         common_rates[k] = source_rates[i];
 390                         ++k;
 391                         ++i;
 392                         ++j;
 393                 } else if (source_rates[i] < sink_rates[j]) {
 394                         ++i;
 395                 } else {
 396                         ++j;
 397                 }
 398         }
 399         return k;
 400 }
 401
 402 /* return index of rate in rates array, or -1 if not found */
 403 static int intel_dp_rate_index(const int *rates, int len, int rate)
 404 {
 405         int i;
 406
 407         for (i = 0; i < len; i++)
 408                 if (rate == rates[i])
 409                         return i;
 410
 411         return -1;
 412 }
 413
 414 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 415 {
 416         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 417
 418         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 419                                                      intel_dp->num_source_rates,
 420                                                      intel_dp->sink_rates,
 421                                                      intel_dp->num_sink_rates,
 422                                                      intel_dp->common_rates);
 423
 424         /* Paranoia, there should always be something in common. */
 425         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 426                 intel_dp->common_rates[0] = 162000;
 427                 intel_dp->num_common_rates = 1;
 428         }
 429 }
 430
 431 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 432                                        uint8_t lane_count)
 433 {
 434         /*
 435          * FIXME: we need to synchronize the current link parameters with
 436          * hardware readout. Currently fast link training doesn't work on
 437          * boot-up.
 438          */
 439         if (link_rate == 0 ||
 440             link_rate > intel_dp->max_link_rate)
 441                 return false;
 442
 443         if (lane_count == 0 ||
 444             lane_count > intel_dp_max_lane_count(intel_dp))
 445                 return false;
 446
 447         return true;
 448 }
 449
 450 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 451                                                      int link_rate,
 452                                                      uint8_t lane_count)
 453 {
 454         const struct drm_display_mode *fixed_mode =
 455                 intel_dp->attached_connector->panel.fixed_mode;
 456         int mode_rate, max_rate;
 457
 458         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 459         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 460         if (mode_rate > max_rate)
 461                 return false;
 462
 463         return true;
 464 }
 465
 466 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 467                                             int link_rate, uint8_t lane_count)
 468 {
 469         int index;
 470
 471         index = intel_dp_rate_index(intel_dp->common_rates,
 472                                     intel_dp->num_common_rates,
 473                                     link_rate);
 474         if (index > 0) {
 475                 if (intel_dp_is_edp(intel_dp) &&
 476                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 477                                                               intel_dp->common_rates[index - 1],
 478                                                               lane_count)) {
 479                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 480                         return 0;
 481                 }
 482                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 483                 intel_dp->max_link_lane_count = lane_count;
 484         } else if (lane_count > 1) {
 485                 if (intel_dp_is_edp(intel_dp) &&
 486                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 487                                                               intel_dp_max_common_rate(intel_dp),
 488                                                               lane_count >> 1)) {
 489                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 490                         return 0;
 491                 }
 492                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 493                 intel_dp->max_link_lane_count = lane_count >> 1;
 494         } else {
 495                 DRM_ERROR("Link Training Unsuccessful\n");
 496                 return -1;
 497         }
 498
 499         return 0;
 500 }
 501
 502 static enum drm_mode_status
 503 intel_dp_mode_valid(struct drm_connector *connector,
 504                     struct drm_display_mode *mode)
 505 {
 506         struct intel_dp *intel_dp = intel_attached_dp(connector);
 507         struct intel_connector *intel_connector = to_intel_connector(connector);
 508         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 509         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 510         int target_clock = mode->clock;
 511         int max_rate, mode_rate, max_lanes, max_link_clock;
 512         int max_dotclk;
 513         u16 dsc_max_output_bpp = 0;
 514         u8 dsc_slice_count = 0;
 515
 516         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 517                 return MODE_NO_DBLESCAN;
 518
 519         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 520
 521         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 522                 if (mode->hdisplay > fixed_mode->hdisplay)
 523                         return MODE_PANEL;
 524
 525                 if (mode->vdisplay > fixed_mode->vdisplay)
 526                         return MODE_PANEL;
 527
 528                 target_clock = fixed_mode->clock;
 529         }
 530
 531         max_link_clock = intel_dp_max_link_rate(intel_dp);
 532         max_lanes = intel_dp_max_lane_count(intel_dp);
 533
 534         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 535         mode_rate = intel_dp_link_required(target_clock, 18);
 536
 537         /*
 538          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 539          * integer value since we support only integer values of bpp.
 540          */
 541         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 542             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 543                 if (intel_dp_is_edp(intel_dp)) {
 544                         dsc_max_output_bpp =
 545                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 546                         dsc_slice_count =
 547                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 548                                                                 true);
 549                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 550                         dsc_max_output_bpp =
 551                                 intel_dp_dsc_get_output_bpp(max_link_clock,
 552                                                             max_lanes,
 553                                                             target_clock,
 554                                                             mode->hdisplay) >> 4;
 555                         dsc_slice_count =
 556                                 intel_dp_dsc_get_slice_count(intel_dp,
 557                                                              target_clock,
 558                                                              mode->hdisplay);
 559                 }
 560         }
 561
 562         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
 563             target_clock > max_dotclk)
 564                 return MODE_CLOCK_HIGH;
 565
 566         if (mode->clock < 10000)
 567                 return MODE_CLOCK_LOW;
 568
 569         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 570                 return MODE_H_ILLEGAL;
 571
 572         return MODE_OK;
 573 }
 574
 575 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 576 {
 577         int     i;
 578         uint32_t v = 0;
 579
 580         if (src_bytes > 4)
 581                 src_bytes = 4;
 582         for (i = 0; i < src_bytes; i++)
 583                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 584         return v;
 585 }
 586
 587 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 588 {
 589         int i;
 590         if (dst_bytes > 4)
 591                 dst_bytes = 4;
 592         for (i = 0; i < dst_bytes; i++)
 593                 dst[i] = src >> ((3-i) * 8);
 594 }
 595
 596 static void
 597 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 598 static void
 599 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 600                                               bool force_disable_vdd);
 601 static void
 602 intel_dp_pps_init(struct intel_dp *intel_dp);
 603
 604 static intel_wakeref_t
 605 pps_lock(struct intel_dp *intel_dp)
 606 {
 607         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 608         intel_wakeref_t wakeref;
 609
 610         /*
 611          * See intel_power_sequencer_reset() why we need
 612          * a power domain reference here.
 613          */
 614         wakeref = intel_display_power_get(dev_priv,
 615                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 616
 617         mutex_lock(&dev_priv->pps_mutex);
 618
 619         return wakeref;
 620 }
 621
 622 static intel_wakeref_t
 623 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 624 {
 625         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 626
 627         mutex_unlock(&dev_priv->pps_mutex);
 628         intel_display_power_put(dev_priv,
 629                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 630                                 wakeref);
 631         return 0;
 632 }
 633
 634 #define with_pps_lock(dp, wf) \
 635         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 636
 637 static void
 638 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 639 {
 640         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 641         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 642         enum pipe pipe = intel_dp->pps_pipe;
 643         bool pll_enabled, release_cl_override = false;
 644         enum dpio_phy phy = DPIO_PHY(pipe);
 645         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 646         uint32_t DP;
 647
 648         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 649                  "skipping pipe %c power sequencer kick due to port %c being active\n",
 650                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 651                 return;
 652
 653         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 654                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 655
 656         /* Preserve the BIOS-computed detected bit. This is
 657          * supposed to be read-only.
 658          */
 659         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 660         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 661         DP |= DP_PORT_WIDTH(1);
 662         DP |= DP_LINK_TRAIN_PAT_1;
 663
 664         if (IS_CHERRYVIEW(dev_priv))
 665                 DP |= DP_PIPE_SEL_CHV(pipe);
 666         else
 667                 DP |= DP_PIPE_SEL(pipe);
 668
 669         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 670
 671         /*
 672          * The DPLL for the pipe must be enabled for this to work.
 673          * So enable temporarily it if it's not already enabled.
 674          */
 675         if (!pll_enabled) {
 676                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 677                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 678
 679                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 680                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 681                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 682                                   pipe_name(pipe));
 683                         return;
 684                 }
 685         }
 686
 687         /*
 688          * Similar magic as in intel_dp_enable_port().
 689          * We _must_ do this port enable + disable trick
 690          * to make this power sequencer lock onto the port.
 691          * Otherwise even VDD force bit won't work.
 692          */
 693         I915_WRITE(intel_dp->output_reg, DP);
 694         POSTING_READ(intel_dp->output_reg);
 695
 696         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 697         POSTING_READ(intel_dp->output_reg);
 698
 699         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 700         POSTING_READ(intel_dp->output_reg);
 701
 702         if (!pll_enabled) {
 703                 vlv_force_pll_off(dev_priv, pipe);
 704
 705                 if (release_cl_override)
 706                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 707         }
 708 }
 709
 710 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 711 {
 712         struct intel_encoder *encoder;
 713         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 714
 715         /*
 716          * We don't have power sequencer currently.
 717          * Pick one that's not used by other ports.
 718          */
 719         for_each_intel_dp(&dev_priv->drm, encoder) {
 720                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 721
 722                 if (encoder->type == INTEL_OUTPUT_EDP) {
 723                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 724                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 725
 726                         if (intel_dp->pps_pipe != INVALID_PIPE)
 727                                 pipes &= ~(1 << intel_dp->pps_pipe);
 728                 } else {
 729                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 730
 731                         if (intel_dp->active_pipe != INVALID_PIPE)
 732                                 pipes &= ~(1 << intel_dp->active_pipe);
 733                 }
 734         }
 735
 736         if (pipes == 0)
 737                 return INVALID_PIPE;
 738
 739         return ffs(pipes) - 1;
 740 }
 741
 742 static enum pipe
 743 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 744 {
 745         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 746         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 747         enum pipe pipe;
 748
 749         lockdep_assert_held(&dev_priv->pps_mutex);
 750
 751         /* We should never land here with regular DP ports */
 752         WARN_ON(!intel_dp_is_edp(intel_dp));
 753
 754         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 755                 intel_dp->active_pipe != intel_dp->pps_pipe);
 756
 757         if (intel_dp->pps_pipe != INVALID_PIPE)
 758                 return intel_dp->pps_pipe;
 759
 760         pipe = vlv_find_free_pps(dev_priv);
 761
 762         /*
 763          * Didn't find one. This should not happen since there
 764          * are two power sequencers and up to two eDP ports.
 765          */
 766         if (WARN_ON(pipe == INVALID_PIPE))
 767                 pipe = PIPE_A;
 768
 769         vlv_steal_power_sequencer(dev_priv, pipe);
 770         intel_dp->pps_pipe = pipe;
 771
 772         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 773                       pipe_name(intel_dp->pps_pipe),
 774                       port_name(intel_dig_port->base.port));
 775
 776         /* init power sequencer on this pipe and port */
 777         intel_dp_init_panel_power_sequencer(intel_dp);
 778         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 779
 780         /*
 781          * Even vdd force doesn't work until we've made
 782          * the power sequencer lock in on the port.
 783          */
 784         vlv_power_sequencer_kick(intel_dp);
 785
 786         return intel_dp->pps_pipe;
 787 }
 788
 789 static int
 790 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 791 {
 792         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 793         int backlight_controller = dev_priv->vbt.backlight.controller;
 794
 795         lockdep_assert_held(&dev_priv->pps_mutex);
 796
 797         /* We should never land here with regular DP ports */
 798         WARN_ON(!intel_dp_is_edp(intel_dp));
 799
 800         if (!intel_dp->pps_reset)
 801                 return backlight_controller;
 802
 803         intel_dp->pps_reset = false;
 804
 805         /*
 806          * Only the HW needs to be reprogrammed, the SW state is fixed and
 807          * has been setup during connector init.
 808          */
 809         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 810
 811         return backlight_controller;
 812 }
 813
 814 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 815                                enum pipe pipe);
 816
 817 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 818                                enum pipe pipe)
 819 {
 820         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 821 }
 822
 823 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 824                                 enum pipe pipe)
 825 {
 826         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 827 }
 828
 829 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 830                          enum pipe pipe)
 831 {
 832         return true;
 833 }
 834
 835 static enum pipe
 836 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 837                      enum port port,
 838                      vlv_pipe_check pipe_check)
 839 {
 840         enum pipe pipe;
 841
 842         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 843                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 844                         PANEL_PORT_SELECT_MASK;
 845
 846                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 847                         continue;
 848
 849                 if (!pipe_check(dev_priv, pipe))
 850                         continue;
 851
 852                 return pipe;
 853         }
 854
 855         return INVALID_PIPE;
 856 }
 857
 858 static void
 859 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 860 {
 861         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 862         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 863         enum port port = intel_dig_port->base.port;
 864
 865         lockdep_assert_held(&dev_priv->pps_mutex);
 866
 867         /* try to find a pipe with this port selected */
 868         /* first pick one where the panel is on */
 869         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 870                                                   vlv_pipe_has_pp_on);
 871         /* didn't find one? pick one where vdd is on */
 872         if (intel_dp->pps_pipe == INVALID_PIPE)
 873                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 874                                                           vlv_pipe_has_vdd_on);
 875         /* didn't find one? pick one with just the correct port */
 876         if (intel_dp->pps_pipe == INVALID_PIPE)
 877                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 878                                                           vlv_pipe_any);
 879
 880         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 881         if (intel_dp->pps_pipe == INVALID_PIPE) {
 882                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 883                               port_name(port));
 884                 return;
 885         }
 886
 887         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 888                       port_name(port), pipe_name(intel_dp->pps_pipe));
 889
 890         intel_dp_init_panel_power_sequencer(intel_dp);
 891         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 892 }
 893
 894 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 895 {
 896         struct intel_encoder *encoder;
 897
 898         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 899                     !IS_GEN9_LP(dev_priv)))
 900                 return;
 901
 902         /*
 903          * We can't grab pps_mutex here due to deadlock with power_domain
 904          * mutex when power_domain functions are called while holding pps_mutex.
 905          * That also means that in order to use pps_pipe the code needs to
 906          * hold both a power domain reference and pps_mutex, and the power domain
 907          * reference get/put must be done while _not_ holding pps_mutex.
 908          * pps_{lock,unlock}() do these steps in the correct order, so one
 909          * should use them always.
 910          */
 911
 912         for_each_intel_dp(&dev_priv->drm, encoder) {
 913                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 914
 915                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 916
 917                 if (encoder->type != INTEL_OUTPUT_EDP)
 918                         continue;
 919
 920                 if (IS_GEN9_LP(dev_priv))
 921                         intel_dp->pps_reset = true;
 922                 else
 923                         intel_dp->pps_pipe = INVALID_PIPE;
 924         }
 925 }
 926
 927 struct pps_registers {
 928         i915_reg_t pp_ctrl;
 929         i915_reg_t pp_stat;
 930         i915_reg_t pp_on;
 931         i915_reg_t pp_off;
 932         i915_reg_t pp_div;
 933 };
 934
 935 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 936                                     struct pps_registers *regs)
 937 {
 938         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 939         int pps_idx = 0;
 940
 941         memset(regs, 0, sizeof(*regs));
 942
 943         if (IS_GEN9_LP(dev_priv))
 944                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 945         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 946                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 947
 948         regs->pp_ctrl = PP_CONTROL(pps_idx);
 949         regs->pp_stat = PP_STATUS(pps_idx);
 950         regs->pp_on = PP_ON_DELAYS(pps_idx);
 951         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 952         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
 953             !HAS_PCH_ICP(dev_priv))
 954                 regs->pp_div = PP_DIVISOR(pps_idx);
 955 }
 956
 957 static i915_reg_t
 958 _pp_ctrl_reg(struct intel_dp *intel_dp)
 959 {
 960         struct pps_registers regs;
 961
 962         intel_pps_get_registers(intel_dp, &regs);
 963
 964         return regs.pp_ctrl;
 965 }
 966
 967 static i915_reg_t
 968 _pp_stat_reg(struct intel_dp *intel_dp)
 969 {
 970         struct pps_registers regs;
 971
 972         intel_pps_get_registers(intel_dp, &regs);
 973
 974         return regs.pp_stat;
 975 }
 976
 977 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 978    This function only applicable when panel PM state is not to be tracked */
 979 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 980                               void *unused)
 981 {
 982         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 983                                                  edp_notifier);
 984         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 985         intel_wakeref_t wakeref;
 986
 987         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 988                 return 0;
 989
 990         with_pps_lock(intel_dp, wakeref) {
 991                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 992                         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 993                         i915_reg_t pp_ctrl_reg, pp_div_reg;
 994                         u32 pp_div;
 995
 996                         pp_ctrl_reg = PP_CONTROL(pipe);
 997                         pp_div_reg  = PP_DIVISOR(pipe);
 998                         pp_div = I915_READ(pp_div_reg);
 999                         pp_div &= PP_REFERENCE_DIVIDER_MASK;
1000
1001                         /* 0x1F write to PP_DIV_REG sets max cycle delay */
1002                         I915_WRITE(pp_div_reg, pp_div | 0x1F);
1003                         I915_WRITE(pp_ctrl_reg,
1004                                    PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
1005                         msleep(intel_dp->panel_power_cycle_delay);
1006                 }
1007         }
1008
1009         return 0;
1010 }
1011
1012 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1013 {
1014         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1015
1016         lockdep_assert_held(&dev_priv->pps_mutex);
1017
1018         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1019             intel_dp->pps_pipe == INVALID_PIPE)
1020                 return false;
1021
1022         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1023 }
1024
1025 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1026 {
1027         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1028
1029         lockdep_assert_held(&dev_priv->pps_mutex);
1030
1031         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1032             intel_dp->pps_pipe == INVALID_PIPE)
1033                 return false;
1034
1035         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1036 }
1037
1038 static void
1039 intel_dp_check_edp(struct intel_dp *intel_dp)
1040 {
1041         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1042
1043         if (!intel_dp_is_edp(intel_dp))
1044                 return;
1045
1046         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1047                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1048                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1049                               I915_READ(_pp_stat_reg(intel_dp)),
1050                               I915_READ(_pp_ctrl_reg(intel_dp)));
1051         }
1052 }
1053
1054 static uint32_t
1055 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1056 {
1057         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1058         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1059         uint32_t status;
1060         bool done;
1061
1062 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1063         done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
1064                                   msecs_to_jiffies_timeout(10));
1065         if (!done)
1066                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1067 #undef C
1068
1069         return status;
1070 }
1071
1072 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1073 {
1074         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1075
1076         if (index)
1077                 return 0;
1078
1079         /*
1080          * The clock divider is based off the hrawclk, and would like to run at
1081          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1082          */
1083         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1084 }
1085
1086 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1087 {
1088         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1089         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1090
1091         if (index)
1092                 return 0;
1093
1094         /*
1095          * The clock divider is based off the cdclk or PCH rawclk, and would
1096          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1097          * divide by 2000 and use that
1098          */
1099         if (dig_port->aux_ch == AUX_CH_A)
1100                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1101         else
1102                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1103 }
1104
1105 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1106 {
1107         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1108         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1109
1110         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1111                 /* Workaround for non-ULT HSW */
1112                 switch (index) {
1113                 case 0: return 63;
1114                 case 1: return 72;
1115                 default: return 0;
1116                 }
1117         }
1118
1119         return ilk_get_aux_clock_divider(intel_dp, index);
1120 }
1121
1122 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1123 {
1124         /*
1125          * SKL doesn't need us to program the AUX clock divider (Hardware will
1126          * derive the clock from CDCLK automatically). We still implement the
1127          * get_aux_clock_divider vfunc to plug-in into the existing code.
1128          */
1129         return index ? 0 : 1;
1130 }
1131
1132 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1133                                      int send_bytes,
1134                                      uint32_t aux_clock_divider)
1135 {
1136         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1137         struct drm_i915_private *dev_priv =
1138                         to_i915(intel_dig_port->base.base.dev);
1139         uint32_t precharge, timeout;
1140
1141         if (IS_GEN(dev_priv, 6))
1142                 precharge = 3;
1143         else
1144                 precharge = 5;
1145
1146         if (IS_BROADWELL(dev_priv))
1147                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1148         else
1149                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1150
1151         return DP_AUX_CH_CTL_SEND_BUSY |
1152                DP_AUX_CH_CTL_DONE |
1153                DP_AUX_CH_CTL_INTERRUPT |
1154                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1155                timeout |
1156                DP_AUX_CH_CTL_RECEIVE_ERROR |
1157                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1158                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1159                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1160 }
1161
1162 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1163                                       int send_bytes,
1164                                       uint32_t unused)
1165 {
1166         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1167         uint32_t ret;
1168
1169         ret = DP_AUX_CH_CTL_SEND_BUSY |
1170               DP_AUX_CH_CTL_DONE |
1171               DP_AUX_CH_CTL_INTERRUPT |
1172               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1173               DP_AUX_CH_CTL_TIME_OUT_MAX |
1174               DP_AUX_CH_CTL_RECEIVE_ERROR |
1175               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1176               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1177               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1178
1179         if (intel_dig_port->tc_type == TC_PORT_TBT)
1180                 ret |= DP_AUX_CH_CTL_TBT_IO;
1181
1182         return ret;
1183 }
1184
1185 static int
1186 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1187                   const uint8_t *send, int send_bytes,
1188                   uint8_t *recv, int recv_size,
1189                   u32 aux_send_ctl_flags)
1190 {
1191         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1192         struct drm_i915_private *dev_priv =
1193                         to_i915(intel_dig_port->base.base.dev);
1194         i915_reg_t ch_ctl, ch_data[5];
1195         uint32_t aux_clock_divider;
1196         intel_wakeref_t wakeref;
1197         int i, ret, recv_bytes;
1198         int try, clock = 0;
1199         uint32_t status;
1200         bool vdd;
1201
1202         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1203         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1204                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1205
1206         wakeref = pps_lock(intel_dp);
1207
1208         /*
1209          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1210          * In such cases we want to leave VDD enabled and it's up to upper layers
1211          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1212          * ourselves.
1213          */
1214         vdd = edp_panel_vdd_on(intel_dp);
1215
1216         /* dp aux is extremely sensitive to irq latency, hence request the
1217          * lowest possible wakeup latency and so prevent the cpu from going into
1218          * deep sleep states.
1219          */
1220         pm_qos_update_request(&dev_priv->pm_qos, 0);
1221
1222         intel_dp_check_edp(intel_dp);
1223
1224         /* Try to wait for any previous AUX channel activity */
1225         for (try = 0; try < 3; try++) {
1226                 status = I915_READ_NOTRACE(ch_ctl);
1227                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1228                         break;
1229                 msleep(1);
1230         }
1231
1232         if (try == 3) {
1233                 static u32 last_status = -1;
1234                 const u32 status = I915_READ(ch_ctl);
1235
1236                 if (status != last_status) {
1237                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1238                              status);
1239                         last_status = status;
1240                 }
1241
1242                 ret = -EBUSY;
1243                 goto out;
1244         }
1245
1246         /* Only 5 data registers! */
1247         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1248                 ret = -E2BIG;
1249                 goto out;
1250         }
1251
1252         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1253                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1254                                                           send_bytes,
1255                                                           aux_clock_divider);
1256
1257                 send_ctl |= aux_send_ctl_flags;
1258
1259                 /* Must try at least 3 times according to DP spec */
1260                 for (try = 0; try < 5; try++) {
1261                         /* Load the send data into the aux channel data registers */
1262                         for (i = 0; i < send_bytes; i += 4)
1263                                 I915_WRITE(ch_data[i >> 2],
1264                                            intel_dp_pack_aux(send + i,
1265                                                              send_bytes - i));
1266
1267                         /* Send the command and wait for it to complete */
1268                         I915_WRITE(ch_ctl, send_ctl);
1269
1270                         status = intel_dp_aux_wait_done(intel_dp);
1271
1272                         /* Clear done status and any errors */
1273                         I915_WRITE(ch_ctl,
1274                                    status |
1275                                    DP_AUX_CH_CTL_DONE |
1276                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1277                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1278
1279                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1280                          *   400us delay required for errors and timeouts
1281                          *   Timeout errors from the HW already meet this
1282                          *   requirement so skip to next iteration
1283                          */
1284                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1285                                 continue;
1286
1287                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1288                                 usleep_range(400, 500);
1289                                 continue;
1290                         }
1291                         if (status & DP_AUX_CH_CTL_DONE)
1292                                 goto done;
1293                 }
1294         }
1295
1296         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1297                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1298                 ret = -EBUSY;
1299                 goto out;
1300         }
1301
1302 done:
1303         /* Check for timeout or receive error.
1304          * Timeouts occur when the sink is not connected
1305          */
1306         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1307                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1308                 ret = -EIO;
1309                 goto out;
1310         }
1311
1312         /* Timeouts occur when the device isn't connected, so they're
1313          * "normal" -- don't fill the kernel log with these */
1314         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1315                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1316                 ret = -ETIMEDOUT;
1317                 goto out;
1318         }
1319
1320         /* Unload any bytes sent back from the other side */
1321         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1322                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1323
1324         /*
1325          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1326          * We have no idea of what happened so we return -EBUSY so
1327          * drm layer takes care for the necessary retries.
1328          */
1329         if (recv_bytes == 0 || recv_bytes > 20) {
1330                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1331                               recv_bytes);
1332                 ret = -EBUSY;
1333                 goto out;
1334         }
1335
1336         if (recv_bytes > recv_size)
1337                 recv_bytes = recv_size;
1338
1339         for (i = 0; i < recv_bytes; i += 4)
1340                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1341                                     recv + i, recv_bytes - i);
1342
1343         ret = recv_bytes;
1344 out:
1345         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1346
1347         if (vdd)
1348                 edp_panel_vdd_off(intel_dp, false);
1349
1350         pps_unlock(intel_dp, wakeref);
1351
1352         return ret;
1353 }
1354
1355 #define BARE_ADDRESS_SIZE       3
1356 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1357
1358 static void
1359 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1360                     const struct drm_dp_aux_msg *msg)
1361 {
1362         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1363         txbuf[1] = (msg->address >> 8) & 0xff;
1364         txbuf[2] = msg->address & 0xff;
1365         txbuf[3] = msg->size - 1;
1366 }
1367
1368 static ssize_t
1369 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1370 {
1371         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1372         uint8_t txbuf[20], rxbuf[20];
1373         size_t txsize, rxsize;
1374         int ret;
1375
1376         intel_dp_aux_header(txbuf, msg);
1377
1378         switch (msg->request & ~DP_AUX_I2C_MOT) {
1379         case DP_AUX_NATIVE_WRITE:
1380         case DP_AUX_I2C_WRITE:
1381         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1382                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1383                 rxsize = 2; /* 0 or 1 data bytes */
1384
1385                 if (WARN_ON(txsize > 20))
1386                         return -E2BIG;
1387
1388                 WARN_ON(!msg->buffer != !msg->size);
1389
1390                 if (msg->buffer)
1391                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1392
1393                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1394                                         rxbuf, rxsize, 0);
1395                 if (ret > 0) {
1396                         msg->reply = rxbuf[0] >> 4;
1397
1398                         if (ret > 1) {
1399                                 /* Number of bytes written in a short write. */
1400                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1401                         } else {
1402                                 /* Return payload size. */
1403                                 ret = msg->size;
1404                         }
1405                 }
1406                 break;
1407
1408         case DP_AUX_NATIVE_READ:
1409         case DP_AUX_I2C_READ:
1410                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1411                 rxsize = msg->size + 1;
1412
1413                 if (WARN_ON(rxsize > 20))
1414                         return -E2BIG;
1415
1416                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1417                                         rxbuf, rxsize, 0);
1418                 if (ret > 0) {
1419                         msg->reply = rxbuf[0] >> 4;
1420                         /*
1421                          * Assume happy day, and copy the data. The caller is
1422                          * expected to check msg->reply before touching it.
1423                          *
1424                          * Return payload size.
1425                          */
1426                         ret--;
1427                         memcpy(msg->buffer, rxbuf + 1, ret);
1428                 }
1429                 break;
1430
1431         default:
1432                 ret = -EINVAL;
1433                 break;
1434         }
1435
1436         return ret;
1437 }
1438
1439
1440 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1441 {
1442         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1443         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1444         enum aux_ch aux_ch = dig_port->aux_ch;
1445
1446         switch (aux_ch) {
1447         case AUX_CH_B:
1448         case AUX_CH_C:
1449         case AUX_CH_D:
1450                 return DP_AUX_CH_CTL(aux_ch);
1451         default:
1452                 MISSING_CASE(aux_ch);
1453                 return DP_AUX_CH_CTL(AUX_CH_B);
1454         }
1455 }
1456
1457 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1458 {
1459         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1460         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1461         enum aux_ch aux_ch = dig_port->aux_ch;
1462
1463         switch (aux_ch) {
1464         case AUX_CH_B:
1465         case AUX_CH_C:
1466         case AUX_CH_D:
1467                 return DP_AUX_CH_DATA(aux_ch, index);
1468         default:
1469                 MISSING_CASE(aux_ch);
1470                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1471         }
1472 }
1473
1474 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1475 {
1476         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1477         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1478         enum aux_ch aux_ch = dig_port->aux_ch;
1479
1480         switch (aux_ch) {
1481         case AUX_CH_A:
1482                 return DP_AUX_CH_CTL(aux_ch);
1483         case AUX_CH_B:
1484         case AUX_CH_C:
1485         case AUX_CH_D:
1486                 return PCH_DP_AUX_CH_CTL(aux_ch);
1487         default:
1488                 MISSING_CASE(aux_ch);
1489                 return DP_AUX_CH_CTL(AUX_CH_A);
1490         }
1491 }
1492
1493 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1494 {
1495         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1496         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1497         enum aux_ch aux_ch = dig_port->aux_ch;
1498
1499         switch (aux_ch) {
1500         case AUX_CH_A:
1501                 return DP_AUX_CH_DATA(aux_ch, index);
1502         case AUX_CH_B:
1503         case AUX_CH_C:
1504         case AUX_CH_D:
1505                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1506         default:
1507                 MISSING_CASE(aux_ch);
1508                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1509         }
1510 }
1511
1512 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1513 {
1514         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1515         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1516         enum aux_ch aux_ch = dig_port->aux_ch;
1517
1518         switch (aux_ch) {
1519         case AUX_CH_A:
1520         case AUX_CH_B:
1521         case AUX_CH_C:
1522         case AUX_CH_D:
1523         case AUX_CH_E:
1524         case AUX_CH_F:
1525                 return DP_AUX_CH_CTL(aux_ch);
1526         default:
1527                 MISSING_CASE(aux_ch);
1528                 return DP_AUX_CH_CTL(AUX_CH_A);
1529         }
1530 }
1531
1532 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1533 {
1534         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1535         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1536         enum aux_ch aux_ch = dig_port->aux_ch;
1537
1538         switch (aux_ch) {
1539         case AUX_CH_A:
1540         case AUX_CH_B:
1541         case AUX_CH_C:
1542         case AUX_CH_D:
1543         case AUX_CH_E:
1544         case AUX_CH_F:
1545                 return DP_AUX_CH_DATA(aux_ch, index);
1546         default:
1547                 MISSING_CASE(aux_ch);
1548                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1549         }
1550 }
1551
1552 static void
1553 intel_dp_aux_fini(struct intel_dp *intel_dp)
1554 {
1555         kfree(intel_dp->aux.name);
1556 }
1557
1558 static void
1559 intel_dp_aux_init(struct intel_dp *intel_dp)
1560 {
1561         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1562         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1563         struct intel_encoder *encoder = &dig_port->base;
1564
1565         if (INTEL_GEN(dev_priv) >= 9) {
1566                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1567                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1568         } else if (HAS_PCH_SPLIT(dev_priv)) {
1569                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1570                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1571         } else {
1572                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1573                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1574         }
1575
1576         if (INTEL_GEN(dev_priv) >= 9)
1577                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1578         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1579                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1580         else if (HAS_PCH_SPLIT(dev_priv))
1581                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1582         else
1583                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1584
1585         if (INTEL_GEN(dev_priv) >= 9)
1586                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1587         else
1588                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1589
1590         drm_dp_aux_init(&intel_dp->aux);
1591
1592         /* Failure to allocate our preferred name is not critical */
1593         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1594                                        port_name(encoder->port));
1595         intel_dp->aux.transfer = intel_dp_aux_transfer;
1596 }
1597
1598 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1599 {
1600         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1601
1602         return max_rate >= 540000;
1603 }
1604
1605 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1606 {
1607         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1608
1609         return max_rate >= 810000;
1610 }
1611
1612 static void
1613 intel_dp_set_clock(struct intel_encoder *encoder,
1614                    struct intel_crtc_state *pipe_config)
1615 {
1616         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1617         const struct dp_link_dpll *divisor = NULL;
1618         int i, count = 0;
1619
1620         if (IS_G4X(dev_priv)) {
1621                 divisor = g4x_dpll;
1622                 count = ARRAY_SIZE(g4x_dpll);
1623         } else if (HAS_PCH_SPLIT(dev_priv)) {
1624                 divisor = pch_dpll;
1625                 count = ARRAY_SIZE(pch_dpll);
1626         } else if (IS_CHERRYVIEW(dev_priv)) {
1627                 divisor = chv_dpll;
1628                 count = ARRAY_SIZE(chv_dpll);
1629         } else if (IS_VALLEYVIEW(dev_priv)) {
1630                 divisor = vlv_dpll;
1631                 count = ARRAY_SIZE(vlv_dpll);
1632         }
1633
1634         if (divisor && count) {
1635                 for (i = 0; i < count; i++) {
1636                         if (pipe_config->port_clock == divisor[i].clock) {
1637                                 pipe_config->dpll = divisor[i].dpll;
1638                                 pipe_config->clock_set = true;
1639                                 break;
1640                         }
1641                 }
1642         }
1643 }
1644
1645 static void snprintf_int_array(char *str, size_t len,
1646                                const int *array, int nelem)
1647 {
1648         int i;
1649
1650         str[0] = '\0';
1651
1652         for (i = 0; i < nelem; i++) {
1653                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1654                 if (r >= len)
1655                         return;
1656                 str += r;
1657                 len -= r;
1658         }
1659 }
1660
1661 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1662 {
1663         char str[128]; /* FIXME: too big for stack? */
1664
1665         if ((drm_debug & DRM_UT_KMS) == 0)
1666                 return;
1667
1668         snprintf_int_array(str, sizeof(str),
1669                            intel_dp->source_rates, intel_dp->num_source_rates);
1670         DRM_DEBUG_KMS("source rates: %s\n", str);
1671
1672         snprintf_int_array(str, sizeof(str),
1673                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1674         DRM_DEBUG_KMS("sink rates: %s\n", str);
1675
1676         snprintf_int_array(str, sizeof(str),
1677                            intel_dp->common_rates, intel_dp->num_common_rates);
1678         DRM_DEBUG_KMS("common rates: %s\n", str);
1679 }
1680
1681 int
1682 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1683 {
1684         int len;
1685
1686         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1687         if (WARN_ON(len <= 0))
1688                 return 162000;
1689
1690         return intel_dp->common_rates[len - 1];
1691 }
1692
1693 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1694 {
1695         int i = intel_dp_rate_index(intel_dp->sink_rates,
1696                                     intel_dp->num_sink_rates, rate);
1697
1698         if (WARN_ON(i < 0))
1699                 i = 0;
1700
1701         return i;
1702 }
1703
1704 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1705                            uint8_t *link_bw, uint8_t *rate_select)
1706 {
1707         /* eDP 1.4 rate select method. */
1708         if (intel_dp->use_rate_select) {
1709                 *link_bw = 0;
1710                 *rate_select =
1711                         intel_dp_rate_select(intel_dp, port_clock);
1712         } else {
1713                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1714                 *rate_select = 0;
1715         }
1716 }
1717
1718 struct link_config_limits {
1719         int min_clock, max_clock;
1720         int min_lane_count, max_lane_count;
1721         int min_bpp, max_bpp;
1722 };
1723
1724 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1725                                          const struct intel_crtc_state *pipe_config)
1726 {
1727         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1728
1729         return INTEL_GEN(dev_priv) >= 11 &&
1730                 pipe_config->cpu_transcoder != TRANSCODER_A;
1731 }
1732
1733 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1734                                   const struct intel_crtc_state *pipe_config)
1735 {
1736         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1737                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1738 }
1739
1740 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1741                                          const struct intel_crtc_state *pipe_config)
1742 {
1743         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1744
1745         return INTEL_GEN(dev_priv) >= 10 &&
1746                 pipe_config->cpu_transcoder != TRANSCODER_A;
1747 }
1748
1749 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1750                                   const struct intel_crtc_state *pipe_config)
1751 {
1752         if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1753                 return false;
1754
1755         return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1756                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1757 }
1758
1759 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1760                                 struct intel_crtc_state *pipe_config)
1761 {
1762         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1763         struct intel_connector *intel_connector = intel_dp->attached_connector;
1764         int bpp, bpc;
1765
1766         bpp = pipe_config->pipe_bpp;
1767         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1768
1769         if (bpc > 0)
1770                 bpp = min(bpp, 3*bpc);
1771
1772         if (intel_dp_is_edp(intel_dp)) {
1773                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1774                 if (intel_connector->base.display_info.bpc == 0 &&
1775                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1776                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1777                                       dev_priv->vbt.edp.bpp);
1778                         bpp = dev_priv->vbt.edp.bpp;
1779                 }
1780         }
1781
1782         return bpp;
1783 }
1784
1785 /* Adjust link config limits based on compliance test requests. */
1786 static void
1787 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1788                                   struct intel_crtc_state *pipe_config,
1789                                   struct link_config_limits *limits)
1790 {
1791         /* For DP Compliance we override the computed bpp for the pipe */
1792         if (intel_dp->compliance.test_data.bpc != 0) {
1793                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1794
1795                 limits->min_bpp = limits->max_bpp = bpp;
1796                 pipe_config->dither_force_disable = bpp == 6 * 3;
1797
1798                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1799         }
1800
1801         /* Use values requested by Compliance Test Request */
1802         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1803                 int index;
1804
1805                 /* Validate the compliance test data since max values
1806                  * might have changed due to link train fallback.
1807                  */
1808                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1809                                                intel_dp->compliance.test_lane_count)) {
1810                         index = intel_dp_rate_index(intel_dp->common_rates,
1811                                                     intel_dp->num_common_rates,
1812                                                     intel_dp->compliance.test_link_rate);
1813                         if (index >= 0)
1814                                 limits->min_clock = limits->max_clock = index;
1815                         limits->min_lane_count = limits->max_lane_count =
1816                                 intel_dp->compliance.test_lane_count;
1817                 }
1818         }
1819 }
1820
1821 /* Optimize link config in order: max bpp, min clock, min lanes */
1822 static int
1823 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1824                                   struct intel_crtc_state *pipe_config,
1825                                   const struct link_config_limits *limits)
1826 {
1827         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1828         int bpp, clock, lane_count;
1829         int mode_rate, link_clock, link_avail;
1830
1831         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1832                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1833                                                    bpp);
1834
1835                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1836                         for (lane_count = limits->min_lane_count;
1837                              lane_count <= limits->max_lane_count;
1838                              lane_count <<= 1) {
1839                                 link_clock = intel_dp->common_rates[clock];
1840                                 link_avail = intel_dp_max_data_rate(link_clock,
1841                                                                     lane_count);
1842
1843                                 if (mode_rate <= link_avail) {
1844                                         pipe_config->lane_count = lane_count;
1845                                         pipe_config->pipe_bpp = bpp;
1846                                         pipe_config->port_clock = link_clock;
1847
1848                                         return 0;
1849                                 }
1850                         }
1851                 }
1852         }
1853
1854         return -EINVAL;
1855 }
1856
1857 /* Optimize link config in order: max bpp, min lanes, min clock */
1858 static int
1859 intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
1860                                   struct intel_crtc_state *pipe_config,
1861                                   const struct link_config_limits *limits)
1862 {
1863         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1864         int bpp, clock, lane_count;
1865         int mode_rate, link_clock, link_avail;
1866
1867         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1868                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1869                                                    bpp);
1870
1871                 for (lane_count = limits->min_lane_count;
1872                      lane_count <= limits->max_lane_count;
1873                      lane_count <<= 1) {
1874                         for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1875                                 link_clock = intel_dp->common_rates[clock];
1876                                 link_avail = intel_dp_max_data_rate(link_clock,
1877                                                                     lane_count);
1878
1879                                 if (mode_rate <= link_avail) {
1880                                         pipe_config->lane_count = lane_count;
1881                                         pipe_config->pipe_bpp = bpp;
1882                                         pipe_config->port_clock = link_clock;
1883
1884                                         return 0;
1885                                 }
1886                         }
1887                 }
1888         }
1889
1890         return -EINVAL;
1891 }
1892
1893 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1894 {
1895         int i, num_bpc;
1896         u8 dsc_bpc[3] = {0};
1897
1898         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1899                                                        dsc_bpc);
1900         for (i = 0; i < num_bpc; i++) {
1901                 if (dsc_max_bpc >= dsc_bpc[i])
1902                         return dsc_bpc[i] * 3;
1903         }
1904
1905         return 0;
1906 }
1907
1908 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1909                                        struct intel_crtc_state *pipe_config,
1910                                        struct drm_connector_state *conn_state,
1911                                        struct link_config_limits *limits)
1912 {
1913         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1914         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1915         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1916         u8 dsc_max_bpc;
1917         int pipe_bpp;
1918         int ret;
1919
1920         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1921                 return -EINVAL;
1922
1923         dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
1924                             conn_state->max_requested_bpc);
1925
1926         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1927         if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
1928                 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
1929                 return -EINVAL;
1930         }
1931
1932         /*
1933          * For now enable DSC for max bpp, max link rate, max lane count.
1934          * Optimize this later for the minimum possible link rate/lane count
1935          * with DSC enabled for the requested mode.
1936          */
1937         pipe_config->pipe_bpp = pipe_bpp;
1938         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1939         pipe_config->lane_count = limits->max_lane_count;
1940
1941         if (intel_dp_is_edp(intel_dp)) {
1942                 pipe_config->dsc_params.compressed_bpp =
1943                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1944                               pipe_config->pipe_bpp);
1945                 pipe_config->dsc_params.slice_count =
1946                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1947                                                         true);
1948         } else {
1949                 u16 dsc_max_output_bpp;
1950                 u8 dsc_dp_slice_count;
1951
1952                 dsc_max_output_bpp =
1953                         intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
1954                                                     pipe_config->lane_count,
1955                                                     adjusted_mode->crtc_clock,
1956                                                     adjusted_mode->crtc_hdisplay);
1957                 dsc_dp_slice_count =
1958                         intel_dp_dsc_get_slice_count(intel_dp,
1959                                                      adjusted_mode->crtc_clock,
1960                                                      adjusted_mode->crtc_hdisplay);
1961                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1962                         DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
1963                         return -EINVAL;
1964                 }
1965                 pipe_config->dsc_params.compressed_bpp = min_t(u16,
1966                                                                dsc_max_output_bpp >> 4,
1967                                                                pipe_config->pipe_bpp);
1968                 pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
1969         }
1970         /*
1971          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1972          * is greater than the maximum Cdclock and if slice count is even
1973          * then we need to use 2 VDSC instances.
1974          */
1975         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
1976                 if (pipe_config->dsc_params.slice_count > 1) {
1977                         pipe_config->dsc_params.dsc_split = true;
1978                 } else {
1979                         DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
1980                         return -EINVAL;
1981                 }
1982         }
1983
1984         ret = intel_dp_compute_dsc_params(intel_dp, pipe_config);
1985         if (ret < 0) {
1986                 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
1987                               "Compressed BPP = %d\n",
1988                               pipe_config->pipe_bpp,
1989                               pipe_config->dsc_params.compressed_bpp);
1990                 return ret;
1991         }
1992
1993         pipe_config->dsc_params.compression_enable = true;
1994         DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
1995                       "Compressed Bpp = %d Slice Count = %d\n",
1996                       pipe_config->pipe_bpp,
1997                       pipe_config->dsc_params.compressed_bpp,
1998                       pipe_config->dsc_params.slice_count);
1999
2000         return 0;
2001 }
2002
2003 static int
2004 intel_dp_compute_link_config(struct intel_encoder *encoder,
2005                              struct intel_crtc_state *pipe_config,
2006                              struct drm_connector_state *conn_state)
2007 {
2008         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2009         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2010         struct link_config_limits limits;
2011         int common_len;
2012         int ret;
2013
2014         common_len = intel_dp_common_len_rate_limit(intel_dp,
2015                                                     intel_dp->max_link_rate);
2016
2017         /* No common link rates between source and sink */
2018         WARN_ON(common_len <= 0);
2019
2020         limits.min_clock = 0;
2021         limits.max_clock = common_len - 1;
2022
2023         limits.min_lane_count = 1;
2024         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2025
2026         limits.min_bpp = 6 * 3;
2027         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2028
2029         if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
2030                 /*
2031                  * Use the maximum clock and number of lanes the eDP panel
2032                  * advertizes being capable of. The eDP 1.3 and earlier panels
2033                  * are generally designed to support only a single clock and
2034                  * lane configuration, and typically these values correspond to
2035                  * the native resolution of the panel. With eDP 1.4 rate select
2036                  * and DSC, this is decreasingly the case, and we need to be
2037                  * able to select less than maximum link config.
2038                  */
2039                 limits.min_lane_count = limits.max_lane_count;
2040                 limits.min_clock = limits.max_clock;
2041         }
2042
2043         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2044
2045         DRM_DEBUG_KMS("DP link computation with max lane count %i "
2046                       "max rate %d max bpp %d pixel clock %iKHz\n",
2047                       limits.max_lane_count,
2048                       intel_dp->common_rates[limits.max_clock],
2049                       limits.max_bpp, adjusted_mode->crtc_clock);
2050
2051         if (intel_dp_is_edp(intel_dp))
2052                 /*
2053                  * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
2054                  * section A.1: "It is recommended that the minimum number of
2055                  * lanes be used, using the minimum link rate allowed for that
2056                  * lane configuration."
2057                  *
2058                  * Note that we use the max clock and lane count for eDP 1.3 and
2059                  * earlier, and fast vs. wide is irrelevant.
2060                  */
2061                 ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config,
2062                                                         &limits);
2063         else
2064                 /* Optimize for slow and wide. */
2065                 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2066                                                         &limits);
2067
2068         /* enable compression if the mode doesn't fit available BW */
2069         DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
2070         if (ret || intel_dp->force_dsc_en) {
2071                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2072                                                   conn_state, &limits);
2073                 if (ret < 0)
2074                         return ret;
2075         }
2076
2077         if (pipe_config->dsc_params.compression_enable) {
2078                 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2079                               pipe_config->lane_count, pipe_config->port_clock,
2080                               pipe_config->pipe_bpp,
2081                               pipe_config->dsc_params.compressed_bpp);
2082
2083                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2084                               intel_dp_link_required(adjusted_mode->crtc_clock,
2085                                                      pipe_config->dsc_params.compressed_bpp),
2086                               intel_dp_max_data_rate(pipe_config->port_clock,
2087                                                      pipe_config->lane_count));
2088         } else {
2089                 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2090                               pipe_config->lane_count, pipe_config->port_clock,
2091                               pipe_config->pipe_bpp);
2092
2093                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2094                               intel_dp_link_required(adjusted_mode->crtc_clock,
2095                                                      pipe_config->pipe_bpp),
2096                               intel_dp_max_data_rate(pipe_config->port_clock,
2097                                                      pipe_config->lane_count));
2098         }
2099         return 0;
2100 }
2101
2102 int
2103 intel_dp_compute_config(struct intel_encoder *encoder,
2104                         struct intel_crtc_state *pipe_config,
2105                         struct drm_connector_state *conn_state)
2106 {
2107         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2108         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2109         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2110         struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2111         enum port port = encoder->port;
2112         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2113         struct intel_connector *intel_connector = intel_dp->attached_connector;
2114         struct intel_digital_connector_state *intel_conn_state =
2115                 to_intel_digital_connector_state(conn_state);
2116         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2117                                            DP_DPCD_QUIRK_CONSTANT_N);
2118         int ret;
2119
2120         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2121                 pipe_config->has_pch_encoder = true;
2122
2123         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2124         if (lspcon->active)
2125                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2126
2127         pipe_config->has_drrs = false;
2128         if (IS_G4X(dev_priv) || port == PORT_A)
2129                 pipe_config->has_audio = false;
2130         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2131                 pipe_config->has_audio = intel_dp->has_audio;
2132         else
2133                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2134
2135         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2136                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2137                                        adjusted_mode);
2138
2139                 if (INTEL_GEN(dev_priv) >= 9) {
2140                         ret = skl_update_scaler_crtc(pipe_config);
2141                         if (ret)
2142                                 return ret;
2143                 }
2144
2145                 if (HAS_GMCH_DISPLAY(dev_priv))
2146                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2147                                                  conn_state->scaling_mode);
2148                 else
2149                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2150                                                 conn_state->scaling_mode);
2151         }
2152
2153         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2154                 return -EINVAL;
2155
2156         if (HAS_GMCH_DISPLAY(dev_priv) &&
2157             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2158                 return -EINVAL;
2159
2160         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2161                 return -EINVAL;
2162
2163         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2164                                   intel_dp_supports_fec(intel_dp, pipe_config);
2165
2166         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2167         if (ret < 0)
2168                 return ret;
2169
2170         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2171                 /*
2172                  * See:
2173                  * CEA-861-E - 5.1 Default Encoding Parameters
2174                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2175                  */
2176                 pipe_config->limited_color_range =
2177                         pipe_config->pipe_bpp != 18 &&
2178                         drm_default_rgb_quant_range(adjusted_mode) ==
2179                         HDMI_QUANTIZATION_RANGE_LIMITED;
2180         } else {
2181                 pipe_config->limited_color_range =
2182                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2183         }
2184
2185         if (!pipe_config->dsc_params.compression_enable)
2186                 intel_link_compute_m_n(pipe_config->pipe_bpp,
2187                                        pipe_config->lane_count,
2188                                        adjusted_mode->crtc_clock,
2189                                        pipe_config->port_clock,
2190                                        &pipe_config->dp_m_n,
2191                                        constant_n);
2192         else
2193                 intel_link_compute_m_n(pipe_config->dsc_params.compressed_bpp,
2194                                        pipe_config->lane_count,
2195                                        adjusted_mode->crtc_clock,
2196                                        pipe_config->port_clock,
2197                                        &pipe_config->dp_m_n,
2198                                        constant_n);
2199
2200         if (intel_connector->panel.downclock_mode != NULL &&
2201                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2202                         pipe_config->has_drrs = true;
2203                         intel_link_compute_m_n(pipe_config->pipe_bpp,
2204                                                pipe_config->lane_count,
2205                                                intel_connector->panel.downclock_mode->clock,
2206                                                pipe_config->port_clock,
2207                                                &pipe_config->dp_m2_n2,
2208                                                constant_n);
2209         }
2210
2211         if (!HAS_DDI(dev_priv))
2212                 intel_dp_set_clock(encoder, pipe_config);
2213
2214         intel_psr_compute_config(intel_dp, pipe_config);
2215
2216         return 0;
2217 }
2218
2219 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2220                               int link_rate, uint8_t lane_count,
2221                               bool link_mst)
2222 {
2223         intel_dp->link_trained = false;
2224         intel_dp->link_rate = link_rate;
2225         intel_dp->lane_count = lane_count;
2226         intel_dp->link_mst = link_mst;
2227 }
2228
2229 static void intel_dp_prepare(struct intel_encoder *encoder,
2230                              const struct intel_crtc_state *pipe_config)
2231 {
2232         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2233         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2234         enum port port = encoder->port;
2235         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2236         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2237
2238         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2239                                  pipe_config->lane_count,
2240                                  intel_crtc_has_type(pipe_config,
2241                                                      INTEL_OUTPUT_DP_MST));
2242
2243         /*
2244          * There are four kinds of DP registers:
2245          *
2246          *      IBX PCH
2247          *      SNB CPU
2248          *      IVB CPU
2249          *      CPT PCH
2250          *
2251          * IBX PCH and CPU are the same for almost everything,
2252          * except that the CPU DP PLL is configured in this
2253          * register
2254          *
2255          * CPT PCH is quite different, having many bits moved
2256          * to the TRANS_DP_CTL register instead. That
2257          * configuration happens (oddly) in ironlake_pch_enable
2258          */
2259
2260         /* Preserve the BIOS-computed detected bit. This is
2261          * supposed to be read-only.
2262          */
2263         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2264
2265         /* Handle DP bits in common between all three register formats */
2266         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2267         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2268
2269         /* Split out the IBX/CPU vs CPT settings */
2270
2271         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2272                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2273                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2274                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2275                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2276                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2277
2278                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2279                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2280
2281                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2282         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2283                 u32 trans_dp;
2284
2285                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2286
2287                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2288                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2289                         trans_dp |= TRANS_DP_ENH_FRAMING;
2290                 else
2291                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2292                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2293         } else {
2294                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2295                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2296
2297                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2298                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2299                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2300                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2301                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2302
2303                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2304                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2305
2306                 if (IS_CHERRYVIEW(dev_priv))
2307                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2308                 else
2309                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2310         }
2311 }
2312
2313 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2314 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2315
2316 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2317 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2318
2319 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2320 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2321
2322 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2323
2324 static void wait_panel_status(struct intel_dp *intel_dp,
2325                                        u32 mask,
2326                                        u32 value)
2327 {
2328         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2329         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2330
2331         lockdep_assert_held(&dev_priv->pps_mutex);
2332
2333         intel_pps_verify_state(intel_dp);
2334
2335         pp_stat_reg = _pp_stat_reg(intel_dp);
2336         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2337
2338         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2339                         mask, value,
2340                         I915_READ(pp_stat_reg),
2341                         I915_READ(pp_ctrl_reg));
2342
2343         if (intel_wait_for_register(dev_priv,
2344                                     pp_stat_reg, mask, value,
2345                                     5000))
2346                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2347                                 I915_READ(pp_stat_reg),
2348                                 I915_READ(pp_ctrl_reg));
2349
2350         DRM_DEBUG_KMS("Wait complete\n");
2351 }
2352
2353 static void wait_panel_on(struct intel_dp *intel_dp)
2354 {
2355         DRM_DEBUG_KMS("Wait for panel power on\n");
2356         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2357 }
2358
2359 static void wait_panel_off(struct intel_dp *intel_dp)
2360 {
2361         DRM_DEBUG_KMS("Wait for panel power off time\n");
2362         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2363 }
2364
2365 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2366 {
2367         ktime_t panel_power_on_time;
2368         s64 panel_power_off_duration;
2369
2370         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2371
2372         /* take the difference of currrent time and panel power off time
2373          * and then make panel wait for t11_t12 if needed. */
2374         panel_power_on_time = ktime_get_boottime();
2375         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2376
2377         /* When we disable the VDD override bit last we have to do the manual
2378          * wait. */
2379         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2380                 wait_remaining_ms_from_jiffies(jiffies,
2381                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2382
2383         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2384 }
2385
2386 static void wait_backlight_on(struct intel_dp *intel_dp)
2387 {
2388         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2389                                        intel_dp->backlight_on_delay);
2390 }
2391
2392 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2393 {
2394         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2395                                        intel_dp->backlight_off_delay);
2396 }
2397
2398 /* Read the current pp_control value, unlocking the register if it
2399  * is locked
2400  */
2401
2402 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2403 {
2404         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2405         u32 control;
2406
2407         lockdep_assert_held(&dev_priv->pps_mutex);
2408
2409         control = I915_READ(_pp_ctrl_reg(intel_dp));
2410         if (WARN_ON(!HAS_DDI(dev_priv) &&
2411                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2412                 control &= ~PANEL_UNLOCK_MASK;
2413                 control |= PANEL_UNLOCK_REGS;
2414         }
2415         return control;
2416 }
2417
2418 /*
2419  * Must be paired with edp_panel_vdd_off().
2420  * Must hold pps_mutex around the whole on/off sequence.
2421  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2422  */
2423 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2424 {
2425         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2426         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2427         u32 pp;
2428         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2429         bool need_to_disable = !intel_dp->want_panel_vdd;
2430
2431         lockdep_assert_held(&dev_priv->pps_mutex);
2432
2433         if (!intel_dp_is_edp(intel_dp))
2434                 return false;
2435
2436         cancel_delayed_work(&intel_dp->panel_vdd_work);
2437         intel_dp->want_panel_vdd = true;
2438
2439         if (edp_have_panel_vdd(intel_dp))
2440                 return need_to_disable;
2441
2442         intel_display_power_get(dev_priv,
2443                                 intel_aux_power_domain(intel_dig_port));
2444
2445         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2446                       port_name(intel_dig_port->base.port));
2447
2448         if (!edp_have_panel_power(intel_dp))
2449                 wait_panel_power_cycle(intel_dp);
2450
2451         pp = ironlake_get_pp_control(intel_dp);
2452         pp |= EDP_FORCE_VDD;
2453
2454         pp_stat_reg = _pp_stat_reg(intel_dp);
2455         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2456
2457         I915_WRITE(pp_ctrl_reg, pp);
2458         POSTING_READ(pp_ctrl_reg);
2459         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2460                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2461         /*
2462          * If the panel wasn't on, delay before accessing aux channel
2463          */
2464         if (!edp_have_panel_power(intel_dp)) {
2465                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2466                               port_name(intel_dig_port->base.port));
2467                 msleep(intel_dp->panel_power_up_delay);
2468         }
2469
2470         return need_to_disable;
2471 }
2472
2473 /*
2474  * Must be paired with intel_edp_panel_vdd_off() or
2475  * intel_edp_panel_off().
2476  * Nested calls to these functions are not allowed since
2477  * we drop the lock. Caller must use some higher level
2478  * locking to prevent nested calls from other threads.
2479  */
2480 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2481 {
2482         intel_wakeref_t wakeref;
2483         bool vdd;
2484
2485         if (!intel_dp_is_edp(intel_dp))
2486                 return;
2487
2488         vdd = false;
2489         with_pps_lock(intel_dp, wakeref)
2490                 vdd = edp_panel_vdd_on(intel_dp);
2491         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2492              port_name(dp_to_dig_port(intel_dp)->base.port));
2493 }
2494
2495 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2496 {
2497         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2498         struct intel_digital_port *intel_dig_port =
2499                 dp_to_dig_port(intel_dp);
2500         u32 pp;
2501         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2502
2503         lockdep_assert_held(&dev_priv->pps_mutex);
2504
2505         WARN_ON(intel_dp->want_panel_vdd);
2506
2507         if (!edp_have_panel_vdd(intel_dp))
2508                 return;
2509
2510         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2511                       port_name(intel_dig_port->base.port));
2512
2513         pp = ironlake_get_pp_control(intel_dp);
2514         pp &= ~EDP_FORCE_VDD;
2515
2516         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2517         pp_stat_reg = _pp_stat_reg(intel_dp);
2518
2519         I915_WRITE(pp_ctrl_reg, pp);
2520         POSTING_READ(pp_ctrl_reg);
2521
2522         /* Make sure sequencer is idle before allowing subsequent activity */
2523         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2524         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2525
2526         if ((pp & PANEL_POWER_ON) == 0)
2527                 intel_dp->panel_power_off_time = ktime_get_boottime();
2528
2529         intel_display_power_put_unchecked(dev_priv,
2530                                           intel_aux_power_domain(intel_dig_port));
2531 }
2532
2533 static void edp_panel_vdd_work(struct work_struct *__work)
2534 {
2535         struct intel_dp *intel_dp =
2536                 container_of(to_delayed_work(__work),
2537                              struct intel_dp, panel_vdd_work);
2538         intel_wakeref_t wakeref;
2539
2540         with_pps_lock(intel_dp, wakeref) {
2541                 if (!intel_dp->want_panel_vdd)
2542                         edp_panel_vdd_off_sync(intel_dp);
2543         }
2544 }
2545
2546 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2547 {
2548         unsigned long delay;
2549
2550         /*
2551          * Queue the timer to fire a long time from now (relative to the power
2552          * down delay) to keep the panel power up across a sequence of
2553          * operations.
2554          */
2555         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2556         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2557 }
2558
2559 /*
2560  * Must be paired with edp_panel_vdd_on().
2561  * Must hold pps_mutex around the whole on/off sequence.
2562  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2563  */
2564 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2565 {
2566         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2567
2568         lockdep_assert_held(&dev_priv->pps_mutex);
2569
2570         if (!intel_dp_is_edp(intel_dp))
2571                 return;
2572
2573         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2574              port_name(dp_to_dig_port(intel_dp)->base.port));
2575
2576         intel_dp->want_panel_vdd = false;
2577
2578         if (sync)
2579                 edp_panel_vdd_off_sync(intel_dp);
2580         else
2581                 edp_panel_vdd_schedule_off(intel_dp);
2582 }
2583
2584 static void edp_panel_on(struct intel_dp *intel_dp)
2585 {
2586         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2587         u32 pp;
2588         i915_reg_t pp_ctrl_reg;
2589
2590         lockdep_assert_held(&dev_priv->pps_mutex);
2591
2592         if (!intel_dp_is_edp(intel_dp))
2593                 return;
2594
2595         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2596                       port_name(dp_to_dig_port(intel_dp)->base.port));
2597
2598         if (WARN(edp_have_panel_power(intel_dp),
2599                  "eDP port %c panel power already on\n",
2600                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2601                 return;
2602
2603         wait_panel_power_cycle(intel_dp);
2604
2605         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2606         pp = ironlake_get_pp_control(intel_dp);
2607         if (IS_GEN(dev_priv, 5)) {
2608                 /* ILK workaround: disable reset around power sequence */
2609                 pp &= ~PANEL_POWER_RESET;
2610                 I915_WRITE(pp_ctrl_reg, pp);
2611                 POSTING_READ(pp_ctrl_reg);
2612         }
2613
2614         pp |= PANEL_POWER_ON;
2615         if (!IS_GEN(dev_priv, 5))
2616                 pp |= PANEL_POWER_RESET;
2617
2618         I915_WRITE(pp_ctrl_reg, pp);
2619         POSTING_READ(pp_ctrl_reg);
2620
2621         wait_panel_on(intel_dp);
2622         intel_dp->last_power_on = jiffies;
2623
2624         if (IS_GEN(dev_priv, 5)) {
2625                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2626                 I915_WRITE(pp_ctrl_reg, pp);
2627                 POSTING_READ(pp_ctrl_reg);
2628         }
2629 }
2630
2631 void intel_edp_panel_on(struct intel_dp *intel_dp)
2632 {
2633         intel_wakeref_t wakeref;
2634
2635         if (!intel_dp_is_edp(intel_dp))
2636                 return;
2637
2638         with_pps_lock(intel_dp, wakeref)
2639                 edp_panel_on(intel_dp);
2640 }
2641
2642
2643 static void edp_panel_off(struct intel_dp *intel_dp)
2644 {
2645         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2646         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2647         u32 pp;
2648         i915_reg_t pp_ctrl_reg;
2649
2650         lockdep_assert_held(&dev_priv->pps_mutex);
2651
2652         if (!intel_dp_is_edp(intel_dp))
2653                 return;
2654
2655         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2656                       port_name(dig_port->base.port));
2657
2658         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2659              port_name(dig_port->base.port));
2660
2661         pp = ironlake_get_pp_control(intel_dp);
2662         /* We need to switch off panel power _and_ force vdd, for otherwise some
2663          * panels get very unhappy and cease to work. */
2664         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2665                 EDP_BLC_ENABLE);
2666
2667         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2668
2669         intel_dp->want_panel_vdd = false;
2670
2671         I915_WRITE(pp_ctrl_reg, pp);
2672         POSTING_READ(pp_ctrl_reg);
2673
2674         wait_panel_off(intel_dp);
2675         intel_dp->panel_power_off_time = ktime_get_boottime();
2676
2677         /* We got a reference when we enabled the VDD. */
2678         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
2679 }
2680
2681 void intel_edp_panel_off(struct intel_dp *intel_dp)
2682 {
2683         intel_wakeref_t wakeref;
2684
2685         if (!intel_dp_is_edp(intel_dp))
2686                 return;
2687
2688         with_pps_lock(intel_dp, wakeref)
2689                 edp_panel_off(intel_dp);
2690 }
2691
2692 /* Enable backlight in the panel power control. */
2693 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2694 {
2695         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2696         intel_wakeref_t wakeref;
2697
2698         /*
2699          * If we enable the backlight right away following a panel power
2700          * on, we may see slight flicker as the panel syncs with the eDP
2701          * link.  So delay a bit to make sure the image is solid before
2702          * allowing it to appear.
2703          */
2704         wait_backlight_on(intel_dp);
2705
2706         with_pps_lock(intel_dp, wakeref) {
2707                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2708                 u32 pp;
2709
2710                 pp = ironlake_get_pp_control(intel_dp);
2711                 pp |= EDP_BLC_ENABLE;
2712
2713                 I915_WRITE(pp_ctrl_reg, pp);
2714                 POSTING_READ(pp_ctrl_reg);
2715         }
2716 }
2717
2718 /* Enable backlight PWM and backlight PP control. */
2719 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2720                             const struct drm_connector_state *conn_state)
2721 {
2722         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2723
2724         if (!intel_dp_is_edp(intel_dp))
2725                 return;
2726
2727         DRM_DEBUG_KMS("\n");
2728
2729         intel_panel_enable_backlight(crtc_state, conn_state);
2730         _intel_edp_backlight_on(intel_dp);
2731 }
2732
2733 /* Disable backlight in the panel power control. */
2734 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2735 {
2736         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2737         intel_wakeref_t wakeref;
2738
2739         if (!intel_dp_is_edp(intel_dp))
2740                 return;
2741
2742         with_pps_lock(intel_dp, wakeref) {
2743                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2744                 u32 pp;
2745
2746                 pp = ironlake_get_pp_control(intel_dp);
2747                 pp &= ~EDP_BLC_ENABLE;
2748
2749                 I915_WRITE(pp_ctrl_reg, pp);
2750                 POSTING_READ(pp_ctrl_reg);
2751         }
2752
2753         intel_dp->last_backlight_off = jiffies;
2754         edp_wait_backlight_off(intel_dp);
2755 }
2756
2757 /* Disable backlight PP control and backlight PWM. */
2758 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2759 {
2760         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2761
2762         if (!intel_dp_is_edp(intel_dp))
2763                 return;
2764
2765         DRM_DEBUG_KMS("\n");
2766
2767         _intel_edp_backlight_off(intel_dp);
2768         intel_panel_disable_backlight(old_conn_state);
2769 }
2770
2771 /*
2772  * Hook for controlling the panel power control backlight through the bl_power
2773  * sysfs attribute. Take care to handle multiple calls.
2774  */
2775 static void intel_edp_backlight_power(struct intel_connector *connector,
2776                                       bool enable)
2777 {
2778         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2779         intel_wakeref_t wakeref;
2780         bool is_enabled;
2781
2782         is_enabled = false;
2783         with_pps_lock(intel_dp, wakeref)
2784                 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2785         if (is_enabled == enable)
2786                 return;
2787
2788         DRM_DEBUG_KMS("panel power control backlight %s\n",
2789                       enable ? "enable" : "disable");
2790
2791         if (enable)
2792                 _intel_edp_backlight_on(intel_dp);
2793         else
2794                 _intel_edp_backlight_off(intel_dp);
2795 }
2796
2797 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2798 {
2799         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2800         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2801         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2802
2803         I915_STATE_WARN(cur_state != state,
2804                         "DP port %c state assertion failure (expected %s, current %s)\n",
2805                         port_name(dig_port->base.port),
2806                         onoff(state), onoff(cur_state));
2807 }
2808 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2809
2810 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2811 {
2812         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2813
2814         I915_STATE_WARN(cur_state != state,
2815                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2816                         onoff(state), onoff(cur_state));
2817 }
2818 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2819 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2820
2821 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2822                                 const struct intel_crtc_state *pipe_config)
2823 {
2824         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2825         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2826
2827         assert_pipe_disabled(dev_priv, crtc->pipe);
2828         assert_dp_port_disabled(intel_dp);
2829         assert_edp_pll_disabled(dev_priv);
2830
2831         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2832                       pipe_config->port_clock);
2833
2834         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2835
2836         if (pipe_config->port_clock == 162000)
2837                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2838         else
2839                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2840
2841         I915_WRITE(DP_A, intel_dp->DP);
2842         POSTING_READ(DP_A);
2843         udelay(500);
2844
2845         /*
2846          * [DevILK] Work around required when enabling DP PLL
2847          * while a pipe is enabled going to FDI:
2848          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2849          * 2. Program DP PLL enable
2850          */
2851         if (IS_GEN(dev_priv, 5))
2852                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2853
2854         intel_dp->DP |= DP_PLL_ENABLE;
2855
2856         I915_WRITE(DP_A, intel_dp->DP);
2857         POSTING_READ(DP_A);
2858         udelay(200);
2859 }
2860
2861 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2862                                  const struct intel_crtc_state *old_crtc_state)
2863 {
2864         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2865         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2866
2867         assert_pipe_disabled(dev_priv, crtc->pipe);
2868         assert_dp_port_disabled(intel_dp);
2869         assert_edp_pll_enabled(dev_priv);
2870
2871         DRM_DEBUG_KMS("disabling eDP PLL\n");
2872
2873         intel_dp->DP &= ~DP_PLL_ENABLE;
2874
2875         I915_WRITE(DP_A, intel_dp->DP);
2876         POSTING_READ(DP_A);
2877         udelay(200);
2878 }
2879
2880 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2881 {
2882         /*
2883          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2884          * be capable of signalling downstream hpd with a long pulse.
2885          * Whether or not that means D3 is safe to use is not clear,
2886          * but let's assume so until proven otherwise.
2887          *
2888          * FIXME should really check all downstream ports...
2889          */
2890         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2891                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2892                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2893 }
2894
2895 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2896                                            const struct intel_crtc_state *crtc_state,
2897                                            bool enable)
2898 {
2899         int ret;
2900
2901         if (!crtc_state->dsc_params.compression_enable)
2902                 return;
2903
2904         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2905                                  enable ? DP_DECOMPRESSION_EN : 0);
2906         if (ret < 0)
2907                 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
2908                               enable ? "enable" : "disable");
2909 }
2910
2911 /* If the sink supports it, try to set the power state appropriately */
2912 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2913 {
2914         int ret, i;
2915
2916         /* Should have a valid DPCD by this point */
2917         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2918                 return;
2919
2920         if (mode != DRM_MODE_DPMS_ON) {
2921                 if (downstream_hpd_needs_d0(intel_dp))
2922                         return;
2923
2924                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2925                                          DP_SET_POWER_D3);
2926         } else {
2927                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2928
2929                 /*
2930                  * When turning on, we need to retry for 1ms to give the sink
2931                  * time to wake up.
2932                  */
2933                 for (i = 0; i < 3; i++) {
2934                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2935                                                  DP_SET_POWER_D0);
2936                         if (ret == 1)
2937                                 break;
2938                         msleep(1);
2939                 }
2940
2941                 if (ret == 1 && lspcon->active)
2942                         lspcon_wait_pcon_mode(lspcon);
2943         }
2944
2945         if (ret != 1)
2946                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2947                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2948 }
2949
2950 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2951                                  enum port port, enum pipe *pipe)
2952 {
2953         enum pipe p;
2954
2955         for_each_pipe(dev_priv, p) {
2956                 u32 val = I915_READ(TRANS_DP_CTL(p));
2957
2958                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2959                         *pipe = p;
2960                         return true;
2961                 }
2962         }
2963
2964         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2965
2966         /* must initialize pipe to something for the asserts */
2967         *pipe = PIPE_A;
2968
2969         return false;
2970 }
2971
2972 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2973                            i915_reg_t dp_reg, enum port port,
2974                            enum pipe *pipe)
2975 {
2976         bool ret;
2977         u32 val;
2978
2979         val = I915_READ(dp_reg);
2980
2981         ret = val & DP_PORT_EN;
2982
2983         /* asserts want to know the pipe even if the port is disabled */
2984         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2985                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2986         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2987                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2988         else if (IS_CHERRYVIEW(dev_priv))
2989                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2990         else
2991                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2992
2993         return ret;
2994 }
2995
2996 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2997                                   enum pipe *pipe)
2998 {
2999         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3000         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3001         intel_wakeref_t wakeref;
3002         bool ret;
3003
3004         wakeref = intel_display_power_get_if_enabled(dev_priv,
3005                                                      encoder->power_domain);
3006         if (!wakeref)
3007                 return false;
3008
3009         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3010                                     encoder->port, pipe);
3011
3012         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3013
3014         return ret;
3015 }
3016
3017 static void intel_dp_get_config(struct intel_encoder *encoder,
3018                                 struct intel_crtc_state *pipe_config)
3019 {
3020         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3021         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3022         u32 tmp, flags = 0;
3023         enum port port = encoder->port;
3024         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3025
3026         if (encoder->type == INTEL_OUTPUT_EDP)
3027                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3028         else
3029                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3030
3031         tmp = I915_READ(intel_dp->output_reg);
3032
3033         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3034
3035         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3036                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3037
3038                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3039                         flags |= DRM_MODE_FLAG_PHSYNC;
3040                 else
3041                         flags |= DRM_MODE_FLAG_NHSYNC;
3042
3043                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3044                         flags |= DRM_MODE_FLAG_PVSYNC;
3045                 else
3046                         flags |= DRM_MODE_FLAG_NVSYNC;
3047         } else {
3048                 if (tmp & DP_SYNC_HS_HIGH)
3049                         flags |= DRM_MODE_FLAG_PHSYNC;
3050                 else
3051                         flags |= DRM_MODE_FLAG_NHSYNC;
3052
3053                 if (tmp & DP_SYNC_VS_HIGH)
3054                         flags |= DRM_MODE_FLAG_PVSYNC;
3055                 else
3056                         flags |= DRM_MODE_FLAG_NVSYNC;
3057         }
3058
3059         pipe_config->base.adjusted_mode.flags |= flags;
3060
3061         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3062                 pipe_config->limited_color_range = true;
3063
3064         pipe_config->lane_count =
3065                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3066
3067         intel_dp_get_m_n(crtc, pipe_config);
3068
3069         if (port == PORT_A) {
3070                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3071                         pipe_config->port_clock = 162000;
3072                 else
3073                         pipe_config->port_clock = 270000;
3074         }
3075
3076         pipe_config->base.adjusted_mode.crtc_clock =
3077                 intel_dotclock_calculate(pipe_config->port_clock,
3078                                          &pipe_config->dp_m_n);
3079
3080         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3081             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3082                 /*
3083                  * This is a big fat ugly hack.
3084                  *
3085                  * Some machines in UEFI boot mode provide us a VBT that has 18
3086                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3087                  * unknown we fail to light up. Yet the same BIOS boots up with
3088                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3089                  * max, not what it tells us to use.
3090                  *
3091                  * Note: This will still be broken if the eDP panel is not lit
3092                  * up by the BIOS, and thus we can't get the mode at module
3093                  * load.
3094                  */
3095                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3096                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3097                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3098         }
3099 }
3100
3101 static void intel_disable_dp(struct intel_encoder *encoder,
3102                              const struct intel_crtc_state *old_crtc_state,
3103                              const struct drm_connector_state *old_conn_state)
3104 {
3105         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3106
3107         intel_dp->link_trained = false;
3108
3109         if (old_crtc_state->has_audio)
3110                 intel_audio_codec_disable(encoder,
3111                                           old_crtc_state, old_conn_state);
3112
3113         /* Make sure the panel is off before trying to change the mode. But also
3114          * ensure that we have vdd while we switch off the panel. */
3115         intel_edp_panel_vdd_on(intel_dp);
3116         intel_edp_backlight_off(old_conn_state);
3117         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3118         intel_edp_panel_off(intel_dp);
3119 }
3120
3121 static void g4x_disable_dp(struct intel_encoder *encoder,
3122                            const struct intel_crtc_state *old_crtc_state,
3123                            const struct drm_connector_state *old_conn_state)
3124 {
3125         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3126 }
3127
3128 static void vlv_disable_dp(struct intel_encoder *encoder,
3129                            const struct intel_crtc_state *old_crtc_state,
3130                            const struct drm_connector_state *old_conn_state)
3131 {
3132         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3133 }
3134
3135 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3136                                 const struct intel_crtc_state *old_crtc_state,
3137                                 const struct drm_connector_state *old_conn_state)
3138 {
3139         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3140         enum port port = encoder->port;
3141
3142         /*
3143          * Bspec does not list a specific disable sequence for g4x DP.
3144          * Follow the ilk+ sequence (disable pipe before the port) for
3145          * g4x DP as it does not suffer from underruns like the normal
3146          * g4x modeset sequence (disable pipe after the port).
3147          */
3148         intel_dp_link_down(encoder, old_crtc_state);
3149
3150         /* Only ilk+ has port A */
3151         if (port == PORT_A)
3152                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3153 }
3154
3155 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3156                                 const struct intel_crtc_state *old_crtc_state,
3157                                 const struct drm_connector_state *old_conn_state)
3158 {
3159         intel_dp_link_down(encoder, old_crtc_state);
3160 }
3161
3162 static void chv_post_disable_dp(struct intel_encoder *encoder,
3163                                 const struct intel_crtc_state *old_crtc_state,
3164                                 const struct drm_connector_state *old_conn_state)
3165 {
3166         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3167
3168         intel_dp_link_down(encoder, old_crtc_state);
3169
3170         mutex_lock(&dev_priv->sb_lock);
3171
3172         /* Assert data lane reset */
3173         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3174
3175         mutex_unlock(&dev_priv->sb_lock);
3176 }
3177
3178 static void
3179 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3180                          uint32_t *DP,
3181                          uint8_t dp_train_pat)
3182 {
3183         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3184         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3185         enum port port = intel_dig_port->base.port;
3186         uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3187
3188         if (dp_train_pat & train_pat_mask)
3189                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3190                               dp_train_pat & train_pat_mask);
3191
3192         if (HAS_DDI(dev_priv)) {
3193                 uint32_t temp = I915_READ(DP_TP_CTL(port));
3194
3195                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3196                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3197                 else
3198                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3199
3200                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3201                 switch (dp_train_pat & train_pat_mask) {
3202                 case DP_TRAINING_PATTERN_DISABLE:
3203                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3204
3205                         break;
3206                 case DP_TRAINING_PATTERN_1:
3207                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3208                         break;
3209                 case DP_TRAINING_PATTERN_2:
3210                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3211                         break;
3212                 case DP_TRAINING_PATTERN_3:
3213                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3214                         break;
3215                 case DP_TRAINING_PATTERN_4:
3216                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3217                         break;
3218                 }
3219                 I915_WRITE(DP_TP_CTL(port), temp);
3220
3221         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3222                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3223                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3224
3225                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3226                 case DP_TRAINING_PATTERN_DISABLE:
3227                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3228                         break;
3229                 case DP_TRAINING_PATTERN_1:
3230                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3231                         break;
3232                 case DP_TRAINING_PATTERN_2:
3233                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3234                         break;
3235                 case DP_TRAINING_PATTERN_3:
3236                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3237                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3238                         break;
3239                 }
3240
3241         } else {
3242                 *DP &= ~DP_LINK_TRAIN_MASK;
3243
3244                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3245                 case DP_TRAINING_PATTERN_DISABLE:
3246                         *DP |= DP_LINK_TRAIN_OFF;
3247                         break;
3248                 case DP_TRAINING_PATTERN_1:
3249                         *DP |= DP_LINK_TRAIN_PAT_1;
3250                         break;
3251                 case DP_TRAINING_PATTERN_2:
3252                         *DP |= DP_LINK_TRAIN_PAT_2;
3253                         break;
3254                 case DP_TRAINING_PATTERN_3:
3255                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3256                         *DP |= DP_LINK_TRAIN_PAT_2;
3257                         break;
3258                 }
3259         }
3260 }
3261
3262 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3263                                  const struct intel_crtc_state *old_crtc_state)
3264 {
3265         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3266
3267         /* enable with pattern 1 (as per spec) */
3268
3269         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3270
3271         /*
3272          * Magic for VLV/CHV. We _must_ first set up the register
3273          * without actually enabling the port, and then do another
3274          * write to enable the port. Otherwise link training will
3275          * fail when the power sequencer is freshly used for this port.
3276          */
3277         intel_dp->DP |= DP_PORT_EN;
3278         if (old_crtc_state->has_audio)
3279                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3280
3281         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3282         POSTING_READ(intel_dp->output_reg);
3283 }
3284
3285 static void intel_enable_dp(struct intel_encoder *encoder,
3286                             const struct intel_crtc_state *pipe_config,
3287                             const struct drm_connector_state *conn_state)
3288 {
3289         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3290         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3291         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3292         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
3293         enum pipe pipe = crtc->pipe;
3294         intel_wakeref_t wakeref;
3295
3296         if (WARN_ON(dp_reg & DP_PORT_EN))
3297                 return;
3298
3299         with_pps_lock(intel_dp, wakeref) {
3300                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3301                         vlv_init_panel_power_sequencer(encoder, pipe_config);
3302
3303                 intel_dp_enable_port(intel_dp, pipe_config);
3304
3305                 edp_panel_vdd_on(intel_dp);
3306                 edp_panel_on(intel_dp);
3307                 edp_panel_vdd_off(intel_dp, true);
3308         }
3309
3310         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3311                 unsigned int lane_mask = 0x0;
3312
3313                 if (IS_CHERRYVIEW(dev_priv))
3314                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3315
3316                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3317                                     lane_mask);
3318         }
3319
3320         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3321         intel_dp_start_link_train(intel_dp);
3322         intel_dp_stop_link_train(intel_dp);
3323
3324         if (pipe_config->has_audio) {
3325                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3326                                  pipe_name(pipe));
3327                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3328         }
3329 }
3330
3331 static void g4x_enable_dp(struct intel_encoder *encoder,
3332                           const struct intel_crtc_state *pipe_config,
3333                           const struct drm_connector_state *conn_state)
3334 {
3335         intel_enable_dp(encoder, pipe_config, conn_state);
3336         intel_edp_backlight_on(pipe_config, conn_state);
3337 }
3338
3339 static void vlv_enable_dp(struct intel_encoder *encoder,
3340                           const struct intel_crtc_state *pipe_config,
3341                           const struct drm_connector_state *conn_state)
3342 {
3343         intel_edp_backlight_on(pipe_config, conn_state);
3344 }
3345
3346 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3347                               const struct intel_crtc_state *pipe_config,
3348                               const struct drm_connector_state *conn_state)
3349 {
3350         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3351         enum port port = encoder->port;
3352
3353         intel_dp_prepare(encoder, pipe_config);
3354
3355         /* Only ilk+ has port A */
3356         if (port == PORT_A)
3357                 ironlake_edp_pll_on(intel_dp, pipe_config);
3358 }
3359
3360 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3361 {
3362         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3363         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3364         enum pipe pipe = intel_dp->pps_pipe;
3365         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3366
3367         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3368
3369         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3370                 return;
3371
3372         edp_panel_vdd_off_sync(intel_dp);
3373
3374         /*
3375          * VLV seems to get confused when multiple power sequencers
3376          * have the same port selected (even if only one has power/vdd
3377          * enabled). The failure manifests as vlv_wait_port_ready() failing
3378          * CHV on the other hand doesn't seem to mind having the same port
3379          * selected in multiple power sequencers, but let's clear the
3380          * port select always when logically disconnecting a power sequencer
3381          * from a port.
3382          */
3383         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3384                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3385         I915_WRITE(pp_on_reg, 0);
3386         POSTING_READ(pp_on_reg);
3387
3388         intel_dp->pps_pipe = INVALID_PIPE;
3389 }
3390
3391 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3392                                       enum pipe pipe)
3393 {
3394         struct intel_encoder *encoder;
3395
3396         lockdep_assert_held(&dev_priv->pps_mutex);
3397
3398         for_each_intel_dp(&dev_priv->drm, encoder) {
3399                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3400                 enum port port = encoder->port;
3401
3402                 WARN(intel_dp->active_pipe == pipe,
3403                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3404                      pipe_name(pipe), port_name(port));
3405
3406                 if (intel_dp->pps_pipe != pipe)
3407                         continue;
3408
3409                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3410                               pipe_name(pipe), port_name(port));
3411
3412                 /* make sure vdd is off before we steal it */
3413                 vlv_detach_power_sequencer(intel_dp);
3414         }
3415 }
3416
3417 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3418                                            const struct intel_crtc_state *crtc_state)
3419 {
3420         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3421         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3422         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3423
3424         lockdep_assert_held(&dev_priv->pps_mutex);
3425
3426         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3427
3428         if (intel_dp->pps_pipe != INVALID_PIPE &&
3429             intel_dp->pps_pipe != crtc->pipe) {
3430                 /*
3431                  * If another power sequencer was being used on this
3432                  * port previously make sure to turn off vdd there while
3433                  * we still have control of it.
3434                  */
3435                 vlv_detach_power_sequencer(intel_dp);
3436         }
3437
3438         /*
3439          * We may be stealing the power
3440          * sequencer from another port.
3441          */
3442         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3443
3444         intel_dp->active_pipe = crtc->pipe;
3445
3446         if (!intel_dp_is_edp(intel_dp))
3447                 return;
3448
3449         /* now it's all ours */
3450         intel_dp->pps_pipe = crtc->pipe;
3451
3452         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3453                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3454
3455         /* init power sequencer on this pipe and port */
3456         intel_dp_init_panel_power_sequencer(intel_dp);
3457         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3458 }
3459
3460 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3461                               const struct intel_crtc_state *pipe_config,
3462                               const struct drm_connector_state *conn_state)
3463 {
3464         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3465
3466         intel_enable_dp(encoder, pipe_config, conn_state);
3467 }
3468
3469 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3470                                   const struct intel_crtc_state *pipe_config,
3471                                   const struct drm_connector_state *conn_state)
3472 {
3473         intel_dp_prepare(encoder, pipe_config);
3474
3475         vlv_phy_pre_pll_enable(encoder, pipe_config);
3476 }
3477
3478 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3479                               const struct intel_crtc_state *pipe_config,
3480                               const struct drm_connector_state *conn_state)
3481 {
3482         chv_phy_pre_encoder_enable(encoder, pipe_config);
3483
3484         intel_enable_dp(encoder, pipe_config, conn_state);
3485
3486         /* Second common lane will stay alive on its own now */
3487         chv_phy_release_cl2_override(encoder);
3488 }
3489
3490 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3491                                   const struct intel_crtc_state *pipe_config,
3492                                   const struct drm_connector_state *conn_state)
3493 {
3494         intel_dp_prepare(encoder, pipe_config);
3495
3496         chv_phy_pre_pll_enable(encoder, pipe_config);
3497 }
3498
3499 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3500                                     const struct intel_crtc_state *old_crtc_state,
3501                                     const struct drm_connector_state *old_conn_state)
3502 {
3503         chv_phy_post_pll_disable(encoder, old_crtc_state);
3504 }
3505
3506 /*
3507  * Fetch AUX CH registers 0x202 - 0x207 which contain
3508  * link status information
3509  */
3510 bool
3511 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3512 {
3513         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3514                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3515 }
3516
3517 /* These are source-specific values. */
3518 uint8_t
3519 intel_dp_voltage_max(struct intel_dp *intel_dp)
3520 {
3521         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3522         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3523         enum port port = encoder->port;
3524
3525         if (HAS_DDI(dev_priv))
3526                 return intel_ddi_dp_voltage_max(encoder);
3527         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3528                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3529         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3530                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3531         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3532                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3533         else
3534                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3535 }
3536
3537 uint8_t
3538 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3539 {
3540         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3541         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3542         enum port port = encoder->port;
3543
3544         if (HAS_DDI(dev_priv)) {
3545                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3546         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3547                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3548                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3549                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3550                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3551                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3552                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3553                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3554                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3555                 default:
3556                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3557                 }
3558         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3559                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3560                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3561                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3562                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3563                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3564                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3565                 default:
3566                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3567                 }
3568         } else {
3569                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3570                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3571                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3572                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3573                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3574                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3575                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3576                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3577                 default:
3578                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3579                 }
3580         }
3581 }
3582
3583 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3584 {
3585         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3586         unsigned long demph_reg_value, preemph_reg_value,
3587                 uniqtranscale_reg_value;
3588         uint8_t train_set = intel_dp->train_set[0];
3589
3590         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3591         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3592                 preemph_reg_value = 0x0004000;
3593                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3594                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3595                         demph_reg_value = 0x2B405555;
3596                         uniqtranscale_reg_value = 0x552AB83A;
3597                         break;
3598                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3599                         demph_reg_value = 0x2B404040;
3600                         uniqtranscale_reg_value = 0x5548B83A;
3601                         break;
3602                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3603                         demph_reg_value = 0x2B245555;
3604                         uniqtranscale_reg_value = 0x5560B83A;
3605                         break;
3606                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3607                         demph_reg_value = 0x2B405555;
3608                         uniqtranscale_reg_value = 0x5598DA3A;
3609                         break;
3610                 default:
3611                         return 0;
3612                 }
3613                 break;
3614         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3615                 preemph_reg_value = 0x0002000;
3616                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3617                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3618                         demph_reg_value = 0x2B404040;
3619                         uniqtranscale_reg_value = 0x5552B83A;
3620                         break;
3621                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3622                         demph_reg_value = 0x2B404848;
3623                         uniqtranscale_reg_value = 0x5580B83A;
3624                         break;
3625                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3626                         demph_reg_value = 0x2B404040;
3627                         uniqtranscale_reg_value = 0x55ADDA3A;
3628                         break;
3629                 default:
3630                         return 0;
3631                 }
3632                 break;
3633         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3634                 preemph_reg_value = 0x0000000;
3635                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3636                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3637                         demph_reg_value = 0x2B305555;
3638                         uniqtranscale_reg_value = 0x5570B83A;
3639                         break;
3640                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3641                         demph_reg_value = 0x2B2B4040;
3642                         uniqtranscale_reg_value = 0x55ADDA3A;
3643                         break;
3644                 default:
3645                         return 0;
3646                 }
3647                 break;
3648         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3649                 preemph_reg_value = 0x0006000;
3650                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3651                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3652                         demph_reg_value = 0x1B405555;
3653                         uniqtranscale_reg_value = 0x55ADDA3A;
3654                         break;
3655                 default:
3656                         return 0;
3657                 }
3658                 break;
3659         default:
3660                 return 0;
3661         }
3662
3663         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3664                                  uniqtranscale_reg_value, 0);
3665
3666         return 0;
3667 }
3668
3669 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3670 {
3671         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3672         u32 deemph_reg_value, margin_reg_value;
3673         bool uniq_trans_scale = false;
3674         uint8_t train_set = intel_dp->train_set[0];
3675
3676         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3677         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3678                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3679                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3680                         deemph_reg_value = 128;
3681                         margin_reg_value = 52;
3682                         break;
3683                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3684                         deemph_reg_value = 128;
3685                         margin_reg_value = 77;
3686                         break;
3687                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3688                         deemph_reg_value = 128;
3689                         margin_reg_value = 102;
3690                         break;
3691                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3692                         deemph_reg_value = 128;
3693                         margin_reg_value = 154;
3694                         uniq_trans_scale = true;
3695                         break;
3696                 default:
3697                         return 0;
3698                 }
3699                 break;
3700         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3701                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3702                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3703                         deemph_reg_value = 85;
3704                         margin_reg_value = 78;
3705                         break;
3706                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3707                         deemph_reg_value = 85;
3708                         margin_reg_value = 116;
3709                         break;
3710                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3711                         deemph_reg_value = 85;
3712                         margin_reg_value = 154;
3713                         break;
3714                 default:
3715                         return 0;
3716                 }
3717                 break;
3718         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3719                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3720                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3721                         deemph_reg_value = 64;
3722                         margin_reg_value = 104;
3723                         break;
3724                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3725                         deemph_reg_value = 64;
3726                         margin_reg_value = 154;
3727                         break;
3728                 default:
3729                         return 0;
3730                 }
3731                 break;
3732         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3733                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3734                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3735                         deemph_reg_value = 43;
3736                         margin_reg_value = 154;
3737                         break;
3738                 default:
3739                         return 0;
3740                 }
3741                 break;
3742         default:
3743                 return 0;
3744         }
3745
3746         chv_set_phy_signal_level(encoder, deemph_reg_value,
3747                                  margin_reg_value, uniq_trans_scale);
3748
3749         return 0;
3750 }
3751
3752 static uint32_t
3753 g4x_signal_levels(uint8_t train_set)
3754 {
3755         uint32_t        signal_levels = 0;
3756
3757         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3758         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3759         default:
3760                 signal_levels |= DP_VOLTAGE_0_4;
3761                 break;
3762         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3763                 signal_levels |= DP_VOLTAGE_0_6;
3764                 break;
3765         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3766                 signal_levels |= DP_VOLTAGE_0_8;
3767                 break;
3768         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3769                 signal_levels |= DP_VOLTAGE_1_2;
3770                 break;
3771         }
3772         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3773         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3774         default:
3775                 signal_levels |= DP_PRE_EMPHASIS_0;
3776                 break;
3777         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3778                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3779                 break;
3780         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3781                 signal_levels |= DP_PRE_EMPHASIS_6;
3782                 break;
3783         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3784                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3785                 break;
3786         }
3787         return signal_levels;
3788 }
3789
3790 /* SNB CPU eDP voltage swing and pre-emphasis control */
3791 static uint32_t
3792 snb_cpu_edp_signal_levels(uint8_t train_set)
3793 {
3794         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3795                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3796         switch (signal_levels) {
3797         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3798         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3799                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3800         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3801                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3802         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3803         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3804                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3805         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3806         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3807                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3808         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3809         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3810                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3811         default:
3812                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3813                               "0x%x\n", signal_levels);
3814                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3815         }
3816 }
3817
3818 /* IVB CPU eDP voltage swing and pre-emphasis control */
3819 static uint32_t
3820 ivb_cpu_edp_signal_levels(uint8_t train_set)
3821 {
3822         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3823                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3824         switch (signal_levels) {
3825         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3826                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3827         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3828                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3829         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3830                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3831
3832         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3833                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3834         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3835                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3836
3837         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3838                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3839         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3840                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3841
3842         default:
3843                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3844                               "0x%x\n", signal_levels);
3845                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3846         }
3847 }
3848
3849 void
3850 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3851 {
3852         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3853         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3854         enum port port = intel_dig_port->base.port;
3855         uint32_t signal_levels, mask = 0;
3856         uint8_t train_set = intel_dp->train_set[0];
3857
3858         if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
3859                 signal_levels = bxt_signal_levels(intel_dp);
3860         } else if (HAS_DDI(dev_priv)) {
3861                 signal_levels = ddi_signal_levels(intel_dp);
3862                 mask = DDI_BUF_EMP_MASK;
3863         } else if (IS_CHERRYVIEW(dev_priv)) {
3864                 signal_levels = chv_signal_levels(intel_dp);
3865         } else if (IS_VALLEYVIEW(dev_priv)) {
3866                 signal_levels = vlv_signal_levels(intel_dp);
3867         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3868                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3869                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3870         } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
3871                 signal_levels = snb_cpu_edp_signal_levels(train_set);
3872                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3873         } else {
3874                 signal_levels = g4x_signal_levels(train_set);
3875                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3876         }
3877
3878         if (mask)
3879                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3880
3881         DRM_DEBUG_KMS("Using vswing level %d\n",
3882                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3883         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3884                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3885                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3886
3887         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3888
3889         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3890         POSTING_READ(intel_dp->output_reg);
3891 }
3892
3893 void
3894 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3895                                        uint8_t dp_train_pat)
3896 {
3897         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3898         struct drm_i915_private *dev_priv =
3899                 to_i915(intel_dig_port->base.base.dev);
3900
3901         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3902
3903         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3904         POSTING_READ(intel_dp->output_reg);
3905 }
3906
3907 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3908 {
3909         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3910         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3911         enum port port = intel_dig_port->base.port;
3912         uint32_t val;
3913
3914         if (!HAS_DDI(dev_priv))
3915                 return;
3916
3917         val = I915_READ(DP_TP_CTL(port));
3918         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3919         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3920         I915_WRITE(DP_TP_CTL(port), val);
3921
3922         /*
3923          * On PORT_A we can have only eDP in SST mode. There the only reason
3924          * we need to set idle transmission mode is to work around a HW issue
3925          * where we enable the pipe while not in idle link-training mode.
3926          * In this case there is requirement to wait for a minimum number of
3927          * idle patterns to be sent.
3928          */
3929         if (port == PORT_A)
3930                 return;
3931
3932         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3933                                     DP_TP_STATUS_IDLE_DONE,
3934                                     DP_TP_STATUS_IDLE_DONE,
3935                                     1))
3936                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3937 }
3938
3939 static void
3940 intel_dp_link_down(struct intel_encoder *encoder,
3941                    const struct intel_crtc_state *old_crtc_state)
3942 {
3943         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3944         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3945         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3946         enum port port = encoder->port;
3947         uint32_t DP = intel_dp->DP;
3948
3949         if (WARN_ON(HAS_DDI(dev_priv)))
3950                 return;
3951
3952         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3953                 return;
3954
3955         DRM_DEBUG_KMS("\n");
3956
3957         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3958             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3959                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3960                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3961         } else {
3962                 DP &= ~DP_LINK_TRAIN_MASK;
3963                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3964         }
3965         I915_WRITE(intel_dp->output_reg, DP);
3966         POSTING_READ(intel_dp->output_reg);
3967
3968         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3969         I915_WRITE(intel_dp->output_reg, DP);
3970         POSTING_READ(intel_dp->output_reg);
3971
3972         /*
3973          * HW workaround for IBX, we need to move the port
3974          * to transcoder A after disabling it to allow the
3975          * matching HDMI port to be enabled on transcoder A.
3976          */
3977         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3978                 /*
3979                  * We get CPU/PCH FIFO underruns on the other pipe when
3980                  * doing the workaround. Sweep them under the rug.
3981                  */
3982                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3983                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3984
3985                 /* always enable with pattern 1 (as per spec) */
3986                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
3987                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
3988                         DP_LINK_TRAIN_PAT_1;
3989                 I915_WRITE(intel_dp->output_reg, DP);
3990                 POSTING_READ(intel_dp->output_reg);
3991
3992                 DP &= ~DP_PORT_EN;
3993                 I915_WRITE(intel_dp->output_reg, DP);
3994                 POSTING_READ(intel_dp->output_reg);
3995
3996                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3997                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3998                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3999         }
4000
4001         msleep(intel_dp->panel_power_down_delay);
4002
4003         intel_dp->DP = DP;
4004
4005         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4006                 intel_wakeref_t wakeref;
4007
4008                 with_pps_lock(intel_dp, wakeref)
4009                         intel_dp->active_pipe = INVALID_PIPE;
4010         }
4011 }
4012
4013 static void
4014 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4015 {
4016         u8 dpcd_ext[6];
4017
4018         /*
4019          * Prior to DP1.3 the bit represented by
4020          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4021          * if it is set DP_DPCD_REV at 0000h could be at a value less than
4022          * the true capability of the panel. The only way to check is to
4023          * then compare 0000h and 2200h.
4024          */
4025         if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4026               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4027                 return;
4028
4029         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4030                              &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4031                 DRM_ERROR("DPCD failed read at extended capabilities\n");
4032                 return;
4033         }
4034
4035         if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4036                 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n");
4037                 return;
4038         }
4039
4040         if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4041                 return;
4042
4043         DRM_DEBUG_KMS("Base DPCD: %*ph\n",
4044                       (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4045
4046         memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4047 }
4048
4049 bool
4050 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4051 {
4052         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4053                              sizeof(intel_dp->dpcd)) < 0)
4054                 return false; /* aux transfer failed */
4055
4056         intel_dp_extended_receiver_capabilities(intel_dp);
4057
4058         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4059
4060         return intel_dp->dpcd[DP_DPCD_REV] != 0;
4061 }
4062
4063 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4064 {
4065         /*
4066          * Clear the cached register set to avoid using stale values
4067          * for the sinks that do not support DSC.
4068          */
4069         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4070
4071         /* Clear fec_capable to avoid using stale values */
4072         intel_dp->fec_capable = 0;
4073
4074         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4075         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4076             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4077                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4078                                      intel_dp->dsc_dpcd,
4079                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4080                         DRM_ERROR("Failed to read DPCD register 0x%x\n",
4081                                   DP_DSC_SUPPORT);
4082
4083                 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4084                               (int)sizeof(intel_dp->dsc_dpcd),
4085                               intel_dp->dsc_dpcd);
4086
4087                 /* FEC is supported only on DP 1.4 */
4088                 if (!intel_dp_is_edp(intel_dp) &&
4089                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4090                                       &intel_dp->fec_capable) < 0)
4091                         DRM_ERROR("Failed to read FEC DPCD register\n");
4092
4093                 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4094         }
4095 }
4096
4097 static bool
4098 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4099 {
4100         struct drm_i915_private *dev_priv =
4101                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4102
4103         /* this function is meant to be called only once */
4104         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4105
4106         if (!intel_dp_read_dpcd(intel_dp))
4107                 return false;
4108
4109         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4110                          drm_dp_is_branch(intel_dp->dpcd));
4111
4112         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4113                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4114                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4115
4116         /*
4117          * Read the eDP display control registers.
4118          *
4119          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4120          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4121          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4122          * method). The display control registers should read zero if they're
4123          * not supported anyway.
4124          */
4125         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4126                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4127                              sizeof(intel_dp->edp_dpcd))
4128                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
4129                               intel_dp->edp_dpcd);
4130
4131         /*
4132          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4133          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4134          */
4135         intel_psr_init_dpcd(intel_dp);
4136
4137         /* Read the eDP 1.4+ supported link rates. */
4138         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4139                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4140                 int i;
4141
4142                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4143                                 sink_rates, sizeof(sink_rates));
4144
4145                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4146                         int val = le16_to_cpu(sink_rates[i]);
4147
4148                         if (val == 0)
4149                                 break;
4150
4151                         /* Value read multiplied by 200kHz gives the per-lane
4152                          * link rate in kHz. The source rates are, however,
4153                          * stored in terms of LS_Clk kHz. The full conversion
4154                          * back to symbols is
4155                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4156                          */
4157                         intel_dp->sink_rates[i] = (val * 200) / 10;
4158                 }
4159                 intel_dp->num_sink_rates = i;
4160         }
4161
4162         /*
4163          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4164          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4165          */
4166         if (intel_dp->num_sink_rates)
4167                 intel_dp->use_rate_select = true;
4168         else
4169                 intel_dp_set_sink_rates(intel_dp);
4170
4171         intel_dp_set_common_rates(intel_dp);
4172
4173         /* Read the eDP DSC DPCD registers */
4174         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4175                 intel_dp_get_dsc_sink_cap(intel_dp);
4176
4177         return true;
4178 }
4179
4180
4181 static bool
4182 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4183 {
4184         if (!intel_dp_read_dpcd(intel_dp))
4185                 return false;
4186
4187         /* Don't clobber cached eDP rates. */
4188         if (!intel_dp_is_edp(intel_dp)) {
4189                 intel_dp_set_sink_rates(intel_dp);
4190                 intel_dp_set_common_rates(intel_dp);
4191         }
4192
4193         /*
4194          * Some eDP panels do not set a valid value for sink count, that is why
4195          * it don't care about read it here and in intel_edp_init_dpcd().
4196          */
4197         if (!intel_dp_is_edp(intel_dp)) {
4198                 u8 count;
4199                 ssize_t r;
4200
4201                 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4202                 if (r < 1)
4203                         return false;
4204
4205                 /*
4206                  * Sink count can change between short pulse hpd hence
4207                  * a member variable in intel_dp will track any changes
4208                  * between short pulse interrupts.
4209                  */
4210                 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4211
4212                 /*
4213                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4214                  * a dongle is present but no display. Unless we require to know
4215                  * if a dongle is present or not, we don't need to update
4216                  * downstream port information. So, an early return here saves
4217                  * time from performing other operations which are not required.
4218                  */
4219                 if (!intel_dp->sink_count)
4220                         return false;
4221         }
4222
4223         if (!drm_dp_is_branch(intel_dp->dpcd))
4224                 return true; /* native DP sink */
4225
4226         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4227                 return true; /* no per-port downstream info */
4228
4229         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4230                              intel_dp->downstream_ports,
4231                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4232                 return false; /* downstream port status fetch failed */
4233
4234         return true;
4235 }
4236
4237 static bool
4238 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4239 {
4240         u8 mstm_cap;
4241
4242         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4243                 return false;
4244
4245         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4246                 return false;
4247
4248         return mstm_cap & DP_MST_CAP;
4249 }
4250
4251 static bool
4252 intel_dp_can_mst(struct intel_dp *intel_dp)
4253 {
4254         return i915_modparams.enable_dp_mst &&
4255                 intel_dp->can_mst &&
4256                 intel_dp_sink_can_mst(intel_dp);
4257 }
4258
4259 static void
4260 intel_dp_configure_mst(struct intel_dp *intel_dp)
4261 {
4262         struct intel_encoder *encoder =
4263                 &dp_to_dig_port(intel_dp)->base;
4264         bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4265
4266         DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
4267                       port_name(encoder->port), yesno(intel_dp->can_mst),
4268                       yesno(sink_can_mst), yesno(i915_modparams.enable_dp_mst));
4269
4270         if (!intel_dp->can_mst)
4271                 return;
4272
4273         intel_dp->is_mst = sink_can_mst &&
4274                 i915_modparams.enable_dp_mst;
4275
4276         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4277                                         intel_dp->is_mst);
4278 }
4279
4280 static bool
4281 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4282 {
4283         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4284                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4285                 DP_DPRX_ESI_LEN;
4286 }
4287
4288 u16 intel_dp_dsc_get_output_bpp(int link_clock, uint8_t lane_count,
4289                                 int mode_clock, int mode_hdisplay)
4290 {
4291         u16 bits_per_pixel, max_bpp_small_joiner_ram;
4292         int i;
4293
4294         /*
4295          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
4296          * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
4297          * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
4298          * for MST -> TimeSlotsPerMTP has to be calculated
4299          */
4300         bits_per_pixel = (link_clock * lane_count * 8 *
4301                           DP_DSC_FEC_OVERHEAD_FACTOR) /
4302                 mode_clock;
4303
4304         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
4305         max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
4306                 mode_hdisplay;
4307
4308         /*
4309          * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
4310          * check, output bpp from small joiner RAM check)
4311          */
4312         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
4313
4314         /* Error out if the max bpp is less than smallest allowed valid bpp */
4315         if (bits_per_pixel < valid_dsc_bpp[0]) {
4316                 DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
4317                 return 0;
4318         }
4319
4320         /* Find the nearest match in the array of known BPPs from VESA */
4321         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
4322                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
4323                         break;
4324         }
4325         bits_per_pixel = valid_dsc_bpp[i];
4326
4327         /*
4328          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
4329          * fractional part is 0
4330          */
4331         return bits_per_pixel << 4;
4332 }
4333
4334 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
4335                                 int mode_clock,
4336                                 int mode_hdisplay)
4337 {
4338         u8 min_slice_count, i;
4339         int max_slice_width;
4340
4341         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
4342                 min_slice_count = DIV_ROUND_UP(mode_clock,
4343                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
4344         else
4345                 min_slice_count = DIV_ROUND_UP(mode_clock,
4346                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
4347
4348         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
4349         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
4350                 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
4351                               max_slice_width);
4352                 return 0;
4353         }
4354         /* Also take into account max slice width */
4355         min_slice_count = min_t(uint8_t, min_slice_count,
4356                                 DIV_ROUND_UP(mode_hdisplay,
4357                                              max_slice_width));
4358
4359         /* Find the closest match to the valid slice count values */
4360         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
4361                 if (valid_dsc_slicecount[i] >
4362                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
4363                                                     false))
4364                         break;
4365                 if (min_slice_count  <= valid_dsc_slicecount[i])
4366                         return valid_dsc_slicecount[i];
4367         }
4368
4369         DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
4370         return 0;
4371 }
4372
4373 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4374 {
4375         int status = 0;
4376         int test_link_rate;
4377         uint8_t test_lane_count, test_link_bw;
4378         /* (DP CTS 1.2)
4379          * 4.3.1.11
4380          */
4381         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4382         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4383                                    &test_lane_count);
4384
4385         if (status <= 0) {
4386                 DRM_DEBUG_KMS("Lane count read failed\n");
4387                 return DP_TEST_NAK;
4388         }
4389         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4390
4391         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4392                                    &test_link_bw);
4393         if (status <= 0) {
4394                 DRM_DEBUG_KMS("Link Rate read failed\n");
4395                 return DP_TEST_NAK;
4396         }
4397         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4398
4399         /* Validate the requested link rate and lane count */
4400         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4401                                         test_lane_count))
4402                 return DP_TEST_NAK;
4403
4404         intel_dp->compliance.test_lane_count = test_lane_count;
4405         intel_dp->compliance.test_link_rate = test_link_rate;
4406
4407         return DP_TEST_ACK;
4408 }
4409
4410 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4411 {
4412         uint8_t test_pattern;
4413         uint8_t test_misc;
4414         __be16 h_width, v_height;
4415         int status = 0;
4416
4417         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4418         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4419                                    &test_pattern);
4420         if (status <= 0) {
4421                 DRM_DEBUG_KMS("Test pattern read failed\n");
4422                 return DP_TEST_NAK;
4423         }
4424         if (test_pattern != DP_COLOR_RAMP)
4425                 return DP_TEST_NAK;
4426
4427         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4428                                   &h_width, 2);
4429         if (status <= 0) {
4430                 DRM_DEBUG_KMS("H Width read failed\n");
4431                 return DP_TEST_NAK;
4432         }
4433
4434         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4435                                   &v_height, 2);
4436         if (status <= 0) {
4437                 DRM_DEBUG_KMS("V Height read failed\n");
4438                 return DP_TEST_NAK;
4439         }
4440
4441         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4442                                    &test_misc);
4443         if (status <= 0) {
4444                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4445                 return DP_TEST_NAK;
4446         }
4447         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4448                 return DP_TEST_NAK;
4449         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4450                 return DP_TEST_NAK;
4451         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4452         case DP_TEST_BIT_DEPTH_6:
4453                 intel_dp->compliance.test_data.bpc = 6;
4454                 break;
4455         case DP_TEST_BIT_DEPTH_8:
4456                 intel_dp->compliance.test_data.bpc = 8;
4457                 break;
4458         default:
4459                 return DP_TEST_NAK;
4460         }
4461
4462         intel_dp->compliance.test_data.video_pattern = test_pattern;
4463         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4464         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4465         /* Set test active flag here so userspace doesn't interrupt things */
4466         intel_dp->compliance.test_active = 1;
4467
4468         return DP_TEST_ACK;
4469 }
4470
4471 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4472 {
4473         uint8_t test_result = DP_TEST_ACK;
4474         struct intel_connector *intel_connector = intel_dp->attached_connector;
4475         struct drm_connector *connector = &intel_connector->base;
4476
4477         if (intel_connector->detect_edid == NULL ||
4478             connector->edid_corrupt ||
4479             intel_dp->aux.i2c_defer_count > 6) {
4480                 /* Check EDID read for NACKs, DEFERs and corruption
4481                  * (DP CTS 1.2 Core r1.1)
4482                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4483                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4484                  *    4.2.2.6 : EDID corruption detected
4485                  * Use failsafe mode for all cases
4486                  */
4487                 if (intel_dp->aux.i2c_nack_count > 0 ||
4488                         intel_dp->aux.i2c_defer_count > 0)
4489                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4490                                       intel_dp->aux.i2c_nack_count,
4491                                       intel_dp->aux.i2c_defer_count);
4492                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4493         } else {
4494                 struct edid *block = intel_connector->detect_edid;
4495
4496                 /* We have to write the checksum
4497                  * of the last block read
4498                  */
4499                 block += intel_connector->detect_edid->extensions;
4500
4501                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4502                                        block->checksum) <= 0)
4503                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4504
4505                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4506                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4507         }
4508
4509         /* Set test active flag here so userspace doesn't interrupt things */
4510         intel_dp->compliance.test_active = 1;
4511
4512         return test_result;
4513 }
4514
4515 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4516 {
4517         uint8_t test_result = DP_TEST_NAK;
4518         return test_result;
4519 }
4520
4521 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4522 {
4523         uint8_t response = DP_TEST_NAK;
4524         uint8_t request = 0;
4525         int status;
4526
4527         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4528         if (status <= 0) {
4529                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4530                 goto update_status;
4531         }
4532
4533         switch (request) {
4534         case DP_TEST_LINK_TRAINING:
4535                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4536                 response = intel_dp_autotest_link_training(intel_dp);
4537                 break;
4538         case DP_TEST_LINK_VIDEO_PATTERN:
4539                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4540                 response = intel_dp_autotest_video_pattern(intel_dp);
4541                 break;
4542         case DP_TEST_LINK_EDID_READ:
4543                 DRM_DEBUG_KMS("EDID test requested\n");
4544                 response = intel_dp_autotest_edid(intel_dp);
4545                 break;
4546         case DP_TEST_LINK_PHY_TEST_PATTERN:
4547                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4548                 response = intel_dp_autotest_phy_pattern(intel_dp);
4549                 break;
4550         default:
4551                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4552                 break;
4553         }
4554
4555         if (response & DP_TEST_ACK)
4556                 intel_dp->compliance.test_type = request;
4557
4558 update_status:
4559         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4560         if (status <= 0)
4561                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4562 }
4563
4564 static int
4565 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4566 {
4567         bool bret;
4568
4569         if (intel_dp->is_mst) {
4570                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4571                 int ret = 0;
4572                 int retry;
4573                 bool handled;
4574
4575                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4576                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4577 go_again:
4578                 if (bret == true) {
4579
4580                         /* check link status - esi[10] = 0x200c */
4581                         if (intel_dp->active_mst_links > 0 &&
4582                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4583                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4584                                 intel_dp_start_link_train(intel_dp);
4585                                 intel_dp_stop_link_train(intel_dp);
4586                         }
4587
4588                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4589                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4590
4591                         if (handled) {
4592                                 for (retry = 0; retry < 3; retry++) {
4593                                         int wret;
4594                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4595                                                                  DP_SINK_COUNT_ESI+1,
4596                                                                  &esi[1], 3);
4597                                         if (wret == 3) {
4598                                                 break;
4599                                         }
4600                                 }
4601
4602                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4603                                 if (bret == true) {
4604                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4605                                         goto go_again;
4606                                 }
4607                         } else
4608                                 ret = 0;
4609
4610                         return ret;
4611                 } else {
4612                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4613                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4614                         intel_dp->is_mst = false;
4615                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4616                         /* send a hotplug event */
4617                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4618                 }
4619         }
4620         return -EINVAL;
4621 }
4622
4623 static bool
4624 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4625 {
4626         u8 link_status[DP_LINK_STATUS_SIZE];
4627
4628         if (!intel_dp->link_trained)
4629                 return false;
4630
4631         /*
4632          * While PSR source HW is enabled, it will control main-link sending
4633          * frames, enabling and disabling it so trying to do a retrain will fail
4634          * as the link would or not be on or it could mix training patterns
4635          * and frame data at the same time causing retrain to fail.
4636          * Also when exiting PSR, HW will retrain the link anyways fixing
4637          * any link status error.
4638          */
4639         if (intel_psr_enabled(intel_dp))
4640                 return false;
4641
4642         if (!intel_dp_get_link_status(intel_dp, link_status))
4643                 return false;
4644
4645         /*
4646          * Validate the cached values of intel_dp->link_rate and
4647          * intel_dp->lane_count before attempting to retrain.
4648          */
4649         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4650                                         intel_dp->lane_count))
4651                 return false;
4652
4653         /* Retrain if Channel EQ or CR not ok */
4654         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4655 }
4656
4657 int intel_dp_retrain_link(struct intel_encoder *encoder,
4658                           struct drm_modeset_acquire_ctx *ctx)
4659 {
4660         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4661         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4662         struct intel_connector *connector = intel_dp->attached_connector;
4663         struct drm_connector_state *conn_state;
4664         struct intel_crtc_state *crtc_state;
4665         struct intel_crtc *crtc;
4666         int ret;
4667
4668         /* FIXME handle the MST connectors as well */
4669
4670         if (!connector || connector->base.status != connector_status_connected)
4671                 return 0;
4672
4673         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4674                                ctx);
4675         if (ret)
4676                 return ret;
4677
4678         conn_state = connector->base.state;
4679
4680         crtc = to_intel_crtc(conn_state->crtc);
4681         if (!crtc)
4682                 return 0;
4683
4684         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4685         if (ret)
4686                 return ret;
4687
4688         crtc_state = to_intel_crtc_state(crtc->base.state);
4689
4690         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4691
4692         if (!crtc_state->base.active)
4693                 return 0;
4694
4695         if (conn_state->commit &&
4696             !try_wait_for_completion(&conn_state->commit->hw_done))
4697                 return 0;
4698
4699         if (!intel_dp_needs_link_retrain(intel_dp))
4700                 return 0;
4701
4702         /* Suppress underruns caused by re-training */
4703         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4704         if (crtc_state->has_pch_encoder)
4705                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4706                                                       intel_crtc_pch_transcoder(crtc), false);
4707
4708         intel_dp_start_link_train(intel_dp);
4709         intel_dp_stop_link_train(intel_dp);
4710
4711         /* Keep underrun reporting disabled until things are stable */
4712         intel_wait_for_vblank(dev_priv, crtc->pipe);
4713
4714         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4715         if (crtc_state->has_pch_encoder)
4716                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4717                                                       intel_crtc_pch_transcoder(crtc), true);
4718
4719         return 0;
4720 }
4721
4722 /*
4723  * If display is now connected check links status,
4724  * there has been known issues of link loss triggering
4725  * long pulse.
4726  *
4727  * Some sinks (eg. ASUS PB287Q) seem to perform some
4728  * weird HPD ping pong during modesets. So we can apparently
4729  * end up with HPD going low during a modeset, and then
4730  * going back up soon after. And once that happens we must
4731  * retrain the link to get a picture. That's in case no
4732  * userspace component reacted to intermittent HPD dip.
4733  */
4734 static bool intel_dp_hotplug(struct intel_encoder *encoder,
4735                              struct intel_connector *connector)
4736 {
4737         struct drm_modeset_acquire_ctx ctx;
4738         bool changed;
4739         int ret;
4740
4741         changed = intel_encoder_hotplug(encoder, connector);
4742
4743         drm_modeset_acquire_init(&ctx, 0);
4744
4745         for (;;) {
4746                 ret = intel_dp_retrain_link(encoder, &ctx);
4747
4748                 if (ret == -EDEADLK) {
4749                         drm_modeset_backoff(&ctx);
4750                         continue;
4751                 }
4752
4753                 break;
4754         }
4755
4756         drm_modeset_drop_locks(&ctx);
4757         drm_modeset_acquire_fini(&ctx);
4758         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4759
4760         return changed;
4761 }
4762
4763 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
4764 {
4765         u8 val;
4766
4767         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4768                 return;
4769
4770         if (drm_dp_dpcd_readb(&intel_dp->aux,
4771                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4772                 return;
4773
4774         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4775
4776         if (val & DP_AUTOMATED_TEST_REQUEST)
4777                 intel_dp_handle_test_request(intel_dp);
4778
4779         if (val & DP_CP_IRQ)
4780                 intel_hdcp_check_link(intel_dp->attached_connector);
4781
4782         if (val & DP_SINK_SPECIFIC_IRQ)
4783                 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
4784 }
4785
4786 /*
4787  * According to DP spec
4788  * 5.1.2:
4789  *  1. Read DPCD
4790  *  2. Configure link according to Receiver Capabilities
4791  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4792  *  4. Check link status on receipt of hot-plug interrupt
4793  *
4794  * intel_dp_short_pulse -  handles short pulse interrupts
4795  * when full detection is not required.
4796  * Returns %true if short pulse is handled and full detection
4797  * is NOT required and %false otherwise.
4798  */
4799 static bool
4800 intel_dp_short_pulse(struct intel_dp *intel_dp)
4801 {
4802         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4803         u8 old_sink_count = intel_dp->sink_count;
4804         bool ret;
4805
4806         /*
4807          * Clearing compliance test variables to allow capturing
4808          * of values for next automated test request.
4809          */
4810         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4811
4812         /*
4813          * Now read the DPCD to see if it's actually running
4814          * If the current value of sink count doesn't match with
4815          * the value that was stored earlier or dpcd read failed
4816          * we need to do full detection
4817          */
4818         ret = intel_dp_get_dpcd(intel_dp);
4819
4820         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4821                 /* No need to proceed if we are going to do full detect */
4822                 return false;
4823         }
4824
4825         intel_dp_check_service_irq(intel_dp);
4826
4827         /* Handle CEC interrupts, if any */
4828         drm_dp_cec_irq(&intel_dp->aux);
4829
4830         /* defer to the hotplug work for link retraining if needed */
4831         if (intel_dp_needs_link_retrain(intel_dp))
4832                 return false;
4833
4834         intel_psr_short_pulse(intel_dp);
4835
4836         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4837                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4838                 /* Send a Hotplug Uevent to userspace to start modeset */
4839                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4840         }
4841
4842         return true;
4843 }
4844
4845 /* XXX this is probably wrong for multiple downstream ports */
4846 static enum drm_connector_status
4847 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4848 {
4849         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4850         uint8_t *dpcd = intel_dp->dpcd;
4851         uint8_t type;
4852
4853         if (lspcon->active)
4854                 lspcon_resume(lspcon);
4855
4856         if (!intel_dp_get_dpcd(intel_dp))
4857                 return connector_status_disconnected;
4858
4859         if (intel_dp_is_edp(intel_dp))
4860                 return connector_status_connected;
4861
4862         /* if there's no downstream port, we're done */
4863         if (!drm_dp_is_branch(dpcd))
4864                 return connector_status_connected;
4865
4866         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4867         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4868             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4869
4870                 return intel_dp->sink_count ?
4871                 connector_status_connected : connector_status_disconnected;
4872         }
4873
4874         if (intel_dp_can_mst(intel_dp))
4875                 return connector_status_connected;
4876
4877         /* If no HPD, poke DDC gently */
4878         if (drm_probe_ddc(&intel_dp->aux.ddc))
4879                 return connector_status_connected;
4880
4881         /* Well we tried, say unknown for unreliable port types */
4882         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4883                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4884                 if (type == DP_DS_PORT_TYPE_VGA ||
4885                     type == DP_DS_PORT_TYPE_NON_EDID)
4886                         return connector_status_unknown;
4887         } else {
4888                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4889                         DP_DWN_STRM_PORT_TYPE_MASK;
4890                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4891                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4892                         return connector_status_unknown;
4893         }
4894
4895         /* Anything else is out of spec, warn and ignore */
4896         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4897         return connector_status_disconnected;
4898 }
4899
4900 static enum drm_connector_status
4901 edp_detect(struct intel_dp *intel_dp)
4902 {
4903         return connector_status_connected;
4904 }
4905
4906 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4907 {
4908         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4909         u32 bit;
4910
4911         switch (encoder->hpd_pin) {
4912         case HPD_PORT_B:
4913                 bit = SDE_PORTB_HOTPLUG;
4914                 break;
4915         case HPD_PORT_C:
4916                 bit = SDE_PORTC_HOTPLUG;
4917                 break;
4918         case HPD_PORT_D:
4919                 bit = SDE_PORTD_HOTPLUG;
4920                 break;
4921         default:
4922                 MISSING_CASE(encoder->hpd_pin);
4923                 return false;
4924         }
4925
4926         return I915_READ(SDEISR) & bit;
4927 }
4928
4929 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4930 {
4931         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4932         u32 bit;
4933
4934         switch (encoder->hpd_pin) {
4935         case HPD_PORT_B:
4936                 bit = SDE_PORTB_HOTPLUG_CPT;
4937                 break;
4938         case HPD_PORT_C:
4939                 bit = SDE_PORTC_HOTPLUG_CPT;
4940                 break;
4941         case HPD_PORT_D:
4942                 bit = SDE_PORTD_HOTPLUG_CPT;
4943                 break;
4944         default:
4945                 MISSING_CASE(encoder->hpd_pin);
4946                 return false;
4947         }
4948
4949         return I915_READ(SDEISR) & bit;
4950 }
4951
4952 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4953 {
4954         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4955         u32 bit;
4956
4957         switch (encoder->hpd_pin) {
4958         case HPD_PORT_A:
4959                 bit = SDE_PORTA_HOTPLUG_SPT;
4960                 break;
4961         case HPD_PORT_E:
4962                 bit = SDE_PORTE_HOTPLUG_SPT;
4963                 break;
4964         default:
4965                 return cpt_digital_port_connected(encoder);
4966         }
4967
4968         return I915_READ(SDEISR) & bit;
4969 }
4970
4971 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4972 {
4973         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4974         u32 bit;
4975
4976         switch (encoder->hpd_pin) {
4977         case HPD_PORT_B:
4978                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4979                 break;
4980         case HPD_PORT_C:
4981                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4982                 break;
4983         case HPD_PORT_D:
4984                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4985                 break;
4986         default:
4987                 MISSING_CASE(encoder->hpd_pin);
4988                 return false;
4989         }
4990
4991         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4992 }
4993
4994 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4995 {
4996         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4997         u32 bit;
4998
4999         switch (encoder->hpd_pin) {
5000         case HPD_PORT_B:
5001                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
5002                 break;
5003         case HPD_PORT_C:
5004                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
5005                 break;
5006         case HPD_PORT_D:
5007                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
5008                 break;
5009         default:
5010                 MISSING_CASE(encoder->hpd_pin);
5011                 return false;
5012         }
5013
5014         return I915_READ(PORT_HOTPLUG_STAT) & bit;
5015 }
5016
5017 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
5018 {
5019         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5020
5021         if (encoder->hpd_pin == HPD_PORT_A)
5022                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5023         else
5024                 return ibx_digital_port_connected(encoder);
5025 }
5026
5027 static bool snb_digital_port_connected(struct intel_encoder *encoder)
5028 {
5029         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5030
5031         if (encoder->hpd_pin == HPD_PORT_A)
5032                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5033         else
5034                 return cpt_digital_port_connected(encoder);
5035 }
5036
5037 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
5038 {
5039         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5040
5041         if (encoder->hpd_pin == HPD_PORT_A)
5042                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
5043         else
5044                 return cpt_digital_port_connected(encoder);
5045 }
5046
5047 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5048 {
5049         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5050
5051         if (encoder->hpd_pin == HPD_PORT_A)
5052                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
5053         else
5054                 return cpt_digital_port_connected(encoder);
5055 }
5056
5057 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5058 {
5059         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5060         u32 bit;
5061
5062         switch (encoder->hpd_pin) {
5063         case HPD_PORT_A:
5064                 bit = BXT_DE_PORT_HP_DDIA;
5065                 break;
5066         case HPD_PORT_B:
5067                 bit = BXT_DE_PORT_HP_DDIB;
5068                 break;
5069         case HPD_PORT_C:
5070                 bit = BXT_DE_PORT_HP_DDIC;
5071                 break;
5072         default:
5073                 MISSING_CASE(encoder->hpd_pin);
5074                 return false;
5075         }
5076
5077         return I915_READ(GEN8_DE_PORT_ISR) & bit;
5078 }
5079
5080 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
5081                                      struct intel_digital_port *intel_dig_port)
5082 {
5083         enum port port = intel_dig_port->base.port;
5084
5085         return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
5086 }
5087
5088 static const char *tc_type_name(enum tc_port_type type)
5089 {
5090         static const char * const names[] = {
5091                 [TC_PORT_UNKNOWN] = "unknown",
5092                 [TC_PORT_LEGACY] = "legacy",
5093                 [TC_PORT_TYPEC] = "typec",
5094                 [TC_PORT_TBT] = "tbt",
5095         };
5096
5097         if (WARN_ON(type >= ARRAY_SIZE(names)))
5098                 type = TC_PORT_UNKNOWN;
5099
5100         return names[type];
5101 }
5102
5103 static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
5104                                     struct intel_digital_port *intel_dig_port,
5105                                     bool is_legacy, bool is_typec, bool is_tbt)
5106 {
5107         enum port port = intel_dig_port->base.port;
5108         enum tc_port_type old_type = intel_dig_port->tc_type;
5109
5110         WARN_ON(is_legacy + is_typec + is_tbt != 1);
5111
5112         if (is_legacy)
5113                 intel_dig_port->tc_type = TC_PORT_LEGACY;
5114         else if (is_typec)
5115                 intel_dig_port->tc_type = TC_PORT_TYPEC;
5116         else if (is_tbt)
5117                 intel_dig_port->tc_type = TC_PORT_TBT;
5118         else
5119                 return;
5120
5121         /* Types are not supposed to be changed at runtime. */
5122         WARN_ON(old_type != TC_PORT_UNKNOWN &&
5123                 old_type != intel_dig_port->tc_type);
5124
5125         if (old_type != intel_dig_port->tc_type)
5126                 DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
5127                               tc_type_name(intel_dig_port->tc_type));
5128 }
5129
5130 /*
5131  * This function implements the first part of the Connect Flow described by our
5132  * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
5133  * lanes, EDID, etc) is done as needed in the typical places.
5134  *
5135  * Unlike the other ports, type-C ports are not available to use as soon as we
5136  * get a hotplug. The type-C PHYs can be shared between multiple controllers:
5137  * display, USB, etc. As a result, handshaking through FIA is required around
5138  * connect and disconnect to cleanly transfer ownership with the controller and
5139  * set the type-C power state.
5140  *
5141  * We could opt to only do the connect flow when we actually try to use the AUX
5142  * channels or do a modeset, then immediately run the disconnect flow after
5143  * usage, but there are some implications on this for a dynamic environment:
5144  * things may go away or change behind our backs. So for now our driver is
5145  * always trying to acquire ownership of the controller as soon as it gets an
5146  * interrupt (or polls state and sees a port is connected) and only gives it
5147  * back when it sees a disconnect. Implementation of a more fine-grained model
5148  * will require a lot of coordination with user space and thorough testing for
5149  * the extra possible cases.
5150  */
5151 static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
5152                                struct intel_digital_port *dig_port)
5153 {
5154         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
5155         u32 val;
5156
5157         if (dig_port->tc_type != TC_PORT_LEGACY &&
5158             dig_port->tc_type != TC_PORT_TYPEC)
5159                 return true;
5160
5161         val = I915_READ(PORT_TX_DFLEXDPPMS);
5162         if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
5163                 DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
5164                 WARN_ON(dig_port->tc_legacy_port);
5165                 return false;
5166         }
5167
5168         /*
5169          * This function may be called many times in a row without an HPD event
5170          * in between, so try to avoid the write when we can.
5171          */
5172         val = I915_READ(PORT_TX_DFLEXDPCSSS);
5173         if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
5174                 val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
5175                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
5176         }
5177
5178         /*
5179          * Now we have to re-check the live state, in case the port recently
5180          * became disconnected. Not necessary for legacy mode.
5181          */
5182         if (dig_port->tc_type == TC_PORT_TYPEC &&
5183             !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
5184                 DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
5185                 icl_tc_phy_disconnect(dev_priv, dig_port);
5186                 return false;
5187         }
5188
5189         return true;
5190 }
5191
5192 /*
5193  * See the comment at the connect function. This implements the Disconnect
5194  * Flow.
5195  */
5196 void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
5197                            struct intel_digital_port *dig_port)
5198 {
5199         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
5200
5201         if (dig_port->tc_type == TC_PORT_UNKNOWN)
5202                 return;
5203
5204         /*
5205          * TBT disconnection flow is read the live status, what was done in
5206          * caller.
5207          */
5208         if (dig_port->tc_type == TC_PORT_TYPEC ||
5209             dig_port->tc_type == TC_PORT_LEGACY) {
5210                 u32 val;
5211
5212                 val = I915_READ(PORT_TX_DFLEXDPCSSS);
5213                 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
5214                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
5215         }
5216
5217         DRM_DEBUG_KMS("Port %c TC type %s disconnected\n",
5218                       port_name(dig_port->base.port),
5219                       tc_type_name(dig_port->tc_type));
5220
5221         dig_port->tc_type = TC_PORT_UNKNOWN;
5222 }
5223
5224 /*
5225  * The type-C ports are different because even when they are connected, they may
5226  * not be available/usable by the graphics driver: see the comment on
5227  * icl_tc_phy_connect(). So in our driver instead of adding the additional
5228  * concept of "usable" and make everything check for "connected and usable" we
5229  * define a port as "connected" when it is not only connected, but also when it
5230  * is usable by the rest of the driver. That maintains the old assumption that
5231  * connected ports are usable, and avoids exposing to the users objects they
5232  * can't really use.
5233  */
5234 static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
5235                                   struct intel_digital_port *intel_dig_port)
5236 {
5237         enum port port = intel_dig_port->base.port;
5238         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
5239         bool is_legacy, is_typec, is_tbt;
5240         u32 dpsp;
5241
5242         /*
5243          * WARN if we got a legacy port HPD, but VBT didn't mark the port as
5244          * legacy. Treat the port as legacy from now on.
5245          */
5246         if (WARN_ON(!intel_dig_port->tc_legacy_port &&
5247                     I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port)))
5248                 intel_dig_port->tc_legacy_port = true;
5249         is_legacy = intel_dig_port->tc_legacy_port;
5250
5251         /*
5252          * The spec says we shouldn't be using the ISR bits for detecting
5253          * between TC and TBT. We should use DFLEXDPSP.
5254          */
5255         dpsp = I915_READ(PORT_TX_DFLEXDPSP);
5256         is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
5257         is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
5258
5259         if (!is_legacy && !is_typec && !is_tbt) {
5260                 icl_tc_phy_disconnect(dev_priv, intel_dig_port);
5261
5262                 return false;
5263         }
5264
5265         icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
5266                                 is_tbt);
5267
5268         if (!icl_tc_phy_connect(dev_priv, intel_dig_port))
5269                 return false;
5270
5271         return true;
5272 }
5273
5274 static bool icl_digital_port_connected(struct intel_encoder *encoder)
5275 {
5276         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5277         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
5278
5279         if (intel_port_is_combophy(dev_priv, encoder->port))
5280                 return icl_combo_port_connected(dev_priv, dig_port);
5281         else if (intel_port_is_tc(dev_priv, encoder->port))
5282                 return icl_tc_port_connected(dev_priv, dig_port);
5283         else
5284                 MISSING_CASE(encoder->hpd_pin);
5285
5286         return false;
5287 }
5288
5289 /*
5290  * intel_digital_port_connected - is the specified port connected?
5291  * @encoder: intel_encoder
5292  *
5293  * In cases where there's a connector physically connected but it can't be used
5294  * by our hardware we also return false, since the rest of the driver should
5295  * pretty much treat the port as disconnected. This is relevant for type-C
5296  * (starting on ICL) where there's ownership involved.
5297  *
5298  * Return %true if port is connected, %false otherwise.
5299  */
5300 bool intel_digital_port_connected(struct intel_encoder *encoder)
5301 {
5302         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5303
5304         if (HAS_GMCH_DISPLAY(dev_priv)) {
5305                 if (IS_GM45(dev_priv))
5306                         return gm45_digital_port_connected(encoder);
5307                 else
5308                         return g4x_digital_port_connected(encoder);
5309         }
5310
5311         if (INTEL_GEN(dev_priv) >= 11)
5312                 return icl_digital_port_connected(encoder);
5313         else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv))
5314                 return spt_digital_port_connected(encoder);
5315         else if (IS_GEN9_LP(dev_priv))
5316                 return bxt_digital_port_connected(encoder);
5317         else if (IS_GEN(dev_priv, 8))
5318                 return bdw_digital_port_connected(encoder);
5319         else if (IS_GEN(dev_priv, 7))
5320                 return ivb_digital_port_connected(encoder);
5321         else if (IS_GEN(dev_priv, 6))
5322                 return snb_digital_port_connected(encoder);
5323         else if (IS_GEN(dev_priv, 5))
5324                 return ilk_digital_port_connected(encoder);
5325
5326         MISSING_CASE(INTEL_GEN(dev_priv));
5327         return false;
5328 }
5329
5330 static struct edid *
5331 intel_dp_get_edid(struct intel_dp *intel_dp)
5332 {
5333         struct intel_connector *intel_connector = intel_dp->attached_connector;
5334
5335         /* use cached edid if we have one */
5336         if (intel_connector->edid) {
5337                 /* invalid edid */
5338                 if (IS_ERR(intel_connector->edid))
5339                         return NULL;
5340
5341                 return drm_edid_duplicate(intel_connector->edid);
5342         } else
5343                 return drm_get_edid(&intel_connector->base,
5344                                     &intel_dp->aux.ddc);
5345 }
5346
5347 static void
5348 intel_dp_set_edid(struct intel_dp *intel_dp)
5349 {
5350         struct intel_connector *intel_connector = intel_dp->attached_connector;
5351         struct edid *edid;
5352
5353         intel_dp_unset_edid(intel_dp);
5354         edid = intel_dp_get_edid(intel_dp);
5355         intel_connector->detect_edid = edid;
5356
5357         intel_dp->has_audio = drm_detect_monitor_audio(edid);
5358         drm_dp_cec_set_edid(&intel_dp->aux, edid);
5359 }
5360
5361 static void
5362 intel_dp_unset_edid(struct intel_dp *intel_dp)
5363 {
5364         struct intel_connector *intel_connector = intel_dp->attached_connector;
5365
5366         drm_dp_cec_unset_edid(&intel_dp->aux);
5367         kfree(intel_connector->detect_edid);
5368         intel_connector->detect_edid = NULL;
5369
5370         intel_dp->has_audio = false;
5371 }
5372
5373 static int
5374 intel_dp_detect(struct drm_connector *connector,
5375                 struct drm_modeset_acquire_ctx *ctx,
5376                 bool force)
5377 {
5378         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5379         struct intel_dp *intel_dp = intel_attached_dp(connector);
5380         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5381         struct intel_encoder *encoder = &dig_port->base;
5382         enum drm_connector_status status;
5383         enum intel_display_power_domain aux_domain =
5384                 intel_aux_power_domain(dig_port);
5385         intel_wakeref_t wakeref;
5386
5387         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5388                       connector->base.id, connector->name);
5389         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5390
5391         wakeref = intel_display_power_get(dev_priv, aux_domain);
5392
5393         /* Can't disconnect eDP */
5394         if (intel_dp_is_edp(intel_dp))
5395                 status = edp_detect(intel_dp);
5396         else if (intel_digital_port_connected(encoder))
5397                 status = intel_dp_detect_dpcd(intel_dp);
5398         else
5399                 status = connector_status_disconnected;
5400
5401         if (status == connector_status_disconnected) {
5402                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5403                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5404
5405                 if (intel_dp->is_mst) {
5406                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5407                                       intel_dp->is_mst,
5408                                       intel_dp->mst_mgr.mst_state);
5409                         intel_dp->is_mst = false;
5410                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5411                                                         intel_dp->is_mst);
5412                 }
5413
5414                 goto out;
5415         }
5416
5417         if (intel_dp->reset_link_params) {
5418                 /* Initial max link lane count */
5419                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5420
5421                 /* Initial max link rate */
5422                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5423
5424                 intel_dp->reset_link_params = false;
5425         }
5426
5427         intel_dp_print_rates(intel_dp);
5428
5429         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5430         if (INTEL_GEN(dev_priv) >= 11)
5431                 intel_dp_get_dsc_sink_cap(intel_dp);
5432
5433         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5434                          drm_dp_is_branch(intel_dp->dpcd));
5435
5436         intel_dp_configure_mst(intel_dp);
5437
5438         if (intel_dp->is_mst) {
5439                 /*
5440                  * If we are in MST mode then this connector
5441                  * won't appear connected or have anything
5442                  * with EDID on it
5443                  */
5444                 status = connector_status_disconnected;
5445                 goto out;
5446         }
5447
5448         /*
5449          * Some external monitors do not signal loss of link synchronization
5450          * with an IRQ_HPD, so force a link status check.
5451          */
5452         if (!intel_dp_is_edp(intel_dp)) {
5453                 int ret;
5454
5455                 ret = intel_dp_retrain_link(encoder, ctx);
5456                 if (ret) {
5457                         intel_display_power_put(dev_priv, aux_domain, wakeref);
5458                         return ret;
5459                 }
5460         }
5461
5462         /*
5463          * Clearing NACK and defer counts to get their exact values
5464          * while reading EDID which are required by Compliance tests
5465          * 4.2.2.4 and 4.2.2.5
5466          */
5467         intel_dp->aux.i2c_nack_count = 0;
5468         intel_dp->aux.i2c_defer_count = 0;
5469
5470         intel_dp_set_edid(intel_dp);
5471         if (intel_dp_is_edp(intel_dp) ||
5472             to_intel_connector(connector)->detect_edid)
5473                 status = connector_status_connected;
5474
5475         intel_dp_check_service_irq(intel_dp);
5476
5477 out:
5478         if (status != connector_status_connected && !intel_dp->is_mst)
5479                 intel_dp_unset_edid(intel_dp);
5480
5481         intel_display_power_put(dev_priv, aux_domain, wakeref);
5482         return status;
5483 }
5484
5485 static void
5486 intel_dp_force(struct drm_connector *connector)
5487 {
5488         struct intel_dp *intel_dp = intel_attached_dp(connector);
5489         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5490         struct intel_encoder *intel_encoder = &dig_port->base;
5491         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5492         enum intel_display_power_domain aux_domain =
5493                 intel_aux_power_domain(dig_port);
5494         intel_wakeref_t wakeref;
5495
5496         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5497                       connector->base.id, connector->name);
5498         intel_dp_unset_edid(intel_dp);
5499
5500         if (connector->status != connector_status_connected)
5501                 return;
5502
5503         wakeref = intel_display_power_get(dev_priv, aux_domain);
5504
5505         intel_dp_set_edid(intel_dp);
5506
5507         intel_display_power_put(dev_priv, aux_domain, wakeref);
5508 }
5509
5510 static int intel_dp_get_modes(struct drm_connector *connector)
5511 {
5512         struct intel_connector *intel_connector = to_intel_connector(connector);
5513         struct edid *edid;
5514
5515         edid = intel_connector->detect_edid;
5516         if (edid) {
5517                 int ret = intel_connector_update_modes(connector, edid);
5518                 if (ret)
5519                         return ret;
5520         }
5521
5522         /* if eDP has no EDID, fall back to fixed mode */
5523         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5524             intel_connector->panel.fixed_mode) {
5525                 struct drm_display_mode *mode;
5526
5527                 mode = drm_mode_duplicate(connector->dev,
5528                                           intel_connector->panel.fixed_mode);
5529                 if (mode) {
5530                         drm_mode_probed_add(connector, mode);
5531                         return 1;
5532                 }
5533         }
5534
5535         return 0;
5536 }
5537
5538 static int
5539 intel_dp_connector_register(struct drm_connector *connector)
5540 {
5541         struct intel_dp *intel_dp = intel_attached_dp(connector);
5542         struct drm_device *dev = connector->dev;
5543         int ret;
5544
5545         ret = intel_connector_register(connector);
5546         if (ret)
5547                 return ret;
5548
5549         i915_debugfs_connector_add(connector);
5550
5551         DRM_DEBUG_KMS("registering %s bus for %s\n",
5552                       intel_dp->aux.name, connector->kdev->kobj.name);
5553
5554         intel_dp->aux.dev = connector->kdev;
5555         ret = drm_dp_aux_register(&intel_dp->aux);
5556         if (!ret)
5557                 drm_dp_cec_register_connector(&intel_dp->aux,
5558                                               connector->name, dev->dev);
5559         return ret;
5560 }
5561
5562 static void
5563 intel_dp_connector_unregister(struct drm_connector *connector)
5564 {
5565         struct intel_dp *intel_dp = intel_attached_dp(connector);
5566
5567         drm_dp_cec_unregister_connector(&intel_dp->aux);
5568         drm_dp_aux_unregister(&intel_dp->aux);
5569         intel_connector_unregister(connector);
5570 }
5571
5572 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5573 {
5574         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5575         struct intel_dp *intel_dp = &intel_dig_port->dp;
5576
5577         intel_dp_mst_encoder_cleanup(intel_dig_port);
5578         if (intel_dp_is_edp(intel_dp)) {
5579                 intel_wakeref_t wakeref;
5580
5581                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5582                 /*
5583                  * vdd might still be enabled do to the delayed vdd off.
5584                  * Make sure vdd is actually turned off here.
5585                  */
5586                 with_pps_lock(intel_dp, wakeref)
5587                         edp_panel_vdd_off_sync(intel_dp);
5588
5589                 if (intel_dp->edp_notifier.notifier_call) {
5590                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5591                         intel_dp->edp_notifier.notifier_call = NULL;
5592                 }
5593         }
5594
5595         intel_dp_aux_fini(intel_dp);
5596 }
5597
5598 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5599 {
5600         intel_dp_encoder_flush_work(encoder);
5601
5602         drm_encoder_cleanup(encoder);
5603         kfree(enc_to_dig_port(encoder));
5604 }
5605
5606 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5607 {
5608         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5609         intel_wakeref_t wakeref;
5610
5611         if (!intel_dp_is_edp(intel_dp))
5612                 return;
5613
5614         /*
5615          * vdd might still be enabled do to the delayed vdd off.
5616          * Make sure vdd is actually turned off here.
5617          */
5618         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5619         with_pps_lock(intel_dp, wakeref)
5620                 edp_panel_vdd_off_sync(intel_dp);
5621 }
5622
5623 static
5624 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5625                                 u8 *an)
5626 {
5627         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5628         static const struct drm_dp_aux_msg msg = {
5629                 .request = DP_AUX_NATIVE_WRITE,
5630                 .address = DP_AUX_HDCP_AKSV,
5631                 .size = DRM_HDCP_KSV_LEN,
5632         };
5633         uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5634         ssize_t dpcd_ret;
5635         int ret;
5636
5637         /* Output An first, that's easy */
5638         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5639                                      an, DRM_HDCP_AN_LEN);
5640         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5641                 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5642                               dpcd_ret);
5643                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5644         }
5645
5646         /*
5647          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5648          * order to get it on the wire, we need to create the AUX header as if
5649          * we were writing the data, and then tickle the hardware to output the
5650          * data once the header is sent out.
5651          */
5652         intel_dp_aux_header(txbuf, &msg);
5653
5654         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5655                                 rxbuf, sizeof(rxbuf),
5656                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5657         if (ret < 0) {
5658                 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5659                 return ret;
5660         } else if (ret == 0) {
5661                 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5662                 return -EIO;
5663         }
5664
5665         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5666         if (reply != DP_AUX_NATIVE_REPLY_ACK) {
5667                 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
5668                               reply);
5669                 return -EIO;
5670         }
5671         return 0;
5672 }
5673
5674 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5675                                    u8 *bksv)
5676 {
5677         ssize_t ret;
5678         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5679                                DRM_HDCP_KSV_LEN);
5680         if (ret != DRM_HDCP_KSV_LEN) {
5681                 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5682                 return ret >= 0 ? -EIO : ret;
5683         }
5684         return 0;
5685 }
5686
5687 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5688                                       u8 *bstatus)
5689 {
5690         ssize_t ret;
5691         /*
5692          * For some reason the HDMI and DP HDCP specs call this register
5693          * definition by different names. In the HDMI spec, it's called BSTATUS,
5694          * but in DP it's called BINFO.
5695          */
5696         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5697                                bstatus, DRM_HDCP_BSTATUS_LEN);
5698         if (ret != DRM_HDCP_BSTATUS_LEN) {
5699                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5700                 return ret >= 0 ? -EIO : ret;
5701         }
5702         return 0;
5703 }
5704
5705 static
5706 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5707                              u8 *bcaps)
5708 {
5709         ssize_t ret;
5710
5711         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5712                                bcaps, 1);
5713         if (ret != 1) {
5714                 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
5715                 return ret >= 0 ? -EIO : ret;
5716         }
5717
5718         return 0;
5719 }
5720
5721 static
5722 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5723                                    bool *repeater_present)
5724 {
5725         ssize_t ret;
5726         u8 bcaps;
5727
5728         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5729         if (ret)
5730                 return ret;
5731
5732         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5733         return 0;
5734 }
5735
5736 static
5737 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5738                                 u8 *ri_prime)
5739 {
5740         ssize_t ret;
5741         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5742                                ri_prime, DRM_HDCP_RI_LEN);
5743         if (ret != DRM_HDCP_RI_LEN) {
5744                 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
5745                 return ret >= 0 ? -EIO : ret;
5746         }
5747         return 0;
5748 }
5749
5750 static
5751 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5752                                  bool *ksv_ready)
5753 {
5754         ssize_t ret;
5755         u8 bstatus;
5756         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5757                                &bstatus, 1);
5758         if (ret != 1) {
5759                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5760                 return ret >= 0 ? -EIO : ret;
5761         }
5762         *ksv_ready = bstatus & DP_BSTATUS_READY;
5763         return 0;
5764 }
5765
5766 static
5767 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5768                                 int num_downstream, u8 *ksv_fifo)
5769 {
5770         ssize_t ret;
5771         int i;
5772
5773         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5774         for (i = 0; i < num_downstream; i += 3) {
5775                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5776                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5777                                        DP_AUX_HDCP_KSV_FIFO,
5778                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5779                                        len);
5780                 if (ret != len) {
5781                         DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
5782                                       i, ret);
5783                         return ret >= 0 ? -EIO : ret;
5784                 }
5785         }
5786         return 0;
5787 }
5788
5789 static
5790 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5791                                     int i, u32 *part)
5792 {
5793         ssize_t ret;
5794
5795         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5796                 return -EINVAL;
5797
5798         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5799                                DP_AUX_HDCP_V_PRIME(i), part,
5800                                DRM_HDCP_V_PRIME_PART_LEN);
5801         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5802                 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5803                 return ret >= 0 ? -EIO : ret;
5804         }
5805         return 0;
5806 }
5807
5808 static
5809 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5810                                     bool enable)
5811 {
5812         /* Not used for single stream DisplayPort setups */
5813         return 0;
5814 }
5815
5816 static
5817 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5818 {
5819         ssize_t ret;
5820         u8 bstatus;
5821
5822         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5823                                &bstatus, 1);
5824         if (ret != 1) {
5825                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5826                 return false;
5827         }
5828
5829         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5830 }
5831
5832 static
5833 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5834                           bool *hdcp_capable)
5835 {
5836         ssize_t ret;
5837         u8 bcaps;
5838
5839         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5840         if (ret)
5841                 return ret;
5842
5843         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5844         return 0;
5845 }
5846
5847 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
5848         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
5849         .read_bksv = intel_dp_hdcp_read_bksv,
5850         .read_bstatus = intel_dp_hdcp_read_bstatus,
5851         .repeater_present = intel_dp_hdcp_repeater_present,
5852         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
5853         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
5854         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
5855         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
5856         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
5857         .check_link = intel_dp_hdcp_check_link,
5858         .hdcp_capable = intel_dp_hdcp_capable,
5859 };
5860
5861 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5862 {
5863         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5864         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5865
5866         lockdep_assert_held(&dev_priv->pps_mutex);
5867
5868         if (!edp_have_panel_vdd(intel_dp))
5869                 return;
5870
5871         /*
5872          * The VDD bit needs a power domain reference, so if the bit is
5873          * already enabled when we boot or resume, grab this reference and
5874          * schedule a vdd off, so we don't hold on to the reference
5875          * indefinitely.
5876          */
5877         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5878         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
5879
5880         edp_panel_vdd_schedule_off(intel_dp);
5881 }
5882
5883 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5884 {
5885         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5886         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5887         enum pipe pipe;
5888
5889         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
5890                                   encoder->port, &pipe))
5891                 return pipe;
5892
5893         return INVALID_PIPE;
5894 }
5895
5896 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5897 {
5898         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5899         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5900         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5901         intel_wakeref_t wakeref;
5902
5903         if (!HAS_DDI(dev_priv))
5904                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5905
5906         if (lspcon->active)
5907                 lspcon_resume(lspcon);
5908
5909         intel_dp->reset_link_params = true;
5910
5911         with_pps_lock(intel_dp, wakeref) {
5912                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5913                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5914
5915                 if (intel_dp_is_edp(intel_dp)) {
5916                         /*
5917                          * Reinit the power sequencer, in case BIOS did
5918                          * something nasty with it.
5919                          */
5920                         intel_dp_pps_init(intel_dp);
5921                         intel_edp_panel_vdd_sanitize(intel_dp);
5922                 }
5923         }
5924 }
5925
5926 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5927         .force = intel_dp_force,
5928         .fill_modes = drm_helper_probe_single_connector_modes,
5929         .atomic_get_property = intel_digital_connector_atomic_get_property,
5930         .atomic_set_property = intel_digital_connector_atomic_set_property,
5931         .late_register = intel_dp_connector_register,
5932         .early_unregister = intel_dp_connector_unregister,
5933         .destroy = intel_connector_destroy,
5934         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5935         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5936 };
5937
5938 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5939         .detect_ctx = intel_dp_detect,
5940         .get_modes = intel_dp_get_modes,
5941         .mode_valid = intel_dp_mode_valid,
5942         .atomic_check = intel_digital_connector_atomic_check,
5943 };
5944
5945 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5946         .reset = intel_dp_encoder_reset,
5947         .destroy = intel_dp_encoder_destroy,
5948 };
5949
5950 enum irqreturn
5951 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5952 {
5953         struct intel_dp *intel_dp = &intel_dig_port->dp;
5954         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5955         enum irqreturn ret = IRQ_NONE;
5956         intel_wakeref_t wakeref;
5957
5958         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5959                 /*
5960                  * vdd off can generate a long pulse on eDP which
5961                  * would require vdd on to handle it, and thus we
5962                  * would end up in an endless cycle of
5963                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5964                  */
5965                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5966                               port_name(intel_dig_port->base.port));
5967                 return IRQ_HANDLED;
5968         }
5969
5970         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5971                       port_name(intel_dig_port->base.port),
5972                       long_hpd ? "long" : "short");
5973
5974         if (long_hpd) {
5975                 intel_dp->reset_link_params = true;
5976                 return IRQ_NONE;
5977         }
5978
5979         wakeref = intel_display_power_get(dev_priv,
5980                                           intel_aux_power_domain(intel_dig_port));
5981
5982         if (intel_dp->is_mst) {
5983                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5984                         /*
5985                          * If we were in MST mode, and device is not
5986                          * there, get out of MST mode
5987                          */
5988                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5989                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5990                         intel_dp->is_mst = false;
5991                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5992                                                         intel_dp->is_mst);
5993                         goto put_power;
5994                 }
5995         }
5996
5997         if (!intel_dp->is_mst) {
5998                 bool handled;
5999
6000                 handled = intel_dp_short_pulse(intel_dp);
6001
6002                 if (!handled)
6003                         goto put_power;
6004         }
6005
6006         ret = IRQ_HANDLED;
6007
6008 put_power:
6009         intel_display_power_put(dev_priv,
6010                                 intel_aux_power_domain(intel_dig_port),
6011                                 wakeref);
6012
6013         return ret;
6014 }
6015
6016 /* check the VBT to see whether the eDP is on another port */
6017 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
6018 {
6019         /*
6020          * eDP not supported on g4x. so bail out early just
6021          * for a bit extra safety in case the VBT is bonkers.
6022          */
6023         if (INTEL_GEN(dev_priv) < 5)
6024                 return false;
6025
6026         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
6027                 return true;
6028
6029         return intel_bios_is_port_edp(dev_priv, port);
6030 }
6031
6032 static void
6033 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6034 {
6035         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6036         enum port port = dp_to_dig_port(intel_dp)->base.port;
6037
6038         if (!IS_G4X(dev_priv) && port != PORT_A)
6039                 intel_attach_force_audio_property(connector);
6040
6041         intel_attach_broadcast_rgb_property(connector);
6042         if (HAS_GMCH_DISPLAY(dev_priv))
6043                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6044         else if (INTEL_GEN(dev_priv) >= 5)
6045                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6046
6047         if (intel_dp_is_edp(intel_dp)) {
6048                 u32 allowed_scalers;
6049
6050                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
6051                 if (!HAS_GMCH_DISPLAY(dev_priv))
6052                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
6053
6054                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
6055
6056                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
6057
6058         }
6059 }
6060
6061 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
6062 {
6063         intel_dp->panel_power_off_time = ktime_get_boottime();
6064         intel_dp->last_power_on = jiffies;
6065         intel_dp->last_backlight_off = jiffies;
6066 }
6067
6068 static void
6069 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
6070 {
6071         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6072         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
6073         struct pps_registers regs;
6074
6075         intel_pps_get_registers(intel_dp, &regs);
6076
6077         /* Workaround: Need to write PP_CONTROL with the unlock key as
6078          * the very first thing. */
6079         pp_ctl = ironlake_get_pp_control(intel_dp);
6080
6081         pp_on = I915_READ(regs.pp_on);
6082         pp_off = I915_READ(regs.pp_off);
6083         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
6084             !HAS_PCH_ICP(dev_priv)) {
6085                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6086                 pp_div = I915_READ(regs.pp_div);
6087         }
6088
6089         /* Pull timing values out of registers */
6090         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
6091                      PANEL_POWER_UP_DELAY_SHIFT;
6092
6093         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
6094                   PANEL_LIGHT_ON_DELAY_SHIFT;
6095
6096         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
6097                   PANEL_LIGHT_OFF_DELAY_SHIFT;
6098
6099         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
6100                    PANEL_POWER_DOWN_DELAY_SHIFT;
6101
6102         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
6103             HAS_PCH_ICP(dev_priv)) {
6104                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
6105                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
6106         } else {
6107                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
6108                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
6109         }
6110 }
6111
6112 static void
6113 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6114 {
6115         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6116                       state_name,
6117                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6118 }
6119
6120 static void
6121 intel_pps_verify_state(struct intel_dp *intel_dp)
6122 {
6123         struct edp_power_seq hw;
6124         struct edp_power_seq *sw = &intel_dp->pps_delays;
6125
6126         intel_pps_readout_hw_state(intel_dp, &hw);
6127
6128         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6129             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6130                 DRM_ERROR("PPS state mismatch\n");
6131                 intel_pps_dump_state("sw", sw);
6132                 intel_pps_dump_state("hw", &hw);
6133         }
6134 }
6135
6136 static void
6137 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6138 {
6139         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6140         struct edp_power_seq cur, vbt, spec,
6141                 *final = &intel_dp->pps_delays;
6142
6143         lockdep_assert_held(&dev_priv->pps_mutex);
6144
6145         /* already initialized? */
6146         if (final->t11_t12 != 0)
6147                 return;
6148
6149         intel_pps_readout_hw_state(intel_dp, &cur);
6150
6151         intel_pps_dump_state("cur", &cur);
6152
6153         vbt = dev_priv->vbt.edp.pps;
6154         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6155          * of 500ms appears to be too short. Ocassionally the panel
6156          * just fails to power back on. Increasing the delay to 800ms
6157          * seems sufficient to avoid this problem.
6158          */
6159         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6160                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6161                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6162                               vbt.t11_t12);
6163         }
6164         /* T11_T12 delay is special and actually in units of 100ms, but zero
6165          * based in the hw (so we need to add 100 ms). But the sw vbt
6166          * table multiplies it with 1000 to make it in units of 100usec,
6167          * too. */
6168         vbt.t11_t12 += 100 * 10;
6169
6170         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6171          * our hw here, which are all in 100usec. */
6172         spec.t1_t3 = 210 * 10;
6173         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6174         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6175         spec.t10 = 500 * 10;
6176         /* This one is special and actually in units of 100ms, but zero
6177          * based in the hw (so we need to add 100 ms). But the sw vbt
6178          * table multiplies it with 1000 to make it in units of 100usec,
6179          * too. */
6180         spec.t11_t12 = (510 + 100) * 10;
6181
6182         intel_pps_dump_state("vbt", &vbt);
6183
6184         /* Use the max of the register settings and vbt. If both are
6185          * unset, fall back to the spec limits. */
6186 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
6187                                        spec.field : \
6188                                        max(cur.field, vbt.field))
6189         assign_final(t1_t3);
6190         assign_final(t8);
6191         assign_final(t9);
6192         assign_final(t10);
6193         assign_final(t11_t12);
6194 #undef assign_final
6195
6196 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
6197         intel_dp->panel_power_up_delay = get_delay(t1_t3);
6198         intel_dp->backlight_on_delay = get_delay(t8);
6199         intel_dp->backlight_off_delay = get_delay(t9);
6200         intel_dp->panel_power_down_delay = get_delay(t10);
6201         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6202 #undef get_delay
6203
6204         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6205                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
6206                       intel_dp->panel_power_cycle_delay);
6207
6208         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6209                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
6210
6211         /*
6212          * We override the HW backlight delays to 1 because we do manual waits
6213          * on them. For T8, even BSpec recommends doing it. For T9, if we
6214          * don't do this, we'll end up waiting for the backlight off delay
6215          * twice: once when we do the manual sleep, and once when we disable
6216          * the panel and wait for the PP_STATUS bit to become zero.
6217          */
6218         final->t8 = 1;
6219         final->t9 = 1;
6220
6221         /*
6222          * HW has only a 100msec granularity for t11_t12 so round it up
6223          * accordingly.
6224          */
6225         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6226 }
6227
6228 static void
6229 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6230                                               bool force_disable_vdd)
6231 {
6232         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6233         u32 pp_on, pp_off, pp_div, port_sel = 0;
6234         int div = dev_priv->rawclk_freq / 1000;
6235         struct pps_registers regs;
6236         enum port port = dp_to_dig_port(intel_dp)->base.port;
6237         const struct edp_power_seq *seq = &intel_dp->pps_delays;
6238
6239         lockdep_assert_held(&dev_priv->pps_mutex);
6240
6241         intel_pps_get_registers(intel_dp, &regs);
6242
6243         /*
6244          * On some VLV machines the BIOS can leave the VDD
6245          * enabled even on power sequencers which aren't
6246          * hooked up to any port. This would mess up the
6247          * power domain tracking the first time we pick
6248          * one of these power sequencers for use since
6249          * edp_panel_vdd_on() would notice that the VDD was
6250          * already on and therefore wouldn't grab the power
6251          * domain reference. Disable VDD first to avoid this.
6252          * This also avoids spuriously turning the VDD on as
6253          * soon as the new power sequencer gets initialized.
6254          */
6255         if (force_disable_vdd) {
6256                 u32 pp = ironlake_get_pp_control(intel_dp);
6257
6258                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
6259
6260                 if (pp & EDP_FORCE_VDD)
6261                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
6262
6263                 pp &= ~EDP_FORCE_VDD;
6264
6265                 I915_WRITE(regs.pp_ctrl, pp);
6266         }
6267
6268         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
6269                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
6270         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
6271                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
6272         /* Compute the divisor for the pp clock, simply match the Bspec
6273          * formula. */
6274         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
6275             HAS_PCH_ICP(dev_priv)) {
6276                 pp_div = I915_READ(regs.pp_ctrl);
6277                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
6278                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
6279                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
6280         } else {
6281                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
6282                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
6283                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
6284         }
6285
6286         /* Haswell doesn't have any port selection bits for the panel
6287          * power sequencer any more. */
6288         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6289                 port_sel = PANEL_PORT_SELECT_VLV(port);
6290         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6291                 switch (port) {
6292                 case PORT_A:
6293                         port_sel = PANEL_PORT_SELECT_DPA;
6294                         break;
6295                 case PORT_C:
6296                         port_sel = PANEL_PORT_SELECT_DPC;
6297                         break;
6298                 case PORT_D:
6299                         port_sel = PANEL_PORT_SELECT_DPD;
6300                         break;
6301                 default:
6302                         MISSING_CASE(port);
6303                         break;
6304                 }
6305         }
6306
6307         pp_on |= port_sel;
6308
6309         I915_WRITE(regs.pp_on, pp_on);
6310         I915_WRITE(regs.pp_off, pp_off);
6311         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
6312             HAS_PCH_ICP(dev_priv))
6313                 I915_WRITE(regs.pp_ctrl, pp_div);
6314         else
6315                 I915_WRITE(regs.pp_div, pp_div);
6316
6317         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6318                       I915_READ(regs.pp_on),
6319                       I915_READ(regs.pp_off),
6320                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)  ||
6321                        HAS_PCH_ICP(dev_priv)) ?
6322                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
6323                       I915_READ(regs.pp_div));
6324 }
6325
6326 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6327 {
6328         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6329
6330         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6331                 vlv_initial_power_sequencer_setup(intel_dp);
6332         } else {
6333                 intel_dp_init_panel_power_sequencer(intel_dp);
6334                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6335         }
6336 }
6337
6338 /**
6339  * intel_dp_set_drrs_state - program registers for RR switch to take effect
6340  * @dev_priv: i915 device
6341  * @crtc_state: a pointer to the active intel_crtc_state
6342  * @refresh_rate: RR to be programmed
6343  *
6344  * This function gets called when refresh rate (RR) has to be changed from
6345  * one frequency to another. Switches can be between high and low RR
6346  * supported by the panel or to any other RR based on media playback (in
6347  * this case, RR value needs to be passed from user space).
6348  *
6349  * The caller of this function needs to take a lock on dev_priv->drrs.
6350  */
6351 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6352                                     const struct intel_crtc_state *crtc_state,
6353                                     int refresh_rate)
6354 {
6355         struct intel_encoder *encoder;
6356         struct intel_digital_port *dig_port = NULL;
6357         struct intel_dp *intel_dp = dev_priv->drrs.dp;
6358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6359         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6360
6361         if (refresh_rate <= 0) {
6362                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6363                 return;
6364         }
6365
6366         if (intel_dp == NULL) {
6367                 DRM_DEBUG_KMS("DRRS not supported.\n");
6368                 return;
6369         }
6370
6371         dig_port = dp_to_dig_port(intel_dp);
6372         encoder = &dig_port->base;
6373
6374         if (!intel_crtc) {
6375                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6376                 return;
6377         }
6378
6379         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6380                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6381                 return;
6382         }
6383
6384         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6385                         refresh_rate)
6386                 index = DRRS_LOW_RR;
6387
6388         if (index == dev_priv->drrs.refresh_rate_type) {
6389                 DRM_DEBUG_KMS(
6390                         "DRRS requested for previously set RR...ignoring\n");
6391                 return;
6392         }
6393
6394         if (!crtc_state->base.active) {
6395                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6396                 return;
6397         }
6398
6399         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6400                 switch (index) {
6401                 case DRRS_HIGH_RR:
6402                         intel_dp_set_m_n(crtc_state, M1_N1);
6403                         break;
6404                 case DRRS_LOW_RR:
6405                         intel_dp_set_m_n(crtc_state, M2_N2);
6406                         break;
6407                 case DRRS_MAX_RR:
6408                 default:
6409                         DRM_ERROR("Unsupported refreshrate type\n");
6410                 }
6411         } else if (INTEL_GEN(dev_priv) > 6) {
6412                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6413                 u32 val;
6414
6415                 val = I915_READ(reg);
6416                 if (index > DRRS_HIGH_RR) {
6417                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6418                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6419                         else
6420                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6421                 } else {
6422                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6423                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6424                         else
6425                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6426                 }
6427                 I915_WRITE(reg, val);
6428         }
6429
6430         dev_priv->drrs.refresh_rate_type = index;
6431
6432         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6433 }
6434
6435 /**
6436  * intel_edp_drrs_enable - init drrs struct if supported
6437  * @intel_dp: DP struct
6438  * @crtc_state: A pointer to the active crtc state.
6439  *
6440  * Initializes frontbuffer_bits and drrs.dp
6441  */
6442 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6443                            const struct intel_crtc_state *crtc_state)
6444 {
6445         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6446
6447         if (!crtc_state->has_drrs) {
6448                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6449                 return;
6450         }
6451
6452         if (dev_priv->psr.enabled) {
6453                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6454                 return;
6455         }
6456
6457         mutex_lock(&dev_priv->drrs.mutex);
6458         if (dev_priv->drrs.dp) {
6459                 DRM_DEBUG_KMS("DRRS already enabled\n");
6460                 goto unlock;
6461         }
6462
6463         dev_priv->drrs.busy_frontbuffer_bits = 0;
6464
6465         dev_priv->drrs.dp = intel_dp;
6466
6467 unlock:
6468         mutex_unlock(&dev_priv->drrs.mutex);
6469 }
6470
6471 /**
6472  * intel_edp_drrs_disable - Disable DRRS
6473  * @intel_dp: DP struct
6474  * @old_crtc_state: Pointer to old crtc_state.
6475  *
6476  */
6477 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6478                             const struct intel_crtc_state *old_crtc_state)
6479 {
6480         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6481
6482         if (!old_crtc_state->has_drrs)
6483                 return;
6484
6485         mutex_lock(&dev_priv->drrs.mutex);
6486         if (!dev_priv->drrs.dp) {
6487                 mutex_unlock(&dev_priv->drrs.mutex);
6488                 return;
6489         }
6490
6491         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6492                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
6493                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
6494
6495         dev_priv->drrs.dp = NULL;
6496         mutex_unlock(&dev_priv->drrs.mutex);
6497
6498         cancel_delayed_work_sync(&dev_priv->drrs.work);
6499 }
6500
6501 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6502 {
6503         struct drm_i915_private *dev_priv =
6504                 container_of(work, typeof(*dev_priv), drrs.work.work);
6505         struct intel_dp *intel_dp;
6506
6507         mutex_lock(&dev_priv->drrs.mutex);
6508
6509         intel_dp = dev_priv->drrs.dp;
6510
6511         if (!intel_dp)
6512                 goto unlock;
6513
6514         /*
6515          * The delayed work can race with an invalidate hence we need to
6516          * recheck.
6517          */
6518
6519         if (dev_priv->drrs.busy_frontbuffer_bits)
6520                 goto unlock;
6521
6522         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6523                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6524
6525                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6526                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
6527         }
6528
6529 unlock:
6530         mutex_unlock(&dev_priv->drrs.mutex);
6531 }
6532
6533 /**
6534  * intel_edp_drrs_invalidate - Disable Idleness DRRS
6535  * @dev_priv: i915 device
6536  * @frontbuffer_bits: frontbuffer plane tracking bits
6537  *
6538  * This function gets called everytime rendering on the given planes start.
6539  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6540  *
6541  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6542  */
6543 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6544                                unsigned int frontbuffer_bits)
6545 {
6546         struct drm_crtc *crtc;
6547         enum pipe pipe;
6548
6549         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6550                 return;
6551
6552         cancel_delayed_work(&dev_priv->drrs.work);
6553
6554         mutex_lock(&dev_priv->drrs.mutex);
6555         if (!dev_priv->drrs.dp) {
6556                 mutex_unlock(&dev_priv->drrs.mutex);
6557                 return;
6558         }
6559
6560         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6561         pipe = to_intel_crtc(crtc)->pipe;
6562
6563         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6564         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6565
6566         /* invalidate means busy screen hence upclock */
6567         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6568                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6569                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6570
6571         mutex_unlock(&dev_priv->drrs.mutex);
6572 }
6573
6574 /**
6575  * intel_edp_drrs_flush - Restart Idleness DRRS
6576  * @dev_priv: i915 device
6577  * @frontbuffer_bits: frontbuffer plane tracking bits
6578  *
6579  * This function gets called every time rendering on the given planes has
6580  * completed or flip on a crtc is completed. So DRRS should be upclocked
6581  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6582  * if no other planes are dirty.
6583  *
6584  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6585  */
6586 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6587                           unsigned int frontbuffer_bits)
6588 {
6589         struct drm_crtc *crtc;
6590         enum pipe pipe;
6591
6592         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6593                 return;
6594
6595         cancel_delayed_work(&dev_priv->drrs.work);
6596
6597         mutex_lock(&dev_priv->drrs.mutex);
6598         if (!dev_priv->drrs.dp) {
6599                 mutex_unlock(&dev_priv->drrs.mutex);
6600                 return;
6601         }
6602
6603         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6604         pipe = to_intel_crtc(crtc)->pipe;
6605
6606         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6607         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6608
6609         /* flush means busy screen hence upclock */
6610         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6611                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6612                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6613
6614         /*
6615          * flush also means no more activity hence schedule downclock, if all
6616          * other fbs are quiescent too
6617          */
6618         if (!dev_priv->drrs.busy_frontbuffer_bits)
6619                 schedule_delayed_work(&dev_priv->drrs.work,
6620                                 msecs_to_jiffies(1000));
6621         mutex_unlock(&dev_priv->drrs.mutex);
6622 }
6623
6624 /**
6625  * DOC: Display Refresh Rate Switching (DRRS)
6626  *
6627  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6628  * which enables swtching between low and high refresh rates,
6629  * dynamically, based on the usage scenario. This feature is applicable
6630  * for internal panels.
6631  *
6632  * Indication that the panel supports DRRS is given by the panel EDID, which
6633  * would list multiple refresh rates for one resolution.
6634  *
6635  * DRRS is of 2 types - static and seamless.
6636  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6637  * (may appear as a blink on screen) and is used in dock-undock scenario.
6638  * Seamless DRRS involves changing RR without any visual effect to the user
6639  * and can be used during normal system usage. This is done by programming
6640  * certain registers.
6641  *
6642  * Support for static/seamless DRRS may be indicated in the VBT based on
6643  * inputs from the panel spec.
6644  *
6645  * DRRS saves power by switching to low RR based on usage scenarios.
6646  *
6647  * The implementation is based on frontbuffer tracking implementation.  When
6648  * there is a disturbance on the screen triggered by user activity or a periodic
6649  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6650  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6651  * made.
6652  *
6653  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6654  * and intel_edp_drrs_flush() are called.
6655  *
6656  * DRRS can be further extended to support other internal panels and also
6657  * the scenario of video playback wherein RR is set based on the rate
6658  * requested by userspace.
6659  */
6660
6661 /**
6662  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6663  * @connector: eDP connector
6664  * @fixed_mode: preferred mode of panel
6665  *
6666  * This function is  called only once at driver load to initialize basic
6667  * DRRS stuff.
6668  *
6669  * Returns:
6670  * Downclock mode if panel supports it, else return NULL.
6671  * DRRS support is determined by the presence of downclock mode (apart
6672  * from VBT setting).
6673  */
6674 static struct drm_display_mode *
6675 intel_dp_drrs_init(struct intel_connector *connector,
6676                    struct drm_display_mode *fixed_mode)
6677 {
6678         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6679         struct drm_display_mode *downclock_mode = NULL;
6680
6681         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6682         mutex_init(&dev_priv->drrs.mutex);
6683
6684         if (INTEL_GEN(dev_priv) <= 6) {
6685                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6686                 return NULL;
6687         }
6688
6689         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6690                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6691                 return NULL;
6692         }
6693
6694         downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
6695                                                     &connector->base);
6696
6697         if (!downclock_mode) {
6698                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6699                 return NULL;
6700         }
6701
6702         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6703
6704         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6705         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6706         return downclock_mode;
6707 }
6708
6709 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6710                                      struct intel_connector *intel_connector)
6711 {
6712         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6713         struct drm_device *dev = &dev_priv->drm;
6714         struct drm_connector *connector = &intel_connector->base;
6715         struct drm_display_mode *fixed_mode = NULL;
6716         struct drm_display_mode *downclock_mode = NULL;
6717         bool has_dpcd;
6718         struct drm_display_mode *scan;
6719         enum pipe pipe = INVALID_PIPE;
6720         intel_wakeref_t wakeref;
6721         struct edid *edid;
6722
6723         if (!intel_dp_is_edp(intel_dp))
6724                 return true;
6725
6726         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
6727
6728         /*
6729          * On IBX/CPT we may get here with LVDS already registered. Since the
6730          * driver uses the only internal power sequencer available for both
6731          * eDP and LVDS bail out early in this case to prevent interfering
6732          * with an already powered-on LVDS power sequencer.
6733          */
6734         if (intel_get_lvds_encoder(&dev_priv->drm)) {
6735                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6736                 DRM_INFO("LVDS was detected, not registering eDP\n");
6737
6738                 return false;
6739         }
6740
6741         with_pps_lock(intel_dp, wakeref) {
6742                 intel_dp_init_panel_power_timestamps(intel_dp);
6743                 intel_dp_pps_init(intel_dp);
6744                 intel_edp_panel_vdd_sanitize(intel_dp);
6745         }
6746
6747         /* Cache DPCD and EDID for edp. */
6748         has_dpcd = intel_edp_init_dpcd(intel_dp);
6749
6750         if (!has_dpcd) {
6751                 /* if this fails, presume the device is a ghost */
6752                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6753                 goto out_vdd_off;
6754         }
6755
6756         mutex_lock(&dev->mode_config.mutex);
6757         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6758         if (edid) {
6759                 if (drm_add_edid_modes(connector, edid)) {
6760                         drm_connector_update_edid_property(connector,
6761                                                                 edid);
6762                 } else {
6763                         kfree(edid);
6764                         edid = ERR_PTR(-EINVAL);
6765                 }
6766         } else {
6767                 edid = ERR_PTR(-ENOENT);
6768         }
6769         intel_connector->edid = edid;
6770
6771         /* prefer fixed mode from EDID if available */
6772         list_for_each_entry(scan, &connector->probed_modes, head) {
6773                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
6774                         fixed_mode = drm_mode_duplicate(dev, scan);
6775                         downclock_mode = intel_dp_drrs_init(
6776                                                 intel_connector, fixed_mode);
6777                         break;
6778                 }
6779         }
6780
6781         /* fallback to VBT if available for eDP */
6782         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
6783                 fixed_mode = drm_mode_duplicate(dev,
6784                                         dev_priv->vbt.lfp_lvds_vbt_mode);
6785                 if (fixed_mode) {
6786                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
6787                         connector->display_info.width_mm = fixed_mode->width_mm;
6788                         connector->display_info.height_mm = fixed_mode->height_mm;
6789                 }
6790         }
6791         mutex_unlock(&dev->mode_config.mutex);
6792
6793         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6794                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
6795                 register_reboot_notifier(&intel_dp->edp_notifier);
6796
6797                 /*
6798                  * Figure out the current pipe for the initial backlight setup.
6799                  * If the current pipe isn't valid, try the PPS pipe, and if that
6800                  * fails just assume pipe A.
6801                  */
6802                 pipe = vlv_active_pipe(intel_dp);
6803
6804                 if (pipe != PIPE_A && pipe != PIPE_B)
6805                         pipe = intel_dp->pps_pipe;
6806
6807                 if (pipe != PIPE_A && pipe != PIPE_B)
6808                         pipe = PIPE_A;
6809
6810                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6811                               pipe_name(pipe));
6812         }
6813
6814         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6815         intel_connector->panel.backlight.power = intel_edp_backlight_power;
6816         intel_panel_setup_backlight(connector, pipe);
6817
6818         if (fixed_mode)
6819                 drm_connector_init_panel_orientation_property(
6820                         connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
6821
6822         return true;
6823
6824 out_vdd_off:
6825         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6826         /*
6827          * vdd might still be enabled do to the delayed vdd off.
6828          * Make sure vdd is actually turned off here.
6829          */
6830         with_pps_lock(intel_dp, wakeref)
6831                 edp_panel_vdd_off_sync(intel_dp);
6832
6833         return false;
6834 }
6835
6836 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6837 {
6838         struct intel_connector *intel_connector;
6839         struct drm_connector *connector;
6840
6841         intel_connector = container_of(work, typeof(*intel_connector),
6842                                        modeset_retry_work);
6843         connector = &intel_connector->base;
6844         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6845                       connector->name);
6846
6847         /* Grab the locks before changing connector property*/
6848         mutex_lock(&connector->dev->mode_config.mutex);
6849         /* Set connector link status to BAD and send a Uevent to notify
6850          * userspace to do a modeset.
6851          */
6852         drm_connector_set_link_status_property(connector,
6853                                                DRM_MODE_LINK_STATUS_BAD);
6854         mutex_unlock(&connector->dev->mode_config.mutex);
6855         /* Send Hotplug uevent so userspace can reprobe */
6856         drm_kms_helper_hotplug_event(connector->dev);
6857 }
6858
6859 bool
6860 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6861                         struct intel_connector *intel_connector)
6862 {
6863         struct drm_connector *connector = &intel_connector->base;
6864         struct intel_dp *intel_dp = &intel_dig_port->dp;
6865         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6866         struct drm_device *dev = intel_encoder->base.dev;
6867         struct drm_i915_private *dev_priv = to_i915(dev);
6868         enum port port = intel_encoder->port;
6869         int type;
6870
6871         /* Initialize the work for modeset in case of link train failure */
6872         INIT_WORK(&intel_connector->modeset_retry_work,
6873                   intel_dp_modeset_retry_work_fn);
6874
6875         if (WARN(intel_dig_port->max_lanes < 1,
6876                  "Not enough lanes (%d) for DP on port %c\n",
6877                  intel_dig_port->max_lanes, port_name(port)))
6878                 return false;
6879
6880         intel_dp_set_source_rates(intel_dp);
6881
6882         intel_dp->reset_link_params = true;
6883         intel_dp->pps_pipe = INVALID_PIPE;
6884         intel_dp->active_pipe = INVALID_PIPE;
6885
6886         /* intel_dp vfuncs */
6887         if (HAS_DDI(dev_priv))
6888                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6889
6890         /* Preserve the current hw state. */
6891         intel_dp->DP = I915_READ(intel_dp->output_reg);
6892         intel_dp->attached_connector = intel_connector;
6893
6894         if (intel_dp_is_port_edp(dev_priv, port))
6895                 type = DRM_MODE_CONNECTOR_eDP;
6896         else
6897                 type = DRM_MODE_CONNECTOR_DisplayPort;
6898
6899         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6900                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6901
6902         /*
6903          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6904          * for DP the encoder type can be set by the caller to
6905          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6906          */
6907         if (type == DRM_MODE_CONNECTOR_eDP)
6908                 intel_encoder->type = INTEL_OUTPUT_EDP;
6909
6910         /* eDP only on port B and/or C on vlv/chv */
6911         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6912                     intel_dp_is_edp(intel_dp) &&
6913                     port != PORT_B && port != PORT_C))
6914                 return false;
6915
6916         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6917                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6918                         port_name(port));
6919
6920         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6921         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6922
6923         if (!HAS_GMCH_DISPLAY(dev_priv))
6924                 connector->interlace_allowed = true;
6925         connector->doublescan_allowed = 0;
6926
6927         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
6928
6929         intel_dp_aux_init(intel_dp);
6930
6931         intel_connector_attach_encoder(intel_connector, intel_encoder);
6932
6933         if (HAS_DDI(dev_priv))
6934                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6935         else
6936                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6937
6938         /* init MST on ports that can support it */
6939         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6940             (port == PORT_B || port == PORT_C ||
6941              port == PORT_D || port == PORT_F))
6942                 intel_dp_mst_encoder_init(intel_dig_port,
6943                                           intel_connector->base.base.id);
6944
6945         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6946                 intel_dp_aux_fini(intel_dp);
6947                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6948                 goto fail;
6949         }
6950
6951         intel_dp_add_properties(intel_dp, connector);
6952
6953         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6954                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
6955                 if (ret)
6956                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6957         }
6958
6959         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6960          * 0xd.  Failure to do so will result in spurious interrupts being
6961          * generated on the port when a cable is not attached.
6962          */
6963         if (IS_G45(dev_priv)) {
6964                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6965                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6966         }
6967
6968         return true;
6969
6970 fail:
6971         drm_connector_cleanup(connector);
6972
6973         return false;
6974 }
6975
6976 bool intel_dp_init(struct drm_i915_private *dev_priv,
6977                    i915_reg_t output_reg,
6978                    enum port port)
6979 {
6980         struct intel_digital_port *intel_dig_port;
6981         struct intel_encoder *intel_encoder;
6982         struct drm_encoder *encoder;
6983         struct intel_connector *intel_connector;
6984
6985         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6986         if (!intel_dig_port)
6987                 return false;
6988
6989         intel_connector = intel_connector_alloc();
6990         if (!intel_connector)
6991                 goto err_connector_alloc;
6992
6993         intel_encoder = &intel_dig_port->base;
6994         encoder = &intel_encoder->base;
6995
6996         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6997                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6998                              "DP %c", port_name(port)))
6999                 goto err_encoder_init;
7000
7001         intel_encoder->hotplug = intel_dp_hotplug;
7002         intel_encoder->compute_config = intel_dp_compute_config;
7003         intel_encoder->get_hw_state = intel_dp_get_hw_state;
7004         intel_encoder->get_config = intel_dp_get_config;
7005         intel_encoder->suspend = intel_dp_encoder_suspend;
7006         if (IS_CHERRYVIEW(dev_priv)) {
7007                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
7008                 intel_encoder->pre_enable = chv_pre_enable_dp;
7009                 intel_encoder->enable = vlv_enable_dp;
7010                 intel_encoder->disable = vlv_disable_dp;
7011                 intel_encoder->post_disable = chv_post_disable_dp;
7012                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
7013         } else if (IS_VALLEYVIEW(dev_priv)) {
7014                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
7015                 intel_encoder->pre_enable = vlv_pre_enable_dp;
7016                 intel_encoder->enable = vlv_enable_dp;
7017                 intel_encoder->disable = vlv_disable_dp;
7018                 intel_encoder->post_disable = vlv_post_disable_dp;
7019         } else {
7020                 intel_encoder->pre_enable = g4x_pre_enable_dp;
7021                 intel_encoder->enable = g4x_enable_dp;
7022                 intel_encoder->disable = g4x_disable_dp;
7023                 intel_encoder->post_disable = g4x_post_disable_dp;
7024         }
7025
7026         intel_dig_port->dp.output_reg = output_reg;
7027         intel_dig_port->max_lanes = 4;
7028
7029         intel_encoder->type = INTEL_OUTPUT_DP;
7030         intel_encoder->power_domain = intel_port_to_power_domain(port);
7031         if (IS_CHERRYVIEW(dev_priv)) {
7032                 if (port == PORT_D)
7033                         intel_encoder->crtc_mask = 1 << 2;
7034                 else
7035                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
7036         } else {
7037                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
7038         }
7039         intel_encoder->cloneable = 0;
7040         intel_encoder->port = port;
7041
7042         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
7043
7044         if (port != PORT_A)
7045                 intel_infoframe_init(intel_dig_port);
7046
7047         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
7048         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
7049                 goto err_init_connector;
7050
7051         return true;
7052
7053 err_init_connector:
7054         drm_encoder_cleanup(encoder);
7055 err_encoder_init:
7056         kfree(intel_connector);
7057 err_connector_alloc:
7058         kfree(intel_dig_port);
7059         return false;
7060 }
7061
7062 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
7063 {
7064         struct intel_encoder *encoder;
7065
7066         for_each_intel_encoder(&dev_priv->drm, encoder) {
7067                 struct intel_dp *intel_dp;
7068
7069                 if (encoder->type != INTEL_OUTPUT_DDI)
7070                         continue;
7071
7072                 intel_dp = enc_to_intel_dp(&encoder->base);
7073
7074                 if (!intel_dp->can_mst)
7075                         continue;
7076
7077                 if (intel_dp->is_mst)
7078                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
7079         }
7080 }
7081
7082 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
7083 {
7084         struct intel_encoder *encoder;
7085
7086         for_each_intel_encoder(&dev_priv->drm, encoder) {
7087                 struct intel_dp *intel_dp;
7088                 int ret;
7089
7090                 if (encoder->type != INTEL_OUTPUT_DDI)
7091                         continue;
7092
7093                 intel_dp = enc_to_intel_dp(&encoder->base);
7094
7095                 if (!intel_dp->can_mst)
7096                         continue;
7097
7098                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
7099                 if (ret)
7100                         intel_dp_check_mst_status(intel_dp);
7101         }
7102 }