drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drm_atomic_helper.h>
  36 #include <drm/drm_crtc.h>
  37 #include <drm/drm_dp_helper.h>
  38 #include <drm/drm_edid.h>
  39 #include <drm/drm_hdcp.h>
  40 #include <drm/drm_probe_helper.h>
  41 #include "intel_drv.h"
  42 #include <drm/i915_drm.h>
  43 #include "i915_drv.h"
  44
  45 #define DP_DPRX_ESI_LEN 14
  46
  47 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
  48 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER      61440
  49 #define DP_DSC_MIN_SUPPORTED_BPC                8
  50 #define DP_DSC_MAX_SUPPORTED_BPC                10
  51
  52 /* DP DSC throughput values used for slice count calculations KPixels/s */
  53 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  54 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  55 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  56
  57 /* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
  58 #define DP_DSC_FEC_OVERHEAD_FACTOR              976
  59
  60 /* Compliance test status bits  */
  61 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  62 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  63 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  64 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  65
  66 struct dp_link_dpll {
  67         int clock;
  68         struct dpll dpll;
  69 };
  70
  71 static const struct dp_link_dpll g4x_dpll[] = {
  72         { 162000,
  73                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  74         { 270000,
  75                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  76 };
  77
  78 static const struct dp_link_dpll pch_dpll[] = {
  79         { 162000,
  80                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  81         { 270000,
  82                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  83 };
  84
  85 static const struct dp_link_dpll vlv_dpll[] = {
  86         { 162000,
  87                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  88         { 270000,
  89                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  90 };
  91
  92 /*
  93  * CHV supports eDP 1.4 that have  more link rates.
  94  * Below only provides the fixed rate but exclude variable rate.
  95  */
  96 static const struct dp_link_dpll chv_dpll[] = {
  97         /*
  98          * CHV requires to program fractional division for m2.
  99          * m2 is stored in fixed point format using formula below
 100          * (m2_int << 22) | m2_fraction
 101          */
 102         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 103                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 104         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 105                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 106 };
 107
 108 /* Constants for DP DSC configurations */
 109 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 110
 111 /* With Single pipe configuration, HW is capable of supporting maximum
 112  * of 4 slices per line.
 113  */
 114 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 115
 116 /**
 117  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 118  * @intel_dp: DP struct
 119  *
 120  * If a CPU or PCH DP output is attached to an eDP panel, this function
 121  * will return true, and false otherwise.
 122  */
 123 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 124 {
 125         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 126
 127         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 128 }
 129
 130 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 131 {
 132         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 133 }
 134
 135 static void intel_dp_link_down(struct intel_encoder *encoder,
 136                                const struct intel_crtc_state *old_crtc_state);
 137 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 138 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 139 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 140                                            const struct intel_crtc_state *crtc_state);
 141 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 142                                       enum pipe pipe);
 143 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 144
 145 /* update sink rates from dpcd */
 146 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 147 {
 148         static const int dp_rates[] = {
 149                 162000, 270000, 540000, 810000
 150         };
 151         int i, max_rate;
 152
 153         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 154
 155         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 156                 if (dp_rates[i] > max_rate)
 157                         break;
 158                 intel_dp->sink_rates[i] = dp_rates[i];
 159         }
 160
 161         intel_dp->num_sink_rates = i;
 162 }
 163
 164 /* Get length of rates array potentially limited by max_rate. */
 165 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 166 {
 167         int i;
 168
 169         /* Limit results by potentially reduced max rate */
 170         for (i = 0; i < len; i++) {
 171                 if (rates[len - i - 1] <= max_rate)
 172                         return len - i;
 173         }
 174
 175         return 0;
 176 }
 177
 178 /* Get length of common rates array potentially limited by max_rate. */
 179 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 180                                           int max_rate)
 181 {
 182         return intel_dp_rate_limit_len(intel_dp->common_rates,
 183                                        intel_dp->num_common_rates, max_rate);
 184 }
 185
 186 /* Theoretical max between source and sink */
 187 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 188 {
 189         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 190 }
 191
 192 static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
 193 {
 194         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 195         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 196         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
 197         u32 lane_info;
 198
 199         if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
 200                 return 4;
 201
 202         lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
 203                      DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
 204                     DP_LANE_ASSIGNMENT_SHIFT(tc_port);
 205
 206         switch (lane_info) {
 207         default:
 208                 MISSING_CASE(lane_info);
 209         case 1:
 210         case 2:
 211         case 4:
 212         case 8:
 213                 return 1;
 214         case 3:
 215         case 12:
 216                 return 2;
 217         case 15:
 218                 return 4;
 219         }
 220 }
 221
 222 /* Theoretical max between source and sink */
 223 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 224 {
 225         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 226         int source_max = intel_dig_port->max_lanes;
 227         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 228         int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
 229
 230         return min3(source_max, sink_max, fia_max);
 231 }
 232
 233 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 234 {
 235         return intel_dp->max_link_lane_count;
 236 }
 237
 238 int
 239 intel_dp_link_required(int pixel_clock, int bpp)
 240 {
 241         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 242         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 243 }
 244
 245 int
 246 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 247 {
 248         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 249          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 250          * is transmitted every LS_Clk per lane, there is no need to account for
 251          * the channel encoding that is done in the PHY layer here.
 252          */
 253
 254         return max_link_clock * max_lanes;
 255 }
 256
 257 static int
 258 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 259 {
 260         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 261         struct intel_encoder *encoder = &intel_dig_port->base;
 262         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 263         int max_dotclk = dev_priv->max_dotclk_freq;
 264         int ds_max_dotclk;
 265
 266         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 267
 268         if (type != DP_DS_PORT_TYPE_VGA)
 269                 return max_dotclk;
 270
 271         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 272                                                     intel_dp->downstream_ports);
 273
 274         if (ds_max_dotclk != 0)
 275                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 276
 277         return max_dotclk;
 278 }
 279
 280 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 281 {
 282         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 283         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 284         enum port port = dig_port->base.port;
 285
 286         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 287
 288         /* Low voltage SKUs are limited to max of 5.4G */
 289         if (voltage == VOLTAGE_INFO_0_85V)
 290                 return 540000;
 291
 292         /* For this SKU 8.1G is supported in all ports */
 293         if (IS_CNL_WITH_PORT_F(dev_priv))
 294                 return 810000;
 295
 296         /* For other SKUs, max rate on ports A and D is 5.4G */
 297         if (port == PORT_A || port == PORT_D)
 298                 return 540000;
 299
 300         return 810000;
 301 }
 302
 303 static int icl_max_source_rate(struct intel_dp *intel_dp)
 304 {
 305         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 306         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 307         enum port port = dig_port->base.port;
 308
 309         if (intel_port_is_combophy(dev_priv, port) &&
 310             !intel_dp_is_edp(intel_dp))
 311                 return 540000;
 312
 313         return 810000;
 314 }
 315
 316 static void
 317 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 318 {
 319         /* The values must be in increasing order */
 320         static const int cnl_rates[] = {
 321                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 322         };
 323         static const int bxt_rates[] = {
 324                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 325         };
 326         static const int skl_rates[] = {
 327                 162000, 216000, 270000, 324000, 432000, 540000
 328         };
 329         static const int hsw_rates[] = {
 330                 162000, 270000, 540000
 331         };
 332         static const int g4x_rates[] = {
 333                 162000, 270000
 334         };
 335         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 336         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 337         const struct ddi_vbt_port_info *info =
 338                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 339         const int *source_rates;
 340         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 341
 342         /* This should only be done once */
 343         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 344
 345         if (INTEL_GEN(dev_priv) >= 10) {
 346                 source_rates = cnl_rates;
 347                 size = ARRAY_SIZE(cnl_rates);
 348                 if (IS_GEN(dev_priv, 10))
 349                         max_rate = cnl_max_source_rate(intel_dp);
 350                 else
 351                         max_rate = icl_max_source_rate(intel_dp);
 352         } else if (IS_GEN9_LP(dev_priv)) {
 353                 source_rates = bxt_rates;
 354                 size = ARRAY_SIZE(bxt_rates);
 355         } else if (IS_GEN9_BC(dev_priv)) {
 356                 source_rates = skl_rates;
 357                 size = ARRAY_SIZE(skl_rates);
 358         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 359                    IS_BROADWELL(dev_priv)) {
 360                 source_rates = hsw_rates;
 361                 size = ARRAY_SIZE(hsw_rates);
 362         } else {
 363                 source_rates = g4x_rates;
 364                 size = ARRAY_SIZE(g4x_rates);
 365         }
 366
 367         if (max_rate && vbt_max_rate)
 368                 max_rate = min(max_rate, vbt_max_rate);
 369         else if (vbt_max_rate)
 370                 max_rate = vbt_max_rate;
 371
 372         if (max_rate)
 373                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 374
 375         intel_dp->source_rates = source_rates;
 376         intel_dp->num_source_rates = size;
 377 }
 378
 379 static int intersect_rates(const int *source_rates, int source_len,
 380                            const int *sink_rates, int sink_len,
 381                            int *common_rates)
 382 {
 383         int i = 0, j = 0, k = 0;
 384
 385         while (i < source_len && j < sink_len) {
 386                 if (source_rates[i] == sink_rates[j]) {
 387                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 388                                 return k;
 389                         common_rates[k] = source_rates[i];
 390                         ++k;
 391                         ++i;
 392                         ++j;
 393                 } else if (source_rates[i] < sink_rates[j]) {
 394                         ++i;
 395                 } else {
 396                         ++j;
 397                 }
 398         }
 399         return k;
 400 }
 401
 402 /* return index of rate in rates array, or -1 if not found */
 403 static int intel_dp_rate_index(const int *rates, int len, int rate)
 404 {
 405         int i;
 406
 407         for (i = 0; i < len; i++)
 408                 if (rate == rates[i])
 409                         return i;
 410
 411         return -1;
 412 }
 413
 414 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 415 {
 416         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 417
 418         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 419                                                      intel_dp->num_source_rates,
 420                                                      intel_dp->sink_rates,
 421                                                      intel_dp->num_sink_rates,
 422                                                      intel_dp->common_rates);
 423
 424         /* Paranoia, there should always be something in common. */
 425         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 426                 intel_dp->common_rates[0] = 162000;
 427                 intel_dp->num_common_rates = 1;
 428         }
 429 }
 430
 431 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 432                                        u8 lane_count)
 433 {
 434         /*
 435          * FIXME: we need to synchronize the current link parameters with
 436          * hardware readout. Currently fast link training doesn't work on
 437          * boot-up.
 438          */
 439         if (link_rate == 0 ||
 440             link_rate > intel_dp->max_link_rate)
 441                 return false;
 442
 443         if (lane_count == 0 ||
 444             lane_count > intel_dp_max_lane_count(intel_dp))
 445                 return false;
 446
 447         return true;
 448 }
 449
 450 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 451                                                      int link_rate,
 452                                                      u8 lane_count)
 453 {
 454         const struct drm_display_mode *fixed_mode =
 455                 intel_dp->attached_connector->panel.fixed_mode;
 456         int mode_rate, max_rate;
 457
 458         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 459         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 460         if (mode_rate > max_rate)
 461                 return false;
 462
 463         return true;
 464 }
 465
 466 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 467                                             int link_rate, u8 lane_count)
 468 {
 469         int index;
 470
 471         index = intel_dp_rate_index(intel_dp->common_rates,
 472                                     intel_dp->num_common_rates,
 473                                     link_rate);
 474         if (index > 0) {
 475                 if (intel_dp_is_edp(intel_dp) &&
 476                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 477                                                               intel_dp->common_rates[index - 1],
 478                                                               lane_count)) {
 479                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 480                         return 0;
 481                 }
 482                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 483                 intel_dp->max_link_lane_count = lane_count;
 484         } else if (lane_count > 1) {
 485                 if (intel_dp_is_edp(intel_dp) &&
 486                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 487                                                               intel_dp_max_common_rate(intel_dp),
 488                                                               lane_count >> 1)) {
 489                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 490                         return 0;
 491                 }
 492                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 493                 intel_dp->max_link_lane_count = lane_count >> 1;
 494         } else {
 495                 DRM_ERROR("Link Training Unsuccessful\n");
 496                 return -1;
 497         }
 498
 499         return 0;
 500 }
 501
 502 static enum drm_mode_status
 503 intel_dp_mode_valid(struct drm_connector *connector,
 504                     struct drm_display_mode *mode)
 505 {
 506         struct intel_dp *intel_dp = intel_attached_dp(connector);
 507         struct intel_connector *intel_connector = to_intel_connector(connector);
 508         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 509         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 510         int target_clock = mode->clock;
 511         int max_rate, mode_rate, max_lanes, max_link_clock;
 512         int max_dotclk;
 513         u16 dsc_max_output_bpp = 0;
 514         u8 dsc_slice_count = 0;
 515
 516         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 517                 return MODE_NO_DBLESCAN;
 518
 519         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 520
 521         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 522                 if (mode->hdisplay > fixed_mode->hdisplay)
 523                         return MODE_PANEL;
 524
 525                 if (mode->vdisplay > fixed_mode->vdisplay)
 526                         return MODE_PANEL;
 527
 528                 target_clock = fixed_mode->clock;
 529         }
 530
 531         max_link_clock = intel_dp_max_link_rate(intel_dp);
 532         max_lanes = intel_dp_max_lane_count(intel_dp);
 533
 534         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 535         mode_rate = intel_dp_link_required(target_clock, 18);
 536
 537         /*
 538          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 539          * integer value since we support only integer values of bpp.
 540          */
 541         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 542             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 543                 if (intel_dp_is_edp(intel_dp)) {
 544                         dsc_max_output_bpp =
 545                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 546                         dsc_slice_count =
 547                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 548                                                                 true);
 549                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 550                         dsc_max_output_bpp =
 551                                 intel_dp_dsc_get_output_bpp(max_link_clock,
 552                                                             max_lanes,
 553                                                             target_clock,
 554                                                             mode->hdisplay) >> 4;
 555                         dsc_slice_count =
 556                                 intel_dp_dsc_get_slice_count(intel_dp,
 557                                                              target_clock,
 558                                                              mode->hdisplay);
 559                 }
 560         }
 561
 562         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
 563             target_clock > max_dotclk)
 564                 return MODE_CLOCK_HIGH;
 565
 566         if (mode->clock < 10000)
 567                 return MODE_CLOCK_LOW;
 568
 569         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 570                 return MODE_H_ILLEGAL;
 571
 572         return MODE_OK;
 573 }
 574
 575 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 576 {
 577         int i;
 578         u32 v = 0;
 579
 580         if (src_bytes > 4)
 581                 src_bytes = 4;
 582         for (i = 0; i < src_bytes; i++)
 583                 v |= ((u32)src[i]) << ((3 - i) * 8);
 584         return v;
 585 }
 586
 587 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 588 {
 589         int i;
 590         if (dst_bytes > 4)
 591                 dst_bytes = 4;
 592         for (i = 0; i < dst_bytes; i++)
 593                 dst[i] = src >> ((3-i) * 8);
 594 }
 595
 596 static void
 597 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 598 static void
 599 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 600                                               bool force_disable_vdd);
 601 static void
 602 intel_dp_pps_init(struct intel_dp *intel_dp);
 603
 604 static intel_wakeref_t
 605 pps_lock(struct intel_dp *intel_dp)
 606 {
 607         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 608         intel_wakeref_t wakeref;
 609
 610         /*
 611          * See intel_power_sequencer_reset() why we need
 612          * a power domain reference here.
 613          */
 614         wakeref = intel_display_power_get(dev_priv,
 615                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 616
 617         mutex_lock(&dev_priv->pps_mutex);
 618
 619         return wakeref;
 620 }
 621
 622 static intel_wakeref_t
 623 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 624 {
 625         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 626
 627         mutex_unlock(&dev_priv->pps_mutex);
 628         intel_display_power_put(dev_priv,
 629                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 630                                 wakeref);
 631         return 0;
 632 }
 633
 634 #define with_pps_lock(dp, wf) \
 635         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 636
 637 static void
 638 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 639 {
 640         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 641         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 642         enum pipe pipe = intel_dp->pps_pipe;
 643         bool pll_enabled, release_cl_override = false;
 644         enum dpio_phy phy = DPIO_PHY(pipe);
 645         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 646         u32 DP;
 647
 648         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 649                  "skipping pipe %c power sequencer kick due to port %c being active\n",
 650                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 651                 return;
 652
 653         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 654                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 655
 656         /* Preserve the BIOS-computed detected bit. This is
 657          * supposed to be read-only.
 658          */
 659         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 660         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 661         DP |= DP_PORT_WIDTH(1);
 662         DP |= DP_LINK_TRAIN_PAT_1;
 663
 664         if (IS_CHERRYVIEW(dev_priv))
 665                 DP |= DP_PIPE_SEL_CHV(pipe);
 666         else
 667                 DP |= DP_PIPE_SEL(pipe);
 668
 669         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 670
 671         /*
 672          * The DPLL for the pipe must be enabled for this to work.
 673          * So enable temporarily it if it's not already enabled.
 674          */
 675         if (!pll_enabled) {
 676                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 677                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 678
 679                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 680                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 681                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 682                                   pipe_name(pipe));
 683                         return;
 684                 }
 685         }
 686
 687         /*
 688          * Similar magic as in intel_dp_enable_port().
 689          * We _must_ do this port enable + disable trick
 690          * to make this power sequencer lock onto the port.
 691          * Otherwise even VDD force bit won't work.
 692          */
 693         I915_WRITE(intel_dp->output_reg, DP);
 694         POSTING_READ(intel_dp->output_reg);
 695
 696         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 697         POSTING_READ(intel_dp->output_reg);
 698
 699         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 700         POSTING_READ(intel_dp->output_reg);
 701
 702         if (!pll_enabled) {
 703                 vlv_force_pll_off(dev_priv, pipe);
 704
 705                 if (release_cl_override)
 706                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 707         }
 708 }
 709
 710 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 711 {
 712         struct intel_encoder *encoder;
 713         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 714
 715         /*
 716          * We don't have power sequencer currently.
 717          * Pick one that's not used by other ports.
 718          */
 719         for_each_intel_dp(&dev_priv->drm, encoder) {
 720                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 721
 722                 if (encoder->type == INTEL_OUTPUT_EDP) {
 723                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 724                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 725
 726                         if (intel_dp->pps_pipe != INVALID_PIPE)
 727                                 pipes &= ~(1 << intel_dp->pps_pipe);
 728                 } else {
 729                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 730
 731                         if (intel_dp->active_pipe != INVALID_PIPE)
 732                                 pipes &= ~(1 << intel_dp->active_pipe);
 733                 }
 734         }
 735
 736         if (pipes == 0)
 737                 return INVALID_PIPE;
 738
 739         return ffs(pipes) - 1;
 740 }
 741
 742 static enum pipe
 743 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 744 {
 745         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 746         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 747         enum pipe pipe;
 748
 749         lockdep_assert_held(&dev_priv->pps_mutex);
 750
 751         /* We should never land here with regular DP ports */
 752         WARN_ON(!intel_dp_is_edp(intel_dp));
 753
 754         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 755                 intel_dp->active_pipe != intel_dp->pps_pipe);
 756
 757         if (intel_dp->pps_pipe != INVALID_PIPE)
 758                 return intel_dp->pps_pipe;
 759
 760         pipe = vlv_find_free_pps(dev_priv);
 761
 762         /*
 763          * Didn't find one. This should not happen since there
 764          * are two power sequencers and up to two eDP ports.
 765          */
 766         if (WARN_ON(pipe == INVALID_PIPE))
 767                 pipe = PIPE_A;
 768
 769         vlv_steal_power_sequencer(dev_priv, pipe);
 770         intel_dp->pps_pipe = pipe;
 771
 772         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 773                       pipe_name(intel_dp->pps_pipe),
 774                       port_name(intel_dig_port->base.port));
 775
 776         /* init power sequencer on this pipe and port */
 777         intel_dp_init_panel_power_sequencer(intel_dp);
 778         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 779
 780         /*
 781          * Even vdd force doesn't work until we've made
 782          * the power sequencer lock in on the port.
 783          */
 784         vlv_power_sequencer_kick(intel_dp);
 785
 786         return intel_dp->pps_pipe;
 787 }
 788
 789 static int
 790 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 791 {
 792         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 793         int backlight_controller = dev_priv->vbt.backlight.controller;
 794
 795         lockdep_assert_held(&dev_priv->pps_mutex);
 796
 797         /* We should never land here with regular DP ports */
 798         WARN_ON(!intel_dp_is_edp(intel_dp));
 799
 800         if (!intel_dp->pps_reset)
 801                 return backlight_controller;
 802
 803         intel_dp->pps_reset = false;
 804
 805         /*
 806          * Only the HW needs to be reprogrammed, the SW state is fixed and
 807          * has been setup during connector init.
 808          */
 809         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 810
 811         return backlight_controller;
 812 }
 813
 814 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 815                                enum pipe pipe);
 816
 817 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 818                                enum pipe pipe)
 819 {
 820         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 821 }
 822
 823 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 824                                 enum pipe pipe)
 825 {
 826         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 827 }
 828
 829 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 830                          enum pipe pipe)
 831 {
 832         return true;
 833 }
 834
 835 static enum pipe
 836 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 837                      enum port port,
 838                      vlv_pipe_check pipe_check)
 839 {
 840         enum pipe pipe;
 841
 842         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 843                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 844                         PANEL_PORT_SELECT_MASK;
 845
 846                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 847                         continue;
 848
 849                 if (!pipe_check(dev_priv, pipe))
 850                         continue;
 851
 852                 return pipe;
 853         }
 854
 855         return INVALID_PIPE;
 856 }
 857
 858 static void
 859 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 860 {
 861         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 862         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 863         enum port port = intel_dig_port->base.port;
 864
 865         lockdep_assert_held(&dev_priv->pps_mutex);
 866
 867         /* try to find a pipe with this port selected */
 868         /* first pick one where the panel is on */
 869         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 870                                                   vlv_pipe_has_pp_on);
 871         /* didn't find one? pick one where vdd is on */
 872         if (intel_dp->pps_pipe == INVALID_PIPE)
 873                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 874                                                           vlv_pipe_has_vdd_on);
 875         /* didn't find one? pick one with just the correct port */
 876         if (intel_dp->pps_pipe == INVALID_PIPE)
 877                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 878                                                           vlv_pipe_any);
 879
 880         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 881         if (intel_dp->pps_pipe == INVALID_PIPE) {
 882                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 883                               port_name(port));
 884                 return;
 885         }
 886
 887         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 888                       port_name(port), pipe_name(intel_dp->pps_pipe));
 889
 890         intel_dp_init_panel_power_sequencer(intel_dp);
 891         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 892 }
 893
 894 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 895 {
 896         struct intel_encoder *encoder;
 897
 898         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 899                     !IS_GEN9_LP(dev_priv)))
 900                 return;
 901
 902         /*
 903          * We can't grab pps_mutex here due to deadlock with power_domain
 904          * mutex when power_domain functions are called while holding pps_mutex.
 905          * That also means that in order to use pps_pipe the code needs to
 906          * hold both a power domain reference and pps_mutex, and the power domain
 907          * reference get/put must be done while _not_ holding pps_mutex.
 908          * pps_{lock,unlock}() do these steps in the correct order, so one
 909          * should use them always.
 910          */
 911
 912         for_each_intel_dp(&dev_priv->drm, encoder) {
 913                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 914
 915                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 916
 917                 if (encoder->type != INTEL_OUTPUT_EDP)
 918                         continue;
 919
 920                 if (IS_GEN9_LP(dev_priv))
 921                         intel_dp->pps_reset = true;
 922                 else
 923                         intel_dp->pps_pipe = INVALID_PIPE;
 924         }
 925 }
 926
 927 struct pps_registers {
 928         i915_reg_t pp_ctrl;
 929         i915_reg_t pp_stat;
 930         i915_reg_t pp_on;
 931         i915_reg_t pp_off;
 932         i915_reg_t pp_div;
 933 };
 934
 935 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 936                                     struct pps_registers *regs)
 937 {
 938         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 939         int pps_idx = 0;
 940
 941         memset(regs, 0, sizeof(*regs));
 942
 943         if (IS_GEN9_LP(dev_priv))
 944                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 945         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 946                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 947
 948         regs->pp_ctrl = PP_CONTROL(pps_idx);
 949         regs->pp_stat = PP_STATUS(pps_idx);
 950         regs->pp_on = PP_ON_DELAYS(pps_idx);
 951         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 952
 953         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
 954         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
 955                 regs->pp_div = INVALID_MMIO_REG;
 956         else
 957                 regs->pp_div = PP_DIVISOR(pps_idx);
 958 }
 959
 960 static i915_reg_t
 961 _pp_ctrl_reg(struct intel_dp *intel_dp)
 962 {
 963         struct pps_registers regs;
 964
 965         intel_pps_get_registers(intel_dp, &regs);
 966
 967         return regs.pp_ctrl;
 968 }
 969
 970 static i915_reg_t
 971 _pp_stat_reg(struct intel_dp *intel_dp)
 972 {
 973         struct pps_registers regs;
 974
 975         intel_pps_get_registers(intel_dp, &regs);
 976
 977         return regs.pp_stat;
 978 }
 979
 980 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 981    This function only applicable when panel PM state is not to be tracked */
 982 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 983                               void *unused)
 984 {
 985         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 986                                                  edp_notifier);
 987         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 988         intel_wakeref_t wakeref;
 989
 990         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 991                 return 0;
 992
 993         with_pps_lock(intel_dp, wakeref) {
 994                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 995                         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 996                         i915_reg_t pp_ctrl_reg, pp_div_reg;
 997                         u32 pp_div;
 998
 999                         pp_ctrl_reg = PP_CONTROL(pipe);
1000                         pp_div_reg  = PP_DIVISOR(pipe);
1001                         pp_div = I915_READ(pp_div_reg);
1002                         pp_div &= PP_REFERENCE_DIVIDER_MASK;
1003
1004                         /* 0x1F write to PP_DIV_REG sets max cycle delay */
1005                         I915_WRITE(pp_div_reg, pp_div | 0x1F);
1006                         I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS);
1007                         msleep(intel_dp->panel_power_cycle_delay);
1008                 }
1009         }
1010
1011         return 0;
1012 }
1013
1014 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1015 {
1016         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1017
1018         lockdep_assert_held(&dev_priv->pps_mutex);
1019
1020         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1021             intel_dp->pps_pipe == INVALID_PIPE)
1022                 return false;
1023
1024         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1025 }
1026
1027 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1028 {
1029         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1030
1031         lockdep_assert_held(&dev_priv->pps_mutex);
1032
1033         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1034             intel_dp->pps_pipe == INVALID_PIPE)
1035                 return false;
1036
1037         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1038 }
1039
1040 static void
1041 intel_dp_check_edp(struct intel_dp *intel_dp)
1042 {
1043         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1044
1045         if (!intel_dp_is_edp(intel_dp))
1046                 return;
1047
1048         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1049                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1050                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1051                               I915_READ(_pp_stat_reg(intel_dp)),
1052                               I915_READ(_pp_ctrl_reg(intel_dp)));
1053         }
1054 }
1055
1056 static u32
1057 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1058 {
1059         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1060         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1061         u32 status;
1062         bool done;
1063
1064 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1065         done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
1066                                   msecs_to_jiffies_timeout(10));
1067
1068         /* just trace the final value */
1069         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1070
1071         if (!done)
1072                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1073 #undef C
1074
1075         return status;
1076 }
1077
1078 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1079 {
1080         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1081
1082         if (index)
1083                 return 0;
1084
1085         /*
1086          * The clock divider is based off the hrawclk, and would like to run at
1087          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1088          */
1089         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1090 }
1091
1092 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1093 {
1094         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1095         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1096
1097         if (index)
1098                 return 0;
1099
1100         /*
1101          * The clock divider is based off the cdclk or PCH rawclk, and would
1102          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1103          * divide by 2000 and use that
1104          */
1105         if (dig_port->aux_ch == AUX_CH_A)
1106                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1107         else
1108                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1109 }
1110
1111 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1112 {
1113         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1114         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1115
1116         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1117                 /* Workaround for non-ULT HSW */
1118                 switch (index) {
1119                 case 0: return 63;
1120                 case 1: return 72;
1121                 default: return 0;
1122                 }
1123         }
1124
1125         return ilk_get_aux_clock_divider(intel_dp, index);
1126 }
1127
1128 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1129 {
1130         /*
1131          * SKL doesn't need us to program the AUX clock divider (Hardware will
1132          * derive the clock from CDCLK automatically). We still implement the
1133          * get_aux_clock_divider vfunc to plug-in into the existing code.
1134          */
1135         return index ? 0 : 1;
1136 }
1137
1138 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1139                                 int send_bytes,
1140                                 u32 aux_clock_divider)
1141 {
1142         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1143         struct drm_i915_private *dev_priv =
1144                         to_i915(intel_dig_port->base.base.dev);
1145         u32 precharge, timeout;
1146
1147         if (IS_GEN(dev_priv, 6))
1148                 precharge = 3;
1149         else
1150                 precharge = 5;
1151
1152         if (IS_BROADWELL(dev_priv))
1153                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1154         else
1155                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1156
1157         return DP_AUX_CH_CTL_SEND_BUSY |
1158                DP_AUX_CH_CTL_DONE |
1159                DP_AUX_CH_CTL_INTERRUPT |
1160                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1161                timeout |
1162                DP_AUX_CH_CTL_RECEIVE_ERROR |
1163                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1164                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1165                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1166 }
1167
1168 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1169                                 int send_bytes,
1170                                 u32 unused)
1171 {
1172         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1173         u32 ret;
1174
1175         ret = DP_AUX_CH_CTL_SEND_BUSY |
1176               DP_AUX_CH_CTL_DONE |
1177               DP_AUX_CH_CTL_INTERRUPT |
1178               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1179               DP_AUX_CH_CTL_TIME_OUT_MAX |
1180               DP_AUX_CH_CTL_RECEIVE_ERROR |
1181               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1182               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1183               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1184
1185         if (intel_dig_port->tc_type == TC_PORT_TBT)
1186                 ret |= DP_AUX_CH_CTL_TBT_IO;
1187
1188         return ret;
1189 }
1190
1191 static int
1192 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1193                   const u8 *send, int send_bytes,
1194                   u8 *recv, int recv_size,
1195                   u32 aux_send_ctl_flags)
1196 {
1197         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1198         struct drm_i915_private *dev_priv =
1199                         to_i915(intel_dig_port->base.base.dev);
1200         i915_reg_t ch_ctl, ch_data[5];
1201         u32 aux_clock_divider;
1202         intel_wakeref_t wakeref;
1203         int i, ret, recv_bytes;
1204         int try, clock = 0;
1205         u32 status;
1206         bool vdd;
1207
1208         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1209         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1210                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1211
1212         wakeref = pps_lock(intel_dp);
1213
1214         /*
1215          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1216          * In such cases we want to leave VDD enabled and it's up to upper layers
1217          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1218          * ourselves.
1219          */
1220         vdd = edp_panel_vdd_on(intel_dp);
1221
1222         /* dp aux is extremely sensitive to irq latency, hence request the
1223          * lowest possible wakeup latency and so prevent the cpu from going into
1224          * deep sleep states.
1225          */
1226         pm_qos_update_request(&dev_priv->pm_qos, 0);
1227
1228         intel_dp_check_edp(intel_dp);
1229
1230         /* Try to wait for any previous AUX channel activity */
1231         for (try = 0; try < 3; try++) {
1232                 status = I915_READ_NOTRACE(ch_ctl);
1233                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1234                         break;
1235                 msleep(1);
1236         }
1237         /* just trace the final value */
1238         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1239
1240         if (try == 3) {
1241                 static u32 last_status = -1;
1242                 const u32 status = I915_READ(ch_ctl);
1243
1244                 if (status != last_status) {
1245                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1246                              status);
1247                         last_status = status;
1248                 }
1249
1250                 ret = -EBUSY;
1251                 goto out;
1252         }
1253
1254         /* Only 5 data registers! */
1255         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1256                 ret = -E2BIG;
1257                 goto out;
1258         }
1259
1260         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1261                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1262                                                           send_bytes,
1263                                                           aux_clock_divider);
1264
1265                 send_ctl |= aux_send_ctl_flags;
1266
1267                 /* Must try at least 3 times according to DP spec */
1268                 for (try = 0; try < 5; try++) {
1269                         /* Load the send data into the aux channel data registers */
1270                         for (i = 0; i < send_bytes; i += 4)
1271                                 I915_WRITE(ch_data[i >> 2],
1272                                            intel_dp_pack_aux(send + i,
1273                                                              send_bytes - i));
1274
1275                         /* Send the command and wait for it to complete */
1276                         I915_WRITE(ch_ctl, send_ctl);
1277
1278                         status = intel_dp_aux_wait_done(intel_dp);
1279
1280                         /* Clear done status and any errors */
1281                         I915_WRITE(ch_ctl,
1282                                    status |
1283                                    DP_AUX_CH_CTL_DONE |
1284                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1285                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1286
1287                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1288                          *   400us delay required for errors and timeouts
1289                          *   Timeout errors from the HW already meet this
1290                          *   requirement so skip to next iteration
1291                          */
1292                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1293                                 continue;
1294
1295                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1296                                 usleep_range(400, 500);
1297                                 continue;
1298                         }
1299                         if (status & DP_AUX_CH_CTL_DONE)
1300                                 goto done;
1301                 }
1302         }
1303
1304         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1305                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1306                 ret = -EBUSY;
1307                 goto out;
1308         }
1309
1310 done:
1311         /* Check for timeout or receive error.
1312          * Timeouts occur when the sink is not connected
1313          */
1314         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1315                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1316                 ret = -EIO;
1317                 goto out;
1318         }
1319
1320         /* Timeouts occur when the device isn't connected, so they're
1321          * "normal" -- don't fill the kernel log with these */
1322         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1323                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1324                 ret = -ETIMEDOUT;
1325                 goto out;
1326         }
1327
1328         /* Unload any bytes sent back from the other side */
1329         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1330                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1331
1332         /*
1333          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1334          * We have no idea of what happened so we return -EBUSY so
1335          * drm layer takes care for the necessary retries.
1336          */
1337         if (recv_bytes == 0 || recv_bytes > 20) {
1338                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1339                               recv_bytes);
1340                 ret = -EBUSY;
1341                 goto out;
1342         }
1343
1344         if (recv_bytes > recv_size)
1345                 recv_bytes = recv_size;
1346
1347         for (i = 0; i < recv_bytes; i += 4)
1348                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1349                                     recv + i, recv_bytes - i);
1350
1351         ret = recv_bytes;
1352 out:
1353         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1354
1355         if (vdd)
1356                 edp_panel_vdd_off(intel_dp, false);
1357
1358         pps_unlock(intel_dp, wakeref);
1359
1360         return ret;
1361 }
1362
1363 #define BARE_ADDRESS_SIZE       3
1364 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1365
1366 static void
1367 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1368                     const struct drm_dp_aux_msg *msg)
1369 {
1370         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1371         txbuf[1] = (msg->address >> 8) & 0xff;
1372         txbuf[2] = msg->address & 0xff;
1373         txbuf[3] = msg->size - 1;
1374 }
1375
1376 static ssize_t
1377 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1378 {
1379         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1380         u8 txbuf[20], rxbuf[20];
1381         size_t txsize, rxsize;
1382         int ret;
1383
1384         intel_dp_aux_header(txbuf, msg);
1385
1386         switch (msg->request & ~DP_AUX_I2C_MOT) {
1387         case DP_AUX_NATIVE_WRITE:
1388         case DP_AUX_I2C_WRITE:
1389         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1390                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1391                 rxsize = 2; /* 0 or 1 data bytes */
1392
1393                 if (WARN_ON(txsize > 20))
1394                         return -E2BIG;
1395
1396                 WARN_ON(!msg->buffer != !msg->size);
1397
1398                 if (msg->buffer)
1399                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1400
1401                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1402                                         rxbuf, rxsize, 0);
1403                 if (ret > 0) {
1404                         msg->reply = rxbuf[0] >> 4;
1405
1406                         if (ret > 1) {
1407                                 /* Number of bytes written in a short write. */
1408                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1409                         } else {
1410                                 /* Return payload size. */
1411                                 ret = msg->size;
1412                         }
1413                 }
1414                 break;
1415
1416         case DP_AUX_NATIVE_READ:
1417         case DP_AUX_I2C_READ:
1418                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1419                 rxsize = msg->size + 1;
1420
1421                 if (WARN_ON(rxsize > 20))
1422                         return -E2BIG;
1423
1424                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1425                                         rxbuf, rxsize, 0);
1426                 if (ret > 0) {
1427                         msg->reply = rxbuf[0] >> 4;
1428                         /*
1429                          * Assume happy day, and copy the data. The caller is
1430                          * expected to check msg->reply before touching it.
1431                          *
1432                          * Return payload size.
1433                          */
1434                         ret--;
1435                         memcpy(msg->buffer, rxbuf + 1, ret);
1436                 }
1437                 break;
1438
1439         default:
1440                 ret = -EINVAL;
1441                 break;
1442         }
1443
1444         return ret;
1445 }
1446
1447
1448 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1449 {
1450         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1451         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1452         enum aux_ch aux_ch = dig_port->aux_ch;
1453
1454         switch (aux_ch) {
1455         case AUX_CH_B:
1456         case AUX_CH_C:
1457         case AUX_CH_D:
1458                 return DP_AUX_CH_CTL(aux_ch);
1459         default:
1460                 MISSING_CASE(aux_ch);
1461                 return DP_AUX_CH_CTL(AUX_CH_B);
1462         }
1463 }
1464
1465 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1466 {
1467         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1468         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1469         enum aux_ch aux_ch = dig_port->aux_ch;
1470
1471         switch (aux_ch) {
1472         case AUX_CH_B:
1473         case AUX_CH_C:
1474         case AUX_CH_D:
1475                 return DP_AUX_CH_DATA(aux_ch, index);
1476         default:
1477                 MISSING_CASE(aux_ch);
1478                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1479         }
1480 }
1481
1482 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1483 {
1484         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1485         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1486         enum aux_ch aux_ch = dig_port->aux_ch;
1487
1488         switch (aux_ch) {
1489         case AUX_CH_A:
1490                 return DP_AUX_CH_CTL(aux_ch);
1491         case AUX_CH_B:
1492         case AUX_CH_C:
1493         case AUX_CH_D:
1494                 return PCH_DP_AUX_CH_CTL(aux_ch);
1495         default:
1496                 MISSING_CASE(aux_ch);
1497                 return DP_AUX_CH_CTL(AUX_CH_A);
1498         }
1499 }
1500
1501 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1502 {
1503         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1504         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1505         enum aux_ch aux_ch = dig_port->aux_ch;
1506
1507         switch (aux_ch) {
1508         case AUX_CH_A:
1509                 return DP_AUX_CH_DATA(aux_ch, index);
1510         case AUX_CH_B:
1511         case AUX_CH_C:
1512         case AUX_CH_D:
1513                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1514         default:
1515                 MISSING_CASE(aux_ch);
1516                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1517         }
1518 }
1519
1520 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1521 {
1522         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1523         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1524         enum aux_ch aux_ch = dig_port->aux_ch;
1525
1526         switch (aux_ch) {
1527         case AUX_CH_A:
1528         case AUX_CH_B:
1529         case AUX_CH_C:
1530         case AUX_CH_D:
1531         case AUX_CH_E:
1532         case AUX_CH_F:
1533                 return DP_AUX_CH_CTL(aux_ch);
1534         default:
1535                 MISSING_CASE(aux_ch);
1536                 return DP_AUX_CH_CTL(AUX_CH_A);
1537         }
1538 }
1539
1540 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1541 {
1542         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1543         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1544         enum aux_ch aux_ch = dig_port->aux_ch;
1545
1546         switch (aux_ch) {
1547         case AUX_CH_A:
1548         case AUX_CH_B:
1549         case AUX_CH_C:
1550         case AUX_CH_D:
1551         case AUX_CH_E:
1552         case AUX_CH_F:
1553                 return DP_AUX_CH_DATA(aux_ch, index);
1554         default:
1555                 MISSING_CASE(aux_ch);
1556                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1557         }
1558 }
1559
1560 static void
1561 intel_dp_aux_fini(struct intel_dp *intel_dp)
1562 {
1563         kfree(intel_dp->aux.name);
1564 }
1565
1566 static void
1567 intel_dp_aux_init(struct intel_dp *intel_dp)
1568 {
1569         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1570         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1571         struct intel_encoder *encoder = &dig_port->base;
1572
1573         if (INTEL_GEN(dev_priv) >= 9) {
1574                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1575                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1576         } else if (HAS_PCH_SPLIT(dev_priv)) {
1577                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1578                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1579         } else {
1580                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1581                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1582         }
1583
1584         if (INTEL_GEN(dev_priv) >= 9)
1585                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1586         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1587                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1588         else if (HAS_PCH_SPLIT(dev_priv))
1589                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1590         else
1591                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1592
1593         if (INTEL_GEN(dev_priv) >= 9)
1594                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1595         else
1596                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1597
1598         drm_dp_aux_init(&intel_dp->aux);
1599
1600         /* Failure to allocate our preferred name is not critical */
1601         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1602                                        port_name(encoder->port));
1603         intel_dp->aux.transfer = intel_dp_aux_transfer;
1604 }
1605
1606 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1607 {
1608         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1609
1610         return max_rate >= 540000;
1611 }
1612
1613 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1614 {
1615         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1616
1617         return max_rate >= 810000;
1618 }
1619
1620 static void
1621 intel_dp_set_clock(struct intel_encoder *encoder,
1622                    struct intel_crtc_state *pipe_config)
1623 {
1624         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1625         const struct dp_link_dpll *divisor = NULL;
1626         int i, count = 0;
1627
1628         if (IS_G4X(dev_priv)) {
1629                 divisor = g4x_dpll;
1630                 count = ARRAY_SIZE(g4x_dpll);
1631         } else if (HAS_PCH_SPLIT(dev_priv)) {
1632                 divisor = pch_dpll;
1633                 count = ARRAY_SIZE(pch_dpll);
1634         } else if (IS_CHERRYVIEW(dev_priv)) {
1635                 divisor = chv_dpll;
1636                 count = ARRAY_SIZE(chv_dpll);
1637         } else if (IS_VALLEYVIEW(dev_priv)) {
1638                 divisor = vlv_dpll;
1639                 count = ARRAY_SIZE(vlv_dpll);
1640         }
1641
1642         if (divisor && count) {
1643                 for (i = 0; i < count; i++) {
1644                         if (pipe_config->port_clock == divisor[i].clock) {
1645                                 pipe_config->dpll = divisor[i].dpll;
1646                                 pipe_config->clock_set = true;
1647                                 break;
1648                         }
1649                 }
1650         }
1651 }
1652
1653 static void snprintf_int_array(char *str, size_t len,
1654                                const int *array, int nelem)
1655 {
1656         int i;
1657
1658         str[0] = '\0';
1659
1660         for (i = 0; i < nelem; i++) {
1661                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1662                 if (r >= len)
1663                         return;
1664                 str += r;
1665                 len -= r;
1666         }
1667 }
1668
1669 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1670 {
1671         char str[128]; /* FIXME: too big for stack? */
1672
1673         if ((drm_debug & DRM_UT_KMS) == 0)
1674                 return;
1675
1676         snprintf_int_array(str, sizeof(str),
1677                            intel_dp->source_rates, intel_dp->num_source_rates);
1678         DRM_DEBUG_KMS("source rates: %s\n", str);
1679
1680         snprintf_int_array(str, sizeof(str),
1681                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1682         DRM_DEBUG_KMS("sink rates: %s\n", str);
1683
1684         snprintf_int_array(str, sizeof(str),
1685                            intel_dp->common_rates, intel_dp->num_common_rates);
1686         DRM_DEBUG_KMS("common rates: %s\n", str);
1687 }
1688
1689 int
1690 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1691 {
1692         int len;
1693
1694         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1695         if (WARN_ON(len <= 0))
1696                 return 162000;
1697
1698         return intel_dp->common_rates[len - 1];
1699 }
1700
1701 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1702 {
1703         int i = intel_dp_rate_index(intel_dp->sink_rates,
1704                                     intel_dp->num_sink_rates, rate);
1705
1706         if (WARN_ON(i < 0))
1707                 i = 0;
1708
1709         return i;
1710 }
1711
1712 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1713                            u8 *link_bw, u8 *rate_select)
1714 {
1715         /* eDP 1.4 rate select method. */
1716         if (intel_dp->use_rate_select) {
1717                 *link_bw = 0;
1718                 *rate_select =
1719                         intel_dp_rate_select(intel_dp, port_clock);
1720         } else {
1721                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1722                 *rate_select = 0;
1723         }
1724 }
1725
1726 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1727                                          const struct intel_crtc_state *pipe_config)
1728 {
1729         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1730
1731         return INTEL_GEN(dev_priv) >= 11 &&
1732                 pipe_config->cpu_transcoder != TRANSCODER_A;
1733 }
1734
1735 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1736                                   const struct intel_crtc_state *pipe_config)
1737 {
1738         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1739                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1740 }
1741
1742 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1743                                          const struct intel_crtc_state *pipe_config)
1744 {
1745         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1746
1747         return INTEL_GEN(dev_priv) >= 10 &&
1748                 pipe_config->cpu_transcoder != TRANSCODER_A;
1749 }
1750
1751 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1752                                   const struct intel_crtc_state *pipe_config)
1753 {
1754         if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1755                 return false;
1756
1757         return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1758                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1759 }
1760
1761 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1762                                 struct intel_crtc_state *pipe_config)
1763 {
1764         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1765         struct intel_connector *intel_connector = intel_dp->attached_connector;
1766         int bpp, bpc;
1767
1768         bpp = pipe_config->pipe_bpp;
1769         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1770
1771         if (bpc > 0)
1772                 bpp = min(bpp, 3*bpc);
1773
1774         if (intel_dp_is_edp(intel_dp)) {
1775                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1776                 if (intel_connector->base.display_info.bpc == 0 &&
1777                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1778                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1779                                       dev_priv->vbt.edp.bpp);
1780                         bpp = dev_priv->vbt.edp.bpp;
1781                 }
1782         }
1783
1784         return bpp;
1785 }
1786
1787 /* Adjust link config limits based on compliance test requests. */
1788 void
1789 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1790                                   struct intel_crtc_state *pipe_config,
1791                                   struct link_config_limits *limits)
1792 {
1793         /* For DP Compliance we override the computed bpp for the pipe */
1794         if (intel_dp->compliance.test_data.bpc != 0) {
1795                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1796
1797                 limits->min_bpp = limits->max_bpp = bpp;
1798                 pipe_config->dither_force_disable = bpp == 6 * 3;
1799
1800                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1801         }
1802
1803         /* Use values requested by Compliance Test Request */
1804         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1805                 int index;
1806
1807                 /* Validate the compliance test data since max values
1808                  * might have changed due to link train fallback.
1809                  */
1810                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1811                                                intel_dp->compliance.test_lane_count)) {
1812                         index = intel_dp_rate_index(intel_dp->common_rates,
1813                                                     intel_dp->num_common_rates,
1814                                                     intel_dp->compliance.test_link_rate);
1815                         if (index >= 0)
1816                                 limits->min_clock = limits->max_clock = index;
1817                         limits->min_lane_count = limits->max_lane_count =
1818                                 intel_dp->compliance.test_lane_count;
1819                 }
1820         }
1821 }
1822
1823 /* Optimize link config in order: max bpp, min clock, min lanes */
1824 static int
1825 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1826                                   struct intel_crtc_state *pipe_config,
1827                                   const struct link_config_limits *limits)
1828 {
1829         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1830         int bpp, clock, lane_count;
1831         int mode_rate, link_clock, link_avail;
1832
1833         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1834                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1835                                                    bpp);
1836
1837                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1838                         for (lane_count = limits->min_lane_count;
1839                              lane_count <= limits->max_lane_count;
1840                              lane_count <<= 1) {
1841                                 link_clock = intel_dp->common_rates[clock];
1842                                 link_avail = intel_dp_max_data_rate(link_clock,
1843                                                                     lane_count);
1844
1845                                 if (mode_rate <= link_avail) {
1846                                         pipe_config->lane_count = lane_count;
1847                                         pipe_config->pipe_bpp = bpp;
1848                                         pipe_config->port_clock = link_clock;
1849
1850                                         return 0;
1851                                 }
1852                         }
1853                 }
1854         }
1855
1856         return -EINVAL;
1857 }
1858
1859 /* Optimize link config in order: max bpp, min lanes, min clock */
1860 static int
1861 intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
1862                                   struct intel_crtc_state *pipe_config,
1863                                   const struct link_config_limits *limits)
1864 {
1865         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1866         int bpp, clock, lane_count;
1867         int mode_rate, link_clock, link_avail;
1868
1869         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1870                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1871                                                    bpp);
1872
1873                 for (lane_count = limits->min_lane_count;
1874                      lane_count <= limits->max_lane_count;
1875                      lane_count <<= 1) {
1876                         for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1877                                 link_clock = intel_dp->common_rates[clock];
1878                                 link_avail = intel_dp_max_data_rate(link_clock,
1879                                                                     lane_count);
1880
1881                                 if (mode_rate <= link_avail) {
1882                                         pipe_config->lane_count = lane_count;
1883                                         pipe_config->pipe_bpp = bpp;
1884                                         pipe_config->port_clock = link_clock;
1885
1886                                         return 0;
1887                                 }
1888                         }
1889                 }
1890         }
1891
1892         return -EINVAL;
1893 }
1894
1895 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
1896 {
1897         int i, num_bpc;
1898         u8 dsc_bpc[3] = {0};
1899
1900         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
1901                                                        dsc_bpc);
1902         for (i = 0; i < num_bpc; i++) {
1903                 if (dsc_max_bpc >= dsc_bpc[i])
1904                         return dsc_bpc[i] * 3;
1905         }
1906
1907         return 0;
1908 }
1909
1910 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
1911                                        struct intel_crtc_state *pipe_config,
1912                                        struct drm_connector_state *conn_state,
1913                                        struct link_config_limits *limits)
1914 {
1915         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1916         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1917         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1918         u8 dsc_max_bpc;
1919         int pipe_bpp;
1920         int ret;
1921
1922         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
1923                 return -EINVAL;
1924
1925         dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
1926                             conn_state->max_requested_bpc);
1927
1928         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
1929         if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
1930                 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
1931                 return -EINVAL;
1932         }
1933
1934         /*
1935          * For now enable DSC for max bpp, max link rate, max lane count.
1936          * Optimize this later for the minimum possible link rate/lane count
1937          * with DSC enabled for the requested mode.
1938          */
1939         pipe_config->pipe_bpp = pipe_bpp;
1940         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
1941         pipe_config->lane_count = limits->max_lane_count;
1942
1943         if (intel_dp_is_edp(intel_dp)) {
1944                 pipe_config->dsc_params.compressed_bpp =
1945                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
1946                               pipe_config->pipe_bpp);
1947                 pipe_config->dsc_params.slice_count =
1948                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
1949                                                         true);
1950         } else {
1951                 u16 dsc_max_output_bpp;
1952                 u8 dsc_dp_slice_count;
1953
1954                 dsc_max_output_bpp =
1955                         intel_dp_dsc_get_output_bpp(pipe_config->port_clock,
1956                                                     pipe_config->lane_count,
1957                                                     adjusted_mode->crtc_clock,
1958                                                     adjusted_mode->crtc_hdisplay);
1959                 dsc_dp_slice_count =
1960                         intel_dp_dsc_get_slice_count(intel_dp,
1961                                                      adjusted_mode->crtc_clock,
1962                                                      adjusted_mode->crtc_hdisplay);
1963                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
1964                         DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
1965                         return -EINVAL;
1966                 }
1967                 pipe_config->dsc_params.compressed_bpp = min_t(u16,
1968                                                                dsc_max_output_bpp >> 4,
1969                                                                pipe_config->pipe_bpp);
1970                 pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
1971         }
1972         /*
1973          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
1974          * is greater than the maximum Cdclock and if slice count is even
1975          * then we need to use 2 VDSC instances.
1976          */
1977         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
1978                 if (pipe_config->dsc_params.slice_count > 1) {
1979                         pipe_config->dsc_params.dsc_split = true;
1980                 } else {
1981                         DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
1982                         return -EINVAL;
1983                 }
1984         }
1985
1986         ret = intel_dp_compute_dsc_params(intel_dp, pipe_config);
1987         if (ret < 0) {
1988                 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
1989                               "Compressed BPP = %d\n",
1990                               pipe_config->pipe_bpp,
1991                               pipe_config->dsc_params.compressed_bpp);
1992                 return ret;
1993         }
1994
1995         pipe_config->dsc_params.compression_enable = true;
1996         DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
1997                       "Compressed Bpp = %d Slice Count = %d\n",
1998                       pipe_config->pipe_bpp,
1999                       pipe_config->dsc_params.compressed_bpp,
2000                       pipe_config->dsc_params.slice_count);
2001
2002         return 0;
2003 }
2004
2005 static int
2006 intel_dp_compute_link_config(struct intel_encoder *encoder,
2007                              struct intel_crtc_state *pipe_config,
2008                              struct drm_connector_state *conn_state)
2009 {
2010         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2011         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2012         struct link_config_limits limits;
2013         int common_len;
2014         int ret;
2015
2016         common_len = intel_dp_common_len_rate_limit(intel_dp,
2017                                                     intel_dp->max_link_rate);
2018
2019         /* No common link rates between source and sink */
2020         WARN_ON(common_len <= 0);
2021
2022         limits.min_clock = 0;
2023         limits.max_clock = common_len - 1;
2024
2025         limits.min_lane_count = 1;
2026         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2027
2028         limits.min_bpp = 6 * 3;
2029         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2030
2031         if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
2032                 /*
2033                  * Use the maximum clock and number of lanes the eDP panel
2034                  * advertizes being capable of. The eDP 1.3 and earlier panels
2035                  * are generally designed to support only a single clock and
2036                  * lane configuration, and typically these values correspond to
2037                  * the native resolution of the panel. With eDP 1.4 rate select
2038                  * and DSC, this is decreasingly the case, and we need to be
2039                  * able to select less than maximum link config.
2040                  */
2041                 limits.min_lane_count = limits.max_lane_count;
2042                 limits.min_clock = limits.max_clock;
2043         }
2044
2045         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2046
2047         DRM_DEBUG_KMS("DP link computation with max lane count %i "
2048                       "max rate %d max bpp %d pixel clock %iKHz\n",
2049                       limits.max_lane_count,
2050                       intel_dp->common_rates[limits.max_clock],
2051                       limits.max_bpp, adjusted_mode->crtc_clock);
2052
2053         if (intel_dp_is_edp(intel_dp))
2054                 /*
2055                  * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
2056                  * section A.1: "It is recommended that the minimum number of
2057                  * lanes be used, using the minimum link rate allowed for that
2058                  * lane configuration."
2059                  *
2060                  * Note that we use the max clock and lane count for eDP 1.3 and
2061                  * earlier, and fast vs. wide is irrelevant.
2062                  */
2063                 ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config,
2064                                                         &limits);
2065         else
2066                 /* Optimize for slow and wide. */
2067                 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2068                                                         &limits);
2069
2070         /* enable compression if the mode doesn't fit available BW */
2071         DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
2072         if (ret || intel_dp->force_dsc_en) {
2073                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2074                                                   conn_state, &limits);
2075                 if (ret < 0)
2076                         return ret;
2077         }
2078
2079         if (pipe_config->dsc_params.compression_enable) {
2080                 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2081                               pipe_config->lane_count, pipe_config->port_clock,
2082                               pipe_config->pipe_bpp,
2083                               pipe_config->dsc_params.compressed_bpp);
2084
2085                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2086                               intel_dp_link_required(adjusted_mode->crtc_clock,
2087                                                      pipe_config->dsc_params.compressed_bpp),
2088                               intel_dp_max_data_rate(pipe_config->port_clock,
2089                                                      pipe_config->lane_count));
2090         } else {
2091                 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2092                               pipe_config->lane_count, pipe_config->port_clock,
2093                               pipe_config->pipe_bpp);
2094
2095                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2096                               intel_dp_link_required(adjusted_mode->crtc_clock,
2097                                                      pipe_config->pipe_bpp),
2098                               intel_dp_max_data_rate(pipe_config->port_clock,
2099                                                      pipe_config->lane_count));
2100         }
2101         return 0;
2102 }
2103
2104 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2105                                   const struct drm_connector_state *conn_state)
2106 {
2107         const struct intel_digital_connector_state *intel_conn_state =
2108                 to_intel_digital_connector_state(conn_state);
2109         const struct drm_display_mode *adjusted_mode =
2110                 &crtc_state->base.adjusted_mode;
2111
2112         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2113                 /*
2114                  * See:
2115                  * CEA-861-E - 5.1 Default Encoding Parameters
2116                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2117                  */
2118                 return crtc_state->pipe_bpp != 18 &&
2119                         drm_default_rgb_quant_range(adjusted_mode) ==
2120                         HDMI_QUANTIZATION_RANGE_LIMITED;
2121         } else {
2122                 return intel_conn_state->broadcast_rgb ==
2123                         INTEL_BROADCAST_RGB_LIMITED;
2124         }
2125 }
2126
2127 int
2128 intel_dp_compute_config(struct intel_encoder *encoder,
2129                         struct intel_crtc_state *pipe_config,
2130                         struct drm_connector_state *conn_state)
2131 {
2132         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2133         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2134         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2135         struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2136         enum port port = encoder->port;
2137         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2138         struct intel_connector *intel_connector = intel_dp->attached_connector;
2139         struct intel_digital_connector_state *intel_conn_state =
2140                 to_intel_digital_connector_state(conn_state);
2141         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2142                                            DP_DPCD_QUIRK_CONSTANT_N);
2143         int ret;
2144
2145         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2146                 pipe_config->has_pch_encoder = true;
2147
2148         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2149         if (lspcon->active)
2150                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2151
2152         pipe_config->has_drrs = false;
2153         if (IS_G4X(dev_priv) || port == PORT_A)
2154                 pipe_config->has_audio = false;
2155         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2156                 pipe_config->has_audio = intel_dp->has_audio;
2157         else
2158                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2159
2160         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2161                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2162                                        adjusted_mode);
2163
2164                 if (INTEL_GEN(dev_priv) >= 9) {
2165                         ret = skl_update_scaler_crtc(pipe_config);
2166                         if (ret)
2167                                 return ret;
2168                 }
2169
2170                 if (HAS_GMCH(dev_priv))
2171                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2172                                                  conn_state->scaling_mode);
2173                 else
2174                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2175                                                 conn_state->scaling_mode);
2176         }
2177
2178         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2179                 return -EINVAL;
2180
2181         if (HAS_GMCH(dev_priv) &&
2182             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2183                 return -EINVAL;
2184
2185         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2186                 return -EINVAL;
2187
2188         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2189                                   intel_dp_supports_fec(intel_dp, pipe_config);
2190
2191         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2192         if (ret < 0)
2193                 return ret;
2194
2195         pipe_config->limited_color_range =
2196                 intel_dp_limited_color_range(pipe_config, conn_state);
2197
2198         if (!pipe_config->dsc_params.compression_enable)
2199                 intel_link_compute_m_n(pipe_config->pipe_bpp,
2200                                        pipe_config->lane_count,
2201                                        adjusted_mode->crtc_clock,
2202                                        pipe_config->port_clock,
2203                                        &pipe_config->dp_m_n,
2204                                        constant_n);
2205         else
2206                 intel_link_compute_m_n(pipe_config->dsc_params.compressed_bpp,
2207                                        pipe_config->lane_count,
2208                                        adjusted_mode->crtc_clock,
2209                                        pipe_config->port_clock,
2210                                        &pipe_config->dp_m_n,
2211                                        constant_n);
2212
2213         if (intel_connector->panel.downclock_mode != NULL &&
2214                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2215                         pipe_config->has_drrs = true;
2216                         intel_link_compute_m_n(pipe_config->pipe_bpp,
2217                                                pipe_config->lane_count,
2218                                                intel_connector->panel.downclock_mode->clock,
2219                                                pipe_config->port_clock,
2220                                                &pipe_config->dp_m2_n2,
2221                                                constant_n);
2222         }
2223
2224         if (!HAS_DDI(dev_priv))
2225                 intel_dp_set_clock(encoder, pipe_config);
2226
2227         intel_psr_compute_config(intel_dp, pipe_config);
2228
2229         return 0;
2230 }
2231
2232 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2233                               int link_rate, u8 lane_count,
2234                               bool link_mst)
2235 {
2236         intel_dp->link_trained = false;
2237         intel_dp->link_rate = link_rate;
2238         intel_dp->lane_count = lane_count;
2239         intel_dp->link_mst = link_mst;
2240 }
2241
2242 static void intel_dp_prepare(struct intel_encoder *encoder,
2243                              const struct intel_crtc_state *pipe_config)
2244 {
2245         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2246         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2247         enum port port = encoder->port;
2248         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2249         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2250
2251         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2252                                  pipe_config->lane_count,
2253                                  intel_crtc_has_type(pipe_config,
2254                                                      INTEL_OUTPUT_DP_MST));
2255
2256         /*
2257          * There are four kinds of DP registers:
2258          *
2259          *      IBX PCH
2260          *      SNB CPU
2261          *      IVB CPU
2262          *      CPT PCH
2263          *
2264          * IBX PCH and CPU are the same for almost everything,
2265          * except that the CPU DP PLL is configured in this
2266          * register
2267          *
2268          * CPT PCH is quite different, having many bits moved
2269          * to the TRANS_DP_CTL register instead. That
2270          * configuration happens (oddly) in ironlake_pch_enable
2271          */
2272
2273         /* Preserve the BIOS-computed detected bit. This is
2274          * supposed to be read-only.
2275          */
2276         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2277
2278         /* Handle DP bits in common between all three register formats */
2279         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2280         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2281
2282         /* Split out the IBX/CPU vs CPT settings */
2283
2284         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2285                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2286                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2287                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2288                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2289                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2290
2291                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2292                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2293
2294                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2295         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2296                 u32 trans_dp;
2297
2298                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2299
2300                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2301                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2302                         trans_dp |= TRANS_DP_ENH_FRAMING;
2303                 else
2304                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2305                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2306         } else {
2307                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2308                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2309
2310                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2311                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2312                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2313                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2314                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2315
2316                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2317                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2318
2319                 if (IS_CHERRYVIEW(dev_priv))
2320                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2321                 else
2322                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2323         }
2324 }
2325
2326 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2327 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2328
2329 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2330 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2331
2332 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2333 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2334
2335 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2336
2337 static void wait_panel_status(struct intel_dp *intel_dp,
2338                                        u32 mask,
2339                                        u32 value)
2340 {
2341         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2342         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2343
2344         lockdep_assert_held(&dev_priv->pps_mutex);
2345
2346         intel_pps_verify_state(intel_dp);
2347
2348         pp_stat_reg = _pp_stat_reg(intel_dp);
2349         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2350
2351         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2352                         mask, value,
2353                         I915_READ(pp_stat_reg),
2354                         I915_READ(pp_ctrl_reg));
2355
2356         if (intel_wait_for_register(&dev_priv->uncore,
2357                                     pp_stat_reg, mask, value,
2358                                     5000))
2359                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2360                                 I915_READ(pp_stat_reg),
2361                                 I915_READ(pp_ctrl_reg));
2362
2363         DRM_DEBUG_KMS("Wait complete\n");
2364 }
2365
2366 static void wait_panel_on(struct intel_dp *intel_dp)
2367 {
2368         DRM_DEBUG_KMS("Wait for panel power on\n");
2369         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2370 }
2371
2372 static void wait_panel_off(struct intel_dp *intel_dp)
2373 {
2374         DRM_DEBUG_KMS("Wait for panel power off time\n");
2375         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2376 }
2377
2378 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2379 {
2380         ktime_t panel_power_on_time;
2381         s64 panel_power_off_duration;
2382
2383         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2384
2385         /* take the difference of currrent time and panel power off time
2386          * and then make panel wait for t11_t12 if needed. */
2387         panel_power_on_time = ktime_get_boottime();
2388         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2389
2390         /* When we disable the VDD override bit last we have to do the manual
2391          * wait. */
2392         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2393                 wait_remaining_ms_from_jiffies(jiffies,
2394                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2395
2396         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2397 }
2398
2399 static void wait_backlight_on(struct intel_dp *intel_dp)
2400 {
2401         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2402                                        intel_dp->backlight_on_delay);
2403 }
2404
2405 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2406 {
2407         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2408                                        intel_dp->backlight_off_delay);
2409 }
2410
2411 /* Read the current pp_control value, unlocking the register if it
2412  * is locked
2413  */
2414
2415 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2416 {
2417         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2418         u32 control;
2419
2420         lockdep_assert_held(&dev_priv->pps_mutex);
2421
2422         control = I915_READ(_pp_ctrl_reg(intel_dp));
2423         if (WARN_ON(!HAS_DDI(dev_priv) &&
2424                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2425                 control &= ~PANEL_UNLOCK_MASK;
2426                 control |= PANEL_UNLOCK_REGS;
2427         }
2428         return control;
2429 }
2430
2431 /*
2432  * Must be paired with edp_panel_vdd_off().
2433  * Must hold pps_mutex around the whole on/off sequence.
2434  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2435  */
2436 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2437 {
2438         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2439         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2440         u32 pp;
2441         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2442         bool need_to_disable = !intel_dp->want_panel_vdd;
2443
2444         lockdep_assert_held(&dev_priv->pps_mutex);
2445
2446         if (!intel_dp_is_edp(intel_dp))
2447                 return false;
2448
2449         cancel_delayed_work(&intel_dp->panel_vdd_work);
2450         intel_dp->want_panel_vdd = true;
2451
2452         if (edp_have_panel_vdd(intel_dp))
2453                 return need_to_disable;
2454
2455         intel_display_power_get(dev_priv,
2456                                 intel_aux_power_domain(intel_dig_port));
2457
2458         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2459                       port_name(intel_dig_port->base.port));
2460
2461         if (!edp_have_panel_power(intel_dp))
2462                 wait_panel_power_cycle(intel_dp);
2463
2464         pp = ironlake_get_pp_control(intel_dp);
2465         pp |= EDP_FORCE_VDD;
2466
2467         pp_stat_reg = _pp_stat_reg(intel_dp);
2468         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2469
2470         I915_WRITE(pp_ctrl_reg, pp);
2471         POSTING_READ(pp_ctrl_reg);
2472         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2473                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2474         /*
2475          * If the panel wasn't on, delay before accessing aux channel
2476          */
2477         if (!edp_have_panel_power(intel_dp)) {
2478                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2479                               port_name(intel_dig_port->base.port));
2480                 msleep(intel_dp->panel_power_up_delay);
2481         }
2482
2483         return need_to_disable;
2484 }
2485
2486 /*
2487  * Must be paired with intel_edp_panel_vdd_off() or
2488  * intel_edp_panel_off().
2489  * Nested calls to these functions are not allowed since
2490  * we drop the lock. Caller must use some higher level
2491  * locking to prevent nested calls from other threads.
2492  */
2493 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2494 {
2495         intel_wakeref_t wakeref;
2496         bool vdd;
2497
2498         if (!intel_dp_is_edp(intel_dp))
2499                 return;
2500
2501         vdd = false;
2502         with_pps_lock(intel_dp, wakeref)
2503                 vdd = edp_panel_vdd_on(intel_dp);
2504         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2505              port_name(dp_to_dig_port(intel_dp)->base.port));
2506 }
2507
2508 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2509 {
2510         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2511         struct intel_digital_port *intel_dig_port =
2512                 dp_to_dig_port(intel_dp);
2513         u32 pp;
2514         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2515
2516         lockdep_assert_held(&dev_priv->pps_mutex);
2517
2518         WARN_ON(intel_dp->want_panel_vdd);
2519
2520         if (!edp_have_panel_vdd(intel_dp))
2521                 return;
2522
2523         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2524                       port_name(intel_dig_port->base.port));
2525
2526         pp = ironlake_get_pp_control(intel_dp);
2527         pp &= ~EDP_FORCE_VDD;
2528
2529         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2530         pp_stat_reg = _pp_stat_reg(intel_dp);
2531
2532         I915_WRITE(pp_ctrl_reg, pp);
2533         POSTING_READ(pp_ctrl_reg);
2534
2535         /* Make sure sequencer is idle before allowing subsequent activity */
2536         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2537         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2538
2539         if ((pp & PANEL_POWER_ON) == 0)
2540                 intel_dp->panel_power_off_time = ktime_get_boottime();
2541
2542         intel_display_power_put_unchecked(dev_priv,
2543                                           intel_aux_power_domain(intel_dig_port));
2544 }
2545
2546 static void edp_panel_vdd_work(struct work_struct *__work)
2547 {
2548         struct intel_dp *intel_dp =
2549                 container_of(to_delayed_work(__work),
2550                              struct intel_dp, panel_vdd_work);
2551         intel_wakeref_t wakeref;
2552
2553         with_pps_lock(intel_dp, wakeref) {
2554                 if (!intel_dp->want_panel_vdd)
2555                         edp_panel_vdd_off_sync(intel_dp);
2556         }
2557 }
2558
2559 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2560 {
2561         unsigned long delay;
2562
2563         /*
2564          * Queue the timer to fire a long time from now (relative to the power
2565          * down delay) to keep the panel power up across a sequence of
2566          * operations.
2567          */
2568         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2569         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2570 }
2571
2572 /*
2573  * Must be paired with edp_panel_vdd_on().
2574  * Must hold pps_mutex around the whole on/off sequence.
2575  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2576  */
2577 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2578 {
2579         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2580
2581         lockdep_assert_held(&dev_priv->pps_mutex);
2582
2583         if (!intel_dp_is_edp(intel_dp))
2584                 return;
2585
2586         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2587              port_name(dp_to_dig_port(intel_dp)->base.port));
2588
2589         intel_dp->want_panel_vdd = false;
2590
2591         if (sync)
2592                 edp_panel_vdd_off_sync(intel_dp);
2593         else
2594                 edp_panel_vdd_schedule_off(intel_dp);
2595 }
2596
2597 static void edp_panel_on(struct intel_dp *intel_dp)
2598 {
2599         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2600         u32 pp;
2601         i915_reg_t pp_ctrl_reg;
2602
2603         lockdep_assert_held(&dev_priv->pps_mutex);
2604
2605         if (!intel_dp_is_edp(intel_dp))
2606                 return;
2607
2608         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2609                       port_name(dp_to_dig_port(intel_dp)->base.port));
2610
2611         if (WARN(edp_have_panel_power(intel_dp),
2612                  "eDP port %c panel power already on\n",
2613                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2614                 return;
2615
2616         wait_panel_power_cycle(intel_dp);
2617
2618         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2619         pp = ironlake_get_pp_control(intel_dp);
2620         if (IS_GEN(dev_priv, 5)) {
2621                 /* ILK workaround: disable reset around power sequence */
2622                 pp &= ~PANEL_POWER_RESET;
2623                 I915_WRITE(pp_ctrl_reg, pp);
2624                 POSTING_READ(pp_ctrl_reg);
2625         }
2626
2627         pp |= PANEL_POWER_ON;
2628         if (!IS_GEN(dev_priv, 5))
2629                 pp |= PANEL_POWER_RESET;
2630
2631         I915_WRITE(pp_ctrl_reg, pp);
2632         POSTING_READ(pp_ctrl_reg);
2633
2634         wait_panel_on(intel_dp);
2635         intel_dp->last_power_on = jiffies;
2636
2637         if (IS_GEN(dev_priv, 5)) {
2638                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2639                 I915_WRITE(pp_ctrl_reg, pp);
2640                 POSTING_READ(pp_ctrl_reg);
2641         }
2642 }
2643
2644 void intel_edp_panel_on(struct intel_dp *intel_dp)
2645 {
2646         intel_wakeref_t wakeref;
2647
2648         if (!intel_dp_is_edp(intel_dp))
2649                 return;
2650
2651         with_pps_lock(intel_dp, wakeref)
2652                 edp_panel_on(intel_dp);
2653 }
2654
2655
2656 static void edp_panel_off(struct intel_dp *intel_dp)
2657 {
2658         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2659         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2660         u32 pp;
2661         i915_reg_t pp_ctrl_reg;
2662
2663         lockdep_assert_held(&dev_priv->pps_mutex);
2664
2665         if (!intel_dp_is_edp(intel_dp))
2666                 return;
2667
2668         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2669                       port_name(dig_port->base.port));
2670
2671         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2672              port_name(dig_port->base.port));
2673
2674         pp = ironlake_get_pp_control(intel_dp);
2675         /* We need to switch off panel power _and_ force vdd, for otherwise some
2676          * panels get very unhappy and cease to work. */
2677         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2678                 EDP_BLC_ENABLE);
2679
2680         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2681
2682         intel_dp->want_panel_vdd = false;
2683
2684         I915_WRITE(pp_ctrl_reg, pp);
2685         POSTING_READ(pp_ctrl_reg);
2686
2687         wait_panel_off(intel_dp);
2688         intel_dp->panel_power_off_time = ktime_get_boottime();
2689
2690         /* We got a reference when we enabled the VDD. */
2691         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
2692 }
2693
2694 void intel_edp_panel_off(struct intel_dp *intel_dp)
2695 {
2696         intel_wakeref_t wakeref;
2697
2698         if (!intel_dp_is_edp(intel_dp))
2699                 return;
2700
2701         with_pps_lock(intel_dp, wakeref)
2702                 edp_panel_off(intel_dp);
2703 }
2704
2705 /* Enable backlight in the panel power control. */
2706 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2707 {
2708         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2709         intel_wakeref_t wakeref;
2710
2711         /*
2712          * If we enable the backlight right away following a panel power
2713          * on, we may see slight flicker as the panel syncs with the eDP
2714          * link.  So delay a bit to make sure the image is solid before
2715          * allowing it to appear.
2716          */
2717         wait_backlight_on(intel_dp);
2718
2719         with_pps_lock(intel_dp, wakeref) {
2720                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2721                 u32 pp;
2722
2723                 pp = ironlake_get_pp_control(intel_dp);
2724                 pp |= EDP_BLC_ENABLE;
2725
2726                 I915_WRITE(pp_ctrl_reg, pp);
2727                 POSTING_READ(pp_ctrl_reg);
2728         }
2729 }
2730
2731 /* Enable backlight PWM and backlight PP control. */
2732 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2733                             const struct drm_connector_state *conn_state)
2734 {
2735         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2736
2737         if (!intel_dp_is_edp(intel_dp))
2738                 return;
2739
2740         DRM_DEBUG_KMS("\n");
2741
2742         intel_panel_enable_backlight(crtc_state, conn_state);
2743         _intel_edp_backlight_on(intel_dp);
2744 }
2745
2746 /* Disable backlight in the panel power control. */
2747 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2748 {
2749         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2750         intel_wakeref_t wakeref;
2751
2752         if (!intel_dp_is_edp(intel_dp))
2753                 return;
2754
2755         with_pps_lock(intel_dp, wakeref) {
2756                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2757                 u32 pp;
2758
2759                 pp = ironlake_get_pp_control(intel_dp);
2760                 pp &= ~EDP_BLC_ENABLE;
2761
2762                 I915_WRITE(pp_ctrl_reg, pp);
2763                 POSTING_READ(pp_ctrl_reg);
2764         }
2765
2766         intel_dp->last_backlight_off = jiffies;
2767         edp_wait_backlight_off(intel_dp);
2768 }
2769
2770 /* Disable backlight PP control and backlight PWM. */
2771 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2772 {
2773         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2774
2775         if (!intel_dp_is_edp(intel_dp))
2776                 return;
2777
2778         DRM_DEBUG_KMS("\n");
2779
2780         _intel_edp_backlight_off(intel_dp);
2781         intel_panel_disable_backlight(old_conn_state);
2782 }
2783
2784 /*
2785  * Hook for controlling the panel power control backlight through the bl_power
2786  * sysfs attribute. Take care to handle multiple calls.
2787  */
2788 static void intel_edp_backlight_power(struct intel_connector *connector,
2789                                       bool enable)
2790 {
2791         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2792         intel_wakeref_t wakeref;
2793         bool is_enabled;
2794
2795         is_enabled = false;
2796         with_pps_lock(intel_dp, wakeref)
2797                 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2798         if (is_enabled == enable)
2799                 return;
2800
2801         DRM_DEBUG_KMS("panel power control backlight %s\n",
2802                       enable ? "enable" : "disable");
2803
2804         if (enable)
2805                 _intel_edp_backlight_on(intel_dp);
2806         else
2807                 _intel_edp_backlight_off(intel_dp);
2808 }
2809
2810 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2811 {
2812         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2813         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2814         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2815
2816         I915_STATE_WARN(cur_state != state,
2817                         "DP port %c state assertion failure (expected %s, current %s)\n",
2818                         port_name(dig_port->base.port),
2819                         onoff(state), onoff(cur_state));
2820 }
2821 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2822
2823 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2824 {
2825         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2826
2827         I915_STATE_WARN(cur_state != state,
2828                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2829                         onoff(state), onoff(cur_state));
2830 }
2831 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2832 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2833
2834 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2835                                 const struct intel_crtc_state *pipe_config)
2836 {
2837         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2838         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2839
2840         assert_pipe_disabled(dev_priv, crtc->pipe);
2841         assert_dp_port_disabled(intel_dp);
2842         assert_edp_pll_disabled(dev_priv);
2843
2844         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2845                       pipe_config->port_clock);
2846
2847         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2848
2849         if (pipe_config->port_clock == 162000)
2850                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2851         else
2852                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2853
2854         I915_WRITE(DP_A, intel_dp->DP);
2855         POSTING_READ(DP_A);
2856         udelay(500);
2857
2858         /*
2859          * [DevILK] Work around required when enabling DP PLL
2860          * while a pipe is enabled going to FDI:
2861          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2862          * 2. Program DP PLL enable
2863          */
2864         if (IS_GEN(dev_priv, 5))
2865                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2866
2867         intel_dp->DP |= DP_PLL_ENABLE;
2868
2869         I915_WRITE(DP_A, intel_dp->DP);
2870         POSTING_READ(DP_A);
2871         udelay(200);
2872 }
2873
2874 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2875                                  const struct intel_crtc_state *old_crtc_state)
2876 {
2877         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2878         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2879
2880         assert_pipe_disabled(dev_priv, crtc->pipe);
2881         assert_dp_port_disabled(intel_dp);
2882         assert_edp_pll_enabled(dev_priv);
2883
2884         DRM_DEBUG_KMS("disabling eDP PLL\n");
2885
2886         intel_dp->DP &= ~DP_PLL_ENABLE;
2887
2888         I915_WRITE(DP_A, intel_dp->DP);
2889         POSTING_READ(DP_A);
2890         udelay(200);
2891 }
2892
2893 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2894 {
2895         /*
2896          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2897          * be capable of signalling downstream hpd with a long pulse.
2898          * Whether or not that means D3 is safe to use is not clear,
2899          * but let's assume so until proven otherwise.
2900          *
2901          * FIXME should really check all downstream ports...
2902          */
2903         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2904                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2905                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2906 }
2907
2908 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2909                                            const struct intel_crtc_state *crtc_state,
2910                                            bool enable)
2911 {
2912         int ret;
2913
2914         if (!crtc_state->dsc_params.compression_enable)
2915                 return;
2916
2917         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2918                                  enable ? DP_DECOMPRESSION_EN : 0);
2919         if (ret < 0)
2920                 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
2921                               enable ? "enable" : "disable");
2922 }
2923
2924 /* If the sink supports it, try to set the power state appropriately */
2925 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2926 {
2927         int ret, i;
2928
2929         /* Should have a valid DPCD by this point */
2930         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2931                 return;
2932
2933         if (mode != DRM_MODE_DPMS_ON) {
2934                 if (downstream_hpd_needs_d0(intel_dp))
2935                         return;
2936
2937                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2938                                          DP_SET_POWER_D3);
2939         } else {
2940                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2941
2942                 /*
2943                  * When turning on, we need to retry for 1ms to give the sink
2944                  * time to wake up.
2945                  */
2946                 for (i = 0; i < 3; i++) {
2947                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2948                                                  DP_SET_POWER_D0);
2949                         if (ret == 1)
2950                                 break;
2951                         msleep(1);
2952                 }
2953
2954                 if (ret == 1 && lspcon->active)
2955                         lspcon_wait_pcon_mode(lspcon);
2956         }
2957
2958         if (ret != 1)
2959                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2960                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2961 }
2962
2963 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2964                                  enum port port, enum pipe *pipe)
2965 {
2966         enum pipe p;
2967
2968         for_each_pipe(dev_priv, p) {
2969                 u32 val = I915_READ(TRANS_DP_CTL(p));
2970
2971                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2972                         *pipe = p;
2973                         return true;
2974                 }
2975         }
2976
2977         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2978
2979         /* must initialize pipe to something for the asserts */
2980         *pipe = PIPE_A;
2981
2982         return false;
2983 }
2984
2985 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2986                            i915_reg_t dp_reg, enum port port,
2987                            enum pipe *pipe)
2988 {
2989         bool ret;
2990         u32 val;
2991
2992         val = I915_READ(dp_reg);
2993
2994         ret = val & DP_PORT_EN;
2995
2996         /* asserts want to know the pipe even if the port is disabled */
2997         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2998                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2999         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3000                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3001         else if (IS_CHERRYVIEW(dev_priv))
3002                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3003         else
3004                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3005
3006         return ret;
3007 }
3008
3009 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3010                                   enum pipe *pipe)
3011 {
3012         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3013         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3014         intel_wakeref_t wakeref;
3015         bool ret;
3016
3017         wakeref = intel_display_power_get_if_enabled(dev_priv,
3018                                                      encoder->power_domain);
3019         if (!wakeref)
3020                 return false;
3021
3022         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3023                                     encoder->port, pipe);
3024
3025         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3026
3027         return ret;
3028 }
3029
3030 static void intel_dp_get_config(struct intel_encoder *encoder,
3031                                 struct intel_crtc_state *pipe_config)
3032 {
3033         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3034         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3035         u32 tmp, flags = 0;
3036         enum port port = encoder->port;
3037         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3038
3039         if (encoder->type == INTEL_OUTPUT_EDP)
3040                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3041         else
3042                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3043
3044         tmp = I915_READ(intel_dp->output_reg);
3045
3046         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3047
3048         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3049                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3050
3051                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3052                         flags |= DRM_MODE_FLAG_PHSYNC;
3053                 else
3054                         flags |= DRM_MODE_FLAG_NHSYNC;
3055
3056                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3057                         flags |= DRM_MODE_FLAG_PVSYNC;
3058                 else
3059                         flags |= DRM_MODE_FLAG_NVSYNC;
3060         } else {
3061                 if (tmp & DP_SYNC_HS_HIGH)
3062                         flags |= DRM_MODE_FLAG_PHSYNC;
3063                 else
3064                         flags |= DRM_MODE_FLAG_NHSYNC;
3065
3066                 if (tmp & DP_SYNC_VS_HIGH)
3067                         flags |= DRM_MODE_FLAG_PVSYNC;
3068                 else
3069                         flags |= DRM_MODE_FLAG_NVSYNC;
3070         }
3071
3072         pipe_config->base.adjusted_mode.flags |= flags;
3073
3074         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3075                 pipe_config->limited_color_range = true;
3076
3077         pipe_config->lane_count =
3078                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3079
3080         intel_dp_get_m_n(crtc, pipe_config);
3081
3082         if (port == PORT_A) {
3083                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3084                         pipe_config->port_clock = 162000;
3085                 else
3086                         pipe_config->port_clock = 270000;
3087         }
3088
3089         pipe_config->base.adjusted_mode.crtc_clock =
3090                 intel_dotclock_calculate(pipe_config->port_clock,
3091                                          &pipe_config->dp_m_n);
3092
3093         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3094             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3095                 /*
3096                  * This is a big fat ugly hack.
3097                  *
3098                  * Some machines in UEFI boot mode provide us a VBT that has 18
3099                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3100                  * unknown we fail to light up. Yet the same BIOS boots up with
3101                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3102                  * max, not what it tells us to use.
3103                  *
3104                  * Note: This will still be broken if the eDP panel is not lit
3105                  * up by the BIOS, and thus we can't get the mode at module
3106                  * load.
3107                  */
3108                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3109                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3110                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3111         }
3112 }
3113
3114 static void intel_disable_dp(struct intel_encoder *encoder,
3115                              const struct intel_crtc_state *old_crtc_state,
3116                              const struct drm_connector_state *old_conn_state)
3117 {
3118         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3119
3120         intel_dp->link_trained = false;
3121
3122         if (old_crtc_state->has_audio)
3123                 intel_audio_codec_disable(encoder,
3124                                           old_crtc_state, old_conn_state);
3125
3126         /* Make sure the panel is off before trying to change the mode. But also
3127          * ensure that we have vdd while we switch off the panel. */
3128         intel_edp_panel_vdd_on(intel_dp);
3129         intel_edp_backlight_off(old_conn_state);
3130         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3131         intel_edp_panel_off(intel_dp);
3132 }
3133
3134 static void g4x_disable_dp(struct intel_encoder *encoder,
3135                            const struct intel_crtc_state *old_crtc_state,
3136                            const struct drm_connector_state *old_conn_state)
3137 {
3138         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3139 }
3140
3141 static void vlv_disable_dp(struct intel_encoder *encoder,
3142                            const struct intel_crtc_state *old_crtc_state,
3143                            const struct drm_connector_state *old_conn_state)
3144 {
3145         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3146 }
3147
3148 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3149                                 const struct intel_crtc_state *old_crtc_state,
3150                                 const struct drm_connector_state *old_conn_state)
3151 {
3152         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3153         enum port port = encoder->port;
3154
3155         /*
3156          * Bspec does not list a specific disable sequence for g4x DP.
3157          * Follow the ilk+ sequence (disable pipe before the port) for
3158          * g4x DP as it does not suffer from underruns like the normal
3159          * g4x modeset sequence (disable pipe after the port).
3160          */
3161         intel_dp_link_down(encoder, old_crtc_state);
3162
3163         /* Only ilk+ has port A */
3164         if (port == PORT_A)
3165                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3166 }
3167
3168 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3169                                 const struct intel_crtc_state *old_crtc_state,
3170                                 const struct drm_connector_state *old_conn_state)
3171 {
3172         intel_dp_link_down(encoder, old_crtc_state);
3173 }
3174
3175 static void chv_post_disable_dp(struct intel_encoder *encoder,
3176                                 const struct intel_crtc_state *old_crtc_state,
3177                                 const struct drm_connector_state *old_conn_state)
3178 {
3179         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3180
3181         intel_dp_link_down(encoder, old_crtc_state);
3182
3183         mutex_lock(&dev_priv->sb_lock);
3184
3185         /* Assert data lane reset */
3186         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3187
3188         mutex_unlock(&dev_priv->sb_lock);
3189 }
3190
3191 static void
3192 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3193                          u32 *DP,
3194                          u8 dp_train_pat)
3195 {
3196         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3197         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3198         enum port port = intel_dig_port->base.port;
3199         u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3200
3201         if (dp_train_pat & train_pat_mask)
3202                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3203                               dp_train_pat & train_pat_mask);
3204
3205         if (HAS_DDI(dev_priv)) {
3206                 u32 temp = I915_READ(DP_TP_CTL(port));
3207
3208                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3209                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3210                 else
3211                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3212
3213                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3214                 switch (dp_train_pat & train_pat_mask) {
3215                 case DP_TRAINING_PATTERN_DISABLE:
3216                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3217
3218                         break;
3219                 case DP_TRAINING_PATTERN_1:
3220                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3221                         break;
3222                 case DP_TRAINING_PATTERN_2:
3223                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3224                         break;
3225                 case DP_TRAINING_PATTERN_3:
3226                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3227                         break;
3228                 case DP_TRAINING_PATTERN_4:
3229                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3230                         break;
3231                 }
3232                 I915_WRITE(DP_TP_CTL(port), temp);
3233
3234         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3235                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3236                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3237
3238                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3239                 case DP_TRAINING_PATTERN_DISABLE:
3240                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3241                         break;
3242                 case DP_TRAINING_PATTERN_1:
3243                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3244                         break;
3245                 case DP_TRAINING_PATTERN_2:
3246                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3247                         break;
3248                 case DP_TRAINING_PATTERN_3:
3249                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3250                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3251                         break;
3252                 }
3253
3254         } else {
3255                 *DP &= ~DP_LINK_TRAIN_MASK;
3256
3257                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3258                 case DP_TRAINING_PATTERN_DISABLE:
3259                         *DP |= DP_LINK_TRAIN_OFF;
3260                         break;
3261                 case DP_TRAINING_PATTERN_1:
3262                         *DP |= DP_LINK_TRAIN_PAT_1;
3263                         break;
3264                 case DP_TRAINING_PATTERN_2:
3265                         *DP |= DP_LINK_TRAIN_PAT_2;
3266                         break;
3267                 case DP_TRAINING_PATTERN_3:
3268                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3269                         *DP |= DP_LINK_TRAIN_PAT_2;
3270                         break;
3271                 }
3272         }
3273 }
3274
3275 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3276                                  const struct intel_crtc_state *old_crtc_state)
3277 {
3278         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3279
3280         /* enable with pattern 1 (as per spec) */
3281
3282         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3283
3284         /*
3285          * Magic for VLV/CHV. We _must_ first set up the register
3286          * without actually enabling the port, and then do another
3287          * write to enable the port. Otherwise link training will
3288          * fail when the power sequencer is freshly used for this port.
3289          */
3290         intel_dp->DP |= DP_PORT_EN;
3291         if (old_crtc_state->has_audio)
3292                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3293
3294         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3295         POSTING_READ(intel_dp->output_reg);
3296 }
3297
3298 static void intel_enable_dp(struct intel_encoder *encoder,
3299                             const struct intel_crtc_state *pipe_config,
3300                             const struct drm_connector_state *conn_state)
3301 {
3302         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3303         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3304         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3305         u32 dp_reg = I915_READ(intel_dp->output_reg);
3306         enum pipe pipe = crtc->pipe;
3307         intel_wakeref_t wakeref;
3308
3309         if (WARN_ON(dp_reg & DP_PORT_EN))
3310                 return;
3311
3312         with_pps_lock(intel_dp, wakeref) {
3313                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3314                         vlv_init_panel_power_sequencer(encoder, pipe_config);
3315
3316                 intel_dp_enable_port(intel_dp, pipe_config);
3317
3318                 edp_panel_vdd_on(intel_dp);
3319                 edp_panel_on(intel_dp);
3320                 edp_panel_vdd_off(intel_dp, true);
3321         }
3322
3323         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3324                 unsigned int lane_mask = 0x0;
3325
3326                 if (IS_CHERRYVIEW(dev_priv))
3327                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3328
3329                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3330                                     lane_mask);
3331         }
3332
3333         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3334         intel_dp_start_link_train(intel_dp);
3335         intel_dp_stop_link_train(intel_dp);
3336
3337         if (pipe_config->has_audio) {
3338                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3339                                  pipe_name(pipe));
3340                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3341         }
3342 }
3343
3344 static void g4x_enable_dp(struct intel_encoder *encoder,
3345                           const struct intel_crtc_state *pipe_config,
3346                           const struct drm_connector_state *conn_state)
3347 {
3348         intel_enable_dp(encoder, pipe_config, conn_state);
3349         intel_edp_backlight_on(pipe_config, conn_state);
3350 }
3351
3352 static void vlv_enable_dp(struct intel_encoder *encoder,
3353                           const struct intel_crtc_state *pipe_config,
3354                           const struct drm_connector_state *conn_state)
3355 {
3356         intel_edp_backlight_on(pipe_config, conn_state);
3357 }
3358
3359 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3360                               const struct intel_crtc_state *pipe_config,
3361                               const struct drm_connector_state *conn_state)
3362 {
3363         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3364         enum port port = encoder->port;
3365
3366         intel_dp_prepare(encoder, pipe_config);
3367
3368         /* Only ilk+ has port A */
3369         if (port == PORT_A)
3370                 ironlake_edp_pll_on(intel_dp, pipe_config);
3371 }
3372
3373 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3374 {
3375         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3376         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3377         enum pipe pipe = intel_dp->pps_pipe;
3378         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3379
3380         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3381
3382         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3383                 return;
3384
3385         edp_panel_vdd_off_sync(intel_dp);
3386
3387         /*
3388          * VLV seems to get confused when multiple power sequencers
3389          * have the same port selected (even if only one has power/vdd
3390          * enabled). The failure manifests as vlv_wait_port_ready() failing
3391          * CHV on the other hand doesn't seem to mind having the same port
3392          * selected in multiple power sequencers, but let's clear the
3393          * port select always when logically disconnecting a power sequencer
3394          * from a port.
3395          */
3396         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3397                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3398         I915_WRITE(pp_on_reg, 0);
3399         POSTING_READ(pp_on_reg);
3400
3401         intel_dp->pps_pipe = INVALID_PIPE;
3402 }
3403
3404 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3405                                       enum pipe pipe)
3406 {
3407         struct intel_encoder *encoder;
3408
3409         lockdep_assert_held(&dev_priv->pps_mutex);
3410
3411         for_each_intel_dp(&dev_priv->drm, encoder) {
3412                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3413                 enum port port = encoder->port;
3414
3415                 WARN(intel_dp->active_pipe == pipe,
3416                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3417                      pipe_name(pipe), port_name(port));
3418
3419                 if (intel_dp->pps_pipe != pipe)
3420                         continue;
3421
3422                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3423                               pipe_name(pipe), port_name(port));
3424
3425                 /* make sure vdd is off before we steal it */
3426                 vlv_detach_power_sequencer(intel_dp);
3427         }
3428 }
3429
3430 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3431                                            const struct intel_crtc_state *crtc_state)
3432 {
3433         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3434         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3435         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3436
3437         lockdep_assert_held(&dev_priv->pps_mutex);
3438
3439         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3440
3441         if (intel_dp->pps_pipe != INVALID_PIPE &&
3442             intel_dp->pps_pipe != crtc->pipe) {
3443                 /*
3444                  * If another power sequencer was being used on this
3445                  * port previously make sure to turn off vdd there while
3446                  * we still have control of it.
3447                  */
3448                 vlv_detach_power_sequencer(intel_dp);
3449         }
3450
3451         /*
3452          * We may be stealing the power
3453          * sequencer from another port.
3454          */
3455         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3456
3457         intel_dp->active_pipe = crtc->pipe;
3458
3459         if (!intel_dp_is_edp(intel_dp))
3460                 return;
3461
3462         /* now it's all ours */
3463         intel_dp->pps_pipe = crtc->pipe;
3464
3465         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3466                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3467
3468         /* init power sequencer on this pipe and port */
3469         intel_dp_init_panel_power_sequencer(intel_dp);
3470         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3471 }
3472
3473 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3474                               const struct intel_crtc_state *pipe_config,
3475                               const struct drm_connector_state *conn_state)
3476 {
3477         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3478
3479         intel_enable_dp(encoder, pipe_config, conn_state);
3480 }
3481
3482 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3483                                   const struct intel_crtc_state *pipe_config,
3484                                   const struct drm_connector_state *conn_state)
3485 {
3486         intel_dp_prepare(encoder, pipe_config);
3487
3488         vlv_phy_pre_pll_enable(encoder, pipe_config);
3489 }
3490
3491 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3492                               const struct intel_crtc_state *pipe_config,
3493                               const struct drm_connector_state *conn_state)
3494 {
3495         chv_phy_pre_encoder_enable(encoder, pipe_config);
3496
3497         intel_enable_dp(encoder, pipe_config, conn_state);
3498
3499         /* Second common lane will stay alive on its own now */
3500         chv_phy_release_cl2_override(encoder);
3501 }
3502
3503 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3504                                   const struct intel_crtc_state *pipe_config,
3505                                   const struct drm_connector_state *conn_state)
3506 {
3507         intel_dp_prepare(encoder, pipe_config);
3508
3509         chv_phy_pre_pll_enable(encoder, pipe_config);
3510 }
3511
3512 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3513                                     const struct intel_crtc_state *old_crtc_state,
3514                                     const struct drm_connector_state *old_conn_state)
3515 {
3516         chv_phy_post_pll_disable(encoder, old_crtc_state);
3517 }
3518
3519 /*
3520  * Fetch AUX CH registers 0x202 - 0x207 which contain
3521  * link status information
3522  */
3523 bool
3524 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3525 {
3526         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3527                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3528 }
3529
3530 /* These are source-specific values. */
3531 u8
3532 intel_dp_voltage_max(struct intel_dp *intel_dp)
3533 {
3534         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3535         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3536         enum port port = encoder->port;
3537
3538         if (HAS_DDI(dev_priv))
3539                 return intel_ddi_dp_voltage_max(encoder);
3540         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3541                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3542         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3543                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3544         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3545                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3546         else
3547                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3548 }
3549
3550 u8
3551 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
3552 {
3553         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3554         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3555         enum port port = encoder->port;
3556
3557         if (HAS_DDI(dev_priv)) {
3558                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3559         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3560                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3561                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3562                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3563                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3564                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3565                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3566                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3567                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3568                 default:
3569                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3570                 }
3571         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3572                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3573                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3574                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3575                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3576                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3577                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3578                 default:
3579                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3580                 }
3581         } else {
3582                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3583                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3584                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3585                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3586                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3587                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3588                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3589                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3590                 default:
3591                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3592                 }
3593         }
3594 }
3595
3596 static u32 vlv_signal_levels(struct intel_dp *intel_dp)
3597 {
3598         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3599         unsigned long demph_reg_value, preemph_reg_value,
3600                 uniqtranscale_reg_value;
3601         u8 train_set = intel_dp->train_set[0];
3602
3603         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3604         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3605                 preemph_reg_value = 0x0004000;
3606                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3607                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3608                         demph_reg_value = 0x2B405555;
3609                         uniqtranscale_reg_value = 0x552AB83A;
3610                         break;
3611                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3612                         demph_reg_value = 0x2B404040;
3613                         uniqtranscale_reg_value = 0x5548B83A;
3614                         break;
3615                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3616                         demph_reg_value = 0x2B245555;
3617                         uniqtranscale_reg_value = 0x5560B83A;
3618                         break;
3619                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3620                         demph_reg_value = 0x2B405555;
3621                         uniqtranscale_reg_value = 0x5598DA3A;
3622                         break;
3623                 default:
3624                         return 0;
3625                 }
3626                 break;
3627         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3628                 preemph_reg_value = 0x0002000;
3629                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3630                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3631                         demph_reg_value = 0x2B404040;
3632                         uniqtranscale_reg_value = 0x5552B83A;
3633                         break;
3634                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3635                         demph_reg_value = 0x2B404848;
3636                         uniqtranscale_reg_value = 0x5580B83A;
3637                         break;
3638                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3639                         demph_reg_value = 0x2B404040;
3640                         uniqtranscale_reg_value = 0x55ADDA3A;
3641                         break;
3642                 default:
3643                         return 0;
3644                 }
3645                 break;
3646         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3647                 preemph_reg_value = 0x0000000;
3648                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3649                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3650                         demph_reg_value = 0x2B305555;
3651                         uniqtranscale_reg_value = 0x5570B83A;
3652                         break;
3653                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3654                         demph_reg_value = 0x2B2B4040;
3655                         uniqtranscale_reg_value = 0x55ADDA3A;
3656                         break;
3657                 default:
3658                         return 0;
3659                 }
3660                 break;
3661         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3662                 preemph_reg_value = 0x0006000;
3663                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3664                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3665                         demph_reg_value = 0x1B405555;
3666                         uniqtranscale_reg_value = 0x55ADDA3A;
3667                         break;
3668                 default:
3669                         return 0;
3670                 }
3671                 break;
3672         default:
3673                 return 0;
3674         }
3675
3676         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3677                                  uniqtranscale_reg_value, 0);
3678
3679         return 0;
3680 }
3681
3682 static u32 chv_signal_levels(struct intel_dp *intel_dp)
3683 {
3684         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3685         u32 deemph_reg_value, margin_reg_value;
3686         bool uniq_trans_scale = false;
3687         u8 train_set = intel_dp->train_set[0];
3688
3689         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3690         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3691                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3692                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3693                         deemph_reg_value = 128;
3694                         margin_reg_value = 52;
3695                         break;
3696                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3697                         deemph_reg_value = 128;
3698                         margin_reg_value = 77;
3699                         break;
3700                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3701                         deemph_reg_value = 128;
3702                         margin_reg_value = 102;
3703                         break;
3704                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3705                         deemph_reg_value = 128;
3706                         margin_reg_value = 154;
3707                         uniq_trans_scale = true;
3708                         break;
3709                 default:
3710                         return 0;
3711                 }
3712                 break;
3713         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3714                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3715                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3716                         deemph_reg_value = 85;
3717                         margin_reg_value = 78;
3718                         break;
3719                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3720                         deemph_reg_value = 85;
3721                         margin_reg_value = 116;
3722                         break;
3723                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3724                         deemph_reg_value = 85;
3725                         margin_reg_value = 154;
3726                         break;
3727                 default:
3728                         return 0;
3729                 }
3730                 break;
3731         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3732                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3733                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3734                         deemph_reg_value = 64;
3735                         margin_reg_value = 104;
3736                         break;
3737                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3738                         deemph_reg_value = 64;
3739                         margin_reg_value = 154;
3740                         break;
3741                 default:
3742                         return 0;
3743                 }
3744                 break;
3745         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3746                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3747                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3748                         deemph_reg_value = 43;
3749                         margin_reg_value = 154;
3750                         break;
3751                 default:
3752                         return 0;
3753                 }
3754                 break;
3755         default:
3756                 return 0;
3757         }
3758
3759         chv_set_phy_signal_level(encoder, deemph_reg_value,
3760                                  margin_reg_value, uniq_trans_scale);
3761
3762         return 0;
3763 }
3764
3765 static u32
3766 g4x_signal_levels(u8 train_set)
3767 {
3768         u32 signal_levels = 0;
3769
3770         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3771         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3772         default:
3773                 signal_levels |= DP_VOLTAGE_0_4;
3774                 break;
3775         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3776                 signal_levels |= DP_VOLTAGE_0_6;
3777                 break;
3778         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3779                 signal_levels |= DP_VOLTAGE_0_8;
3780                 break;
3781         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3782                 signal_levels |= DP_VOLTAGE_1_2;
3783                 break;
3784         }
3785         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3786         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3787         default:
3788                 signal_levels |= DP_PRE_EMPHASIS_0;
3789                 break;
3790         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3791                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3792                 break;
3793         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3794                 signal_levels |= DP_PRE_EMPHASIS_6;
3795                 break;
3796         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3797                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3798                 break;
3799         }
3800         return signal_levels;
3801 }
3802
3803 /* SNB CPU eDP voltage swing and pre-emphasis control */
3804 static u32
3805 snb_cpu_edp_signal_levels(u8 train_set)
3806 {
3807         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3808                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3809         switch (signal_levels) {
3810         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3811         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3812                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3813         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3814                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3815         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3816         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3817                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3818         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3819         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3820                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3821         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3822         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3823                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3824         default:
3825                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3826                               "0x%x\n", signal_levels);
3827                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3828         }
3829 }
3830
3831 /* IVB CPU eDP voltage swing and pre-emphasis control */
3832 static u32
3833 ivb_cpu_edp_signal_levels(u8 train_set)
3834 {
3835         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3836                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3837         switch (signal_levels) {
3838         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3839                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3840         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3841                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3842         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3843                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3844
3845         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3846                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3847         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3848                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3849
3850         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3851                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3852         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3853                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3854
3855         default:
3856                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3857                               "0x%x\n", signal_levels);
3858                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3859         }
3860 }
3861
3862 void
3863 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3864 {
3865         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3866         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3867         enum port port = intel_dig_port->base.port;
3868         u32 signal_levels, mask = 0;
3869         u8 train_set = intel_dp->train_set[0];
3870
3871         if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
3872                 signal_levels = bxt_signal_levels(intel_dp);
3873         } else if (HAS_DDI(dev_priv)) {
3874                 signal_levels = ddi_signal_levels(intel_dp);
3875                 mask = DDI_BUF_EMP_MASK;
3876         } else if (IS_CHERRYVIEW(dev_priv)) {
3877                 signal_levels = chv_signal_levels(intel_dp);
3878         } else if (IS_VALLEYVIEW(dev_priv)) {
3879                 signal_levels = vlv_signal_levels(intel_dp);
3880         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3881                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3882                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3883         } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
3884                 signal_levels = snb_cpu_edp_signal_levels(train_set);
3885                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3886         } else {
3887                 signal_levels = g4x_signal_levels(train_set);
3888                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3889         }
3890
3891         if (mask)
3892                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3893
3894         DRM_DEBUG_KMS("Using vswing level %d\n",
3895                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3896         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3897                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3898                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3899
3900         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3901
3902         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3903         POSTING_READ(intel_dp->output_reg);
3904 }
3905
3906 void
3907 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3908                                        u8 dp_train_pat)
3909 {
3910         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3911         struct drm_i915_private *dev_priv =
3912                 to_i915(intel_dig_port->base.base.dev);
3913
3914         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3915
3916         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3917         POSTING_READ(intel_dp->output_reg);
3918 }
3919
3920 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3921 {
3922         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3923         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3924         enum port port = intel_dig_port->base.port;
3925         u32 val;
3926
3927         if (!HAS_DDI(dev_priv))
3928                 return;
3929
3930         val = I915_READ(DP_TP_CTL(port));
3931         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3932         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3933         I915_WRITE(DP_TP_CTL(port), val);
3934
3935         /*
3936          * On PORT_A we can have only eDP in SST mode. There the only reason
3937          * we need to set idle transmission mode is to work around a HW issue
3938          * where we enable the pipe while not in idle link-training mode.
3939          * In this case there is requirement to wait for a minimum number of
3940          * idle patterns to be sent.
3941          */
3942         if (port == PORT_A)
3943                 return;
3944
3945         if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
3946                                     DP_TP_STATUS_IDLE_DONE,
3947                                     DP_TP_STATUS_IDLE_DONE,
3948                                     1))
3949                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3950 }
3951
3952 static void
3953 intel_dp_link_down(struct intel_encoder *encoder,
3954                    const struct intel_crtc_state *old_crtc_state)
3955 {
3956         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3957         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3958         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3959         enum port port = encoder->port;
3960         u32 DP = intel_dp->DP;
3961
3962         if (WARN_ON(HAS_DDI(dev_priv)))
3963                 return;
3964
3965         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3966                 return;
3967
3968         DRM_DEBUG_KMS("\n");
3969
3970         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3971             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3972                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3973                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3974         } else {
3975                 DP &= ~DP_LINK_TRAIN_MASK;
3976                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3977         }
3978         I915_WRITE(intel_dp->output_reg, DP);
3979         POSTING_READ(intel_dp->output_reg);
3980
3981         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3982         I915_WRITE(intel_dp->output_reg, DP);
3983         POSTING_READ(intel_dp->output_reg);
3984
3985         /*
3986          * HW workaround for IBX, we need to move the port
3987          * to transcoder A after disabling it to allow the
3988          * matching HDMI port to be enabled on transcoder A.
3989          */
3990         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3991                 /*
3992                  * We get CPU/PCH FIFO underruns on the other pipe when
3993                  * doing the workaround. Sweep them under the rug.
3994                  */
3995                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3996                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3997
3998                 /* always enable with pattern 1 (as per spec) */
3999                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4000                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4001                         DP_LINK_TRAIN_PAT_1;
4002                 I915_WRITE(intel_dp->output_reg, DP);
4003                 POSTING_READ(intel_dp->output_reg);
4004
4005                 DP &= ~DP_PORT_EN;
4006                 I915_WRITE(intel_dp->output_reg, DP);
4007                 POSTING_READ(intel_dp->output_reg);
4008
4009                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4010                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4011                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4012         }
4013
4014         msleep(intel_dp->panel_power_down_delay);
4015
4016         intel_dp->DP = DP;
4017
4018         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4019                 intel_wakeref_t wakeref;
4020
4021                 with_pps_lock(intel_dp, wakeref)
4022                         intel_dp->active_pipe = INVALID_PIPE;
4023         }
4024 }
4025
4026 static void
4027 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4028 {
4029         u8 dpcd_ext[6];
4030
4031         /*
4032          * Prior to DP1.3 the bit represented by
4033          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4034          * if it is set DP_DPCD_REV at 0000h could be at a value less than
4035          * the true capability of the panel. The only way to check is to
4036          * then compare 0000h and 2200h.
4037          */
4038         if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4039               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4040                 return;
4041
4042         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4043                              &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4044                 DRM_ERROR("DPCD failed read at extended capabilities\n");
4045                 return;
4046         }
4047
4048         if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4049                 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n");
4050                 return;
4051         }
4052
4053         if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4054                 return;
4055
4056         DRM_DEBUG_KMS("Base DPCD: %*ph\n",
4057                       (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4058
4059         memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4060 }
4061
4062 bool
4063 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4064 {
4065         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4066                              sizeof(intel_dp->dpcd)) < 0)
4067                 return false; /* aux transfer failed */
4068
4069         intel_dp_extended_receiver_capabilities(intel_dp);
4070
4071         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4072
4073         return intel_dp->dpcd[DP_DPCD_REV] != 0;
4074 }
4075
4076 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4077 {
4078         /*
4079          * Clear the cached register set to avoid using stale values
4080          * for the sinks that do not support DSC.
4081          */
4082         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4083
4084         /* Clear fec_capable to avoid using stale values */
4085         intel_dp->fec_capable = 0;
4086
4087         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4088         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4089             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4090                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4091                                      intel_dp->dsc_dpcd,
4092                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4093                         DRM_ERROR("Failed to read DPCD register 0x%x\n",
4094                                   DP_DSC_SUPPORT);
4095
4096                 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4097                               (int)sizeof(intel_dp->dsc_dpcd),
4098                               intel_dp->dsc_dpcd);
4099
4100                 /* FEC is supported only on DP 1.4 */
4101                 if (!intel_dp_is_edp(intel_dp) &&
4102                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4103                                       &intel_dp->fec_capable) < 0)
4104                         DRM_ERROR("Failed to read FEC DPCD register\n");
4105
4106                 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4107         }
4108 }
4109
4110 static bool
4111 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4112 {
4113         struct drm_i915_private *dev_priv =
4114                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4115
4116         /* this function is meant to be called only once */
4117         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4118
4119         if (!intel_dp_read_dpcd(intel_dp))
4120                 return false;
4121
4122         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4123                          drm_dp_is_branch(intel_dp->dpcd));
4124
4125         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4126                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4127                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4128
4129         /*
4130          * Read the eDP display control registers.
4131          *
4132          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4133          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4134          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4135          * method). The display control registers should read zero if they're
4136          * not supported anyway.
4137          */
4138         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4139                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4140                              sizeof(intel_dp->edp_dpcd))
4141                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
4142                               intel_dp->edp_dpcd);
4143
4144         /*
4145          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4146          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4147          */
4148         intel_psr_init_dpcd(intel_dp);
4149
4150         /* Read the eDP 1.4+ supported link rates. */
4151         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4152                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4153                 int i;
4154
4155                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4156                                 sink_rates, sizeof(sink_rates));
4157
4158                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4159                         int val = le16_to_cpu(sink_rates[i]);
4160
4161                         if (val == 0)
4162                                 break;
4163
4164                         /* Value read multiplied by 200kHz gives the per-lane
4165                          * link rate in kHz. The source rates are, however,
4166                          * stored in terms of LS_Clk kHz. The full conversion
4167                          * back to symbols is
4168                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4169                          */
4170                         intel_dp->sink_rates[i] = (val * 200) / 10;
4171                 }
4172                 intel_dp->num_sink_rates = i;
4173         }
4174
4175         /*
4176          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4177          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4178          */
4179         if (intel_dp->num_sink_rates)
4180                 intel_dp->use_rate_select = true;
4181         else
4182                 intel_dp_set_sink_rates(intel_dp);
4183
4184         intel_dp_set_common_rates(intel_dp);
4185
4186         /* Read the eDP DSC DPCD registers */
4187         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4188                 intel_dp_get_dsc_sink_cap(intel_dp);
4189
4190         return true;
4191 }
4192
4193
4194 static bool
4195 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4196 {
4197         if (!intel_dp_read_dpcd(intel_dp))
4198                 return false;
4199
4200         /* Don't clobber cached eDP rates. */
4201         if (!intel_dp_is_edp(intel_dp)) {
4202                 intel_dp_set_sink_rates(intel_dp);
4203                 intel_dp_set_common_rates(intel_dp);
4204         }
4205
4206         /*
4207          * Some eDP panels do not set a valid value for sink count, that is why
4208          * it don't care about read it here and in intel_edp_init_dpcd().
4209          */
4210         if (!intel_dp_is_edp(intel_dp)) {
4211                 u8 count;
4212                 ssize_t r;
4213
4214                 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4215                 if (r < 1)
4216                         return false;
4217
4218                 /*
4219                  * Sink count can change between short pulse hpd hence
4220                  * a member variable in intel_dp will track any changes
4221                  * between short pulse interrupts.
4222                  */
4223                 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4224
4225                 /*
4226                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4227                  * a dongle is present but no display. Unless we require to know
4228                  * if a dongle is present or not, we don't need to update
4229                  * downstream port information. So, an early return here saves
4230                  * time from performing other operations which are not required.
4231                  */
4232                 if (!intel_dp->sink_count)
4233                         return false;
4234         }
4235
4236         if (!drm_dp_is_branch(intel_dp->dpcd))
4237                 return true; /* native DP sink */
4238
4239         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4240                 return true; /* no per-port downstream info */
4241
4242         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4243                              intel_dp->downstream_ports,
4244                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4245                 return false; /* downstream port status fetch failed */
4246
4247         return true;
4248 }
4249
4250 static bool
4251 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4252 {
4253         u8 mstm_cap;
4254
4255         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4256                 return false;
4257
4258         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4259                 return false;
4260
4261         return mstm_cap & DP_MST_CAP;
4262 }
4263
4264 static bool
4265 intel_dp_can_mst(struct intel_dp *intel_dp)
4266 {
4267         return i915_modparams.enable_dp_mst &&
4268                 intel_dp->can_mst &&
4269                 intel_dp_sink_can_mst(intel_dp);
4270 }
4271
4272 static void
4273 intel_dp_configure_mst(struct intel_dp *intel_dp)
4274 {
4275         struct intel_encoder *encoder =
4276                 &dp_to_dig_port(intel_dp)->base;
4277         bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4278
4279         DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
4280                       port_name(encoder->port), yesno(intel_dp->can_mst),
4281                       yesno(sink_can_mst), yesno(i915_modparams.enable_dp_mst));
4282
4283         if (!intel_dp->can_mst)
4284                 return;
4285
4286         intel_dp->is_mst = sink_can_mst &&
4287                 i915_modparams.enable_dp_mst;
4288
4289         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4290                                         intel_dp->is_mst);
4291 }
4292
4293 static bool
4294 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4295 {
4296         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4297                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4298                 DP_DPRX_ESI_LEN;
4299 }
4300
4301 u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
4302                                 int mode_clock, int mode_hdisplay)
4303 {
4304         u16 bits_per_pixel, max_bpp_small_joiner_ram;
4305         int i;
4306
4307         /*
4308          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
4309          * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
4310          * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
4311          * for MST -> TimeSlotsPerMTP has to be calculated
4312          */
4313         bits_per_pixel = (link_clock * lane_count * 8 *
4314                           DP_DSC_FEC_OVERHEAD_FACTOR) /
4315                 mode_clock;
4316
4317         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
4318         max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
4319                 mode_hdisplay;
4320
4321         /*
4322          * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
4323          * check, output bpp from small joiner RAM check)
4324          */
4325         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
4326
4327         /* Error out if the max bpp is less than smallest allowed valid bpp */
4328         if (bits_per_pixel < valid_dsc_bpp[0]) {
4329                 DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
4330                 return 0;
4331         }
4332
4333         /* Find the nearest match in the array of known BPPs from VESA */
4334         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
4335                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
4336                         break;
4337         }
4338         bits_per_pixel = valid_dsc_bpp[i];
4339
4340         /*
4341          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
4342          * fractional part is 0
4343          */
4344         return bits_per_pixel << 4;
4345 }
4346
4347 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
4348                                 int mode_clock,
4349                                 int mode_hdisplay)
4350 {
4351         u8 min_slice_count, i;
4352         int max_slice_width;
4353
4354         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
4355                 min_slice_count = DIV_ROUND_UP(mode_clock,
4356                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
4357         else
4358                 min_slice_count = DIV_ROUND_UP(mode_clock,
4359                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
4360
4361         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
4362         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
4363                 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
4364                               max_slice_width);
4365                 return 0;
4366         }
4367         /* Also take into account max slice width */
4368         min_slice_count = min_t(u8, min_slice_count,
4369                                 DIV_ROUND_UP(mode_hdisplay,
4370                                              max_slice_width));
4371
4372         /* Find the closest match to the valid slice count values */
4373         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
4374                 if (valid_dsc_slicecount[i] >
4375                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
4376                                                     false))
4377                         break;
4378                 if (min_slice_count  <= valid_dsc_slicecount[i])
4379                         return valid_dsc_slicecount[i];
4380         }
4381
4382         DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
4383         return 0;
4384 }
4385
4386 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4387 {
4388         int status = 0;
4389         int test_link_rate;
4390         u8 test_lane_count, test_link_bw;
4391         /* (DP CTS 1.2)
4392          * 4.3.1.11
4393          */
4394         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4395         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4396                                    &test_lane_count);
4397
4398         if (status <= 0) {
4399                 DRM_DEBUG_KMS("Lane count read failed\n");
4400                 return DP_TEST_NAK;
4401         }
4402         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4403
4404         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4405                                    &test_link_bw);
4406         if (status <= 0) {
4407                 DRM_DEBUG_KMS("Link Rate read failed\n");
4408                 return DP_TEST_NAK;
4409         }
4410         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4411
4412         /* Validate the requested link rate and lane count */
4413         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4414                                         test_lane_count))
4415                 return DP_TEST_NAK;
4416
4417         intel_dp->compliance.test_lane_count = test_lane_count;
4418         intel_dp->compliance.test_link_rate = test_link_rate;
4419
4420         return DP_TEST_ACK;
4421 }
4422
4423 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4424 {
4425         u8 test_pattern;
4426         u8 test_misc;
4427         __be16 h_width, v_height;
4428         int status = 0;
4429
4430         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4431         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4432                                    &test_pattern);
4433         if (status <= 0) {
4434                 DRM_DEBUG_KMS("Test pattern read failed\n");
4435                 return DP_TEST_NAK;
4436         }
4437         if (test_pattern != DP_COLOR_RAMP)
4438                 return DP_TEST_NAK;
4439
4440         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4441                                   &h_width, 2);
4442         if (status <= 0) {
4443                 DRM_DEBUG_KMS("H Width read failed\n");
4444                 return DP_TEST_NAK;
4445         }
4446
4447         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4448                                   &v_height, 2);
4449         if (status <= 0) {
4450                 DRM_DEBUG_KMS("V Height read failed\n");
4451                 return DP_TEST_NAK;
4452         }
4453
4454         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4455                                    &test_misc);
4456         if (status <= 0) {
4457                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4458                 return DP_TEST_NAK;
4459         }
4460         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4461                 return DP_TEST_NAK;
4462         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4463                 return DP_TEST_NAK;
4464         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4465         case DP_TEST_BIT_DEPTH_6:
4466                 intel_dp->compliance.test_data.bpc = 6;
4467                 break;
4468         case DP_TEST_BIT_DEPTH_8:
4469                 intel_dp->compliance.test_data.bpc = 8;
4470                 break;
4471         default:
4472                 return DP_TEST_NAK;
4473         }
4474
4475         intel_dp->compliance.test_data.video_pattern = test_pattern;
4476         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4477         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4478         /* Set test active flag here so userspace doesn't interrupt things */
4479         intel_dp->compliance.test_active = 1;
4480
4481         return DP_TEST_ACK;
4482 }
4483
4484 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4485 {
4486         u8 test_result = DP_TEST_ACK;
4487         struct intel_connector *intel_connector = intel_dp->attached_connector;
4488         struct drm_connector *connector = &intel_connector->base;
4489
4490         if (intel_connector->detect_edid == NULL ||
4491             connector->edid_corrupt ||
4492             intel_dp->aux.i2c_defer_count > 6) {
4493                 /* Check EDID read for NACKs, DEFERs and corruption
4494                  * (DP CTS 1.2 Core r1.1)
4495                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4496                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4497                  *    4.2.2.6 : EDID corruption detected
4498                  * Use failsafe mode for all cases
4499                  */
4500                 if (intel_dp->aux.i2c_nack_count > 0 ||
4501                         intel_dp->aux.i2c_defer_count > 0)
4502                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4503                                       intel_dp->aux.i2c_nack_count,
4504                                       intel_dp->aux.i2c_defer_count);
4505                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4506         } else {
4507                 struct edid *block = intel_connector->detect_edid;
4508
4509                 /* We have to write the checksum
4510                  * of the last block read
4511                  */
4512                 block += intel_connector->detect_edid->extensions;
4513
4514                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4515                                        block->checksum) <= 0)
4516                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4517
4518                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4519                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4520         }
4521
4522         /* Set test active flag here so userspace doesn't interrupt things */
4523         intel_dp->compliance.test_active = 1;
4524
4525         return test_result;
4526 }
4527
4528 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4529 {
4530         u8 test_result = DP_TEST_NAK;
4531         return test_result;
4532 }
4533
4534 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4535 {
4536         u8 response = DP_TEST_NAK;
4537         u8 request = 0;
4538         int status;
4539
4540         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4541         if (status <= 0) {
4542                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4543                 goto update_status;
4544         }
4545
4546         switch (request) {
4547         case DP_TEST_LINK_TRAINING:
4548                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4549                 response = intel_dp_autotest_link_training(intel_dp);
4550                 break;
4551         case DP_TEST_LINK_VIDEO_PATTERN:
4552                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4553                 response = intel_dp_autotest_video_pattern(intel_dp);
4554                 break;
4555         case DP_TEST_LINK_EDID_READ:
4556                 DRM_DEBUG_KMS("EDID test requested\n");
4557                 response = intel_dp_autotest_edid(intel_dp);
4558                 break;
4559         case DP_TEST_LINK_PHY_TEST_PATTERN:
4560                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4561                 response = intel_dp_autotest_phy_pattern(intel_dp);
4562                 break;
4563         default:
4564                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4565                 break;
4566         }
4567
4568         if (response & DP_TEST_ACK)
4569                 intel_dp->compliance.test_type = request;
4570
4571 update_status:
4572         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4573         if (status <= 0)
4574                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4575 }
4576
4577 static int
4578 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4579 {
4580         bool bret;
4581
4582         if (intel_dp->is_mst) {
4583                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4584                 int ret = 0;
4585                 int retry;
4586                 bool handled;
4587
4588                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4589                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4590 go_again:
4591                 if (bret == true) {
4592
4593                         /* check link status - esi[10] = 0x200c */
4594                         if (intel_dp->active_mst_links > 0 &&
4595                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4596                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4597                                 intel_dp_start_link_train(intel_dp);
4598                                 intel_dp_stop_link_train(intel_dp);
4599                         }
4600
4601                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4602                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4603
4604                         if (handled) {
4605                                 for (retry = 0; retry < 3; retry++) {
4606                                         int wret;
4607                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4608                                                                  DP_SINK_COUNT_ESI+1,
4609                                                                  &esi[1], 3);
4610                                         if (wret == 3) {
4611                                                 break;
4612                                         }
4613                                 }
4614
4615                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4616                                 if (bret == true) {
4617                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4618                                         goto go_again;
4619                                 }
4620                         } else
4621                                 ret = 0;
4622
4623                         return ret;
4624                 } else {
4625                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4626                         intel_dp->is_mst = false;
4627                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4628                                                         intel_dp->is_mst);
4629                 }
4630         }
4631         return -EINVAL;
4632 }
4633
4634 static bool
4635 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4636 {
4637         u8 link_status[DP_LINK_STATUS_SIZE];
4638
4639         if (!intel_dp->link_trained)
4640                 return false;
4641
4642         /*
4643          * While PSR source HW is enabled, it will control main-link sending
4644          * frames, enabling and disabling it so trying to do a retrain will fail
4645          * as the link would or not be on or it could mix training patterns
4646          * and frame data at the same time causing retrain to fail.
4647          * Also when exiting PSR, HW will retrain the link anyways fixing
4648          * any link status error.
4649          */
4650         if (intel_psr_enabled(intel_dp))
4651                 return false;
4652
4653         if (!intel_dp_get_link_status(intel_dp, link_status))
4654                 return false;
4655
4656         /*
4657          * Validate the cached values of intel_dp->link_rate and
4658          * intel_dp->lane_count before attempting to retrain.
4659          */
4660         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4661                                         intel_dp->lane_count))
4662                 return false;
4663
4664         /* Retrain if Channel EQ or CR not ok */
4665         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4666 }
4667
4668 int intel_dp_retrain_link(struct intel_encoder *encoder,
4669                           struct drm_modeset_acquire_ctx *ctx)
4670 {
4671         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4672         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4673         struct intel_connector *connector = intel_dp->attached_connector;
4674         struct drm_connector_state *conn_state;
4675         struct intel_crtc_state *crtc_state;
4676         struct intel_crtc *crtc;
4677         int ret;
4678
4679         /* FIXME handle the MST connectors as well */
4680
4681         if (!connector || connector->base.status != connector_status_connected)
4682                 return 0;
4683
4684         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4685                                ctx);
4686         if (ret)
4687                 return ret;
4688
4689         conn_state = connector->base.state;
4690
4691         crtc = to_intel_crtc(conn_state->crtc);
4692         if (!crtc)
4693                 return 0;
4694
4695         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4696         if (ret)
4697                 return ret;
4698
4699         crtc_state = to_intel_crtc_state(crtc->base.state);
4700
4701         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4702
4703         if (!crtc_state->base.active)
4704                 return 0;
4705
4706         if (conn_state->commit &&
4707             !try_wait_for_completion(&conn_state->commit->hw_done))
4708                 return 0;
4709
4710         if (!intel_dp_needs_link_retrain(intel_dp))
4711                 return 0;
4712
4713         /* Suppress underruns caused by re-training */
4714         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4715         if (crtc_state->has_pch_encoder)
4716                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4717                                                       intel_crtc_pch_transcoder(crtc), false);
4718
4719         intel_dp_start_link_train(intel_dp);
4720         intel_dp_stop_link_train(intel_dp);
4721
4722         /* Keep underrun reporting disabled until things are stable */
4723         intel_wait_for_vblank(dev_priv, crtc->pipe);
4724
4725         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4726         if (crtc_state->has_pch_encoder)
4727                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4728                                                       intel_crtc_pch_transcoder(crtc), true);
4729
4730         return 0;
4731 }
4732
4733 /*
4734  * If display is now connected check links status,
4735  * there has been known issues of link loss triggering
4736  * long pulse.
4737  *
4738  * Some sinks (eg. ASUS PB287Q) seem to perform some
4739  * weird HPD ping pong during modesets. So we can apparently
4740  * end up with HPD going low during a modeset, and then
4741  * going back up soon after. And once that happens we must
4742  * retrain the link to get a picture. That's in case no
4743  * userspace component reacted to intermittent HPD dip.
4744  */
4745 static bool intel_dp_hotplug(struct intel_encoder *encoder,
4746                              struct intel_connector *connector)
4747 {
4748         struct drm_modeset_acquire_ctx ctx;
4749         bool changed;
4750         int ret;
4751
4752         changed = intel_encoder_hotplug(encoder, connector);
4753
4754         drm_modeset_acquire_init(&ctx, 0);
4755
4756         for (;;) {
4757                 ret = intel_dp_retrain_link(encoder, &ctx);
4758
4759                 if (ret == -EDEADLK) {
4760                         drm_modeset_backoff(&ctx);
4761                         continue;
4762                 }
4763
4764                 break;
4765         }
4766
4767         drm_modeset_drop_locks(&ctx);
4768         drm_modeset_acquire_fini(&ctx);
4769         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4770
4771         return changed;
4772 }
4773
4774 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
4775 {
4776         u8 val;
4777
4778         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4779                 return;
4780
4781         if (drm_dp_dpcd_readb(&intel_dp->aux,
4782                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4783                 return;
4784
4785         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4786
4787         if (val & DP_AUTOMATED_TEST_REQUEST)
4788                 intel_dp_handle_test_request(intel_dp);
4789
4790         if (val & DP_CP_IRQ)
4791                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4792
4793         if (val & DP_SINK_SPECIFIC_IRQ)
4794                 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
4795 }
4796
4797 /*
4798  * According to DP spec
4799  * 5.1.2:
4800  *  1. Read DPCD
4801  *  2. Configure link according to Receiver Capabilities
4802  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4803  *  4. Check link status on receipt of hot-plug interrupt
4804  *
4805  * intel_dp_short_pulse -  handles short pulse interrupts
4806  * when full detection is not required.
4807  * Returns %true if short pulse is handled and full detection
4808  * is NOT required and %false otherwise.
4809  */
4810 static bool
4811 intel_dp_short_pulse(struct intel_dp *intel_dp)
4812 {
4813         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4814         u8 old_sink_count = intel_dp->sink_count;
4815         bool ret;
4816
4817         /*
4818          * Clearing compliance test variables to allow capturing
4819          * of values for next automated test request.
4820          */
4821         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4822
4823         /*
4824          * Now read the DPCD to see if it's actually running
4825          * If the current value of sink count doesn't match with
4826          * the value that was stored earlier or dpcd read failed
4827          * we need to do full detection
4828          */
4829         ret = intel_dp_get_dpcd(intel_dp);
4830
4831         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4832                 /* No need to proceed if we are going to do full detect */
4833                 return false;
4834         }
4835
4836         intel_dp_check_service_irq(intel_dp);
4837
4838         /* Handle CEC interrupts, if any */
4839         drm_dp_cec_irq(&intel_dp->aux);
4840
4841         /* defer to the hotplug work for link retraining if needed */
4842         if (intel_dp_needs_link_retrain(intel_dp))
4843                 return false;
4844
4845         intel_psr_short_pulse(intel_dp);
4846
4847         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4848                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4849                 /* Send a Hotplug Uevent to userspace to start modeset */
4850                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4851         }
4852
4853         return true;
4854 }
4855
4856 /* XXX this is probably wrong for multiple downstream ports */
4857 static enum drm_connector_status
4858 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4859 {
4860         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4861         u8 *dpcd = intel_dp->dpcd;
4862         u8 type;
4863
4864         if (lspcon->active)
4865                 lspcon_resume(lspcon);
4866
4867         if (!intel_dp_get_dpcd(intel_dp))
4868                 return connector_status_disconnected;
4869
4870         if (intel_dp_is_edp(intel_dp))
4871                 return connector_status_connected;
4872
4873         /* if there's no downstream port, we're done */
4874         if (!drm_dp_is_branch(dpcd))
4875                 return connector_status_connected;
4876
4877         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4878         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4879             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4880
4881                 return intel_dp->sink_count ?
4882                 connector_status_connected : connector_status_disconnected;
4883         }
4884
4885         if (intel_dp_can_mst(intel_dp))
4886                 return connector_status_connected;
4887
4888         /* If no HPD, poke DDC gently */
4889         if (drm_probe_ddc(&intel_dp->aux.ddc))
4890                 return connector_status_connected;
4891
4892         /* Well we tried, say unknown for unreliable port types */
4893         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4894                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4895                 if (type == DP_DS_PORT_TYPE_VGA ||
4896                     type == DP_DS_PORT_TYPE_NON_EDID)
4897                         return connector_status_unknown;
4898         } else {
4899                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4900                         DP_DWN_STRM_PORT_TYPE_MASK;
4901                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4902                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4903                         return connector_status_unknown;
4904         }
4905
4906         /* Anything else is out of spec, warn and ignore */
4907         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4908         return connector_status_disconnected;
4909 }
4910
4911 static enum drm_connector_status
4912 edp_detect(struct intel_dp *intel_dp)
4913 {
4914         return connector_status_connected;
4915 }
4916
4917 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4918 {
4919         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4920         u32 bit;
4921
4922         switch (encoder->hpd_pin) {
4923         case HPD_PORT_B:
4924                 bit = SDE_PORTB_HOTPLUG;
4925                 break;
4926         case HPD_PORT_C:
4927                 bit = SDE_PORTC_HOTPLUG;
4928                 break;
4929         case HPD_PORT_D:
4930                 bit = SDE_PORTD_HOTPLUG;
4931                 break;
4932         default:
4933                 MISSING_CASE(encoder->hpd_pin);
4934                 return false;
4935         }
4936
4937         return I915_READ(SDEISR) & bit;
4938 }
4939
4940 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4941 {
4942         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4943         u32 bit;
4944
4945         switch (encoder->hpd_pin) {
4946         case HPD_PORT_B:
4947                 bit = SDE_PORTB_HOTPLUG_CPT;
4948                 break;
4949         case HPD_PORT_C:
4950                 bit = SDE_PORTC_HOTPLUG_CPT;
4951                 break;
4952         case HPD_PORT_D:
4953                 bit = SDE_PORTD_HOTPLUG_CPT;
4954                 break;
4955         default:
4956                 MISSING_CASE(encoder->hpd_pin);
4957                 return false;
4958         }
4959
4960         return I915_READ(SDEISR) & bit;
4961 }
4962
4963 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4964 {
4965         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4966         u32 bit;
4967
4968         switch (encoder->hpd_pin) {
4969         case HPD_PORT_A:
4970                 bit = SDE_PORTA_HOTPLUG_SPT;
4971                 break;
4972         case HPD_PORT_E:
4973                 bit = SDE_PORTE_HOTPLUG_SPT;
4974                 break;
4975         default:
4976                 return cpt_digital_port_connected(encoder);
4977         }
4978
4979         return I915_READ(SDEISR) & bit;
4980 }
4981
4982 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4983 {
4984         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4985         u32 bit;
4986
4987         switch (encoder->hpd_pin) {
4988         case HPD_PORT_B:
4989                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4990                 break;
4991         case HPD_PORT_C:
4992                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4993                 break;
4994         case HPD_PORT_D:
4995                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4996                 break;
4997         default:
4998                 MISSING_CASE(encoder->hpd_pin);
4999                 return false;
5000         }
5001
5002         return I915_READ(PORT_HOTPLUG_STAT) & bit;
5003 }
5004
5005 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
5006 {
5007         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5008         u32 bit;
5009
5010         switch (encoder->hpd_pin) {
5011         case HPD_PORT_B:
5012                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
5013                 break;
5014         case HPD_PORT_C:
5015                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
5016                 break;
5017         case HPD_PORT_D:
5018                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
5019                 break;
5020         default:
5021                 MISSING_CASE(encoder->hpd_pin);
5022                 return false;
5023         }
5024
5025         return I915_READ(PORT_HOTPLUG_STAT) & bit;
5026 }
5027
5028 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
5029 {
5030         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5031
5032         if (encoder->hpd_pin == HPD_PORT_A)
5033                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5034         else
5035                 return ibx_digital_port_connected(encoder);
5036 }
5037
5038 static bool snb_digital_port_connected(struct intel_encoder *encoder)
5039 {
5040         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5041
5042         if (encoder->hpd_pin == HPD_PORT_A)
5043                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5044         else
5045                 return cpt_digital_port_connected(encoder);
5046 }
5047
5048 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
5049 {
5050         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5051
5052         if (encoder->hpd_pin == HPD_PORT_A)
5053                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
5054         else
5055                 return cpt_digital_port_connected(encoder);
5056 }
5057
5058 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5059 {
5060         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5061
5062         if (encoder->hpd_pin == HPD_PORT_A)
5063                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
5064         else
5065                 return cpt_digital_port_connected(encoder);
5066 }
5067
5068 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5069 {
5070         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5071         u32 bit;
5072
5073         switch (encoder->hpd_pin) {
5074         case HPD_PORT_A:
5075                 bit = BXT_DE_PORT_HP_DDIA;
5076                 break;
5077         case HPD_PORT_B:
5078                 bit = BXT_DE_PORT_HP_DDIB;
5079                 break;
5080         case HPD_PORT_C:
5081                 bit = BXT_DE_PORT_HP_DDIC;
5082                 break;
5083         default:
5084                 MISSING_CASE(encoder->hpd_pin);
5085                 return false;
5086         }
5087
5088         return I915_READ(GEN8_DE_PORT_ISR) & bit;
5089 }
5090
5091 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
5092                                      struct intel_digital_port *intel_dig_port)
5093 {
5094         enum port port = intel_dig_port->base.port;
5095
5096         return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
5097 }
5098
5099 static const char *tc_type_name(enum tc_port_type type)
5100 {
5101         static const char * const names[] = {
5102                 [TC_PORT_UNKNOWN] = "unknown",
5103                 [TC_PORT_LEGACY] = "legacy",
5104                 [TC_PORT_TYPEC] = "typec",
5105                 [TC_PORT_TBT] = "tbt",
5106         };
5107
5108         if (WARN_ON(type >= ARRAY_SIZE(names)))
5109                 type = TC_PORT_UNKNOWN;
5110
5111         return names[type];
5112 }
5113
5114 static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
5115                                     struct intel_digital_port *intel_dig_port,
5116                                     bool is_legacy, bool is_typec, bool is_tbt)
5117 {
5118         enum port port = intel_dig_port->base.port;
5119         enum tc_port_type old_type = intel_dig_port->tc_type;
5120
5121         WARN_ON(is_legacy + is_typec + is_tbt != 1);
5122
5123         if (is_legacy)
5124                 intel_dig_port->tc_type = TC_PORT_LEGACY;
5125         else if (is_typec)
5126                 intel_dig_port->tc_type = TC_PORT_TYPEC;
5127         else if (is_tbt)
5128                 intel_dig_port->tc_type = TC_PORT_TBT;
5129         else
5130                 return;
5131
5132         /* Types are not supposed to be changed at runtime. */
5133         WARN_ON(old_type != TC_PORT_UNKNOWN &&
5134                 old_type != intel_dig_port->tc_type);
5135
5136         if (old_type != intel_dig_port->tc_type)
5137                 DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
5138                               tc_type_name(intel_dig_port->tc_type));
5139 }
5140
5141 /*
5142  * This function implements the first part of the Connect Flow described by our
5143  * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
5144  * lanes, EDID, etc) is done as needed in the typical places.
5145  *
5146  * Unlike the other ports, type-C ports are not available to use as soon as we
5147  * get a hotplug. The type-C PHYs can be shared between multiple controllers:
5148  * display, USB, etc. As a result, handshaking through FIA is required around
5149  * connect and disconnect to cleanly transfer ownership with the controller and
5150  * set the type-C power state.
5151  *
5152  * We could opt to only do the connect flow when we actually try to use the AUX
5153  * channels or do a modeset, then immediately run the disconnect flow after
5154  * usage, but there are some implications on this for a dynamic environment:
5155  * things may go away or change behind our backs. So for now our driver is
5156  * always trying to acquire ownership of the controller as soon as it gets an
5157  * interrupt (or polls state and sees a port is connected) and only gives it
5158  * back when it sees a disconnect. Implementation of a more fine-grained model
5159  * will require a lot of coordination with user space and thorough testing for
5160  * the extra possible cases.
5161  */
5162 static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
5163                                struct intel_digital_port *dig_port)
5164 {
5165         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
5166         u32 val;
5167
5168         if (dig_port->tc_type != TC_PORT_LEGACY &&
5169             dig_port->tc_type != TC_PORT_TYPEC)
5170                 return true;
5171
5172         val = I915_READ(PORT_TX_DFLEXDPPMS);
5173         if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
5174                 DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
5175                 WARN_ON(dig_port->tc_legacy_port);
5176                 return false;
5177         }
5178
5179         /*
5180          * This function may be called many times in a row without an HPD event
5181          * in between, so try to avoid the write when we can.
5182          */
5183         val = I915_READ(PORT_TX_DFLEXDPCSSS);
5184         if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
5185                 val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
5186                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
5187         }
5188
5189         /*
5190          * Now we have to re-check the live state, in case the port recently
5191          * became disconnected. Not necessary for legacy mode.
5192          */
5193         if (dig_port->tc_type == TC_PORT_TYPEC &&
5194             !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
5195                 DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
5196                 icl_tc_phy_disconnect(dev_priv, dig_port);
5197                 return false;
5198         }
5199
5200         return true;
5201 }
5202
5203 /*
5204  * See the comment at the connect function. This implements the Disconnect
5205  * Flow.
5206  */
5207 void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
5208                            struct intel_digital_port *dig_port)
5209 {
5210         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
5211
5212         if (dig_port->tc_type == TC_PORT_UNKNOWN)
5213                 return;
5214
5215         /*
5216          * TBT disconnection flow is read the live status, what was done in
5217          * caller.
5218          */
5219         if (dig_port->tc_type == TC_PORT_TYPEC ||
5220             dig_port->tc_type == TC_PORT_LEGACY) {
5221                 u32 val;
5222
5223                 val = I915_READ(PORT_TX_DFLEXDPCSSS);
5224                 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
5225                 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
5226         }
5227
5228         DRM_DEBUG_KMS("Port %c TC type %s disconnected\n",
5229                       port_name(dig_port->base.port),
5230                       tc_type_name(dig_port->tc_type));
5231
5232         dig_port->tc_type = TC_PORT_UNKNOWN;
5233 }
5234
5235 /*
5236  * The type-C ports are different because even when they are connected, they may
5237  * not be available/usable by the graphics driver: see the comment on
5238  * icl_tc_phy_connect(). So in our driver instead of adding the additional
5239  * concept of "usable" and make everything check for "connected and usable" we
5240  * define a port as "connected" when it is not only connected, but also when it
5241  * is usable by the rest of the driver. That maintains the old assumption that
5242  * connected ports are usable, and avoids exposing to the users objects they
5243  * can't really use.
5244  */
5245 static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
5246                                   struct intel_digital_port *intel_dig_port)
5247 {
5248         enum port port = intel_dig_port->base.port;
5249         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
5250         bool is_legacy, is_typec, is_tbt;
5251         u32 dpsp;
5252
5253         /*
5254          * WARN if we got a legacy port HPD, but VBT didn't mark the port as
5255          * legacy. Treat the port as legacy from now on.
5256          */
5257         if (WARN_ON(!intel_dig_port->tc_legacy_port &&
5258                     I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port)))
5259                 intel_dig_port->tc_legacy_port = true;
5260         is_legacy = intel_dig_port->tc_legacy_port;
5261
5262         /*
5263          * The spec says we shouldn't be using the ISR bits for detecting
5264          * between TC and TBT. We should use DFLEXDPSP.
5265          */
5266         dpsp = I915_READ(PORT_TX_DFLEXDPSP);
5267         is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
5268         is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
5269
5270         if (!is_legacy && !is_typec && !is_tbt) {
5271                 icl_tc_phy_disconnect(dev_priv, intel_dig_port);
5272
5273                 return false;
5274         }
5275
5276         icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
5277                                 is_tbt);
5278
5279         if (!icl_tc_phy_connect(dev_priv, intel_dig_port))
5280                 return false;
5281
5282         return true;
5283 }
5284
5285 static bool icl_digital_port_connected(struct intel_encoder *encoder)
5286 {
5287         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5288         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
5289
5290         if (intel_port_is_combophy(dev_priv, encoder->port))
5291                 return icl_combo_port_connected(dev_priv, dig_port);
5292         else if (intel_port_is_tc(dev_priv, encoder->port))
5293                 return icl_tc_port_connected(dev_priv, dig_port);
5294         else
5295                 MISSING_CASE(encoder->hpd_pin);
5296
5297         return false;
5298 }
5299
5300 /*
5301  * intel_digital_port_connected - is the specified port connected?
5302  * @encoder: intel_encoder
5303  *
5304  * In cases where there's a connector physically connected but it can't be used
5305  * by our hardware we also return false, since the rest of the driver should
5306  * pretty much treat the port as disconnected. This is relevant for type-C
5307  * (starting on ICL) where there's ownership involved.
5308  *
5309  * Return %true if port is connected, %false otherwise.
5310  */
5311 bool intel_digital_port_connected(struct intel_encoder *encoder)
5312 {
5313         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5314
5315         if (HAS_GMCH(dev_priv)) {
5316                 if (IS_GM45(dev_priv))
5317                         return gm45_digital_port_connected(encoder);
5318                 else
5319                         return g4x_digital_port_connected(encoder);
5320         }
5321
5322         if (INTEL_GEN(dev_priv) >= 11)
5323                 return icl_digital_port_connected(encoder);
5324         else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv))
5325                 return spt_digital_port_connected(encoder);
5326         else if (IS_GEN9_LP(dev_priv))
5327                 return bxt_digital_port_connected(encoder);
5328         else if (IS_GEN(dev_priv, 8))
5329                 return bdw_digital_port_connected(encoder);
5330         else if (IS_GEN(dev_priv, 7))
5331                 return ivb_digital_port_connected(encoder);
5332         else if (IS_GEN(dev_priv, 6))
5333                 return snb_digital_port_connected(encoder);
5334         else if (IS_GEN(dev_priv, 5))
5335                 return ilk_digital_port_connected(encoder);
5336
5337         MISSING_CASE(INTEL_GEN(dev_priv));
5338         return false;
5339 }
5340
5341 static struct edid *
5342 intel_dp_get_edid(struct intel_dp *intel_dp)
5343 {
5344         struct intel_connector *intel_connector = intel_dp->attached_connector;
5345
5346         /* use cached edid if we have one */
5347         if (intel_connector->edid) {
5348                 /* invalid edid */
5349                 if (IS_ERR(intel_connector->edid))
5350                         return NULL;
5351
5352                 return drm_edid_duplicate(intel_connector->edid);
5353         } else
5354                 return drm_get_edid(&intel_connector->base,
5355                                     &intel_dp->aux.ddc);
5356 }
5357
5358 static void
5359 intel_dp_set_edid(struct intel_dp *intel_dp)
5360 {
5361         struct intel_connector *intel_connector = intel_dp->attached_connector;
5362         struct edid *edid;
5363
5364         intel_dp_unset_edid(intel_dp);
5365         edid = intel_dp_get_edid(intel_dp);
5366         intel_connector->detect_edid = edid;
5367
5368         intel_dp->has_audio = drm_detect_monitor_audio(edid);
5369         drm_dp_cec_set_edid(&intel_dp->aux, edid);
5370 }
5371
5372 static void
5373 intel_dp_unset_edid(struct intel_dp *intel_dp)
5374 {
5375         struct intel_connector *intel_connector = intel_dp->attached_connector;
5376
5377         drm_dp_cec_unset_edid(&intel_dp->aux);
5378         kfree(intel_connector->detect_edid);
5379         intel_connector->detect_edid = NULL;
5380
5381         intel_dp->has_audio = false;
5382 }
5383
5384 static int
5385 intel_dp_detect(struct drm_connector *connector,
5386                 struct drm_modeset_acquire_ctx *ctx,
5387                 bool force)
5388 {
5389         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5390         struct intel_dp *intel_dp = intel_attached_dp(connector);
5391         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5392         struct intel_encoder *encoder = &dig_port->base;
5393         enum drm_connector_status status;
5394         enum intel_display_power_domain aux_domain =
5395                 intel_aux_power_domain(dig_port);
5396         intel_wakeref_t wakeref;
5397
5398         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5399                       connector->base.id, connector->name);
5400         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5401
5402         wakeref = intel_display_power_get(dev_priv, aux_domain);
5403
5404         /* Can't disconnect eDP */
5405         if (intel_dp_is_edp(intel_dp))
5406                 status = edp_detect(intel_dp);
5407         else if (intel_digital_port_connected(encoder))
5408                 status = intel_dp_detect_dpcd(intel_dp);
5409         else
5410                 status = connector_status_disconnected;
5411
5412         if (status == connector_status_disconnected) {
5413                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5414                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5415
5416                 if (intel_dp->is_mst) {
5417                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5418                                       intel_dp->is_mst,
5419                                       intel_dp->mst_mgr.mst_state);
5420                         intel_dp->is_mst = false;
5421                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5422                                                         intel_dp->is_mst);
5423                 }
5424
5425                 goto out;
5426         }
5427
5428         if (intel_dp->reset_link_params) {
5429                 /* Initial max link lane count */
5430                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5431
5432                 /* Initial max link rate */
5433                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5434
5435                 intel_dp->reset_link_params = false;
5436         }
5437
5438         intel_dp_print_rates(intel_dp);
5439
5440         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5441         if (INTEL_GEN(dev_priv) >= 11)
5442                 intel_dp_get_dsc_sink_cap(intel_dp);
5443
5444         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5445                          drm_dp_is_branch(intel_dp->dpcd));
5446
5447         intel_dp_configure_mst(intel_dp);
5448
5449         if (intel_dp->is_mst) {
5450                 /*
5451                  * If we are in MST mode then this connector
5452                  * won't appear connected or have anything
5453                  * with EDID on it
5454                  */
5455                 status = connector_status_disconnected;
5456                 goto out;
5457         }
5458
5459         /*
5460          * Some external monitors do not signal loss of link synchronization
5461          * with an IRQ_HPD, so force a link status check.
5462          */
5463         if (!intel_dp_is_edp(intel_dp)) {
5464                 int ret;
5465
5466                 ret = intel_dp_retrain_link(encoder, ctx);
5467                 if (ret) {
5468                         intel_display_power_put(dev_priv, aux_domain, wakeref);
5469                         return ret;
5470                 }
5471         }
5472
5473         /*
5474          * Clearing NACK and defer counts to get their exact values
5475          * while reading EDID which are required by Compliance tests
5476          * 4.2.2.4 and 4.2.2.5
5477          */
5478         intel_dp->aux.i2c_nack_count = 0;
5479         intel_dp->aux.i2c_defer_count = 0;
5480
5481         intel_dp_set_edid(intel_dp);
5482         if (intel_dp_is_edp(intel_dp) ||
5483             to_intel_connector(connector)->detect_edid)
5484                 status = connector_status_connected;
5485
5486         intel_dp_check_service_irq(intel_dp);
5487
5488 out:
5489         if (status != connector_status_connected && !intel_dp->is_mst)
5490                 intel_dp_unset_edid(intel_dp);
5491
5492         intel_display_power_put(dev_priv, aux_domain, wakeref);
5493         return status;
5494 }
5495
5496 static void
5497 intel_dp_force(struct drm_connector *connector)
5498 {
5499         struct intel_dp *intel_dp = intel_attached_dp(connector);
5500         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5501         struct intel_encoder *intel_encoder = &dig_port->base;
5502         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5503         enum intel_display_power_domain aux_domain =
5504                 intel_aux_power_domain(dig_port);
5505         intel_wakeref_t wakeref;
5506
5507         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5508                       connector->base.id, connector->name);
5509         intel_dp_unset_edid(intel_dp);
5510
5511         if (connector->status != connector_status_connected)
5512                 return;
5513
5514         wakeref = intel_display_power_get(dev_priv, aux_domain);
5515
5516         intel_dp_set_edid(intel_dp);
5517
5518         intel_display_power_put(dev_priv, aux_domain, wakeref);
5519 }
5520
5521 static int intel_dp_get_modes(struct drm_connector *connector)
5522 {
5523         struct intel_connector *intel_connector = to_intel_connector(connector);
5524         struct edid *edid;
5525
5526         edid = intel_connector->detect_edid;
5527         if (edid) {
5528                 int ret = intel_connector_update_modes(connector, edid);
5529                 if (ret)
5530                         return ret;
5531         }
5532
5533         /* if eDP has no EDID, fall back to fixed mode */
5534         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5535             intel_connector->panel.fixed_mode) {
5536                 struct drm_display_mode *mode;
5537
5538                 mode = drm_mode_duplicate(connector->dev,
5539                                           intel_connector->panel.fixed_mode);
5540                 if (mode) {
5541                         drm_mode_probed_add(connector, mode);
5542                         return 1;
5543                 }
5544         }
5545
5546         return 0;
5547 }
5548
5549 static int
5550 intel_dp_connector_register(struct drm_connector *connector)
5551 {
5552         struct intel_dp *intel_dp = intel_attached_dp(connector);
5553         struct drm_device *dev = connector->dev;
5554         int ret;
5555
5556         ret = intel_connector_register(connector);
5557         if (ret)
5558                 return ret;
5559
5560         i915_debugfs_connector_add(connector);
5561
5562         DRM_DEBUG_KMS("registering %s bus for %s\n",
5563                       intel_dp->aux.name, connector->kdev->kobj.name);
5564
5565         intel_dp->aux.dev = connector->kdev;
5566         ret = drm_dp_aux_register(&intel_dp->aux);
5567         if (!ret)
5568                 drm_dp_cec_register_connector(&intel_dp->aux,
5569                                               connector->name, dev->dev);
5570         return ret;
5571 }
5572
5573 static void
5574 intel_dp_connector_unregister(struct drm_connector *connector)
5575 {
5576         struct intel_dp *intel_dp = intel_attached_dp(connector);
5577
5578         drm_dp_cec_unregister_connector(&intel_dp->aux);
5579         drm_dp_aux_unregister(&intel_dp->aux);
5580         intel_connector_unregister(connector);
5581 }
5582
5583 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5584 {
5585         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5586         struct intel_dp *intel_dp = &intel_dig_port->dp;
5587
5588         intel_dp_mst_encoder_cleanup(intel_dig_port);
5589         if (intel_dp_is_edp(intel_dp)) {
5590                 intel_wakeref_t wakeref;
5591
5592                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5593                 /*
5594                  * vdd might still be enabled do to the delayed vdd off.
5595                  * Make sure vdd is actually turned off here.
5596                  */
5597                 with_pps_lock(intel_dp, wakeref)
5598                         edp_panel_vdd_off_sync(intel_dp);
5599
5600                 if (intel_dp->edp_notifier.notifier_call) {
5601                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5602                         intel_dp->edp_notifier.notifier_call = NULL;
5603                 }
5604         }
5605
5606         intel_dp_aux_fini(intel_dp);
5607 }
5608
5609 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5610 {
5611         intel_dp_encoder_flush_work(encoder);
5612
5613         drm_encoder_cleanup(encoder);
5614         kfree(enc_to_dig_port(encoder));
5615 }
5616
5617 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5618 {
5619         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5620         intel_wakeref_t wakeref;
5621
5622         if (!intel_dp_is_edp(intel_dp))
5623                 return;
5624
5625         /*
5626          * vdd might still be enabled do to the delayed vdd off.
5627          * Make sure vdd is actually turned off here.
5628          */
5629         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5630         with_pps_lock(intel_dp, wakeref)
5631                 edp_panel_vdd_off_sync(intel_dp);
5632 }
5633
5634 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
5635 {
5636         long ret;
5637
5638 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
5639         ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
5640                                                msecs_to_jiffies(timeout));
5641
5642         if (!ret)
5643                 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
5644 }
5645
5646 static
5647 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5648                                 u8 *an)
5649 {
5650         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5651         static const struct drm_dp_aux_msg msg = {
5652                 .request = DP_AUX_NATIVE_WRITE,
5653                 .address = DP_AUX_HDCP_AKSV,
5654                 .size = DRM_HDCP_KSV_LEN,
5655         };
5656         u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5657         ssize_t dpcd_ret;
5658         int ret;
5659
5660         /* Output An first, that's easy */
5661         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5662                                      an, DRM_HDCP_AN_LEN);
5663         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5664                 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5665                               dpcd_ret);
5666                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5667         }
5668
5669         /*
5670          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5671          * order to get it on the wire, we need to create the AUX header as if
5672          * we were writing the data, and then tickle the hardware to output the
5673          * data once the header is sent out.
5674          */
5675         intel_dp_aux_header(txbuf, &msg);
5676
5677         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5678                                 rxbuf, sizeof(rxbuf),
5679                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5680         if (ret < 0) {
5681                 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5682                 return ret;
5683         } else if (ret == 0) {
5684                 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5685                 return -EIO;
5686         }
5687
5688         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5689         if (reply != DP_AUX_NATIVE_REPLY_ACK) {
5690                 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
5691                               reply);
5692                 return -EIO;
5693         }
5694         return 0;
5695 }
5696
5697 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5698                                    u8 *bksv)
5699 {
5700         ssize_t ret;
5701         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5702                                DRM_HDCP_KSV_LEN);
5703         if (ret != DRM_HDCP_KSV_LEN) {
5704                 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5705                 return ret >= 0 ? -EIO : ret;
5706         }
5707         return 0;
5708 }
5709
5710 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5711                                       u8 *bstatus)
5712 {
5713         ssize_t ret;
5714         /*
5715          * For some reason the HDMI and DP HDCP specs call this register
5716          * definition by different names. In the HDMI spec, it's called BSTATUS,
5717          * but in DP it's called BINFO.
5718          */
5719         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5720                                bstatus, DRM_HDCP_BSTATUS_LEN);
5721         if (ret != DRM_HDCP_BSTATUS_LEN) {
5722                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5723                 return ret >= 0 ? -EIO : ret;
5724         }
5725         return 0;
5726 }
5727
5728 static
5729 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5730                              u8 *bcaps)
5731 {
5732         ssize_t ret;
5733
5734         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5735                                bcaps, 1);
5736         if (ret != 1) {
5737                 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
5738                 return ret >= 0 ? -EIO : ret;
5739         }
5740
5741         return 0;
5742 }
5743
5744 static
5745 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5746                                    bool *repeater_present)
5747 {
5748         ssize_t ret;
5749         u8 bcaps;
5750
5751         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5752         if (ret)
5753                 return ret;
5754
5755         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5756         return 0;
5757 }
5758
5759 static
5760 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5761                                 u8 *ri_prime)
5762 {
5763         ssize_t ret;
5764         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5765                                ri_prime, DRM_HDCP_RI_LEN);
5766         if (ret != DRM_HDCP_RI_LEN) {
5767                 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
5768                 return ret >= 0 ? -EIO : ret;
5769         }
5770         return 0;
5771 }
5772
5773 static
5774 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5775                                  bool *ksv_ready)
5776 {
5777         ssize_t ret;
5778         u8 bstatus;
5779         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5780                                &bstatus, 1);
5781         if (ret != 1) {
5782                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5783                 return ret >= 0 ? -EIO : ret;
5784         }
5785         *ksv_ready = bstatus & DP_BSTATUS_READY;
5786         return 0;
5787 }
5788
5789 static
5790 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5791                                 int num_downstream, u8 *ksv_fifo)
5792 {
5793         ssize_t ret;
5794         int i;
5795
5796         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5797         for (i = 0; i < num_downstream; i += 3) {
5798                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5799                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5800                                        DP_AUX_HDCP_KSV_FIFO,
5801                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5802                                        len);
5803                 if (ret != len) {
5804                         DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
5805                                       i, ret);
5806                         return ret >= 0 ? -EIO : ret;
5807                 }
5808         }
5809         return 0;
5810 }
5811
5812 static
5813 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5814                                     int i, u32 *part)
5815 {
5816         ssize_t ret;
5817
5818         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5819                 return -EINVAL;
5820
5821         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5822                                DP_AUX_HDCP_V_PRIME(i), part,
5823                                DRM_HDCP_V_PRIME_PART_LEN);
5824         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5825                 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5826                 return ret >= 0 ? -EIO : ret;
5827         }
5828         return 0;
5829 }
5830
5831 static
5832 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5833                                     bool enable)
5834 {
5835         /* Not used for single stream DisplayPort setups */
5836         return 0;
5837 }
5838
5839 static
5840 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5841 {
5842         ssize_t ret;
5843         u8 bstatus;
5844
5845         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5846                                &bstatus, 1);
5847         if (ret != 1) {
5848                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5849                 return false;
5850         }
5851
5852         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5853 }
5854
5855 static
5856 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5857                           bool *hdcp_capable)
5858 {
5859         ssize_t ret;
5860         u8 bcaps;
5861
5862         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5863         if (ret)
5864                 return ret;
5865
5866         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5867         return 0;
5868 }
5869
5870 struct hdcp2_dp_errata_stream_type {
5871         u8      msg_id;
5872         u8      stream_type;
5873 } __packed;
5874
5875 static struct hdcp2_dp_msg_data {
5876         u8 msg_id;
5877         u32 offset;
5878         bool msg_detectable;
5879         u32 timeout;
5880         u32 timeout2; /* Added for non_paired situation */
5881         } hdcp2_msg_data[] = {
5882                 {HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0},
5883                 {HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
5884                                 false, HDCP_2_2_CERT_TIMEOUT_MS, 0},
5885                 {HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
5886                                 false, 0, 0},
5887                 {HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
5888                                 false, 0, 0},
5889                 {HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
5890                                 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
5891                                 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS},
5892                 {HDCP_2_2_AKE_SEND_PAIRING_INFO,
5893                                 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
5894                                 HDCP_2_2_PAIRING_TIMEOUT_MS, 0},
5895                 {HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0},
5896                 {HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
5897                                 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0},
5898                 {HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
5899                                 0, 0},
5900                 {HDCP_2_2_REP_SEND_RECVID_LIST,
5901                                 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
5902                                 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0},
5903                 {HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
5904                                 0, 0},
5905                 {HDCP_2_2_REP_STREAM_MANAGE,
5906                                 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
5907                                 0, 0},
5908                 {HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
5909                                 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0},
5910 /* local define to shovel this through the write_2_2 interface */
5911 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE  50
5912                 {HDCP_2_2_ERRATA_DP_STREAM_TYPE,
5913                                 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
5914                                 0, 0},
5915                 };
5916
5917 static inline
5918 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
5919                                   u8 *rx_status)
5920 {
5921         ssize_t ret;
5922
5923         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5924                                DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
5925                                HDCP_2_2_DP_RXSTATUS_LEN);
5926         if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
5927                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5928                 return ret >= 0 ? -EIO : ret;
5929         }
5930
5931         return 0;
5932 }
5933
5934 static
5935 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
5936                                   u8 msg_id, bool *msg_ready)
5937 {
5938         u8 rx_status;
5939         int ret;
5940
5941         *msg_ready = false;
5942         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
5943         if (ret < 0)
5944                 return ret;
5945
5946         switch (msg_id) {
5947         case HDCP_2_2_AKE_SEND_HPRIME:
5948                 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
5949                         *msg_ready = true;
5950                 break;
5951         case HDCP_2_2_AKE_SEND_PAIRING_INFO:
5952                 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
5953                         *msg_ready = true;
5954                 break;
5955         case HDCP_2_2_REP_SEND_RECVID_LIST:
5956                 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
5957                         *msg_ready = true;
5958                 break;
5959         default:
5960                 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
5961                 return -EINVAL;
5962         }
5963
5964         return 0;
5965 }
5966
5967 static ssize_t
5968 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
5969                             struct hdcp2_dp_msg_data *hdcp2_msg_data)
5970 {
5971         struct intel_dp *dp = &intel_dig_port->dp;
5972         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
5973         u8 msg_id = hdcp2_msg_data->msg_id;
5974         int ret, timeout;
5975         bool msg_ready = false;
5976
5977         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
5978                 timeout = hdcp2_msg_data->timeout2;
5979         else
5980                 timeout = hdcp2_msg_data->timeout;
5981
5982         /*
5983          * There is no way to detect the CERT, LPRIME and STREAM_READY
5984          * availability. So Wait for timeout and read the msg.
5985          */
5986         if (!hdcp2_msg_data->msg_detectable) {
5987                 mdelay(timeout);
5988                 ret = 0;
5989         } else {
5990                 /*
5991                  * As we want to check the msg availability at timeout, Ignoring
5992                  * the timeout at wait for CP_IRQ.
5993                  */
5994                 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
5995                 ret = hdcp2_detect_msg_availability(intel_dig_port,
5996                                                     msg_id, &msg_ready);
5997                 if (!msg_ready)
5998                         ret = -ETIMEDOUT;
5999         }
6000
6001         if (ret)
6002                 DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n",
6003                               hdcp2_msg_data->msg_id, ret, timeout);
6004
6005         return ret;
6006 }
6007
6008 static struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
6009 {
6010         int i;
6011
6012         for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++)
6013                 if (hdcp2_msg_data[i].msg_id == msg_id)
6014                         return &hdcp2_msg_data[i];
6015
6016         return NULL;
6017 }
6018
6019 static
6020 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
6021                              void *buf, size_t size)
6022 {
6023         struct intel_dp *dp = &intel_dig_port->dp;
6024         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6025         unsigned int offset;
6026         u8 *byte = buf;
6027         ssize_t ret, bytes_to_write, len;
6028         struct hdcp2_dp_msg_data *hdcp2_msg_data;
6029
6030         hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
6031         if (!hdcp2_msg_data)
6032                 return -EINVAL;
6033
6034         offset = hdcp2_msg_data->offset;
6035
6036         /* No msg_id in DP HDCP2.2 msgs */
6037         bytes_to_write = size - 1;
6038         byte++;
6039
6040         hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
6041
6042         while (bytes_to_write) {
6043                 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
6044                                 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
6045
6046                 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
6047                                         offset, (void *)byte, len);
6048                 if (ret < 0)
6049                         return ret;
6050
6051                 bytes_to_write -= ret;
6052                 byte += ret;
6053                 offset += ret;
6054         }
6055
6056         return size;
6057 }
6058
6059 static
6060 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6061 {
6062         u8 rx_info[HDCP_2_2_RXINFO_LEN];
6063         u32 dev_cnt;
6064         ssize_t ret;
6065
6066         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6067                                DP_HDCP_2_2_REG_RXINFO_OFFSET,
6068                                (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6069         if (ret != HDCP_2_2_RXINFO_LEN)
6070                 return ret >= 0 ? -EIO : ret;
6071
6072         dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6073                    HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6074
6075         if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6076                 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
6077
6078         ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
6079                 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
6080                 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
6081
6082         return ret;
6083 }
6084
6085 static
6086 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
6087                             u8 msg_id, void *buf, size_t size)
6088 {
6089         unsigned int offset;
6090         u8 *byte = buf;
6091         ssize_t ret, bytes_to_recv, len;
6092         struct hdcp2_dp_msg_data *hdcp2_msg_data;
6093
6094         hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
6095         if (!hdcp2_msg_data)
6096                 return -EINVAL;
6097         offset = hdcp2_msg_data->offset;
6098
6099         ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
6100         if (ret < 0)
6101                 return ret;
6102
6103         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
6104                 ret = get_receiver_id_list_size(intel_dig_port);
6105                 if (ret < 0)
6106                         return ret;
6107
6108                 size = ret;
6109         }
6110         bytes_to_recv = size - 1;
6111
6112         /* DP adaptation msgs has no msg_id */
6113         byte++;
6114
6115         while (bytes_to_recv) {
6116                 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
6117                       DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
6118
6119                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
6120                                        (void *)byte, len);
6121                 if (ret < 0) {
6122                         DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret);
6123                         return ret;
6124                 }
6125
6126                 bytes_to_recv -= ret;
6127                 byte += ret;
6128                 offset += ret;
6129         }
6130         byte = buf;
6131         *byte = msg_id;
6132
6133         return size;
6134 }
6135
6136 static
6137 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
6138                                       bool is_repeater, u8 content_type)
6139 {
6140         struct hdcp2_dp_errata_stream_type stream_type_msg;
6141
6142         if (is_repeater)
6143                 return 0;
6144
6145         /*
6146          * Errata for DP: As Stream type is used for encryption, Receiver
6147          * should be communicated with stream type for the decryption of the
6148          * content.
6149          * Repeater will be communicated with stream type as a part of it's
6150          * auth later in time.
6151          */
6152         stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
6153         stream_type_msg.stream_type = content_type;
6154
6155         return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
6156                                         sizeof(stream_type_msg));
6157 }
6158
6159 static
6160 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
6161 {
6162         u8 rx_status;
6163         int ret;
6164
6165         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6166         if (ret)
6167                 return ret;
6168
6169         if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
6170                 ret = HDCP_REAUTH_REQUEST;
6171         else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
6172                 ret = HDCP_LINK_INTEGRITY_FAILURE;
6173         else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6174                 ret = HDCP_TOPOLOGY_CHANGE;
6175
6176         return ret;
6177 }
6178
6179 static
6180 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
6181                            bool *capable)
6182 {
6183         u8 rx_caps[3];
6184         int ret;
6185
6186         *capable = false;
6187         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6188                                DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
6189                                rx_caps, HDCP_2_2_RXCAPS_LEN);
6190         if (ret != HDCP_2_2_RXCAPS_LEN)
6191                 return ret >= 0 ? -EIO : ret;
6192
6193         if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
6194             HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
6195                 *capable = true;
6196
6197         return 0;
6198 }
6199
6200 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
6201         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
6202         .read_bksv = intel_dp_hdcp_read_bksv,
6203         .read_bstatus = intel_dp_hdcp_read_bstatus,
6204         .repeater_present = intel_dp_hdcp_repeater_present,
6205         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
6206         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
6207         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
6208         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
6209         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
6210         .check_link = intel_dp_hdcp_check_link,
6211         .hdcp_capable = intel_dp_hdcp_capable,
6212         .write_2_2_msg = intel_dp_hdcp2_write_msg,
6213         .read_2_2_msg = intel_dp_hdcp2_read_msg,
6214         .config_stream_type = intel_dp_hdcp2_config_stream_type,
6215         .check_2_2_link = intel_dp_hdcp2_check_link,
6216         .hdcp_2_2_capable = intel_dp_hdcp2_capable,
6217         .protocol = HDCP_PROTOCOL_DP,
6218 };
6219
6220 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
6221 {
6222         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6223         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6224
6225         lockdep_assert_held(&dev_priv->pps_mutex);
6226
6227         if (!edp_have_panel_vdd(intel_dp))
6228                 return;
6229
6230         /*
6231          * The VDD bit needs a power domain reference, so if the bit is
6232          * already enabled when we boot or resume, grab this reference and
6233          * schedule a vdd off, so we don't hold on to the reference
6234          * indefinitely.
6235          */
6236         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
6237         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
6238
6239         edp_panel_vdd_schedule_off(intel_dp);
6240 }
6241
6242 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
6243 {
6244         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6245         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6246         enum pipe pipe;
6247
6248         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
6249                                   encoder->port, &pipe))
6250                 return pipe;
6251
6252         return INVALID_PIPE;
6253 }
6254
6255 void intel_dp_encoder_reset(struct drm_encoder *encoder)
6256 {
6257         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6258         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6259         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
6260         intel_wakeref_t wakeref;
6261
6262         if (!HAS_DDI(dev_priv))
6263                 intel_dp->DP = I915_READ(intel_dp->output_reg);
6264
6265         if (lspcon->active)
6266                 lspcon_resume(lspcon);
6267
6268         intel_dp->reset_link_params = true;
6269
6270         with_pps_lock(intel_dp, wakeref) {
6271                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6272                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6273
6274                 if (intel_dp_is_edp(intel_dp)) {
6275                         /*
6276                          * Reinit the power sequencer, in case BIOS did
6277                          * something nasty with it.
6278                          */
6279                         intel_dp_pps_init(intel_dp);
6280                         intel_edp_panel_vdd_sanitize(intel_dp);
6281                 }
6282         }
6283 }
6284
6285 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6286         .force = intel_dp_force,
6287         .fill_modes = drm_helper_probe_single_connector_modes,
6288         .atomic_get_property = intel_digital_connector_atomic_get_property,
6289         .atomic_set_property = intel_digital_connector_atomic_set_property,
6290         .late_register = intel_dp_connector_register,
6291         .early_unregister = intel_dp_connector_unregister,
6292         .destroy = intel_connector_destroy,
6293         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6294         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6295 };
6296
6297 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6298         .detect_ctx = intel_dp_detect,
6299         .get_modes = intel_dp_get_modes,
6300         .mode_valid = intel_dp_mode_valid,
6301         .atomic_check = intel_digital_connector_atomic_check,
6302 };
6303
6304 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6305         .reset = intel_dp_encoder_reset,
6306         .destroy = intel_dp_encoder_destroy,
6307 };
6308
6309 enum irqreturn
6310 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
6311 {
6312         struct intel_dp *intel_dp = &intel_dig_port->dp;
6313         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6314         enum irqreturn ret = IRQ_NONE;
6315         intel_wakeref_t wakeref;
6316
6317         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
6318                 /*
6319                  * vdd off can generate a long pulse on eDP which
6320                  * would require vdd on to handle it, and thus we
6321                  * would end up in an endless cycle of
6322                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
6323                  */
6324                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
6325                               port_name(intel_dig_port->base.port));
6326                 return IRQ_HANDLED;
6327         }
6328
6329         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
6330                       port_name(intel_dig_port->base.port),
6331                       long_hpd ? "long" : "short");
6332
6333         if (long_hpd) {
6334                 intel_dp->reset_link_params = true;
6335                 return IRQ_NONE;
6336         }
6337
6338         wakeref = intel_display_power_get(dev_priv,
6339                                           intel_aux_power_domain(intel_dig_port));
6340
6341         if (intel_dp->is_mst) {
6342                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
6343                         /*
6344                          * If we were in MST mode, and device is not
6345                          * there, get out of MST mode
6346                          */
6347                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
6348                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
6349                         intel_dp->is_mst = false;
6350                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6351                                                         intel_dp->is_mst);
6352                         goto put_power;
6353                 }
6354         }
6355
6356         if (!intel_dp->is_mst) {
6357                 bool handled;
6358
6359                 handled = intel_dp_short_pulse(intel_dp);
6360
6361                 if (!handled)
6362                         goto put_power;
6363         }
6364
6365         ret = IRQ_HANDLED;
6366
6367 put_power:
6368         intel_display_power_put(dev_priv,
6369                                 intel_aux_power_domain(intel_dig_port),
6370                                 wakeref);
6371
6372         return ret;
6373 }
6374
6375 /* check the VBT to see whether the eDP is on another port */
6376 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
6377 {
6378         /*
6379          * eDP not supported on g4x. so bail out early just
6380          * for a bit extra safety in case the VBT is bonkers.
6381          */
6382         if (INTEL_GEN(dev_priv) < 5)
6383                 return false;
6384
6385         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
6386                 return true;
6387
6388         return intel_bios_is_port_edp(dev_priv, port);
6389 }
6390
6391 static void
6392 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6393 {
6394         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6395         enum port port = dp_to_dig_port(intel_dp)->base.port;
6396
6397         if (!IS_G4X(dev_priv) && port != PORT_A)
6398                 intel_attach_force_audio_property(connector);
6399
6400         intel_attach_broadcast_rgb_property(connector);
6401         if (HAS_GMCH(dev_priv))
6402                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6403         else if (INTEL_GEN(dev_priv) >= 5)
6404                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6405
6406         if (intel_dp_is_edp(intel_dp)) {
6407                 u32 allowed_scalers;
6408
6409                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
6410                 if (!HAS_GMCH(dev_priv))
6411                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
6412
6413                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
6414
6415                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
6416
6417         }
6418 }
6419
6420 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
6421 {
6422         intel_dp->panel_power_off_time = ktime_get_boottime();
6423         intel_dp->last_power_on = jiffies;
6424         intel_dp->last_backlight_off = jiffies;
6425 }
6426
6427 static void
6428 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
6429 {
6430         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6431         u32 pp_on, pp_off, pp_ctl;
6432         struct pps_registers regs;
6433
6434         intel_pps_get_registers(intel_dp, &regs);
6435
6436         pp_ctl = ironlake_get_pp_control(intel_dp);
6437
6438         /* Ensure PPS is unlocked */
6439         if (!HAS_DDI(dev_priv))
6440                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6441
6442         pp_on = I915_READ(regs.pp_on);
6443         pp_off = I915_READ(regs.pp_off);
6444
6445         /* Pull timing values out of registers */
6446         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
6447         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
6448         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
6449         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
6450
6451         if (i915_mmio_reg_valid(regs.pp_div)) {
6452                 u32 pp_div;
6453
6454                 pp_div = I915_READ(regs.pp_div);
6455
6456                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
6457         } else {
6458                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
6459         }
6460 }
6461
6462 static void
6463 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6464 {
6465         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6466                       state_name,
6467                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6468 }
6469
6470 static void
6471 intel_pps_verify_state(struct intel_dp *intel_dp)
6472 {
6473         struct edp_power_seq hw;
6474         struct edp_power_seq *sw = &intel_dp->pps_delays;
6475
6476         intel_pps_readout_hw_state(intel_dp, &hw);
6477
6478         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6479             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6480                 DRM_ERROR("PPS state mismatch\n");
6481                 intel_pps_dump_state("sw", sw);
6482                 intel_pps_dump_state("hw", &hw);
6483         }
6484 }
6485
6486 static void
6487 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6488 {
6489         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6490         struct edp_power_seq cur, vbt, spec,
6491                 *final = &intel_dp->pps_delays;
6492
6493         lockdep_assert_held(&dev_priv->pps_mutex);
6494
6495         /* already initialized? */
6496         if (final->t11_t12 != 0)
6497                 return;
6498
6499         intel_pps_readout_hw_state(intel_dp, &cur);
6500
6501         intel_pps_dump_state("cur", &cur);
6502
6503         vbt = dev_priv->vbt.edp.pps;
6504         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6505          * of 500ms appears to be too short. Ocassionally the panel
6506          * just fails to power back on. Increasing the delay to 800ms
6507          * seems sufficient to avoid this problem.
6508          */
6509         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6510                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6511                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6512                               vbt.t11_t12);
6513         }
6514         /* T11_T12 delay is special and actually in units of 100ms, but zero
6515          * based in the hw (so we need to add 100 ms). But the sw vbt
6516          * table multiplies it with 1000 to make it in units of 100usec,
6517          * too. */
6518         vbt.t11_t12 += 100 * 10;
6519
6520         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6521          * our hw here, which are all in 100usec. */
6522         spec.t1_t3 = 210 * 10;
6523         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6524         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6525         spec.t10 = 500 * 10;
6526         /* This one is special and actually in units of 100ms, but zero
6527          * based in the hw (so we need to add 100 ms). But the sw vbt
6528          * table multiplies it with 1000 to make it in units of 100usec,
6529          * too. */
6530         spec.t11_t12 = (510 + 100) * 10;
6531
6532         intel_pps_dump_state("vbt", &vbt);
6533
6534         /* Use the max of the register settings and vbt. If both are
6535          * unset, fall back to the spec limits. */
6536 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
6537                                        spec.field : \
6538                                        max(cur.field, vbt.field))
6539         assign_final(t1_t3);
6540         assign_final(t8);
6541         assign_final(t9);
6542         assign_final(t10);
6543         assign_final(t11_t12);
6544 #undef assign_final
6545
6546 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
6547         intel_dp->panel_power_up_delay = get_delay(t1_t3);
6548         intel_dp->backlight_on_delay = get_delay(t8);
6549         intel_dp->backlight_off_delay = get_delay(t9);
6550         intel_dp->panel_power_down_delay = get_delay(t10);
6551         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6552 #undef get_delay
6553
6554         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6555                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
6556                       intel_dp->panel_power_cycle_delay);
6557
6558         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6559                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
6560
6561         /*
6562          * We override the HW backlight delays to 1 because we do manual waits
6563          * on them. For T8, even BSpec recommends doing it. For T9, if we
6564          * don't do this, we'll end up waiting for the backlight off delay
6565          * twice: once when we do the manual sleep, and once when we disable
6566          * the panel and wait for the PP_STATUS bit to become zero.
6567          */
6568         final->t8 = 1;
6569         final->t9 = 1;
6570
6571         /*
6572          * HW has only a 100msec granularity for t11_t12 so round it up
6573          * accordingly.
6574          */
6575         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6576 }
6577
6578 static void
6579 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6580                                               bool force_disable_vdd)
6581 {
6582         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6583         u32 pp_on, pp_off, port_sel = 0;
6584         int div = dev_priv->rawclk_freq / 1000;
6585         struct pps_registers regs;
6586         enum port port = dp_to_dig_port(intel_dp)->base.port;
6587         const struct edp_power_seq *seq = &intel_dp->pps_delays;
6588
6589         lockdep_assert_held(&dev_priv->pps_mutex);
6590
6591         intel_pps_get_registers(intel_dp, &regs);
6592
6593         /*
6594          * On some VLV machines the BIOS can leave the VDD
6595          * enabled even on power sequencers which aren't
6596          * hooked up to any port. This would mess up the
6597          * power domain tracking the first time we pick
6598          * one of these power sequencers for use since
6599          * edp_panel_vdd_on() would notice that the VDD was
6600          * already on and therefore wouldn't grab the power
6601          * domain reference. Disable VDD first to avoid this.
6602          * This also avoids spuriously turning the VDD on as
6603          * soon as the new power sequencer gets initialized.
6604          */
6605         if (force_disable_vdd) {
6606                 u32 pp = ironlake_get_pp_control(intel_dp);
6607
6608                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
6609
6610                 if (pp & EDP_FORCE_VDD)
6611                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
6612
6613                 pp &= ~EDP_FORCE_VDD;
6614
6615                 I915_WRITE(regs.pp_ctrl, pp);
6616         }
6617
6618         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
6619                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
6620         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
6621                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
6622
6623         /* Haswell doesn't have any port selection bits for the panel
6624          * power sequencer any more. */
6625         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6626                 port_sel = PANEL_PORT_SELECT_VLV(port);
6627         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6628                 switch (port) {
6629                 case PORT_A:
6630                         port_sel = PANEL_PORT_SELECT_DPA;
6631                         break;
6632                 case PORT_C:
6633                         port_sel = PANEL_PORT_SELECT_DPC;
6634                         break;
6635                 case PORT_D:
6636                         port_sel = PANEL_PORT_SELECT_DPD;
6637                         break;
6638                 default:
6639                         MISSING_CASE(port);
6640                         break;
6641                 }
6642         }
6643
6644         pp_on |= port_sel;
6645
6646         I915_WRITE(regs.pp_on, pp_on);
6647         I915_WRITE(regs.pp_off, pp_off);
6648
6649         /*
6650          * Compute the divisor for the pp clock, simply match the Bspec formula.
6651          */
6652         if (i915_mmio_reg_valid(regs.pp_div)) {
6653                 I915_WRITE(regs.pp_div,
6654                            REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) |
6655                            REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
6656         } else {
6657                 u32 pp_ctl;
6658
6659                 pp_ctl = I915_READ(regs.pp_ctrl);
6660                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
6661                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
6662                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6663         }
6664
6665         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6666                       I915_READ(regs.pp_on),
6667                       I915_READ(regs.pp_off),
6668                       i915_mmio_reg_valid(regs.pp_div) ?
6669                       I915_READ(regs.pp_div) :
6670                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
6671 }
6672
6673 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6674 {
6675         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6676
6677         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6678                 vlv_initial_power_sequencer_setup(intel_dp);
6679         } else {
6680                 intel_dp_init_panel_power_sequencer(intel_dp);
6681                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6682         }
6683 }
6684
6685 /**
6686  * intel_dp_set_drrs_state - program registers for RR switch to take effect
6687  * @dev_priv: i915 device
6688  * @crtc_state: a pointer to the active intel_crtc_state
6689  * @refresh_rate: RR to be programmed
6690  *
6691  * This function gets called when refresh rate (RR) has to be changed from
6692  * one frequency to another. Switches can be between high and low RR
6693  * supported by the panel or to any other RR based on media playback (in
6694  * this case, RR value needs to be passed from user space).
6695  *
6696  * The caller of this function needs to take a lock on dev_priv->drrs.
6697  */
6698 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6699                                     const struct intel_crtc_state *crtc_state,
6700                                     int refresh_rate)
6701 {
6702         struct intel_encoder *encoder;
6703         struct intel_digital_port *dig_port = NULL;
6704         struct intel_dp *intel_dp = dev_priv->drrs.dp;
6705         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6706         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6707
6708         if (refresh_rate <= 0) {
6709                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6710                 return;
6711         }
6712
6713         if (intel_dp == NULL) {
6714                 DRM_DEBUG_KMS("DRRS not supported.\n");
6715                 return;
6716         }
6717
6718         dig_port = dp_to_dig_port(intel_dp);
6719         encoder = &dig_port->base;
6720
6721         if (!intel_crtc) {
6722                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6723                 return;
6724         }
6725
6726         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6727                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6728                 return;
6729         }
6730
6731         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6732                         refresh_rate)
6733                 index = DRRS_LOW_RR;
6734
6735         if (index == dev_priv->drrs.refresh_rate_type) {
6736                 DRM_DEBUG_KMS(
6737                         "DRRS requested for previously set RR...ignoring\n");
6738                 return;
6739         }
6740
6741         if (!crtc_state->base.active) {
6742                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6743                 return;
6744         }
6745
6746         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6747                 switch (index) {
6748                 case DRRS_HIGH_RR:
6749                         intel_dp_set_m_n(crtc_state, M1_N1);
6750                         break;
6751                 case DRRS_LOW_RR:
6752                         intel_dp_set_m_n(crtc_state, M2_N2);
6753                         break;
6754                 case DRRS_MAX_RR:
6755                 default:
6756                         DRM_ERROR("Unsupported refreshrate type\n");
6757                 }
6758         } else if (INTEL_GEN(dev_priv) > 6) {
6759                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6760                 u32 val;
6761
6762                 val = I915_READ(reg);
6763                 if (index > DRRS_HIGH_RR) {
6764                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6765                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6766                         else
6767                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6768                 } else {
6769                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6770                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6771                         else
6772                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6773                 }
6774                 I915_WRITE(reg, val);
6775         }
6776
6777         dev_priv->drrs.refresh_rate_type = index;
6778
6779         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6780 }
6781
6782 /**
6783  * intel_edp_drrs_enable - init drrs struct if supported
6784  * @intel_dp: DP struct
6785  * @crtc_state: A pointer to the active crtc state.
6786  *
6787  * Initializes frontbuffer_bits and drrs.dp
6788  */
6789 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6790                            const struct intel_crtc_state *crtc_state)
6791 {
6792         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6793
6794         if (!crtc_state->has_drrs) {
6795                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6796                 return;
6797         }
6798
6799         if (dev_priv->psr.enabled) {
6800                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6801                 return;
6802         }
6803
6804         mutex_lock(&dev_priv->drrs.mutex);
6805         if (dev_priv->drrs.dp) {
6806                 DRM_DEBUG_KMS("DRRS already enabled\n");
6807                 goto unlock;
6808         }
6809
6810         dev_priv->drrs.busy_frontbuffer_bits = 0;
6811
6812         dev_priv->drrs.dp = intel_dp;
6813
6814 unlock:
6815         mutex_unlock(&dev_priv->drrs.mutex);
6816 }
6817
6818 /**
6819  * intel_edp_drrs_disable - Disable DRRS
6820  * @intel_dp: DP struct
6821  * @old_crtc_state: Pointer to old crtc_state.
6822  *
6823  */
6824 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6825                             const struct intel_crtc_state *old_crtc_state)
6826 {
6827         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6828
6829         if (!old_crtc_state->has_drrs)
6830                 return;
6831
6832         mutex_lock(&dev_priv->drrs.mutex);
6833         if (!dev_priv->drrs.dp) {
6834                 mutex_unlock(&dev_priv->drrs.mutex);
6835                 return;
6836         }
6837
6838         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6839                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
6840                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
6841
6842         dev_priv->drrs.dp = NULL;
6843         mutex_unlock(&dev_priv->drrs.mutex);
6844
6845         cancel_delayed_work_sync(&dev_priv->drrs.work);
6846 }
6847
6848 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6849 {
6850         struct drm_i915_private *dev_priv =
6851                 container_of(work, typeof(*dev_priv), drrs.work.work);
6852         struct intel_dp *intel_dp;
6853
6854         mutex_lock(&dev_priv->drrs.mutex);
6855
6856         intel_dp = dev_priv->drrs.dp;
6857
6858         if (!intel_dp)
6859                 goto unlock;
6860
6861         /*
6862          * The delayed work can race with an invalidate hence we need to
6863          * recheck.
6864          */
6865
6866         if (dev_priv->drrs.busy_frontbuffer_bits)
6867                 goto unlock;
6868
6869         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6870                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6871
6872                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6873                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
6874         }
6875
6876 unlock:
6877         mutex_unlock(&dev_priv->drrs.mutex);
6878 }
6879
6880 /**
6881  * intel_edp_drrs_invalidate - Disable Idleness DRRS
6882  * @dev_priv: i915 device
6883  * @frontbuffer_bits: frontbuffer plane tracking bits
6884  *
6885  * This function gets called everytime rendering on the given planes start.
6886  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6887  *
6888  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6889  */
6890 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6891                                unsigned int frontbuffer_bits)
6892 {
6893         struct drm_crtc *crtc;
6894         enum pipe pipe;
6895
6896         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6897                 return;
6898
6899         cancel_delayed_work(&dev_priv->drrs.work);
6900
6901         mutex_lock(&dev_priv->drrs.mutex);
6902         if (!dev_priv->drrs.dp) {
6903                 mutex_unlock(&dev_priv->drrs.mutex);
6904                 return;
6905         }
6906
6907         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6908         pipe = to_intel_crtc(crtc)->pipe;
6909
6910         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6911         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6912
6913         /* invalidate means busy screen hence upclock */
6914         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6915                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6916                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6917
6918         mutex_unlock(&dev_priv->drrs.mutex);
6919 }
6920
6921 /**
6922  * intel_edp_drrs_flush - Restart Idleness DRRS
6923  * @dev_priv: i915 device
6924  * @frontbuffer_bits: frontbuffer plane tracking bits
6925  *
6926  * This function gets called every time rendering on the given planes has
6927  * completed or flip on a crtc is completed. So DRRS should be upclocked
6928  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6929  * if no other planes are dirty.
6930  *
6931  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6932  */
6933 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6934                           unsigned int frontbuffer_bits)
6935 {
6936         struct drm_crtc *crtc;
6937         enum pipe pipe;
6938
6939         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6940                 return;
6941
6942         cancel_delayed_work(&dev_priv->drrs.work);
6943
6944         mutex_lock(&dev_priv->drrs.mutex);
6945         if (!dev_priv->drrs.dp) {
6946                 mutex_unlock(&dev_priv->drrs.mutex);
6947                 return;
6948         }
6949
6950         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6951         pipe = to_intel_crtc(crtc)->pipe;
6952
6953         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6954         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6955
6956         /* flush means busy screen hence upclock */
6957         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6958                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6959                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6960
6961         /*
6962          * flush also means no more activity hence schedule downclock, if all
6963          * other fbs are quiescent too
6964          */
6965         if (!dev_priv->drrs.busy_frontbuffer_bits)
6966                 schedule_delayed_work(&dev_priv->drrs.work,
6967                                 msecs_to_jiffies(1000));
6968         mutex_unlock(&dev_priv->drrs.mutex);
6969 }
6970
6971 /**
6972  * DOC: Display Refresh Rate Switching (DRRS)
6973  *
6974  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6975  * which enables swtching between low and high refresh rates,
6976  * dynamically, based on the usage scenario. This feature is applicable
6977  * for internal panels.
6978  *
6979  * Indication that the panel supports DRRS is given by the panel EDID, which
6980  * would list multiple refresh rates for one resolution.
6981  *
6982  * DRRS is of 2 types - static and seamless.
6983  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6984  * (may appear as a blink on screen) and is used in dock-undock scenario.
6985  * Seamless DRRS involves changing RR without any visual effect to the user
6986  * and can be used during normal system usage. This is done by programming
6987  * certain registers.
6988  *
6989  * Support for static/seamless DRRS may be indicated in the VBT based on
6990  * inputs from the panel spec.
6991  *
6992  * DRRS saves power by switching to low RR based on usage scenarios.
6993  *
6994  * The implementation is based on frontbuffer tracking implementation.  When
6995  * there is a disturbance on the screen triggered by user activity or a periodic
6996  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6997  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6998  * made.
6999  *
7000  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
7001  * and intel_edp_drrs_flush() are called.
7002  *
7003  * DRRS can be further extended to support other internal panels and also
7004  * the scenario of video playback wherein RR is set based on the rate
7005  * requested by userspace.
7006  */
7007
7008 /**
7009  * intel_dp_drrs_init - Init basic DRRS work and mutex.
7010  * @connector: eDP connector
7011  * @fixed_mode: preferred mode of panel
7012  *
7013  * This function is  called only once at driver load to initialize basic
7014  * DRRS stuff.
7015  *
7016  * Returns:
7017  * Downclock mode if panel supports it, else return NULL.
7018  * DRRS support is determined by the presence of downclock mode (apart
7019  * from VBT setting).
7020  */
7021 static struct drm_display_mode *
7022 intel_dp_drrs_init(struct intel_connector *connector,
7023                    struct drm_display_mode *fixed_mode)
7024 {
7025         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7026         struct drm_display_mode *downclock_mode = NULL;
7027
7028         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
7029         mutex_init(&dev_priv->drrs.mutex);
7030
7031         if (INTEL_GEN(dev_priv) <= 6) {
7032                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
7033                 return NULL;
7034         }
7035
7036         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
7037                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
7038                 return NULL;
7039         }
7040
7041         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
7042         if (!downclock_mode) {
7043                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
7044                 return NULL;
7045         }
7046
7047         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
7048
7049         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
7050         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
7051         return downclock_mode;
7052 }
7053
7054 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
7055                                      struct intel_connector *intel_connector)
7056 {
7057         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7058         struct drm_device *dev = &dev_priv->drm;
7059         struct drm_connector *connector = &intel_connector->base;
7060         struct drm_display_mode *fixed_mode = NULL;
7061         struct drm_display_mode *downclock_mode = NULL;
7062         bool has_dpcd;
7063         enum pipe pipe = INVALID_PIPE;
7064         intel_wakeref_t wakeref;
7065         struct edid *edid;
7066
7067         if (!intel_dp_is_edp(intel_dp))
7068                 return true;
7069
7070         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
7071
7072         /*
7073          * On IBX/CPT we may get here with LVDS already registered. Since the
7074          * driver uses the only internal power sequencer available for both
7075          * eDP and LVDS bail out early in this case to prevent interfering
7076          * with an already powered-on LVDS power sequencer.
7077          */
7078         if (intel_get_lvds_encoder(dev_priv)) {
7079                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7080                 DRM_INFO("LVDS was detected, not registering eDP\n");
7081
7082                 return false;
7083         }
7084
7085         with_pps_lock(intel_dp, wakeref) {
7086                 intel_dp_init_panel_power_timestamps(intel_dp);
7087                 intel_dp_pps_init(intel_dp);
7088                 intel_edp_panel_vdd_sanitize(intel_dp);
7089         }
7090
7091         /* Cache DPCD and EDID for edp. */
7092         has_dpcd = intel_edp_init_dpcd(intel_dp);
7093
7094         if (!has_dpcd) {
7095                 /* if this fails, presume the device is a ghost */
7096                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
7097                 goto out_vdd_off;
7098         }
7099
7100         mutex_lock(&dev->mode_config.mutex);
7101         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
7102         if (edid) {
7103                 if (drm_add_edid_modes(connector, edid)) {
7104                         drm_connector_update_edid_property(connector,
7105                                                                 edid);
7106                 } else {
7107                         kfree(edid);
7108                         edid = ERR_PTR(-EINVAL);
7109                 }
7110         } else {
7111                 edid = ERR_PTR(-ENOENT);
7112         }
7113         intel_connector->edid = edid;
7114
7115         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
7116         if (fixed_mode)
7117                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
7118
7119         /* fallback to VBT if available for eDP */
7120         if (!fixed_mode)
7121                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
7122         mutex_unlock(&dev->mode_config.mutex);
7123
7124         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7125                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
7126                 register_reboot_notifier(&intel_dp->edp_notifier);
7127
7128                 /*
7129                  * Figure out the current pipe for the initial backlight setup.
7130                  * If the current pipe isn't valid, try the PPS pipe, and if that
7131                  * fails just assume pipe A.
7132                  */
7133                 pipe = vlv_active_pipe(intel_dp);
7134
7135                 if (pipe != PIPE_A && pipe != PIPE_B)
7136                         pipe = intel_dp->pps_pipe;
7137
7138                 if (pipe != PIPE_A && pipe != PIPE_B)
7139                         pipe = PIPE_A;
7140
7141                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
7142                               pipe_name(pipe));
7143         }
7144
7145         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
7146         intel_connector->panel.backlight.power = intel_edp_backlight_power;
7147         intel_panel_setup_backlight(connector, pipe);
7148
7149         if (fixed_mode)
7150                 drm_connector_init_panel_orientation_property(
7151                         connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
7152
7153         return true;
7154
7155 out_vdd_off:
7156         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7157         /*
7158          * vdd might still be enabled do to the delayed vdd off.
7159          * Make sure vdd is actually turned off here.
7160          */
7161         with_pps_lock(intel_dp, wakeref)
7162                 edp_panel_vdd_off_sync(intel_dp);
7163
7164         return false;
7165 }
7166
7167 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
7168 {
7169         struct intel_connector *intel_connector;
7170         struct drm_connector *connector;
7171
7172         intel_connector = container_of(work, typeof(*intel_connector),
7173                                        modeset_retry_work);
7174         connector = &intel_connector->base;
7175         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
7176                       connector->name);
7177
7178         /* Grab the locks before changing connector property*/
7179         mutex_lock(&connector->dev->mode_config.mutex);
7180         /* Set connector link status to BAD and send a Uevent to notify
7181          * userspace to do a modeset.
7182          */
7183         drm_connector_set_link_status_property(connector,
7184                                                DRM_MODE_LINK_STATUS_BAD);
7185         mutex_unlock(&connector->dev->mode_config.mutex);
7186         /* Send Hotplug uevent so userspace can reprobe */
7187         drm_kms_helper_hotplug_event(connector->dev);
7188 }
7189
7190 bool
7191 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
7192                         struct intel_connector *intel_connector)
7193 {
7194         struct drm_connector *connector = &intel_connector->base;
7195         struct intel_dp *intel_dp = &intel_dig_port->dp;
7196         struct intel_encoder *intel_encoder = &intel_dig_port->base;
7197         struct drm_device *dev = intel_encoder->base.dev;
7198         struct drm_i915_private *dev_priv = to_i915(dev);
7199         enum port port = intel_encoder->port;
7200         int type;
7201
7202         /* Initialize the work for modeset in case of link train failure */
7203         INIT_WORK(&intel_connector->modeset_retry_work,
7204                   intel_dp_modeset_retry_work_fn);
7205
7206         if (WARN(intel_dig_port->max_lanes < 1,
7207                  "Not enough lanes (%d) for DP on port %c\n",
7208                  intel_dig_port->max_lanes, port_name(port)))
7209                 return false;
7210
7211         intel_dp_set_source_rates(intel_dp);
7212
7213         intel_dp->reset_link_params = true;
7214         intel_dp->pps_pipe = INVALID_PIPE;
7215         intel_dp->active_pipe = INVALID_PIPE;
7216
7217         /* intel_dp vfuncs */
7218         if (HAS_DDI(dev_priv))
7219                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
7220
7221         /* Preserve the current hw state. */
7222         intel_dp->DP = I915_READ(intel_dp->output_reg);
7223         intel_dp->attached_connector = intel_connector;
7224
7225         if (intel_dp_is_port_edp(dev_priv, port))
7226                 type = DRM_MODE_CONNECTOR_eDP;
7227         else
7228                 type = DRM_MODE_CONNECTOR_DisplayPort;
7229
7230         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7231                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7232
7233         /*
7234          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
7235          * for DP the encoder type can be set by the caller to
7236          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
7237          */
7238         if (type == DRM_MODE_CONNECTOR_eDP)
7239                 intel_encoder->type = INTEL_OUTPUT_EDP;
7240
7241         /* eDP only on port B and/or C on vlv/chv */
7242         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7243                     intel_dp_is_edp(intel_dp) &&
7244                     port != PORT_B && port != PORT_C))
7245                 return false;
7246
7247         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
7248                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
7249                         port_name(port));
7250
7251         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
7252         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
7253
7254         if (!HAS_GMCH(dev_priv))
7255                 connector->interlace_allowed = true;
7256         connector->doublescan_allowed = 0;
7257
7258         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
7259
7260         intel_dp_aux_init(intel_dp);
7261
7262         intel_connector_attach_encoder(intel_connector, intel_encoder);
7263
7264         if (HAS_DDI(dev_priv))
7265                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
7266         else
7267                 intel_connector->get_hw_state = intel_connector_get_hw_state;
7268
7269         /* init MST on ports that can support it */
7270         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
7271             (port == PORT_B || port == PORT_C ||
7272              port == PORT_D || port == PORT_F))
7273                 intel_dp_mst_encoder_init(intel_dig_port,
7274                                           intel_connector->base.base.id);
7275
7276         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
7277                 intel_dp_aux_fini(intel_dp);
7278                 intel_dp_mst_encoder_cleanup(intel_dig_port);
7279                 goto fail;
7280         }
7281
7282         intel_dp_add_properties(intel_dp, connector);
7283
7284         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
7285                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
7286                 if (ret)
7287                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
7288         }
7289
7290         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
7291          * 0xd.  Failure to do so will result in spurious interrupts being
7292          * generated on the port when a cable is not attached.
7293          */
7294         if (IS_G45(dev_priv)) {
7295                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
7296                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
7297         }
7298
7299         return true;
7300
7301 fail:
7302         drm_connector_cleanup(connector);
7303
7304         return false;
7305 }
7306
7307 bool intel_dp_init(struct drm_i915_private *dev_priv,
7308                    i915_reg_t output_reg,
7309                    enum port port)
7310 {
7311         struct intel_digital_port *intel_dig_port;
7312         struct intel_encoder *intel_encoder;
7313         struct drm_encoder *encoder;
7314         struct intel_connector *intel_connector;
7315
7316         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
7317         if (!intel_dig_port)
7318                 return false;
7319
7320         intel_connector = intel_connector_alloc();
7321         if (!intel_connector)
7322                 goto err_connector_alloc;
7323
7324         intel_encoder = &intel_dig_port->base;
7325         encoder = &intel_encoder->base;
7326
7327         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
7328                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
7329                              "DP %c", port_name(port)))
7330                 goto err_encoder_init;
7331
7332         intel_encoder->hotplug = intel_dp_hotplug;
7333         intel_encoder->compute_config = intel_dp_compute_config;
7334         intel_encoder->get_hw_state = intel_dp_get_hw_state;
7335         intel_encoder->get_config = intel_dp_get_config;
7336         intel_encoder->update_pipe = intel_panel_update_backlight;
7337         intel_encoder->suspend = intel_dp_encoder_suspend;
7338         if (IS_CHERRYVIEW(dev_priv)) {
7339                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
7340                 intel_encoder->pre_enable = chv_pre_enable_dp;
7341                 intel_encoder->enable = vlv_enable_dp;
7342                 intel_encoder->disable = vlv_disable_dp;
7343                 intel_encoder->post_disable = chv_post_disable_dp;
7344                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
7345         } else if (IS_VALLEYVIEW(dev_priv)) {
7346                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
7347                 intel_encoder->pre_enable = vlv_pre_enable_dp;
7348                 intel_encoder->enable = vlv_enable_dp;
7349                 intel_encoder->disable = vlv_disable_dp;
7350                 intel_encoder->post_disable = vlv_post_disable_dp;
7351         } else {
7352                 intel_encoder->pre_enable = g4x_pre_enable_dp;
7353                 intel_encoder->enable = g4x_enable_dp;
7354                 intel_encoder->disable = g4x_disable_dp;
7355                 intel_encoder->post_disable = g4x_post_disable_dp;
7356         }
7357
7358         intel_dig_port->dp.output_reg = output_reg;
7359         intel_dig_port->max_lanes = 4;
7360
7361         intel_encoder->type = INTEL_OUTPUT_DP;
7362         intel_encoder->power_domain = intel_port_to_power_domain(port);
7363         if (IS_CHERRYVIEW(dev_priv)) {
7364                 if (port == PORT_D)
7365                         intel_encoder->crtc_mask = 1 << 2;
7366                 else
7367                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
7368         } else {
7369                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
7370         }
7371         intel_encoder->cloneable = 0;
7372         intel_encoder->port = port;
7373
7374         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
7375
7376         if (port != PORT_A)
7377                 intel_infoframe_init(intel_dig_port);
7378
7379         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
7380         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
7381                 goto err_init_connector;
7382
7383         return true;
7384
7385 err_init_connector:
7386         drm_encoder_cleanup(encoder);
7387 err_encoder_init:
7388         kfree(intel_connector);
7389 err_connector_alloc:
7390         kfree(intel_dig_port);
7391         return false;
7392 }
7393
7394 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
7395 {
7396         struct intel_encoder *encoder;
7397
7398         for_each_intel_encoder(&dev_priv->drm, encoder) {
7399                 struct intel_dp *intel_dp;
7400
7401                 if (encoder->type != INTEL_OUTPUT_DDI)
7402                         continue;
7403
7404                 intel_dp = enc_to_intel_dp(&encoder->base);
7405
7406                 if (!intel_dp->can_mst)
7407                         continue;
7408
7409                 if (intel_dp->is_mst)
7410                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
7411         }
7412 }
7413
7414 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
7415 {
7416         struct intel_encoder *encoder;
7417
7418         for_each_intel_encoder(&dev_priv->drm, encoder) {
7419                 struct intel_dp *intel_dp;
7420                 int ret;
7421
7422                 if (encoder->type != INTEL_OUTPUT_DDI)
7423                         continue;
7424
7425                 intel_dp = enc_to_intel_dp(&encoder->base);
7426
7427                 if (!intel_dp->can_mst)
7428                         continue;
7429
7430                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
7431                 if (ret) {
7432                         intel_dp->is_mst = false;
7433                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7434                                                         false);
7435                 }
7436         }
7437 }