drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_crtc_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 /* Compliance test status bits  */
  45 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  46 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  47 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  48 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49
  50 struct dp_link_dpll {
  51         int link_bw;
  52         struct dpll dpll;
  53 };
  54
  55 static const struct dp_link_dpll gen4_dpll[] = {
  56         { DP_LINK_BW_1_62,
  57                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  58         { DP_LINK_BW_2_7,
  59                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  60 };
  61
  62 static const struct dp_link_dpll pch_dpll[] = {
  63         { DP_LINK_BW_1_62,
  64                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  65         { DP_LINK_BW_2_7,
  66                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  67 };
  68
  69 static const struct dp_link_dpll vlv_dpll[] = {
  70         { DP_LINK_BW_1_62,
  71                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  72         { DP_LINK_BW_2_7,
  73                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  74 };
  75
  76 /*
  77  * CHV supports eDP 1.4 that have  more link rates.
  78  * Below only provides the fixed rate but exclude variable rate.
  79  */
  80 static const struct dp_link_dpll chv_dpll[] = {
  81         /*
  82          * CHV requires to program fractional division for m2.
  83          * m2 is stored in fixed point format using formula below
  84          * (m2_int << 22) | m2_fraction
  85          */
  86         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  87                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  88         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  89                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  90         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  92 };
  93
  94 static const int skl_rates[] = { 162000, 216000, 270000,
  95                                   324000, 432000, 540000 };
  96 static const int chv_rates[] = { 162000, 202500, 210000, 216000,
  97                                  243000, 270000, 324000, 405000,
  98                                  420000, 432000, 540000 };
  99 static const int default_rates[] = { 162000, 270000, 540000 };
 100
 101 /**
 102  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 103  * @intel_dp: DP struct
 104  *
 105  * If a CPU or PCH DP output is attached to an eDP panel, this function
 106  * will return true, and false otherwise.
 107  */
 108 static bool is_edp(struct intel_dp *intel_dp)
 109 {
 110         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 111
 112         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 113 }
 114
 115 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 116 {
 117         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 118
 119         return intel_dig_port->base.base.dev;
 120 }
 121
 122 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 123 {
 124         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 125 }
 126
 127 static void intel_dp_link_down(struct intel_dp *intel_dp);
 128 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 129 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 130 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 131 static void vlv_steal_power_sequencer(struct drm_device *dev,
 132                                       enum pipe pipe);
 133
 134 static int
 135 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 136 {
 137         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 138
 139         switch (max_link_bw) {
 140         case DP_LINK_BW_1_62:
 141         case DP_LINK_BW_2_7:
 142         case DP_LINK_BW_5_4:
 143                 break;
 144         default:
 145                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 146                      max_link_bw);
 147                 max_link_bw = DP_LINK_BW_1_62;
 148                 break;
 149         }
 150         return max_link_bw;
 151 }
 152
 153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 154 {
 155         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 156         struct drm_device *dev = intel_dig_port->base.base.dev;
 157         u8 source_max, sink_max;
 158
 159         source_max = 4;
 160         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 161             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 162                 source_max = 2;
 163
 164         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 165
 166         return min(source_max, sink_max);
 167 }
 168
 169 /*
 170  * The units on the numbers in the next two are... bizarre.  Examples will
 171  * make it clearer; this one parallels an example in the eDP spec.
 172  *
 173  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 174  *
 175  *     270000 * 1 * 8 / 10 == 216000
 176  *
 177  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 178  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 179  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 180  * 119000.  At 18bpp that's 2142000 kilobits per second.
 181  *
 182  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 183  * get the result in decakilobits instead of kilobits.
 184  */
 185
 186 static int
 187 intel_dp_link_required(int pixel_clock, int bpp)
 188 {
 189         return (pixel_clock * bpp + 9) / 10;
 190 }
 191
 192 static int
 193 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 194 {
 195         return (max_link_clock * max_lanes * 8) / 10;
 196 }
 197
 198 static enum drm_mode_status
 199 intel_dp_mode_valid(struct drm_connector *connector,
 200                     struct drm_display_mode *mode)
 201 {
 202         struct intel_dp *intel_dp = intel_attached_dp(connector);
 203         struct intel_connector *intel_connector = to_intel_connector(connector);
 204         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 205         int target_clock = mode->clock;
 206         int max_rate, mode_rate, max_lanes, max_link_clock;
 207
 208         if (is_edp(intel_dp) && fixed_mode) {
 209                 if (mode->hdisplay > fixed_mode->hdisplay)
 210                         return MODE_PANEL;
 211
 212                 if (mode->vdisplay > fixed_mode->vdisplay)
 213                         return MODE_PANEL;
 214
 215                 target_clock = fixed_mode->clock;
 216         }
 217
 218         max_link_clock = intel_dp_max_link_rate(intel_dp);
 219         max_lanes = intel_dp_max_lane_count(intel_dp);
 220
 221         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 222         mode_rate = intel_dp_link_required(target_clock, 18);
 223
 224         if (mode_rate > max_rate)
 225                 return MODE_CLOCK_HIGH;
 226
 227         if (mode->clock < 10000)
 228                 return MODE_CLOCK_LOW;
 229
 230         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 231                 return MODE_H_ILLEGAL;
 232
 233         return MODE_OK;
 234 }
 235
 236 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 237 {
 238         int     i;
 239         uint32_t v = 0;
 240
 241         if (src_bytes > 4)
 242                 src_bytes = 4;
 243         for (i = 0; i < src_bytes; i++)
 244                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 245         return v;
 246 }
 247
 248 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 249 {
 250         int i;
 251         if (dst_bytes > 4)
 252                 dst_bytes = 4;
 253         for (i = 0; i < dst_bytes; i++)
 254                 dst[i] = src >> ((3-i) * 8);
 255 }
 256
 257 /* hrawclock is 1/4 the FSB frequency */
 258 static int
 259 intel_hrawclk(struct drm_device *dev)
 260 {
 261         struct drm_i915_private *dev_priv = dev->dev_private;
 262         uint32_t clkcfg;
 263
 264         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 265         if (IS_VALLEYVIEW(dev))
 266                 return 200;
 267
 268         clkcfg = I915_READ(CLKCFG);
 269         switch (clkcfg & CLKCFG_FSB_MASK) {
 270         case CLKCFG_FSB_400:
 271                 return 100;
 272         case CLKCFG_FSB_533:
 273                 return 133;
 274         case CLKCFG_FSB_667:
 275                 return 166;
 276         case CLKCFG_FSB_800:
 277                 return 200;
 278         case CLKCFG_FSB_1067:
 279                 return 266;
 280         case CLKCFG_FSB_1333:
 281                 return 333;
 282         /* these two are just a guess; one of them might be right */
 283         case CLKCFG_FSB_1600:
 284         case CLKCFG_FSB_1600_ALT:
 285                 return 400;
 286         default:
 287                 return 133;
 288         }
 289 }
 290
 291 static void
 292 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 293                                     struct intel_dp *intel_dp);
 294 static void
 295 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 296                                               struct intel_dp *intel_dp);
 297
 298 static void pps_lock(struct intel_dp *intel_dp)
 299 {
 300         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 301         struct intel_encoder *encoder = &intel_dig_port->base;
 302         struct drm_device *dev = encoder->base.dev;
 303         struct drm_i915_private *dev_priv = dev->dev_private;
 304         enum intel_display_power_domain power_domain;
 305
 306         /*
 307          * See vlv_power_sequencer_reset() why we need
 308          * a power domain reference here.
 309          */
 310         power_domain = intel_display_port_power_domain(encoder);
 311         intel_display_power_get(dev_priv, power_domain);
 312
 313         mutex_lock(&dev_priv->pps_mutex);
 314 }
 315
 316 static void pps_unlock(struct intel_dp *intel_dp)
 317 {
 318         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 319         struct intel_encoder *encoder = &intel_dig_port->base;
 320         struct drm_device *dev = encoder->base.dev;
 321         struct drm_i915_private *dev_priv = dev->dev_private;
 322         enum intel_display_power_domain power_domain;
 323
 324         mutex_unlock(&dev_priv->pps_mutex);
 325
 326         power_domain = intel_display_port_power_domain(encoder);
 327         intel_display_power_put(dev_priv, power_domain);
 328 }
 329
 330 static void
 331 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 332 {
 333         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 334         struct drm_device *dev = intel_dig_port->base.base.dev;
 335         struct drm_i915_private *dev_priv = dev->dev_private;
 336         enum pipe pipe = intel_dp->pps_pipe;
 337         bool pll_enabled;
 338         uint32_t DP;
 339
 340         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 341                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 342                  pipe_name(pipe), port_name(intel_dig_port->port)))
 343                 return;
 344
 345         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 346                       pipe_name(pipe), port_name(intel_dig_port->port));
 347
 348         /* Preserve the BIOS-computed detected bit. This is
 349          * supposed to be read-only.
 350          */
 351         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 352         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 353         DP |= DP_PORT_WIDTH(1);
 354         DP |= DP_LINK_TRAIN_PAT_1;
 355
 356         if (IS_CHERRYVIEW(dev))
 357                 DP |= DP_PIPE_SELECT_CHV(pipe);
 358         else if (pipe == PIPE_B)
 359                 DP |= DP_PIPEB_SELECT;
 360
 361         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 362
 363         /*
 364          * The DPLL for the pipe must be enabled for this to work.
 365          * So enable temporarily it if it's not already enabled.
 366          */
 367         if (!pll_enabled)
 368                 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 369                                  &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
 370
 371         /*
 372          * Similar magic as in intel_dp_enable_port().
 373          * We _must_ do this port enable + disable trick
 374          * to make this power seqeuencer lock onto the port.
 375          * Otherwise even VDD force bit won't work.
 376          */
 377         I915_WRITE(intel_dp->output_reg, DP);
 378         POSTING_READ(intel_dp->output_reg);
 379
 380         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 381         POSTING_READ(intel_dp->output_reg);
 382
 383         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 384         POSTING_READ(intel_dp->output_reg);
 385
 386         if (!pll_enabled)
 387                 vlv_force_pll_off(dev, pipe);
 388 }
 389
 390 static enum pipe
 391 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 392 {
 393         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 394         struct drm_device *dev = intel_dig_port->base.base.dev;
 395         struct drm_i915_private *dev_priv = dev->dev_private;
 396         struct intel_encoder *encoder;
 397         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 398         enum pipe pipe;
 399
 400         lockdep_assert_held(&dev_priv->pps_mutex);
 401
 402         /* We should never land here with regular DP ports */
 403         WARN_ON(!is_edp(intel_dp));
 404
 405         if (intel_dp->pps_pipe != INVALID_PIPE)
 406                 return intel_dp->pps_pipe;
 407
 408         /*
 409          * We don't have power sequencer currently.
 410          * Pick one that's not used by other ports.
 411          */
 412         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 413                             base.head) {
 414                 struct intel_dp *tmp;
 415
 416                 if (encoder->type != INTEL_OUTPUT_EDP)
 417                         continue;
 418
 419                 tmp = enc_to_intel_dp(&encoder->base);
 420
 421                 if (tmp->pps_pipe != INVALID_PIPE)
 422                         pipes &= ~(1 << tmp->pps_pipe);
 423         }
 424
 425         /*
 426          * Didn't find one. This should not happen since there
 427          * are two power sequencers and up to two eDP ports.
 428          */
 429         if (WARN_ON(pipes == 0))
 430                 pipe = PIPE_A;
 431         else
 432                 pipe = ffs(pipes) - 1;
 433
 434         vlv_steal_power_sequencer(dev, pipe);
 435         intel_dp->pps_pipe = pipe;
 436
 437         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 438                       pipe_name(intel_dp->pps_pipe),
 439                       port_name(intel_dig_port->port));
 440
 441         /* init power sequencer on this pipe and port */
 442         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 443         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 444
 445         /*
 446          * Even vdd force doesn't work until we've made
 447          * the power sequencer lock in on the port.
 448          */
 449         vlv_power_sequencer_kick(intel_dp);
 450
 451         return intel_dp->pps_pipe;
 452 }
 453
 454 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 455                                enum pipe pipe);
 456
 457 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 458                                enum pipe pipe)
 459 {
 460         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 461 }
 462
 463 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 464                                 enum pipe pipe)
 465 {
 466         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 467 }
 468
 469 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 470                          enum pipe pipe)
 471 {
 472         return true;
 473 }
 474
 475 static enum pipe
 476 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 477                      enum port port,
 478                      vlv_pipe_check pipe_check)
 479 {
 480         enum pipe pipe;
 481
 482         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 483                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 484                         PANEL_PORT_SELECT_MASK;
 485
 486                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 487                         continue;
 488
 489                 if (!pipe_check(dev_priv, pipe))
 490                         continue;
 491
 492                 return pipe;
 493         }
 494
 495         return INVALID_PIPE;
 496 }
 497
 498 static void
 499 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 500 {
 501         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 502         struct drm_device *dev = intel_dig_port->base.base.dev;
 503         struct drm_i915_private *dev_priv = dev->dev_private;
 504         enum port port = intel_dig_port->port;
 505
 506         lockdep_assert_held(&dev_priv->pps_mutex);
 507
 508         /* try to find a pipe with this port selected */
 509         /* first pick one where the panel is on */
 510         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 511                                                   vlv_pipe_has_pp_on);
 512         /* didn't find one? pick one where vdd is on */
 513         if (intel_dp->pps_pipe == INVALID_PIPE)
 514                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 515                                                           vlv_pipe_has_vdd_on);
 516         /* didn't find one? pick one with just the correct port */
 517         if (intel_dp->pps_pipe == INVALID_PIPE)
 518                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 519                                                           vlv_pipe_any);
 520
 521         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 522         if (intel_dp->pps_pipe == INVALID_PIPE) {
 523                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 524                               port_name(port));
 525                 return;
 526         }
 527
 528         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 529                       port_name(port), pipe_name(intel_dp->pps_pipe));
 530
 531         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 532         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 533 }
 534
 535 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 536 {
 537         struct drm_device *dev = dev_priv->dev;
 538         struct intel_encoder *encoder;
 539
 540         if (WARN_ON(!IS_VALLEYVIEW(dev)))
 541                 return;
 542
 543         /*
 544          * We can't grab pps_mutex here due to deadlock with power_domain
 545          * mutex when power_domain functions are called while holding pps_mutex.
 546          * That also means that in order to use pps_pipe the code needs to
 547          * hold both a power domain reference and pps_mutex, and the power domain
 548          * reference get/put must be done while _not_ holding pps_mutex.
 549          * pps_{lock,unlock}() do these steps in the correct order, so one
 550          * should use them always.
 551          */
 552
 553         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 554                 struct intel_dp *intel_dp;
 555
 556                 if (encoder->type != INTEL_OUTPUT_EDP)
 557                         continue;
 558
 559                 intel_dp = enc_to_intel_dp(&encoder->base);
 560                 intel_dp->pps_pipe = INVALID_PIPE;
 561         }
 562 }
 563
 564 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 565 {
 566         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 567
 568         if (HAS_PCH_SPLIT(dev))
 569                 return PCH_PP_CONTROL;
 570         else
 571                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 572 }
 573
 574 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 575 {
 576         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 577
 578         if (HAS_PCH_SPLIT(dev))
 579                 return PCH_PP_STATUS;
 580         else
 581                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 582 }
 583
 584 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 585    This function only applicable when panel PM state is not to be tracked */
 586 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 587                               void *unused)
 588 {
 589         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 590                                                  edp_notifier);
 591         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 592         struct drm_i915_private *dev_priv = dev->dev_private;
 593         u32 pp_div;
 594         u32 pp_ctrl_reg, pp_div_reg;
 595
 596         if (!is_edp(intel_dp) || code != SYS_RESTART)
 597                 return 0;
 598
 599         pps_lock(intel_dp);
 600
 601         if (IS_VALLEYVIEW(dev)) {
 602                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 603
 604                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 605                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 606                 pp_div = I915_READ(pp_div_reg);
 607                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 608
 609                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 610                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 611                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 612                 msleep(intel_dp->panel_power_cycle_delay);
 613         }
 614
 615         pps_unlock(intel_dp);
 616
 617         return 0;
 618 }
 619
 620 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 621 {
 622         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 623         struct drm_i915_private *dev_priv = dev->dev_private;
 624
 625         lockdep_assert_held(&dev_priv->pps_mutex);
 626
 627         if (IS_VALLEYVIEW(dev) &&
 628             intel_dp->pps_pipe == INVALID_PIPE)
 629                 return false;
 630
 631         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 632 }
 633
 634 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 635 {
 636         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 637         struct drm_i915_private *dev_priv = dev->dev_private;
 638
 639         lockdep_assert_held(&dev_priv->pps_mutex);
 640
 641         if (IS_VALLEYVIEW(dev) &&
 642             intel_dp->pps_pipe == INVALID_PIPE)
 643                 return false;
 644
 645         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 646 }
 647
 648 static void
 649 intel_dp_check_edp(struct intel_dp *intel_dp)
 650 {
 651         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 652         struct drm_i915_private *dev_priv = dev->dev_private;
 653
 654         if (!is_edp(intel_dp))
 655                 return;
 656
 657         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 658                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 659                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 660                               I915_READ(_pp_stat_reg(intel_dp)),
 661                               I915_READ(_pp_ctrl_reg(intel_dp)));
 662         }
 663 }
 664
 665 static uint32_t
 666 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 667 {
 668         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 669         struct drm_device *dev = intel_dig_port->base.base.dev;
 670         struct drm_i915_private *dev_priv = dev->dev_private;
 671         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 672         uint32_t status;
 673         bool done;
 674
 675 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 676         if (has_aux_irq)
 677                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 678                                           msecs_to_jiffies_timeout(10));
 679         else
 680                 done = wait_for_atomic(C, 10) == 0;
 681         if (!done)
 682                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 683                           has_aux_irq);
 684 #undef C
 685
 686         return status;
 687 }
 688
 689 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 690 {
 691         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 692         struct drm_device *dev = intel_dig_port->base.base.dev;
 693
 694         /*
 695          * The clock divider is based off the hrawclk, and would like to run at
 696          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 697          */
 698         return index ? 0 : intel_hrawclk(dev) / 2;
 699 }
 700
 701 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 702 {
 703         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 704         struct drm_device *dev = intel_dig_port->base.base.dev;
 705         struct drm_i915_private *dev_priv = dev->dev_private;
 706
 707         if (index)
 708                 return 0;
 709
 710         if (intel_dig_port->port == PORT_A) {
 711                 return DIV_ROUND_UP(dev_priv->display.get_display_clock_speed(dev), 2000);
 712         } else {
 713                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 714         }
 715 }
 716
 717 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 718 {
 719         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 720         struct drm_device *dev = intel_dig_port->base.base.dev;
 721         struct drm_i915_private *dev_priv = dev->dev_private;
 722
 723         if (intel_dig_port->port == PORT_A) {
 724                 if (index)
 725                         return 0;
 726                 return DIV_ROUND_CLOSEST(dev_priv->display.get_display_clock_speed(dev), 2000);
 727         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 728                 /* Workaround for non-ULT HSW */
 729                 switch (index) {
 730                 case 0: return 63;
 731                 case 1: return 72;
 732                 default: return 0;
 733                 }
 734         } else  {
 735                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 736         }
 737 }
 738
 739 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 740 {
 741         return index ? 0 : 100;
 742 }
 743
 744 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 745 {
 746         /*
 747          * SKL doesn't need us to program the AUX clock divider (Hardware will
 748          * derive the clock from CDCLK automatically). We still implement the
 749          * get_aux_clock_divider vfunc to plug-in into the existing code.
 750          */
 751         return index ? 0 : 1;
 752 }
 753
 754 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 755                                       bool has_aux_irq,
 756                                       int send_bytes,
 757                                       uint32_t aux_clock_divider)
 758 {
 759         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 760         struct drm_device *dev = intel_dig_port->base.base.dev;
 761         uint32_t precharge, timeout;
 762
 763         if (IS_GEN6(dev))
 764                 precharge = 3;
 765         else
 766                 precharge = 5;
 767
 768         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 769                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 770         else
 771                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 772
 773         return DP_AUX_CH_CTL_SEND_BUSY |
 774                DP_AUX_CH_CTL_DONE |
 775                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 776                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 777                timeout |
 778                DP_AUX_CH_CTL_RECEIVE_ERROR |
 779                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 780                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 781                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 782 }
 783
 784 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 785                                       bool has_aux_irq,
 786                                       int send_bytes,
 787                                       uint32_t unused)
 788 {
 789         return DP_AUX_CH_CTL_SEND_BUSY |
 790                DP_AUX_CH_CTL_DONE |
 791                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 792                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 793                DP_AUX_CH_CTL_TIME_OUT_1600us |
 794                DP_AUX_CH_CTL_RECEIVE_ERROR |
 795                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 796                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 797 }
 798
 799 static int
 800 intel_dp_aux_ch(struct intel_dp *intel_dp,
 801                 const uint8_t *send, int send_bytes,
 802                 uint8_t *recv, int recv_size)
 803 {
 804         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 805         struct drm_device *dev = intel_dig_port->base.base.dev;
 806         struct drm_i915_private *dev_priv = dev->dev_private;
 807         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 808         uint32_t ch_data = ch_ctl + 4;
 809         uint32_t aux_clock_divider;
 810         int i, ret, recv_bytes;
 811         uint32_t status;
 812         int try, clock = 0;
 813         bool has_aux_irq = HAS_AUX_IRQ(dev);
 814         bool vdd;
 815
 816         pps_lock(intel_dp);
 817
 818         /*
 819          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 820          * In such cases we want to leave VDD enabled and it's up to upper layers
 821          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 822          * ourselves.
 823          */
 824         vdd = edp_panel_vdd_on(intel_dp);
 825
 826         /* dp aux is extremely sensitive to irq latency, hence request the
 827          * lowest possible wakeup latency and so prevent the cpu from going into
 828          * deep sleep states.
 829          */
 830         pm_qos_update_request(&dev_priv->pm_qos, 0);
 831
 832         intel_dp_check_edp(intel_dp);
 833
 834         intel_aux_display_runtime_get(dev_priv);
 835
 836         /* Try to wait for any previous AUX channel activity */
 837         for (try = 0; try < 3; try++) {
 838                 status = I915_READ_NOTRACE(ch_ctl);
 839                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 840                         break;
 841                 msleep(1);
 842         }
 843
 844         if (try == 3) {
 845                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 846                      I915_READ(ch_ctl));
 847                 ret = -EBUSY;
 848                 goto out;
 849         }
 850
 851         /* Only 5 data registers! */
 852         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 853                 ret = -E2BIG;
 854                 goto out;
 855         }
 856
 857         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 858                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 859                                                           has_aux_irq,
 860                                                           send_bytes,
 861                                                           aux_clock_divider);
 862
 863                 /* Must try at least 3 times according to DP spec */
 864                 for (try = 0; try < 5; try++) {
 865                         /* Load the send data into the aux channel data registers */
 866                         for (i = 0; i < send_bytes; i += 4)
 867                                 I915_WRITE(ch_data + i,
 868                                            intel_dp_pack_aux(send + i,
 869                                                              send_bytes - i));
 870
 871                         /* Send the command and wait for it to complete */
 872                         I915_WRITE(ch_ctl, send_ctl);
 873
 874                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 875
 876                         /* Clear done status and any errors */
 877                         I915_WRITE(ch_ctl,
 878                                    status |
 879                                    DP_AUX_CH_CTL_DONE |
 880                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 881                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 882
 883                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
 884                                 continue;
 885
 886                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
 887                          *   400us delay required for errors and timeouts
 888                          *   Timeout errors from the HW already meet this
 889                          *   requirement so skip to next iteration
 890                          */
 891                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 892                                 usleep_range(400, 500);
 893                                 continue;
 894                         }
 895                         if (status & DP_AUX_CH_CTL_DONE)
 896                                 break;
 897                 }
 898                 if (status & DP_AUX_CH_CTL_DONE)
 899                         break;
 900         }
 901
 902         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 903                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 904                 ret = -EBUSY;
 905                 goto out;
 906         }
 907
 908         /* Check for timeout or receive error.
 909          * Timeouts occur when the sink is not connected
 910          */
 911         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 912                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 913                 ret = -EIO;
 914                 goto out;
 915         }
 916
 917         /* Timeouts occur when the device isn't connected, so they're
 918          * "normal" -- don't fill the kernel log with these */
 919         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 920                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 921                 ret = -ETIMEDOUT;
 922                 goto out;
 923         }
 924
 925         /* Unload any bytes sent back from the other side */
 926         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 927                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 928         if (recv_bytes > recv_size)
 929                 recv_bytes = recv_size;
 930
 931         for (i = 0; i < recv_bytes; i += 4)
 932                 intel_dp_unpack_aux(I915_READ(ch_data + i),
 933                                     recv + i, recv_bytes - i);
 934
 935         ret = recv_bytes;
 936 out:
 937         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 938         intel_aux_display_runtime_put(dev_priv);
 939
 940         if (vdd)
 941                 edp_panel_vdd_off(intel_dp, false);
 942
 943         pps_unlock(intel_dp);
 944
 945         return ret;
 946 }
 947
 948 #define BARE_ADDRESS_SIZE       3
 949 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 950 static ssize_t
 951 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 952 {
 953         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 954         uint8_t txbuf[20], rxbuf[20];
 955         size_t txsize, rxsize;
 956         int ret;
 957
 958         txbuf[0] = (msg->request << 4) |
 959                 ((msg->address >> 16) & 0xf);
 960         txbuf[1] = (msg->address >> 8) & 0xff;
 961         txbuf[2] = msg->address & 0xff;
 962         txbuf[3] = msg->size - 1;
 963
 964         switch (msg->request & ~DP_AUX_I2C_MOT) {
 965         case DP_AUX_NATIVE_WRITE:
 966         case DP_AUX_I2C_WRITE:
 967                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 968                 rxsize = 2; /* 0 or 1 data bytes */
 969
 970                 if (WARN_ON(txsize > 20))
 971                         return -E2BIG;
 972
 973                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 974
 975                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 976                 if (ret > 0) {
 977                         msg->reply = rxbuf[0] >> 4;
 978
 979                         if (ret > 1) {
 980                                 /* Number of bytes written in a short write. */
 981                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
 982                         } else {
 983                                 /* Return payload size. */
 984                                 ret = msg->size;
 985                         }
 986                 }
 987                 break;
 988
 989         case DP_AUX_NATIVE_READ:
 990         case DP_AUX_I2C_READ:
 991                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 992                 rxsize = msg->size + 1;
 993
 994                 if (WARN_ON(rxsize > 20))
 995                         return -E2BIG;
 996
 997                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 998                 if (ret > 0) {
 999                         msg->reply = rxbuf[0] >> 4;
1000                         /*
1001                          * Assume happy day, and copy the data. The caller is
1002                          * expected to check msg->reply before touching it.
1003                          *
1004                          * Return payload size.
1005                          */
1006                         ret--;
1007                         memcpy(msg->buffer, rxbuf + 1, ret);
1008                 }
1009                 break;
1010
1011         default:
1012                 ret = -EINVAL;
1013                 break;
1014         }
1015
1016         return ret;
1017 }
1018
1019 static void
1020 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1021 {
1022         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1023         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1024         enum port port = intel_dig_port->port;
1025         const char *name = NULL;
1026         int ret;
1027
1028         switch (port) {
1029         case PORT_A:
1030                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
1031                 name = "DPDDC-A";
1032                 break;
1033         case PORT_B:
1034                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1035                 name = "DPDDC-B";
1036                 break;
1037         case PORT_C:
1038                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1039                 name = "DPDDC-C";
1040                 break;
1041         case PORT_D:
1042                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1043                 name = "DPDDC-D";
1044                 break;
1045         default:
1046                 BUG();
1047         }
1048
1049         /*
1050          * The AUX_CTL register is usually DP_CTL + 0x10.
1051          *
1052          * On Haswell and Broadwell though:
1053          *   - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1054          *   - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1055          *
1056          * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1057          */
1058         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1059                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1060
1061         intel_dp->aux.name = name;
1062         intel_dp->aux.dev = dev->dev;
1063         intel_dp->aux.transfer = intel_dp_aux_transfer;
1064
1065         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1066                       connector->base.kdev->kobj.name);
1067
1068         ret = drm_dp_aux_register(&intel_dp->aux);
1069         if (ret < 0) {
1070                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1071                           name, ret);
1072                 return;
1073         }
1074
1075         ret = sysfs_create_link(&connector->base.kdev->kobj,
1076                                 &intel_dp->aux.ddc.dev.kobj,
1077                                 intel_dp->aux.ddc.dev.kobj.name);
1078         if (ret < 0) {
1079                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
1080                 drm_dp_aux_unregister(&intel_dp->aux);
1081         }
1082 }
1083
1084 static void
1085 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1086 {
1087         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1088
1089         if (!intel_connector->mst_port)
1090                 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1091                                   intel_dp->aux.ddc.dev.kobj.name);
1092         intel_connector_unregister(intel_connector);
1093 }
1094
1095 static void
1096 skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
1097 {
1098         u32 ctrl1;
1099
1100         memset(&pipe_config->dpll_hw_state, 0,
1101                sizeof(pipe_config->dpll_hw_state));
1102
1103         pipe_config->ddi_pll_sel = SKL_DPLL0;
1104         pipe_config->dpll_hw_state.cfgcr1 = 0;
1105         pipe_config->dpll_hw_state.cfgcr2 = 0;
1106
1107         ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1108         switch (link_clock / 2) {
1109         case 81000:
1110                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
1111                                               SKL_DPLL0);
1112                 break;
1113         case 135000:
1114                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
1115                                               SKL_DPLL0);
1116                 break;
1117         case 270000:
1118                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
1119                                               SKL_DPLL0);
1120                 break;
1121         case 162000:
1122                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
1123                                               SKL_DPLL0);
1124                 break;
1125         /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1126         results in CDCLK change. Need to handle the change of CDCLK by
1127         disabling pipes and re-enabling them */
1128         case 108000:
1129                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
1130                                               SKL_DPLL0);
1131                 break;
1132         case 216000:
1133                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
1134                                               SKL_DPLL0);
1135                 break;
1136
1137         }
1138         pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1139 }
1140
1141 static void
1142 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
1143 {
1144         switch (link_bw) {
1145         case DP_LINK_BW_1_62:
1146                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1147                 break;
1148         case DP_LINK_BW_2_7:
1149                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1150                 break;
1151         case DP_LINK_BW_5_4:
1152                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1153                 break;
1154         }
1155 }
1156
1157 static int
1158 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1159 {
1160         if (intel_dp->num_sink_rates) {
1161                 *sink_rates = intel_dp->sink_rates;
1162                 return intel_dp->num_sink_rates;
1163         }
1164
1165         *sink_rates = default_rates;
1166
1167         return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1168 }
1169
1170 static int
1171 intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
1172 {
1173         if (IS_SKYLAKE(dev)) {
1174                 *source_rates = skl_rates;
1175                 return ARRAY_SIZE(skl_rates);
1176         } else if (IS_CHERRYVIEW(dev)) {
1177                 *source_rates = chv_rates;
1178                 return ARRAY_SIZE(chv_rates);
1179         }
1180
1181         *source_rates = default_rates;
1182
1183         if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
1184                 /* WaDisableHBR2:skl */
1185                 return (DP_LINK_BW_2_7 >> 3) + 1;
1186         else if (INTEL_INFO(dev)->gen >= 8 ||
1187             (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
1188                 return (DP_LINK_BW_5_4 >> 3) + 1;
1189         else
1190                 return (DP_LINK_BW_2_7 >> 3) + 1;
1191 }
1192
1193 static void
1194 intel_dp_set_clock(struct intel_encoder *encoder,
1195                    struct intel_crtc_state *pipe_config, int link_bw)
1196 {
1197         struct drm_device *dev = encoder->base.dev;
1198         const struct dp_link_dpll *divisor = NULL;
1199         int i, count = 0;
1200
1201         if (IS_G4X(dev)) {
1202                 divisor = gen4_dpll;
1203                 count = ARRAY_SIZE(gen4_dpll);
1204         } else if (HAS_PCH_SPLIT(dev)) {
1205                 divisor = pch_dpll;
1206                 count = ARRAY_SIZE(pch_dpll);
1207         } else if (IS_CHERRYVIEW(dev)) {
1208                 divisor = chv_dpll;
1209                 count = ARRAY_SIZE(chv_dpll);
1210         } else if (IS_VALLEYVIEW(dev)) {
1211                 divisor = vlv_dpll;
1212                 count = ARRAY_SIZE(vlv_dpll);
1213         }
1214
1215         if (divisor && count) {
1216                 for (i = 0; i < count; i++) {
1217                         if (link_bw == divisor[i].link_bw) {
1218                                 pipe_config->dpll = divisor[i].dpll;
1219                                 pipe_config->clock_set = true;
1220                                 break;
1221                         }
1222                 }
1223         }
1224 }
1225
1226 static int intersect_rates(const int *source_rates, int source_len,
1227                            const int *sink_rates, int sink_len,
1228                            int *common_rates)
1229 {
1230         int i = 0, j = 0, k = 0;
1231
1232         while (i < source_len && j < sink_len) {
1233                 if (source_rates[i] == sink_rates[j]) {
1234                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1235                                 return k;
1236                         common_rates[k] = source_rates[i];
1237                         ++k;
1238                         ++i;
1239                         ++j;
1240                 } else if (source_rates[i] < sink_rates[j]) {
1241                         ++i;
1242                 } else {
1243                         ++j;
1244                 }
1245         }
1246         return k;
1247 }
1248
1249 static int intel_dp_common_rates(struct intel_dp *intel_dp,
1250                                  int *common_rates)
1251 {
1252         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1253         const int *source_rates, *sink_rates;
1254         int source_len, sink_len;
1255
1256         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1257         source_len = intel_dp_source_rates(dev, &source_rates);
1258
1259         return intersect_rates(source_rates, source_len,
1260                                sink_rates, sink_len,
1261                                common_rates);
1262 }
1263
1264 static void snprintf_int_array(char *str, size_t len,
1265                                const int *array, int nelem)
1266 {
1267         int i;
1268
1269         str[0] = '\0';
1270
1271         for (i = 0; i < nelem; i++) {
1272                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1273                 if (r >= len)
1274                         return;
1275                 str += r;
1276                 len -= r;
1277         }
1278 }
1279
1280 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1281 {
1282         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1283         const int *source_rates, *sink_rates;
1284         int source_len, sink_len, common_len;
1285         int common_rates[DP_MAX_SUPPORTED_RATES];
1286         char str[128]; /* FIXME: too big for stack? */
1287
1288         if ((drm_debug & DRM_UT_KMS) == 0)
1289                 return;
1290
1291         source_len = intel_dp_source_rates(dev, &source_rates);
1292         snprintf_int_array(str, sizeof(str), source_rates, source_len);
1293         DRM_DEBUG_KMS("source rates: %s\n", str);
1294
1295         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1296         snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1297         DRM_DEBUG_KMS("sink rates: %s\n", str);
1298
1299         common_len = intel_dp_common_rates(intel_dp, common_rates);
1300         snprintf_int_array(str, sizeof(str), common_rates, common_len);
1301         DRM_DEBUG_KMS("common rates: %s\n", str);
1302 }
1303
1304 static int rate_to_index(int find, const int *rates)
1305 {
1306         int i = 0;
1307
1308         for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1309                 if (find == rates[i])
1310                         break;
1311
1312         return i;
1313 }
1314
1315 int
1316 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1317 {
1318         int rates[DP_MAX_SUPPORTED_RATES] = {};
1319         int len;
1320
1321         len = intel_dp_common_rates(intel_dp, rates);
1322         if (WARN_ON(len <= 0))
1323                 return 162000;
1324
1325         return rates[rate_to_index(0, rates) - 1];
1326 }
1327
1328 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1329 {
1330         return rate_to_index(rate, intel_dp->sink_rates);
1331 }
1332
1333 bool
1334 intel_dp_compute_config(struct intel_encoder *encoder,
1335                         struct intel_crtc_state *pipe_config)
1336 {
1337         struct drm_device *dev = encoder->base.dev;
1338         struct drm_i915_private *dev_priv = dev->dev_private;
1339         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1340         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1341         enum port port = dp_to_dig_port(intel_dp)->port;
1342         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1343         struct intel_connector *intel_connector = intel_dp->attached_connector;
1344         int lane_count, clock;
1345         int min_lane_count = 1;
1346         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1347         /* Conveniently, the link BW constants become indices with a shift...*/
1348         int min_clock = 0;
1349         int max_clock;
1350         int bpp, mode_rate;
1351         int link_avail, link_clock;
1352         int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1353         int common_len;
1354
1355         common_len = intel_dp_common_rates(intel_dp, common_rates);
1356
1357         /* No common link rates between source and sink */
1358         WARN_ON(common_len <= 0);
1359
1360         max_clock = common_len - 1;
1361
1362         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1363                 pipe_config->has_pch_encoder = true;
1364
1365         pipe_config->has_dp_encoder = true;
1366         pipe_config->has_drrs = false;
1367         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1368
1369         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1370                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1371                                        adjusted_mode);
1372
1373                 if (INTEL_INFO(dev)->gen >= 9) {
1374                         int ret;
1375                         ret = skl_update_scaler_users(intel_crtc, pipe_config, NULL, NULL, 0);
1376                         if (ret)
1377                                 return ret;
1378                 }
1379
1380                 if (!HAS_PCH_SPLIT(dev))
1381                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1382                                                  intel_connector->panel.fitting_mode);
1383                 else
1384                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1385                                                 intel_connector->panel.fitting_mode);
1386         }
1387
1388         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1389                 return false;
1390
1391         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1392                       "max bw %d pixel clock %iKHz\n",
1393                       max_lane_count, common_rates[max_clock],
1394                       adjusted_mode->crtc_clock);
1395
1396         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1397          * bpc in between. */
1398         bpp = pipe_config->pipe_bpp;
1399         if (is_edp(intel_dp)) {
1400                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1401                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1402                                       dev_priv->vbt.edp_bpp);
1403                         bpp = dev_priv->vbt.edp_bpp;
1404                 }
1405
1406                 /*
1407                  * Use the maximum clock and number of lanes the eDP panel
1408                  * advertizes being capable of. The panels are generally
1409                  * designed to support only a single clock and lane
1410                  * configuration, and typically these values correspond to the
1411                  * native resolution of the panel.
1412                  */
1413                 min_lane_count = max_lane_count;
1414                 min_clock = max_clock;
1415         }
1416
1417         for (; bpp >= 6*3; bpp -= 2*3) {
1418                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1419                                                    bpp);
1420
1421                 for (clock = min_clock; clock <= max_clock; clock++) {
1422                         for (lane_count = min_lane_count;
1423                                 lane_count <= max_lane_count;
1424                                 lane_count <<= 1) {
1425
1426                                 link_clock = common_rates[clock];
1427                                 link_avail = intel_dp_max_data_rate(link_clock,
1428                                                                     lane_count);
1429
1430                                 if (mode_rate <= link_avail) {
1431                                         goto found;
1432                                 }
1433                         }
1434                 }
1435         }
1436
1437         return false;
1438
1439 found:
1440         if (intel_dp->color_range_auto) {
1441                 /*
1442                  * See:
1443                  * CEA-861-E - 5.1 Default Encoding Parameters
1444                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1445                  */
1446                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
1447                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
1448                 else
1449                         intel_dp->color_range = 0;
1450         }
1451
1452         if (intel_dp->color_range)
1453                 pipe_config->limited_color_range = true;
1454
1455         intel_dp->lane_count = lane_count;
1456
1457         if (intel_dp->num_sink_rates) {
1458                 intel_dp->link_bw = 0;
1459                 intel_dp->rate_select =
1460                         intel_dp_rate_select(intel_dp, common_rates[clock]);
1461         } else {
1462                 intel_dp->link_bw =
1463                         drm_dp_link_rate_to_bw_code(common_rates[clock]);
1464                 intel_dp->rate_select = 0;
1465         }
1466
1467         pipe_config->pipe_bpp = bpp;
1468         pipe_config->port_clock = common_rates[clock];
1469
1470         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1471                       intel_dp->link_bw, intel_dp->lane_count,
1472                       pipe_config->port_clock, bpp);
1473         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1474                       mode_rate, link_avail);
1475
1476         intel_link_compute_m_n(bpp, lane_count,
1477                                adjusted_mode->crtc_clock,
1478                                pipe_config->port_clock,
1479                                &pipe_config->dp_m_n);
1480
1481         if (intel_connector->panel.downclock_mode != NULL &&
1482                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1483                         pipe_config->has_drrs = true;
1484                         intel_link_compute_m_n(bpp, lane_count,
1485                                 intel_connector->panel.downclock_mode->clock,
1486                                 pipe_config->port_clock,
1487                                 &pipe_config->dp_m2_n2);
1488         }
1489
1490         if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1491                 skl_edp_set_pll_config(pipe_config, common_rates[clock]);
1492         else if (IS_BROXTON(dev))
1493                 /* handled in ddi */;
1494         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1495                 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1496         else
1497                 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1498
1499         return true;
1500 }
1501
1502 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1503 {
1504         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1505         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1506         struct drm_device *dev = crtc->base.dev;
1507         struct drm_i915_private *dev_priv = dev->dev_private;
1508         u32 dpa_ctl;
1509
1510         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1511                       crtc->config->port_clock);
1512         dpa_ctl = I915_READ(DP_A);
1513         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1514
1515         if (crtc->config->port_clock == 162000) {
1516                 /* For a long time we've carried around a ILK-DevA w/a for the
1517                  * 160MHz clock. If we're really unlucky, it's still required.
1518                  */
1519                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1520                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1521                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1522         } else {
1523                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1524                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1525         }
1526
1527         I915_WRITE(DP_A, dpa_ctl);
1528
1529         POSTING_READ(DP_A);
1530         udelay(500);
1531 }
1532
1533 static void intel_dp_prepare(struct intel_encoder *encoder)
1534 {
1535         struct drm_device *dev = encoder->base.dev;
1536         struct drm_i915_private *dev_priv = dev->dev_private;
1537         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1538         enum port port = dp_to_dig_port(intel_dp)->port;
1539         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1540         struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1541
1542         /*
1543          * There are four kinds of DP registers:
1544          *
1545          *      IBX PCH
1546          *      SNB CPU
1547          *      IVB CPU
1548          *      CPT PCH
1549          *
1550          * IBX PCH and CPU are the same for almost everything,
1551          * except that the CPU DP PLL is configured in this
1552          * register
1553          *
1554          * CPT PCH is quite different, having many bits moved
1555          * to the TRANS_DP_CTL register instead. That
1556          * configuration happens (oddly) in ironlake_pch_enable
1557          */
1558
1559         /* Preserve the BIOS-computed detected bit. This is
1560          * supposed to be read-only.
1561          */
1562         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1563
1564         /* Handle DP bits in common between all three register formats */
1565         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1566         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1567
1568         if (crtc->config->has_audio)
1569                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1570
1571         /* Split out the IBX/CPU vs CPT settings */
1572
1573         if (IS_GEN7(dev) && port == PORT_A) {
1574                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1575                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1576                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1577                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1578                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1579
1580                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1581                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1582
1583                 intel_dp->DP |= crtc->pipe << 29;
1584         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1585                 u32 trans_dp;
1586
1587                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1588
1589                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1590                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1591                         trans_dp |= TRANS_DP_ENH_FRAMING;
1592                 else
1593                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1594                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1595         } else {
1596                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1597                         intel_dp->DP |= intel_dp->color_range;
1598
1599                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1600                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1601                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1602                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1603                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1604
1605                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1606                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1607
1608                 if (IS_CHERRYVIEW(dev))
1609                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1610                 else if (crtc->pipe == PIPE_B)
1611                         intel_dp->DP |= DP_PIPEB_SELECT;
1612         }
1613 }
1614
1615 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1616 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1617
1618 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1619 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1620
1621 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1622 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1623
1624 static void wait_panel_status(struct intel_dp *intel_dp,
1625                                        u32 mask,
1626                                        u32 value)
1627 {
1628         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1629         struct drm_i915_private *dev_priv = dev->dev_private;
1630         u32 pp_stat_reg, pp_ctrl_reg;
1631
1632         lockdep_assert_held(&dev_priv->pps_mutex);
1633
1634         pp_stat_reg = _pp_stat_reg(intel_dp);
1635         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1636
1637         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1638                         mask, value,
1639                         I915_READ(pp_stat_reg),
1640                         I915_READ(pp_ctrl_reg));
1641
1642         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1643                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1644                                 I915_READ(pp_stat_reg),
1645                                 I915_READ(pp_ctrl_reg));
1646         }
1647
1648         DRM_DEBUG_KMS("Wait complete\n");
1649 }
1650
1651 static void wait_panel_on(struct intel_dp *intel_dp)
1652 {
1653         DRM_DEBUG_KMS("Wait for panel power on\n");
1654         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1655 }
1656
1657 static void wait_panel_off(struct intel_dp *intel_dp)
1658 {
1659         DRM_DEBUG_KMS("Wait for panel power off time\n");
1660         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1661 }
1662
1663 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1664 {
1665         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1666
1667         /* When we disable the VDD override bit last we have to do the manual
1668          * wait. */
1669         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1670                                        intel_dp->panel_power_cycle_delay);
1671
1672         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1673 }
1674
1675 static void wait_backlight_on(struct intel_dp *intel_dp)
1676 {
1677         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1678                                        intel_dp->backlight_on_delay);
1679 }
1680
1681 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1682 {
1683         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1684                                        intel_dp->backlight_off_delay);
1685 }
1686
1687 /* Read the current pp_control value, unlocking the register if it
1688  * is locked
1689  */
1690
1691 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1692 {
1693         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1694         struct drm_i915_private *dev_priv = dev->dev_private;
1695         u32 control;
1696
1697         lockdep_assert_held(&dev_priv->pps_mutex);
1698
1699         control = I915_READ(_pp_ctrl_reg(intel_dp));
1700         control &= ~PANEL_UNLOCK_MASK;
1701         control |= PANEL_UNLOCK_REGS;
1702         return control;
1703 }
1704
1705 /*
1706  * Must be paired with edp_panel_vdd_off().
1707  * Must hold pps_mutex around the whole on/off sequence.
1708  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1709  */
1710 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1711 {
1712         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1713         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1714         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1715         struct drm_i915_private *dev_priv = dev->dev_private;
1716         enum intel_display_power_domain power_domain;
1717         u32 pp;
1718         u32 pp_stat_reg, pp_ctrl_reg;
1719         bool need_to_disable = !intel_dp->want_panel_vdd;
1720
1721         lockdep_assert_held(&dev_priv->pps_mutex);
1722
1723         if (!is_edp(intel_dp))
1724                 return false;
1725
1726         cancel_delayed_work(&intel_dp->panel_vdd_work);
1727         intel_dp->want_panel_vdd = true;
1728
1729         if (edp_have_panel_vdd(intel_dp))
1730                 return need_to_disable;
1731
1732         power_domain = intel_display_port_power_domain(intel_encoder);
1733         intel_display_power_get(dev_priv, power_domain);
1734
1735         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1736                       port_name(intel_dig_port->port));
1737
1738         if (!edp_have_panel_power(intel_dp))
1739                 wait_panel_power_cycle(intel_dp);
1740
1741         pp = ironlake_get_pp_control(intel_dp);
1742         pp |= EDP_FORCE_VDD;
1743
1744         pp_stat_reg = _pp_stat_reg(intel_dp);
1745         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1746
1747         I915_WRITE(pp_ctrl_reg, pp);
1748         POSTING_READ(pp_ctrl_reg);
1749         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1750                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1751         /*
1752          * If the panel wasn't on, delay before accessing aux channel
1753          */
1754         if (!edp_have_panel_power(intel_dp)) {
1755                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1756                               port_name(intel_dig_port->port));
1757                 msleep(intel_dp->panel_power_up_delay);
1758         }
1759
1760         return need_to_disable;
1761 }
1762
1763 /*
1764  * Must be paired with intel_edp_panel_vdd_off() or
1765  * intel_edp_panel_off().
1766  * Nested calls to these functions are not allowed since
1767  * we drop the lock. Caller must use some higher level
1768  * locking to prevent nested calls from other threads.
1769  */
1770 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1771 {
1772         bool vdd;
1773
1774         if (!is_edp(intel_dp))
1775                 return;
1776
1777         pps_lock(intel_dp);
1778         vdd = edp_panel_vdd_on(intel_dp);
1779         pps_unlock(intel_dp);
1780
1781         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1782              port_name(dp_to_dig_port(intel_dp)->port));
1783 }
1784
1785 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1786 {
1787         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1788         struct drm_i915_private *dev_priv = dev->dev_private;
1789         struct intel_digital_port *intel_dig_port =
1790                 dp_to_dig_port(intel_dp);
1791         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1792         enum intel_display_power_domain power_domain;
1793         u32 pp;
1794         u32 pp_stat_reg, pp_ctrl_reg;
1795
1796         lockdep_assert_held(&dev_priv->pps_mutex);
1797
1798         WARN_ON(intel_dp->want_panel_vdd);
1799
1800         if (!edp_have_panel_vdd(intel_dp))
1801                 return;
1802
1803         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1804                       port_name(intel_dig_port->port));
1805
1806         pp = ironlake_get_pp_control(intel_dp);
1807         pp &= ~EDP_FORCE_VDD;
1808
1809         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1810         pp_stat_reg = _pp_stat_reg(intel_dp);
1811
1812         I915_WRITE(pp_ctrl_reg, pp);
1813         POSTING_READ(pp_ctrl_reg);
1814
1815         /* Make sure sequencer is idle before allowing subsequent activity */
1816         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1817         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1818
1819         if ((pp & POWER_TARGET_ON) == 0)
1820                 intel_dp->last_power_cycle = jiffies;
1821
1822         power_domain = intel_display_port_power_domain(intel_encoder);
1823         intel_display_power_put(dev_priv, power_domain);
1824 }
1825
1826 static void edp_panel_vdd_work(struct work_struct *__work)
1827 {
1828         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1829                                                  struct intel_dp, panel_vdd_work);
1830
1831         pps_lock(intel_dp);
1832         if (!intel_dp->want_panel_vdd)
1833                 edp_panel_vdd_off_sync(intel_dp);
1834         pps_unlock(intel_dp);
1835 }
1836
1837 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1838 {
1839         unsigned long delay;
1840
1841         /*
1842          * Queue the timer to fire a long time from now (relative to the power
1843          * down delay) to keep the panel power up across a sequence of
1844          * operations.
1845          */
1846         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1847         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1848 }
1849
1850 /*
1851  * Must be paired with edp_panel_vdd_on().
1852  * Must hold pps_mutex around the whole on/off sequence.
1853  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1854  */
1855 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1856 {
1857         struct drm_i915_private *dev_priv =
1858                 intel_dp_to_dev(intel_dp)->dev_private;
1859
1860         lockdep_assert_held(&dev_priv->pps_mutex);
1861
1862         if (!is_edp(intel_dp))
1863                 return;
1864
1865         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1866              port_name(dp_to_dig_port(intel_dp)->port));
1867
1868         intel_dp->want_panel_vdd = false;
1869
1870         if (sync)
1871                 edp_panel_vdd_off_sync(intel_dp);
1872         else
1873                 edp_panel_vdd_schedule_off(intel_dp);
1874 }
1875
1876 static void edp_panel_on(struct intel_dp *intel_dp)
1877 {
1878         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1879         struct drm_i915_private *dev_priv = dev->dev_private;
1880         u32 pp;
1881         u32 pp_ctrl_reg;
1882
1883         lockdep_assert_held(&dev_priv->pps_mutex);
1884
1885         if (!is_edp(intel_dp))
1886                 return;
1887
1888         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1889                       port_name(dp_to_dig_port(intel_dp)->port));
1890
1891         if (WARN(edp_have_panel_power(intel_dp),
1892                  "eDP port %c panel power already on\n",
1893                  port_name(dp_to_dig_port(intel_dp)->port)))
1894                 return;
1895
1896         wait_panel_power_cycle(intel_dp);
1897
1898         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1899         pp = ironlake_get_pp_control(intel_dp);
1900         if (IS_GEN5(dev)) {
1901                 /* ILK workaround: disable reset around power sequence */
1902                 pp &= ~PANEL_POWER_RESET;
1903                 I915_WRITE(pp_ctrl_reg, pp);
1904                 POSTING_READ(pp_ctrl_reg);
1905         }
1906
1907         pp |= POWER_TARGET_ON;
1908         if (!IS_GEN5(dev))
1909                 pp |= PANEL_POWER_RESET;
1910
1911         I915_WRITE(pp_ctrl_reg, pp);
1912         POSTING_READ(pp_ctrl_reg);
1913
1914         wait_panel_on(intel_dp);
1915         intel_dp->last_power_on = jiffies;
1916
1917         if (IS_GEN5(dev)) {
1918                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1919                 I915_WRITE(pp_ctrl_reg, pp);
1920                 POSTING_READ(pp_ctrl_reg);
1921         }
1922 }
1923
1924 void intel_edp_panel_on(struct intel_dp *intel_dp)
1925 {
1926         if (!is_edp(intel_dp))
1927                 return;
1928
1929         pps_lock(intel_dp);
1930         edp_panel_on(intel_dp);
1931         pps_unlock(intel_dp);
1932 }
1933
1934
1935 static void edp_panel_off(struct intel_dp *intel_dp)
1936 {
1937         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1938         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1939         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1940         struct drm_i915_private *dev_priv = dev->dev_private;
1941         enum intel_display_power_domain power_domain;
1942         u32 pp;
1943         u32 pp_ctrl_reg;
1944
1945         lockdep_assert_held(&dev_priv->pps_mutex);
1946
1947         if (!is_edp(intel_dp))
1948                 return;
1949
1950         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1951                       port_name(dp_to_dig_port(intel_dp)->port));
1952
1953         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1954              port_name(dp_to_dig_port(intel_dp)->port));
1955
1956         pp = ironlake_get_pp_control(intel_dp);
1957         /* We need to switch off panel power _and_ force vdd, for otherwise some
1958          * panels get very unhappy and cease to work. */
1959         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1960                 EDP_BLC_ENABLE);
1961
1962         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1963
1964         intel_dp->want_panel_vdd = false;
1965
1966         I915_WRITE(pp_ctrl_reg, pp);
1967         POSTING_READ(pp_ctrl_reg);
1968
1969         intel_dp->last_power_cycle = jiffies;
1970         wait_panel_off(intel_dp);
1971
1972         /* We got a reference when we enabled the VDD. */
1973         power_domain = intel_display_port_power_domain(intel_encoder);
1974         intel_display_power_put(dev_priv, power_domain);
1975 }
1976
1977 void intel_edp_panel_off(struct intel_dp *intel_dp)
1978 {
1979         if (!is_edp(intel_dp))
1980                 return;
1981
1982         pps_lock(intel_dp);
1983         edp_panel_off(intel_dp);
1984         pps_unlock(intel_dp);
1985 }
1986
1987 /* Enable backlight in the panel power control. */
1988 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1989 {
1990         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1991         struct drm_device *dev = intel_dig_port->base.base.dev;
1992         struct drm_i915_private *dev_priv = dev->dev_private;
1993         u32 pp;
1994         u32 pp_ctrl_reg;
1995
1996         /*
1997          * If we enable the backlight right away following a panel power
1998          * on, we may see slight flicker as the panel syncs with the eDP
1999          * link.  So delay a bit to make sure the image is solid before
2000          * allowing it to appear.
2001          */
2002         wait_backlight_on(intel_dp);
2003
2004         pps_lock(intel_dp);
2005
2006         pp = ironlake_get_pp_control(intel_dp);
2007         pp |= EDP_BLC_ENABLE;
2008
2009         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2010
2011         I915_WRITE(pp_ctrl_reg, pp);
2012         POSTING_READ(pp_ctrl_reg);
2013
2014         pps_unlock(intel_dp);
2015 }
2016
2017 /* Enable backlight PWM and backlight PP control. */
2018 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2019 {
2020         if (!is_edp(intel_dp))
2021                 return;
2022
2023         DRM_DEBUG_KMS("\n");
2024
2025         intel_panel_enable_backlight(intel_dp->attached_connector);
2026         _intel_edp_backlight_on(intel_dp);
2027 }
2028
2029 /* Disable backlight in the panel power control. */
2030 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2031 {
2032         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2033         struct drm_i915_private *dev_priv = dev->dev_private;
2034         u32 pp;
2035         u32 pp_ctrl_reg;
2036
2037         if (!is_edp(intel_dp))
2038                 return;
2039
2040         pps_lock(intel_dp);
2041
2042         pp = ironlake_get_pp_control(intel_dp);
2043         pp &= ~EDP_BLC_ENABLE;
2044
2045         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2046
2047         I915_WRITE(pp_ctrl_reg, pp);
2048         POSTING_READ(pp_ctrl_reg);
2049
2050         pps_unlock(intel_dp);
2051
2052         intel_dp->last_backlight_off = jiffies;
2053         edp_wait_backlight_off(intel_dp);
2054 }
2055
2056 /* Disable backlight PP control and backlight PWM. */
2057 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2058 {
2059         if (!is_edp(intel_dp))
2060                 return;
2061
2062         DRM_DEBUG_KMS("\n");
2063
2064         _intel_edp_backlight_off(intel_dp);
2065         intel_panel_disable_backlight(intel_dp->attached_connector);
2066 }
2067
2068 /*
2069  * Hook for controlling the panel power control backlight through the bl_power
2070  * sysfs attribute. Take care to handle multiple calls.
2071  */
2072 static void intel_edp_backlight_power(struct intel_connector *connector,
2073                                       bool enable)
2074 {
2075         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2076         bool is_enabled;
2077
2078         pps_lock(intel_dp);
2079         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2080         pps_unlock(intel_dp);
2081
2082         if (is_enabled == enable)
2083                 return;
2084
2085         DRM_DEBUG_KMS("panel power control backlight %s\n",
2086                       enable ? "enable" : "disable");
2087
2088         if (enable)
2089                 _intel_edp_backlight_on(intel_dp);
2090         else
2091                 _intel_edp_backlight_off(intel_dp);
2092 }
2093
2094 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2095 {
2096         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2097         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2098         struct drm_device *dev = crtc->dev;
2099         struct drm_i915_private *dev_priv = dev->dev_private;
2100         u32 dpa_ctl;
2101
2102         assert_pipe_disabled(dev_priv,
2103                              to_intel_crtc(crtc)->pipe);
2104
2105         DRM_DEBUG_KMS("\n");
2106         dpa_ctl = I915_READ(DP_A);
2107         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
2108         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2109
2110         /* We don't adjust intel_dp->DP while tearing down the link, to
2111          * facilitate link retraining (e.g. after hotplug). Hence clear all
2112          * enable bits here to ensure that we don't enable too much. */
2113         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
2114         intel_dp->DP |= DP_PLL_ENABLE;
2115         I915_WRITE(DP_A, intel_dp->DP);
2116         POSTING_READ(DP_A);
2117         udelay(200);
2118 }
2119
2120 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2121 {
2122         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2123         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2124         struct drm_device *dev = crtc->dev;
2125         struct drm_i915_private *dev_priv = dev->dev_private;
2126         u32 dpa_ctl;
2127
2128         assert_pipe_disabled(dev_priv,
2129                              to_intel_crtc(crtc)->pipe);
2130
2131         dpa_ctl = I915_READ(DP_A);
2132         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
2133              "dp pll off, should be on\n");
2134         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2135
2136         /* We can't rely on the value tracked for the DP register in
2137          * intel_dp->DP because link_down must not change that (otherwise link
2138          * re-training will fail. */
2139         dpa_ctl &= ~DP_PLL_ENABLE;
2140         I915_WRITE(DP_A, dpa_ctl);
2141         POSTING_READ(DP_A);
2142         udelay(200);
2143 }
2144
2145 /* If the sink supports it, try to set the power state appropriately */
2146 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2147 {
2148         int ret, i;
2149
2150         /* Should have a valid DPCD by this point */
2151         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2152                 return;
2153
2154         if (mode != DRM_MODE_DPMS_ON) {
2155                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2156                                          DP_SET_POWER_D3);
2157         } else {
2158                 /*
2159                  * When turning on, we need to retry for 1ms to give the sink
2160                  * time to wake up.
2161                  */
2162                 for (i = 0; i < 3; i++) {
2163                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2164                                                  DP_SET_POWER_D0);
2165                         if (ret == 1)
2166                                 break;
2167                         msleep(1);
2168                 }
2169         }
2170
2171         if (ret != 1)
2172                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2173                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2174 }
2175
2176 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2177                                   enum pipe *pipe)
2178 {
2179         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2180         enum port port = dp_to_dig_port(intel_dp)->port;
2181         struct drm_device *dev = encoder->base.dev;
2182         struct drm_i915_private *dev_priv = dev->dev_private;
2183         enum intel_display_power_domain power_domain;
2184         u32 tmp;
2185
2186         power_domain = intel_display_port_power_domain(encoder);
2187         if (!intel_display_power_is_enabled(dev_priv, power_domain))
2188                 return false;
2189
2190         tmp = I915_READ(intel_dp->output_reg);
2191
2192         if (!(tmp & DP_PORT_EN))
2193                 return false;
2194
2195         if (IS_GEN7(dev) && port == PORT_A) {
2196                 *pipe = PORT_TO_PIPE_CPT(tmp);
2197         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2198                 enum pipe p;
2199
2200                 for_each_pipe(dev_priv, p) {
2201                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2202                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2203                                 *pipe = p;
2204                                 return true;
2205                         }
2206                 }
2207
2208                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2209                               intel_dp->output_reg);
2210         } else if (IS_CHERRYVIEW(dev)) {
2211                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2212         } else {
2213                 *pipe = PORT_TO_PIPE(tmp);
2214         }
2215
2216         return true;
2217 }
2218
2219 static void intel_dp_get_config(struct intel_encoder *encoder,
2220                                 struct intel_crtc_state *pipe_config)
2221 {
2222         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2223         u32 tmp, flags = 0;
2224         struct drm_device *dev = encoder->base.dev;
2225         struct drm_i915_private *dev_priv = dev->dev_private;
2226         enum port port = dp_to_dig_port(intel_dp)->port;
2227         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2228         int dotclock;
2229
2230         tmp = I915_READ(intel_dp->output_reg);
2231
2232         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2233
2234         if (HAS_PCH_CPT(dev) && port != PORT_A) {
2235                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2236                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2237                         flags |= DRM_MODE_FLAG_PHSYNC;
2238                 else
2239                         flags |= DRM_MODE_FLAG_NHSYNC;
2240
2241                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2242                         flags |= DRM_MODE_FLAG_PVSYNC;
2243                 else
2244                         flags |= DRM_MODE_FLAG_NVSYNC;
2245         } else {
2246                 if (tmp & DP_SYNC_HS_HIGH)
2247                         flags |= DRM_MODE_FLAG_PHSYNC;
2248                 else
2249                         flags |= DRM_MODE_FLAG_NHSYNC;
2250
2251                 if (tmp & DP_SYNC_VS_HIGH)
2252                         flags |= DRM_MODE_FLAG_PVSYNC;
2253                 else
2254                         flags |= DRM_MODE_FLAG_NVSYNC;
2255         }
2256
2257         pipe_config->base.adjusted_mode.flags |= flags;
2258
2259         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2260             tmp & DP_COLOR_RANGE_16_235)
2261                 pipe_config->limited_color_range = true;
2262
2263         pipe_config->has_dp_encoder = true;
2264
2265         intel_dp_get_m_n(crtc, pipe_config);
2266
2267         if (port == PORT_A) {
2268                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2269                         pipe_config->port_clock = 162000;
2270                 else
2271                         pipe_config->port_clock = 270000;
2272         }
2273
2274         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2275                                             &pipe_config->dp_m_n);
2276
2277         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2278                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2279
2280         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2281
2282         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2283             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2284                 /*
2285                  * This is a big fat ugly hack.
2286                  *
2287                  * Some machines in UEFI boot mode provide us a VBT that has 18
2288                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2289                  * unknown we fail to light up. Yet the same BIOS boots up with
2290                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2291                  * max, not what it tells us to use.
2292                  *
2293                  * Note: This will still be broken if the eDP panel is not lit
2294                  * up by the BIOS, and thus we can't get the mode at module
2295                  * load.
2296                  */
2297                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2298                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2299                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2300         }
2301 }
2302
2303 static void intel_disable_dp(struct intel_encoder *encoder)
2304 {
2305         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2306         struct drm_device *dev = encoder->base.dev;
2307         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2308
2309         if (crtc->config->has_audio)
2310                 intel_audio_codec_disable(encoder);
2311
2312         if (HAS_PSR(dev) && !HAS_DDI(dev))
2313                 intel_psr_disable(intel_dp);
2314
2315         /* Make sure the panel is off before trying to change the mode. But also
2316          * ensure that we have vdd while we switch off the panel. */
2317         intel_edp_panel_vdd_on(intel_dp);
2318         intel_edp_backlight_off(intel_dp);
2319         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2320         intel_edp_panel_off(intel_dp);
2321
2322         /* disable the port before the pipe on g4x */
2323         if (INTEL_INFO(dev)->gen < 5)
2324                 intel_dp_link_down(intel_dp);
2325 }
2326
2327 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2328 {
2329         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2330         enum port port = dp_to_dig_port(intel_dp)->port;
2331
2332         intel_dp_link_down(intel_dp);
2333         if (port == PORT_A)
2334                 ironlake_edp_pll_off(intel_dp);
2335 }
2336
2337 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2338 {
2339         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2340
2341         intel_dp_link_down(intel_dp);
2342 }
2343
2344 static void chv_post_disable_dp(struct intel_encoder *encoder)
2345 {
2346         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2347         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2348         struct drm_device *dev = encoder->base.dev;
2349         struct drm_i915_private *dev_priv = dev->dev_private;
2350         struct intel_crtc *intel_crtc =
2351                 to_intel_crtc(encoder->base.crtc);
2352         enum dpio_channel ch = vlv_dport_to_channel(dport);
2353         enum pipe pipe = intel_crtc->pipe;
2354         u32 val;
2355
2356         intel_dp_link_down(intel_dp);
2357
2358         mutex_lock(&dev_priv->sb_lock);
2359
2360         /* Propagate soft reset to data lane reset */
2361         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2362         val |= CHV_PCS_REQ_SOFTRESET_EN;
2363         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2364
2365         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2366         val |= CHV_PCS_REQ_SOFTRESET_EN;
2367         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2368
2369         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2370         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2371         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2372
2373         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2374         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2375         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2376
2377         mutex_unlock(&dev_priv->sb_lock);
2378 }
2379
2380 static void
2381 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2382                          uint32_t *DP,
2383                          uint8_t dp_train_pat)
2384 {
2385         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2386         struct drm_device *dev = intel_dig_port->base.base.dev;
2387         struct drm_i915_private *dev_priv = dev->dev_private;
2388         enum port port = intel_dig_port->port;
2389
2390         if (HAS_DDI(dev)) {
2391                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2392
2393                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2394                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2395                 else
2396                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2397
2398                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2399                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2400                 case DP_TRAINING_PATTERN_DISABLE:
2401                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2402
2403                         break;
2404                 case DP_TRAINING_PATTERN_1:
2405                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2406                         break;
2407                 case DP_TRAINING_PATTERN_2:
2408                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2409                         break;
2410                 case DP_TRAINING_PATTERN_3:
2411                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2412                         break;
2413                 }
2414                 I915_WRITE(DP_TP_CTL(port), temp);
2415
2416         } else if ((IS_GEN7(dev) && port == PORT_A) ||
2417                    (HAS_PCH_CPT(dev) && port != PORT_A)) {
2418                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2419
2420                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2421                 case DP_TRAINING_PATTERN_DISABLE:
2422                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2423                         break;
2424                 case DP_TRAINING_PATTERN_1:
2425                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2426                         break;
2427                 case DP_TRAINING_PATTERN_2:
2428                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2429                         break;
2430                 case DP_TRAINING_PATTERN_3:
2431                         DRM_ERROR("DP training pattern 3 not supported\n");
2432                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2433                         break;
2434                 }
2435
2436         } else {
2437                 if (IS_CHERRYVIEW(dev))
2438                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2439                 else
2440                         *DP &= ~DP_LINK_TRAIN_MASK;
2441
2442                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2443                 case DP_TRAINING_PATTERN_DISABLE:
2444                         *DP |= DP_LINK_TRAIN_OFF;
2445                         break;
2446                 case DP_TRAINING_PATTERN_1:
2447                         *DP |= DP_LINK_TRAIN_PAT_1;
2448                         break;
2449                 case DP_TRAINING_PATTERN_2:
2450                         *DP |= DP_LINK_TRAIN_PAT_2;
2451                         break;
2452                 case DP_TRAINING_PATTERN_3:
2453                         if (IS_CHERRYVIEW(dev)) {
2454                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2455                         } else {
2456                                 DRM_ERROR("DP training pattern 3 not supported\n");
2457                                 *DP |= DP_LINK_TRAIN_PAT_2;
2458                         }
2459                         break;
2460                 }
2461         }
2462 }
2463
2464 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2465 {
2466         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2467         struct drm_i915_private *dev_priv = dev->dev_private;
2468
2469         /* enable with pattern 1 (as per spec) */
2470         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2471                                  DP_TRAINING_PATTERN_1);
2472
2473         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2474         POSTING_READ(intel_dp->output_reg);
2475
2476         /*
2477          * Magic for VLV/CHV. We _must_ first set up the register
2478          * without actually enabling the port, and then do another
2479          * write to enable the port. Otherwise link training will
2480          * fail when the power sequencer is freshly used for this port.
2481          */
2482         intel_dp->DP |= DP_PORT_EN;
2483
2484         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2485         POSTING_READ(intel_dp->output_reg);
2486 }
2487
2488 static void intel_enable_dp(struct intel_encoder *encoder)
2489 {
2490         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2491         struct drm_device *dev = encoder->base.dev;
2492         struct drm_i915_private *dev_priv = dev->dev_private;
2493         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2494         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2495         unsigned int lane_mask = 0x0;
2496
2497         if (WARN_ON(dp_reg & DP_PORT_EN))
2498                 return;
2499
2500         pps_lock(intel_dp);
2501
2502         if (IS_VALLEYVIEW(dev))
2503                 vlv_init_panel_power_sequencer(intel_dp);
2504
2505         intel_dp_enable_port(intel_dp);
2506
2507         edp_panel_vdd_on(intel_dp);
2508         edp_panel_on(intel_dp);
2509         edp_panel_vdd_off(intel_dp, true);
2510
2511         pps_unlock(intel_dp);
2512
2513         if (IS_VALLEYVIEW(dev))
2514                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2515                                     lane_mask);
2516
2517         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2518         intel_dp_start_link_train(intel_dp);
2519         intel_dp_complete_link_train(intel_dp);
2520         intel_dp_stop_link_train(intel_dp);
2521
2522         if (crtc->config->has_audio) {
2523                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2524                                  pipe_name(crtc->pipe));
2525                 intel_audio_codec_enable(encoder);
2526         }
2527 }
2528
2529 static void g4x_enable_dp(struct intel_encoder *encoder)
2530 {
2531         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2532
2533         intel_enable_dp(encoder);
2534         intel_edp_backlight_on(intel_dp);
2535 }
2536
2537 static void vlv_enable_dp(struct intel_encoder *encoder)
2538 {
2539         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2540
2541         intel_edp_backlight_on(intel_dp);
2542         intel_psr_enable(intel_dp);
2543 }
2544
2545 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2546 {
2547         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2548         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2549
2550         intel_dp_prepare(encoder);
2551
2552         /* Only ilk+ has port A */
2553         if (dport->port == PORT_A) {
2554                 ironlake_set_pll_cpu_edp(intel_dp);
2555                 ironlake_edp_pll_on(intel_dp);
2556         }
2557 }
2558
2559 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2560 {
2561         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2562         struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2563         enum pipe pipe = intel_dp->pps_pipe;
2564         int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2565
2566         edp_panel_vdd_off_sync(intel_dp);
2567
2568         /*
2569          * VLV seems to get confused when multiple power seqeuencers
2570          * have the same port selected (even if only one has power/vdd
2571          * enabled). The failure manifests as vlv_wait_port_ready() failing
2572          * CHV on the other hand doesn't seem to mind having the same port
2573          * selected in multiple power seqeuencers, but let's clear the
2574          * port select always when logically disconnecting a power sequencer
2575          * from a port.
2576          */
2577         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2578                       pipe_name(pipe), port_name(intel_dig_port->port));
2579         I915_WRITE(pp_on_reg, 0);
2580         POSTING_READ(pp_on_reg);
2581
2582         intel_dp->pps_pipe = INVALID_PIPE;
2583 }
2584
2585 static void vlv_steal_power_sequencer(struct drm_device *dev,
2586                                       enum pipe pipe)
2587 {
2588         struct drm_i915_private *dev_priv = dev->dev_private;
2589         struct intel_encoder *encoder;
2590
2591         lockdep_assert_held(&dev_priv->pps_mutex);
2592
2593         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2594                 return;
2595
2596         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2597                             base.head) {
2598                 struct intel_dp *intel_dp;
2599                 enum port port;
2600
2601                 if (encoder->type != INTEL_OUTPUT_EDP)
2602                         continue;
2603
2604                 intel_dp = enc_to_intel_dp(&encoder->base);
2605                 port = dp_to_dig_port(intel_dp)->port;
2606
2607                 if (intel_dp->pps_pipe != pipe)
2608                         continue;
2609
2610                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2611                               pipe_name(pipe), port_name(port));
2612
2613                 WARN(encoder->connectors_active,
2614                      "stealing pipe %c power sequencer from active eDP port %c\n",
2615                      pipe_name(pipe), port_name(port));
2616
2617                 /* make sure vdd is off before we steal it */
2618                 vlv_detach_power_sequencer(intel_dp);
2619         }
2620 }
2621
2622 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2623 {
2624         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2625         struct intel_encoder *encoder = &intel_dig_port->base;
2626         struct drm_device *dev = encoder->base.dev;
2627         struct drm_i915_private *dev_priv = dev->dev_private;
2628         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2629
2630         lockdep_assert_held(&dev_priv->pps_mutex);
2631
2632         if (!is_edp(intel_dp))
2633                 return;
2634
2635         if (intel_dp->pps_pipe == crtc->pipe)
2636                 return;
2637
2638         /*
2639          * If another power sequencer was being used on this
2640          * port previously make sure to turn off vdd there while
2641          * we still have control of it.
2642          */
2643         if (intel_dp->pps_pipe != INVALID_PIPE)
2644                 vlv_detach_power_sequencer(intel_dp);
2645
2646         /*
2647          * We may be stealing the power
2648          * sequencer from another port.
2649          */
2650         vlv_steal_power_sequencer(dev, crtc->pipe);
2651
2652         /* now it's all ours */
2653         intel_dp->pps_pipe = crtc->pipe;
2654
2655         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2656                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2657
2658         /* init power sequencer on this pipe and port */
2659         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2660         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2661 }
2662
2663 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2664 {
2665         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2666         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2667         struct drm_device *dev = encoder->base.dev;
2668         struct drm_i915_private *dev_priv = dev->dev_private;
2669         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2670         enum dpio_channel port = vlv_dport_to_channel(dport);
2671         int pipe = intel_crtc->pipe;
2672         u32 val;
2673
2674         mutex_lock(&dev_priv->sb_lock);
2675
2676         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2677         val = 0;
2678         if (pipe)
2679                 val |= (1<<21);
2680         else
2681                 val &= ~(1<<21);
2682         val |= 0x001000c4;
2683         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2684         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2685         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2686
2687         mutex_unlock(&dev_priv->sb_lock);
2688
2689         intel_enable_dp(encoder);
2690 }
2691
2692 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2693 {
2694         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2695         struct drm_device *dev = encoder->base.dev;
2696         struct drm_i915_private *dev_priv = dev->dev_private;
2697         struct intel_crtc *intel_crtc =
2698                 to_intel_crtc(encoder->base.crtc);
2699         enum dpio_channel port = vlv_dport_to_channel(dport);
2700         int pipe = intel_crtc->pipe;
2701
2702         intel_dp_prepare(encoder);
2703
2704         /* Program Tx lane resets to default */
2705         mutex_lock(&dev_priv->sb_lock);
2706         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2707                          DPIO_PCS_TX_LANE2_RESET |
2708                          DPIO_PCS_TX_LANE1_RESET);
2709         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2710                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2711                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2712                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2713                                  DPIO_PCS_CLK_SOFT_RESET);
2714
2715         /* Fix up inter-pair skew failure */
2716         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2717         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2718         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2719         mutex_unlock(&dev_priv->sb_lock);
2720 }
2721
2722 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2723 {
2724         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2725         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2726         struct drm_device *dev = encoder->base.dev;
2727         struct drm_i915_private *dev_priv = dev->dev_private;
2728         struct intel_crtc *intel_crtc =
2729                 to_intel_crtc(encoder->base.crtc);
2730         enum dpio_channel ch = vlv_dport_to_channel(dport);
2731         int pipe = intel_crtc->pipe;
2732         int data, i, stagger;
2733         u32 val;
2734
2735         mutex_lock(&dev_priv->sb_lock);
2736
2737         /* allow hardware to manage TX FIFO reset source */
2738         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2739         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2740         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2741
2742         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2743         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2744         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2745
2746         /* Deassert soft data lane reset*/
2747         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2748         val |= CHV_PCS_REQ_SOFTRESET_EN;
2749         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2750
2751         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2752         val |= CHV_PCS_REQ_SOFTRESET_EN;
2753         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2754
2755         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2756         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2757         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2758
2759         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2760         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2761         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2762
2763         /* Program Tx lane latency optimal setting*/
2764         for (i = 0; i < 4; i++) {
2765                 /* Set the upar bit */
2766                 data = (i == 1) ? 0x0 : 0x1;
2767                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2768                                 data << DPIO_UPAR_SHIFT);
2769         }
2770
2771         /* Data lane stagger programming */
2772         if (intel_crtc->config->port_clock > 270000)
2773                 stagger = 0x18;
2774         else if (intel_crtc->config->port_clock > 135000)
2775                 stagger = 0xd;
2776         else if (intel_crtc->config->port_clock > 67500)
2777                 stagger = 0x7;
2778         else if (intel_crtc->config->port_clock > 33750)
2779                 stagger = 0x4;
2780         else
2781                 stagger = 0x2;
2782
2783         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2784         val |= DPIO_TX2_STAGGER_MASK(0x1f);
2785         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2786
2787         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2788         val |= DPIO_TX2_STAGGER_MASK(0x1f);
2789         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2790
2791         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
2792                        DPIO_LANESTAGGER_STRAP(stagger) |
2793                        DPIO_LANESTAGGER_STRAP_OVRD |
2794                        DPIO_TX1_STAGGER_MASK(0x1f) |
2795                        DPIO_TX1_STAGGER_MULT(6) |
2796                        DPIO_TX2_STAGGER_MULT(0));
2797
2798         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
2799                        DPIO_LANESTAGGER_STRAP(stagger) |
2800                        DPIO_LANESTAGGER_STRAP_OVRD |
2801                        DPIO_TX1_STAGGER_MASK(0x1f) |
2802                        DPIO_TX1_STAGGER_MULT(7) |
2803                        DPIO_TX2_STAGGER_MULT(5));
2804
2805         mutex_unlock(&dev_priv->sb_lock);
2806
2807         intel_enable_dp(encoder);
2808 }
2809
2810 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2811 {
2812         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2813         struct drm_device *dev = encoder->base.dev;
2814         struct drm_i915_private *dev_priv = dev->dev_private;
2815         struct intel_crtc *intel_crtc =
2816                 to_intel_crtc(encoder->base.crtc);
2817         enum dpio_channel ch = vlv_dport_to_channel(dport);
2818         enum pipe pipe = intel_crtc->pipe;
2819         u32 val;
2820
2821         intel_dp_prepare(encoder);
2822
2823         mutex_lock(&dev_priv->sb_lock);
2824
2825         /* program left/right clock distribution */
2826         if (pipe != PIPE_B) {
2827                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2828                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2829                 if (ch == DPIO_CH0)
2830                         val |= CHV_BUFLEFTENA1_FORCE;
2831                 if (ch == DPIO_CH1)
2832                         val |= CHV_BUFRIGHTENA1_FORCE;
2833                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2834         } else {
2835                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2836                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2837                 if (ch == DPIO_CH0)
2838                         val |= CHV_BUFLEFTENA2_FORCE;
2839                 if (ch == DPIO_CH1)
2840                         val |= CHV_BUFRIGHTENA2_FORCE;
2841                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2842         }
2843
2844         /* program clock channel usage */
2845         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2846         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2847         if (pipe != PIPE_B)
2848                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2849         else
2850                 val |= CHV_PCS_USEDCLKCHANNEL;
2851         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2852
2853         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2854         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2855         if (pipe != PIPE_B)
2856                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2857         else
2858                 val |= CHV_PCS_USEDCLKCHANNEL;
2859         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2860
2861         /*
2862          * This a a bit weird since generally CL
2863          * matches the pipe, but here we need to
2864          * pick the CL based on the port.
2865          */
2866         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2867         if (pipe != PIPE_B)
2868                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2869         else
2870                 val |= CHV_CMN_USEDCLKCHANNEL;
2871         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2872
2873         mutex_unlock(&dev_priv->sb_lock);
2874 }
2875
2876 /*
2877  * Native read with retry for link status and receiver capability reads for
2878  * cases where the sink may still be asleep.
2879  *
2880  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2881  * supposed to retry 3 times per the spec.
2882  */
2883 static ssize_t
2884 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2885                         void *buffer, size_t size)
2886 {
2887         ssize_t ret;
2888         int i;
2889
2890         /*
2891          * Sometime we just get the same incorrect byte repeated
2892          * over the entire buffer. Doing just one throw away read
2893          * initially seems to "solve" it.
2894          */
2895         drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2896
2897         for (i = 0; i < 3; i++) {
2898                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2899                 if (ret == size)
2900                         return ret;
2901                 msleep(1);
2902         }
2903
2904         return ret;
2905 }
2906
2907 /*
2908  * Fetch AUX CH registers 0x202 - 0x207 which contain
2909  * link status information
2910  */
2911 static bool
2912 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2913 {
2914         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2915                                        DP_LANE0_1_STATUS,
2916                                        link_status,
2917                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2918 }
2919
2920 /* These are source-specific values. */
2921 static uint8_t
2922 intel_dp_voltage_max(struct intel_dp *intel_dp)
2923 {
2924         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2925         struct drm_i915_private *dev_priv = dev->dev_private;
2926         enum port port = dp_to_dig_port(intel_dp)->port;
2927
2928         if (IS_BROXTON(dev))
2929                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2930         else if (INTEL_INFO(dev)->gen >= 9) {
2931                 if (dev_priv->edp_low_vswing && port == PORT_A)
2932                         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2933                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2934         } else if (IS_VALLEYVIEW(dev))
2935                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2936         else if (IS_GEN7(dev) && port == PORT_A)
2937                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2938         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2939                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2940         else
2941                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2942 }
2943
2944 static uint8_t
2945 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2946 {
2947         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2948         enum port port = dp_to_dig_port(intel_dp)->port;
2949
2950         if (INTEL_INFO(dev)->gen >= 9) {
2951                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2952                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2953                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2954                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2955                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2956                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2957                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2958                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2959                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2960                 default:
2961                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2962                 }
2963         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2964                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2965                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2966                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2967                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2968                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2969                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2970                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2971                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2972                 default:
2973                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2974                 }
2975         } else if (IS_VALLEYVIEW(dev)) {
2976                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2977                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2978                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2979                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2980                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2981                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2982                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2983                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2984                 default:
2985                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2986                 }
2987         } else if (IS_GEN7(dev) && port == PORT_A) {
2988                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2989                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2990                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2991                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2992                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2993                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2994                 default:
2995                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2996                 }
2997         } else {
2998                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2999                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3000                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3001                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3002                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3003                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3004                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3005                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3006                 default:
3007                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3008                 }
3009         }
3010 }
3011
3012 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3013 {
3014         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3015         struct drm_i915_private *dev_priv = dev->dev_private;
3016         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3017         struct intel_crtc *intel_crtc =
3018                 to_intel_crtc(dport->base.base.crtc);
3019         unsigned long demph_reg_value, preemph_reg_value,
3020                 uniqtranscale_reg_value;
3021         uint8_t train_set = intel_dp->train_set[0];
3022         enum dpio_channel port = vlv_dport_to_channel(dport);
3023         int pipe = intel_crtc->pipe;
3024
3025         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3026         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3027                 preemph_reg_value = 0x0004000;
3028                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3029                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3030                         demph_reg_value = 0x2B405555;
3031                         uniqtranscale_reg_value = 0x552AB83A;
3032                         break;
3033                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3034                         demph_reg_value = 0x2B404040;
3035                         uniqtranscale_reg_value = 0x5548B83A;
3036                         break;
3037                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3038                         demph_reg_value = 0x2B245555;
3039                         uniqtranscale_reg_value = 0x5560B83A;
3040                         break;
3041                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3042                         demph_reg_value = 0x2B405555;
3043                         uniqtranscale_reg_value = 0x5598DA3A;
3044                         break;
3045                 default:
3046                         return 0;
3047                 }
3048                 break;
3049         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3050                 preemph_reg_value = 0x0002000;
3051                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3052                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3053                         demph_reg_value = 0x2B404040;
3054                         uniqtranscale_reg_value = 0x5552B83A;
3055                         break;
3056                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3057                         demph_reg_value = 0x2B404848;
3058                         uniqtranscale_reg_value = 0x5580B83A;
3059                         break;
3060                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3061                         demph_reg_value = 0x2B404040;
3062                         uniqtranscale_reg_value = 0x55ADDA3A;
3063                         break;
3064                 default:
3065                         return 0;
3066                 }
3067                 break;
3068         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3069                 preemph_reg_value = 0x0000000;
3070                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3071                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3072                         demph_reg_value = 0x2B305555;
3073                         uniqtranscale_reg_value = 0x5570B83A;
3074                         break;
3075                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3076                         demph_reg_value = 0x2B2B4040;
3077                         uniqtranscale_reg_value = 0x55ADDA3A;
3078                         break;
3079                 default:
3080                         return 0;
3081                 }
3082                 break;
3083         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3084                 preemph_reg_value = 0x0006000;
3085                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3086                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3087                         demph_reg_value = 0x1B405555;
3088                         uniqtranscale_reg_value = 0x55ADDA3A;
3089                         break;
3090                 default:
3091                         return 0;
3092                 }
3093                 break;
3094         default:
3095                 return 0;
3096         }
3097
3098         mutex_lock(&dev_priv->sb_lock);
3099         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3100         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3101         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3102                          uniqtranscale_reg_value);
3103         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3104         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3105         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3106         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
3107         mutex_unlock(&dev_priv->sb_lock);
3108
3109         return 0;
3110 }
3111
3112 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3113 {
3114         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3115         struct drm_i915_private *dev_priv = dev->dev_private;
3116         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3117         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3118         u32 deemph_reg_value, margin_reg_value, val;
3119         uint8_t train_set = intel_dp->train_set[0];
3120         enum dpio_channel ch = vlv_dport_to_channel(dport);
3121         enum pipe pipe = intel_crtc->pipe;
3122         int i;
3123
3124         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3125         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3126                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3127                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3128                         deemph_reg_value = 128;
3129                         margin_reg_value = 52;
3130                         break;
3131                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3132                         deemph_reg_value = 128;
3133                         margin_reg_value = 77;
3134                         break;
3135                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3136                         deemph_reg_value = 128;
3137                         margin_reg_value = 102;
3138                         break;
3139                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3140                         deemph_reg_value = 128;
3141                         margin_reg_value = 154;
3142                         /* FIXME extra to set for 1200 */
3143                         break;
3144                 default:
3145                         return 0;
3146                 }
3147                 break;
3148         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3149                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3150                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3151                         deemph_reg_value = 85;
3152                         margin_reg_value = 78;
3153                         break;
3154                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3155                         deemph_reg_value = 85;
3156                         margin_reg_value = 116;
3157                         break;
3158                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3159                         deemph_reg_value = 85;
3160                         margin_reg_value = 154;
3161                         break;
3162                 default:
3163                         return 0;
3164                 }
3165                 break;
3166         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3167                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3168                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3169                         deemph_reg_value = 64;
3170                         margin_reg_value = 104;
3171                         break;
3172                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3173                         deemph_reg_value = 64;
3174                         margin_reg_value = 154;
3175                         break;
3176                 default:
3177                         return 0;
3178                 }
3179                 break;
3180         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3181                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3182                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3183                         deemph_reg_value = 43;
3184                         margin_reg_value = 154;
3185                         break;
3186                 default:
3187                         return 0;
3188                 }
3189                 break;
3190         default:
3191                 return 0;
3192         }
3193
3194         mutex_lock(&dev_priv->sb_lock);
3195
3196         /* Clear calc init */
3197         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3198         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3199         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3200         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3201         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3202
3203         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3204         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3205         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3206         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3207         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3208
3209         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3210         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3211         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3212         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3213
3214         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3215         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3216         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3217         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3218
3219         /* Program swing deemph */
3220         for (i = 0; i < 4; i++) {
3221                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3222                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3223                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3224                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3225         }
3226
3227         /* Program swing margin */
3228         for (i = 0; i < 4; i++) {
3229                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3230                 val &= ~DPIO_SWING_MARGIN000_MASK;
3231                 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3232                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3233         }
3234
3235         /* Disable unique transition scale */
3236         for (i = 0; i < 4; i++) {
3237                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3238                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3239                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3240         }
3241
3242         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
3243                         == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
3244                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
3245                         == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
3246
3247                 /*
3248                  * The document said it needs to set bit 27 for ch0 and bit 26
3249                  * for ch1. Might be a typo in the doc.
3250                  * For now, for this unique transition scale selection, set bit
3251                  * 27 for ch0 and ch1.
3252                  */
3253                 for (i = 0; i < 4; i++) {
3254                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3255                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3256                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3257                 }
3258
3259                 for (i = 0; i < 4; i++) {
3260                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3261                         val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3262                         val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3263                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3264                 }
3265         }
3266
3267         /* Start swing calculation */
3268         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3269         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3270         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3271
3272         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3273         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3274         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3275
3276         /* LRC Bypass */
3277         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3278         val |= DPIO_LRC_BYPASS;
3279         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3280
3281         mutex_unlock(&dev_priv->sb_lock);
3282
3283         return 0;
3284 }
3285
3286 static void
3287 intel_get_adjust_train(struct intel_dp *intel_dp,
3288                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
3289 {
3290         uint8_t v = 0;
3291         uint8_t p = 0;
3292         int lane;
3293         uint8_t voltage_max;
3294         uint8_t preemph_max;
3295
3296         for (lane = 0; lane < intel_dp->lane_count; lane++) {
3297                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3298                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3299
3300                 if (this_v > v)
3301                         v = this_v;
3302                 if (this_p > p)
3303                         p = this_p;
3304         }
3305
3306         voltage_max = intel_dp_voltage_max(intel_dp);
3307         if (v >= voltage_max)
3308                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3309
3310         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3311         if (p >= preemph_max)
3312                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3313
3314         for (lane = 0; lane < 4; lane++)
3315                 intel_dp->train_set[lane] = v | p;
3316 }
3317
3318 static uint32_t
3319 gen4_signal_levels(uint8_t train_set)
3320 {
3321         uint32_t        signal_levels = 0;
3322
3323         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3324         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3325         default:
3326                 signal_levels |= DP_VOLTAGE_0_4;
3327                 break;
3328         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3329                 signal_levels |= DP_VOLTAGE_0_6;
3330                 break;
3331         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3332                 signal_levels |= DP_VOLTAGE_0_8;
3333                 break;
3334         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3335                 signal_levels |= DP_VOLTAGE_1_2;
3336                 break;
3337         }
3338         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3339         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3340         default:
3341                 signal_levels |= DP_PRE_EMPHASIS_0;
3342                 break;
3343         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3344                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3345                 break;
3346         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3347                 signal_levels |= DP_PRE_EMPHASIS_6;
3348                 break;
3349         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3350                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3351                 break;
3352         }
3353         return signal_levels;
3354 }
3355
3356 /* Gen6's DP voltage swing and pre-emphasis control */
3357 static uint32_t
3358 gen6_edp_signal_levels(uint8_t train_set)
3359 {
3360         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3361                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3362         switch (signal_levels) {
3363         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3364         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3365                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3366         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3367                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3368         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3369         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3370                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3371         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3372         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3373                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3374         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3375         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3376                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3377         default:
3378                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3379                               "0x%x\n", signal_levels);
3380                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3381         }
3382 }
3383
3384 /* Gen7's DP voltage swing and pre-emphasis control */
3385 static uint32_t
3386 gen7_edp_signal_levels(uint8_t train_set)
3387 {
3388         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3389                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3390         switch (signal_levels) {
3391         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3392                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3393         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3394                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3395         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3396                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3397
3398         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3399                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3400         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3401                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3402
3403         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3404                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3405         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3406                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3407
3408         default:
3409                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3410                               "0x%x\n", signal_levels);
3411                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3412         }
3413 }
3414
3415 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3416 static uint32_t
3417 hsw_signal_levels(uint8_t train_set)
3418 {
3419         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3420                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3421         switch (signal_levels) {
3422         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3423                 return DDI_BUF_TRANS_SELECT(0);
3424         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3425                 return DDI_BUF_TRANS_SELECT(1);
3426         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3427                 return DDI_BUF_TRANS_SELECT(2);
3428         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3429                 return DDI_BUF_TRANS_SELECT(3);
3430
3431         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3432                 return DDI_BUF_TRANS_SELECT(4);
3433         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3434                 return DDI_BUF_TRANS_SELECT(5);
3435         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3436                 return DDI_BUF_TRANS_SELECT(6);
3437
3438         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3439                 return DDI_BUF_TRANS_SELECT(7);
3440         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3441                 return DDI_BUF_TRANS_SELECT(8);
3442
3443         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3444                 return DDI_BUF_TRANS_SELECT(9);
3445         default:
3446                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3447                               "0x%x\n", signal_levels);
3448                 return DDI_BUF_TRANS_SELECT(0);
3449         }
3450 }
3451
3452 static void bxt_signal_levels(struct intel_dp *intel_dp)
3453 {
3454         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3455         enum port port = dport->port;
3456         struct drm_device *dev = dport->base.base.dev;
3457         struct intel_encoder *encoder = &dport->base;
3458         uint8_t train_set = intel_dp->train_set[0];
3459         uint32_t level = 0;
3460
3461         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3462                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3463         switch (signal_levels) {
3464         default:
3465                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emph level\n");
3466         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3467                 level = 0;
3468                 break;
3469         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3470                 level = 1;
3471                 break;
3472         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3473                 level = 2;
3474                 break;
3475         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3476                 level = 3;
3477                 break;
3478         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3479                 level = 4;
3480                 break;
3481         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3482                 level = 5;
3483                 break;
3484         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3485                 level = 6;
3486                 break;
3487         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3488                 level = 7;
3489                 break;
3490         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3491                 level = 8;
3492                 break;
3493         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3494                 level = 9;
3495                 break;
3496         }
3497
3498         bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
3499 }
3500
3501 /* Properly updates "DP" with the correct signal levels. */
3502 static void
3503 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3504 {
3505         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3506         enum port port = intel_dig_port->port;
3507         struct drm_device *dev = intel_dig_port->base.base.dev;
3508         uint32_t signal_levels, mask;
3509         uint8_t train_set = intel_dp->train_set[0];
3510
3511         if (IS_BROXTON(dev)) {
3512                 signal_levels = 0;
3513                 bxt_signal_levels(intel_dp);
3514                 mask = 0;
3515         } else if (HAS_DDI(dev)) {
3516                 signal_levels = hsw_signal_levels(train_set);
3517                 mask = DDI_BUF_EMP_MASK;
3518         } else if (IS_CHERRYVIEW(dev)) {
3519                 signal_levels = chv_signal_levels(intel_dp);
3520                 mask = 0;
3521         } else if (IS_VALLEYVIEW(dev)) {
3522                 signal_levels = vlv_signal_levels(intel_dp);
3523                 mask = 0;
3524         } else if (IS_GEN7(dev) && port == PORT_A) {
3525                 signal_levels = gen7_edp_signal_levels(train_set);
3526                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3527         } else if (IS_GEN6(dev) && port == PORT_A) {
3528                 signal_levels = gen6_edp_signal_levels(train_set);
3529                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3530         } else {
3531                 signal_levels = gen4_signal_levels(train_set);
3532                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3533         }
3534
3535         if (mask)
3536                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3537
3538         DRM_DEBUG_KMS("Using vswing level %d\n",
3539                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3540         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3541                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3542                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3543
3544         *DP = (*DP & ~mask) | signal_levels;
3545 }
3546
3547 static bool
3548 intel_dp_set_link_train(struct intel_dp *intel_dp,
3549                         uint32_t *DP,
3550                         uint8_t dp_train_pat)
3551 {
3552         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3553         struct drm_device *dev = intel_dig_port->base.base.dev;
3554         struct drm_i915_private *dev_priv = dev->dev_private;
3555         uint8_t buf[sizeof(intel_dp->train_set) + 1];
3556         int ret, len;
3557
3558         _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3559
3560         I915_WRITE(intel_dp->output_reg, *DP);
3561         POSTING_READ(intel_dp->output_reg);
3562
3563         buf[0] = dp_train_pat;
3564         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3565             DP_TRAINING_PATTERN_DISABLE) {
3566                 /* don't write DP_TRAINING_LANEx_SET on disable */
3567                 len = 1;
3568         } else {
3569                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3570                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3571                 len = intel_dp->lane_count + 1;
3572         }
3573
3574         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3575                                 buf, len);
3576
3577         return ret == len;
3578 }
3579
3580 static bool
3581 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3582                         uint8_t dp_train_pat)
3583 {
3584         if (!intel_dp->train_set_valid)
3585                 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3586         intel_dp_set_signal_levels(intel_dp, DP);
3587         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3588 }
3589
3590 static bool
3591 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3592                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
3593 {
3594         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3595         struct drm_device *dev = intel_dig_port->base.base.dev;
3596         struct drm_i915_private *dev_priv = dev->dev_private;
3597         int ret;
3598
3599         intel_get_adjust_train(intel_dp, link_status);
3600         intel_dp_set_signal_levels(intel_dp, DP);
3601
3602         I915_WRITE(intel_dp->output_reg, *DP);
3603         POSTING_READ(intel_dp->output_reg);
3604
3605         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3606                                 intel_dp->train_set, intel_dp->lane_count);
3607
3608         return ret == intel_dp->lane_count;
3609 }
3610
3611 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3612 {
3613         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3614         struct drm_device *dev = intel_dig_port->base.base.dev;
3615         struct drm_i915_private *dev_priv = dev->dev_private;
3616         enum port port = intel_dig_port->port;
3617         uint32_t val;
3618
3619         if (!HAS_DDI(dev))
3620                 return;
3621
3622         val = I915_READ(DP_TP_CTL(port));
3623         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3624         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3625         I915_WRITE(DP_TP_CTL(port), val);
3626
3627         /*
3628          * On PORT_A we can have only eDP in SST mode. There the only reason
3629          * we need to set idle transmission mode is to work around a HW issue
3630          * where we enable the pipe while not in idle link-training mode.
3631          * In this case there is requirement to wait for a minimum number of
3632          * idle patterns to be sent.
3633          */
3634         if (port == PORT_A)
3635                 return;
3636
3637         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3638                      1))
3639                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3640 }
3641
3642 /* Enable corresponding port and start training pattern 1 */
3643 void
3644 intel_dp_start_link_train(struct intel_dp *intel_dp)
3645 {
3646         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3647         struct drm_device *dev = encoder->dev;
3648         int i;
3649         uint8_t voltage;
3650         int voltage_tries, loop_tries;
3651         uint32_t DP = intel_dp->DP;
3652         uint8_t link_config[2];
3653
3654         if (HAS_DDI(dev))
3655                 intel_ddi_prepare_link_retrain(encoder);
3656
3657         /* Write the link configuration data */
3658         link_config[0] = intel_dp->link_bw;
3659         link_config[1] = intel_dp->lane_count;
3660         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3661                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3662         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3663         if (intel_dp->num_sink_rates)
3664                 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
3665                                 &intel_dp->rate_select, 1);
3666
3667         link_config[0] = 0;
3668         link_config[1] = DP_SET_ANSI_8B10B;
3669         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3670
3671         DP |= DP_PORT_EN;
3672
3673         /* clock recovery */
3674         if (!intel_dp_reset_link_train(intel_dp, &DP,
3675                                        DP_TRAINING_PATTERN_1 |
3676                                        DP_LINK_SCRAMBLING_DISABLE)) {
3677                 DRM_ERROR("failed to enable link training\n");
3678                 return;
3679         }
3680
3681         voltage = 0xff;
3682         voltage_tries = 0;
3683         loop_tries = 0;
3684         for (;;) {
3685                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3686
3687                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3688                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3689                         DRM_ERROR("failed to get link status\n");
3690                         break;
3691                 }
3692
3693                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3694                         DRM_DEBUG_KMS("clock recovery OK\n");
3695                         break;
3696                 }
3697
3698                 /*
3699                  * if we used previously trained voltage and pre-emphasis values
3700                  * and we don't get clock recovery, reset link training values
3701                  */
3702                 if (intel_dp->train_set_valid) {
3703                         DRM_DEBUG_KMS("clock recovery not ok, reset");
3704                         /* clear the flag as we are not reusing train set */
3705                         intel_dp->train_set_valid = false;
3706                         if (!intel_dp_reset_link_train(intel_dp, &DP,
3707                                                        DP_TRAINING_PATTERN_1 |
3708                                                        DP_LINK_SCRAMBLING_DISABLE)) {
3709                                 DRM_ERROR("failed to enable link training\n");
3710                                 return;
3711                         }
3712                         continue;
3713                 }
3714
3715                 /* Check to see if we've tried the max voltage */
3716                 for (i = 0; i < intel_dp->lane_count; i++)
3717                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3718                                 break;
3719                 if (i == intel_dp->lane_count) {
3720                         ++loop_tries;
3721                         if (loop_tries == 5) {
3722                                 DRM_ERROR("too many full retries, give up\n");
3723                                 break;
3724                         }
3725                         intel_dp_reset_link_train(intel_dp, &DP,
3726                                                   DP_TRAINING_PATTERN_1 |
3727                                                   DP_LINK_SCRAMBLING_DISABLE);
3728                         voltage_tries = 0;
3729                         continue;
3730                 }
3731
3732                 /* Check to see if we've tried the same voltage 5 times */
3733                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3734                         ++voltage_tries;
3735                         if (voltage_tries == 5) {
3736                                 DRM_ERROR("too many voltage retries, give up\n");
3737                                 break;
3738                         }
3739                 } else
3740                         voltage_tries = 0;
3741                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3742
3743                 /* Update training set as requested by target */
3744                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3745                         DRM_ERROR("failed to update link training\n");
3746                         break;
3747                 }
3748         }
3749
3750         intel_dp->DP = DP;
3751 }
3752
3753 void
3754 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3755 {
3756         bool channel_eq = false;
3757         int tries, cr_tries;
3758         uint32_t DP = intel_dp->DP;
3759         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3760
3761         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3762         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3763                 training_pattern = DP_TRAINING_PATTERN_3;
3764
3765         /* channel equalization */
3766         if (!intel_dp_set_link_train(intel_dp, &DP,
3767                                      training_pattern |
3768                                      DP_LINK_SCRAMBLING_DISABLE)) {
3769                 DRM_ERROR("failed to start channel equalization\n");
3770                 return;
3771         }
3772
3773         tries = 0;
3774         cr_tries = 0;
3775         channel_eq = false;
3776         for (;;) {
3777                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3778
3779                 if (cr_tries > 5) {
3780                         DRM_ERROR("failed to train DP, aborting\n");
3781                         break;
3782                 }
3783
3784                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3785                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3786                         DRM_ERROR("failed to get link status\n");
3787                         break;
3788                 }
3789
3790                 /* Make sure clock is still ok */
3791                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3792                         intel_dp->train_set_valid = false;
3793                         intel_dp_start_link_train(intel_dp);
3794                         intel_dp_set_link_train(intel_dp, &DP,
3795                                                 training_pattern |
3796                                                 DP_LINK_SCRAMBLING_DISABLE);
3797                         cr_tries++;
3798                         continue;
3799                 }
3800
3801                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3802                         channel_eq = true;
3803                         break;
3804                 }
3805
3806                 /* Try 5 times, then try clock recovery if that fails */
3807                 if (tries > 5) {
3808                         intel_dp->train_set_valid = false;
3809                         intel_dp_start_link_train(intel_dp);
3810                         intel_dp_set_link_train(intel_dp, &DP,
3811                                                 training_pattern |
3812                                                 DP_LINK_SCRAMBLING_DISABLE);
3813                         tries = 0;
3814                         cr_tries++;
3815                         continue;
3816                 }
3817
3818                 /* Update training set as requested by target */
3819                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3820                         DRM_ERROR("failed to update link training\n");
3821                         break;
3822                 }
3823                 ++tries;
3824         }
3825
3826         intel_dp_set_idle_link_train(intel_dp);
3827
3828         intel_dp->DP = DP;
3829
3830         if (channel_eq) {
3831                 intel_dp->train_set_valid = true;
3832                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3833         }
3834 }
3835
3836 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3837 {
3838         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3839                                 DP_TRAINING_PATTERN_DISABLE);
3840 }
3841
3842 static void
3843 intel_dp_link_down(struct intel_dp *intel_dp)
3844 {
3845         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3846         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3847         enum port port = intel_dig_port->port;
3848         struct drm_device *dev = intel_dig_port->base.base.dev;
3849         struct drm_i915_private *dev_priv = dev->dev_private;
3850         uint32_t DP = intel_dp->DP;
3851
3852         if (WARN_ON(HAS_DDI(dev)))
3853                 return;
3854
3855         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3856                 return;
3857
3858         DRM_DEBUG_KMS("\n");
3859
3860         if ((IS_GEN7(dev) && port == PORT_A) ||
3861             (HAS_PCH_CPT(dev) && port != PORT_A)) {
3862                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3863                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3864         } else {
3865                 if (IS_CHERRYVIEW(dev))
3866                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3867                 else
3868                         DP &= ~DP_LINK_TRAIN_MASK;
3869                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3870         }
3871         I915_WRITE(intel_dp->output_reg, DP);
3872         POSTING_READ(intel_dp->output_reg);
3873
3874         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3875         I915_WRITE(intel_dp->output_reg, DP);
3876         POSTING_READ(intel_dp->output_reg);
3877
3878         /*
3879          * HW workaround for IBX, we need to move the port
3880          * to transcoder A after disabling it to allow the
3881          * matching HDMI port to be enabled on transcoder A.
3882          */
3883         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3884                 /* always enable with pattern 1 (as per spec) */
3885                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3886                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3887                 I915_WRITE(intel_dp->output_reg, DP);
3888                 POSTING_READ(intel_dp->output_reg);
3889
3890                 DP &= ~DP_PORT_EN;
3891                 I915_WRITE(intel_dp->output_reg, DP);
3892                 POSTING_READ(intel_dp->output_reg);
3893         }
3894
3895         msleep(intel_dp->panel_power_down_delay);
3896 }
3897
3898 static bool
3899 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3900 {
3901         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3902         struct drm_device *dev = dig_port->base.base.dev;
3903         struct drm_i915_private *dev_priv = dev->dev_private;
3904         uint8_t rev;
3905
3906         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3907                                     sizeof(intel_dp->dpcd)) < 0)
3908                 return false; /* aux transfer failed */
3909
3910         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3911
3912         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3913                 return false; /* DPCD not present */
3914
3915         /* Check if the panel supports PSR */
3916         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3917         if (is_edp(intel_dp)) {
3918                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3919                                         intel_dp->psr_dpcd,
3920                                         sizeof(intel_dp->psr_dpcd));
3921                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3922                         dev_priv->psr.sink_support = true;
3923                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3924                 }
3925
3926                 if (INTEL_INFO(dev)->gen >= 9 &&
3927                         (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3928                         uint8_t frame_sync_cap;
3929
3930                         dev_priv->psr.sink_support = true;
3931                         intel_dp_dpcd_read_wake(&intel_dp->aux,
3932                                         DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3933                                         &frame_sync_cap, 1);
3934                         dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3935                         /* PSR2 needs frame sync as well */
3936                         dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3937                         DRM_DEBUG_KMS("PSR2 %s on sink",
3938                                 dev_priv->psr.psr2_support ? "supported" : "not supported");
3939                 }
3940         }
3941
3942         /* Training Pattern 3 support, both source and sink */
3943         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3944             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3945             (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
3946                 intel_dp->use_tps3 = true;
3947                 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3948         } else
3949                 intel_dp->use_tps3 = false;
3950
3951         /* Intermediate frequency support */
3952         if (is_edp(intel_dp) &&
3953             (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3954             (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3955             (rev >= 0x03)) { /* eDp v1.4 or higher */
3956                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3957                 int i;
3958
3959                 intel_dp_dpcd_read_wake(&intel_dp->aux,
3960                                 DP_SUPPORTED_LINK_RATES,
3961                                 sink_rates,
3962                                 sizeof(sink_rates));
3963
3964                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3965                         int val = le16_to_cpu(sink_rates[i]);
3966
3967                         if (val == 0)
3968                                 break;
3969
3970                         /* Value read is in kHz while drm clock is saved in deca-kHz */
3971                         intel_dp->sink_rates[i] = (val * 200) / 10;
3972                 }
3973                 intel_dp->num_sink_rates = i;
3974         }
3975
3976         intel_dp_print_rates(intel_dp);
3977
3978         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3979               DP_DWN_STRM_PORT_PRESENT))
3980                 return true; /* native DP sink */
3981
3982         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3983                 return true; /* no per-port downstream info */
3984
3985         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3986                                     intel_dp->downstream_ports,
3987                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3988                 return false; /* downstream port status fetch failed */
3989
3990         return true;
3991 }
3992
3993 static void
3994 intel_dp_probe_oui(struct intel_dp *intel_dp)
3995 {
3996         u8 buf[3];
3997
3998         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3999                 return;
4000
4001         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
4002                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
4003                               buf[0], buf[1], buf[2]);
4004
4005         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
4006                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
4007                               buf[0], buf[1], buf[2]);
4008 }
4009
4010 static bool
4011 intel_dp_probe_mst(struct intel_dp *intel_dp)
4012 {
4013         u8 buf[1];
4014
4015         if (!intel_dp->can_mst)
4016                 return false;
4017
4018         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4019                 return false;
4020
4021         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
4022                 if (buf[0] & DP_MST_CAP) {
4023                         DRM_DEBUG_KMS("Sink is MST capable\n");
4024                         intel_dp->is_mst = true;
4025                 } else {
4026                         DRM_DEBUG_KMS("Sink is not MST capable\n");
4027                         intel_dp->is_mst = false;
4028                 }
4029         }
4030
4031         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4032         return intel_dp->is_mst;
4033 }
4034
4035 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
4036 {
4037         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4038         struct drm_device *dev = intel_dig_port->base.base.dev;
4039         struct intel_crtc *intel_crtc =
4040                 to_intel_crtc(intel_dig_port->base.base.crtc);
4041         u8 buf;
4042         int test_crc_count;
4043         int attempts = 6;
4044
4045         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
4046                 return -EIO;
4047
4048         if (!(buf & DP_TEST_CRC_SUPPORTED))
4049                 return -ENOTTY;
4050
4051         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4052                 return -EIO;
4053
4054         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4055                                 buf | DP_TEST_SINK_START) < 0)
4056                 return -EIO;
4057
4058         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
4059                 return -EIO;
4060         test_crc_count = buf & DP_TEST_COUNT_MASK;
4061
4062         do {
4063                 if (drm_dp_dpcd_readb(&intel_dp->aux,
4064                                       DP_TEST_SINK_MISC, &buf) < 0)
4065                         return -EIO;
4066                 intel_wait_for_vblank(dev, intel_crtc->pipe);
4067         } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
4068
4069         if (attempts == 0) {
4070                 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
4071                 return -ETIMEDOUT;
4072         }
4073
4074         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
4075                 return -EIO;
4076
4077         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4078                 return -EIO;
4079         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4080                                buf & ~DP_TEST_SINK_START) < 0)
4081                 return -EIO;
4082
4083         return 0;
4084 }
4085
4086 static bool
4087 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4088 {
4089         return intel_dp_dpcd_read_wake(&intel_dp->aux,
4090                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
4091                                        sink_irq_vector, 1) == 1;
4092 }
4093
4094 static bool
4095 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4096 {
4097         int ret;
4098
4099         ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4100                                              DP_SINK_COUNT_ESI,
4101                                              sink_irq_vector, 14);
4102         if (ret != 14)
4103                 return false;
4104
4105         return true;
4106 }
4107
4108 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4109 {
4110         uint8_t test_result = DP_TEST_ACK;
4111         return test_result;
4112 }
4113
4114 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4115 {
4116         uint8_t test_result = DP_TEST_NAK;
4117         return test_result;
4118 }
4119
4120 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4121 {
4122         uint8_t test_result = DP_TEST_NAK;
4123         struct intel_connector *intel_connector = intel_dp->attached_connector;
4124         struct drm_connector *connector = &intel_connector->base;
4125
4126         if (intel_connector->detect_edid == NULL ||
4127             connector->edid_corrupt ||
4128             intel_dp->aux.i2c_defer_count > 6) {
4129                 /* Check EDID read for NACKs, DEFERs and corruption
4130                  * (DP CTS 1.2 Core r1.1)
4131                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4132                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4133                  *    4.2.2.6 : EDID corruption detected
4134                  * Use failsafe mode for all cases
4135                  */
4136                 if (intel_dp->aux.i2c_nack_count > 0 ||
4137                         intel_dp->aux.i2c_defer_count > 0)
4138                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4139                                       intel_dp->aux.i2c_nack_count,
4140                                       intel_dp->aux.i2c_defer_count);
4141                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4142         } else {
4143                 if (!drm_dp_dpcd_write(&intel_dp->aux,
4144                                         DP_TEST_EDID_CHECKSUM,
4145                                         &intel_connector->detect_edid->checksum,
4146                                         1))
4147                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4148
4149                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4150                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4151         }
4152
4153         /* Set test active flag here so userspace doesn't interrupt things */
4154         intel_dp->compliance_test_active = 1;
4155
4156         return test_result;
4157 }
4158
4159 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4160 {
4161         uint8_t test_result = DP_TEST_NAK;
4162         return test_result;
4163 }
4164
4165 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4166 {
4167         uint8_t response = DP_TEST_NAK;
4168         uint8_t rxdata = 0;
4169         int status = 0;
4170
4171         intel_dp->compliance_test_active = 0;
4172         intel_dp->compliance_test_type = 0;
4173         intel_dp->compliance_test_data = 0;
4174
4175         intel_dp->aux.i2c_nack_count = 0;
4176         intel_dp->aux.i2c_defer_count = 0;
4177
4178         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4179         if (status <= 0) {
4180                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4181                 goto update_status;
4182         }
4183
4184         switch (rxdata) {
4185         case DP_TEST_LINK_TRAINING:
4186                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4187                 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4188                 response = intel_dp_autotest_link_training(intel_dp);
4189                 break;
4190         case DP_TEST_LINK_VIDEO_PATTERN:
4191                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4192                 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4193                 response = intel_dp_autotest_video_pattern(intel_dp);
4194                 break;
4195         case DP_TEST_LINK_EDID_READ:
4196                 DRM_DEBUG_KMS("EDID test requested\n");
4197                 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4198                 response = intel_dp_autotest_edid(intel_dp);
4199                 break;
4200         case DP_TEST_LINK_PHY_TEST_PATTERN:
4201                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4202                 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4203                 response = intel_dp_autotest_phy_pattern(intel_dp);
4204                 break;
4205         default:
4206                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4207                 break;
4208         }
4209
4210 update_status:
4211         status = drm_dp_dpcd_write(&intel_dp->aux,
4212                                    DP_TEST_RESPONSE,
4213                                    &response, 1);
4214         if (status <= 0)
4215                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4216 }
4217
4218 static int
4219 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4220 {
4221         bool bret;
4222
4223         if (intel_dp->is_mst) {
4224                 u8 esi[16] = { 0 };
4225                 int ret = 0;
4226                 int retry;
4227                 bool handled;
4228                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4229 go_again:
4230                 if (bret == true) {
4231
4232                         /* check link status - esi[10] = 0x200c */
4233                         if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4234                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4235                                 intel_dp_start_link_train(intel_dp);
4236                                 intel_dp_complete_link_train(intel_dp);
4237                                 intel_dp_stop_link_train(intel_dp);
4238                         }
4239
4240                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4241                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4242
4243                         if (handled) {
4244                                 for (retry = 0; retry < 3; retry++) {
4245                                         int wret;
4246                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4247                                                                  DP_SINK_COUNT_ESI+1,
4248                                                                  &esi[1], 3);
4249                                         if (wret == 3) {
4250                                                 break;
4251                                         }
4252                                 }
4253
4254                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4255                                 if (bret == true) {
4256                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4257                                         goto go_again;
4258                                 }
4259                         } else
4260                                 ret = 0;
4261
4262                         return ret;
4263                 } else {
4264                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4265                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4266                         intel_dp->is_mst = false;
4267                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4268                         /* send a hotplug event */
4269                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4270                 }
4271         }
4272         return -EINVAL;
4273 }
4274
4275 /*
4276  * According to DP spec
4277  * 5.1.2:
4278  *  1. Read DPCD
4279  *  2. Configure link according to Receiver Capabilities
4280  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4281  *  4. Check link status on receipt of hot-plug interrupt
4282  */
4283 static void
4284 intel_dp_check_link_status(struct intel_dp *intel_dp)
4285 {
4286         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4287         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4288         u8 sink_irq_vector;
4289         u8 link_status[DP_LINK_STATUS_SIZE];
4290
4291         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4292
4293         if (!intel_encoder->connectors_active)
4294                 return;
4295
4296         if (WARN_ON(!intel_encoder->base.crtc))
4297                 return;
4298
4299         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4300                 return;
4301
4302         /* Try to read receiver status if the link appears to be up */
4303         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4304                 return;
4305         }
4306
4307         /* Now read the DPCD to see if it's actually running */
4308         if (!intel_dp_get_dpcd(intel_dp)) {
4309                 return;
4310         }
4311
4312         /* Try to read the source of the interrupt */
4313         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4314             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4315                 /* Clear interrupt source */
4316                 drm_dp_dpcd_writeb(&intel_dp->aux,
4317                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4318                                    sink_irq_vector);
4319
4320                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4321                         DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4322                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4323                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4324         }
4325
4326         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4327                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4328                               intel_encoder->base.name);
4329                 intel_dp_start_link_train(intel_dp);
4330                 intel_dp_complete_link_train(intel_dp);
4331                 intel_dp_stop_link_train(intel_dp);
4332         }
4333 }
4334
4335 /* XXX this is probably wrong for multiple downstream ports */
4336 static enum drm_connector_status
4337 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4338 {
4339         uint8_t *dpcd = intel_dp->dpcd;
4340         uint8_t type;
4341
4342         if (!intel_dp_get_dpcd(intel_dp))
4343                 return connector_status_disconnected;
4344
4345         /* if there's no downstream port, we're done */
4346         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4347                 return connector_status_connected;
4348
4349         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4350         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4351             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4352                 uint8_t reg;
4353
4354                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4355                                             &reg, 1) < 0)
4356                         return connector_status_unknown;
4357
4358                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4359                                               : connector_status_disconnected;
4360         }
4361
4362         /* If no HPD, poke DDC gently */
4363         if (drm_probe_ddc(&intel_dp->aux.ddc))
4364                 return connector_status_connected;
4365
4366         /* Well we tried, say unknown for unreliable port types */
4367         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4368                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4369                 if (type == DP_DS_PORT_TYPE_VGA ||
4370                     type == DP_DS_PORT_TYPE_NON_EDID)
4371                         return connector_status_unknown;
4372         } else {
4373                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4374                         DP_DWN_STRM_PORT_TYPE_MASK;
4375                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4376                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4377                         return connector_status_unknown;
4378         }
4379
4380         /* Anything else is out of spec, warn and ignore */
4381         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4382         return connector_status_disconnected;
4383 }
4384
4385 static enum drm_connector_status
4386 edp_detect(struct intel_dp *intel_dp)
4387 {
4388         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4389         enum drm_connector_status status;
4390
4391         status = intel_panel_detect(dev);
4392         if (status == connector_status_unknown)
4393                 status = connector_status_connected;
4394
4395         return status;
4396 }
4397
4398 static enum drm_connector_status
4399 ironlake_dp_detect(struct intel_dp *intel_dp)
4400 {
4401         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4402         struct drm_i915_private *dev_priv = dev->dev_private;
4403         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4404
4405         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4406                 return connector_status_disconnected;
4407
4408         return intel_dp_detect_dpcd(intel_dp);
4409 }
4410
4411 static int g4x_digital_port_connected(struct drm_device *dev,
4412                                        struct intel_digital_port *intel_dig_port)
4413 {
4414         struct drm_i915_private *dev_priv = dev->dev_private;
4415         uint32_t bit;
4416
4417         if (IS_VALLEYVIEW(dev)) {
4418                 switch (intel_dig_port->port) {
4419                 case PORT_B:
4420                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4421                         break;
4422                 case PORT_C:
4423                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4424                         break;
4425                 case PORT_D:
4426                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4427                         break;
4428                 default:
4429                         return -EINVAL;
4430                 }
4431         } else {
4432                 switch (intel_dig_port->port) {
4433                 case PORT_B:
4434                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4435                         break;
4436                 case PORT_C:
4437                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4438                         break;
4439                 case PORT_D:
4440                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4441                         break;
4442                 default:
4443                         return -EINVAL;
4444                 }
4445         }
4446
4447         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
4448                 return 0;
4449         return 1;
4450 }
4451
4452 static enum drm_connector_status
4453 g4x_dp_detect(struct intel_dp *intel_dp)
4454 {
4455         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4456         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4457         int ret;
4458
4459         /* Can't disconnect eDP, but you can close the lid... */
4460         if (is_edp(intel_dp)) {
4461                 enum drm_connector_status status;
4462
4463                 status = intel_panel_detect(dev);
4464                 if (status == connector_status_unknown)
4465                         status = connector_status_connected;
4466                 return status;
4467         }
4468
4469         ret = g4x_digital_port_connected(dev, intel_dig_port);
4470         if (ret == -EINVAL)
4471                 return connector_status_unknown;
4472         else if (ret == 0)
4473                 return connector_status_disconnected;
4474
4475         return intel_dp_detect_dpcd(intel_dp);
4476 }
4477
4478 static struct edid *
4479 intel_dp_get_edid(struct intel_dp *intel_dp)
4480 {
4481         struct intel_connector *intel_connector = intel_dp->attached_connector;
4482
4483         /* use cached edid if we have one */
4484         if (intel_connector->edid) {
4485                 /* invalid edid */
4486                 if (IS_ERR(intel_connector->edid))
4487                         return NULL;
4488
4489                 return drm_edid_duplicate(intel_connector->edid);
4490         } else
4491                 return drm_get_edid(&intel_connector->base,
4492                                     &intel_dp->aux.ddc);
4493 }
4494
4495 static void
4496 intel_dp_set_edid(struct intel_dp *intel_dp)
4497 {
4498         struct intel_connector *intel_connector = intel_dp->attached_connector;
4499         struct edid *edid;
4500
4501         edid = intel_dp_get_edid(intel_dp);
4502         intel_connector->detect_edid = edid;
4503
4504         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4505                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4506         else
4507                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4508 }
4509
4510 static void
4511 intel_dp_unset_edid(struct intel_dp *intel_dp)
4512 {
4513         struct intel_connector *intel_connector = intel_dp->attached_connector;
4514
4515         kfree(intel_connector->detect_edid);
4516         intel_connector->detect_edid = NULL;
4517
4518         intel_dp->has_audio = false;
4519 }
4520
4521 static enum intel_display_power_domain
4522 intel_dp_power_get(struct intel_dp *dp)
4523 {
4524         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4525         enum intel_display_power_domain power_domain;
4526
4527         power_domain = intel_display_port_power_domain(encoder);
4528         intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4529
4530         return power_domain;
4531 }
4532
4533 static void
4534 intel_dp_power_put(struct intel_dp *dp,
4535                    enum intel_display_power_domain power_domain)
4536 {
4537         struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4538         intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4539 }
4540
4541 static enum drm_connector_status
4542 intel_dp_detect(struct drm_connector *connector, bool force)
4543 {
4544         struct intel_dp *intel_dp = intel_attached_dp(connector);
4545         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4546         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4547         struct drm_device *dev = connector->dev;
4548         enum drm_connector_status status;
4549         enum intel_display_power_domain power_domain;
4550         bool ret;
4551         u8 sink_irq_vector;
4552
4553         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4554                       connector->base.id, connector->name);
4555         intel_dp_unset_edid(intel_dp);
4556
4557         if (intel_dp->is_mst) {
4558                 /* MST devices are disconnected from a monitor POV */
4559                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4560                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4561                 return connector_status_disconnected;
4562         }
4563
4564         power_domain = intel_dp_power_get(intel_dp);
4565
4566         /* Can't disconnect eDP, but you can close the lid... */
4567         if (is_edp(intel_dp))
4568                 status = edp_detect(intel_dp);
4569         else if (HAS_PCH_SPLIT(dev))
4570                 status = ironlake_dp_detect(intel_dp);
4571         else
4572                 status = g4x_dp_detect(intel_dp);
4573         if (status != connector_status_connected)
4574                 goto out;
4575
4576         intel_dp_probe_oui(intel_dp);
4577
4578         ret = intel_dp_probe_mst(intel_dp);
4579         if (ret) {
4580                 /* if we are in MST mode then this connector
4581                    won't appear connected or have anything with EDID on it */
4582                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4583                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4584                 status = connector_status_disconnected;
4585                 goto out;
4586         }
4587
4588         intel_dp_set_edid(intel_dp);
4589
4590         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4591                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4592         status = connector_status_connected;
4593
4594         /* Try to read the source of the interrupt */
4595         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4596             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4597                 /* Clear interrupt source */
4598                 drm_dp_dpcd_writeb(&intel_dp->aux,
4599                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4600                                    sink_irq_vector);
4601
4602                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4603                         intel_dp_handle_test_request(intel_dp);
4604                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4605                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4606         }
4607
4608 out:
4609         intel_dp_power_put(intel_dp, power_domain);
4610         return status;
4611 }
4612
4613 static void
4614 intel_dp_force(struct drm_connector *connector)
4615 {
4616         struct intel_dp *intel_dp = intel_attached_dp(connector);
4617         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4618         enum intel_display_power_domain power_domain;
4619
4620         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4621                       connector->base.id, connector->name);
4622         intel_dp_unset_edid(intel_dp);
4623
4624         if (connector->status != connector_status_connected)
4625                 return;
4626
4627         power_domain = intel_dp_power_get(intel_dp);
4628
4629         intel_dp_set_edid(intel_dp);
4630
4631         intel_dp_power_put(intel_dp, power_domain);
4632
4633         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4634                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4635 }
4636
4637 static int intel_dp_get_modes(struct drm_connector *connector)
4638 {
4639         struct intel_connector *intel_connector = to_intel_connector(connector);
4640         struct edid *edid;
4641
4642         edid = intel_connector->detect_edid;
4643         if (edid) {
4644                 int ret = intel_connector_update_modes(connector, edid);
4645                 if (ret)
4646                         return ret;
4647         }
4648
4649         /* if eDP has no EDID, fall back to fixed mode */
4650         if (is_edp(intel_attached_dp(connector)) &&
4651             intel_connector->panel.fixed_mode) {
4652                 struct drm_display_mode *mode;
4653
4654                 mode = drm_mode_duplicate(connector->dev,
4655                                           intel_connector->panel.fixed_mode);
4656                 if (mode) {
4657                         drm_mode_probed_add(connector, mode);
4658                         return 1;
4659                 }
4660         }
4661
4662         return 0;
4663 }
4664
4665 static bool
4666 intel_dp_detect_audio(struct drm_connector *connector)
4667 {
4668         bool has_audio = false;
4669         struct edid *edid;
4670
4671         edid = to_intel_connector(connector)->detect_edid;
4672         if (edid)
4673                 has_audio = drm_detect_monitor_audio(edid);
4674
4675         return has_audio;
4676 }
4677
4678 static int
4679 intel_dp_set_property(struct drm_connector *connector,
4680                       struct drm_property *property,
4681                       uint64_t val)
4682 {
4683         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4684         struct intel_connector *intel_connector = to_intel_connector(connector);
4685         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4686         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4687         int ret;
4688
4689         ret = drm_object_property_set_value(&connector->base, property, val);
4690         if (ret)
4691                 return ret;
4692
4693         if (property == dev_priv->force_audio_property) {
4694                 int i = val;
4695                 bool has_audio;
4696
4697                 if (i == intel_dp->force_audio)
4698                         return 0;
4699
4700                 intel_dp->force_audio = i;
4701
4702                 if (i == HDMI_AUDIO_AUTO)
4703                         has_audio = intel_dp_detect_audio(connector);
4704                 else
4705                         has_audio = (i == HDMI_AUDIO_ON);
4706
4707                 if (has_audio == intel_dp->has_audio)
4708                         return 0;
4709
4710                 intel_dp->has_audio = has_audio;
4711                 goto done;
4712         }
4713
4714         if (property == dev_priv->broadcast_rgb_property) {
4715                 bool old_auto = intel_dp->color_range_auto;
4716                 uint32_t old_range = intel_dp->color_range;
4717
4718                 switch (val) {
4719                 case INTEL_BROADCAST_RGB_AUTO:
4720                         intel_dp->color_range_auto = true;
4721                         break;
4722                 case INTEL_BROADCAST_RGB_FULL:
4723                         intel_dp->color_range_auto = false;
4724                         intel_dp->color_range = 0;
4725                         break;
4726                 case INTEL_BROADCAST_RGB_LIMITED:
4727                         intel_dp->color_range_auto = false;
4728                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
4729                         break;
4730                 default:
4731                         return -EINVAL;
4732                 }
4733
4734                 if (old_auto == intel_dp->color_range_auto &&
4735                     old_range == intel_dp->color_range)
4736                         return 0;
4737
4738                 goto done;
4739         }
4740
4741         if (is_edp(intel_dp) &&
4742             property == connector->dev->mode_config.scaling_mode_property) {
4743                 if (val == DRM_MODE_SCALE_NONE) {
4744                         DRM_DEBUG_KMS("no scaling not supported\n");
4745                         return -EINVAL;
4746                 }
4747
4748                 if (intel_connector->panel.fitting_mode == val) {
4749                         /* the eDP scaling property is not changed */
4750                         return 0;
4751                 }
4752                 intel_connector->panel.fitting_mode = val;
4753
4754                 goto done;
4755         }
4756
4757         return -EINVAL;
4758
4759 done:
4760         if (intel_encoder->base.crtc)
4761                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4762
4763         return 0;
4764 }
4765
4766 static void
4767 intel_dp_connector_destroy(struct drm_connector *connector)
4768 {
4769         struct intel_connector *intel_connector = to_intel_connector(connector);
4770
4771         kfree(intel_connector->detect_edid);
4772
4773         if (!IS_ERR_OR_NULL(intel_connector->edid))
4774                 kfree(intel_connector->edid);
4775
4776         /* Can't call is_edp() since the encoder may have been destroyed
4777          * already. */
4778         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4779                 intel_panel_fini(&intel_connector->panel);
4780
4781         drm_connector_cleanup(connector);
4782         kfree(connector);
4783 }
4784
4785 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4786 {
4787         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4788         struct intel_dp *intel_dp = &intel_dig_port->dp;
4789
4790         drm_dp_aux_unregister(&intel_dp->aux);
4791         intel_dp_mst_encoder_cleanup(intel_dig_port);
4792         if (is_edp(intel_dp)) {
4793                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4794                 /*
4795                  * vdd might still be enabled do to the delayed vdd off.
4796                  * Make sure vdd is actually turned off here.
4797                  */
4798                 pps_lock(intel_dp);
4799                 edp_panel_vdd_off_sync(intel_dp);
4800                 pps_unlock(intel_dp);
4801
4802                 if (intel_dp->edp_notifier.notifier_call) {
4803                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4804                         intel_dp->edp_notifier.notifier_call = NULL;
4805                 }
4806         }
4807         drm_encoder_cleanup(encoder);
4808         kfree(intel_dig_port);
4809 }
4810
4811 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4812 {
4813         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4814
4815         if (!is_edp(intel_dp))
4816                 return;
4817
4818         /*
4819          * vdd might still be enabled do to the delayed vdd off.
4820          * Make sure vdd is actually turned off here.
4821          */
4822         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4823         pps_lock(intel_dp);
4824         edp_panel_vdd_off_sync(intel_dp);
4825         pps_unlock(intel_dp);
4826 }
4827
4828 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4829 {
4830         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4831         struct drm_device *dev = intel_dig_port->base.base.dev;
4832         struct drm_i915_private *dev_priv = dev->dev_private;
4833         enum intel_display_power_domain power_domain;
4834
4835         lockdep_assert_held(&dev_priv->pps_mutex);
4836
4837         if (!edp_have_panel_vdd(intel_dp))
4838                 return;
4839
4840         /*
4841          * The VDD bit needs a power domain reference, so if the bit is
4842          * already enabled when we boot or resume, grab this reference and
4843          * schedule a vdd off, so we don't hold on to the reference
4844          * indefinitely.
4845          */
4846         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4847         power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4848         intel_display_power_get(dev_priv, power_domain);
4849
4850         edp_panel_vdd_schedule_off(intel_dp);
4851 }
4852
4853 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4854 {
4855         struct intel_dp *intel_dp;
4856
4857         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4858                 return;
4859
4860         intel_dp = enc_to_intel_dp(encoder);
4861
4862         pps_lock(intel_dp);
4863
4864         /*
4865          * Read out the current power sequencer assignment,
4866          * in case the BIOS did something with it.
4867          */
4868         if (IS_VALLEYVIEW(encoder->dev))
4869                 vlv_initial_power_sequencer_setup(intel_dp);
4870
4871         intel_edp_panel_vdd_sanitize(intel_dp);
4872
4873         pps_unlock(intel_dp);
4874 }
4875
4876 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4877         .dpms = intel_connector_dpms,
4878         .detect = intel_dp_detect,
4879         .force = intel_dp_force,
4880         .fill_modes = drm_helper_probe_single_connector_modes,
4881         .set_property = intel_dp_set_property,
4882         .atomic_get_property = intel_connector_atomic_get_property,
4883         .destroy = intel_dp_connector_destroy,
4884         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4885         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4886 };
4887
4888 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4889         .get_modes = intel_dp_get_modes,
4890         .mode_valid = intel_dp_mode_valid,
4891         .best_encoder = intel_best_encoder,
4892 };
4893
4894 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4895         .reset = intel_dp_encoder_reset,
4896         .destroy = intel_dp_encoder_destroy,
4897 };
4898
4899 void
4900 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4901 {
4902         return;
4903 }
4904
4905 enum irqreturn
4906 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4907 {
4908         struct intel_dp *intel_dp = &intel_dig_port->dp;
4909         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4910         struct drm_device *dev = intel_dig_port->base.base.dev;
4911         struct drm_i915_private *dev_priv = dev->dev_private;
4912         enum intel_display_power_domain power_domain;
4913         enum irqreturn ret = IRQ_NONE;
4914
4915         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4916                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4917
4918         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4919                 /*
4920                  * vdd off can generate a long pulse on eDP which
4921                  * would require vdd on to handle it, and thus we
4922                  * would end up in an endless cycle of
4923                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4924                  */
4925                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4926                               port_name(intel_dig_port->port));
4927                 return IRQ_HANDLED;
4928         }
4929
4930         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4931                       port_name(intel_dig_port->port),
4932                       long_hpd ? "long" : "short");
4933
4934         power_domain = intel_display_port_power_domain(intel_encoder);
4935         intel_display_power_get(dev_priv, power_domain);
4936
4937         if (long_hpd) {
4938                 /* indicate that we need to restart link training */
4939                 intel_dp->train_set_valid = false;
4940
4941                 if (HAS_PCH_SPLIT(dev)) {
4942                         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4943                                 goto mst_fail;
4944                 } else {
4945                         if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4946                                 goto mst_fail;
4947                 }
4948
4949                 if (!intel_dp_get_dpcd(intel_dp)) {
4950                         goto mst_fail;
4951                 }
4952
4953                 intel_dp_probe_oui(intel_dp);
4954
4955                 if (!intel_dp_probe_mst(intel_dp))
4956                         goto mst_fail;
4957
4958         } else {
4959                 if (intel_dp->is_mst) {
4960                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4961                                 goto mst_fail;
4962                 }
4963
4964                 if (!intel_dp->is_mst) {
4965                         /*
4966                          * we'll check the link status via the normal hot plug path later -
4967                          * but for short hpds we should check it now
4968                          */
4969                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4970                         intel_dp_check_link_status(intel_dp);
4971                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4972                 }
4973         }
4974
4975         ret = IRQ_HANDLED;
4976
4977         goto put_power;
4978 mst_fail:
4979         /* if we were in MST mode, and device is not there get out of MST mode */
4980         if (intel_dp->is_mst) {
4981                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4982                 intel_dp->is_mst = false;
4983                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4984         }
4985 put_power:
4986         intel_display_power_put(dev_priv, power_domain);
4987
4988         return ret;
4989 }
4990
4991 /* Return which DP Port should be selected for Transcoder DP control */
4992 int
4993 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4994 {
4995         struct drm_device *dev = crtc->dev;
4996         struct intel_encoder *intel_encoder;
4997         struct intel_dp *intel_dp;
4998
4999         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5000                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
5001
5002                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
5003                     intel_encoder->type == INTEL_OUTPUT_EDP)
5004                         return intel_dp->output_reg;
5005         }
5006
5007         return -1;
5008 }
5009
5010 /* check the VBT to see whether the eDP is on DP-D port */
5011 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
5012 {
5013         struct drm_i915_private *dev_priv = dev->dev_private;
5014         union child_device_config *p_child;
5015         int i;
5016         static const short port_mapping[] = {
5017                 [PORT_B] = PORT_IDPB,
5018                 [PORT_C] = PORT_IDPC,
5019                 [PORT_D] = PORT_IDPD,
5020         };
5021
5022         if (port == PORT_A)
5023                 return true;
5024
5025         if (!dev_priv->vbt.child_dev_num)
5026                 return false;
5027
5028         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
5029                 p_child = dev_priv->vbt.child_dev + i;
5030
5031                 if (p_child->common.dvo_port == port_mapping[port] &&
5032                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
5033                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
5034                         return true;
5035         }
5036         return false;
5037 }
5038
5039 void
5040 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5041 {
5042         struct intel_connector *intel_connector = to_intel_connector(connector);
5043
5044         intel_attach_force_audio_property(connector);
5045         intel_attach_broadcast_rgb_property(connector);
5046         intel_dp->color_range_auto = true;
5047
5048         if (is_edp(intel_dp)) {
5049                 drm_mode_create_scaling_mode_property(connector->dev);
5050                 drm_object_attach_property(
5051                         &connector->base,
5052                         connector->dev->mode_config.scaling_mode_property,
5053                         DRM_MODE_SCALE_ASPECT);
5054                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5055         }
5056 }
5057
5058 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5059 {
5060         intel_dp->last_power_cycle = jiffies;
5061         intel_dp->last_power_on = jiffies;
5062         intel_dp->last_backlight_off = jiffies;
5063 }
5064
5065 static void
5066 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5067                                     struct intel_dp *intel_dp)
5068 {
5069         struct drm_i915_private *dev_priv = dev->dev_private;
5070         struct edp_power_seq cur, vbt, spec,
5071                 *final = &intel_dp->pps_delays;
5072         u32 pp_on, pp_off, pp_div, pp;
5073         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
5074
5075         lockdep_assert_held(&dev_priv->pps_mutex);
5076
5077         /* already initialized? */
5078         if (final->t11_t12 != 0)
5079                 return;
5080
5081         if (HAS_PCH_SPLIT(dev)) {
5082                 pp_ctrl_reg = PCH_PP_CONTROL;
5083                 pp_on_reg = PCH_PP_ON_DELAYS;
5084                 pp_off_reg = PCH_PP_OFF_DELAYS;
5085                 pp_div_reg = PCH_PP_DIVISOR;
5086         } else {
5087                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5088
5089                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5090                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5091                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5092                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5093         }
5094
5095         /* Workaround: Need to write PP_CONTROL with the unlock key as
5096          * the very first thing. */
5097         pp = ironlake_get_pp_control(intel_dp);
5098         I915_WRITE(pp_ctrl_reg, pp);
5099
5100         pp_on = I915_READ(pp_on_reg);
5101         pp_off = I915_READ(pp_off_reg);
5102         pp_div = I915_READ(pp_div_reg);
5103
5104         /* Pull timing values out of registers */
5105         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5106                 PANEL_POWER_UP_DELAY_SHIFT;
5107
5108         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5109                 PANEL_LIGHT_ON_DELAY_SHIFT;
5110
5111         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5112                 PANEL_LIGHT_OFF_DELAY_SHIFT;
5113
5114         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5115                 PANEL_POWER_DOWN_DELAY_SHIFT;
5116
5117         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5118                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5119
5120         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5121                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5122
5123         vbt = dev_priv->vbt.edp_pps;
5124
5125         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5126          * our hw here, which are all in 100usec. */
5127         spec.t1_t3 = 210 * 10;
5128         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5129         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5130         spec.t10 = 500 * 10;
5131         /* This one is special and actually in units of 100ms, but zero
5132          * based in the hw (so we need to add 100 ms). But the sw vbt
5133          * table multiplies it with 1000 to make it in units of 100usec,
5134          * too. */
5135         spec.t11_t12 = (510 + 100) * 10;
5136
5137         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5138                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5139
5140         /* Use the max of the register settings and vbt. If both are
5141          * unset, fall back to the spec limits. */
5142 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5143                                        spec.field : \
5144                                        max(cur.field, vbt.field))
5145         assign_final(t1_t3);
5146         assign_final(t8);
5147         assign_final(t9);
5148         assign_final(t10);
5149         assign_final(t11_t12);
5150 #undef assign_final
5151
5152 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5153         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5154         intel_dp->backlight_on_delay = get_delay(t8);
5155         intel_dp->backlight_off_delay = get_delay(t9);
5156         intel_dp->panel_power_down_delay = get_delay(t10);
5157         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5158 #undef get_delay
5159
5160         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5161                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5162                       intel_dp->panel_power_cycle_delay);
5163
5164         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5165                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5166 }
5167
5168 static void
5169 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5170                                               struct intel_dp *intel_dp)
5171 {
5172         struct drm_i915_private *dev_priv = dev->dev_private;
5173         u32 pp_on, pp_off, pp_div, port_sel = 0;
5174         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
5175         int pp_on_reg, pp_off_reg, pp_div_reg;
5176         enum port port = dp_to_dig_port(intel_dp)->port;
5177         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5178
5179         lockdep_assert_held(&dev_priv->pps_mutex);
5180
5181         if (HAS_PCH_SPLIT(dev)) {
5182                 pp_on_reg = PCH_PP_ON_DELAYS;
5183                 pp_off_reg = PCH_PP_OFF_DELAYS;
5184                 pp_div_reg = PCH_PP_DIVISOR;
5185         } else {
5186                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5187
5188                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5189                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5190                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5191         }
5192
5193         /*
5194          * And finally store the new values in the power sequencer. The
5195          * backlight delays are set to 1 because we do manual waits on them. For
5196          * T8, even BSpec recommends doing it. For T9, if we don't do this,
5197          * we'll end up waiting for the backlight off delay twice: once when we
5198          * do the manual sleep, and once when we disable the panel and wait for
5199          * the PP_STATUS bit to become zero.
5200          */
5201         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5202                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5203         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5204                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5205         /* Compute the divisor for the pp clock, simply match the Bspec
5206          * formula. */
5207         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5208         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5209                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
5210
5211         /* Haswell doesn't have any port selection bits for the panel
5212          * power sequencer any more. */
5213         if (IS_VALLEYVIEW(dev)) {
5214                 port_sel = PANEL_PORT_SELECT_VLV(port);
5215         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5216                 if (port == PORT_A)
5217                         port_sel = PANEL_PORT_SELECT_DPA;
5218                 else
5219                         port_sel = PANEL_PORT_SELECT_DPD;
5220         }
5221
5222         pp_on |= port_sel;
5223
5224         I915_WRITE(pp_on_reg, pp_on);
5225         I915_WRITE(pp_off_reg, pp_off);
5226         I915_WRITE(pp_div_reg, pp_div);
5227
5228         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5229                       I915_READ(pp_on_reg),
5230                       I915_READ(pp_off_reg),
5231                       I915_READ(pp_div_reg));
5232 }
5233
5234 /**
5235  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5236  * @dev: DRM device
5237  * @refresh_rate: RR to be programmed
5238  *
5239  * This function gets called when refresh rate (RR) has to be changed from
5240  * one frequency to another. Switches can be between high and low RR
5241  * supported by the panel or to any other RR based on media playback (in
5242  * this case, RR value needs to be passed from user space).
5243  *
5244  * The caller of this function needs to take a lock on dev_priv->drrs.
5245  */
5246 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5247 {
5248         struct drm_i915_private *dev_priv = dev->dev_private;
5249         struct intel_encoder *encoder;
5250         struct intel_digital_port *dig_port = NULL;
5251         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5252         struct intel_crtc_state *config = NULL;
5253         struct intel_crtc *intel_crtc = NULL;
5254         u32 reg, val;
5255         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5256
5257         if (refresh_rate <= 0) {
5258                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5259                 return;
5260         }
5261
5262         if (intel_dp == NULL) {
5263                 DRM_DEBUG_KMS("DRRS not supported.\n");
5264                 return;
5265         }
5266
5267         /*
5268          * FIXME: This needs proper synchronization with psr state for some
5269          * platforms that cannot have PSR and DRRS enabled at the same time.
5270          */
5271
5272         dig_port = dp_to_dig_port(intel_dp);
5273         encoder = &dig_port->base;
5274         intel_crtc = to_intel_crtc(encoder->base.crtc);
5275
5276         if (!intel_crtc) {
5277                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5278                 return;
5279         }
5280
5281         config = intel_crtc->config;
5282
5283         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5284                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5285                 return;
5286         }
5287
5288         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5289                         refresh_rate)
5290                 index = DRRS_LOW_RR;
5291
5292         if (index == dev_priv->drrs.refresh_rate_type) {
5293                 DRM_DEBUG_KMS(
5294                         "DRRS requested for previously set RR...ignoring\n");
5295                 return;
5296         }
5297
5298         if (!intel_crtc->active) {
5299                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5300                 return;
5301         }
5302
5303         if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
5304                 switch (index) {
5305                 case DRRS_HIGH_RR:
5306                         intel_dp_set_m_n(intel_crtc, M1_N1);
5307                         break;
5308                 case DRRS_LOW_RR:
5309                         intel_dp_set_m_n(intel_crtc, M2_N2);
5310                         break;
5311                 case DRRS_MAX_RR:
5312                 default:
5313                         DRM_ERROR("Unsupported refreshrate type\n");
5314                 }
5315         } else if (INTEL_INFO(dev)->gen > 6) {
5316                 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5317                 val = I915_READ(reg);
5318
5319                 if (index > DRRS_HIGH_RR) {
5320                         if (IS_VALLEYVIEW(dev))
5321                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5322                         else
5323                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5324                 } else {
5325                         if (IS_VALLEYVIEW(dev))
5326                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5327                         else
5328                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5329                 }
5330                 I915_WRITE(reg, val);
5331         }
5332
5333         dev_priv->drrs.refresh_rate_type = index;
5334
5335         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5336 }
5337
5338 /**
5339  * intel_edp_drrs_enable - init drrs struct if supported
5340  * @intel_dp: DP struct
5341  *
5342  * Initializes frontbuffer_bits and drrs.dp
5343  */
5344 void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5345 {
5346         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5347         struct drm_i915_private *dev_priv = dev->dev_private;
5348         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5349         struct drm_crtc *crtc = dig_port->base.base.crtc;
5350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5351
5352         if (!intel_crtc->config->has_drrs) {
5353                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5354                 return;
5355         }
5356
5357         mutex_lock(&dev_priv->drrs.mutex);
5358         if (WARN_ON(dev_priv->drrs.dp)) {
5359                 DRM_ERROR("DRRS already enabled\n");
5360                 goto unlock;
5361         }
5362
5363         dev_priv->drrs.busy_frontbuffer_bits = 0;
5364
5365         dev_priv->drrs.dp = intel_dp;
5366
5367 unlock:
5368         mutex_unlock(&dev_priv->drrs.mutex);
5369 }
5370
5371 /**
5372  * intel_edp_drrs_disable - Disable DRRS
5373  * @intel_dp: DP struct
5374  *
5375  */
5376 void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5377 {
5378         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5379         struct drm_i915_private *dev_priv = dev->dev_private;
5380         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5381         struct drm_crtc *crtc = dig_port->base.base.crtc;
5382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5383
5384         if (!intel_crtc->config->has_drrs)
5385                 return;
5386
5387         mutex_lock(&dev_priv->drrs.mutex);
5388         if (!dev_priv->drrs.dp) {
5389                 mutex_unlock(&dev_priv->drrs.mutex);
5390                 return;
5391         }
5392
5393         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5394                 intel_dp_set_drrs_state(dev_priv->dev,
5395                         intel_dp->attached_connector->panel.
5396                         fixed_mode->vrefresh);
5397
5398         dev_priv->drrs.dp = NULL;
5399         mutex_unlock(&dev_priv->drrs.mutex);
5400
5401         cancel_delayed_work_sync(&dev_priv->drrs.work);
5402 }
5403
5404 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5405 {
5406         struct drm_i915_private *dev_priv =
5407                 container_of(work, typeof(*dev_priv), drrs.work.work);
5408         struct intel_dp *intel_dp;
5409
5410         mutex_lock(&dev_priv->drrs.mutex);
5411
5412         intel_dp = dev_priv->drrs.dp;
5413
5414         if (!intel_dp)
5415                 goto unlock;
5416
5417         /*
5418          * The delayed work can race with an invalidate hence we need to
5419          * recheck.
5420          */
5421
5422         if (dev_priv->drrs.busy_frontbuffer_bits)
5423                 goto unlock;
5424
5425         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5426                 intel_dp_set_drrs_state(dev_priv->dev,
5427                         intel_dp->attached_connector->panel.
5428                         downclock_mode->vrefresh);
5429
5430 unlock:
5431         mutex_unlock(&dev_priv->drrs.mutex);
5432 }
5433
5434 /**
5435  * intel_edp_drrs_invalidate - Invalidate DRRS
5436  * @dev: DRM device
5437  * @frontbuffer_bits: frontbuffer plane tracking bits
5438  *
5439  * When there is a disturbance on screen (due to cursor movement/time
5440  * update etc), DRRS needs to be invalidated, i.e. need to switch to
5441  * high RR.
5442  *
5443  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5444  */
5445 void intel_edp_drrs_invalidate(struct drm_device *dev,
5446                 unsigned frontbuffer_bits)
5447 {
5448         struct drm_i915_private *dev_priv = dev->dev_private;
5449         struct drm_crtc *crtc;
5450         enum pipe pipe;
5451
5452         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5453                 return;
5454
5455         cancel_delayed_work(&dev_priv->drrs.work);
5456
5457         mutex_lock(&dev_priv->drrs.mutex);
5458         if (!dev_priv->drrs.dp) {
5459                 mutex_unlock(&dev_priv->drrs.mutex);
5460                 return;
5461         }
5462
5463         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5464         pipe = to_intel_crtc(crtc)->pipe;
5465
5466         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
5467                 intel_dp_set_drrs_state(dev_priv->dev,
5468                                 dev_priv->drrs.dp->attached_connector->panel.
5469                                 fixed_mode->vrefresh);
5470         }
5471
5472         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5473
5474         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5475         mutex_unlock(&dev_priv->drrs.mutex);
5476 }
5477
5478 /**
5479  * intel_edp_drrs_flush - Flush DRRS
5480  * @dev: DRM device
5481  * @frontbuffer_bits: frontbuffer plane tracking bits
5482  *
5483  * When there is no movement on screen, DRRS work can be scheduled.
5484  * This DRRS work is responsible for setting relevant registers after a
5485  * timeout of 1 second.
5486  *
5487  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5488  */
5489 void intel_edp_drrs_flush(struct drm_device *dev,
5490                 unsigned frontbuffer_bits)
5491 {
5492         struct drm_i915_private *dev_priv = dev->dev_private;
5493         struct drm_crtc *crtc;
5494         enum pipe pipe;
5495
5496         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5497                 return;
5498
5499         cancel_delayed_work(&dev_priv->drrs.work);
5500
5501         mutex_lock(&dev_priv->drrs.mutex);
5502         if (!dev_priv->drrs.dp) {
5503                 mutex_unlock(&dev_priv->drrs.mutex);
5504                 return;
5505         }
5506
5507         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5508         pipe = to_intel_crtc(crtc)->pipe;
5509         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5510
5511         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR &&
5512                         !dev_priv->drrs.busy_frontbuffer_bits)
5513                 schedule_delayed_work(&dev_priv->drrs.work,
5514                                 msecs_to_jiffies(1000));
5515         mutex_unlock(&dev_priv->drrs.mutex);
5516 }
5517
5518 /**
5519  * DOC: Display Refresh Rate Switching (DRRS)
5520  *
5521  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5522  * which enables swtching between low and high refresh rates,
5523  * dynamically, based on the usage scenario. This feature is applicable
5524  * for internal panels.
5525  *
5526  * Indication that the panel supports DRRS is given by the panel EDID, which
5527  * would list multiple refresh rates for one resolution.
5528  *
5529  * DRRS is of 2 types - static and seamless.
5530  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5531  * (may appear as a blink on screen) and is used in dock-undock scenario.
5532  * Seamless DRRS involves changing RR without any visual effect to the user
5533  * and can be used during normal system usage. This is done by programming
5534  * certain registers.
5535  *
5536  * Support for static/seamless DRRS may be indicated in the VBT based on
5537  * inputs from the panel spec.
5538  *
5539  * DRRS saves power by switching to low RR based on usage scenarios.
5540  *
5541  * eDP DRRS:-
5542  *        The implementation is based on frontbuffer tracking implementation.
5543  * When there is a disturbance on the screen triggered by user activity or a
5544  * periodic system activity, DRRS is disabled (RR is changed to high RR).
5545  * When there is no movement on screen, after a timeout of 1 second, a switch
5546  * to low RR is made.
5547  *        For integration with frontbuffer tracking code,
5548  * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5549  *
5550  * DRRS can be further extended to support other internal panels and also
5551  * the scenario of video playback wherein RR is set based on the rate
5552  * requested by userspace.
5553  */
5554
5555 /**
5556  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5557  * @intel_connector: eDP connector
5558  * @fixed_mode: preferred mode of panel
5559  *
5560  * This function is  called only once at driver load to initialize basic
5561  * DRRS stuff.
5562  *
5563  * Returns:
5564  * Downclock mode if panel supports it, else return NULL.
5565  * DRRS support is determined by the presence of downclock mode (apart
5566  * from VBT setting).
5567  */
5568 static struct drm_display_mode *
5569 intel_dp_drrs_init(struct intel_connector *intel_connector,
5570                 struct drm_display_mode *fixed_mode)
5571 {
5572         struct drm_connector *connector = &intel_connector->base;
5573         struct drm_device *dev = connector->dev;
5574         struct drm_i915_private *dev_priv = dev->dev_private;
5575         struct drm_display_mode *downclock_mode = NULL;
5576
5577         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5578         mutex_init(&dev_priv->drrs.mutex);
5579
5580         if (INTEL_INFO(dev)->gen <= 6) {
5581                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5582                 return NULL;
5583         }
5584
5585         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5586                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5587                 return NULL;
5588         }
5589
5590         downclock_mode = intel_find_panel_downclock
5591                                         (dev, fixed_mode, connector);
5592
5593         if (!downclock_mode) {
5594                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5595                 return NULL;
5596         }
5597
5598         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5599
5600         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5601         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5602         return downclock_mode;
5603 }
5604
5605 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5606                                      struct intel_connector *intel_connector)
5607 {
5608         struct drm_connector *connector = &intel_connector->base;
5609         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5610         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5611         struct drm_device *dev = intel_encoder->base.dev;
5612         struct drm_i915_private *dev_priv = dev->dev_private;
5613         struct drm_display_mode *fixed_mode = NULL;
5614         struct drm_display_mode *downclock_mode = NULL;
5615         bool has_dpcd;
5616         struct drm_display_mode *scan;
5617         struct edid *edid;
5618         enum pipe pipe = INVALID_PIPE;
5619
5620         if (!is_edp(intel_dp))
5621                 return true;
5622
5623         pps_lock(intel_dp);
5624         intel_edp_panel_vdd_sanitize(intel_dp);
5625         pps_unlock(intel_dp);
5626
5627         /* Cache DPCD and EDID for edp. */
5628         has_dpcd = intel_dp_get_dpcd(intel_dp);
5629
5630         if (has_dpcd) {
5631                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5632                         dev_priv->no_aux_handshake =
5633                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5634                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5635         } else {
5636                 /* if this fails, presume the device is a ghost */
5637                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5638                 return false;
5639         }
5640
5641         /* We now know it's not a ghost, init power sequence regs. */
5642         pps_lock(intel_dp);
5643         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5644         pps_unlock(intel_dp);
5645
5646         mutex_lock(&dev->mode_config.mutex);
5647         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5648         if (edid) {
5649                 if (drm_add_edid_modes(connector, edid)) {
5650                         drm_mode_connector_update_edid_property(connector,
5651                                                                 edid);
5652                         drm_edid_to_eld(connector, edid);
5653                 } else {
5654                         kfree(edid);
5655                         edid = ERR_PTR(-EINVAL);
5656                 }
5657         } else {
5658                 edid = ERR_PTR(-ENOENT);
5659         }
5660         intel_connector->edid = edid;
5661
5662         /* prefer fixed mode from EDID if available */
5663         list_for_each_entry(scan, &connector->probed_modes, head) {
5664                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5665                         fixed_mode = drm_mode_duplicate(dev, scan);
5666                         downclock_mode = intel_dp_drrs_init(
5667                                                 intel_connector, fixed_mode);
5668                         break;
5669                 }
5670         }
5671
5672         /* fallback to VBT if available for eDP */
5673         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5674                 fixed_mode = drm_mode_duplicate(dev,
5675                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5676                 if (fixed_mode)
5677                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5678         }
5679         mutex_unlock(&dev->mode_config.mutex);
5680
5681         if (IS_VALLEYVIEW(dev)) {
5682                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5683                 register_reboot_notifier(&intel_dp->edp_notifier);
5684
5685                 /*
5686                  * Figure out the current pipe for the initial backlight setup.
5687                  * If the current pipe isn't valid, try the PPS pipe, and if that
5688                  * fails just assume pipe A.
5689                  */
5690                 if (IS_CHERRYVIEW(dev))
5691                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5692                 else
5693                         pipe = PORT_TO_PIPE(intel_dp->DP);
5694
5695                 if (pipe != PIPE_A && pipe != PIPE_B)
5696                         pipe = intel_dp->pps_pipe;
5697
5698                 if (pipe != PIPE_A && pipe != PIPE_B)
5699                         pipe = PIPE_A;
5700
5701                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5702                               pipe_name(pipe));
5703         }
5704
5705         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5706         intel_connector->panel.backlight_power = intel_edp_backlight_power;
5707         intel_panel_setup_backlight(connector, pipe);
5708
5709         return true;
5710 }
5711
5712 bool
5713 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5714                         struct intel_connector *intel_connector)
5715 {
5716         struct drm_connector *connector = &intel_connector->base;
5717         struct intel_dp *intel_dp = &intel_dig_port->dp;
5718         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5719         struct drm_device *dev = intel_encoder->base.dev;
5720         struct drm_i915_private *dev_priv = dev->dev_private;
5721         enum port port = intel_dig_port->port;
5722         int type;
5723
5724         intel_dp->pps_pipe = INVALID_PIPE;
5725
5726         /* intel_dp vfuncs */
5727         if (INTEL_INFO(dev)->gen >= 9)
5728                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5729         else if (IS_VALLEYVIEW(dev))
5730                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5731         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5732                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5733         else if (HAS_PCH_SPLIT(dev))
5734                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5735         else
5736                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5737
5738         if (INTEL_INFO(dev)->gen >= 9)
5739                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5740         else
5741                 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5742
5743         /* Preserve the current hw state. */
5744         intel_dp->DP = I915_READ(intel_dp->output_reg);
5745         intel_dp->attached_connector = intel_connector;
5746
5747         if (intel_dp_is_edp(dev, port))
5748                 type = DRM_MODE_CONNECTOR_eDP;
5749         else
5750                 type = DRM_MODE_CONNECTOR_DisplayPort;
5751
5752         /*
5753          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5754          * for DP the encoder type can be set by the caller to
5755          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5756          */
5757         if (type == DRM_MODE_CONNECTOR_eDP)
5758                 intel_encoder->type = INTEL_OUTPUT_EDP;
5759
5760         /* eDP only on port B and/or C on vlv/chv */
5761         if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5762                     port != PORT_B && port != PORT_C))
5763                 return false;
5764
5765         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5766                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5767                         port_name(port));
5768
5769         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5770         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5771
5772         connector->interlace_allowed = true;
5773         connector->doublescan_allowed = 0;
5774
5775         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5776                           edp_panel_vdd_work);
5777
5778         intel_connector_attach_encoder(intel_connector, intel_encoder);
5779         drm_connector_register(connector);
5780
5781         if (HAS_DDI(dev))
5782                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5783         else
5784                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5785         intel_connector->unregister = intel_dp_connector_unregister;
5786
5787         /* Set up the hotplug pin. */
5788         switch (port) {
5789         case PORT_A:
5790                 intel_encoder->hpd_pin = HPD_PORT_A;
5791                 break;
5792         case PORT_B:
5793                 intel_encoder->hpd_pin = HPD_PORT_B;
5794                 break;
5795         case PORT_C:
5796                 intel_encoder->hpd_pin = HPD_PORT_C;
5797                 break;
5798         case PORT_D:
5799                 intel_encoder->hpd_pin = HPD_PORT_D;
5800                 break;
5801         default:
5802                 BUG();
5803         }
5804
5805         if (is_edp(intel_dp)) {
5806                 pps_lock(intel_dp);
5807                 intel_dp_init_panel_power_timestamps(intel_dp);
5808                 if (IS_VALLEYVIEW(dev))
5809                         vlv_initial_power_sequencer_setup(intel_dp);
5810                 else
5811                         intel_dp_init_panel_power_sequencer(dev, intel_dp);
5812                 pps_unlock(intel_dp);
5813         }
5814
5815         intel_dp_aux_init(intel_dp, intel_connector);
5816
5817         /* init MST on ports that can support it */
5818         if (HAS_DP_MST(dev) &&
5819             (port == PORT_B || port == PORT_C || port == PORT_D))
5820                 intel_dp_mst_encoder_init(intel_dig_port,
5821                                           intel_connector->base.base.id);
5822
5823         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5824                 drm_dp_aux_unregister(&intel_dp->aux);
5825                 if (is_edp(intel_dp)) {
5826                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5827                         /*
5828                          * vdd might still be enabled do to the delayed vdd off.
5829                          * Make sure vdd is actually turned off here.
5830                          */
5831                         pps_lock(intel_dp);
5832                         edp_panel_vdd_off_sync(intel_dp);
5833                         pps_unlock(intel_dp);
5834                 }
5835                 drm_connector_unregister(connector);
5836                 drm_connector_cleanup(connector);
5837                 return false;
5838         }
5839
5840         intel_dp_add_properties(intel_dp, connector);
5841
5842         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5843          * 0xd.  Failure to do so will result in spurious interrupts being
5844          * generated on the port when a cable is not attached.
5845          */
5846         if (IS_G4X(dev) && !IS_GM45(dev)) {
5847                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5848                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5849         }
5850
5851         i915_debugfs_connector_add(connector);
5852
5853         return true;
5854 }
5855
5856 void
5857 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5858 {
5859         struct drm_i915_private *dev_priv = dev->dev_private;
5860         struct intel_digital_port *intel_dig_port;
5861         struct intel_encoder *intel_encoder;
5862         struct drm_encoder *encoder;
5863         struct intel_connector *intel_connector;
5864
5865         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5866         if (!intel_dig_port)
5867                 return;
5868
5869         intel_connector = intel_connector_alloc();
5870         if (!intel_connector) {
5871                 kfree(intel_dig_port);
5872                 return;
5873         }
5874
5875         intel_encoder = &intel_dig_port->base;
5876         encoder = &intel_encoder->base;
5877
5878         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5879                          DRM_MODE_ENCODER_TMDS);
5880
5881         intel_encoder->compute_config = intel_dp_compute_config;
5882         intel_encoder->disable = intel_disable_dp;
5883         intel_encoder->get_hw_state = intel_dp_get_hw_state;
5884         intel_encoder->get_config = intel_dp_get_config;
5885         intel_encoder->suspend = intel_dp_encoder_suspend;
5886         if (IS_CHERRYVIEW(dev)) {
5887                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5888                 intel_encoder->pre_enable = chv_pre_enable_dp;
5889                 intel_encoder->enable = vlv_enable_dp;
5890                 intel_encoder->post_disable = chv_post_disable_dp;
5891         } else if (IS_VALLEYVIEW(dev)) {
5892                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5893                 intel_encoder->pre_enable = vlv_pre_enable_dp;
5894                 intel_encoder->enable = vlv_enable_dp;
5895                 intel_encoder->post_disable = vlv_post_disable_dp;
5896         } else {
5897                 intel_encoder->pre_enable = g4x_pre_enable_dp;
5898                 intel_encoder->enable = g4x_enable_dp;
5899                 if (INTEL_INFO(dev)->gen >= 5)
5900                         intel_encoder->post_disable = ilk_post_disable_dp;
5901         }
5902
5903         intel_dig_port->port = port;
5904         intel_dig_port->dp.output_reg = output_reg;
5905
5906         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5907         if (IS_CHERRYVIEW(dev)) {
5908                 if (port == PORT_D)
5909                         intel_encoder->crtc_mask = 1 << 2;
5910                 else
5911                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5912         } else {
5913                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5914         }
5915         intel_encoder->cloneable = 0;
5916         intel_encoder->hot_plug = intel_dp_hot_plug;
5917
5918         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5919         dev_priv->hpd_irq_port[port] = intel_dig_port;
5920
5921         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5922                 drm_encoder_cleanup(encoder);
5923                 kfree(intel_dig_port);
5924                 kfree(intel_connector);
5925         }
5926 }
5927
5928 void intel_dp_mst_suspend(struct drm_device *dev)
5929 {
5930         struct drm_i915_private *dev_priv = dev->dev_private;
5931         int i;
5932
5933         /* disable MST */
5934         for (i = 0; i < I915_MAX_PORTS; i++) {
5935                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5936                 if (!intel_dig_port)
5937                         continue;
5938
5939                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5940                         if (!intel_dig_port->dp.can_mst)
5941                                 continue;
5942                         if (intel_dig_port->dp.is_mst)
5943                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5944                 }
5945         }
5946 }
5947
5948 void intel_dp_mst_resume(struct drm_device *dev)
5949 {
5950         struct drm_i915_private *dev_priv = dev->dev_private;
5951         int i;
5952
5953         for (i = 0; i < I915_MAX_PORTS; i++) {
5954                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5955                 if (!intel_dig_port)
5956                         continue;
5957                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5958                         int ret;
5959
5960                         if (!intel_dig_port->dp.can_mst)
5961                                 continue;
5962
5963                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5964                         if (ret != 0) {
5965                                 intel_dp_check_mst_status(&intel_dig_port->dp);
5966                         }
5967                 }
5968         }
5969 }